diff --git a/components/esp_driver_uart/test_apps/.build-test-rules.yml b/components/esp_driver_uart/test_apps/.build-test-rules.yml index d75321f14c..d60f4758a9 100644 --- a/components/esp_driver_uart/test_apps/.build-test-rules.yml +++ b/components/esp_driver_uart/test_apps/.build-test-rules.yml @@ -3,9 +3,6 @@ components/esp_driver_uart/test_apps/rs485: disable: - if: SOC_UART_SUPPORTED != 1 - - if: IDF_TARGET in ["esp32h4"] - temporary: true - reason: not support yet # TODO: [ESP32H4] IDF-12398 disable_test: - if: IDF_TARGET not in ["esp32", "esp32h2"] temporary: true @@ -17,9 +14,6 @@ components/esp_driver_uart/test_apps/rs485: components/esp_driver_uart/test_apps/uart: disable: - if: SOC_UART_SUPPORTED != 1 - - if: IDF_TARGET in ["esp32h4"] - temporary: true - reason: not support yet # TODO: [ESP32H4] IDF-12398 depends_components: - esp_driver_uart - esp_driver_gpio diff --git a/components/esp_driver_uart/test_apps/rs485/README.md b/components/esp_driver_uart/test_apps/rs485/README.md index 15bfc62bf3..44f3780f1d 100644 --- a/components/esp_driver_uart/test_apps/rs485/README.md +++ b/components/esp_driver_uart/test_apps/rs485/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_uart/test_apps/uart/README.md b/components/esp_driver_uart/test_apps/uart/README.md index 15bfc62bf3..44f3780f1d 100644 --- a/components/esp_driver_uart/test_apps/uart/README.md +++ b/components/esp_driver_uart/test_apps/uart/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c b/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c index a1de927291..5955041037 100644 --- a/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c +++ b/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c @@ -39,6 +39,9 @@ #elif CONFIG_IDF_TARGET_ESP32C5 #define DEFAULT_UART1_TX_IO_NUM GPIO_NUM_2 #define DEFAULT_UART1_RX_IO_NUM GPIO_NUM_3 +#elif CONFIG_IDF_TARGET_ESP32H4 +#define DEFAULT_UART1_TX_IO_NUM GPIO_NUM_15 +#define DEFAULT_UART1_RX_IO_NUM GPIO_NUM_16 #endif #define MASTER_UART_NUM (1) diff --git a/components/esp_rom/esp32h4/include/esp32h4/rom/uart.h b/components/esp_rom/esp32h4/include/esp32h4/rom/uart.h index e73dfa2691..be9aaaac94 100644 --- a/components/esp_rom/esp32h4/include/esp32h4/rom/uart.h +++ b/components/esp_rom/esp32h4/include/esp32h4/rom/uart.h @@ -17,8 +17,6 @@ extern "C" { #endif -//TODO: [ESP32H4] IDF-12398 inherit from verification branch, need check - /** \defgroup uart_apis, uart configuration and communication related apis * @brief uart apis */ @@ -27,8 +25,9 @@ extern "C" { * @{ */ -#define RX_BUFF_SIZE 0x400 -#define TX_BUFF_SIZE 100 +/*It is found that when the buf is only 0x400, and the baud rate is set to 921600, the download is likely to fail */ +#define RX_BUFF_SIZE 0x800 +#define TX_BUFF_SIZE 100 //uart int enable register ctrl bits #define UART_RCV_INTEN BIT0 @@ -292,7 +291,7 @@ void uart_rx_intr_handler(void *para); * @return OK for successful. * FAIL for failed. */ -ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); +ETS_STATUS uart_rx_readbuff(RcvMsgBuff *pRxBuff, uint8_t *pRxByte); /** * @brief Get all chars from receive buffer. diff --git a/components/hal/esp32h4/include/hal/uart_ll.h b/components/hal/esp32h4/include/hal/uart_ll.h index fe98d536ba..b25bd85240 100644 --- a/components/hal/esp32h4/include/hal/uart_ll.h +++ b/components/hal/esp32h4/include/hal/uart_ll.h @@ -18,8 +18,6 @@ #include "soc/pcr_reg.h" #include "hal/assert.h" -//TODO: [ESP32H4] IDF-12398 inherited from verification branch, need check - #ifdef __cplusplus extern "C" { #endif @@ -110,15 +108,14 @@ FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw) */ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) { - HAL_ASSERT(uart_num < SOC_UART_HP_NUM); - uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG : - (uart_num == 1) ? PCR_UART1_CONF_REG : 0); - uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN : - (uart_num == 1) ? PCR_UART1_RST_EN : 0); - uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN : - (uart_num == 1) ? PCR_UART1_CLK_EN : 0); - return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 && - REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0; + switch (uart_num) { + case 0: + return PCR.uart0_conf.uart0_clk_en && !PCR.uart0_conf.uart0_rst_en; + case 1: + return PCR.uart1_conf.uart1_clk_en && !PCR.uart1_conf.uart1_rst_en; + default: + return false; + } } /** @@ -212,14 +209,14 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_ { uint32_t sel_value = 0; switch (source_clk) { - case UART_SCLK_PLL_F48M: - sel_value = 2; + case UART_SCLK_XTAL: + sel_value = 0; break; case UART_SCLK_RTC: sel_value = 1; break; - case UART_SCLK_XTAL: - sel_value = 0; + case UART_SCLK_PLL_F48M: + sel_value = 2; break; default: // Invalid HP_UART clock source @@ -240,14 +237,14 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source { switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { default: - case 2: - *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M; + case 0: + *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; break; case 1: *source_clk = (soc_module_clk_t)UART_SCLK_RTC; break; - case 0: - *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; + case 2: + *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M; break; } } @@ -405,6 +402,9 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_ */ FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) { + // Write to the FIFO should make sure only involve write operation, any read operation would cause data lost. + // Non-32-bit access would lead to a read-modify-write operation to the register, which is undesired. + // Therefore, use 32-bit access to avoid any potential problem. for (int i = 0; i < (int)wr_len; i++) { hw->fifo.val = buf[i]; } @@ -449,7 +449,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) { - return hw->status.rxfifo_cnt; + return HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt); } /** @@ -538,7 +538,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_ */ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) { - hw->conf1.rxfifo_full_thrhd = full_thrhd; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd); } /** @@ -552,7 +552,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full */ FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) { - hw->conf1.txfifo_empty_thrhd = empty_thrhd; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd); } /** @@ -616,7 +616,7 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont { //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { - hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs); hw->hwfc_conf_sync.rx_flow_en = 1; } else { hw->hwfc_conf_sync.rx_flow_en = 0; @@ -662,8 +662,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl if (sw_flow_ctrl_en) { hw->swfc_conf0_sync.xonoff_del = 1; hw->swfc_conf0_sync.sw_flow_con_en = 1; - hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; - hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, flow_ctrl->xon_thrd); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, flow_ctrl->xoff_thrd); HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); } else { @@ -779,12 +779,81 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_ case UART_WK_MODE_ACTIVE_THRESH: hw->sleep_conf2.wk_mode_sel = 0; break; + case UART_WK_MODE_FIFO_THRESH: + hw->sleep_conf2.wk_mode_sel = 1; + break; + case UART_WK_MODE_START_BIT: + hw->sleep_conf2.wk_mode_sel = 2; + break; + case UART_WK_MODE_CHAR_SEQ: + hw->sleep_conf2.wk_mode_sel = 3; + break; default: abort(); break; } } +/** + * @brief Set the UART specific character sequence wakeup mode mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask UART wakeup char seq mask to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_mask(uart_dev_t *hw, uint32_t mask) +{ + hw->sleep_conf2.wk_char_mask = mask; +} + +/** + * @brief Set the UART specific character sequence wakeup phrase size. + * + * @param hw Beginning address of the peripheral registers. + * @param char_num UART wakeup char seq phrase size to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint32_t char_num) +{ + hw->sleep_conf2.wk_char_num = char_num; +} + +/** + * @brief Set the UART specific character sequence wakeup mode char. + * + * @param hw Beginning address of the peripheral registers. + * @param char_position UART wakeup char seq char position to be set. + * @param value UART wakeup char seq char value to be set. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value) +{ + switch (char_position) { + case 0: + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value); + break; + case 1: + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value); + break; + case 2: + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value); + break; + case 3: + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value); + break; + case 4: + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value); + break; + default: + abort(); + break; + } + +} + /** * @brief Enable/disable the UART pad clock in sleep_state * @@ -976,7 +1045,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length */ FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) { - return (((hw->status.txfifo_cnt) == 0) && (hw->fsm_status.st_utx_out == 0)); + return ((HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) == 0) && (hw->fsm_status.st_utx_out == 0)); } /** diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index cb35db3a83..fe024eea21 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1539,10 +1539,6 @@ config SOC_UART_BITRATE_MAX int default 5000000 -config SOC_UART_SUPPORT_PLL_F80M_CLK - bool - default y - config SOC_UART_SUPPORT_RTC_CLK bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 92731060be..7a1b551954 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -600,7 +600,6 @@ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 399e48e196..9a6cc61654 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -1307,10 +1307,6 @@ config SOC_UART_BITRATE_MAX int default 5000000 -config SOC_UART_SUPPORT_PLL_F80M_CLK - bool - default y - config SOC_UART_SUPPORT_RTC_CLK bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 38218f04f4..b8766b8d63 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -513,7 +513,6 @@ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 4697c679ae..725f96b6e0 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -1039,10 +1039,6 @@ config SOC_UART_BITRATE_MAX int default 5000000 -config SOC_UART_SUPPORT_PLL_F80M_CLK - bool - default y - config SOC_UART_SUPPORT_RTC_CLK bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 8f24373341..a04929dfe7 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -427,7 +427,6 @@ #define SOC_UART_HP_NUM (3) #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index ab2572594a..b80a9c9d0c 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -763,18 +763,10 @@ config SOC_UART_FIFO_LEN int default 128 -config SOC_LP_UART_FIFO_LEN - int - default 16 - config SOC_UART_BITRATE_MAX int default 5000000 -config SOC_UART_SUPPORT_PLL_F80M_CLK - bool - default y - config SOC_UART_SUPPORT_RTC_CLK bool default y @@ -791,10 +783,30 @@ config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND bool default y +config SOC_UART_SUPPORT_SLEEP_RETENTION + bool + default y + +config SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN + int + default 5 + config SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE bool default y +config SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE + bool + default y + +config SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE + bool + default y + +config SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE + bool + default y + config SOC_SPIRAM_XIP_SUPPORTED bool default y diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h index c520614e11..41810eb430 100644 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h @@ -225,6 +225,11 @@ typedef enum { ///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// +/** + * @brief Array initializer for all supported clock sources of UART + */ +#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + /** * @brief Type of UART clock source, reserved for the legacy UART driver */ diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index fe26ac767f..383a99c7e4 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -34,7 +34,7 @@ // #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12368 IDF-12370 // #define SOC_ANA_CMPR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12395 big change!! // #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12401 -#define SOC_UART_SUPPORTED 1 // TODO: [ESP32H4] IDF-12398 +#define SOC_UART_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 #define SOC_AHB_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 @@ -495,9 +495,7 @@ #define SOC_UART_NUM (2) #define SOC_UART_HP_NUM (2) #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ -#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ @@ -505,7 +503,13 @@ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) +#define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */ + +#define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5 #define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1) +#define SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE (1) +#define SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE (1) +#define SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE (1) /*-------------------------- SPIRAM CAPS -------------------------------------*/ #define SOC_SPIRAM_XIP_SUPPORTED 1 diff --git a/components/soc/esp32h4/include/soc/uart_pins.h b/components/soc/esp32h4/include/soc/uart_pins.h index 874b0a4c84..83ecbe9278 100644 --- a/components/soc/esp32h4/include/soc/uart_pins.h +++ b/components/soc/esp32h4/include/soc/uart_pins.h @@ -23,11 +23,6 @@ #define U1DTR_GPIO_NUM (-1) #define U1DSR_GPIO_NUM (-1) -#define LP_U0RXD_GPIO_NUM 4 -#define LP_U0TXD_GPIO_NUM 5 -#define LP_U0RTS_GPIO_NUM 2 -#define LP_U0CTS_GPIO_NUM 3 - /* The following defines are necessary for reconfiguring the UART * to use IOMUX, at runtime. */ #define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD) @@ -45,8 +40,3 @@ #define U1CTS_MUX_FUNC (-1) #define U1DTR_MUX_FUNC (-1) #define U1DSR_MUX_FUNC (-1) - -#define LP_U0TXD_MUX_FUNC (1) -#define LP_U0RXD_MUX_FUNC (1) -#define LP_U0RTS_MUX_FUNC (1) -#define LP_U0CTS_MUX_FUNC (1) diff --git a/components/soc/esp32h4/uart_periph.c b/components/soc/esp32h4/uart_periph.c index 5ffec21944..aae5372e17 100644 --- a/components/soc/esp32h4/uart_periph.c +++ b/components/soc/esp32h4/uart_periph.c @@ -107,3 +107,54 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { .irq = ETS_UART1_INTR_SOURCE, } }; + +/** + * UART registers to be saved during sleep retention + * + * Reset TXFIFO and RXFIFO + * UART registers require set the reg_update bit to make the configuration take effect + * + * UART_INT_ENA_REG, UART_CLKDIV_SYNC_REG, UART_RX_FILT_REG, UART_CONF0_SYNC_REG, UART_CONF1_REG, + * UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG, + * UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG, + * UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG, + * UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_CLK_CONF_REG, UART_ID_REG + */ +#define UART_RETENTION_ADDR_MAP_REGS_CNT 22 +#define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i) +static const uint32_t uart_regs_map[4] = {0x807fff6d, 0x10, 0x0, 0x0}; +#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \ + [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \ + UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \ + UART_RETENTION_ADDR_MAP_REGS_CNT, 0, 0, \ + uart_regs_map[0], uart_regs_map[1], \ + uart_regs_map[2], uart_regs_map[3] \ + ), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_UART_LINK(0x01), \ + UART_REG_UPDATE_REG(uart_num), UART_REG_UPDATE, \ + UART_REG_UPDATE_M, 1, 0 \ + ), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [2] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_UART_LINK(0x02), \ + UART_REG_UPDATE_REG(uart_num), 0x0, \ + UART_REG_UPDATE_M, 1, 0 \ + ), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +} + +static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0); +static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1); + +const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_UART0, + .regdma_entry_array = uart0_regdma_entries, + .array_size = ARRAY_SIZE(uart0_regdma_entries), + }, + [1] = { + .module = SLEEP_RETENTION_MODULE_UART1, + .regdma_entry_array = uart1_regdma_entries, + .array_size = ARRAY_SIZE(uart1_regdma_entries), + }, +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 0d1ad891d1..47f4d8d1e2 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1879,10 +1879,6 @@ config SOC_UART_BITRATE_MAX int default 5000000 -config SOC_UART_SUPPORT_PLL_F80M_CLK - bool - default y - config SOC_UART_SUPPORT_RTC_CLK bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index d789b1f1be..af0ef9a4dc 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -696,7 +696,6 @@ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ diff --git a/docs/docs_not_updated/esp32h4.txt b/docs/docs_not_updated/esp32h4.txt index e1884f6e04..47566d3f39 100644 --- a/docs/docs_not_updated/esp32h4.txt +++ b/docs/docs_not_updated/esp32h4.txt @@ -151,7 +151,6 @@ api-reference/peripherals/sdspi_share.rst api-reference/peripherals/ana_cmpr.rst api-reference/peripherals/adc_continuous.rst api-reference/peripherals/hmac.rst -api-reference/peripherals/uart.rst api-reference/peripherals/sdspi_host.rst api-reference/peripherals/vad.rst api-reference/peripherals/i2s.rst diff --git a/examples/peripherals/uart/nmea0183_parser/main/Kconfig.projbuild b/examples/peripherals/uart/nmea0183_parser/main/Kconfig.projbuild index 0e53a92063..080d3bcee4 100644 --- a/examples/peripherals/uart/nmea0183_parser/main/Kconfig.projbuild +++ b/examples/peripherals/uart/nmea0183_parser/main/Kconfig.projbuild @@ -5,7 +5,8 @@ menu "Example Configuration" config NMEA_PARSER_UART_RXD int "UART RXD pin number" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 5 + default 5 if !IDF_TARGET_ESP32H4 + default 15 if IDF_TARGET_ESP32H4 help GPIO number for UART RX pin. See UART documentation for more information about available pin numbers for UART. diff --git a/examples/peripherals/uart/uart_async_rxtxtasks/main/Kconfig.projbuild b/examples/peripherals/uart/uart_async_rxtxtasks/main/Kconfig.projbuild index 3068b7abea..bc88bef752 100644 --- a/examples/peripherals/uart/uart_async_rxtxtasks/main/Kconfig.projbuild +++ b/examples/peripherals/uart/uart_async_rxtxtasks/main/Kconfig.projbuild @@ -12,7 +12,8 @@ menu "Example Configuration" config EXAMPLE_UART_RXD int "UART RXD pin number" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 5 + default 5 if !IDF_TARGET_ESP32H4 + default 15 if IDF_TARGET_ESP32H4 help GPIO number for UART RX pin. See UART documentation for more information about available pin numbers for UART. @@ -20,7 +21,8 @@ menu "Example Configuration" config EXAMPLE_UART_TXD int "UART TXD pin number" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 4 + default 4 if !IDF_TARGET_ESP32H4 + default 16 if IDF_TARGET_ESP32H4 help GPIO number for UART TX pin. See UART documentation for more information about available pin numbers for UART. diff --git a/examples/peripherals/uart/uart_echo/main/Kconfig.projbuild b/examples/peripherals/uart/uart_echo/main/Kconfig.projbuild index 29b325386f..50500f07fe 100644 --- a/examples/peripherals/uart/uart_echo/main/Kconfig.projbuild +++ b/examples/peripherals/uart/uart_echo/main/Kconfig.projbuild @@ -22,7 +22,8 @@ menu "Echo Example Configuration" config EXAMPLE_UART_RXD int "UART RXD pin number" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 5 + default 5 if !IDF_TARGET_ESP32H4 + default 15 if IDF_TARGET_ESP32H4 help GPIO number for UART RX pin. See UART documentation for more information about available pin numbers for UART. @@ -30,7 +31,8 @@ menu "Echo Example Configuration" config EXAMPLE_UART_TXD int "UART TXD pin number" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 4 + default 4 if !IDF_TARGET_ESP32H4 + default 16 if IDF_TARGET_ESP32H4 help GPIO number for UART TX pin. See UART documentation for more information about available pin numbers for UART. diff --git a/examples/peripherals/uart/uart_repl/main/uart_repl_example_main.c b/examples/peripherals/uart/uart_repl/main/uart_repl_example_main.c index 820bf27bcc..52e3e0e21c 100644 --- a/examples/peripherals/uart/uart_repl/main/uart_repl_example_main.c +++ b/examples/peripherals/uart/uart_repl/main/uart_repl_example_main.c @@ -23,8 +23,14 @@ #define CONSOLE_UART_CHANNEL (1 - DEFAULT_UART_CHANNEL) #define DEFAULT_UART_RX_PIN (3) #define DEFAULT_UART_TX_PIN (2) + +#if CONFIG_IDF_TARGET_ESP32H4 +#define CONSOLE_UART_RX_PIN (15) +#define CONSOLE_UART_TX_PIN (16) +#else #define CONSOLE_UART_RX_PIN (4) #define CONSOLE_UART_TX_PIN (5) +#endif #define UARTS_BAUD_RATE (115200) #define TASK_STACK_SIZE (2048)