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feat(gdma): set burst size and return alignment constraint

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burst size can affect the buffer alignment
This commit is contained in:
morris
2024-04-25 18:16:29 +08:00
parent 19c784efef
commit dc6989796a
33 changed files with 522 additions and 356 deletions
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20
components/hal/esp32c5/beta3/include/hal/gdma_beta3_ll.h
View File

@@ -13,7 +13,6 @@
#include "soc/gdma_struct.h"
#include "soc/gdma_reg.h"
#include "soc/soc_etm_source.h"
#include "soc/pcr_struct.h"
#include "soc/retention_periph_defs.h"
#ifdef __cplusplus
@@ -102,25 +101,6 @@ extern "C" {
///////////////////////////////////// Common /////////////////////////////////////////
/**
* @brief Enable the bus clock for the DMA module
*/
static inline void gdma_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.gdma_conf.gdma_clk_en = enable;
}
/**
* @brief Reset the DMA module
*/
static inline void gdma_ll_reset_register(int group_id)
{
(void)group_id;
PCR.gdma_conf.gdma_rst_en = 1;
PCR.gdma_conf.gdma_rst_en = 0;
}
/**
* @brief Force enable register clock
*/

30
components/hal/esp32c5/include/hal/gdma_ll.h
View File

@@ -6,8 +6,38 @@
#pragma once
#include "sdkconfig.h"
#include "soc/pcr_struct.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "hal/gdma_beta3_ll.h"
#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT 1
#else
#include "hal/ahb_dma_ll.h"
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for the DMA module
*/
static inline void gdma_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.gdma_conf.gdma_clk_en = enable;
}
/**
* @brief Reset the DMA module
*/
static inline void gdma_ll_reset_register(int group_id)
{
(void)group_id;
PCR.gdma_conf.gdma_rst_en = 1;
PCR.gdma_conf.gdma_rst_en = 0;
}
#ifdef __cplusplus
}
#endif

79
components/hal/esp32c5/mp/include/hal/ahb_dma_ll.h
View File

@@ -10,10 +10,10 @@
#include <stdbool.h>
#include "soc/soc_caps.h"
#include "hal/gdma_types.h"
#include "hal/assert.h"
#include "soc/ahb_dma_struct.h"
#include "soc/ahb_dma_reg.h"
#include "soc/soc_etm_source.h"
#include "soc/pcr_struct.h"
#include "soc/retention_periph_defs.h"
#ifdef __cplusplus
@@ -99,25 +99,6 @@ extern "C" {
///////////////////////////////////// Common /////////////////////////////////////////
/**
* @brief Enable the bus clock for the DMA module
*/
static inline void gdma_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.gdma_conf.gdma_clk_en = enable;
}
/**
* @brief Reset the DMA module
*/
static inline void gdma_ll_reset_register(int group_id)
{
(void)group_id;
PCR.gdma_conf.gdma_rst_en = 1;
PCR.gdma_conf.gdma_rst_en = 0;
}
/**
* @brief Force enable register clock
*/
@@ -212,11 +193,10 @@ static inline void ahb_dma_ll_rx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t
}
/**
* @brief Enable DMA RX channel burst reading data, disabled by default
* @brief Enable DMA RX channel burst reading data, always enabled
*/
static inline void ahb_dma_ll_rx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
{
// dev->channel[channel].in.in_conf0.in_data_burst_mode_sel_chn = enable; // single/incr4/incr8/incr16
}
/**
@@ -227,6 +207,32 @@ static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uin
dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable;
}
/**
* @brief Set RX channel burst size
*/
static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz)
{
uint8_t burst_mode = 0;
switch (sz) {
case 4:
burst_mode = 0; // single
break;
case 16:
burst_mode = 1; // incr4
break;
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;
}
dev->channel[channel].in.in_conf0.in_data_burst_mode_sel_chn = burst_mode;
}
/**
* @brief Reset DMA RX channel FSM and FIFO pointer
*/
@@ -440,11 +446,10 @@ static inline void ahb_dma_ll_tx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t
}
/**
* @brief Enable DMA TX channel burst sending data, disabled by default
* @brief Enable DMA TX channel burst sending data, always enabled
*/
static inline void ahb_dma_ll_tx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
{
// dev->channel[channel].out.out_conf0.out_data_burst_mode_sel_chn = enable;
}
/**
@@ -455,6 +460,32 @@ static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uin
dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable;
}
/**
* @brief Set TX channel burst size
*/
static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz)
{
uint8_t burst_mode = 0;
switch (sz) {
case 4:
burst_mode = 0; // single
break;
case 16:
burst_mode = 1; // incr4
break;
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;
}
dev->channel[channel].out.out_conf0.out_data_burst_mode_sel_chn = burst_mode;
}
/**
* @brief Set TX channel EOF mode
*/