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feat(gdma): set burst size and return alignment constraint

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burst size can affect the buffer alignment
This commit is contained in:
morris
2024-04-25 18:16:29 +08:00
parent 19c784efef
commit dc6989796a
33 changed files with 522 additions and 356 deletions
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32
components/hal/esp32p4/include/hal/axi_dma_ll.h
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@@ -125,7 +125,7 @@ static inline void axi_dma_ll_rx_enable_owner_check(axi_dma_dev_t *dev, uint32_t
}
/**
* @brief Enable DMA RX channel burst reading data, disabled by default
* @brief Enable DMA RX channel burst reading data, always enabled
*/
static inline void axi_dma_ll_rx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
@@ -139,6 +139,16 @@ static inline void axi_dma_ll_rx_enable_descriptor_burst(axi_dma_dev_t *dev, uin
dev->in[channel].conf.in_conf0.indscr_burst_en_chn = enable;
}
/**
* @brief Set the RX channel burst size
*/
static inline void axi_dma_ll_rx_set_burst_size(axi_dma_dev_t *dev, uint32_t channel, uint32_t sz)
{
HAL_ASSERT(sz >= 8 && sz <= 128);
int ctz = __builtin_ctz(sz);
dev->in[channel].conf.in_conf0.in_burst_size_sel_chn = ctz - 3;
}
/**
* @brief Reset DMA RX channel FSM and FIFO pointer
*/
@@ -274,11 +284,11 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
}
/**
* @brief Whether to enable the mean access ecc or aes domain
* @brief Whether to enable access to ecc or aes memory
*/
static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in[channel].conf.in_conf0.in_ecc_aec_en_chn = enable;
dev->in[channel].conf.in_conf0.in_ecc_aes_en_chn = enable;
}
///////////////////////////////////// TX /////////////////////////////////////////
@@ -333,7 +343,7 @@ static inline void axi_dma_ll_tx_enable_owner_check(axi_dma_dev_t *dev, uint32_t
}
/**
* @brief Enable DMA TX channel burst sending data, disabled by default
* @brief Enable DMA TX channel burst sending data, always enabled
*/
static inline void axi_dma_ll_tx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
@@ -347,6 +357,16 @@ static inline void axi_dma_ll_tx_enable_descriptor_burst(axi_dma_dev_t *dev, uin
dev->out[channel].conf.out_conf0.outdscr_burst_en_chn = enable;
}
/**
* @brief Set the TX channel burst size
*/
static inline void axi_dma_ll_tx_set_burst_size(axi_dma_dev_t *dev, uint32_t channel, uint32_t sz)
{
HAL_ASSERT(sz >= 8 && sz <= 128);
int ctz = __builtin_ctz(sz);
dev->out[channel].conf.out_conf0.out_burst_size_sel_chn = ctz - 3;
}
/**
* @brief Set TX channel EOF mode
*/
@@ -480,11 +500,11 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
}
/**
* @brief Whether to enable the mean access ecc or aes domain
* @brief Whether to enable access to ecc or aes memory
*/
static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
{
dev->out[channel].conf.out_conf0.out_ecc_aec_en_chn = enable;
dev->out[channel].conf.out_conf0.out_ecc_aes_en_chn = enable;
}
///////////////////////////////////// CRC-TX /////////////////////////////////////////