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feat(uart): support uart module sleep retention on c6/h2/p4

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This commit is contained in:
Song Ruo Jing
2024-05-15 19:07:58 +08:00
parent 13e5b6f335
commit dca7c286d0
66 changed files with 707 additions and 277 deletions
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6
components/soc/esp32c5/beta3/gdma_periph.c
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@@ -49,7 +49,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
g0p0_regs_map0[0], g0p0_regs_map0[1], \
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
g0p0_regs_map1[0], g0p0_regs_map1[1], \
@@ -76,7 +76,7 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
g0p1_regs_map0[0], g0p1_regs_map0[1], \
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
g0p1_regs_map1[0], g0p1_regs_map1[1], \
@@ -103,7 +103,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
g0p2_regs_map0[0], g0p2_regs_map0[1], \
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
g0p2_regs_map1[0], g0p2_regs_map1[1], \

4
components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
View File

@@ -691,6 +691,10 @@ config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_UART_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_COEX_HW_PTI
bool
default y

2
components/soc/esp32c5/beta3/include/soc/soc_caps.h
View File

@@ -498,6 +498,8 @@
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
#define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)

10
components/soc/esp32c5/beta3/include/soc/system_periph_retention.h
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@@ -48,16 +48,6 @@ extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LI
#define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN 1
extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN];
/**
* @brief Provide access to uart configuration registers retention
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
*/
#define UART_RETENTION_LINK_LEN 3
extern const regdma_entries_config_t uart_regs_retention[UART_RETENTION_LINK_LEN];
/**
* @brief Provide access to timer group configuration registers retention
* context definition.

10
components/soc/esp32c5/beta3/system_retention_periph.c
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@@ -44,16 +44,6 @@ const regdma_entries_config_t tee_apm_highpri_regs_retention[] = {
};
_Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions");
/* UART0 Registers Context */
#define N_REGS_UART() (((UART_ID_REG(0) - UART_INT_RAW_REG(0)) / 4) + 1)
const regdma_entries_config_t uart_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_UART_LINK(0x00), UART_INT_RAW_REG(0), UART_INT_RAW_REG(0), N_REGS_UART(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* uart */
/* Note: uart register should set update reg to make the configuration take effect */
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_UART_LINK(0x01), UART_REG_UPDATE_REG(0), UART_REG_UPDATE, UART_REG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_UART_LINK(0x02), UART_REG_UPDATE_REG(0), 0x0, UART_REG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }
};
_Static_assert(ARRAY_SIZE(uart_regs_retention) == UART_RETENTION_LINK_LEN, "Inconsistent UART retention link length definitions");
/* IO MUX Registers Context */
#define N_REGS_IOMUX_0() (((IO_MUX_GPIO26_REG - REG_IO_MUX_BASE) / 4) + 1)
#define N_REGS_IOMUX_1() (((GPIO_FUNC30_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)

43
components/soc/esp32c5/beta3/uart_periph.c
View File

@@ -5,6 +5,7 @@
*/
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
@@ -41,7 +42,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
}
},
.irq = ETS_UART0_INTR_SOURCE,
.module = PERIPH_UART0_MODULE,
},
{ // HP UART1
@@ -75,7 +75,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_UART1_INTR_SOURCE,
.module = PERIPH_UART1_MODULE,
},
{ // LP UART0
@@ -109,6 +108,44 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
.module = PERIPH_LP_UART0_MODULE,
},
};
/**
* UART registers to be saved during sleep retention
*
* Reset TXFIFO and RXFIFO
* UART registers require set the reg_update bit to make the configuration take effect
*/
#define N_REGS_UART(uart_num) (((UART_ID_REG(uart_num) - UART_INT_RAW_REG(uart_num)) / 4) + 1)
#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
[0] = {.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_UART_LINK(0x00), \
UART_INT_RAW_REG(uart_num), UART_INT_RAW_REG(uart_num), \
N_REGS_UART(uart_num), 0, 0 \
), \
.owner = ENTRY(0) | ENTRY(2) }, \
[1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_UART_LINK(0x01), \
UART_REG_UPDATE_REG(uart_num), UART_REG_UPDATE, \
UART_REG_UPDATE_M, 1, 0 \
), \
.owner = ENTRY(0) | ENTRY(2) }, \
[2] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_UART_LINK(0x02), \
UART_REG_UPDATE_REG(uart_num), 0x0, \
UART_REG_UPDATE_M, 1, 0 \
), \
.owner = ENTRY(0) | ENTRY(2) }, \
}
static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0);
static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1);
const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
[0] = {
.regdma_entry_array = uart0_regdma_entries,
.array_size = ARRAY_SIZE(uart0_regdma_entries),
},
[1] = {
.regdma_entry_array = uart1_regdma_entries,
.array_size = ARRAY_SIZE(uart1_regdma_entries),
},
};

6
components/soc/esp32c5/mp/gdma_periph.c
View File

@@ -56,7 +56,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
g0p0_regs_map0[0], g0p0_regs_map0[1], \
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) }, \
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x01), \
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
g0p0_regs_map1[0], g0p0_regs_map1[1], \
@@ -90,7 +90,7 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
g0p1_regs_map0[0], g0p1_regs_map0[1], \
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x01), \
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
g0p1_regs_map1[0], g0p1_regs_map1[1], \
@@ -125,7 +125,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
g0p2_regs_map0[0], g0p2_regs_map0[1], \
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x01), \
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
g0p2_regs_map1[0], g0p2_regs_map1[1], \

3
components/soc/esp32c5/mp/uart_periph.c
View File

@@ -41,7 +41,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
}
},
.irq = ETS_UART0_INTR_SOURCE,
.module = PERIPH_UART0_MODULE,
},
{ // HP UART1
@@ -75,7 +74,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_UART1_INTR_SOURCE,
.module = PERIPH_UART1_MODULE,
},
{ // LP UART0
@@ -109,6 +107,5 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
.module = PERIPH_LP_UART0_MODULE,
},
};