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feat(uart): support uart module sleep retention on c6/h2/p4

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This commit is contained in:
Song Ruo Jing
2024-05-15 19:07:58 +08:00
parent 13e5b6f335
commit dca7c286d0
66 changed files with 707 additions and 277 deletions
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4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -1503,6 +1503,10 @@ config SOC_UART_HAS_LP_UART
bool
default y
config SOC_UART_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y

20
components/soc/esp32p4/include/soc/retention_periph_defs.h
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@@ -25,6 +25,12 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_TG1_WDT = 4,
SLEEP_RETENTION_MODULE_TG0_TIMER = 5,
SLEEP_RETENTION_MODULE_TG1_TIMER = 6,
/* MISC Peripherals */
SLEEP_RETENTION_MODULE_UART0 = 7,
SLEEP_RETENTION_MODULE_UART1 = 8,
SLEEP_RETENTION_MODULE_UART2 = 9,
SLEEP_RETENTION_MODULE_UART3 = 10,
SLEEP_RETENTION_MODULE_UART4 = 11,
SLEEP_RETENTION_MODULE_MAX = 31
} periph_retention_module_t;
@@ -40,6 +46,12 @@ typedef enum periph_retention_module_bitmap {
SLEEP_RETENTION_MODULE_BM_TG1_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
/* MISC Peripherals */
SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0),
SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1),
SLEEP_RETENTION_MODULE_BM_UART2 = BIT(SLEEP_RETENTION_MODULE_UART2),
SLEEP_RETENTION_MODULE_BM_UART3 = BIT(SLEEP_RETENTION_MODULE_UART3),
SLEEP_RETENTION_MODULE_BM_UART4 = BIT(SLEEP_RETENTION_MODULE_UART4),
SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
} periph_retention_module_bitmap_t;
@@ -49,7 +61,13 @@ typedef enum periph_retention_module_bitmap {
| SLEEP_RETENTION_MODULE_BM_TG0_WDT \
| SLEEP_RETENTION_MODULE_BM_TG1_WDT \
| SLEEP_RETENTION_MODULE_BM_TG0_TIMER \
| SLEEP_RETENTION_MODULE_BM_TG1_TIMER)
| SLEEP_RETENTION_MODULE_BM_TG1_TIMER \
| SLEEP_RETENTION_MODULE_BM_UART0 \
| SLEEP_RETENTION_MODULE_BM_UART1 \
| SLEEP_RETENTION_MODULE_BM_UART2 \
| SLEEP_RETENTION_MODULE_BM_UART3 \
| SLEEP_RETENTION_MODULE_BM_UART4 \
)
#ifdef __cplusplus
}

1
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -591,6 +591,7 @@
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_HAS_LP_UART (1) /*!< Support LP UART */
#define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)

10
components/soc/esp32p4/include/soc/system_periph_retention.h
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@@ -45,16 +45,6 @@ extern const regdma_entries_config_t l2_cache_regs_retention[L2_CACHE_RETENTION_
#define HP_SYSTEM_RETENTION_LINK_LEN 1
extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN];
/**
* @brief Provide access to uart configuration registers retention
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
*/
#define UART_RETENTION_LINK_LEN 3
extern const regdma_entries_config_t uart_regs_retention[UART_RETENTION_LINK_LEN];
/**
* @brief Provide access to timer group configuration registers retention
* context definition.

10
components/soc/esp32p4/system_retention_periph.c
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@@ -42,16 +42,6 @@ const regdma_entries_config_t hp_system_regs_retention[] = {
};
_Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions");
/* UART0 Registers Context */
#define N_REGS_UART() (((UART_CLK_CONF_REG(0) - REG_UART_BASE(0)) / 4) + 1)
const regdma_entries_config_t uart_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_UART_LINK(0x00), REG_UART_BASE(0), REG_UART_BASE(0), N_REGS_UART(), 0, 0), .owner = ENTRY(0) }, /* uart */
/* Note: uart register should set update reg to make the configuration take effect */
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_UART_LINK(0x01), UART_REG_UPDATE_REG(0), UART_REG_UPDATE, UART_REG_UPDATE_M, 1, 0), .owner = ENTRY(0) },
[2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_UART_LINK(0x02), UART_REG_UPDATE_REG(0), 0x0, UART_REG_UPDATE_M, 1, 0), .owner = ENTRY(0) }
};
_Static_assert(ARRAY_SIZE(uart_regs_retention) == UART_RETENTION_LINK_LEN, "Inconsistent UART retention link length definitions");
/* IO MUX Registers Context */
#define N_REGS_IOMUX_0() (((IO_MUX_GPIO54_REG - REG_IO_MUX_BASE) / 4) + 1)
#define N_REGS_IOMUX_1() (((GPIO_ZERO_DET1_FILTER_CNT_REG - DR_REG_GPIO_BASE) / 4) + 1)

73
components/soc/esp32p4/uart_periph.c
View File

@@ -1,11 +1,12 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "soc/lp_gpio_sig_map.h"
#include "soc/uart_reg.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
@@ -42,7 +43,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
}
},
.irq = ETS_UART0_INTR_SOURCE,
.module = PERIPH_UART0_MODULE,
},
{ // HP UART1
@@ -76,7 +76,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_UART1_INTR_SOURCE,
.module = PERIPH_UART1_MODULE,
},
{ // HP UART2
@@ -110,7 +109,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_UART2_INTR_SOURCE,
.module = PERIPH_UART2_MODULE,
},
{ // HP UART3
@@ -144,7 +142,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_UART3_INTR_SOURCE,
.module = PERIPH_UART3_MODULE,
},
{ // HP UART4
@@ -178,7 +175,6 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_UART4_INTR_SOURCE,
.module = PERIPH_UART4_MODULE,
},
{ // LP UART0
.pins = {
@@ -211,6 +207,69 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
.module = PERIPH_LP_UART0_MODULE,
},
};
/**
* UART registers to be saved during sleep retention
*
* Reset TXFIFO and RXFIFO
* UART registers require set the reg_update bit to make the configuration take effect
*
* UART_INT_ENA_REG, UART_CLKDIV_SYNC_REG, UART_RX_FILT_REG, UART_CONF0_SYNC_REG, UART_CONF1_REG,
* UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG,
* UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG,
* UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG,
* UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_ID_REG
*/
#define UART_RETENTION_ADDR_MAP_REGS_CNT 21
#define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i)
static const uint32_t uart_regs_map[4] = {0x7fff6d, 0x10, 0x0, 0x0};
#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
[0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \
UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \
UART_RETENTION_ADDR_MAP_REGS_CNT, 0, 0, \
uart_regs_map[0], uart_regs_map[1], \
uart_regs_map[2], uart_regs_map[3] \
), \
.owner = ENTRY(0) }, \
[1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_UART_LINK(0x01), \
UART_REG_UPDATE_REG(uart_num), UART_REG_UPDATE, \
UART_REG_UPDATE_M, 1, 0 \
), \
.owner = ENTRY(0) }, \
[2] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_UART_LINK(0x02), \
UART_REG_UPDATE_REG(uart_num), 0x0, \
UART_REG_UPDATE_M, 1, 0 \
), \
.owner = ENTRY(0) }, \
}
static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0);
static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1);
static const regdma_entries_config_t uart2_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(2);
static const regdma_entries_config_t uart3_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(3);
static const regdma_entries_config_t uart4_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(4);
const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
[0] = {
.regdma_entry_array = uart0_regdma_entries,
.array_size = ARRAY_SIZE(uart0_regdma_entries),
},
[1] = {
.regdma_entry_array = uart1_regdma_entries,
.array_size = ARRAY_SIZE(uart1_regdma_entries),
},
[2] = {
.regdma_entry_array = uart2_regdma_entries,
.array_size = ARRAY_SIZE(uart2_regdma_entries),
},
[3] = {
.regdma_entry_array = uart3_regdma_entries,
.array_size = ARRAY_SIZE(uart3_regdma_entries),
},
[4] = {
.regdma_entry_array = uart4_regdma_entries,
.array_size = ARRAY_SIZE(uart4_regdma_entries),
},
};