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feat(uart): support uart module sleep retention on c6/h2/p4

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This commit is contained in:
Song Ruo Jing
2024-05-15 19:07:58 +08:00
parent 13e5b6f335
commit dca7c286d0
66 changed files with 707 additions and 277 deletions
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4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -1503,6 +1503,10 @@ config SOC_UART_HAS_LP_UART
bool
default y
config SOC_UART_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y

20
components/soc/esp32p4/include/soc/retention_periph_defs.h
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@@ -25,6 +25,12 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_TG1_WDT = 4,
SLEEP_RETENTION_MODULE_TG0_TIMER = 5,
SLEEP_RETENTION_MODULE_TG1_TIMER = 6,
/* MISC Peripherals */
SLEEP_RETENTION_MODULE_UART0 = 7,
SLEEP_RETENTION_MODULE_UART1 = 8,
SLEEP_RETENTION_MODULE_UART2 = 9,
SLEEP_RETENTION_MODULE_UART3 = 10,
SLEEP_RETENTION_MODULE_UART4 = 11,
SLEEP_RETENTION_MODULE_MAX = 31
} periph_retention_module_t;
@@ -40,6 +46,12 @@ typedef enum periph_retention_module_bitmap {
SLEEP_RETENTION_MODULE_BM_TG1_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
/* MISC Peripherals */
SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0),
SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1),
SLEEP_RETENTION_MODULE_BM_UART2 = BIT(SLEEP_RETENTION_MODULE_UART2),
SLEEP_RETENTION_MODULE_BM_UART3 = BIT(SLEEP_RETENTION_MODULE_UART3),
SLEEP_RETENTION_MODULE_BM_UART4 = BIT(SLEEP_RETENTION_MODULE_UART4),
SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
} periph_retention_module_bitmap_t;
@@ -49,7 +61,13 @@ typedef enum periph_retention_module_bitmap {
| SLEEP_RETENTION_MODULE_BM_TG0_WDT \
| SLEEP_RETENTION_MODULE_BM_TG1_WDT \
| SLEEP_RETENTION_MODULE_BM_TG0_TIMER \
| SLEEP_RETENTION_MODULE_BM_TG1_TIMER)
| SLEEP_RETENTION_MODULE_BM_TG1_TIMER \
| SLEEP_RETENTION_MODULE_BM_UART0 \
| SLEEP_RETENTION_MODULE_BM_UART1 \
| SLEEP_RETENTION_MODULE_BM_UART2 \
| SLEEP_RETENTION_MODULE_BM_UART3 \
| SLEEP_RETENTION_MODULE_BM_UART4 \
)
#ifdef __cplusplus
}

1
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -591,6 +591,7 @@
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_HAS_LP_UART (1) /*!< Support LP UART */
#define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)

10
components/soc/esp32p4/include/soc/system_periph_retention.h
View File

@@ -45,16 +45,6 @@ extern const regdma_entries_config_t l2_cache_regs_retention[L2_CACHE_RETENTION_
#define HP_SYSTEM_RETENTION_LINK_LEN 1
extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN];
/**
* @brief Provide access to uart configuration registers retention
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
*/
#define UART_RETENTION_LINK_LEN 3
extern const regdma_entries_config_t uart_regs_retention[UART_RETENTION_LINK_LEN];
/**
* @brief Provide access to timer group configuration registers retention
* context definition.