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System/Security: Memprot API unified (ESP32C3)
Unified Memory protection API for all PMS-aware chips (ESP32C3) Closes JIRA IDF-3849
This commit is contained in:
Martin Vychodil
@@ -1,59 +1,22 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/sensitive_reg.h"
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#include "soc/cache_memory.h"
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#include "hal/assert.h"
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#include "soc/memprot_defs.h"
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#include "hal/memprot_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ******************************************************************************************************
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* *** GLOBALS ***
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* NOTE: in this version, all the configurations apply only to WORLD_0
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*/
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#define IRAM_SRAM_START 0x4037C000
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#define DRAM_SRAM_START 0x3FC7C000
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/* ICache size is fixed to 16KB on ESP32-C3 */
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#ifndef ICACHE_SIZE
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#define ICACHE_SIZE 0x4000
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#endif
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#ifndef I_D_SRAM_SEGMENT_SIZE
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#define I_D_SRAM_SEGMENT_SIZE 0x20000
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#endif
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#define I_D_SPLIT_LINE_SHIFT 0x9
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#define I_D_FAULT_ADDR_SHIFT 0x2
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typedef union {
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struct {
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uint32_t cat0 : 2;
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uint32_t cat1 : 2;
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uint32_t cat2 : 2;
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uint32_t res0 : 8;
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uint32_t splitaddr : 8;
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uint32_t res1 : 10;
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};
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uint32_t val;
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} constrain_reg_fields_t;
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* *** COMMON ***
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* ******************************************************************************************************/
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static inline void memprot_ll_set_iram0_dram0_split_line_lock(void)
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{
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REG_WRITE(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG, 1);
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@@ -64,7 +27,7 @@ static inline bool memprot_ll_get_iram0_dram0_split_line_lock(void)
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return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1;
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}
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static inline void* memprot_ll_get_split_addr_from_reg(uint32_t regval, uint32_t base)
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static inline void *memprot_ll_get_split_addr_from_reg(uint32_t regval, uint32_t base)
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{
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constrain_reg_fields_t reg_val;
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reg_val.val = regval;
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@@ -85,43 +48,30 @@ static inline void* memprot_ll_get_split_addr_from_reg(uint32_t regval, uint32_t
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/* ******************************************************************************************************
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* *** IRAM0 ***
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*/
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//16kB (CACHE)
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#define IRAM0_SRAM_LEVEL_0_LOW IRAM_SRAM_START //0x40370000
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#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + ICACHE_SIZE - 0x1) //0x4037FFFF
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//128kB (LEVEL 1)
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#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
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#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
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//128kB (LEVEL 2)
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#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
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#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
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//128kB (LEVEL 3)
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#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
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#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
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//permission bits
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R 0x1
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W 0x2
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F 0x4
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* ******************************************************************************************************/
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static inline uint32_t memprot_ll_iram0_get_intr_source_num(void)
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{
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return ETS_CORE0_IRAM0_PMS_INTR_SOURCE;
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}
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///////////////////////////////////
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// IRAM0 - SPLIT LINES
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///////////////////////////////////
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static inline void memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg)
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/* ********************************
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* IRAM0 - SPLIT LINES
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*
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* NOTES:
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* 1. IRAM0/DRAM0 split-lines must be aligned to 512B boundaries (PMS module restriction)
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* 2. split address must fall into appropriate IRAM0/DRAM0 region
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*/
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static inline memprot_ll_err_t memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg)
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{
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uint32_t addr = (uint32_t)line_addr;
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HAL_ASSERT(addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH);
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if (addr < IRAM0_SRAM_LEVEL_1_LOW || addr > IRAM0_SRAM_LEVEL_3_HIGH) {
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return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE;
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}
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if (addr % 0x200 != 0) {
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return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
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}
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uint32_t category[3] = {0};
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if (addr <= IRAM0_SRAM_LEVEL_1_HIGH) {
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@@ -141,47 +91,61 @@ static inline void memprot_ll_set_iram0_split_line(const void *line_addr, uint32
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(category[2] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S);
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uint32_t conf_addr = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S;
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uint32_t reg_cfg = conf_addr | category_bits;
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REG_WRITE(sensitive_reg, reg_cfg);
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return MEMP_LL_OK;
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}
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/* can be both IRAM0/DRAM0 address */
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static inline void memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr)
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static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr)
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{
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memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG);
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return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG);
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}
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static inline void memprot_ll_set_iram0_split_line_I_0(const void *line_addr)
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static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_I_0(const void *line_addr)
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{
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memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG);
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return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG);
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}
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static inline void memprot_ll_set_iram0_split_line_I_1(const void *line_addr)
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static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_I_1(const void *line_addr)
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{
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memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG);
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return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG);
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}
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static inline void* memprot_ll_get_iram0_split_line_main_I_D(void)
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static inline uint32_t memprot_ll_get_iram0_split_line_main_I_D_cat(void)
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{
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return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG) & 0x3F;
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}
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static inline uint32_t memprot_ll_get_iram0_split_line_I_0_cat(void)
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{
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return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG) & 0x3F;
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}
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static inline uint32_t memprot_ll_get_iram0_split_line_I_1_cat(void)
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{
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return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG) & 0x3F;
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}
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static inline void *memprot_ll_get_iram0_split_line_main_I_D(void)
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{
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return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG), SOC_DIRAM_IRAM_LOW);
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}
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static inline void* memprot_ll_get_iram0_split_line_I_0(void)
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static inline void *memprot_ll_get_iram0_split_line_I_0(void)
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{
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return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG), SOC_DIRAM_IRAM_LOW);
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}
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static inline void* memprot_ll_get_iram0_split_line_I_1(void)
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static inline void *memprot_ll_get_iram0_split_line_I_1(void)
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{
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return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG), SOC_DIRAM_IRAM_LOW);
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}
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///////////////////////////////////
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// IRAM0 - PMS CONFIGURATION
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///////////////////////////////////
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// lock
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static inline void memprot_ll_iram0_set_pms_lock(void)
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@@ -198,14 +162,14 @@ static inline bool memprot_ll_iram0_get_pms_lock(void)
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static inline uint32_t memprot_ll_iram0_set_permissions(bool r, bool w, bool x)
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{
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uint32_t permissions = 0;
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if ( r ) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R;
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if (r) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R;
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}
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if ( w ) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W;
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if (w) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W;
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}
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if ( x ) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F;
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if (x) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F;
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}
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return permissions;
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@@ -233,39 +197,38 @@ static inline void memprot_ll_iram0_set_pms_area_3(bool r, bool w, bool x)
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static inline void memprot_ll_iram0_get_permissions(uint32_t perms, bool *r, bool *w, bool *x)
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{
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*r = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R;
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*w = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W;
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*x = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F;
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*r = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R;
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*w = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W;
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*x = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F;
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}
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static inline void memprot_ll_iram0_get_pms_area_0(bool *r, bool *w, bool *x)
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{
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uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0);
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memprot_ll_iram0_get_permissions( permissions, r, w, x);
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memprot_ll_iram0_get_permissions(permissions, r, w, x);
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}
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static inline void memprot_ll_iram0_get_pms_area_1(bool *r, bool *w, bool *x)
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{
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uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1);
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memprot_ll_iram0_get_permissions( permissions, r, w, x);
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memprot_ll_iram0_get_permissions(permissions, r, w, x);
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}
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static inline void memprot_ll_iram0_get_pms_area_2(bool *r, bool *w, bool *x)
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{
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uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2);
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memprot_ll_iram0_get_permissions( permissions, r, w, x);
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memprot_ll_iram0_get_permissions(permissions, r, w, x);
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}
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static inline void memprot_ll_iram0_get_pms_area_3(bool *r, bool *w, bool *x)
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{
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uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3);
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memprot_ll_iram0_get_permissions( permissions, r, w, x);
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memprot_ll_iram0_get_permissions(permissions, r, w, x);
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}
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///////////////////////////////////
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// IRAM0 - MONITOR
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///////////////////////////////////
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// lock
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static inline void memprot_ll_iram0_set_monitor_lock(void)
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@@ -281,26 +244,31 @@ static inline bool memprot_ll_iram0_get_monitor_lock(void)
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// interrupt enable/clear
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static inline void memprot_ll_iram0_set_monitor_en(bool enable)
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{
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if ( enable ) {
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REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN );
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if (enable) {
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REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN);
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} else {
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REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN );
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REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN);
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}
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}
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static inline bool memprot_ll_iram0_get_monitor_intrclr(void)
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{
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return REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0;
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}
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static inline bool memprot_ll_iram0_get_monitor_en(void)
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{
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return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN ) == 1;
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return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) == 1;
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}
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static inline void memprot_ll_iram0_clear_monitor_intr(void)
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static inline void memprot_ll_iram0_set_monitor_intrclr(void)
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{
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REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR );
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REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR);
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}
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static inline void memprot_ll_iram0_reset_clear_monitor_intr(void)
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static inline void memprot_ll_iram0_reset_monitor_intrclr(void)
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{
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REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR );
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REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR);
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}
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static inline uint32_t memprot_ll_iram0_get_monitor_enable_register(void)
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@@ -308,31 +276,31 @@ static inline uint32_t memprot_ll_iram0_get_monitor_enable_register(void)
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return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG);
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}
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// // permission violation status
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// permission violation status
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static inline uint32_t memprot_ll_iram0_get_monitor_status_intr(void)
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{
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return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_wr(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_loadstore(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_world(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_addr(void)
|
||||
static inline intptr_t memprot_ll_iram0_get_monitor_status_fault_addr(void)
|
||||
{
|
||||
uint32_t addr = REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR );
|
||||
return addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0;
|
||||
uint32_t addr = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR);
|
||||
return (intptr_t)(addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_iram0_get_monitor_status_register(void)
|
||||
@@ -342,43 +310,309 @@ static inline uint32_t memprot_ll_iram0_get_monitor_status_register(void)
|
||||
|
||||
|
||||
/* ******************************************************************************************************
|
||||
* *** DRAM0 ***
|
||||
* *** RTC_FAST ***
|
||||
*/
|
||||
|
||||
//cache not available from DRAM (!)
|
||||
#define DRAM0_SRAM_LEVEL_0_LOW DRAM_SRAM_START //0x3FC7C000
|
||||
#define DRAM0_SRAM_LEVEL_0_HIGH (DRAM0_SRAM_LEVEL_0_LOW + ICACHE_SIZE - 0x1) //0x3FC7FFFF
|
||||
static inline uint32_t memprot_ll_rtcfast_get_intr_source_num(void)
|
||||
{
|
||||
return ETS_CORE0_PIF_PMS_INTR_SOURCE;
|
||||
}
|
||||
|
||||
//128kB
|
||||
#define DRAM0_SRAM_LEVEL_1_LOW (DRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x3FC80000
|
||||
#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
|
||||
//shared PIF PMS lock
|
||||
//!!!: use after ALL the constraints have been set
|
||||
static inline void memprot_ll_set_pif_constraint_lock(void)
|
||||
{
|
||||
REG_WRITE(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG, 1);
|
||||
}
|
||||
|
||||
//128kB
|
||||
#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
|
||||
#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
|
||||
static inline bool memprot_ll_get_pif_constraint_lock(void)
|
||||
{
|
||||
return REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG) == 1;
|
||||
}
|
||||
|
||||
//128kB
|
||||
#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
|
||||
#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
|
||||
static inline uint32_t memprot_ll_rtcfast_get_splitaddr_register(void)
|
||||
{
|
||||
return REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG);
|
||||
}
|
||||
|
||||
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W 0x2
|
||||
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R 0x1
|
||||
/* ********************************
|
||||
* IRAM0 RTCFAST - SPLIT LINES
|
||||
*
|
||||
* NOTES:
|
||||
* 1. there is only 1 split line for RTCFAST/WORLD
|
||||
* 2. RTCFAST split-line must be aligned to 4B boundaries (PMS stores 11 bits of 13-bit offset in 8kB RTCFAST region)
|
||||
* 3. RTCFAST has weird section structure (text -> dummy (!) -> force -> data) - .dummy section seems to have wrong mapping (it doesn't fall inline with .rtctext)
|
||||
*/
|
||||
static inline memprot_ll_err_t memprot_ll_set_rtcfast_split_line(const void *line_addr, memprot_ll_world_t world)
|
||||
{
|
||||
uint32_t addr = (uint32_t)line_addr;
|
||||
uint32_t mask;
|
||||
|
||||
if (addr < SOC_RTC_IRAM_LOW || addr >= SOC_RTC_IRAM_HIGH) {
|
||||
return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE;
|
||||
}
|
||||
|
||||
if (addr % 0x4 != 0) {
|
||||
return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
|
||||
}
|
||||
|
||||
switch (world) {
|
||||
case MEMP_LL_WORLD_0:
|
||||
mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M;
|
||||
break;
|
||||
case MEMP_LL_WORLD_1:
|
||||
mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M;
|
||||
break;
|
||||
default:
|
||||
return MEMP_LL_ERR_WORLD_INVALID;
|
||||
}
|
||||
|
||||
//offset bits to store are the same width for both worlds -> using SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V
|
||||
CLEAR_PERI_REG_MASK(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG, mask);
|
||||
REG_SET_BITS(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG, mask, (addr >> 2) & SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V);
|
||||
|
||||
return MEMP_LL_OK;
|
||||
}
|
||||
|
||||
static inline memprot_ll_err_t memprot_ll_get_rtcfast_split_line(memprot_ll_world_t world, void **line_addr)
|
||||
{
|
||||
uint32_t reg_addr = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG);
|
||||
uint32_t mask = 0;
|
||||
uint32_t shift = 0;
|
||||
|
||||
switch (world) {
|
||||
case MEMP_LL_WORLD_0:
|
||||
mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M;
|
||||
shift = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S;
|
||||
break;
|
||||
case MEMP_LL_WORLD_1:
|
||||
mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M;
|
||||
shift = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S;
|
||||
break;
|
||||
default:
|
||||
return MEMP_LL_ERR_WORLD_INVALID;
|
||||
}
|
||||
|
||||
*line_addr = (void *)((((reg_addr & mask) >> shift) << 2) + SOC_RTC_IRAM_LOW);
|
||||
|
||||
return MEMP_LL_OK;
|
||||
}
|
||||
|
||||
///////////////////////////////////
|
||||
// RTC_FAST - PMS CONFIGURATION
|
||||
|
||||
// permission settings
|
||||
static inline uint32_t memprot_ll_rtcfast_set_permissions(bool r, bool w, bool x)
|
||||
{
|
||||
uint32_t permissions = 0;
|
||||
if (r) {
|
||||
permissions |= SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R;
|
||||
}
|
||||
if (w) {
|
||||
permissions |= SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W;
|
||||
}
|
||||
if (x) {
|
||||
permissions |= SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F;
|
||||
}
|
||||
|
||||
return permissions;
|
||||
}
|
||||
|
||||
static inline memprot_ll_err_t memprot_ll_rtcfast_set_pms_area(bool r, bool w, bool x, memprot_ll_world_t world, memprot_ll_area_t area)
|
||||
{
|
||||
uint32_t bits = 0;
|
||||
uint32_t mask = 0;
|
||||
|
||||
switch (world) {
|
||||
case MEMP_LL_WORLD_0: {
|
||||
switch (area) {
|
||||
case MEMP_LL_AREA_LOW:
|
||||
bits = memprot_ll_rtcfast_set_permissions(r, w, x) << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S;
|
||||
mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M;
|
||||
break;
|
||||
case MEMP_LL_AREA_HIGH:
|
||||
bits = memprot_ll_rtcfast_set_permissions(r, w, x) << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S;
|
||||
mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M;
|
||||
break;
|
||||
default:
|
||||
return MEMP_LL_ERR_AREA_INVALID;
|
||||
}
|
||||
} break;
|
||||
case MEMP_LL_WORLD_1: {
|
||||
switch (area) {
|
||||
case MEMP_LL_AREA_LOW:
|
||||
bits = memprot_ll_rtcfast_set_permissions(r, w, x) << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S;
|
||||
mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M;
|
||||
break;
|
||||
case MEMP_LL_AREA_HIGH:
|
||||
bits = memprot_ll_rtcfast_set_permissions(r, w, x) << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S;
|
||||
mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M;
|
||||
break;
|
||||
default:
|
||||
return MEMP_LL_ERR_AREA_INVALID;
|
||||
}
|
||||
} break;
|
||||
default:
|
||||
return MEMP_LL_ERR_WORLD_INVALID;
|
||||
}
|
||||
|
||||
CLEAR_PERI_REG_MASK(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, mask);
|
||||
REG_SET_BITS(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, bits, mask);
|
||||
|
||||
return MEMP_LL_OK;
|
||||
}
|
||||
|
||||
static inline void memprot_ll_rtcfast_get_permissions(uint32_t perms, bool *r, bool *w, bool *x)
|
||||
{
|
||||
*r = perms & SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R;
|
||||
*w = perms & SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W;
|
||||
*x = perms & SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F;
|
||||
}
|
||||
|
||||
static inline memprot_ll_err_t memprot_ll_rtcfast_get_pms_area(bool *r, bool *w, bool *x, memprot_ll_world_t world, memprot_ll_area_t area)
|
||||
{
|
||||
uint32_t permissions = 0;
|
||||
|
||||
switch (world) {
|
||||
case MEMP_LL_WORLD_0: {
|
||||
switch (area) {
|
||||
case MEMP_LL_AREA_LOW:
|
||||
permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L);
|
||||
break;
|
||||
case MEMP_LL_AREA_HIGH:
|
||||
permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H);
|
||||
break;
|
||||
default:
|
||||
return MEMP_LL_ERR_AREA_INVALID;
|
||||
}
|
||||
} break;
|
||||
case MEMP_LL_WORLD_1: {
|
||||
switch (area) {
|
||||
case MEMP_LL_AREA_LOW:
|
||||
permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L);
|
||||
break;
|
||||
case MEMP_LL_AREA_HIGH:
|
||||
permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H);
|
||||
break;
|
||||
default:
|
||||
return MEMP_LL_ERR_AREA_INVALID;
|
||||
}
|
||||
} break;
|
||||
default:
|
||||
return MEMP_LL_ERR_WORLD_INVALID;
|
||||
}
|
||||
|
||||
memprot_ll_rtcfast_get_permissions(permissions, r, w, x);
|
||||
|
||||
return MEMP_LL_OK;
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_rtcfast_get_permission_register(void)
|
||||
{
|
||||
return REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG);
|
||||
}
|
||||
|
||||
///////////////////////////////////
|
||||
// RTC_FAST - MONITOR
|
||||
|
||||
// lock
|
||||
static inline void memprot_ll_rtcfast_set_monitor_lock(void)
|
||||
{
|
||||
REG_WRITE(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG, 1);
|
||||
}
|
||||
|
||||
static inline bool memprot_ll_rtcfast_get_monitor_lock(void)
|
||||
{
|
||||
return REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG) == 1;
|
||||
}
|
||||
|
||||
// interrupt enable/clear
|
||||
static inline void memprot_ll_rtcfast_set_monitor_en(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN);
|
||||
} else {
|
||||
REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN);
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool memprot_ll_rtcfast_get_monitor_en(void)
|
||||
{
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) > 0;
|
||||
}
|
||||
|
||||
static inline bool memprot_ll_rtcfast_get_monitor_intrclr(void)
|
||||
{
|
||||
return REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) > 0;
|
||||
}
|
||||
|
||||
static inline void memprot_ll_rtcfast_set_monitor_intrclr(void)
|
||||
{
|
||||
REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR);
|
||||
}
|
||||
|
||||
static inline void memprot_ll_rtcfast_reset_monitor_intrclr(void)
|
||||
{
|
||||
REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_rtcfast_get_monitor_register(void)
|
||||
{
|
||||
return REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG);
|
||||
}
|
||||
|
||||
// permission violation status
|
||||
static inline uint32_t memprot_ll_rtcfast_get_monitor_status_intr(void)
|
||||
{
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR);
|
||||
}
|
||||
|
||||
static inline intptr_t memprot_ll_rtcfast_get_monitor_status_fault_addr(void)
|
||||
{
|
||||
//full address SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR
|
||||
return (intptr_t)REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_rtcfast_get_monitor_status_fault_world(void)
|
||||
{
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_rtcfast_get_monitor_status_fault_loadstore(void)
|
||||
{
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_rtcfast_get_monitor_status_fault_wr(void)
|
||||
{
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE);
|
||||
}
|
||||
|
||||
|
||||
/* ******************************************************************************************************
|
||||
* *** DRAM0 ***
|
||||
* ******************************************************************************************************/
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_intr_source_num(void)
|
||||
{
|
||||
return ETS_CORE0_DRAM0_PMS_INTR_SOURCE;
|
||||
}
|
||||
|
||||
|
||||
///////////////////////////////////
|
||||
// DRAM0 - SPLIT LINES
|
||||
///////////////////////////////////
|
||||
|
||||
static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg)
|
||||
static inline memprot_ll_err_t memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg)
|
||||
{
|
||||
uint32_t addr = (uint32_t)line_addr;
|
||||
HAL_ASSERT(addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH);
|
||||
|
||||
//sanity check: split address required above unified mgmt region & 32bit aligned
|
||||
if (addr < DRAM0_SRAM_LEVEL_1_LOW || addr > DRAM0_SRAM_LEVEL_3_HIGH) {
|
||||
return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE;
|
||||
}
|
||||
//split-line must be divisible by 512 (PMS module restriction)
|
||||
if (addr % 0x200 != 0) {
|
||||
return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
|
||||
}
|
||||
|
||||
uint32_t category[3] = {0};
|
||||
if (addr <= DRAM0_SRAM_LEVEL_1_HIGH) {
|
||||
@@ -398,36 +632,45 @@ static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32
|
||||
(category[2] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S);
|
||||
|
||||
uint32_t conf_addr = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S;
|
||||
|
||||
uint32_t reg_cfg = conf_addr | category_bits;
|
||||
|
||||
REG_WRITE(sensitive_reg, reg_cfg);
|
||||
|
||||
return MEMP_LL_OK;
|
||||
}
|
||||
|
||||
static inline void memprot_ll_set_dram0_split_line_D_0(const void *line_addr)
|
||||
static inline memprot_ll_err_t memprot_ll_set_dram0_split_line_D_0(const void *line_addr)
|
||||
{
|
||||
memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG);
|
||||
return memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG);
|
||||
}
|
||||
|
||||
static inline void memprot_ll_set_dram0_split_line_D_1(const void *line_addr)
|
||||
static inline memprot_ll_err_t memprot_ll_set_dram0_split_line_D_1(const void *line_addr)
|
||||
{
|
||||
memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG);
|
||||
return memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG);
|
||||
}
|
||||
|
||||
static inline void* memprot_ll_get_dram0_split_line_D_0(void)
|
||||
static inline void *memprot_ll_get_dram0_split_line_D_0(void)
|
||||
{
|
||||
return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG), SOC_DIRAM_DRAM_LOW);
|
||||
}
|
||||
|
||||
static inline void* memprot_ll_get_dram0_split_line_D_1(void)
|
||||
static inline void *memprot_ll_get_dram0_split_line_D_1(void)
|
||||
{
|
||||
return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG), SOC_DIRAM_DRAM_LOW);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_get_dram0_split_line_D_0_cat(void)
|
||||
{
|
||||
return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG) & 0x3F;
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_get_dram0_split_line_D_1_cat(void)
|
||||
{
|
||||
return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG) & 0x3F;
|
||||
}
|
||||
|
||||
///////////////////////////////////
|
||||
// DRAM0 - PMS CONFIGURATION
|
||||
///////////////////////////////////
|
||||
|
||||
// lock
|
||||
static inline void memprot_ll_dram0_set_pms_lock(void)
|
||||
@@ -444,11 +687,11 @@ static inline bool memprot_ll_dram0_get_pms_lock(void)
|
||||
static inline uint32_t memprot_ll_dram0_set_permissions(bool r, bool w)
|
||||
{
|
||||
uint32_t permissions = 0;
|
||||
if ( r ) {
|
||||
permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R;
|
||||
if (r) {
|
||||
permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R;
|
||||
}
|
||||
if ( w ) {
|
||||
permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W;
|
||||
if (w) {
|
||||
permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W;
|
||||
}
|
||||
|
||||
return permissions;
|
||||
@@ -476,37 +719,36 @@ static inline void memprot_ll_dram0_set_pms_area_3(bool r, bool w)
|
||||
|
||||
static inline void memprot_ll_dram0_get_permissions(uint32_t perms, bool *r, bool *w )
|
||||
{
|
||||
*r = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R;
|
||||
*w = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W;
|
||||
*r = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R;
|
||||
*w = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W;
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_get_pms_area_0(bool *r, bool *w)
|
||||
{
|
||||
uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0);
|
||||
memprot_ll_dram0_get_permissions( permissions, r, w);
|
||||
memprot_ll_dram0_get_permissions(permissions, r, w);
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_get_pms_area_1(bool *r, bool *w)
|
||||
{
|
||||
uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1);
|
||||
memprot_ll_dram0_get_permissions( permissions, r, w);
|
||||
memprot_ll_dram0_get_permissions(permissions, r, w);
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_get_pms_area_2(bool *r, bool *w)
|
||||
{
|
||||
uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2);
|
||||
memprot_ll_dram0_get_permissions( permissions, r, w);
|
||||
memprot_ll_dram0_get_permissions(permissions, r, w);
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_get_pms_area_3(bool *r, bool *w)
|
||||
{
|
||||
uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3);
|
||||
memprot_ll_dram0_get_permissions( permissions, r, w);
|
||||
memprot_ll_dram0_get_permissions(permissions, r, w);
|
||||
}
|
||||
|
||||
///////////////////////////////////
|
||||
// DRAM0 - MONITOR
|
||||
///////////////////////////////////
|
||||
|
||||
// lock
|
||||
static inline void memprot_ll_dram0_set_monitor_lock(void)
|
||||
@@ -522,26 +764,31 @@ static inline bool memprot_ll_dram0_get_monitor_lock(void)
|
||||
// interrupt enable/clear
|
||||
static inline void memprot_ll_dram0_set_monitor_en(bool enable)
|
||||
{
|
||||
if ( enable ) {
|
||||
REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN );
|
||||
if (enable) {
|
||||
REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN);
|
||||
} else {
|
||||
REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN );
|
||||
REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN);
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool memprot_ll_dram0_get_monitor_en(void)
|
||||
{
|
||||
return REG_GET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN ) == 1;
|
||||
return REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0;
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_clear_monitor_intr(void)
|
||||
static inline void memprot_ll_dram0_set_monitor_intrclr(void)
|
||||
{
|
||||
REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR );
|
||||
REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR);
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_reset_clear_monitor_intr(void)
|
||||
static inline void memprot_ll_dram0_reset_monitor_intrclr(void)
|
||||
{
|
||||
REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR );
|
||||
REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR);
|
||||
}
|
||||
|
||||
static inline bool memprot_ll_dram0_get_monitor_intrclr(void)
|
||||
{
|
||||
return REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0;
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_enable_register(void)
|
||||
@@ -552,33 +799,33 @@ static inline uint32_t memprot_ll_dram0_get_monitor_enable_register(void)
|
||||
// permission violation status
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_intr(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_lock(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_world(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_addr(void)
|
||||
{
|
||||
uint32_t addr = REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR );
|
||||
uint32_t addr = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR);
|
||||
return addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + DRAM0_ADDRESS_LOW : 0;
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_wr(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_byte_en(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN );
|
||||
return REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN);
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_register_1(void)
|
||||
|
||||
Reference in New Issue
Block a user