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esp32/esp32s2beta: Extract common SPIRAM options into esp_commmon component

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This commit is contained in:
Angus Gratton
2019-06-05 14:34:19 +10:00
committed by suda-morris
parent 06e31e243c
commit ddbd09eb15
28 changed files with 156 additions and 238 deletions
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4
components/soc/esp32s2beta/soc_memory_layout.c
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@@ -67,7 +67,7 @@ Because of requirements in the coalescing code which merges adjacent regions, th
from low to high start address.
*/
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available
#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
{ SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH - SOC_SLOW_EXTRAM_DATA_LOW, 5, 0}, //SPI SRAM, if available
@@ -135,7 +135,7 @@ const soc_reserved_region_t soc_reserved_regions[] = {
#endif
#endif
#ifdef CONFIG_SPIRAM_SUPPORT
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH}, //SPI RAM gets added later if needed, in spiram.c; reserve it for now
#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
{ SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH}, //SPI RAM(Slow) gets added later if needed, in spiram.c; reserve it for now

4
components/soc/esp32s2beta/test/test_rtc_clk.c
View File

@@ -214,7 +214,7 @@ static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_m
printf("Test passed successfully\n");
}
#ifdef CONFIG_SPIRAM_SUPPORT
#ifdef CONFIG_SPIRAM
// PSRAM tests run on ESP-WROVER-KIT boards, which have the 32k XTAL installed.
// Other tests may run on DevKitC boards, which don't have a 32k XTAL.
TEST_CASE("Test starting external RTC quartz", "[rtc_clk]")
@@ -280,5 +280,5 @@ TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_
start_freq(RTC_SLOW_FREQ_RTC, 0);
}
#endif // CONFIG_SPIRAM_SUPPORT
#endif // CONFIG_SPIRAM
#endif