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feat(glitch_filter): support GPIO glitch filter on esp32p4
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -14,6 +14,12 @@
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#include "driver/dedic_gpio.h"
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#include "soc/soc_caps.h"
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#if CONFIG_IDF_TARGET_ESP32P4
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#define TEST_FILTER_GPIO 20
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#else
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#define TEST_FILTER_GPIO 2
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#endif
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#if SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
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TEST_CASE("GPIO pin glitch filter life cycle", "[gpio_filter]")
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@@ -108,7 +114,7 @@ NOINLINE_ATTR IRAM_ATTR static void test_gpio_simulate_glitch_pulse(void)
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TEST_CASE("GPIO flex glitch filter enable/disable", "[gpio_filter]")
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{
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const gpio_num_t test_gpio = 2;
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const gpio_num_t test_gpio = TEST_FILTER_GPIO;
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printf("initialize GPIO for input and out\r\n");
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gpio_config_t gpio_cfg = {
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@@ -1,6 +1,5 @@
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# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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# SPDX-License-Identifier: CC0-1.0
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import pytest
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from pytest_embedded_idf import IdfDut
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@@ -16,6 +15,7 @@ CONFIGS = [
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@pytest.mark.esp32h2
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@pytest.mark.esp32s2
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@pytest.mark.esp32s3
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@pytest.mark.esp32p4
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@pytest.mark.generic
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@pytest.mark.parametrize('config', CONFIGS, indirect=True)
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def test_gpio_filter(dut: IdfDut) -> None:
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