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change(soc): added SOC_ prefix to mmu defs

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This commit is contained in:
Armando
2023-08-31 12:28:04 +08:00
parent a9e3f963c2
commit de77ab3061
44 changed files with 550 additions and 621 deletions
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46
components/hal/esp32p4/include/hal/mmu_ll.h
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@@ -72,9 +72,9 @@ static inline mmu_target_t mmu_ll_vaddr_to_target(uint32_t vaddr)
{
mmu_target_t target = MMU_TARGET_FLASH0;
if (ADDRESS_IN_DRAM_FLASH(vaddr)) {
if (SOC_ADDRESS_IN_DRAM_FLASH(vaddr)) {
target = MMU_TARGET_FLASH0;
} else if (ADDRESS_IN_DRAM_PSRAM(vaddr)) {
} else if (SOC_ADDRESS_IN_DRAM_PSRAM(vaddr)) {
target = MMU_TARGET_PSRAM0;
} else {
HAL_ASSERT(false);
@@ -133,7 +133,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
(void)mmu_id;
(void)type;
uint32_t vaddr_end = vaddr_start + len - 1;
return (ADDRESS_IN_DRAM_FLASH(vaddr_start) && ADDRESS_IN_DRAM_FLASH(vaddr_end)) || (ADDRESS_IN_DRAM_PSRAM(vaddr_start) && ADDRESS_IN_DRAM_PSRAM(vaddr_end));
return (SOC_ADDRESS_IN_DRAM_FLASH(vaddr_start) && SOC_ADDRESS_IN_DRAM_FLASH(vaddr_end)) || (SOC_ADDRESS_IN_DRAM_PSRAM(vaddr_start) && SOC_ADDRESS_IN_DRAM_PSRAM(vaddr_end));
}
/**
@@ -150,9 +150,9 @@ static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t pad
{
int max_paddr_page_num = 0;
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
max_paddr_page_num = MMU_FLASH_MAX_PADDR_PAGE_NUM;
max_paddr_page_num = SOC_MMU_FLASH_MAX_PADDR_PAGE_NUM;
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
max_paddr_page_num = MMU_PSRAM_MAX_PADDR_PAGE_NUM;
max_paddr_page_num = SOC_MMU_PSRAM_MAX_PADDR_PAGE_NUM;
} else {
HAL_ASSERT(false);
}
@@ -192,7 +192,7 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
default:
HAL_ASSERT(shift_code);
}
return ((vaddr & MMU_VADDR_MASK) >> shift_code);
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
}
/**
@@ -247,15 +247,15 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
sensitive = MMU_FLASH_SENSITIVE;
mmu_val |= MMU_FLASH_VALID;
mmu_val |= MMU_ACCESS_FLASH;
sensitive = SOC_MMU_FLASH_SENSITIVE;
mmu_val |= SOC_MMU_FLASH_VALID;
mmu_val |= SOC_MMU_ACCESS_FLASH;
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
sensitive = MMU_PSRAM_SENSITIVE;
mmu_val |= MMU_PSRAM_VALID;
mmu_val |= MMU_ACCESS_PSRAM;
sensitive = SOC_MMU_PSRAM_SENSITIVE;
mmu_val |= SOC_MMU_PSRAM_VALID;
mmu_val |= SOC_MMU_ACCESS_PSRAM;
} else {
HAL_ASSERT(false);
}
@@ -312,11 +312,11 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
invalid_mask = MMU_FLASH_INVALID;
invalid_mask = SOC_MMU_FLASH_INVALID;
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
invalid_mask = MMU_PSRAM_INVALID;
invalid_mask = SOC_MMU_PSRAM_INVALID;
} else {
HAL_ASSERT(false);
}
@@ -333,7 +333,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
__attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{
for (int i = 0; i < MMU_ENTRY_NUM; i++) {
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i);
}
}
@@ -356,11 +356,11 @@ static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
valid_mask = MMU_FLASH_VALID;
valid_mask = SOC_MMU_FLASH_VALID;
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
valid_mask = MMU_PSRAM_VALID;
valid_mask = SOC_MMU_PSRAM_VALID;
} else {
HAL_ASSERT(false);
}
@@ -410,7 +410,7 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
*/
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
{
HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
@@ -432,10 +432,10 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
}
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, entry_id);
return (REG_READ(SPI_MEM_C_MMU_ITEM_CONTENT_REG) & MMU_FLASH_VALID_VAL_MASK) << shift_code;
return (REG_READ(SPI_MEM_C_MMU_ITEM_CONTENT_REG) & SOC_MMU_FLASH_VALID_VAL_MASK) << shift_code;
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
REG_WRITE(SPI_MEM_S_MMU_ITEM_INDEX_REG, entry_id);
return (REG_READ(SPI_MEM_S_MMU_ITEM_CONTENT_REG) & MMU_PSRAM_VALID_VAL_MASK) << shift_code;
return (REG_READ(SPI_MEM_S_MMU_ITEM_CONTENT_REG) & SOC_MMU_PSRAM_VALID_VAL_MASK) << shift_code;
} else {
HAL_ASSERT(false);
}
@@ -461,16 +461,16 @@ static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint3
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
valid_val_mask = MMU_FLASH_VALID_VAL_MASK;
valid_val_mask = SOC_MMU_FLASH_VALID_VAL_MASK;
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
valid_val_mask = MMU_PSRAM_VALID_VAL_MASK;
valid_val_mask = SOC_MMU_PSRAM_VALID_VAL_MASK;
} else {
HAL_ASSERT(false);
}
for (int i = 0; i < MMU_ENTRY_NUM; i++) {
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
if (mmu_ll_check_entry_valid(mmu_id, i)) {
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
REG_WRITE(index_reg, i);