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Merge branch 'bugfix/fix_batch_of_i2c_issue_v5.3' into 'release/v5.3'

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fix(i2c_master): Fix an I2C issue that slave streth happen but master timeout...etc.4MR (backport v5.3)

See merge request espressif/esp-idf!33475
This commit is contained in:
morris
2024-09-13 15:49:39 +08:00
parent c72fec55dd 403bd86a21
commit df00c22439
11 changed files with 255 additions and 120 deletions
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42
components/hal/esp32c5/include/hal/i2c_ll.h
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@@ -611,7 +611,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@@ -646,7 +646,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
@@ -738,18 +738,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**
@@ -790,8 +801,8 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0;
ctrl_reg.ms_mode = 1;
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val;
}
@@ -806,8 +817,8 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
{
typeof(hw->ctr) ctrl_reg;
ctrl_reg.val = 0;
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
@@ -863,7 +874,8 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@@ -902,7 +914,7 @@ typedef enum {
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL high period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@@ -1090,7 +1102,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param hight_period The I2C SCL high period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
*
* @return None.