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feat(pwr_glitch): Add power glitch support on esp32c5/esp32c61

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chaijie@espressif.com
2024-08-23 14:31:49 +08:00
committed by zhoupeng
parent 1662e28718
commit e1423c53d5
11 changed files with 120 additions and 51 deletions
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29
components/bootloader_support/src/esp32c5/bootloader_soc.c
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@@ -7,18 +7,29 @@
#include <assert.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
// TODO: [ESP32C5] IDF-8667 remove esp_log.h
#include "esp_log.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
// TODO: [ESP32C5] IDF-8667
ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
}
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
// TODO: [ESP32C5] IDF-8667, PM-207
(void)enable;
}
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
{
assert(dref < 8);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
if (enable) {
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
} else {
REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
}
}