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feat(adc): add always inline for adc ll functions called by bootloader

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gaoxu
2025-05-14 13:45:55 +08:00
parent b691eaba6d
commit e1b6493304
5 changed files with 55 additions and 0 deletions
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11
components/hal/esp32c6/include/hal/adc_ll.h
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@@ -138,6 +138,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
*
* @param div Division factor.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_set_clk_div(uint32_t div)
{
/* ADC clock divided from digital controller clock clk */
@@ -187,6 +188,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 8.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{
APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -202,6 +204,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
* @param pattern_index Items index. Range: 0 ~ 7.
* @param pattern Stored conversion rules.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{
uint32_t tab;
@@ -274,6 +277,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
* @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
* @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
{
APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -282,6 +286,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
/**
* Enable digital controller timer to trigger the measurement.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_trigger_enable(void)
{
APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -290,6 +295,7 @@ static inline void adc_ll_digi_trigger_enable(void)
/**
* Disable digital controller timer to trigger the measurement.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_trigger_disable(void)
{
APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -303,6 +309,7 @@ static inline void adc_ll_digi_trigger_disable(void)
* @param div_b Division factor. Range: 1 ~ 63.
* @param div_a Division factor. Range: 0 ~ 63.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -315,6 +322,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
*
* @param clk_src clock source for ADC digital controller.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
@@ -569,6 +577,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
* @brief Enable the ADC clock
* @param enable true to enable, false to disable
*/
__attribute__((always_inline))
static inline void adc_ll_enable_bus_clock(bool enable)
{
PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -578,6 +587,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
* @brief Enable the ADC function clock
* @param enable true to enable, false to disable
*/
__attribute__((always_inline))
static inline void adc_ll_enable_func_clock(bool enable)
{
PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -586,6 +596,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
/**
* @brief Reset ADC module
*/
__attribute__((always_inline))
static inline void adc_ll_reset_register(void)
{
PCR.saradc_conf.saradc_rst_en = 1;