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gptimer: clean up hal and ll for driver-ng
This commit is contained in:
morris
@@ -1,382 +1,250 @@
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Timer Group register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "hal/timer_types.h"
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#include "soc/timer_group_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdlib.h>
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#include "hal/misc.h"
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#include "hal/assert.h"
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#include "hal/timer_types.h"
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#include "soc/timer_periph.h"
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#include "soc/timer_group_struct.h"
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_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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_Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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// Get timer group instance with giving group number
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#define TIMER_LL_GET_HW(num) ((num == 0) ? (&TIMERG0) : (&TIMERG1))
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// Get timer group register base address with giving group number
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#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
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#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
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/**
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* @brief Set timer clock prescale value
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* @brief Set clock source for timer
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param divider Prescale value (0 and 1 are not valid)
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*
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* @return None
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param clk_src Clock source
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*/
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static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
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static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src)
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{
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switch (clk_src) {
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case GPTIMER_CLK_SRC_APB:
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break;
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default:
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HAL_ASSERT(false && "unsupported clock source");
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break;
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}
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}
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/**
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* @brief Enable alarm event
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable alarm
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* False: disable alarm
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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hw->hw_timer[timer_num].config.tx_alarm_en = en;
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// use level type interrupt
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hw->hw_timer[timer_num].config.tx_level_int_en = en;
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}
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/**
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* @brief Set clock prescale for timer
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param divider Prescale value (0 and 1 are not valid)
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*/
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static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
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{
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HAL_ASSERT(divider >= 2 && divider <= 65536);
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if (divider >= 65536) {
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divider = 0;
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}
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int timer_en = hw->hw_timer[timer_num].config.enable;
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hw->hw_timer[timer_num].config.enable = 0;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider, divider);
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hw->hw_timer[timer_num].config.enable = timer_en;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
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}
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/**
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* @brief Get timer clock prescale value
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* @brief Enable auto-reload mode
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param divider Pointer to accept the prescale value
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*
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* @return None
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable auto reload mode
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* False: disable auto reload mode
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*/
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static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
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static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider);
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if (d == 0) {
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d = 65536;
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} else if (d == 1) {
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d = 2;
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hw->hw_timer[timer_num].config.tx_autoreload = en;
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}
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/**
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* @brief Set count direction
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*
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* @param hw Timer peripheral register base address
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* @param timer_num Timer number in the group
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* @param direction Count direction
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*/
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static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
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{
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hw->hw_timer[timer_num].config.tx_increase = direction == GPTIMER_COUNT_UP;
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}
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/**
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* @brief Enable timer, start couting
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable the counter
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* False: disable the counter
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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hw->hw_timer[timer_num].config.tx_en = en;
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}
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/**
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* @brief Get counter value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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*
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* @return counter value
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*/
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__attribute__((always_inline))
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static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num)
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{
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hw->hw_timer[timer_num].update.tx_update = 1;
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// Timer register is in a different clock domain from Timer hardware logic
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// We need to wait for the update to take effect before fetching the count value
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while (hw->hw_timer[timer_num].update.tx_update) {
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}
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*divider = d;
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return ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
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}
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/**
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* @brief Load counter value into time-base counter
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* @brief Set alarm value
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param load_val Counter value
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*
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* @return None
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param alarm_value When counter reaches alarm value, alarm event will be triggered
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*/
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static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t load_val)
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__attribute__((always_inline))
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static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
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{
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hw->hw_timer[timer_num].load_high = (uint32_t) (load_val >> 32);
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hw->hw_timer[timer_num].load_low = (uint32_t) load_val;
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hw->hw_timer[timer_num].reload = 1;
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hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32);
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hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value;
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}
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/**
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* @brief Get counter value from time-base counter
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* @brief Get alarm value
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param timer_val Pointer to accept the counter value
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*
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* @return None
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @return Counter value to trigger the alarm event
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*/
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FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *timer_val)
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static inline uint64_t timer_ll_get_alarm_value(timg_dev_t *hw, uint32_t timer_num)
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{
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hw->hw_timer[timer_num].update = 1;
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while (hw->hw_timer[timer_num].update) {}
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*timer_val = ((uint64_t) hw->hw_timer[timer_num].cnt_high << 32) | (hw->hw_timer[timer_num].cnt_low);
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return ((uint64_t) hw->hw_timer[timer_num].alarmhi.tx_alarm_hi << 32) | (hw->hw_timer[timer_num].alarmlo.tx_alarm_lo);
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}
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/**
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* @brief Set counter mode, include increment mode and decrement mode.
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* @brief Set reload value
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param increase_en True to increment mode, fasle to decrement mode
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*
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* @return None
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param reload_val Reload counter value
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*/
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static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t timer_num, bool increase_en)
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static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t load_val)
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{
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hw->hw_timer[timer_num].config.increase = increase_en;
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hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32);
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hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val;
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}
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/**
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* @brief Get counter mode, include increment mode and decrement mode.
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* @brief Get reload value
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Increment mode
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* - false Decrement mode
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @return reload count value
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*/
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static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t timer_num)
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static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
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{
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return hw->hw_timer[timer_num].config.increase;
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return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo);
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}
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/**
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* @brief Set counter status, enable or disable counter.
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* @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param counter_en True to enable counter, false to disable counter
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*
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* @return None
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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*/
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FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t timer_num, bool counter_en)
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static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num)
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{
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hw->hw_timer[timer_num].config.enable = counter_en;
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hw->hw_timer[timer_num].load.tx_load = 1;
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}
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/**
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* @brief Get counter status.
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* @brief Enable timer interrupt by mask
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Enable counter
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* - false Disable conuter
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* @param hw Timer Group register base address
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* @param mask Mask of interrupt events
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* @param en True: enable interrupt
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* False: disable interrupt
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*/
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static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer_num)
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__attribute__((always_inline))
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static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en)
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{
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return hw->hw_timer[timer_num].config.enable;
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if (en) {
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hw->int_ena_timers.val |= mask;
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} else {
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hw->int_ena_timers.val &= ~mask;
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}
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}
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/**
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* @brief Set auto reload mode.
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* @brief Get interrupt status
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param auto_reload_en True to enable auto reload mode, flase to disable auto reload mode
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* @param hw Timer Group register base address
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*
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* @return None
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* @return Interrupt status
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*/
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static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_num, bool auto_reload_en)
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__attribute__((always_inline))
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static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw)
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{
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hw->hw_timer[timer_num].config.autoreload = auto_reload_en;
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return hw->int_st_timers.val & 0x03;
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}
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/**
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* @brief Get auto reload mode.
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* @brief Clear interrupt status by mask
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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*
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* @return
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* - true Enable auto reload mode
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* - false Disable auto reload mode
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* @param hw Timer Group register base address
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* @param mask Interrupt events mask
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*/
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FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t timer_num)
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__attribute__((always_inline))
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static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask)
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{
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return hw->hw_timer[timer_num].config.autoreload;
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hw->int_clr_timers.val = mask;
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}
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/**
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* @brief Set the counter value to trigger the alarm.
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* @brief Enable the register clock forever
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param alarm_value Counter value to trigger the alarm
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*
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* @return None
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* @param hw Timer Group register base address
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* @param en True: Enable the register clock forever
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* False: Register clock is enabled only when register operation happens
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*/
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FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t alarm_value)
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static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en)
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{
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hw->hw_timer[timer_num].alarm_high = (uint32_t) (alarm_value >> 32);
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hw->hw_timer[timer_num].alarm_low = (uint32_t) alarm_value;
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}
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/**
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* @brief Get the counter value to trigger the alarm.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param alarm_value Pointer to accept the counter value to trigger the alarm
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*
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* @return None
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*/
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static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *alarm_value)
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{
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*alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarm_high << 32) | (hw->hw_timer[timer_num].alarm_low);
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}
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/**
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* @brief Set the alarm status, enable or disable the alarm.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param timer_num The timer number
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* @param alarm_en True to enable alarm, false to disable alarm
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num, bool alarm_en)
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{
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hw->hw_timer[timer_num].config.alarm_en = alarm_en;
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}
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/**
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* @brief Get the alarm status.
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*
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* @param hw Beginning address of the peripheral registers.
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||||
* @param timer_num The timer number
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*
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* @return
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* - true Enable alarm
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* - false Disable alarm
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*/
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static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num)
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{
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return hw->hw_timer[timer_num].config.alarm_en;
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}
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||||
/**
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* @brief Enable timer interrupt.
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||||
*
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||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param timer_num The timer number
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||||
*
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||||
* @return None
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||||
*/
|
||||
FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_num)
|
||||
{
|
||||
hw->int_ena.val |= BIT(timer_num);
|
||||
hw->hw_timer[timer_num].config.level_int_en = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable timer interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param timer_num The timer number
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_num)
|
||||
{
|
||||
hw->int_ena.val &= (~BIT(timer_num));
|
||||
hw->hw_timer[timer_num].config.level_int_en = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable timer interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param timer_num The timer number
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t timer_num)
|
||||
{
|
||||
hw->int_clr_timers.val |= BIT(timer_num);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param intr_status Interrupt status
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
|
||||
{
|
||||
*intr_status = hw->int_st_timers.val & 0x03;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt raw status.
|
||||
*
|
||||
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
|
||||
* @param intr_raw_status Interrupt raw status
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
|
||||
{
|
||||
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
|
||||
*intr_raw_status = hw->int_raw.val & 0x03;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the level interrupt status, enable or disable the level interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param timer_num The timer number
|
||||
* @param level_int_en True to enable level interrupt, false to disable level interrupt
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void timer_ll_set_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool level_int_en)
|
||||
{
|
||||
hw->hw_timer[timer_num].config.level_int_en = level_int_en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the level interrupt status.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param timer_num The timer number
|
||||
*
|
||||
* @return
|
||||
* - true Enable level interrupt
|
||||
* - false Disable level interrupt
|
||||
*/
|
||||
static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
|
||||
{
|
||||
return hw->hw_timer[timer_num].config.level_int_en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the edge interrupt status, enable or disable the edge interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param timer_num The timer number
|
||||
* @param edge_int_en True to enable edge interrupt, false to disable edge interrupt
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool edge_int_en)
|
||||
{
|
||||
hw->hw_timer[timer_num].config.edge_int_en = edge_int_en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the edge interrupt status.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param timer_num The timer number
|
||||
*
|
||||
* @return
|
||||
* - true Enable edge interrupt
|
||||
* - false Disable edge interrupt
|
||||
*/
|
||||
static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
|
||||
{
|
||||
return hw->hw_timer[timer_num].config.edge_int_en;
|
||||
hw->regclk.clk_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -386,14 +254,9 @@ static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t time
|
||||
*
|
||||
* @return Interrupt status register address
|
||||
*/
|
||||
static inline uint32_t timer_ll_get_intr_status_reg(timg_dev_t *hw)
|
||||
static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
|
||||
{
|
||||
return (uint32_t) & (hw->int_st_timers.val);
|
||||
}
|
||||
|
||||
static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t timer_num)
|
||||
{
|
||||
return (1U << timer_num);
|
||||
return &hw->int_st_timers.val;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
Reference in New Issue
Block a user