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gptimer: clean up hal and ll for driver-ng

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This commit is contained in:
morris
2021-09-27 12:46:51 +08:00
parent d9dfa01c95
commit e2275b1f63
45 changed files with 2545 additions and 3276 deletions
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202
components/soc/esp32s2/include/soc/timer_group_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,44 +16,44 @@ extern "C" {
*/
typedef union {
struct {
uint32_t reserved_0:9;
uint32_t reserved_0: 9;
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
uint32_t tx_use_xtal:1;
uint32_t tx_use_xtal: 1;
/** tx_alarm_en : R/W; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
*
* alarm occurs.
*/
uint32_t tx_alarm_en:1;
uint32_t tx_alarm_en: 1;
/** tx_level_int_en : R/W; bitpos: [11]; default: 0;
* When set, an alarm will generate a level type interrupt.
*/
uint32_t tx_level_int_en:1;
uint32_t tx_level_int_en: 1;
/** tx_edge_int_en : R/W; bitpos: [12]; default: 0;
* When set, an alarm will generate an edge type interrupt.
*/
uint32_t tx_edge_int_en:1;
uint32_t tx_edge_int_en: 1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Timer x clock (Tx_clk) prescaler value.
*/
uint32_t tx_divider:16;
uint32_t tx_divider: 16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* When set, timer x auto-reload at alarm is enabled.
*/
uint32_t tx_autoreload:1;
uint32_t tx_autoreload: 1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* When set, the timer x time-base counter will increment every clock tick. When
*
* cleared, the timer x time-base counter will decrement.
*/
uint32_t tx_increase:1;
uint32_t tx_increase: 1;
/** tx_en : R/W; bitpos: [31]; default: 0;
* When set, the timer x time-base counter is enabled.
*/
uint32_t tx_en:1;
uint32_t tx_en: 1;
};
uint32_t val;
} timg_txconfig_reg_t;
@@ -68,7 +68,7 @@ typedef union {
*
* of timer x can be read here.
*/
uint32_t tx_lo:32;
uint32_t tx_lo: 32;
};
uint32_t val;
} timg_txlo_reg_t;
@@ -83,7 +83,7 @@ typedef union {
*
* of timer x can be read here.
*/
uint32_t tx_hi:32;
uint32_t tx_hi: 32;
};
uint32_t val;
} timg_txhi_reg_t;
@@ -93,11 +93,11 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:31;
uint32_t reserved_0: 31;
/** tx_update : R/W; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
*/
uint32_t tx_update:1;
uint32_t tx_update: 1;
};
uint32_t val;
} timg_txupdate_reg_t;
@@ -110,7 +110,7 @@ typedef union {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Timer x alarm trigger time-base counter value, low 32 bits.
*/
uint32_t tx_alarm_lo:32;
uint32_t tx_alarm_lo: 32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
@@ -125,7 +125,7 @@ typedef union {
*
* Timer x alarm trigger time-base counter value, high 32 bits.
*/
uint32_t tx_alarm_hi:32;
uint32_t tx_alarm_hi: 32;
};
uint32_t val;
} timg_txalarmhi_reg_t;
@@ -142,7 +142,7 @@ typedef union {
*
* Counter.
*/
uint32_t tx_load_lo:32;
uint32_t tx_load_lo: 32;
};
uint32_t val;
} timg_txloadlo_reg_t;
@@ -159,7 +159,7 @@ typedef union {
*
* counter.
*/
uint32_t tx_load_hi:32;
uint32_t tx_load_hi: 32;
};
uint32_t val;
} timg_txloadhi_reg_t;
@@ -174,7 +174,7 @@ typedef union {
*
* Write any value to trigger a timer x time-base counter reload.
*/
uint32_t tx_load:32;
uint32_t tx_load: 32;
};
uint32_t val;
} timg_txload_reg_t;
@@ -186,67 +186,67 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:12;
uint32_t reserved_0: 12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* Reserved
*/
uint32_t wdt_appcpu_reset_en:1;
uint32_t wdt_appcpu_reset_en: 1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_procpu_reset_en:1;
uint32_t wdt_procpu_reset_en: 1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
uint32_t wdt_flashboot_mod_en:1;
uint32_t wdt_flashboot_mod_en: 1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
*
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_sys_reset_length:3;
uint32_t wdt_sys_reset_length: 3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
*
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_cpu_reset_length:3;
uint32_t wdt_cpu_reset_length: 3;
/** wdt_level_int_en : R/W; bitpos: [21]; default: 0;
* When set, a level type interrupt will occur at the timeout of a stage
*
* configured to generate an interrupt.
*/
uint32_t wdt_level_int_en:1;
uint32_t wdt_level_int_en: 1;
/** wdt_edge_int_en : R/W; bitpos: [22]; default: 0;
* When set, an edge type interrupt will occur at the timeout of a stage
*
* configured to generate an interrupt.
*/
uint32_t wdt_edge_int_en:1;
uint32_t wdt_edge_int_en: 1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*
*/
uint32_t wdt_stg3:2;
uint32_t wdt_stg3: 2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*
*/
uint32_t wdt_stg2:2;
uint32_t wdt_stg2: 2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*
*/
uint32_t wdt_stg1:2;
uint32_t wdt_stg1: 2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*
*/
uint32_t wdt_stg0:2;
uint32_t wdt_stg0: 2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
uint32_t wdt_en:1;
uint32_t wdt_en: 1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
@@ -256,13 +256,13 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:16;
uint32_t reserved_0: 16;
/** wdt_clk_prescaler : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
*
* TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescaler:16;
uint32_t wdt_clk_prescaler: 16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
@@ -275,7 +275,7 @@ typedef union {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg0_hold:32;
uint32_t wdt_stg0_hold: 32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
@@ -288,7 +288,7 @@ typedef union {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg1_hold:32;
uint32_t wdt_stg1_hold: 32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
@@ -301,7 +301,7 @@ typedef union {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg2_hold:32;
uint32_t wdt_stg2_hold: 32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
@@ -314,7 +314,7 @@ typedef union {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg3_hold:32;
uint32_t wdt_stg3_hold: 32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
@@ -327,7 +327,7 @@ typedef union {
/** wdt_feed : WO; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
uint32_t wdt_feed:32;
uint32_t wdt_feed: 32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
@@ -342,7 +342,7 @@ typedef union {
*
* protection is enabled.
*/
uint32_t wdt_wkey:32;
uint32_t wdt_wkey: 32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
@@ -354,27 +354,27 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:12;
uint32_t reserved_0: 12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* Reserved
*/
uint32_t rtc_cali_start_cycling:1;
uint32_t rtc_cali_start_cycling: 1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtcslowclock. 1:clk_80m. 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel:2;
uint32_t rtc_cali_clk_sel: 2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* Reserved
*/
uint32_t rtc_cali_rdy:1;
uint32_t rtc_cali_rdy: 1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
uint32_t rtc_cali_max:15;
uint32_t rtc_cali_max: 15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t rtc_cali_start:1;
uint32_t rtc_cali_start: 1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
@@ -387,12 +387,12 @@ typedef union {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
uint32_t rtc_cali_cycling_data_vld: 1;
uint32_t reserved_1: 6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
uint32_t rtc_cali_value:25;
uint32_t rtc_cali_value: 25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
@@ -405,17 +405,17 @@ typedef union {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
uint32_t rtc_cali_timeout: 1;
uint32_t reserved_1: 2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
uint32_t rtc_cali_timeout_rst_cnt: 4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
uint32_t rtc_cali_timeout_thres:25;
uint32_t rtc_cali_timeout_thres: 25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
@@ -427,51 +427,51 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:6;
uint32_t reserved_0: 6;
/** lact_use_reftick : R/W; bitpos: [6]; default: 0;
* Reserved
*/
uint32_t lact_use_reftick:1;
uint32_t lact_use_reftick: 1;
/** lact_rtc_only : R/W; bitpos: [7]; default: 0;
* Reserved
*/
uint32_t lact_rtc_only:1;
uint32_t lact_rtc_only: 1;
/** lact_cpst_en : R/W; bitpos: [8]; default: 1;
* Reserved
*/
uint32_t lact_cpst_en:1;
uint32_t lact_cpst_en: 1;
/** lact_lac_en : R/W; bitpos: [9]; default: 1;
* Reserved
*/
uint32_t lact_lac_en:1;
uint32_t lact_lac_en: 1;
/** lact_alarm_en : R/W; bitpos: [10]; default: 0;
* Reserved
*/
uint32_t lact_alarm_en:1;
uint32_t lact_alarm_en: 1;
/** lact_level_int_en : R/W; bitpos: [11]; default: 0;
* Reserved
*/
uint32_t lact_level_int_en:1;
uint32_t lact_level_int_en: 1;
/** lact_edge_int_en : R/W; bitpos: [12]; default: 0;
* Reserved
*/
uint32_t lact_edge_int_en:1;
uint32_t lact_edge_int_en: 1;
/** lact_divider : R/W; bitpos: [28:13]; default: 1;
* Reserved
*/
uint32_t lact_divider:16;
uint32_t lact_divider: 16;
/** lact_autoreload : R/W; bitpos: [29]; default: 1;
* Reserved
*/
uint32_t lact_autoreload:1;
uint32_t lact_autoreload: 1;
/** lact_increase : R/W; bitpos: [30]; default: 1;
* Reserved
*/
uint32_t lact_increase:1;
uint32_t lact_increase: 1;
/** lact_en : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t lact_en:1;
uint32_t lact_en: 1;
};
uint32_t val;
} timg_lactconfig_reg_t;
@@ -481,11 +481,11 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:6;
uint32_t reserved_0: 6;
/** lact_rtc_step_len : R/W; bitpos: [31:6]; default: 0;
* Reserved
*/
uint32_t lact_rtc_step_len:26;
uint32_t lact_rtc_step_len: 26;
};
uint32_t val;
} timg_lactrtc_reg_t;
@@ -498,7 +498,7 @@ typedef union {
/** lact_lo : RO; bitpos: [31:0]; default: 0;
* Reserved
*/
uint32_t lact_lo:32;
uint32_t lact_lo: 32;
};
uint32_t val;
} timg_lactlo_reg_t;
@@ -511,7 +511,7 @@ typedef union {
/** lact_hi : RO; bitpos: [31:0]; default: 0;
* Reserved
*/
uint32_t lact_hi:32;
uint32_t lact_hi: 32;
};
uint32_t val;
} timg_lacthi_reg_t;
@@ -524,7 +524,7 @@ typedef union {
/** lact_update : WO; bitpos: [31:0]; default: 0;
* Reserved
*/
uint32_t lact_update:32;
uint32_t lact_update: 32;
};
uint32_t val;
} timg_lactupdate_reg_t;
@@ -537,7 +537,7 @@ typedef union {
/** lact_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Reserved
*/
uint32_t lact_alarm_lo:32;
uint32_t lact_alarm_lo: 32;
};
uint32_t val;
} timg_lactalarmlo_reg_t;
@@ -550,7 +550,7 @@ typedef union {
/** lact_alarm_hi : R/W; bitpos: [31:0]; default: 0;
* Reserved
*/
uint32_t lact_alarm_hi:32;
uint32_t lact_alarm_hi: 32;
};
uint32_t val;
} timg_lactalarmhi_reg_t;
@@ -563,7 +563,7 @@ typedef union {
/** lact_load_lo : R/W; bitpos: [31:0]; default: 0;
* Reserved
*/
uint32_t lact_load_lo:32;
uint32_t lact_load_lo: 32;
};
uint32_t val;
} timg_lactloadlo_reg_t;
@@ -576,7 +576,7 @@ typedef union {
/** lact_load_hi : R/W; bitpos: [31:0]; default: 0;
* Reserved
*/
uint32_t lact_load_hi:32;
uint32_t lact_load_hi: 32;
};
uint32_t val;
} timg_lactloadhi_reg_t;
@@ -589,7 +589,7 @@ typedef union {
/** lact_load : WO; bitpos: [31:0]; default: 0;
* Reserved
*/
uint32_t lact_load:32;
uint32_t lact_load: 32;
};
uint32_t val;
} timg_lactload_reg_t;
@@ -601,23 +601,23 @@ typedef union {
*/
typedef union {
struct {
/** tx_int_ena : R/W; bitpos: [0]; default: 0;
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T0_INT interrupt.
*/
uint32_t tx_int_ena:1;
uint32_t t0_int_ena: 1;
/** t1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_T1_INT interrupt.
*/
uint32_t t1_int_ena:1;
uint32_t t1_int_ena: 1;
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t wdt_int_ena: 1;
/** lact_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the TIMG_LACT_INT interrupt.
*/
uint32_t lact_int_ena:1;
uint32_t reserved_4:28;
uint32_t lact_int_ena: 1;
uint32_t reserved_4: 28;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
@@ -630,20 +630,20 @@ typedef union {
/** t0_int_raw : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_raw:1;
uint32_t t0_int_raw: 1;
/** t1_int_raw : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_T1_INT interrupt.
*/
uint32_t t1_int_raw:1;
uint32_t t1_int_raw: 1;
/** wdt_int_raw : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t wdt_int_raw: 1;
/** lact_int_raw : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the TIMG_LACT_INT interrupt.
*/
uint32_t lact_int_raw:1;
uint32_t reserved_4:28;
uint32_t lact_int_raw: 1;
uint32_t reserved_4: 28;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
@@ -656,20 +656,20 @@ typedef union {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_st:1;
uint32_t t0_int_st: 1;
/** t1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_T1_INT interrupt.
*/
uint32_t t1_int_st:1;
uint32_t t1_int_st: 1;
/** wdt_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t wdt_int_st: 1;
/** lact_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the TIMG_LACT_INT interrupt.
*/
uint32_t lact_int_st:1;
uint32_t reserved_4:28;
uint32_t lact_int_st: 1;
uint32_t reserved_4: 28;
};
uint32_t val;
} timg_int_st_timers_reg_t;
@@ -682,20 +682,20 @@ typedef union {
/** t0_int_clr : WO; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T0_INT interrupt.
*/
uint32_t t0_int_clr:1;
uint32_t t0_int_clr: 1;
/** t1_int_clr : WO; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_T1_INT interrupt.
*/
uint32_t t1_int_clr:1;
uint32_t t1_int_clr: 1;
/** wdt_int_clr : WO; bitpos: [2]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t wdt_int_clr: 1;
/** lact_int_clr : WO; bitpos: [3]; default: 0;
* Set this bit to clear the TIMG_LACT_INT interrupt.
*/
uint32_t lact_int_clr:1;
uint32_t reserved_4:28;
uint32_t lact_int_clr: 1;
uint32_t reserved_4: 28;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
@@ -710,8 +710,8 @@ typedef union {
/** timers_date : R/W; bitpos: [27:0]; default: 26243681;
* Version control register.
*/
uint32_t timers_date:28;
uint32_t reserved_28:4;
uint32_t timers_date: 28;
uint32_t reserved_28: 4;
};
uint32_t val;
} timg_timers_date_reg_t;
@@ -723,12 +723,12 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:31;
uint32_t reserved_0: 31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
uint32_t clk_en:1;
uint32_t clk_en: 1;
};
uint32_t val;
} timg_regclk_reg_t;
@@ -745,7 +745,7 @@ typedef struct {
volatile timg_txload_reg_t load;
} timg_hwtimer_reg_t;
typedef struct {
typedef struct timg_dev_t {
volatile timg_hwtimer_reg_t hw_timer[2];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;