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feat(spi_master): add test clock src and config validation
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@@ -152,7 +152,7 @@ We have two bits to control the interrupt:
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#endif
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static const char *SPI_TAG = "spi_master";
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#define SPI_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE_ISR(a, ret_val, SPI_TAG, str)
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#define SPI_CHECK(a, str, ret_val, ...) ESP_RETURN_ON_FALSE_ISR(a, ret_val, SPI_TAG, str, ##__VA_ARGS__)
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typedef struct spi_device_t spi_device_t;
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@@ -421,7 +421,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
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if (dev_config->clock_source) {
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clk_src = dev_config->clock_source;
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}
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esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
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esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz);
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#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
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SPI_CHECK((dev_config->clock_speed_hz > 0) && (dev_config->clock_speed_hz <= MIN(clock_source_hz / 2, (80 * 1000000))), "invalid sclk speed", ESP_ERR_INVALID_ARG);
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