diff --git a/components/soc/esp32s3/include/soc/apb_ctrl_reg.h b/components/soc/esp32s3/include/soc/apb_ctrl_reg.h index 0c3e7e0cd8..a5b91fe6b4 100644 --- a/components/soc/esp32s3/include/soc/apb_ctrl_reg.h +++ b/components/soc/esp32s3/include/soc/apb_ctrl_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,536 +11,645 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_APB_CTRL_REG_H_ +#define _SOC_APB_CTRL_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000) +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) /* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_RST_TICK_CNT (BIT(12)) -#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) -#define APB_CTRL_RST_TICK_CNT_V 0x1 -#define APB_CTRL_RST_TICK_CNT_S 12 +/*description: .*/ +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_V 0x1 +#define APB_CTRL_RST_TICK_CNT_S 12 /* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_CLK_EN (BIT(11)) -#define APB_CTRL_CLK_EN_M (BIT(11)) -#define APB_CTRL_CLK_EN_V 0x1 -#define APB_CTRL_CLK_EN_S 11 +/*description: .*/ +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (BIT(11)) +#define APB_CTRL_CLK_EN_V 0x1 +#define APB_CTRL_CLK_EN_S 11 /* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_CLK_320M_EN (BIT(10)) -#define APB_CTRL_CLK_320M_EN_M (BIT(10)) -#define APB_CTRL_CLK_320M_EN_V 0x1 -#define APB_CTRL_CLK_320M_EN_S 10 +/*description: .*/ +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (BIT(10)) +#define APB_CTRL_CLK_320M_EN_V 0x1 +#define APB_CTRL_CLK_320M_EN_S 10 /* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ -/*description: */ -#define APB_CTRL_PRE_DIV_CNT 0x000003FF -#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << (APB_CTRL_PRE_DIV_CNT_S)) -#define APB_CTRL_PRE_DIV_CNT_V 0x3FF -#define APB_CTRL_PRE_DIV_CNT_S 0 +/*description: .*/ +#define APB_CTRL_PRE_DIV_CNT 0x000003FF +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3FF +#define APB_CTRL_PRE_DIV_CNT_S 0 -#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004) +#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) /* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: */ -#define APB_CTRL_TICK_ENABLE (BIT(16)) -#define APB_CTRL_TICK_ENABLE_M (BIT(16)) -#define APB_CTRL_TICK_ENABLE_V 0x1 -#define APB_CTRL_TICK_ENABLE_S 16 +/*description: .*/ +#define APB_CTRL_TICK_ENABLE (BIT(16)) +#define APB_CTRL_TICK_ENABLE_M (BIT(16)) +#define APB_CTRL_TICK_ENABLE_V 0x1 +#define APB_CTRL_TICK_ENABLE_S 16 /* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ -/*description: */ -#define APB_CTRL_CK8M_TICK_NUM 0x000000FF -#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V) << (APB_CTRL_CK8M_TICK_NUM_S)) -#define APB_CTRL_CK8M_TICK_NUM_V 0xFF -#define APB_CTRL_CK8M_TICK_NUM_S 8 +/*description: .*/ +#define APB_CTRL_CK8M_TICK_NUM 0x000000FF +#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) +#define APB_CTRL_CK8M_TICK_NUM_V 0xFF +#define APB_CTRL_CK8M_TICK_NUM_S 8 /* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ -/*description: */ -#define APB_CTRL_XTAL_TICK_NUM 0x000000FF -#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V) << (APB_CTRL_XTAL_TICK_NUM_S)) -#define APB_CTRL_XTAL_TICK_NUM_V 0xFF -#define APB_CTRL_XTAL_TICK_NUM_S 0 +/*description: .*/ +#define APB_CTRL_XTAL_TICK_NUM 0x000000FF +#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) +#define APB_CTRL_XTAL_TICK_NUM_V 0xFF +#define APB_CTRL_XTAL_TICK_NUM_S 0 -#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008) +#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x8) /* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_XTAL_OEN (BIT(10)) -#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10)) -#define APB_CTRL_CLK_XTAL_OEN_V 0x1 -#define APB_CTRL_CLK_XTAL_OEN_S 10 +/*description: .*/ +#define APB_CTRL_CLK_XTAL_OEN (BIT(10)) +#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10)) +#define APB_CTRL_CLK_XTAL_OEN_V 0x1 +#define APB_CTRL_CLK_XTAL_OEN_S 10 /* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK40X_BB_OEN (BIT(9)) -#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9)) -#define APB_CTRL_CLK40X_BB_OEN_V 0x1 -#define APB_CTRL_CLK40X_BB_OEN_S 9 +/*description: .*/ +#define APB_CTRL_CLK40X_BB_OEN (BIT(9)) +#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9)) +#define APB_CTRL_CLK40X_BB_OEN_V 0x1 +#define APB_CTRL_CLK40X_BB_OEN_S 9 /* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8)) -#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8)) -#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1 -#define APB_CTRL_CLK_DAC_CPU_OEN_S 8 +/*description: .*/ +#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8)) +#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8)) +#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1 +#define APB_CTRL_CLK_DAC_CPU_OEN_S 8 /* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7)) -#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7)) -#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1 -#define APB_CTRL_CLK_ADC_INF_OEN_S 7 +/*description: .*/ +#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7)) +#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7)) +#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1 +#define APB_CTRL_CLK_ADC_INF_OEN_S 7 /* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_320M_OEN (BIT(6)) -#define APB_CTRL_CLK_320M_OEN_M (BIT(6)) -#define APB_CTRL_CLK_320M_OEN_V 0x1 -#define APB_CTRL_CLK_320M_OEN_S 6 +/*description: .*/ +#define APB_CTRL_CLK_320M_OEN (BIT(6)) +#define APB_CTRL_CLK_320M_OEN_M (BIT(6)) +#define APB_CTRL_CLK_320M_OEN_V 0x1 +#define APB_CTRL_CLK_320M_OEN_S 6 /* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK160_OEN (BIT(5)) -#define APB_CTRL_CLK160_OEN_M (BIT(5)) -#define APB_CTRL_CLK160_OEN_V 0x1 -#define APB_CTRL_CLK160_OEN_S 5 +/*description: .*/ +#define APB_CTRL_CLK160_OEN (BIT(5)) +#define APB_CTRL_CLK160_OEN_M (BIT(5)) +#define APB_CTRL_CLK160_OEN_V 0x1 +#define APB_CTRL_CLK160_OEN_S 5 /* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK80_OEN (BIT(4)) -#define APB_CTRL_CLK80_OEN_M (BIT(4)) -#define APB_CTRL_CLK80_OEN_V 0x1 -#define APB_CTRL_CLK80_OEN_S 4 +/*description: .*/ +#define APB_CTRL_CLK80_OEN (BIT(4)) +#define APB_CTRL_CLK80_OEN_M (BIT(4)) +#define APB_CTRL_CLK80_OEN_V 0x1 +#define APB_CTRL_CLK80_OEN_S 4 /* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_BB_OEN (BIT(3)) -#define APB_CTRL_CLK_BB_OEN_M (BIT(3)) -#define APB_CTRL_CLK_BB_OEN_V 0x1 -#define APB_CTRL_CLK_BB_OEN_S 3 +/*description: .*/ +#define APB_CTRL_CLK_BB_OEN (BIT(3)) +#define APB_CTRL_CLK_BB_OEN_M (BIT(3)) +#define APB_CTRL_CLK_BB_OEN_V 0x1 +#define APB_CTRL_CLK_BB_OEN_S 3 /* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK44_OEN (BIT(2)) -#define APB_CTRL_CLK44_OEN_M (BIT(2)) -#define APB_CTRL_CLK44_OEN_V 0x1 -#define APB_CTRL_CLK44_OEN_S 2 +/*description: .*/ +#define APB_CTRL_CLK44_OEN (BIT(2)) +#define APB_CTRL_CLK44_OEN_M (BIT(2)) +#define APB_CTRL_CLK44_OEN_V 0x1 +#define APB_CTRL_CLK44_OEN_S 2 /* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK22_OEN (BIT(1)) -#define APB_CTRL_CLK22_OEN_M (BIT(1)) -#define APB_CTRL_CLK22_OEN_V 0x1 -#define APB_CTRL_CLK22_OEN_S 1 +/*description: .*/ +#define APB_CTRL_CLK22_OEN (BIT(1)) +#define APB_CTRL_CLK22_OEN_M (BIT(1)) +#define APB_CTRL_CLK22_OEN_V 0x1 +#define APB_CTRL_CLK22_OEN_S 1 /* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK20_OEN (BIT(0)) -#define APB_CTRL_CLK20_OEN_M (BIT(0)) -#define APB_CTRL_CLK20_OEN_V 0x1 -#define APB_CTRL_CLK20_OEN_S 0 +/*description: .*/ +#define APB_CTRL_CLK20_OEN (BIT(0)) +#define APB_CTRL_CLK20_OEN_M (BIT(0)) +#define APB_CTRL_CLK20_OEN_V 0x1 +#define APB_CTRL_CLK20_OEN_S 0 -#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C) +#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0xC) /* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF -#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V) << (APB_CTRL_WIFI_BB_CFG_S)) -#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF -#define APB_CTRL_WIFI_BB_CFG_S 0 +/*description: .*/ +#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S)) +#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_S 0 -#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x010) +#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x10) /* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF -#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V) << (APB_CTRL_WIFI_BB_CFG_2_S)) -#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF -#define APB_CTRL_WIFI_BB_CFG_2_S 0 +/*description: .*/ +#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S)) +#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_2_S 0 -#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x014) +#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x14) /* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ -/*description: */ -#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF -#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V) << (APB_CTRL_WIFI_CLK_EN_S)) -#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF -#define APB_CTRL_WIFI_CLK_EN_S 0 +/*description: .*/ +#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF +#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S)) +#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF +#define APB_CTRL_WIFI_CLK_EN_S 0 -#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x018) +#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x18) /* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define APB_CTRL_WIFI_RST 0xFFFFFFFF -#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V) << (APB_CTRL_WIFI_RST_S)) -#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF -#define APB_CTRL_WIFI_RST_S 0 +/*description: .*/ +#define APB_CTRL_WIFI_RST 0xFFFFFFFF +#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S)) +#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF +#define APB_CTRL_WIFI_RST_S 0 -#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C) +#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x1C) /* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define APB_CTRL_PERI_IO_SWAP 0x000000FF -#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V) << (APB_CTRL_PERI_IO_SWAP_S)) -#define APB_CTRL_PERI_IO_SWAP_V 0xFF -#define APB_CTRL_PERI_IO_SWAP_S 0 +/*description: .*/ +#define APB_CTRL_PERI_IO_SWAP 0x000000FF +#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S)) +#define APB_CTRL_PERI_IO_SWAP_V 0xFF +#define APB_CTRL_PERI_IO_SWAP_S 0 -#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x020) +#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x20) /* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0)) -#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0)) -#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1 -#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0 +/*description: .*/ +#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0)) +#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0)) +#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1 +#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0 -#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x024) +#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x24) /* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set 1 to bypass cache writeback request to external memory so - that spi will not check its attribute.*/ -#define APB_CTRL_WRITEBACK_BYPASS (BIT(0)) -#define APB_CTRL_WRITEBACK_BYPASS_M (BIT(0)) -#define APB_CTRL_WRITEBACK_BYPASS_V 0x1 -#define APB_CTRL_WRITEBACK_BYPASS_S 0 +/*description: Set 1 to bypass cache writeback request to external memory so that spi will not +check its attribute..*/ +#define APB_CTRL_WRITEBACK_BYPASS (BIT(0)) +#define APB_CTRL_WRITEBACK_BYPASS_M (BIT(0)) +#define APB_CTRL_WRITEBACK_BYPASS_V 0x1 +#define APB_CTRL_WRITEBACK_BYPASS_S 0 -#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x028) +#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x28) /* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE0_ATTR 0x000001FF -#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V) << (APB_CTRL_FLASH_ACE0_ATTR_S)) -#define APB_CTRL_FLASH_ACE0_ATTR_V 0x1FF -#define APB_CTRL_FLASH_ACE0_ATTR_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE0_ATTR 0x000001FF +#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S)) +#define APB_CTRL_FLASH_ACE0_ATTR_V 0x1FF +#define APB_CTRL_FLASH_ACE0_ATTR_S 0 -#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x02C) +#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x2C) /* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE1_ATTR 0x000001FF -#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V) << (APB_CTRL_FLASH_ACE1_ATTR_S)) -#define APB_CTRL_FLASH_ACE1_ATTR_V 0x1FF -#define APB_CTRL_FLASH_ACE1_ATTR_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE1_ATTR 0x000001FF +#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S)) +#define APB_CTRL_FLASH_ACE1_ATTR_V 0x1FF +#define APB_CTRL_FLASH_ACE1_ATTR_S 0 -#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x030) +#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x30) /* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE2_ATTR 0x000001FF -#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V) << (APB_CTRL_FLASH_ACE2_ATTR_S)) -#define APB_CTRL_FLASH_ACE2_ATTR_V 0x1FF -#define APB_CTRL_FLASH_ACE2_ATTR_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE2_ATTR 0x000001FF +#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S)) +#define APB_CTRL_FLASH_ACE2_ATTR_V 0x1FF +#define APB_CTRL_FLASH_ACE2_ATTR_S 0 -#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x034) +#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x34) /* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE3_ATTR 0x000001FF -#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V) << (APB_CTRL_FLASH_ACE3_ATTR_S)) -#define APB_CTRL_FLASH_ACE3_ATTR_V 0x1FF -#define APB_CTRL_FLASH_ACE3_ATTR_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE3_ATTR 0x000001FF +#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S)) +#define APB_CTRL_FLASH_ACE3_ATTR_V 0x1FF +#define APB_CTRL_FLASH_ACE3_ATTR_S 0 -#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x038) +#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x38) /* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V) << (APB_CTRL_FLASH_ACE0_ADDR_S_S)) -#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0 -#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x03C) +#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x3C) /* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V) << (APB_CTRL_FLASH_ACE1_ADDR_S_S)) -#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0 -#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x040) +#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x40) /* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V) << (APB_CTRL_FLASH_ACE2_ADDR_S_S)) -#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0 -#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x044) +#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x44) /* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V) << (APB_CTRL_FLASH_ACE3_ADDR_S_S)) -#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0 -#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x048) +#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x48) /* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF -#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V) << (APB_CTRL_FLASH_ACE0_SIZE_S)) -#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF -#define APB_CTRL_FLASH_ACE0_SIZE_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF +#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S)) +#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF +#define APB_CTRL_FLASH_ACE0_SIZE_S 0 -#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x04C) +#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x4C) /* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF -#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V) << (APB_CTRL_FLASH_ACE1_SIZE_S)) -#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF -#define APB_CTRL_FLASH_ACE1_SIZE_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF +#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S)) +#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF +#define APB_CTRL_FLASH_ACE1_SIZE_S 0 -#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x050) +#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x50) /* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF -#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V) << (APB_CTRL_FLASH_ACE2_SIZE_S)) -#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF -#define APB_CTRL_FLASH_ACE2_SIZE_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF +#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S)) +#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF +#define APB_CTRL_FLASH_ACE2_SIZE_S 0 -#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x054) +#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x54) /* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: */ -#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF -#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V) << (APB_CTRL_FLASH_ACE3_SIZE_S)) -#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF -#define APB_CTRL_FLASH_ACE3_SIZE_S 0 +/*description: .*/ +#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF +#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S)) +#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF +#define APB_CTRL_FLASH_ACE3_SIZE_S 0 -#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x058) +#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x58) /* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE0_ATTR 0x000001FF -#define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V) << (APB_CTRL_SRAM_ACE0_ATTR_S)) -#define APB_CTRL_SRAM_ACE0_ATTR_V 0x1FF -#define APB_CTRL_SRAM_ACE0_ATTR_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE0_ATTR 0x000001FF +#define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S)) +#define APB_CTRL_SRAM_ACE0_ATTR_V 0x1FF +#define APB_CTRL_SRAM_ACE0_ATTR_S 0 -#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x05C) +#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x5C) /* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE1_ATTR 0x000001FF -#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V) << (APB_CTRL_SRAM_ACE1_ATTR_S)) -#define APB_CTRL_SRAM_ACE1_ATTR_V 0x1FF -#define APB_CTRL_SRAM_ACE1_ATTR_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE1_ATTR 0x000001FF +#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S)) +#define APB_CTRL_SRAM_ACE1_ATTR_V 0x1FF +#define APB_CTRL_SRAM_ACE1_ATTR_S 0 -#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x060) +#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x60) /* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE2_ATTR 0x000001FF -#define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V) << (APB_CTRL_SRAM_ACE2_ATTR_S)) -#define APB_CTRL_SRAM_ACE2_ATTR_V 0x1FF -#define APB_CTRL_SRAM_ACE2_ATTR_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE2_ATTR 0x000001FF +#define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S)) +#define APB_CTRL_SRAM_ACE2_ATTR_V 0x1FF +#define APB_CTRL_SRAM_ACE2_ATTR_S 0 -#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x064) +#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x64) /* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE3_ATTR 0x000001FF -#define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V) << (APB_CTRL_SRAM_ACE3_ATTR_S)) -#define APB_CTRL_SRAM_ACE3_ATTR_V 0x1FF -#define APB_CTRL_SRAM_ACE3_ATTR_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE3_ATTR 0x000001FF +#define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S)) +#define APB_CTRL_SRAM_ACE3_ATTR_V 0x1FF +#define APB_CTRL_SRAM_ACE3_ATTR_S 0 -#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x068) +#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x68) /* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF -#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V) << (APB_CTRL_SRAM_ACE0_ADDR_S_S)) -#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S)) +#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0 -#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x06C) +#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x6C) /* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF -#define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V) << (APB_CTRL_SRAM_ACE1_ADDR_S_S)) -#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S)) +#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0 -#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x070) +#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x70) /* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF -#define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V) << (APB_CTRL_SRAM_ACE2_ADDR_S_S)) -#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S)) +#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0 -#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x074) +#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x74) /* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF -#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V) << (APB_CTRL_SRAM_ACE3_ADDR_S_S)) -#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF -#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S)) +#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0 -#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x078) +#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x78) /* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF -#define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V) << (APB_CTRL_SRAM_ACE0_SIZE_S)) -#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF -#define APB_CTRL_SRAM_ACE0_SIZE_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF +#define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S)) +#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF +#define APB_CTRL_SRAM_ACE0_SIZE_S 0 -#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x07C) +#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x7C) /* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF -#define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V) << (APB_CTRL_SRAM_ACE1_SIZE_S)) -#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF -#define APB_CTRL_SRAM_ACE1_SIZE_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF +#define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S)) +#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF +#define APB_CTRL_SRAM_ACE1_SIZE_S 0 -#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x080) +#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x80) /* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF -#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V) << (APB_CTRL_SRAM_ACE2_SIZE_S)) -#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF -#define APB_CTRL_SRAM_ACE2_SIZE_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF +#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S)) +#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF +#define APB_CTRL_SRAM_ACE2_SIZE_S 0 -#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x084) +#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x84) /* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ -/*description: */ -#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF -#define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V) << (APB_CTRL_SRAM_ACE3_SIZE_S)) -#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF -#define APB_CTRL_SRAM_ACE3_SIZE_S 0 +/*description: .*/ +#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF +#define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S)) +#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF +#define APB_CTRL_SRAM_ACE3_SIZE_S 0 -#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x088) +#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x88) /* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ -/*description: */ -#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F -#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V) << (APB_CTRL_SPI_MEM_REJECT_CDE_S)) -#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F -#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2 +/*description: .*/ +#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F +#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S)) +#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F +#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2 /* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1)) -#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1)) -#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1 -#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1 +/*description: .*/ +#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1 +#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1 /* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0)) -#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0)) -#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1 -#define APB_CTRL_SPI_MEM_REJECT_INT_S 0 +/*description: .*/ +#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1 +#define APB_CTRL_SPI_MEM_REJECT_INT_S 0 -#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x08C) +#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x8C) /* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF -#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V) << (APB_CTRL_SPI_MEM_REJECT_ADDR_S)) -#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF -#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0 +/*description: .*/ +#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S)) +#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0 -#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x090) +#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x90) /* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0)) -#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0)) -#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1 -#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0 +/*description: .*/ +#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0)) +#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0)) +#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1 +#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0 -#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x094) +#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x94) /* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define APB_CTRL_REDCY_ANDOR (BIT(31)) -#define APB_CTRL_REDCY_ANDOR_M (BIT(31)) -#define APB_CTRL_REDCY_ANDOR_V 0x1 -#define APB_CTRL_REDCY_ANDOR_S 31 +/*description: .*/ +#define APB_CTRL_REDCY_ANDOR (BIT(31)) +#define APB_CTRL_REDCY_ANDOR_M (BIT(31)) +#define APB_CTRL_REDCY_ANDOR_V 0x1 +#define APB_CTRL_REDCY_ANDOR_S 31 /* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ -/*description: */ -#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF -#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V) << (APB_CTRL_REDCY_SIG0_S)) -#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF -#define APB_CTRL_REDCY_SIG0_S 0 +/*description: .*/ +#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S)) +#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG0_S 0 -#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x098) +#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x98) /* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define APB_CTRL_REDCY_NANDOR (BIT(31)) -#define APB_CTRL_REDCY_NANDOR_M (BIT(31)) -#define APB_CTRL_REDCY_NANDOR_V 0x1 -#define APB_CTRL_REDCY_NANDOR_S 31 +/*description: .*/ +#define APB_CTRL_REDCY_NANDOR (BIT(31)) +#define APB_CTRL_REDCY_NANDOR_M (BIT(31)) +#define APB_CTRL_REDCY_NANDOR_V 0x1 +#define APB_CTRL_REDCY_NANDOR_S 31 /* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ -/*description: */ -#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF -#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V) << (APB_CTRL_REDCY_SIG1_S)) -#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF -#define APB_CTRL_REDCY_SIG1_S 0 +/*description: .*/ +#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S)) +#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG1_S 0 -#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C) +#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x9C) +/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define APB_CTRL_FREQ_MEM_FORCE_PD (BIT(7)) +#define APB_CTRL_FREQ_MEM_FORCE_PD_M (BIT(7)) +#define APB_CTRL_FREQ_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_FREQ_MEM_FORCE_PD_S 7 +/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: .*/ +#define APB_CTRL_FREQ_MEM_FORCE_PU (BIT(6)) +#define APB_CTRL_FREQ_MEM_FORCE_PU_M (BIT(6)) +#define APB_CTRL_FREQ_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_FREQ_MEM_FORCE_PU_S 6 /* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5)) -#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5)) -#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1 -#define APB_CTRL_DC_MEM_FORCE_PD_S 5 +/*description: .*/ +#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5)) +#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5)) +#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_DC_MEM_FORCE_PD_S 5 /* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4)) -#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4)) -#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1 -#define APB_CTRL_DC_MEM_FORCE_PU_S 4 +/*description: .*/ +#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_DC_MEM_FORCE_PU_S 4 /* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3)) -#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3)) -#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1 -#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3 +/*description: .*/ +#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3)) +#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3 /* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2)) -#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2)) -#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1 -#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2 +/*description: .*/ +#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2 /* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1)) -#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1)) -#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1 -#define APB_CTRL_AGC_MEM_FORCE_PD_S 1 +/*description: .*/ +#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1)) +#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1)) +#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_AGC_MEM_FORCE_PD_S 1 /* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0)) -#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0)) -#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1 -#define APB_CTRL_AGC_MEM_FORCE_PU_S 0 +/*description: .*/ +#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_AGC_MEM_FORCE_PU_S 0 -#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0) +#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xA0) /* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */ -/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. - 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ -#define APB_CTRL_SRAM_PAGE_SIZE 0x00000003 -#define APB_CTRL_SRAM_PAGE_SIZE_M ((APB_CTRL_SRAM_PAGE_SIZE_V) << (APB_CTRL_SRAM_PAGE_SIZE_S)) -#define APB_CTRL_SRAM_PAGE_SIZE_V 0x3 -#define APB_CTRL_SRAM_PAGE_SIZE_S 20 +/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: +1024 bytes. 3: 2048 bytes..*/ +#define APB_CTRL_SRAM_PAGE_SIZE 0x00000003 +#define APB_CTRL_SRAM_PAGE_SIZE_M ((APB_CTRL_SRAM_PAGE_SIZE_V)<<(APB_CTRL_SRAM_PAGE_SIZE_S)) +#define APB_CTRL_SRAM_PAGE_SIZE_V 0x3 +#define APB_CTRL_SRAM_PAGE_SIZE_S 20 /* APB_CTRL_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 - bytes. 2: 1024 bytes. 3: 2048 bytes.*/ -#define APB_CTRL_FLASH_PAGE_SIZE 0x00000003 -#define APB_CTRL_FLASH_PAGE_SIZE_M ((APB_CTRL_FLASH_PAGE_SIZE_V) << (APB_CTRL_FLASH_PAGE_SIZE_S)) -#define APB_CTRL_FLASH_PAGE_SIZE_V 0x3 -#define APB_CTRL_FLASH_PAGE_SIZE_S 18 -/* APB_CTRL_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to enable MSPI interrupt when the error times of - MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/ -#define APB_CTRL_ECC_ERR_INT_EN (BIT(17)) -#define APB_CTRL_ECC_ERR_INT_EN_M (BIT(17)) -#define APB_CTRL_ECC_ERR_INT_EN_V 0x1 -#define APB_CTRL_ECC_ERR_INT_EN_S 17 -/* APB_CTRL_ECC_ERR_INT_NUM : R/W ;bitpos:[16:9] ;default: 8'd10 ; */ -/*description: Set the error times of MSPI ECC read to generate MSPI interrupt.*/ -#define APB_CTRL_ECC_ERR_INT_NUM 0x000000FF -#define APB_CTRL_ECC_ERR_INT_NUM_M ((APB_CTRL_ECC_ERR_INT_NUM_V) << (APB_CTRL_ECC_ERR_INT_NUM_S)) -#define APB_CTRL_ECC_ERR_INT_NUM_V 0xFF -#define APB_CTRL_ECC_ERR_INT_NUM_S 9 -/* APB_CTRL_ECC_ERR_CNT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/ -#define APB_CTRL_ECC_ERR_CNT_CLR (BIT(8)) -#define APB_CTRL_ECC_ERR_CNT_CLR_M (BIT(8)) -#define APB_CTRL_ECC_ERR_CNT_CLR_V 0x1 -#define APB_CTRL_ECC_ERR_CNT_CLR_S 8 -/* APB_CTRL_ECC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */ -/*description: This bits show the error times of MSPI ECC read.*/ -#define APB_CTRL_ECC_ERR_CNT 0x000000FF -#define APB_CTRL_ECC_ERR_CNT_M ((APB_CTRL_ECC_ERR_CNT_V) << (APB_CTRL_ECC_ERR_CNT_S)) -#define APB_CTRL_ECC_ERR_CNT_V 0xFF -#define APB_CTRL_ECC_ERR_CNT_S 0 +/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by +tes. 3: 2048 bytes..*/ +#define APB_CTRL_FLASH_PAGE_SIZE 0x00000003 +#define APB_CTRL_FLASH_PAGE_SIZE_M ((APB_CTRL_FLASH_PAGE_SIZE_V)<<(APB_CTRL_FLASH_PAGE_SIZE_S)) +#define APB_CTRL_FLASH_PAGE_SIZE_V 0x3 +#define APB_CTRL_FLASH_PAGE_SIZE_S 18 -#define APB_CTRL_SPI_MEM_ECC_ERR_AADR_REG (DR_REG_APB_CTRL_BASE + 0x0A4) -/* APB_CTRL_ECC_ERR_ADDR : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: This bits show the latest MSPI ECC error address.*/ -#define APB_CTRL_ECC_ERR_ADDR 0xFFFFFFFF -#define APB_CTRL_ECC_ERR_ADDR_M ((APB_CTRL_ECC_ERR_ADDR_V) << (APB_CTRL_ECC_ERR_ADDR_S)) -#define APB_CTRL_ECC_ERR_ADDR_V 0xFFFFFFFF -#define APB_CTRL_ECC_ERR_ADDR_S 0 +#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0xA8) +/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ +/*description: .*/ +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x000007FF +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S)) +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0x7FF +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3 +/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: .*/ +#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000007 +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S)) +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x7 +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0 + +#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0xAC) +/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */ +/*description: .*/ +#define APB_CTRL_SRAM_POWER_DOWN 0x000007FF +#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S)) +#define APB_CTRL_SRAM_POWER_DOWN_V 0x7FF +#define APB_CTRL_SRAM_POWER_DOWN_S 3 +/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: .*/ +#define APB_CTRL_ROM_POWER_DOWN 0x00000007 +#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S)) +#define APB_CTRL_ROM_POWER_DOWN_V 0x7 +#define APB_CTRL_ROM_POWER_DOWN_S 0 + +#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0xB0) +/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ +/*description: .*/ +#define APB_CTRL_SRAM_POWER_UP 0x000007FF +#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S)) +#define APB_CTRL_SRAM_POWER_UP_V 0x7FF +#define APB_CTRL_SRAM_POWER_UP_S 3 +/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: .*/ +#define APB_CTRL_ROM_POWER_UP 0x00000007 +#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S)) +#define APB_CTRL_ROM_POWER_UP_V 0x7 +#define APB_CTRL_ROM_POWER_UP_S 0 + +#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xB4) +/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27)) +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27)) +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1 +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27 +/* APB_CTRL_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: .*/ +#define APB_CTRL_RETENTION_CPU_LINK_ADDR 0x07FFFFFF +#define APB_CTRL_RETENTION_CPU_LINK_ADDR_M ((APB_CTRL_RETENTION_CPU_LINK_ADDR_V)<<(APB_CTRL_RETENTION_CPU_LINK_ADDR_S)) +#define APB_CTRL_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF +#define APB_CTRL_RETENTION_CPU_LINK_ADDR_S 0 + +#define APB_CTRL_RETENTION_CTRL1_REG (DR_REG_APB_CTRL_BASE + 0xB8) +/* APB_CTRL_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: .*/ +#define APB_CTRL_RETENTION_TAG_LINK_ADDR 0x07FFFFFF +#define APB_CTRL_RETENTION_TAG_LINK_ADDR_M ((APB_CTRL_RETENTION_TAG_LINK_ADDR_V)<<(APB_CTRL_RETENTION_TAG_LINK_ADDR_S)) +#define APB_CTRL_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF +#define APB_CTRL_RETENTION_TAG_LINK_ADDR_S 0 + +#define APB_CTRL_RETENTION_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0xBC) +/* APB_CTRL_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define APB_CTRL_RET_ICACHE_ENABLE (BIT(31)) +#define APB_CTRL_RET_ICACHE_ENABLE_M (BIT(31)) +#define APB_CTRL_RET_ICACHE_ENABLE_V 0x1 +#define APB_CTRL_RET_ICACHE_ENABLE_S 31 +/* APB_CTRL_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */ +/*description: .*/ +#define APB_CTRL_RET_ICACHE_START_POINT 0x000000FF +#define APB_CTRL_RET_ICACHE_START_POINT_M ((APB_CTRL_RET_ICACHE_START_POINT_V)<<(APB_CTRL_RET_ICACHE_START_POINT_S)) +#define APB_CTRL_RET_ICACHE_START_POINT_V 0xFF +#define APB_CTRL_RET_ICACHE_START_POINT_S 22 +/* APB_CTRL_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */ +/*description: .*/ +#define APB_CTRL_RET_ICACHE_VLD_SIZE 0x000000FF +#define APB_CTRL_RET_ICACHE_VLD_SIZE_M ((APB_CTRL_RET_ICACHE_VLD_SIZE_V)<<(APB_CTRL_RET_ICACHE_VLD_SIZE_S)) +#define APB_CTRL_RET_ICACHE_VLD_SIZE_V 0xFF +#define APB_CTRL_RET_ICACHE_VLD_SIZE_S 13 +/* APB_CTRL_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */ +/*description: .*/ +#define APB_CTRL_RET_ICACHE_SIZE 0x000000FF +#define APB_CTRL_RET_ICACHE_SIZE_M ((APB_CTRL_RET_ICACHE_SIZE_V)<<(APB_CTRL_RET_ICACHE_SIZE_S)) +#define APB_CTRL_RET_ICACHE_SIZE_V 0xFF +#define APB_CTRL_RET_ICACHE_SIZE_S 4 + +#define APB_CTRL_RETENTION_CTRL3_REG (DR_REG_APB_CTRL_BASE + 0xC0) +/* APB_CTRL_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define APB_CTRL_RET_DCACHE_ENABLE (BIT(31)) +#define APB_CTRL_RET_DCACHE_ENABLE_M (BIT(31)) +#define APB_CTRL_RET_DCACHE_ENABLE_V 0x1 +#define APB_CTRL_RET_DCACHE_ENABLE_S 31 +/* APB_CTRL_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */ +/*description: .*/ +#define APB_CTRL_RET_DCACHE_START_POINT 0x000001FF +#define APB_CTRL_RET_DCACHE_START_POINT_M ((APB_CTRL_RET_DCACHE_START_POINT_V)<<(APB_CTRL_RET_DCACHE_START_POINT_S)) +#define APB_CTRL_RET_DCACHE_START_POINT_V 0x1FF +#define APB_CTRL_RET_DCACHE_START_POINT_S 22 +/* APB_CTRL_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */ +/*description: .*/ +#define APB_CTRL_RET_DCACHE_VLD_SIZE 0x000001FF +#define APB_CTRL_RET_DCACHE_VLD_SIZE_M ((APB_CTRL_RET_DCACHE_VLD_SIZE_V)<<(APB_CTRL_RET_DCACHE_VLD_SIZE_S)) +#define APB_CTRL_RET_DCACHE_VLD_SIZE_V 0x1FF +#define APB_CTRL_RET_DCACHE_VLD_SIZE_S 13 +/* APB_CTRL_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */ +/*description: .*/ +#define APB_CTRL_RET_DCACHE_SIZE 0x000001FF +#define APB_CTRL_RET_DCACHE_SIZE_M ((APB_CTRL_RET_DCACHE_SIZE_V)<<(APB_CTRL_RET_DCACHE_SIZE_S)) +#define APB_CTRL_RET_DCACHE_SIZE_V 0x1FF +#define APB_CTRL_RET_DCACHE_SIZE_S 4 + +#define APB_CTRL_RETENTION_CTRL4_REG (DR_REG_APB_CTRL_BASE + 0xC4) +/* APB_CTRL_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */ +/*description: .*/ +#define APB_CTRL_RETENTION_INV_CFG 0xFFFFFFFF +#define APB_CTRL_RETENTION_INV_CFG_M ((APB_CTRL_RETENTION_INV_CFG_V)<<(APB_CTRL_RETENTION_INV_CFG_S)) +#define APB_CTRL_RETENTION_INV_CFG_V 0xFFFFFFFF +#define APB_CTRL_RETENTION_INV_CFG_S 0 + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC) +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */ +/*description: Version control.*/ +#define APB_CTRL_DATE 0xFFFFFFFF +#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) +#define APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_CTRL_DATE_S 0 -#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC) -/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h20032301 ; */ -/*description: Version control*/ -#define APB_CTRL_DATE 0xFFFFFFFF -#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V) << (APB_CTRL_DATE_S)) -#define APB_CTRL_DATE_V 0xFFFFFFFF -#define APB_CTRL_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_APB_CTRL_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/apb_ctrl_struct.h b/components/soc/esp32s3/include/soc/apb_ctrl_struct.h index 6d2cb0b7e9..34e8dd5d46 100644 --- a/components/soc/esp32s3/include/soc/apb_ctrl_struct.h +++ b/components/soc/esp32s3/include/soc/apb_ctrl_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,14 +11,12 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_APB_CTRL_STRUCT_H_ +#define _SOC_APB_CTRL_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif -#include - typedef volatile struct { union { struct { @@ -56,10 +54,10 @@ typedef volatile struct { }; uint32_t val; } clk_out_en; - uint32_t wifi_bb_cfg; /**/ - uint32_t wifi_bb_cfg_2; /**/ - uint32_t wifi_clk_en; /**/ - uint32_t wifi_rst_en; /**/ + uint32_t wifi_bb_cfg; /**/ + uint32_t wifi_bb_cfg_2; /**/ + uint32_t wifi_clk_en; /**/ + uint32_t wifi_rst_en; /**/ union { struct { uint32_t peri_io_swap: 8; @@ -76,7 +74,7 @@ typedef volatile struct { } ext_mem_pms_lock; union { struct { - uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/ + uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/ uint32_t reserved1: 31; }; uint32_t val; @@ -109,34 +107,34 @@ typedef volatile struct { }; uint32_t val; } flash_ace3_attr; - uint32_t flash_ace0_addr; /**/ - uint32_t flash_ace1_addr; /**/ - uint32_t flash_ace2_addr; /**/ - uint32_t flash_ace3_addr; /**/ + uint32_t flash_ace0_addr; /**/ + uint32_t flash_ace1_addr; /**/ + uint32_t flash_ace2_addr; /**/ + uint32_t flash_ace3_addr; /**/ union { struct { - uint32_t flash_ace0_size: 16; + uint32_t flash_ace0_size:16; uint32_t reserved16: 16; }; uint32_t val; } flash_ace0_size; union { struct { - uint32_t flash_ace1_size: 16; + uint32_t flash_ace1_size:16; uint32_t reserved16: 16; }; uint32_t val; } flash_ace1_size; union { struct { - uint32_t flash_ace2_size: 16; + uint32_t flash_ace2_size:16; uint32_t reserved16: 16; }; uint32_t val; } flash_ace2_size; union { struct { - uint32_t flash_ace3_size: 16; + uint32_t flash_ace3_size:16; uint32_t reserved16: 16; }; uint32_t val; @@ -169,34 +167,34 @@ typedef volatile struct { }; uint32_t val; } sram_ace3_attr; - uint32_t sram_ace0_addr; /**/ - uint32_t sram_ace1_addr; /**/ - uint32_t sram_ace2_addr; /**/ - uint32_t sram_ace3_addr; /**/ + uint32_t sram_ace0_addr; /**/ + uint32_t sram_ace1_addr; /**/ + uint32_t sram_ace2_addr; /**/ + uint32_t sram_ace3_addr; /**/ union { struct { - uint32_t sram_ace0_size: 16; + uint32_t sram_ace0_size:16; uint32_t reserved16: 16; }; uint32_t val; } sram_ace0_size; union { struct { - uint32_t sram_ace1_size: 16; + uint32_t sram_ace1_size:16; uint32_t reserved16: 16; }; uint32_t val; } sram_ace1_size; union { struct { - uint32_t sram_ace2_size: 16; + uint32_t sram_ace2_size:16; uint32_t reserved16: 16; }; uint32_t val; } sram_ace2_size; union { struct { - uint32_t sram_ace3_size: 16; + uint32_t sram_ace3_size:16; uint32_t reserved16: 16; }; uint32_t val; @@ -210,7 +208,7 @@ typedef volatile struct { }; uint32_t val; } spi_mem_pms_ctrl; - uint32_t spi_mem_reject_addr; /**/ + uint32_t spi_mem_reject_addr; /**/ union { struct { uint32_t sdio_win_access_en: 1; @@ -240,31 +238,85 @@ typedef volatile struct { uint32_t pbus_mem_force_pd: 1; uint32_t dc_mem_force_pu: 1; uint32_t dc_mem_force_pd: 1; - uint32_t reserved6: 26; + uint32_t freq_mem_force_pu: 1; + uint32_t freq_mem_force_pd: 1; + uint32_t reserved8: 24; }; uint32_t val; } front_end_mem_pd; union { struct { - uint32_t ecc_err: 8; /*This bits show the error times of MSPI ECC read.*/ - uint32_t ecc_err_clr: 1; /*Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/ - uint32_t ecc_err_int_num: 8; /*Set the error times of MSPI ECC read to generate MSPI interrupt.*/ - uint32_t ecc_err_int_en: 1; /*Set this bit to enable MSPI interrupt when the error times of MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/ - uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ - uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t reserved0: 18; /*reserved*/ + uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reserved22: 10; /*reserved*/ }; uint32_t val; } spi_mem_ecc_ctrl; - uint32_t spi_mem_ecc_err_aadr; /*This bits show the latest MSPI ECC error address.*/ - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; + uint32_t reserved_a4; + union { + struct { + uint32_t rom_clkgate_force_on: 3; + uint32_t sram_clkgate_force_on:11; + uint32_t reserved14: 18; + }; + uint32_t val; + } clkgate_force_on; + union { + struct { + uint32_t rom_power_down: 3; + uint32_t sram_power_down:11; + uint32_t reserved14: 18; + }; + uint32_t val; + } mem_power_down; + union { + struct { + uint32_t rom_power_up: 3; + uint32_t sram_power_up:11; + uint32_t reserved14: 18; + }; + uint32_t val; + } mem_power_up; + union { + struct { + uint32_t retention_cpu_link_addr:27; + uint32_t nobypass_cpu_iso_rst: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } retention_ctrl; + union { + struct { + uint32_t retention_tag_link_addr:27; + uint32_t reserved27: 5; + }; + uint32_t val; + } retention_ctrl1; + union { + struct { + uint32_t reserved0: 4; + uint32_t ret_icache_size: 8; + uint32_t reserved12: 1; + uint32_t ret_icache_vld_size: 8; + uint32_t reserved21: 1; + uint32_t ret_icache_start_point: 8; + uint32_t reserved30: 1; + uint32_t ret_icache_enable: 1; + }; + uint32_t val; + } retention_ctrl2; + union { + struct { + uint32_t reserved0: 4; + uint32_t ret_dcache_size: 9; + uint32_t ret_dcache_vld_size: 9; + uint32_t ret_dcache_start_point: 9; + uint32_t ret_dcache_enable: 1; + }; + uint32_t val; + } retention_ctrl3; + uint32_t retention_ctrl4; uint32_t reserved_c8; uint32_t reserved_cc; uint32_t reserved_d0; @@ -470,11 +522,11 @@ typedef volatile struct { uint32_t reserved_3f0; uint32_t reserved_3f4; uint32_t reserved_3f8; - uint32_t date; /*Version control*/ + uint32_t date; /*Version control*/ } apb_ctrl_dev_t; - extern apb_ctrl_dev_t APB_CTRL; - #ifdef __cplusplus } #endif + +#endif /* _SOC_APB_CTRL_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/apb_saradc_reg.h b/components/soc/esp32s3/include/soc/apb_saradc_reg.h index 4ffc30fe44..e33a298487 100644 --- a/components/soc/esp32s3/include/soc/apb_saradc_reg.h +++ b/components/soc/esp32s3/include/soc/apb_saradc_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,688 +11,636 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_APB_SARADC_REG_H_ +#define _SOC_APB_SARADC_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) /* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ -/*description: wait arbit signal stable after sar_done*/ -#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 -#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V) << (APB_SARADC_WAIT_ARB_CYCLE_S)) -#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 -#define APB_SARADC_WAIT_ARB_CYCLE_S 30 +/*description: wait arbit signal stable after sar_done.*/ +#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 +#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S)) +#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 +#define APB_SARADC_WAIT_ARB_CYCLE_S 30 /* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ -/*description: force option to xpd sar blocks*/ -#define APB_SARADC_XPD_SAR_FORCE 0x00000003 -#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V) << (APB_SARADC_XPD_SAR_FORCE_S)) -#define APB_SARADC_XPD_SAR_FORCE_V 0x3 -#define APB_SARADC_XPD_SAR_FORCE_S 27 +/*description: force option to xpd sar blocks.*/ +#define APB_SARADC_XPD_SAR_FORCE 0x00000003 +#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S)) +#define APB_SARADC_XPD_SAR_FORCE_V 0x3 +#define APB_SARADC_XPD_SAR_FORCE_S 27 /* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data - is from GPIO matrix*/ -#define APB_SARADC_DATA_TO_I2S (BIT(26)) -#define APB_SARADC_DATA_TO_I2S_M (BIT(26)) -#define APB_SARADC_DATA_TO_I2S_V 0x1 -#define APB_SARADC_DATA_TO_I2S_S 26 +/*description: 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matr +ix.*/ +#define APB_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_SARADC_DATA_TO_I2S_M (BIT(26)) +#define APB_SARADC_DATA_TO_I2S_V 0x1 +#define APB_SARADC_DATA_TO_I2S_S 26 /* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data - in this case the resolution should not be larger than 11 bits.*/ -#define APB_SARADC_DATA_SAR_SEL (BIT(25)) -#define APB_SARADC_DATA_SAR_SEL_M (BIT(25)) -#define APB_SARADC_DATA_SAR_SEL_V 0x1 -#define APB_SARADC_DATA_SAR_SEL_S 25 +/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the +resolution should not be larger than 11 bits..*/ +#define APB_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_SARADC_DATA_SAR_SEL_M (BIT(25)) +#define APB_SARADC_DATA_SAR_SEL_V 0x1 +#define APB_SARADC_DATA_SAR_SEL_S 25 /* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ -#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) -#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) -#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1 -#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24 +/*description: clear the pointer of pattern table for DIG ADC2 CTRL.*/ +#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) +#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1 +#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24 /* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ -#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) -#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) -#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1 -#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23 +/*description: clear the pointer of pattern table for DIG ADC1 CTRL.*/ +#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) +#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1 +#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23 /* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ -/*description: 0 ~ 15 means length 1 ~ 16*/ -#define APB_SARADC_SAR2_PATT_LEN 0x0000000F -#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V) << (APB_SARADC_SAR2_PATT_LEN_S)) -#define APB_SARADC_SAR2_PATT_LEN_V 0xF -#define APB_SARADC_SAR2_PATT_LEN_S 19 +/*description: 0 ~ 15 means length 1 ~ 16.*/ +#define APB_SARADC_SAR2_PATT_LEN 0x0000000F +#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S)) +#define APB_SARADC_SAR2_PATT_LEN_V 0xF +#define APB_SARADC_SAR2_PATT_LEN_S 19 /* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ -/*description: 0 ~ 15 means length 1 ~ 16*/ -#define APB_SARADC_SAR1_PATT_LEN 0x0000000F -#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V) << (APB_SARADC_SAR1_PATT_LEN_S)) -#define APB_SARADC_SAR1_PATT_LEN_V 0xF -#define APB_SARADC_SAR1_PATT_LEN_S 15 +/*description: 0 ~ 15 means length 1 ~ 16.*/ +#define APB_SARADC_SAR1_PATT_LEN 0x0000000F +#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S)) +#define APB_SARADC_SAR1_PATT_LEN_V 0xF +#define APB_SARADC_SAR1_PATT_LEN_S 15 /* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ -/*description: SAR clock divider*/ -#define APB_SARADC_SAR_CLK_DIV 0x000000FF -#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V) << (APB_SARADC_SAR_CLK_DIV_S)) -#define APB_SARADC_SAR_CLK_DIV_V 0xFF -#define APB_SARADC_SAR_CLK_DIV_S 7 +/*description: SAR clock divider.*/ +#define APB_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S)) +#define APB_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_SARADC_SAR_CLK_DIV_S 7 /* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define APB_SARADC_SAR_CLK_GATED (BIT(6)) -#define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) -#define APB_SARADC_SAR_CLK_GATED_V 0x1 -#define APB_SARADC_SAR_CLK_GATED_S 6 +/*description: .*/ +#define APB_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_SARADC_SAR_CLK_GATED_S 6 /* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ -#define APB_SARADC_SAR_SEL (BIT(5)) -#define APB_SARADC_SAR_SEL_M (BIT(5)) -#define APB_SARADC_SAR_SEL_V 0x1 -#define APB_SARADC_SAR_SEL_S 5 +/*description: 0: SAR1, 1: SAR2, only work for single SAR mode.*/ +#define APB_SARADC_SAR_SEL (BIT(5)) +#define APB_SARADC_SAR_SEL_M (BIT(5)) +#define APB_SARADC_SAR_SEL_V 0x1 +#define APB_SARADC_SAR_SEL_S 5 /* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ -/*description: 0: single mode 1: double mode 2: alternate mode*/ -#define APB_SARADC_WORK_MODE 0x00000003 -#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V) << (APB_SARADC_WORK_MODE_S)) -#define APB_SARADC_WORK_MODE_V 0x3 -#define APB_SARADC_WORK_MODE_S 3 +/*description: 0: single mode, 1: double mode, 2: alternate mode.*/ +#define APB_SARADC_WORK_MODE 0x00000003 +#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S)) +#define APB_SARADC_WORK_MODE_V 0x3 +#define APB_SARADC_WORK_MODE_S 3 /* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_START (BIT(1)) -#define APB_SARADC_START_M (BIT(1)) -#define APB_SARADC_START_V 0x1 -#define APB_SARADC_START_S 1 +/*description: .*/ +#define APB_SARADC_START (BIT(1)) +#define APB_SARADC_START_M (BIT(1)) +#define APB_SARADC_START_V 0x1 +#define APB_SARADC_START_S 1 /* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_START_FORCE (BIT(0)) -#define APB_SARADC_START_FORCE_M (BIT(0)) -#define APB_SARADC_START_FORCE_V 0x1 -#define APB_SARADC_START_FORCE_S 0 +/*description: .*/ +#define APB_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_START_FORCE_M (BIT(0)) +#define APB_SARADC_START_FORCE_V 0x1 +#define APB_SARADC_START_FORCE_S 0 -#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) /* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: to enable saradc timer trigger*/ -#define APB_SARADC_TIMER_EN (BIT(24)) -#define APB_SARADC_TIMER_EN_M (BIT(24)) -#define APB_SARADC_TIMER_EN_V 0x1 -#define APB_SARADC_TIMER_EN_S 24 +/*description: to enable saradc timer trigger.*/ +#define APB_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_TIMER_EN_M (BIT(24)) +#define APB_SARADC_TIMER_EN_V 0x1 +#define APB_SARADC_TIMER_EN_S 24 /* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ -/*description: to set saradc timer target*/ -#define APB_SARADC_TIMER_TARGET 0x00000FFF -#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V) << (APB_SARADC_TIMER_TARGET_S)) -#define APB_SARADC_TIMER_TARGET_V 0xFFF -#define APB_SARADC_TIMER_TARGET_S 12 +/*description: to set saradc timer target.*/ +#define APB_SARADC_TIMER_TARGET 0x00000FFF +#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S)) +#define APB_SARADC_TIMER_TARGET_V 0xFFF +#define APB_SARADC_TIMER_TARGET_S 12 /* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: 1: select saradc timer 0: i2s_ws trigger*/ -#define APB_SARADC_TIMER_SEL (BIT(11)) -#define APB_SARADC_TIMER_SEL_M (BIT(11)) -#define APB_SARADC_TIMER_SEL_V 0x1 -#define APB_SARADC_TIMER_SEL_S 11 +/*description: 1: select saradc timer 0: i2s_ws trigger.*/ +#define APB_SARADC_TIMER_SEL (BIT(11)) +#define APB_SARADC_TIMER_SEL_M (BIT(11)) +#define APB_SARADC_TIMER_SEL_V 0x1 +#define APB_SARADC_TIMER_SEL_S 11 /* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ -#define APB_SARADC_SAR2_INV (BIT(10)) -#define APB_SARADC_SAR2_INV_M (BIT(10)) -#define APB_SARADC_SAR2_INV_V 0x1 -#define APB_SARADC_SAR2_INV_S 10 +/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/ +#define APB_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SAR2_INV_M (BIT(10)) +#define APB_SARADC_SAR2_INV_V 0x1 +#define APB_SARADC_SAR2_INV_S 10 /* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ -#define APB_SARADC_SAR1_INV (BIT(9)) -#define APB_SARADC_SAR1_INV_M (BIT(9)) -#define APB_SARADC_SAR1_INV_V 0x1 -#define APB_SARADC_SAR1_INV_S 9 +/*description: 1: data to DIG ADC1 CTRL is inverted, otherwise not.*/ +#define APB_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SAR1_INV_M (BIT(9)) +#define APB_SARADC_SAR1_INV_V 0x1 +#define APB_SARADC_SAR1_INV_S 9 /* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ -/*description: max conversion number*/ -#define APB_SARADC_MAX_MEAS_NUM 0x000000FF -#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V) << (APB_SARADC_MAX_MEAS_NUM_S)) -#define APB_SARADC_MAX_MEAS_NUM_V 0xFF -#define APB_SARADC_MAX_MEAS_NUM_S 1 +/*description: max conversion number.*/ +#define APB_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S)) +#define APB_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_SARADC_MAX_MEAS_NUM_S 1 /* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) -#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) -#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 -#define APB_SARADC_MEAS_NUM_LIMIT_S 0 +/*description: .*/ +#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_SARADC_MEAS_NUM_LIMIT_S 0 -#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008) +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) /* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define APB_SARADC_FILTER_FACTOR0 0x00000007 -#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V) << (APB_SARADC_FILTER_FACTOR0_S)) -#define APB_SARADC_FILTER_FACTOR0_V 0x7 -#define APB_SARADC_FILTER_FACTOR0_S 29 +/*description: .*/ +#define APB_SARADC_FILTER_FACTOR0 0x00000007 +#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S)) +#define APB_SARADC_FILTER_FACTOR0_V 0x7 +#define APB_SARADC_FILTER_FACTOR0_S 29 /* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ -/*description: */ -#define APB_SARADC_FILTER_FACTOR1 0x00000007 -#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V) << (APB_SARADC_FILTER_FACTOR1_S)) -#define APB_SARADC_FILTER_FACTOR1_V 0x7 -#define APB_SARADC_FILTER_FACTOR1_S 26 +/*description: .*/ +#define APB_SARADC_FILTER_FACTOR1 0x00000007 +#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S)) +#define APB_SARADC_FILTER_FACTOR1_V 0x7 +#define APB_SARADC_FILTER_FACTOR1_S 26 -#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C) +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xC) /* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ -/*description: */ -#define APB_SARADC_STANDBY_WAIT 0x000000FF -#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V) << (APB_SARADC_STANDBY_WAIT_S)) -#define APB_SARADC_STANDBY_WAIT_V 0xFF -#define APB_SARADC_STANDBY_WAIT_S 16 +/*description: .*/ +#define APB_SARADC_STANDBY_WAIT 0x000000FF +#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S)) +#define APB_SARADC_STANDBY_WAIT_V 0xFF +#define APB_SARADC_STANDBY_WAIT_S 16 /* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ -/*description: */ -#define APB_SARADC_RSTB_WAIT 0x000000FF -#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V) << (APB_SARADC_RSTB_WAIT_S)) -#define APB_SARADC_RSTB_WAIT_V 0xFF -#define APB_SARADC_RSTB_WAIT_S 8 +/*description: .*/ +#define APB_SARADC_RSTB_WAIT 0x000000FF +#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S)) +#define APB_SARADC_RSTB_WAIT_V 0xFF +#define APB_SARADC_RSTB_WAIT_S 8 /* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ -/*description: */ -#define APB_SARADC_XPD_WAIT 0x000000FF -#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V) << (APB_SARADC_XPD_WAIT_S)) -#define APB_SARADC_XPD_WAIT_V 0xFF -#define APB_SARADC_XPD_WAIT_S 0 +/*description: .*/ +#define APB_SARADC_XPD_WAIT 0x000000FF +#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S)) +#define APB_SARADC_XPD_WAIT_V 0xFF +#define APB_SARADC_XPD_WAIT_S 0 -#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010) +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10) /* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF -#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V) << (APB_SARADC_SAR1_STATUS_S)) -#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF -#define APB_SARADC_SAR1_STATUS_S 0 +/*description: .*/ +#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S)) +#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_S 0 -#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014) +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14) /* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF -#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V) << (APB_SARADC_SAR2_STATUS_S)) -#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF -#define APB_SARADC_SAR2_STATUS_S 0 +/*description: .*/ +#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S)) +#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_S 0 -#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018) +#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) /* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ -#define APB_SARADC_SAR1_PATT_TAB1 0x00FFFFFF -#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V) << (APB_SARADC_SAR1_PATT_TAB1_S)) -#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFF -#define APB_SARADC_SAR1_PATT_TAB1_S 0 +/*description: item 0 ~ 3 for pattern table 1 (each item one byte).*/ +#define APB_SARADC_SAR1_PATT_TAB1 0x00FFFFFF +#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S)) +#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFF +#define APB_SARADC_SAR1_PATT_TAB1_S 0 -#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C) +#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1C) /* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ -#define APB_SARADC_SAR1_PATT_TAB2 0x00FFFFFF -#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V) << (APB_SARADC_SAR1_PATT_TAB2_S)) -#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFF -#define APB_SARADC_SAR1_PATT_TAB2_S 0 +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte).*/ +#define APB_SARADC_SAR1_PATT_TAB2 0x00FFFFFF +#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S)) +#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFF +#define APB_SARADC_SAR1_PATT_TAB2_S 0 -#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020) +#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x20) /* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ -#define APB_SARADC_SAR1_PATT_TAB3 0x00FFFFFF -#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V) << (APB_SARADC_SAR1_PATT_TAB3_S)) -#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFF -#define APB_SARADC_SAR1_PATT_TAB3_S 0 +/*description: Item 8 ~ 11 for pattern table 1 (each item one byte).*/ +#define APB_SARADC_SAR1_PATT_TAB3 0x00FFFFFF +#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S)) +#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFF +#define APB_SARADC_SAR1_PATT_TAB3_S 0 -#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024) +#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x24) /* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ -#define APB_SARADC_SAR1_PATT_TAB4 0x00FFFFFF -#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V) << (APB_SARADC_SAR1_PATT_TAB4_S)) -#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFF -#define APB_SARADC_SAR1_PATT_TAB4_S 0 +/*description: Item 12 ~ 15 for pattern table 1 (each item one byte).*/ +#define APB_SARADC_SAR1_PATT_TAB4 0x00FFFFFF +#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S)) +#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFF +#define APB_SARADC_SAR1_PATT_TAB4_S 0 -#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x028) +#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x28) /* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ -#define APB_SARADC_SAR2_PATT_TAB1 0x00FFFFFF -#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V) << (APB_SARADC_SAR2_PATT_TAB1_S)) -#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFF -#define APB_SARADC_SAR2_PATT_TAB1_S 0 +/*description: item 0 ~ 3 for pattern table 2 (each item one byte).*/ +#define APB_SARADC_SAR2_PATT_TAB1 0x00FFFFFF +#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S)) +#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFF +#define APB_SARADC_SAR2_PATT_TAB1_S 0 -#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x02C) +#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x2C) /* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ -#define APB_SARADC_SAR2_PATT_TAB2 0x00FFFFFF -#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V) << (APB_SARADC_SAR2_PATT_TAB2_S)) -#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFF -#define APB_SARADC_SAR2_PATT_TAB2_S 0 +/*description: Item 4 ~ 7 for pattern table 2 (each item one byte).*/ +#define APB_SARADC_SAR2_PATT_TAB2 0x00FFFFFF +#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S)) +#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFF +#define APB_SARADC_SAR2_PATT_TAB2_S 0 -#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x030) +#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x30) /* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ -#define APB_SARADC_SAR2_PATT_TAB3 0x00FFFFFF -#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V) << (APB_SARADC_SAR2_PATT_TAB3_S)) -#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFF -#define APB_SARADC_SAR2_PATT_TAB3_S 0 +/*description: Item 8 ~ 11 for pattern table 2 (each item one byte).*/ +#define APB_SARADC_SAR2_PATT_TAB3 0x00FFFFFF +#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S)) +#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFF +#define APB_SARADC_SAR2_PATT_TAB3_S 0 -#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x034) +#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x34) /* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ -#define APB_SARADC_SAR2_PATT_TAB4 0x00FFFFFF -#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V) << (APB_SARADC_SAR2_PATT_TAB4_S)) -#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFF -#define APB_SARADC_SAR2_PATT_TAB4_S 0 +/*description: Item 12 ~ 15 for pattern table 2 (each item one byte).*/ +#define APB_SARADC_SAR2_PATT_TAB4 0x00FFFFFF +#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S)) +#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFF +#define APB_SARADC_SAR2_PATT_TAB4_S 0 -#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038) +#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) /* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: adc2 arbiter uses fixed priority*/ -#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 +/*description: adc2 arbiter uses fixed priority.*/ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 /* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ -/*description: Set adc2 arbiter wifi priority*/ -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V) << (APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/*description: Set adc2 arbiter wifi priority.*/ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 /* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ -/*description: Set adc2 arbiter rtc priority*/ -#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V) << (APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/*description: Set adc2 arbiter rtc priority.*/ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 /* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Set adc2 arbiterapb priority*/ -#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V) << (APB_SARADC_ADC_ARB_APB_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/*description: Set adc2 arbiterapb priority.*/ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 /* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: adc2 arbiter force grant*/ -#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) -#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) -#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/*description: adc2 arbiter force grant.*/ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 /* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable wifi controller*/ -#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) -#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) -#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/*description: adc2 arbiter force to enable wifi controller.*/ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 /* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable rtc controller*/ -#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) -#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) -#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/*description: adc2 arbiter force to enable rtc controller.*/ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 /* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enableapb controller*/ -#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) -#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) -#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 +/*description: adc2 arbiter force to enableapb controller.*/ +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 -#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x03C) +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x3C) /* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: enable apb_adc1_filter*/ -#define APB_SARADC_FILTER_RESET (BIT(31)) -#define APB_SARADC_FILTER_RESET_M (BIT(31)) -#define APB_SARADC_FILTER_RESET_V 0x1 -#define APB_SARADC_FILTER_RESET_S 31 +/*description: enable apb_adc1_filter.*/ +#define APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_FILTER_RESET_M (BIT(31)) +#define APB_SARADC_FILTER_RESET_V 0x1 +#define APB_SARADC_FILTER_RESET_S 31 /* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[23:19] ;default: 5'hd ; */ -/*description: apb_adc1_filter_factor*/ -#define APB_SARADC_FILTER_CHANNEL0 0x0000001F -#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V) << (APB_SARADC_FILTER_CHANNEL0_S)) -#define APB_SARADC_FILTER_CHANNEL0_V 0x1F -#define APB_SARADC_FILTER_CHANNEL0_S 19 +/*description: apb_adc1_filter_factor.*/ +#define APB_SARADC_FILTER_CHANNEL0 0x0000001F +#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S)) +#define APB_SARADC_FILTER_CHANNEL0_V 0x1F +#define APB_SARADC_FILTER_CHANNEL0_S 19 /* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[18:14] ;default: 5'hd ; */ -/*description: */ -#define APB_SARADC_FILTER_CHANNEL1 0x0000001F -#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V) << (APB_SARADC_FILTER_CHANNEL1_S)) -#define APB_SARADC_FILTER_CHANNEL1_V 0x1F -#define APB_SARADC_FILTER_CHANNEL1_S 14 +/*description: .*/ +#define APB_SARADC_FILTER_CHANNEL1 0x0000001F +#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S)) +#define APB_SARADC_FILTER_CHANNEL1_V 0x1F +#define APB_SARADC_FILTER_CHANNEL1_S 14 -#define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x040) +#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x40) /* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DATA 0x0001FFFF -#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V) << (APB_SARADC_ADC1_DATA_S)) -#define APB_SARADC_ADC1_DATA_V 0x1FFFF -#define APB_SARADC_ADC1_DATA_S 0 +/*description: .*/ +#define APB_SARADC_ADC1_DATA 0x0001FFFF +#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S)) +#define APB_SARADC_ADC1_DATA_V 0x1FFFF +#define APB_SARADC_ADC1_DATA_S 0 -#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x044) +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x44) /* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ -/*description: saradc1's thres0 monitor thres*/ -#define APB_SARADC_THRES0_LOW 0x00001FFF -#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V) << (APB_SARADC_THRES0_LOW_S)) -#define APB_SARADC_THRES0_LOW_V 0x1FFF -#define APB_SARADC_THRES0_LOW_S 18 +/*description: saradc1's thres0 monitor thres.*/ +#define APB_SARADC_THRES0_LOW 0x00001FFF +#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S)) +#define APB_SARADC_THRES0_LOW_V 0x1FFF +#define APB_SARADC_THRES0_LOW_S 18 /* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ -/*description: saradc1's thres0 monitor thres*/ -#define APB_SARADC_THRES0_HIGH 0x00001FFF -#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V) << (APB_SARADC_THRES0_HIGH_S)) -#define APB_SARADC_THRES0_HIGH_V 0x1FFF -#define APB_SARADC_THRES0_HIGH_S 5 +/*description: saradc1's thres0 monitor thres.*/ +#define APB_SARADC_THRES0_HIGH 0x00001FFF +#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S)) +#define APB_SARADC_THRES0_HIGH_V 0x1FFF +#define APB_SARADC_THRES0_HIGH_S 5 /* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */ -/*description: */ -#define APB_SARADC_THRES0_CHANNEL 0x0000001F -#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V) << (APB_SARADC_THRES0_CHANNEL_S)) -#define APB_SARADC_THRES0_CHANNEL_V 0x1F -#define APB_SARADC_THRES0_CHANNEL_S 0 +/*description: .*/ +#define APB_SARADC_THRES0_CHANNEL 0x0000001F +#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S)) +#define APB_SARADC_THRES0_CHANNEL_V 0x1F +#define APB_SARADC_THRES0_CHANNEL_S 0 -#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x048) +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x48) /* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ -/*description: saradc1's thres0 monitor thres*/ -#define APB_SARADC_THRES1_LOW 0x00001FFF -#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V) << (APB_SARADC_THRES1_LOW_S)) -#define APB_SARADC_THRES1_LOW_V 0x1FFF -#define APB_SARADC_THRES1_LOW_S 18 +/*description: saradc1's thres0 monitor thres.*/ +#define APB_SARADC_THRES1_LOW 0x00001FFF +#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S)) +#define APB_SARADC_THRES1_LOW_V 0x1FFF +#define APB_SARADC_THRES1_LOW_S 18 /* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ -/*description: saradc1's thres0 monitor thres*/ -#define APB_SARADC_THRES1_HIGH 0x00001FFF -#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V) << (APB_SARADC_THRES1_HIGH_S)) -#define APB_SARADC_THRES1_HIGH_V 0x1FFF -#define APB_SARADC_THRES1_HIGH_S 5 +/*description: saradc1's thres0 monitor thres.*/ +#define APB_SARADC_THRES1_HIGH 0x00001FFF +#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S)) +#define APB_SARADC_THRES1_HIGH_V 0x1FFF +#define APB_SARADC_THRES1_HIGH_S 5 /* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */ -/*description: */ -#define APB_SARADC_THRES1_CHANNEL 0x0000001F -#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V) << (APB_SARADC_THRES1_CHANNEL_S)) -#define APB_SARADC_THRES1_CHANNEL_V 0x1F -#define APB_SARADC_THRES1_CHANNEL_S 0 +/*description: .*/ +#define APB_SARADC_THRES1_CHANNEL 0x0000001F +#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S)) +#define APB_SARADC_THRES1_CHANNEL_V 0x1F +#define APB_SARADC_THRES1_CHANNEL_S 0 -#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058) +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) /* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_EN (BIT(31)) -#define APB_SARADC_THRES0_EN_M (BIT(31)) -#define APB_SARADC_THRES0_EN_V 0x1 -#define APB_SARADC_THRES0_EN_S 31 +/*description: .*/ +#define APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_THRES0_EN_M (BIT(31)) +#define APB_SARADC_THRES0_EN_V 0x1 +#define APB_SARADC_THRES0_EN_S 31 /* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_EN (BIT(30)) -#define APB_SARADC_THRES1_EN_M (BIT(30)) -#define APB_SARADC_THRES1_EN_V 0x1 -#define APB_SARADC_THRES1_EN_S 30 +/*description: .*/ +#define APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_THRES1_EN_M (BIT(30)) +#define APB_SARADC_THRES1_EN_V 0x1 +#define APB_SARADC_THRES1_EN_S 30 /* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES2_EN (BIT(29)) -#define APB_SARADC_THRES2_EN_M (BIT(29)) -#define APB_SARADC_THRES2_EN_V 0x1 -#define APB_SARADC_THRES2_EN_S 29 +/*description: .*/ +#define APB_SARADC_THRES2_EN (BIT(29)) +#define APB_SARADC_THRES2_EN_M (BIT(29)) +#define APB_SARADC_THRES2_EN_V 0x1 +#define APB_SARADC_THRES2_EN_S 29 /* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES3_EN (BIT(28)) -#define APB_SARADC_THRES3_EN_M (BIT(28)) -#define APB_SARADC_THRES3_EN_V 0x1 -#define APB_SARADC_THRES3_EN_S 28 +/*description: .*/ +#define APB_SARADC_THRES3_EN (BIT(28)) +#define APB_SARADC_THRES3_EN_M (BIT(28)) +#define APB_SARADC_THRES3_EN_V 0x1 +#define APB_SARADC_THRES3_EN_S 28 /* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_THRES_ALL_EN (BIT(27)) -#define APB_SARADC_THRES_ALL_EN_M (BIT(27)) -#define APB_SARADC_THRES_ALL_EN_V 0x1 -#define APB_SARADC_THRES_ALL_EN_S 27 +/*description: .*/ +#define APB_SARADC_THRES_ALL_EN (BIT(27)) +#define APB_SARADC_THRES_ALL_EN_M (BIT(27)) +#define APB_SARADC_THRES_ALL_EN_V 0x1 +#define APB_SARADC_THRES_ALL_EN_S 27 -#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x05C) +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x5C) /* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_ENA_S 31 +/*description: .*/ +#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ENA_S 31 /* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_ENA_S 30 +/*description: .*/ +#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ENA_S 30 /* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 +/*description: .*/ +#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 /* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 +/*description: .*/ +#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 /* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_ENA_S 27 +/*description: .*/ +#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_ENA_S 27 /* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1 -#define APB_SARADC_THRES1_LOW_INT_ENA_S 26 +/*description: .*/ +#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ENA_S 26 -#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x060) +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x60) /* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_RAW_S 31 +/*description: .*/ +#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_RAW_S 31 /* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_RAW_S 30 +/*description: .*/ +#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_RAW_S 30 /* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 +/*description: .*/ +#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 /* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 +/*description: .*/ +#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 /* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_RAW_S 27 +/*description: .*/ +#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_RAW_S 27 /* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1 -#define APB_SARADC_THRES1_LOW_INT_RAW_S 26 +/*description: .*/ +#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_RAW_S 26 -#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x064) +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x64) /* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_ST_S 31 +/*description: .*/ +#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ST_S 31 /* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_ST_S 30 +/*description: .*/ +#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ST_S 30 /* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_ST_S 29 +/*description: .*/ +#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_ST_S 29 /* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_ST_S 28 +/*description: .*/ +#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_ST_S 28 /* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_ST_S 27 +/*description: .*/ +#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_ST_S 27 /* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1 -#define APB_SARADC_THRES1_LOW_INT_ST_S 26 +/*description: .*/ +#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ST_S 26 -#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x068) +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x68) /* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_CLR_S 31 +/*description: .*/ +#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_CLR_S 31 /* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_CLR_S 30 +/*description: .*/ +#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_CLR_S 30 /* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 +/*description: .*/ +#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 /* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 +/*description: .*/ +#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 /* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_CLR_S 27 +/*description: .*/ +#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_CLR_S 27 /* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1 -#define APB_SARADC_THRES1_LOW_INT_CLR_S 26 +/*description: .*/ +#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_CLR_S 26 -#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x06c) +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x6C) /* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: enable apb_adc use spi_dma*/ -#define APB_SARADC_APB_ADC_TRANS (BIT(31)) -#define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) -#define APB_SARADC_APB_ADC_TRANS_V 0x1 -#define APB_SARADC_APB_ADC_TRANS_S 31 +/*description: enable apb_adc use spi_dma.*/ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_V 0x1 +#define APB_SARADC_APB_ADC_TRANS_S 31 /* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: reset_apb_adc_state*/ -#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) -#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) -#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 -#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/*description: reset_apb_adc_state.*/ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 /* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ -/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ -#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF -#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V) << (APB_SARADC_APB_ADC_EOF_NUM_S)) -#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF -#define APB_SARADC_APB_ADC_EOF_NUM_S 0 +/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num.*/ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF +#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S)) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 -#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x070) +#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x70) /* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ -/*description: Set this bit to enable clk_apll*/ -#define APB_SARADC_CLK_SEL 0x00000003 -#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V) << (APB_SARADC_CLK_SEL_S)) -#define APB_SARADC_CLK_SEL_V 0x3 -#define APB_SARADC_CLK_SEL_S 21 +/*description: Set this bit to enable clk_apll.*/ +#define APB_SARADC_CLK_SEL 0x00000003 +#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S)) +#define APB_SARADC_CLK_SEL_V 0x3 +#define APB_SARADC_CLK_SEL_S 21 /* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_CLK_EN (BIT(20)) -#define APB_SARADC_CLK_EN_M (BIT(20)) -#define APB_SARADC_CLK_EN_V 0x1 -#define APB_SARADC_CLK_EN_S 20 +/*description: .*/ +#define APB_SARADC_CLK_EN (BIT(20)) +#define APB_SARADC_CLK_EN_M (BIT(20)) +#define APB_SARADC_CLK_EN_V 0x1 +#define APB_SARADC_CLK_EN_S 20 /* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ -/*description: Fractional clock divider denominator value*/ -#define APB_SARADC_CLKM_DIV_A 0x0000003F -#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V) << (APB_SARADC_CLKM_DIV_A_S)) -#define APB_SARADC_CLKM_DIV_A_V 0x3F -#define APB_SARADC_CLKM_DIV_A_S 14 +/*description: Fractional clock divider denominator value.*/ +#define APB_SARADC_CLKM_DIV_A 0x0000003F +#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S)) +#define APB_SARADC_CLKM_DIV_A_V 0x3F +#define APB_SARADC_CLKM_DIV_A_S 14 /* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ -/*description: Fractional clock divider numerator value*/ -#define APB_SARADC_CLKM_DIV_B 0x0000003F -#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V) << (APB_SARADC_CLKM_DIV_B_S)) -#define APB_SARADC_CLKM_DIV_B_V 0x3F -#define APB_SARADC_CLKM_DIV_B_S 8 +/*description: Fractional clock divider numerator value.*/ +#define APB_SARADC_CLKM_DIV_B 0x0000003F +#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S)) +#define APB_SARADC_CLKM_DIV_B_V 0x3F +#define APB_SARADC_CLKM_DIV_B_S 8 /* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ -/*description: Integral I2S clock divider value*/ -#define APB_SARADC_CLKM_DIV_NUM 0x000000FF -#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V) << (APB_SARADC_CLKM_DIV_NUM_S)) -#define APB_SARADC_CLKM_DIV_NUM_V 0xFF -#define APB_SARADC_CLKM_DIV_NUM_S 0 +/*description: Integral I2S clock divider value.*/ +#define APB_SARADC_CLKM_DIV_NUM 0x000000FF +#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S)) +#define APB_SARADC_CLKM_DIV_NUM_V 0xFF +#define APB_SARADC_CLKM_DIV_NUM_S 0 -#define APB_SARADC_APB_DAC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x074) -/* APB_SARADC_DAC_CLK_GATE_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_DAC_CLK_GATE_EN (BIT(18)) -#define APB_SARADC_DAC_CLK_GATE_EN_M (BIT(18)) -#define APB_SARADC_DAC_CLK_GATE_EN_V 0x1 -#define APB_SARADC_DAC_CLK_GATE_EN_S 18 -/* APB_SARADC_DAC_CLK_FO : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_DAC_CLK_FO (BIT(17)) -#define APB_SARADC_DAC_CLK_FO_M (BIT(17)) -#define APB_SARADC_DAC_CLK_FO_V 0x1 -#define APB_SARADC_DAC_CLK_FO_S 17 -/* APB_SARADC_APB_DAC_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_APB_DAC_RST (BIT(16)) -#define APB_SARADC_APB_DAC_RST_M (BIT(16)) -#define APB_SARADC_APB_DAC_RST_V 0x1 -#define APB_SARADC_APB_DAC_RST_S 16 -/* APB_SARADC_DAC_RESET_FIFO : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_DAC_RESET_FIFO (BIT(15)) -#define APB_SARADC_DAC_RESET_FIFO_M (BIT(15)) -#define APB_SARADC_DAC_RESET_FIFO_V 0x1 -#define APB_SARADC_DAC_RESET_FIFO_S 15 -/* APB_SARADC_APB_DAC_TRANS : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable dma_dac*/ -#define APB_SARADC_APB_DAC_TRANS (BIT(14)) -#define APB_SARADC_APB_DAC_TRANS_M (BIT(14)) -#define APB_SARADC_APB_DAC_TRANS_V 0x1 -#define APB_SARADC_APB_DAC_TRANS_S 14 -/* APB_SARADC_APB_DAC_ALTER_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: enable dac alter mode*/ -#define APB_SARADC_APB_DAC_ALTER_MODE (BIT(13)) -#define APB_SARADC_APB_DAC_ALTER_MODE_M (BIT(13)) -#define APB_SARADC_APB_DAC_ALTER_MODE_V 0x1 -#define APB_SARADC_APB_DAC_ALTER_MODE_S 13 -/* APB_SARADC_DAC_TIMER_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable read dac data*/ -#define APB_SARADC_DAC_TIMER_EN (BIT(12)) -#define APB_SARADC_DAC_TIMER_EN_M (BIT(12)) -#define APB_SARADC_DAC_TIMER_EN_V 0x1 -#define APB_SARADC_DAC_TIMER_EN_S 12 -/* APB_SARADC_DAC_TIMER_TARGET : R/W ;bitpos:[11:0] ;default: 12'd100 ; */ -/*description: dac_timer target*/ -#define APB_SARADC_DAC_TIMER_TARGET 0x00000FFF -#define APB_SARADC_DAC_TIMER_TARGET_M ((APB_SARADC_DAC_TIMER_TARGET_V) << (APB_SARADC_DAC_TIMER_TARGET_S)) -#define APB_SARADC_DAC_TIMER_TARGET_V 0xFFF -#define APB_SARADC_DAC_TIMER_TARGET_S 0 - -#define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x078) +#define APB_SARADC_APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x78) /* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DATA 0x0001FFFF -#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V) << (APB_SARADC_ADC2_DATA_S)) -#define APB_SARADC_ADC2_DATA_V 0x1FFFF -#define APB_SARADC_ADC2_DATA_S 0 +/*description: .*/ +#define APB_SARADC_ADC2_DATA 0x0001FFFF +#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S)) +#define APB_SARADC_ADC2_DATA_V 0x1FFFF +#define APB_SARADC_ADC2_DATA_S 0 -#define APB_SARADC_APB_DAC_CLK_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x07c) -/* APB_SARADC_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: */ -#define APB_SARADC_DAC_CLK_DIV 0x000000FF -#define APB_SARADC_DAC_CLK_DIV_M ((APB_SARADC_DAC_CLK_DIV_V) << (APB_SARADC_DAC_CLK_DIV_S)) -#define APB_SARADC_DAC_CLK_DIV_V 0xFF -#define APB_SARADC_DAC_CLK_DIV_S 0 +#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC) +/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02101180 ; */ +/*description: .*/ +#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF +#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S)) +#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_SARADC_APB_CTRL_DATE_S 0 -#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC) -/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02003060 ; */ -/*description: */ -#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF -#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V) << (APB_SARADC_APB_CTRL_DATE_S)) -#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF -#define APB_SARADC_APB_CTRL_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_APB_SARADC_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/apb_saradc_struct.h b/components/soc/esp32s3/include/soc/apb_saradc_struct.h index 9814b63007..7e77b1e00c 100644 --- a/components/soc/esp32s3/include/soc/apb_saradc_struct.h +++ b/components/soc/esp32s3/include/soc/apb_saradc_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,170 +11,130 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_APB_SARADC_STRUCT_H_ +#define _SOC_APB_SARADC_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { union { struct { - uint32_t start_force: 1; - uint32_t start: 1; - uint32_t reserved2: 1; - uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ - uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ - uint32_t sar_clk_gated: 1; - uint32_t sar_clk_div: 8; /*SAR clock divider*/ - uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ - uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ - uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ - uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ - uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ - uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ - uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ - uint32_t reserved29: 1; - uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/ + uint32_t start_force : 1; + uint32_t start : 1; + uint32_t reserved2 : 1; + uint32_t work_mode : 2; /* 0: single mode, 1: double mode, 2: alternate mode*/ + uint32_t sar_sel : 1; /* 0: SAR1, 1: SAR2, only work for single SAR mode*/ + uint32_t sar_clk_gated : 1; + uint32_t sar_clk_div : 8; /*SAR clock divider*/ + uint32_t sar1_patt_len : 4; /* 0 ~ 15 means length 1 ~ 16*/ + uint32_t sar2_patt_len : 4; /* 0 ~ 15 means length 1 ~ 16*/ + uint32_t sar1_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + uint32_t sar2_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ + uint32_t data_sar_sel : 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.*/ + uint32_t data_to_i2s : 1; /*1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix*/ + uint32_t xpd_sar_force : 2; /*force option to xpd sar blocks*/ + uint32_t reserved29 : 1; + uint32_t wait_arb_cycle : 2; /*wait arbit signal stable after sar_done*/ }; uint32_t val; } ctrl; union { struct { - uint32_t meas_num_limit: 1; - uint32_t max_meas_num: 8; /*max conversion number*/ - uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ - uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ - uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/ - uint32_t timer_target: 12; /*to set saradc timer target*/ - uint32_t timer_en: 1; /*to enable saradc timer trigger*/ - uint32_t reserved25: 7; + uint32_t meas_num_limit : 1; + uint32_t max_meas_num : 8; /*max conversion number*/ + uint32_t sar1_inv : 1; /*1: data to DIG ADC1 CTRL is inverted, otherwise not*/ + uint32_t sar2_inv : 1; /*1: data to DIG ADC2 CTRL is inverted, otherwise not*/ + uint32_t timer_sel : 1; /*1: select saradc timer 0: i2s_ws trigger*/ + uint32_t timer_target : 12; /*to set saradc timer target*/ + uint32_t timer_en : 1; /*to enable saradc timer trigger*/ + uint32_t reserved25 : 7; }; uint32_t val; } ctrl2; union { struct { - uint32_t reserved0: 26; - uint32_t filter_factor1: 3; - uint32_t filter_factor0: 3; + uint32_t reserved0 : 26; + uint32_t filter_factor1 : 3; + uint32_t filter_factor0 : 3; }; uint32_t val; } filter_ctrl1; union { struct { - uint32_t xpd_wait: 8; - uint32_t rstb_wait: 8; - uint32_t standby_wait: 8; - uint32_t reserved24: 8; + uint32_t xpd_wait : 8; + uint32_t rstb_wait : 8; + uint32_t standby_wait : 8; + uint32_t reserved24 : 8; }; uint32_t val; } fsm_wait; - uint32_t sar1_status; /**/ - uint32_t sar2_status; /**/ + uint32_t sar1_status; + uint32_t sar2_status; union { struct { - uint32_t sar1_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ - uint32_t reserved24: 8; + uint32_t sar1_patt_tab : 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + uint32_t reserved24 : 8; }; uint32_t val; - } sar1_patt_tab1; + } sar1_patt_tab[4]; union { struct { - uint32_t sar1_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/ - uint32_t reserved24: 8; + uint32_t sar2_patt_tab : 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ + uint32_t reserved24 : 8; }; uint32_t val; - } sar1_patt_tab2; + } sar2_patt_tab[4]; union { struct { - uint32_t sar1_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } sar1_patt_tab3; - union { - struct { - uint32_t sar1_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } sar1_patt_tab4; - union { - struct { - uint32_t sar2_patt_tab1: 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } sar2_patt_tab1; - union { - struct { - uint32_t sar2_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } sar2_patt_tab2; - union { - struct { - uint32_t sar2_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } sar2_patt_tab3; - union { - struct { - uint32_t sar2_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } sar2_patt_tab4; - union { - struct { - uint32_t reserved0: 2; - uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ - uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ - uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ - uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ - uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ - uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ - uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ - uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ - uint32_t reserved13: 19; + uint32_t reserved0 : 2; + uint32_t adc_arb_apb_force : 1; /*adc2 arbiter force to enableapb controller*/ + uint32_t adc_arb_rtc_force : 1; /*adc2 arbiter force to enable rtc controller*/ + uint32_t adc_arb_wifi_force : 1; /*adc2 arbiter force to enable wifi controller*/ + uint32_t adc_arb_grant_force : 1; /*adc2 arbiter force grant*/ + uint32_t adc_arb_apb_priority : 2; /*Set adc2 arbiterapb priority*/ + uint32_t adc_arb_rtc_priority : 2; /*Set adc2 arbiter rtc priority*/ + uint32_t adc_arb_wifi_priority : 2; /*Set adc2 arbiter wifi priority*/ + uint32_t adc_arb_fix_priority : 1; /*adc2 arbiter uses fixed priority*/ + uint32_t reserved13 : 19; }; uint32_t val; } apb_adc_arb_ctrl; union { struct { - uint32_t reserved0: 14; - uint32_t filter_channel1: 5; - uint32_t filter_channel0: 5; /*apb_adc1_filter_factor*/ - uint32_t reserved24: 7; - uint32_t filter_reset: 1; /*enable apb_adc1_filter*/ + uint32_t reserved0 : 14; + uint32_t filter_channel1 : 5; + uint32_t filter_channel0 : 5; /*apb_adc1_filter_factor*/ + uint32_t reserved24 : 7; + uint32_t filter_reset : 1; /*enable apb_adc1_filter*/ }; uint32_t val; } filter_ctrl0; union { struct { - uint32_t adc1_data: 17; - uint32_t reserved17: 15; + uint32_t adc1_data : 17; + uint32_t reserved17 : 15; }; uint32_t val; } apb_saradc1_data_status; union { struct { - uint32_t thres0_channel: 5; - uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/ - uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/ + uint32_t thres0_channel : 5; + uint32_t thres0_high : 13; /*saradc1's thres0 monitor thres*/ + uint32_t thres0_low : 13; /*saradc1's thres0 monitor thres*/ + uint32_t reserved31 : 1; }; uint32_t val; } thres0_ctrl; union { struct { - uint32_t thres1_channel: 5; - uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/ - uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/ - uint32_t reserved31: 1; + uint32_t thres1_channel : 5; + uint32_t thres1_high : 13; /*saradc1's thres0 monitor thres*/ + uint32_t thres1_low : 13; /*saradc1's thres0 monitor thres*/ + uint32_t reserved31 : 1; }; uint32_t val; } thres1_ctrl; @@ -183,111 +143,92 @@ typedef volatile struct { uint32_t reserved_54; union { struct { - uint32_t reserved0: 27; - uint32_t thres_all_en: 1; - uint32_t thres3_en: 1; - uint32_t thres2_en: 1; - uint32_t thres1_en: 1; - uint32_t thres0_en: 1; + uint32_t reserved0 : 27; + uint32_t thres_all_en : 1; + uint32_t thres3_en : 1; + uint32_t thres2_en : 1; + uint32_t thres1_en : 1; + uint32_t thres0_en : 1; }; uint32_t val; } thres_ctrl; union { struct { - uint32_t reserved0: 26; - uint32_t thres1_low: 1; - uint32_t thres0_low: 1; - uint32_t thres1_high: 1; - uint32_t thres0_high: 1; - uint32_t adc2_done: 1; - uint32_t adc1_done: 1; + uint32_t reserved0 : 26; + uint32_t thres1_low : 1; + uint32_t thres0_low : 1; + uint32_t thres1_high : 1; + uint32_t thres0_high : 1; + uint32_t adc2_done : 1; + uint32_t adc1_done : 1; }; uint32_t val; } int_ena; union { struct { - uint32_t reserved0: 26; - uint32_t thres1_low: 1; - uint32_t thres0_low: 1; - uint32_t thres1_high: 1; - uint32_t thres0_high: 1; - uint32_t adc2_done: 1; - uint32_t adc1_done: 1; + uint32_t reserved0 : 26; + uint32_t thres1_low : 1; + uint32_t thres0_low : 1; + uint32_t thres1_high : 1; + uint32_t thres0_high : 1; + uint32_t adc2_done : 1; + uint32_t adc1_done : 1; }; uint32_t val; } int_raw; union { struct { - uint32_t reserved0: 26; - uint32_t thres1_low: 1; - uint32_t thres0_low: 1; - uint32_t thres1_high: 1; - uint32_t thres0_high: 1; - uint32_t adc2_done: 1; - uint32_t adc1_done: 1; + uint32_t reserved0 : 26; + uint32_t thres1_low : 1; + uint32_t thres0_low : 1; + uint32_t thres1_high : 1; + uint32_t thres0_high : 1; + uint32_t adc2_done : 1; + uint32_t adc1_done : 1; }; uint32_t val; } int_st; union { struct { - uint32_t reserved0: 26; - uint32_t thres1_low: 1; - uint32_t thres0_low: 1; - uint32_t thres1_high: 1; - uint32_t thres0_high: 1; - uint32_t adc2_done: 1; - uint32_t adc1_done: 1; + uint32_t reserved0 : 26; + uint32_t thres1_low : 1; + uint32_t thres0_low : 1; + uint32_t thres1_high : 1; + uint32_t thres0_high : 1; + uint32_t adc2_done : 1; + uint32_t adc1_done : 1; }; uint32_t val; } int_clr; union { struct { - uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ - uint32_t reserved16: 14; - uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/ - uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/ + uint32_t apb_adc_eof_num : 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ + uint32_t reserved16 : 14; + uint32_t apb_adc_reset_fsm : 1; /*reset_apb_adc_state*/ + uint32_t apb_adc_trans : 1; /*enable apb_adc use spi_dma*/ }; uint32_t val; } dma_conf; union { struct { - uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/ - uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/ - uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/ - uint32_t clk_en: 1; - uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ - uint32_t reserved23: 9; + uint32_t clkm_div_num : 8; /*Integral I2S clock divider value*/ + uint32_t clkm_div_b : 6; /*Fractional clock divider numerator value*/ + uint32_t clkm_div_a : 6; /*Fractional clock divider denominator value*/ + uint32_t clk_en : 1; + uint32_t clk_sel : 2; /*Set this bit to enable clk_apll*/ + uint32_t reserved23 : 9; }; uint32_t val; } apb_adc_clkm_conf; + uint32_t reserved_74; union { struct { - uint32_t dac_timer_target: 12; /*dac_timer target*/ - uint32_t dac_timer_en: 1; /*enable read dac data*/ - uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/ - uint32_t apb_dac_trans: 1; /*enable dma_dac*/ - uint32_t dac_reset_fifo: 1; - uint32_t apb_dac_rst: 1; - uint32_t dac_clk_fo: 1; - uint32_t dac_clk_gate_en: 1; - uint32_t reserved19: 13; - }; - uint32_t val; - } apb_dac_ctrl; - union { - struct { - uint32_t adc2_data: 17; - uint32_t reserved17: 15; + uint32_t adc2_data : 17; + uint32_t reserved17 : 15; }; uint32_t val; } apb_saradc2_data_status; - union { - struct { - uint32_t dac_clk_div: 8; - uint32_t reserved8: 24; - }; - uint32_t val; - } apb_dac_clk_ctrl; + uint32_t reserved_7c; uint32_t reserved_80; uint32_t reserved_84; uint32_t reserved_88; @@ -511,11 +452,13 @@ typedef volatile struct { uint32_t reserved_3f0; uint32_t reserved_3f4; uint32_t reserved_3f8; - uint32_t apb_ctrl_date; /**/ + uint32_t apb_ctrl_date; } apb_saradc_dev_t; - extern apb_saradc_dev_t APB_SARADC; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_APB_SARADC_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/cpu.h b/components/soc/esp32s3/include/soc/cpu.h new file mode 100644 index 0000000000..ad7f7c11d5 --- /dev/null +++ b/components/soc/esp32s3/include/soc/cpu.h @@ -0,0 +1,131 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include +#include "xtensa/corebits.h" + +/* C macros for xtensa special register read/write/exchange */ + +#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval)); +#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval)); +#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval)); + +/** @brief Read current stack pointer address + * + */ +static inline void *get_sp(void) +{ + void *sp; + asm volatile ("mov %0, sp;" : "=r" (sp)); + return sp; +} + +/* Functions to set page attributes for Region Protection option in the CPU. + * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2). + */ + +static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr) +{ + asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr)); +} + + +static inline void cpu_write_itlb(unsigned vpn, unsigned attr) +{ + asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr)); +} + +/** + * @brief Configure memory region protection + * + * Make page 0 access raise an exception. + * Also protect some other unused pages so we can catch weirdness. + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + */ + +static inline void cpu_configure_region_protection(void) +{ + const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000}; + for (int i = 0; i < sizeof(pages_to_protect) / sizeof(pages_to_protect[0]); ++i) { + cpu_write_dtlb(pages_to_protect[i], 0xf); + cpu_write_itlb(pages_to_protect[i], 0xf); + } + cpu_write_dtlb(0x20000000, 0); + cpu_write_itlb(0x20000000, 0); +} + +/** + * @brief Stall CPU using RTC controller + * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP) + */ +void esp_cpu_stall(int cpu_id); + +/** + * @brief Un-stall CPU using RTC controller + * @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP) + */ +void esp_cpu_unstall(int cpu_id); + +/** + * @brief Reset CPU using RTC controller + * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP) + */ +void esp_cpu_reset(int cpu_id); + + +/** + * @brief Returns true if a JTAG debugger is attached to CPU + * OCD (on chip debug) port. + * + * @note If "Make exception and panic handlers JTAG/OCD aware" + * is disabled, this function always returns false. + */ +bool esp_cpu_in_ocd_debug_mode(void); + +/** + * @brief Convert the PC register value to its true address + * + * The address of the current instruction is not stored as an exact uint32_t + * representation in PC register. This function will convert the value stored in + * the PC register to a uint32_t address. + * + * @param pc_raw The PC as stored in register format. + * + * @return Address in uint32_t format + */ +static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc) +{ + if (pc & 0x80000000) { + //Top two bits of a0 (return address) specify window increment. Overwrite to map to address space. + pc = (pc & 0x3fffffff) | 0x40000000; + } + //Minus 3 to get PC of previous instruction (i.e. instruction executed before return address) + return pc - 3; +} + +typedef uint32_t esp_cpu_ccount_t; + +static inline esp_cpu_ccount_t esp_cpu_get_ccount(void) +{ + uint32_t result; + RSR(CCOUNT, result); + return result; +} diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h index 5d68868580..81e549bfac 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/include/soc/efuse_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,2242 +11,1935 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_EFUSE_REG_H_ +#define _SOC_EFUSE_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Set this bit to disable eFuse programming.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the 0th 32-bit data to be programmed..*/ +#define EFUSE_PGM_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_M ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S)) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_S 0 -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_VDD_SPI_DREFH : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: SPI regulator high voltage reference.*/ -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) -#define EFUSE_VDD_SPI_DREFH_V 0x3 -#define EFUSE_VDD_SPI_DREFH_S 30 -/* EFUSE_VDD_SPI_MODECURLIM : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: SPI regulator switches current limit mode.*/ -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : R/W ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Enable btlc gpio.*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_USB_EXT_PHY_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable external PHY.*/ -#define EFUSE_USB_EXT_PHY_ENABLE (BIT(26)) -#define EFUSE_USB_EXT_PHY_ENABLE_M (BIT(26)) -#define EFUSE_USB_EXT_PHY_ENABLE_V 0x1 -#define EFUSE_USB_EXT_PHY_ENABLE_S 26 -/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to exchange D+ and D- pins.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefl 0.8 V to 1.04 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefh 1.76 V to 2 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to disable flash encrypt function (except in SPI/HSPI/Legacy_SPI - boot mode).*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_HARD_DIS_JTAG : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ -#define EFUSE_HARD_DIS_JTAG (BIT(19)) -#define EFUSE_HARD_DIS_JTAG_M (BIT(19)) -#define EFUSE_HARD_DIS_JTAG_V 0x1 -#define EFUSE_HARD_DIS_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Set these bits to disable JTAG in the soft way (odd number 1 - means disable). JTAG can be enabled in HMAC module.*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_DIS_APP_CPU : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to disable app cpu.*/ -#define EFUSE_DIS_APP_CPU (BIT(15)) -#define EFUSE_DIS_APP_CPU_M (BIT(15)) -#define EFUSE_DIS_APP_CPU_V 0x1 -#define EFUSE_DIS_APP_CPU_S 15 -/* EFUSE_DIS_CAN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to disable CAN function.*/ -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (BIT(14)) -#define EFUSE_DIS_CAN_V 0x1 -#define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to disable USB function.*/ -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (BIT(13)) -#define EFUSE_DIS_USB_V 0x1 -#define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to disable the function that forces chip into download mode.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to disable Dcache in download mode ( boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to disable Dcache.*/ -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (BIT(9)) -#define EFUSE_DIS_DCACHE_V 0x1 -#define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to disable boot from RTC RAM.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 -/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Set this bit to disable reading from BlOCK4-10.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the 1st 32-bit data to be programmed..*/ +#define EFUSE_PGM_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_M ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S)) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_S 0 -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Purpose of Key1. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Purpose of Key0. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking third secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking second secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking first secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of - 1: enable. even number of 1: disable.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold.*/ -#define EFUSE_WAT_DELAY_SEL 0x00000003 -#define EFUSE_WAT_DELAY_SEL_M ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S)) -#define EFUSE_WAT_DELAY_SEL_V 0x3 -#define EFUSE_WAT_DELAY_SEL_S 16 -/* EFUSE_VDD_SPI_DCAP : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: Prevents SPI regulator from overshoot.*/ -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) -#define EFUSE_VDD_SPI_DCAP_V 0x3 -#define EFUSE_VDD_SPI_DCAP_S 14 -/* EFUSE_VDD_SPI_INIT : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/ -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) -#define EFUSE_VDD_SPI_INIT_V 0x3 -#define EFUSE_VDD_SPI_INIT_S 12 -/* EFUSE_VDD_SPI_DCURLIM : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: Tunes the current limit threshold of SPI regulator when tieh=0 - about 800 mA/(8+d).*/ -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) -#define EFUSE_VDD_SPI_DCURLIM_V 0x7 -#define EFUSE_VDD_SPI_DCURLIM_S 9 -/* EFUSE_VDD_SPI_ENCURLIM : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set SPI regulator to 1 to enable output current limit.*/ -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 -/* EFUSE_VDD_SPI_EN_INIT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set SPI regulator to 0 to configure init[1:0]=0.*/ -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_V 0x1 -#define EFUSE_VDD_SPI_EN_INIT_S 7 -/* EFUSE_VDD_SPI_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_V 0x1 -#define EFUSE_VDD_SPI_FORCE_S 6 -/* EFUSE_VDD_SPI_TIEH : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: SPI regulator output is short connected to VDD3P3_RTC_IO.*/ -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_V 0x1 -#define EFUSE_VDD_SPI_TIEH_S 5 -/* EFUSE_VDD_SPI_XPD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: SPI regulator power up signal.*/ -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (BIT(4)) -#define EFUSE_VDD_SPI_XPD_V 0x1 -#define EFUSE_VDD_SPI_XPD_S 4 -/* EFUSE_VDD_SPI_DREFL : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: SPI regulator low voltage reference.*/ -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) -#define EFUSE_VDD_SPI_DREFL_V 0x3 -#define EFUSE_VDD_SPI_DREFL_S 2 -/* EFUSE_VDD_SPI_DREFM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: SPI regulator medium voltage reference.*/ -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) -#define EFUSE_VDD_SPI_DREFM_V 0x3 -#define EFUSE_VDD_SPI_DREFM_S 0 +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the 2nd 32-bit data to be programmed..*/ +#define EFUSE_PGM_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_M ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S)) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_S 0 -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00C) -/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up in unit of ms. - When the value is 15 the waiting time is 30 ms.*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED0 0x0000003F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3F -#define EFUSE_RPT4_RESERVED0_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking aggressive secure boot.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure boot.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_KEY_PURPOSE_6 : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Purpose of Key6. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_6 0x0000000F -#define EFUSE_KEY_PURPOSE_6_M ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S)) -#define EFUSE_KEY_PURPOSE_6_V 0xF -#define EFUSE_KEY_PURPOSE_6_S 16 -/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Purpose of Key5. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Purpose of Key4. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Purpose of Key3. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Purpose of Key2. Refer to Table KEY_PURPOSE Values.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF -#define EFUSE_KEY_PURPOSE_2_S 0 +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xC) +/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the 3rd 32-bit data to be programmed..*/ +#define EFUSE_PGM_DATA_3 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_M ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S)) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_S 0 -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED1 0x00000003 -#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) -#define EFUSE_RPT4_RESERVED1_V 0x3 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: Secure version (used by ESP-IDF anti-rollback feature).*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_FLASH_ECC_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set 1 to enable ECC for flash boot.*/ -#define EFUSE_FLASH_ECC_EN (BIT(12)) -#define EFUSE_FLASH_ECC_EN_M (BIT(12)) -#define EFUSE_FLASH_ECC_EN_V 0x1 -#define EFUSE_FLASH_ECC_EN_S 12 -/* EFUSE_FLASH_PAGE_SIZE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: Flash page size.*/ -#define EFUSE_FLASH_PAGE_SIZE 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) -#define EFUSE_FLASH_PAGE_SIZE_V 0x3 -#define EFUSE_FLASH_PAGE_SIZE_S 10 -/* EFUSE_FLASH_TYPE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The type of the interfaced flash. 0: four data lines 1: eight data lines.*/ -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (BIT(9)) -#define EFUSE_FLASH_TYPE_V 0x1 -#define EFUSE_FLASH_TYPE_S 9 -/* EFUSE_PIN_POWER_SELECTION : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU 1: VDD_SPI.*/ -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_V 0x1 -#define EFUSE_PIN_POWER_SELECTION_S 8 -/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The type of UART print control.00: Forces to print.01: Controlled - by GPIO46 print at low level.10: Controlled by GPIO46 print at high level.11: Forces to disable print.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable security download mode.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to disable download through USB.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 -/* EFUSE_FLASH_ECC_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. - 1:flash ecc 16to17 byte mode.*/ -#define EFUSE_FLASH_ECC_MODE (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_M (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_V 0x1 -#define EFUSE_FLASH_ECC_MODE_S 3 -/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Selectes UART print channel. 0: UART0 1: UART1.*/ -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_V 0x1 -#define EFUSE_UART_PRINT_CHANNEL_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 -#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the 4th 32-bit data to be programmed..*/ +#define EFUSE_PGM_DATA_4 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_M ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S)) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_S 0 -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the 5th 32-bit data to be programmed..*/ +#define EFUSE_PGM_DATA_5 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_M ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S)) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_S 0 -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) /* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the sixth 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF +/*description: The content of the 6th 32-bit data to be programmed..*/ +#define EFUSE_PGM_DATA_6 0xFFFFFFFF #define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) #define EFUSE_PGM_DATA_6_V 0xFFFFFFFF #define EFUSE_PGM_DATA_6_S 0 -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01C) +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1C) /* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the seventh 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF +/*description: The content of the 7th 32-bit data to be programmed..*/ +#define EFUSE_PGM_DATA_7 0xFFFFFFFF #define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) #define EFUSE_PGM_DATA_7_V 0xFFFFFFFF #define EFUSE_PGM_DATA_7_S 0 -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) /* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF +/*description: The content of the 0th 32-bit RS code to be programmed..*/ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF #define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) #define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF #define EFUSE_PGM_RS_DATA_0_S 0 -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) /* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the first 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF +/*description: The content of the 1st 32-bit RS code to be programmed..*/ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF #define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) #define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF #define EFUSE_PGM_RS_DATA_1_S 0 -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x028) +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) /* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the second 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF +/*description: The content of the 2nd 32-bit RS code to be programmed..*/ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF #define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) #define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF #define EFUSE_PGM_RS_DATA_2_S 0 -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x02C) +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2C) /* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The value of WR_DIS.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF +/*description: Disable programming of individual eFuses..*/ +#define EFUSE_WR_DIS 0xFFFFFFFF #define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) #define EFUSE_WR_DIS_V 0xFFFFFFFF #define EFUSE_WR_DIS_S 0 -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x030) +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /* EFUSE_VDD_SPI_DREFH : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFH.*/ -#define EFUSE_VDD_SPI_DREFH 0x00000003 +/*description: SPI regulator high voltage reference..*/ +#define EFUSE_VDD_SPI_DREFH 0x00000003 #define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) #define EFUSE_VDD_SPI_DREFH_V 0x3 #define EFUSE_VDD_SPI_DREFH_S 30 /* EFUSE_VDD_SPI_MODECURLIM : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_MODECURLIM.*/ -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +/*description: SPI regulator switches current limit mode..*/ +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) #define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) #define EFUSE_VDD_SPI_MODECURLIM_V 0x1 #define EFUSE_VDD_SPI_MODECURLIM_S 29 /* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: The value of BTLC_GPIO_ENABLE.*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 +/*description: Enable btlc gpio..*/ +#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 #define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) #define EFUSE_BTLC_GPIO_ENABLE_V 0x3 #define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The value of EXT_PHY_ENABLE.*/ -#define EFUSE_USB_EXT_PHY_ENABLE (BIT(26)) -#define EFUSE_USB_EXT_PHY_ENABLE_M (BIT(26)) -#define EFUSE_USB_EXT_PHY_ENABLE_V 0x1 -#define EFUSE_USB_EXT_PHY_ENABLE_S 26 +/* EFUSE_EXT_PHY_ENABLE : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable external PHY..*/ +#define EFUSE_EXT_PHY_ENABLE (BIT(26)) +#define EFUSE_EXT_PHY_ENABLE_M (BIT(26)) +#define EFUSE_EXT_PHY_ENABLE_V 0x1 +#define EFUSE_EXT_PHY_ENABLE_S 26 /* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The value of USB_EXCHG_PINS.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) +/*description: Set this bit to exchange USB D+ and D- pins..*/ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) #define EFUSE_USB_EXCHG_PINS_M (BIT(25)) #define EFUSE_USB_EXCHG_PINS_V 0x1 #define EFUSE_USB_EXCHG_PINS_S 25 /* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: The value of USB_DREFL.*/ -#define EFUSE_USB_DREFL 0x00000003 +/*description: Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, s +tored in eFuse..*/ +#define EFUSE_USB_DREFL 0x00000003 #define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) #define EFUSE_USB_DREFL_V 0x3 #define EFUSE_USB_DREFL_S 23 /* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: The value of USB_DREFH.*/ -#define EFUSE_USB_DREFH 0x00000003 +/*description: Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, sto +red in eFuse..*/ +#define EFUSE_USB_DREFH 0x00000003 #define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) #define EFUSE_USB_DREFH_V 0x3 #define EFUSE_USB_DREFH_S 21 /* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +/*description: Set this bit to disable flash encryption when in download boot modes..*/ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_HARD_DIS_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The value of HARD_DIS_JTAG.*/ -#define EFUSE_HARD_DIS_JTAG (BIT(19)) -#define EFUSE_HARD_DIS_JTAG_M (BIT(19)) -#define EFUSE_HARD_DIS_JTAG_V 0x1 -#define EFUSE_HARD_DIS_JTAG_S 19 +/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently..*/ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_V 0x1 +#define EFUSE_DIS_PAD_JTAG_S 19 /* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of SOFT_DIS_JTAG.*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 +/*description: Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JT +AG can be enabled in HMAC module..*/ +#define EFUSE_SOFT_DIS_JTAG 0x00000007 #define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) #define EFUSE_SOFT_DIS_JTAG_V 0x7 #define EFUSE_SOFT_DIS_JTAG_S 16 /* EFUSE_DIS_APP_CPU : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The value of DIS_APP_CPU.*/ -#define EFUSE_DIS_APP_CPU (BIT(15)) +/*description: Disable app cpu..*/ +#define EFUSE_DIS_APP_CPU (BIT(15)) #define EFUSE_DIS_APP_CPU_M (BIT(15)) #define EFUSE_DIS_APP_CPU_V 0x1 #define EFUSE_DIS_APP_CPU_S 15 /* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The value of DIS_CAN.*/ -#define EFUSE_DIS_CAN (BIT(14)) +/*description: Set this bit to disable CAN function..*/ +#define EFUSE_DIS_CAN (BIT(14)) #define EFUSE_DIS_CAN_M (BIT(14)) #define EFUSE_DIS_CAN_V 0x1 #define EFUSE_DIS_CAN_S 14 /* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The value of DIS_USB.*/ -#define EFUSE_DIS_USB (BIT(13)) +/*description: Set this bit to disable USB function..*/ +#define EFUSE_DIS_USB (BIT(13)) #define EFUSE_DIS_USB_M (BIT(13)) #define EFUSE_DIS_USB_V 0x1 #define EFUSE_DIS_USB_S 13 /* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The value of DIS_FORCE_DOWNLOAD.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +/*description: Set this bit to disable the function that forces chip into download mode..*/ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 /* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_DCACHE.*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +/*description: Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, +6, 7)..*/ +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) #define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) #define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 #define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 /* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_ICACHE.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6 +, 7)..*/ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) #define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) #define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 #define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 /* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of DIS_DCACHE.*/ -#define EFUSE_DIS_DCACHE (BIT(9)) +/*description: Set this bit to disable Dcache..*/ +#define EFUSE_DIS_DCACHE (BIT(9)) #define EFUSE_DIS_DCACHE_M (BIT(9)) #define EFUSE_DIS_DCACHE_V 0x1 #define EFUSE_DIS_DCACHE_S 9 /* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of DIS_ICACHE.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) +/*description: Set this bit to disable Icache..*/ +#define EFUSE_DIS_ICACHE (BIT(8)) #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 /* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of DIS_RTC_RAM_BOOT.*/ -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +/*description: Set this bit to disable boot from RTC RAM..*/ +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) #define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) #define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 #define EFUSE_DIS_RTC_RAM_BOOT_S 7 /* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The value of RD_DIS.*/ -#define EFUSE_RD_DIS 0x0000007F +/*description: Set this bit to disable reading from BlOCK4-10..*/ +#define EFUSE_RD_DIS 0x0000007F #define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) #define EFUSE_RD_DIS_V 0x7F #define EFUSE_RD_DIS_S 0 -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x034) +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) /* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F +/*description: Purpose of Key1..*/ +#define EFUSE_KEY_PURPOSE_1 0x0000000F #define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) #define EFUSE_KEY_PURPOSE_1_V 0xF #define EFUSE_KEY_PURPOSE_1_S 28 /* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F +/*description: Purpose of Key0..*/ +#define EFUSE_KEY_PURPOSE_0 0x0000000F #define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) #define EFUSE_KEY_PURPOSE_0_V 0xF #define EFUSE_KEY_PURPOSE_0_S 24 /* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +/*description: Set this bit to enable revoking third secure boot key..*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 /* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +/*description: Set this bit to enable revoking second secure boot key..*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 /* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +/*description: Set this bit to enable revoking first secure boot key..*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 /* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: The value of SPI_BOOT_CRYPT_CNT.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 +/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even n +umber of 1: disable..*/ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 #define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 /* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The value of WDT_DELAY_SEL.*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 +/*description: Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1 +: 80000. 2: 160000. 3:320000..*/ +#define EFUSE_WDT_DELAY_SEL 0x00000003 #define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) #define EFUSE_WDT_DELAY_SEL_V 0x3 #define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_EUFSE_VDD_SPI_DCAP : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: The value of REG_VDD_SPI_DCAP.*/ -#define EFUSE_EUFSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_EUFSE_VDD_SPI_DCAP_M ((EFUSE_EUFSE_VDD_SPI_DCAP_V)<<(EFUSE_EUFSE_VDD_SPI_DCAP_S)) -#define EFUSE_EUFSE_VDD_SPI_DCAP_V 0x3 -#define EFUSE_EUFSE_VDD_SPI_DCAP_S 14 +/* EFUSE_VDD_SPI_DCAP : RO ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: Prevents SPI regulator from overshoot..*/ +#define EFUSE_VDD_SPI_DCAP 0x00000003 +#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) +#define EFUSE_VDD_SPI_DCAP_V 0x3 +#define EFUSE_VDD_SPI_DCAP_S 14 /* EFUSE_VDD_SPI_INIT : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_INIT.*/ -#define EFUSE_VDD_SPI_INIT 0x00000003 +/*description: Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K..*/ +#define EFUSE_VDD_SPI_INIT 0x00000003 #define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) #define EFUSE_VDD_SPI_INIT_V 0x3 #define EFUSE_VDD_SPI_INIT_S 12 -/* EFUSE_VDD_SPI_DCURLIM : RO ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: The value of VDD_SPI_DCURLIM.*/ -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 +/* EFUSE_VDD_SPI_DCURLIM : RO ;bitpos:[11:9]] ;default: 3'h0 ; */ +/*description: Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+ +d)..*/ +#define EFUSE_VDD_SPI_DCURLIM 0x00000007 #define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) #define EFUSE_VDD_SPI_DCURLIM_V 0x7 #define EFUSE_VDD_SPI_DCURLIM_S 9 /* EFUSE_VDD_SPI_ENCURLIM : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_ENCURLIM.*/ -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +/*description: Set SPI regulator to 1 to enable output current limit..*/ +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) #define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) #define EFUSE_VDD_SPI_ENCURLIM_V 0x1 #define EFUSE_VDD_SPI_ENCURLIM_S 8 /* EFUSE_VDD_SPI_EN_INIT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_EN_INIT.*/ -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +/*description: Set SPI regulator to 0 to configure init[1:0]=0..*/ +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) #define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) #define EFUSE_VDD_SPI_EN_INIT_V 0x1 #define EFUSE_VDD_SPI_EN_INIT_S 7 /* EFUSE_VDD_SPI_FORCE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_FORCE.*/ -#define EFUSE_VDD_SPI_FORCE (BIT(6)) +/*description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI..*/ +#define EFUSE_VDD_SPI_FORCE (BIT(6)) #define EFUSE_VDD_SPI_FORCE_M (BIT(6)) #define EFUSE_VDD_SPI_FORCE_V 0x1 #define EFUSE_VDD_SPI_FORCE_S 6 /* EFUSE_VDD_SPI_TIEH : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_TIEH.*/ -#define EFUSE_VDD_SPI_TIEH (BIT(5)) +/*description: SPI regulator output is short connected to VDD3P3_RTC_IO..*/ +#define EFUSE_VDD_SPI_TIEH (BIT(5)) #define EFUSE_VDD_SPI_TIEH_M (BIT(5)) #define EFUSE_VDD_SPI_TIEH_V 0x1 #define EFUSE_VDD_SPI_TIEH_S 5 /* EFUSE_VDD_SPI_XPD : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_XPD.*/ -#define EFUSE_VDD_SPI_XPD (BIT(4)) +/*description: SPI regulator power up signal..*/ +#define EFUSE_VDD_SPI_XPD (BIT(4)) #define EFUSE_VDD_SPI_XPD_M (BIT(4)) #define EFUSE_VDD_SPI_XPD_V 0x1 #define EFUSE_VDD_SPI_XPD_S 4 /* EFUSE_VDD_SPI_DREFL : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFL.*/ -#define EFUSE_VDD_SPI_DREFL 0x00000003 +/*description: SPI regulator low voltage reference..*/ +#define EFUSE_VDD_SPI_DREFL 0x00000003 #define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) #define EFUSE_VDD_SPI_DREFL_V 0x3 #define EFUSE_VDD_SPI_DREFL_S 2 /* EFUSE_VDD_SPI_DREFM : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The value of VDD_SPI_DREFM.*/ -#define EFUSE_VDD_SPI_DREFM 0x00000003 +/*description: SPI regulator medium voltage reference..*/ +#define EFUSE_VDD_SPI_DREFM 0x00000003 #define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) #define EFUSE_VDD_SPI_DREFM_V 0x3 #define EFUSE_VDD_SPI_DREFM_S 0 -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x038) +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) /* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of FLASH_TPUW.*/ -#define EFUSE_FLASH_TPUW 0x0000000F +/*description: Configures flash waiting time after power-up, in unit of ms. If the value is les +s than 15, the waiting time is the configurable value; Otherwise, the waiting ti +me is twice the configurable value..*/ +#define EFUSE_FLASH_TPUW 0x0000000F #define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) #define EFUSE_FLASH_TPUW_V 0xF #define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0 0x0000003F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3F -#define EFUSE_RPT4_RESERVED0_S 22 +/* EFUSE_POWER_GLITCH_DSENSE : RO ;bitpos:[27:26] ;default: 2'h0 ; */ +/*description: Sample delay configuration of power glitch..*/ +#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 +#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) +#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 +#define EFUSE_POWER_GLITCH_DSENSE_S 26 +/* EFUSE_USB_PHY_SEL : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to switch internal PHY and external PHY for USB OTG and USB Dev +ice. 0: internal PHY is assigned to USB Device while external PHY is assigned to + USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned +to USB Device..*/ +#define EFUSE_USB_PHY_SEL (BIT(25)) +#define EFUSE_USB_PHY_SEL_M (BIT(25)) +#define EFUSE_USB_PHY_SEL_V 0x1 +#define EFUSE_USB_PHY_SEL_S 25 +/* EFUSE_STRAP_JTAG_SEL : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through str +apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/ +#define EFUSE_STRAP_JTAG_SEL (BIT(24)) +#define EFUSE_STRAP_JTAG_SEL_M (BIT(24)) +#define EFUSE_STRAP_JTAG_SEL_V 0x1 +#define EFUSE_STRAP_JTAG_SEL_S 24 +/* EFUSE_DIS_USB_DEVICE : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to disable usb device..*/ +#define EFUSE_DIS_USB_DEVICE (BIT(23)) +#define EFUSE_DIS_USB_DEVICE_M (BIT(23)) +#define EFUSE_DIS_USB_DEVICE_V 0x1 +#define EFUSE_DIS_USB_DEVICE_S 23 +/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[22] ;default: 6'h0 ; */ +/*description: Set this bit to disable function of usb switch to jtag in module of usb device..*/ +#define EFUSE_DIS_USB_JTAG (BIT(22)) +#define EFUSE_DIS_USB_JTAG_M (BIT(22)) +#define EFUSE_DIS_USB_JTAG_V 0x1 +#define EFUSE_DIS_USB_JTAG_S 22 /* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +/*description: Set this bit to enable revoking aggressive secure boot..*/ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 /* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_EN.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) +/*description: Set this bit to enable secure boot..*/ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) #define EFUSE_SECURE_BOOT_EN_M (BIT(20)) #define EFUSE_SECURE_BOOT_EN_V 0x1 #define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_KEY_PURPOSE_6 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_6.*/ -#define EFUSE_KEY_PURPOSE_6 0x0000000F -#define EFUSE_KEY_PURPOSE_6_M ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S)) -#define EFUSE_KEY_PURPOSE_6_V 0xF -#define EFUSE_KEY_PURPOSE_6_S 16 +/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: Reserved (used for four backups method)..*/ +#define EFUSE_RPT4_RESERVED0 0x0000000F +#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) +#define EFUSE_RPT4_RESERVED0_V 0xF +#define EFUSE_RPT4_RESERVED0_S 16 /* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F +/*description: Purpose of Key5..*/ +#define EFUSE_KEY_PURPOSE_5 0x0000000F #define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) #define EFUSE_KEY_PURPOSE_5_V 0xF #define EFUSE_KEY_PURPOSE_5_S 12 /* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F +/*description: Purpose of Key4..*/ +#define EFUSE_KEY_PURPOSE_4 0x0000000F #define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) #define EFUSE_KEY_PURPOSE_4_V 0xF #define EFUSE_KEY_PURPOSE_4_S 8 /* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F +/*description: Purpose of Key3..*/ +#define EFUSE_KEY_PURPOSE_3 0x0000000F #define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) #define EFUSE_KEY_PURPOSE_3_V 0xF #define EFUSE_KEY_PURPOSE_3_S 4 /* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F +/*description: Purpose of Key2..*/ +#define EFUSE_KEY_PURPOSE_2 0x0000000F #define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) #define EFUSE_KEY_PURPOSE_2_V 0xF #define EFUSE_KEY_PURPOSE_2_S 0 -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C) -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1 0x00000003 -#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) -#define EFUSE_RPT4_RESERVED1_V 0x3 -#define EFUSE_RPT4_RESERVED1_S 30 +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3C) +/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Reserved (used for four backups method)..*/ +#define EFUSE_RPT4_RESERVED1 (BIT(31)) +#define EFUSE_RPT4_RESERVED1_M (BIT(31)) +#define EFUSE_RPT4_RESERVED1_V 0x1 +#define EFUSE_RPT4_RESERVED1_S 31 +/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable power glitch function..*/ +#define EFUSE_POWERGLITCH_EN (BIT(30)) +#define EFUSE_POWERGLITCH_EN_M (BIT(30)) +#define EFUSE_POWERGLITCH_EN_V 0x1 +#define EFUSE_POWERGLITCH_EN_S 30 /* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: The value of SECURE_VERSION.*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF +/*description: Secure version (used by ESP-IDF anti-rollback feature)..*/ +#define EFUSE_SECURE_VERSION 0x0000FFFF #define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) #define EFUSE_SECURE_VERSION_V 0xFFFF #define EFUSE_SECURE_VERSION_S 14 /* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The value of FORCE_SEND_RESUME.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +/*description: Set this bit to force ROM code to send a resume command during SPI boot..*/ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) #define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) #define EFUSE_FORCE_SEND_RESUME_V 0x1 #define EFUSE_FORCE_SEND_RESUME_S 13 /* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The value of FLASH_ECC_EN.*/ -#define EFUSE_FLASH_ECC_EN (BIT(12)) +/*description: Set 1 to enable ECC for flash boot..*/ +#define EFUSE_FLASH_ECC_EN (BIT(12)) #define EFUSE_FLASH_ECC_EN_M (BIT(12)) #define EFUSE_FLASH_ECC_EN_V 0x1 #define EFUSE_FLASH_ECC_EN_S 12 /* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: The value of FLASH_PAGE_SIZE.*/ -#define EFUSE_FLASH_PAGE_SIZE 0x00000003 +/*description: Set Flash page size..*/ +#define EFUSE_FLASH_PAGE_SIZE 0x00000003 #define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) #define EFUSE_FLASH_PAGE_SIZE_V 0x3 #define EFUSE_FLASH_PAGE_SIZE_S 10 /* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of FLASH_TYPE.*/ -#define EFUSE_FLASH_TYPE (BIT(9)) +/*description: Set the maximum lines of SPI flash. 0: four lines. 1: eight lines..*/ +#define EFUSE_FLASH_TYPE (BIT(9)) #define EFUSE_FLASH_TYPE_M (BIT(9)) #define EFUSE_FLASH_TYPE_V 0x1 #define EFUSE_FLASH_TYPE_S 9 /* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of PIN_POWER_SELECTION.*/ -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI..*/ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) #define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) #define EFUSE_PIN_POWER_SELECTION_V 0x1 #define EFUSE_PIN_POWER_SELECTION_S 8 /* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The value of UART_PRINT_CONTROL.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 +/*description: Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO +8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled..*/ +#define EFUSE_UART_PRINT_CONTROL 0x00000003 #define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) #define EFUSE_UART_PRINT_CONTROL_V 0x3 #define EFUSE_UART_PRINT_CONTROL_S 6 /* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +/*description: Set this bit to enable secure UART download mode..*/ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 /* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +/*description: Set this bit to disable UART download mode through USB..*/ +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) #define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 #define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 /* EFUSE_FLASH_ECC_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The value of FLASH_ECC_MODE.*/ -#define EFUSE_FLASH_ECC_MODE (BIT(3)) +/*description: Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + use 16to17 byte mode..*/ +#define EFUSE_FLASH_ECC_MODE (BIT(3)) #define EFUSE_FLASH_ECC_MODE_M (BIT(3)) #define EFUSE_FLASH_ECC_MODE_V 0x1 #define EFUSE_FLASH_ECC_MODE_S 3 /* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The value of UART_PRINT_CHANNEL.*/ -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +/*description: Selectes the default UART print channel. 0: UART0. 1: UART1..*/ +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) #define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) #define EFUSE_UART_PRINT_CHANNEL_V 0x1 #define EFUSE_UART_PRINT_CHANNEL_S 2 /* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The value of DIS_LEGACY_SPI_BOOT.*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +/*description: Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4)..*/ +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) #define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) #define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 #define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 /* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +/*description: Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7)..*/ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 #define EFUSE_DIS_DOWNLOAD_MODE_S 0 -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Reserved (used for four backups method)..*/ +#define EFUSE_RPT4_RESERVED2 0x00FFFFFF +#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) +#define EFUSE_RPT4_RESERVED2_V 0xFFFFFF +#define EFUSE_RPT4_RESERVED2_S 0 -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x044) +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) /* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address.*/ -#define EFUSE_MAC_0 0xFFFFFFFF +/*description: Stores the low 32 bits of MAC address..*/ +#define EFUSE_MAC_0 0xFFFFFFFF #define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) #define EFUSE_MAC_0_V 0xFFFFFFFF #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x048) +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) /* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the zeroth part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF +/*description: Stores the zeroth part of SPI_PAD_CONF..*/ +#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF #define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) #define EFUSE_SPI_PAD_CONF_0_V 0xFFFF #define EFUSE_SPI_PAD_CONF_0_S 16 /* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address.*/ -#define EFUSE_MAC_1 0x0000FFFF +/*description: Stores the high 16 bits of MAC address..*/ +#define EFUSE_MAC_1 0x0000FFFF #define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) #define EFUSE_MAC_1_V 0xFFFF #define EFUSE_MAC_1_S 0 -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x04C) +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4C) /* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF +/*description: Stores the first part of SPI_PAD_CONF..*/ +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) #define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_S 0 -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) /* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */ -/*description: Stores the fist 14 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFF +/*description: Stores the fist 14 bits of the zeroth part of system data..*/ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFF #define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) #define EFUSE_SYS_DATA_PART0_0_V 0x3FFF #define EFUSE_SYS_DATA_PART0_0_S 18 /* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +/*description: Stores the second part of SPI_PAD_CONF..*/ +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF #define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) #define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF #define EFUSE_SPI_PAD_CONF_2_S 0 -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) /* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF +/*description: Stores the fist 32 bits of the zeroth part of system data..*/ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) #define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_1_S 0 -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) /* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF +/*description: Stores the second 32 bits of the zeroth part of system data..*/ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) #define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x05C) +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5C) /* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF +/*description: Stores the zeroth 32 bits of the first part of system data..*/ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) #define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_0_S 0 -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) /* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF +/*description: Stores the first 32 bits of the first part of system data..*/ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) #define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_1_S 0 -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) /* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF +/*description: Stores the second 32 bits of the first part of system data..*/ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) #define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_2_S 0 -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) /* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF +/*description: Stores the third 32 bits of the first part of system data..*/ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) #define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_3_S 0 -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x06C) +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6C) /* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF +/*description: Stores the fourth 32 bits of the first part of system data..*/ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) #define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_4_S 0 -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) /* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF +/*description: Stores the fifth 32 bits of the first part of system data..*/ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) #define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_5_S 0 -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) /* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF +/*description: Stores the sixth 32 bits of the first part of system data..*/ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) #define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_6_S 0 -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) /* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF +/*description: Stores the seventh 32 bits of the first part of system data..*/ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) #define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART1_7_S 0 -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x07C) +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7C) /* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF +/*description: Stores the zeroth 32 bits of BLOCK3 (user)..*/ +#define EFUSE_USR_DATA0 0xFFFFFFFF #define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) #define EFUSE_USR_DATA0_V 0xFFFFFFFF #define EFUSE_USR_DATA0_S 0 -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x080) +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) /* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF +/*description: Stores the first 32 bits of BLOCK3 (user)..*/ +#define EFUSE_USR_DATA1 0xFFFFFFFF #define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) #define EFUSE_USR_DATA1_V 0xFFFFFFFF #define EFUSE_USR_DATA1_S 0 -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x084) +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) /* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF +/*description: Stores the second 32 bits of BLOCK3 (user)..*/ +#define EFUSE_USR_DATA2 0xFFFFFFFF #define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) #define EFUSE_USR_DATA2_V 0xFFFFFFFF #define EFUSE_USR_DATA2_S 0 -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x088) +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) /* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF +/*description: Stores the third 32 bits of BLOCK3 (user)..*/ +#define EFUSE_USR_DATA3 0xFFFFFFFF #define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) #define EFUSE_USR_DATA3_V 0xFFFFFFFF #define EFUSE_USR_DATA3_S 0 -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x08C) +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8C) /* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF +/*description: Stores the fourth 32 bits of BLOCK3 (user)..*/ +#define EFUSE_USR_DATA4 0xFFFFFFFF #define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) #define EFUSE_USR_DATA4_V 0xFFFFFFFF #define EFUSE_USR_DATA4_S 0 -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x090) +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) /* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF +/*description: Stores the fifth 32 bits of BLOCK3 (user)..*/ +#define EFUSE_USR_DATA5 0xFFFFFFFF #define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) #define EFUSE_USR_DATA5_V 0xFFFFFFFF #define EFUSE_USR_DATA5_S 0 -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x094) +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) /* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF +/*description: Stores the sixth 32 bits of BLOCK3 (user)..*/ +#define EFUSE_USR_DATA6 0xFFFFFFFF #define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) #define EFUSE_USR_DATA6_V 0xFFFFFFFF #define EFUSE_USR_DATA6_S 0 -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x098) +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) /* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF +/*description: Stores the seventh 32 bits of BLOCK3 (user)..*/ +#define EFUSE_USR_DATA7 0xFFFFFFFF #define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) #define EFUSE_USR_DATA7_V 0xFFFFFFFF #define EFUSE_USR_DATA7_S 0 -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x09C) +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9C) /* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF +/*description: Stores the zeroth 32 bits of KEY0..*/ +#define EFUSE_KEY0_DATA0 0xFFFFFFFF #define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) #define EFUSE_KEY0_DATA0_V 0xFFFFFFFF #define EFUSE_KEY0_DATA0_S 0 -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0x0A0) +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xA0) /* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF +/*description: Stores the first 32 bits of KEY0..*/ +#define EFUSE_KEY0_DATA1 0xFFFFFFFF #define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) #define EFUSE_KEY0_DATA1_V 0xFFFFFFFF #define EFUSE_KEY0_DATA1_S 0 -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0x0A4) +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xA4) /* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF +/*description: Stores the second 32 bits of KEY0..*/ +#define EFUSE_KEY0_DATA2 0xFFFFFFFF #define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) #define EFUSE_KEY0_DATA2_V 0xFFFFFFFF #define EFUSE_KEY0_DATA2_S 0 -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0x0A8) +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xA8) /* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF +/*description: Stores the third 32 bits of KEY0..*/ +#define EFUSE_KEY0_DATA3 0xFFFFFFFF #define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) #define EFUSE_KEY0_DATA3_V 0xFFFFFFFF #define EFUSE_KEY0_DATA3_S 0 -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0x0AC) +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xAC) /* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF +/*description: Stores the fourth 32 bits of KEY0..*/ +#define EFUSE_KEY0_DATA4 0xFFFFFFFF #define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) #define EFUSE_KEY0_DATA4_V 0xFFFFFFFF #define EFUSE_KEY0_DATA4_S 0 -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0x0B0) +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xB0) /* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF +/*description: Stores the fifth 32 bits of KEY0..*/ +#define EFUSE_KEY0_DATA5 0xFFFFFFFF #define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) #define EFUSE_KEY0_DATA5_V 0xFFFFFFFF #define EFUSE_KEY0_DATA5_S 0 -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0x0B4) +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xB4) /* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF +/*description: Stores the sixth 32 bits of KEY0..*/ +#define EFUSE_KEY0_DATA6 0xFFFFFFFF #define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) #define EFUSE_KEY0_DATA6_V 0xFFFFFFFF #define EFUSE_KEY0_DATA6_S 0 -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0x0B8) +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xB8) /* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF +/*description: Stores the seventh 32 bits of KEY0..*/ +#define EFUSE_KEY0_DATA7 0xFFFFFFFF #define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) #define EFUSE_KEY0_DATA7_V 0xFFFFFFFF #define EFUSE_KEY0_DATA7_S 0 -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0x0BC) +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xBC) /* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF +/*description: Stores the zeroth 32 bits of KEY1..*/ +#define EFUSE_KEY1_DATA0 0xFFFFFFFF #define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) #define EFUSE_KEY1_DATA0_V 0xFFFFFFFF #define EFUSE_KEY1_DATA0_S 0 -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0x0C0) +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xC0) /* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF +/*description: Stores the first 32 bits of KEY1..*/ +#define EFUSE_KEY1_DATA1 0xFFFFFFFF #define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) #define EFUSE_KEY1_DATA1_V 0xFFFFFFFF #define EFUSE_KEY1_DATA1_S 0 -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0x0C4) +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xC4) /* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF +/*description: Stores the second 32 bits of KEY1..*/ +#define EFUSE_KEY1_DATA2 0xFFFFFFFF #define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) #define EFUSE_KEY1_DATA2_V 0xFFFFFFFF #define EFUSE_KEY1_DATA2_S 0 -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0x0C8) +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xC8) /* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF +/*description: Stores the third 32 bits of KEY1..*/ +#define EFUSE_KEY1_DATA3 0xFFFFFFFF #define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) #define EFUSE_KEY1_DATA3_V 0xFFFFFFFF #define EFUSE_KEY1_DATA3_S 0 -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0x0CC) +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xCC) /* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF +/*description: Stores the fourth 32 bits of KEY1..*/ +#define EFUSE_KEY1_DATA4 0xFFFFFFFF #define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) #define EFUSE_KEY1_DATA4_V 0xFFFFFFFF #define EFUSE_KEY1_DATA4_S 0 -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0x0D0) +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xD0) /* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF +/*description: Stores the fifth 32 bits of KEY1..*/ +#define EFUSE_KEY1_DATA5 0xFFFFFFFF #define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) #define EFUSE_KEY1_DATA5_V 0xFFFFFFFF #define EFUSE_KEY1_DATA5_S 0 -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0x0D4) +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xD4) /* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF +/*description: Stores the sixth 32 bits of KEY1..*/ +#define EFUSE_KEY1_DATA6 0xFFFFFFFF #define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) #define EFUSE_KEY1_DATA6_V 0xFFFFFFFF #define EFUSE_KEY1_DATA6_S 0 -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0x0D8) +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xD8) /* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF +/*description: Stores the seventh 32 bits of KEY1..*/ +#define EFUSE_KEY1_DATA7 0xFFFFFFFF #define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) #define EFUSE_KEY1_DATA7_V 0xFFFFFFFF #define EFUSE_KEY1_DATA7_S 0 -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0x0DC) +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xDC) /* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF +/*description: Stores the zeroth 32 bits of KEY2..*/ +#define EFUSE_KEY2_DATA0 0xFFFFFFFF #define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) #define EFUSE_KEY2_DATA0_V 0xFFFFFFFF #define EFUSE_KEY2_DATA0_S 0 -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0x0E0) +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xE0) /* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF +/*description: Stores the first 32 bits of KEY2..*/ +#define EFUSE_KEY2_DATA1 0xFFFFFFFF #define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) #define EFUSE_KEY2_DATA1_V 0xFFFFFFFF #define EFUSE_KEY2_DATA1_S 0 -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0x0E4) +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xE4) /* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF +/*description: Stores the second 32 bits of KEY2..*/ +#define EFUSE_KEY2_DATA2 0xFFFFFFFF #define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) #define EFUSE_KEY2_DATA2_V 0xFFFFFFFF #define EFUSE_KEY2_DATA2_S 0 -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0x0E8) +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xE8) /* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF +/*description: Stores the third 32 bits of KEY2..*/ +#define EFUSE_KEY2_DATA3 0xFFFFFFFF #define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) #define EFUSE_KEY2_DATA3_V 0xFFFFFFFF #define EFUSE_KEY2_DATA3_S 0 -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0x0EC) +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xEC) /* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF +/*description: Stores the fourth 32 bits of KEY2..*/ +#define EFUSE_KEY2_DATA4 0xFFFFFFFF #define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) #define EFUSE_KEY2_DATA4_V 0xFFFFFFFF #define EFUSE_KEY2_DATA4_S 0 -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0x0F0) +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xF0) /* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF +/*description: Stores the fifth 32 bits of KEY2..*/ +#define EFUSE_KEY2_DATA5 0xFFFFFFFF #define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) #define EFUSE_KEY2_DATA5_V 0xFFFFFFFF #define EFUSE_KEY2_DATA5_S 0 -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x0F4) +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xF4) /* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF +/*description: Stores the sixth 32 bits of KEY2..*/ +#define EFUSE_KEY2_DATA6 0xFFFFFFFF #define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) #define EFUSE_KEY2_DATA6_V 0xFFFFFFFF #define EFUSE_KEY2_DATA6_S 0 -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x0F8) +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xF8) /* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF +/*description: Stores the seventh 32 bits of KEY2..*/ +#define EFUSE_KEY2_DATA7 0xFFFFFFFF #define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) #define EFUSE_KEY2_DATA7_V 0xFFFFFFFF #define EFUSE_KEY2_DATA7_S 0 -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x0FC) +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xFC) /* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF +/*description: Stores the zeroth 32 bits of KEY3..*/ +#define EFUSE_KEY3_DATA0 0xFFFFFFFF #define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) #define EFUSE_KEY3_DATA0_V 0xFFFFFFFF #define EFUSE_KEY3_DATA0_S 0 #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) /* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF +/*description: Stores the first 32 bits of KEY3..*/ +#define EFUSE_KEY3_DATA1 0xFFFFFFFF #define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) #define EFUSE_KEY3_DATA1_V 0xFFFFFFFF #define EFUSE_KEY3_DATA1_S 0 #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) /* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF +/*description: Stores the second 32 bits of KEY3..*/ +#define EFUSE_KEY3_DATA2 0xFFFFFFFF #define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) #define EFUSE_KEY3_DATA2_V 0xFFFFFFFF #define EFUSE_KEY3_DATA2_S 0 #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) /* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF +/*description: Stores the third 32 bits of KEY3..*/ +#define EFUSE_KEY3_DATA3 0xFFFFFFFF #define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) #define EFUSE_KEY3_DATA3_V 0xFFFFFFFF #define EFUSE_KEY3_DATA3_S 0 #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10C) /* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF +/*description: Stores the fourth 32 bits of KEY3..*/ +#define EFUSE_KEY3_DATA4 0xFFFFFFFF #define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) #define EFUSE_KEY3_DATA4_V 0xFFFFFFFF #define EFUSE_KEY3_DATA4_S 0 #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) /* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF +/*description: Stores the fifth 32 bits of KEY3..*/ +#define EFUSE_KEY3_DATA5 0xFFFFFFFF #define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) #define EFUSE_KEY3_DATA5_V 0xFFFFFFFF #define EFUSE_KEY3_DATA5_S 0 #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) /* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF +/*description: Stores the sixth 32 bits of KEY3..*/ +#define EFUSE_KEY3_DATA6 0xFFFFFFFF #define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) #define EFUSE_KEY3_DATA6_V 0xFFFFFFFF #define EFUSE_KEY3_DATA6_S 0 #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) /* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF +/*description: Stores the seventh 32 bits of KEY3..*/ +#define EFUSE_KEY3_DATA7 0xFFFFFFFF #define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) #define EFUSE_KEY3_DATA7_V 0xFFFFFFFF #define EFUSE_KEY3_DATA7_S 0 #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11C) /* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF +/*description: Stores the zeroth 32 bits of KEY4..*/ +#define EFUSE_KEY4_DATA0 0xFFFFFFFF #define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) #define EFUSE_KEY4_DATA0_V 0xFFFFFFFF #define EFUSE_KEY4_DATA0_S 0 #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) /* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF +/*description: Stores the first 32 bits of KEY4..*/ +#define EFUSE_KEY4_DATA1 0xFFFFFFFF #define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) #define EFUSE_KEY4_DATA1_V 0xFFFFFFFF #define EFUSE_KEY4_DATA1_S 0 #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) /* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF +/*description: Stores the second 32 bits of KEY4..*/ +#define EFUSE_KEY4_DATA2 0xFFFFFFFF #define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) #define EFUSE_KEY4_DATA2_V 0xFFFFFFFF #define EFUSE_KEY4_DATA2_S 0 #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) /* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF +/*description: Stores the third 32 bits of KEY4..*/ +#define EFUSE_KEY4_DATA3 0xFFFFFFFF #define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) #define EFUSE_KEY4_DATA3_V 0xFFFFFFFF #define EFUSE_KEY4_DATA3_S 0 #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12C) /* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF +/*description: Stores the fourth 32 bits of KEY4..*/ +#define EFUSE_KEY4_DATA4 0xFFFFFFFF #define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) #define EFUSE_KEY4_DATA4_V 0xFFFFFFFF #define EFUSE_KEY4_DATA4_S 0 #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) /* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF +/*description: Stores the fifth 32 bits of KEY4..*/ +#define EFUSE_KEY4_DATA5 0xFFFFFFFF #define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) #define EFUSE_KEY4_DATA5_V 0xFFFFFFFF #define EFUSE_KEY4_DATA5_S 0 #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) /* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF +/*description: Stores the sixth 32 bits of KEY4..*/ +#define EFUSE_KEY4_DATA6 0xFFFFFFFF #define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) #define EFUSE_KEY4_DATA6_V 0xFFFFFFFF #define EFUSE_KEY4_DATA6_S 0 #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) /* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF +/*description: Stores the seventh 32 bits of KEY4..*/ +#define EFUSE_KEY4_DATA7 0xFFFFFFFF #define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) #define EFUSE_KEY4_DATA7_V 0xFFFFFFFF #define EFUSE_KEY4_DATA7_S 0 #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13C) /* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF +/*description: Stores the zeroth 32 bits of KEY5..*/ +#define EFUSE_KEY5_DATA0 0xFFFFFFFF #define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) #define EFUSE_KEY5_DATA0_V 0xFFFFFFFF #define EFUSE_KEY5_DATA0_S 0 #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) /* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF +/*description: Stores the first 32 bits of KEY5..*/ +#define EFUSE_KEY5_DATA1 0xFFFFFFFF #define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) #define EFUSE_KEY5_DATA1_V 0xFFFFFFFF #define EFUSE_KEY5_DATA1_S 0 #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) /* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF +/*description: Stores the second 32 bits of KEY5..*/ +#define EFUSE_KEY5_DATA2 0xFFFFFFFF #define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) #define EFUSE_KEY5_DATA2_V 0xFFFFFFFF #define EFUSE_KEY5_DATA2_S 0 #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) /* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF +/*description: Stores the third 32 bits of KEY5..*/ +#define EFUSE_KEY5_DATA3 0xFFFFFFFF #define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) #define EFUSE_KEY5_DATA3_V 0xFFFFFFFF #define EFUSE_KEY5_DATA3_S 0 #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14C) /* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF +/*description: Stores the fourth 32 bits of KEY5..*/ +#define EFUSE_KEY5_DATA4 0xFFFFFFFF #define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) #define EFUSE_KEY5_DATA4_V 0xFFFFFFFF #define EFUSE_KEY5_DATA4_S 0 #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) /* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF +/*description: Stores the fifth 32 bits of KEY5..*/ +#define EFUSE_KEY5_DATA5 0xFFFFFFFF #define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) #define EFUSE_KEY5_DATA5_V 0xFFFFFFFF #define EFUSE_KEY5_DATA5_S 0 #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) /* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF +/*description: Stores the sixth 32 bits of KEY5..*/ +#define EFUSE_KEY5_DATA6 0xFFFFFFFF #define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) #define EFUSE_KEY5_DATA6_V 0xFFFFFFFF #define EFUSE_KEY5_DATA6_S 0 #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) /* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF +/*description: Stores the seventh 32 bits of KEY5..*/ +#define EFUSE_KEY5_DATA7 0xFFFFFFFF #define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) #define EFUSE_KEY5_DATA7_V 0xFFFFFFFF #define EFUSE_KEY5_DATA7_S 0 #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15C) /* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF +/*description: Stores the 0th 32 bits of the 2nd part of system data..*/ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) #define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_0_S 0 #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) /* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF +/*description: Stores the 1st 32 bits of the 2nd part of system data..*/ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) #define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_1_S 0 #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) /* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF +/*description: Stores the 2nd 32 bits of the 2nd part of system data..*/ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) #define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_2_S 0 #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) /* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF +/*description: Stores the 3rd 32 bits of the 2nd part of system data..*/ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) #define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_3_S 0 #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16C) /* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF +/*description: Stores the 4th 32 bits of the 2nd part of system data..*/ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) #define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_4_S 0 #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) /* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF +/*description: Stores the 5th 32 bits of the 2nd part of system data..*/ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) #define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_5_S 0 #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) /* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF +/*description: Stores the 6th 32 bits of the 2nd part of system data..*/ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) #define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_6_S 0 #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) /* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF +/*description: Stores the 7th 32 bits of the 2nd part of system data..*/ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) #define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART2_7_S 0 #define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17C) /* EFUSE_VDD_SPI_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 #define EFUSE_VDD_SPI_DREFH_ERR_M ((EFUSE_VDD_SPI_DREFH_ERR_V)<<(EFUSE_VDD_SPI_DREFH_ERR_S)) #define EFUSE_VDD_SPI_DREFH_ERR_V 0x3 #define EFUSE_VDD_SPI_DREFH_ERR_S 30 /* EFUSE_VDD_SPI_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: If VDD_SPI_MODECURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) #define EFUSE_VDD_SPI_MODECURLIM_ERR_M (BIT(29)) #define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x1 #define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 /* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 #define EFUSE_BTLC_GPIO_ENABLE_ERR_M ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S)) #define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x3 #define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 /* EFUSE_EXT_PHY_ENABLE_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: If EXT_PHY_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26)) #define EFUSE_EXT_PHY_ENABLE_ERR_M (BIT(26)) #define EFUSE_EXT_PHY_ENABLE_ERR_V 0x1 #define EFUSE_EXT_PHY_ENABLE_ERR_S 26 /* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) #define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(25)) #define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 #define EFUSE_USB_EXCHG_PINS_ERR_S 25 /* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFL_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_USB_DREFL_ERR 0x00000003 #define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) #define EFUSE_USB_DREFL_ERR_V 0x3 #define EFUSE_USB_DREFL_ERR_S 23 /* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFH_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_USB_DREFH_ERR 0x00000003 #define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) #define EFUSE_USB_DREFH_ERR_V 0x3 #define EFUSE_USB_DREFH_ERR_S 21 /* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/* EFUSE_HARD_DIS_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: If HARD_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_HARD_DIS_JTAG_ERR (BIT(19)) -#define EFUSE_HARD_DIS_JTAG_ERR_M (BIT(19)) -#define EFUSE_HARD_DIS_JTAG_ERR_V 0x1 -#define EFUSE_HARD_DIS_JTAG_ERR_S 19 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 1'b0 ; */ -/*description: If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 +/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 #define EFUSE_SOFT_DIS_JTAG_ERR_M ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S)) #define EFUSE_SOFT_DIS_JTAG_ERR_V 0x7 #define EFUSE_SOFT_DIS_JTAG_ERR_S 16 /* EFUSE_DIS_APP_CPU_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: If DIS_APP_CPU is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_APP_CPU_ERR (BIT(15)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_APP_CPU_ERR (BIT(15)) #define EFUSE_DIS_APP_CPU_ERR_M (BIT(15)) #define EFUSE_DIS_APP_CPU_ERR_V 0x1 #define EFUSE_DIS_APP_CPU_ERR_S 15 /* EFUSE_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: If DIS_CAN is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_CAN_ERR (BIT(14)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_CAN_ERR (BIT(14)) #define EFUSE_DIS_CAN_ERR_M (BIT(14)) #define EFUSE_DIS_CAN_ERR_V 0x1 #define EFUSE_DIS_CAN_ERR_S 14 /* EFUSE_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If DIS_USB is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_ERR (BIT(13)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_USB_ERR (BIT(13)) #define EFUSE_DIS_USB_ERR_M (BIT(13)) #define EFUSE_DIS_USB_ERR_V 0x1 #define EFUSE_DIS_USB_ERR_S 13 /* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 /* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_DCACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) #define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (BIT(11)) #define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x1 #define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 /* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 #define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 /* EFUSE_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If DIS_DCACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) #define EFUSE_DIS_DCACHE_ERR_M (BIT(9)) #define EFUSE_DIS_DCACHE_ERR_V 0x1 #define EFUSE_DIS_DCACHE_ERR_S 9 /* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If DIS_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_V 0x1 #define EFUSE_DIS_ICACHE_ERR_S 8 /* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) #define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) #define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 #define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 /* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ -#define EFUSE_RD_DIS_ERR 0x0000007F +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_RD_DIS_ERR 0x0000007F #define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) #define EFUSE_RD_DIS_ERR_V 0x7F #define EFUSE_RD_DIS_ERR_S 0 #define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) /* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F #define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) #define EFUSE_KEY_PURPOSE_1_ERR_V 0xF #define EFUSE_KEY_PURPOSE_1_ERR_S 28 /* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F #define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) #define EFUSE_KEY_PURPOSE_0_ERR_V 0xF #define EFUSE_KEY_PURPOSE_0_ERR_S 24 /* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 /* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 /* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 /* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 /* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 #define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) #define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 #define EFUSE_WDT_DELAY_SEL_ERR_S 16 /* EFUSE_VDD_SPI_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DCAP is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 #define EFUSE_VDD_SPI_DCAP_ERR_M ((EFUSE_VDD_SPI_DCAP_ERR_V)<<(EFUSE_VDD_SPI_DCAP_ERR_S)) #define EFUSE_VDD_SPI_DCAP_ERR_V 0x3 #define EFUSE_VDD_SPI_DCAP_ERR_S 14 /* EFUSE_VDD_SPI_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_INIT is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 #define EFUSE_VDD_SPI_INIT_ERR_M ((EFUSE_VDD_SPI_INIT_ERR_V)<<(EFUSE_VDD_SPI_INIT_ERR_S)) #define EFUSE_VDD_SPI_INIT_ERR_V 0x3 #define EFUSE_VDD_SPI_INIT_ERR_S 12 -/* EFUSE_VDD_SPI_DCURLIM_ERR : RO ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: If any bit in VDD_SPI_DCURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 +/* EFUSE_VDD_SPI_DCURLIM_ERR : RO ;bitpos:[11:9]] ;default: 3'h0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 #define EFUSE_VDD_SPI_DCURLIM_ERR_M ((EFUSE_VDD_SPI_DCURLIM_ERR_V)<<(EFUSE_VDD_SPI_DCURLIM_ERR_S)) #define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x7 #define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 /* EFUSE_VDD_SPI_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If VDD_SPI_ENCURLIM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) #define EFUSE_VDD_SPI_ENCURLIM_ERR_M (BIT(8)) #define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x1 #define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 /* EFUSE_VDD_SPI_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: If VDD_SPI_EN_INIT is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) #define EFUSE_VDD_SPI_EN_INIT_ERR_M (BIT(7)) #define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x1 #define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 /* EFUSE_VDD_SPI_FORCE_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: If VDD_SPI_FORCE is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) #define EFUSE_VDD_SPI_FORCE_ERR_M (BIT(6)) #define EFUSE_VDD_SPI_FORCE_ERR_V 0x1 #define EFUSE_VDD_SPI_FORCE_ERR_S 6 /* EFUSE_VDD_SPI_TIEH_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If VDD_SPI_TIEH is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) #define EFUSE_VDD_SPI_TIEH_ERR_M (BIT(5)) #define EFUSE_VDD_SPI_TIEH_ERR_V 0x1 #define EFUSE_VDD_SPI_TIEH_ERR_S 5 /* EFUSE_VDD_SPI_XPD_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If VDD_SPI_XPD is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) #define EFUSE_VDD_SPI_XPD_ERR_M (BIT(4)) #define EFUSE_VDD_SPI_XPD_ERR_V 0x1 #define EFUSE_VDD_SPI_XPD_ERR_S 4 /* EFUSE_VDD_SPI_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 #define EFUSE_VDD_SPI_DREFL_ERR_M ((EFUSE_VDD_SPI_DREFL_ERR_V)<<(EFUSE_VDD_SPI_DREFL_ERR_S)) #define EFUSE_VDD_SPI_DREFL_ERR_V 0x3 #define EFUSE_VDD_SPI_DREFL_ERR_S 2 /* EFUSE_VDD_SPI_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: If any bit in VDD_SPI_DREFM is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 #define EFUSE_VDD_SPI_DREFM_ERR_M ((EFUSE_VDD_SPI_DREFM_ERR_V)<<(EFUSE_VDD_SPI_DREFM_ERR_S)) #define EFUSE_VDD_SPI_DREFM_ERR_V 0x3 #define EFUSE_VDD_SPI_DREFM_ERR_S 0 #define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) /* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_FLASH_TPUW_ERR 0x0000000F #define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) #define EFUSE_FLASH_TPUW_ERR_V 0xF #define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0_ERR 0x0000003F -#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x3F -#define EFUSE_RPT4_RESERVED0_ERR_S 22 +/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO ;bitpos:[27:26] ;default: 2'h0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003 +#define EFUSE_POWER_GLITCH_DSENSE_ERR_M ((EFUSE_POWER_GLITCH_DSENSE_ERR_V)<<(EFUSE_POWER_GLITCH_DSENSE_ERR_S)) +#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x3 +#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 26 +/* EFUSE_USB_PHY_SEL_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) +#define EFUSE_USB_PHY_SEL_ERR_M (BIT(25)) +#define EFUSE_USB_PHY_SEL_ERR_V 0x1 +#define EFUSE_USB_PHY_SEL_ERR_S 25 +/* EFUSE_STRAP_JTAG_SEL_ERR : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_STRAP_JTAG_SEL_ERR (BIT(24)) +#define EFUSE_STRAP_JTAG_SEL_ERR_M (BIT(24)) +#define EFUSE_STRAP_JTAG_SEL_ERR_V 0x1 +#define EFUSE_STRAP_JTAG_SEL_ERR_S 24 +/* EFUSE_DIS_USB_DEVICE_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_USB_DEVICE_ERR (BIT(23)) +#define EFUSE_DIS_USB_DEVICE_ERR_M (BIT(23)) +#define EFUSE_DIS_USB_DEVICE_ERR_V 0x1 +#define EFUSE_DIS_USB_DEVICE_ERR_S 23 +/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[22] ;default: 6'h0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(22)) +#define EFUSE_DIS_USB_JTAG_ERR_M (BIT(22)) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x1 +#define EFUSE_DIS_USB_JTAG_ERR_S 22 /* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 /* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) #define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) #define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 #define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_KEY_PURPOSE_6_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_6 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_6_ERR_M ((EFUSE_KEY_PURPOSE_6_ERR_V)<<(EFUSE_KEY_PURPOSE_6_ERR_S)) -#define EFUSE_KEY_PURPOSE_6_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_6_ERR_S 16 +/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_RPT4_RESERVED0_ERR 0x0000000F +#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) +#define EFUSE_RPT4_RESERVED0_ERR_V 0xF +#define EFUSE_RPT4_RESERVED0_ERR_S 16 /* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F #define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) #define EFUSE_KEY_PURPOSE_5_ERR_V 0xF #define EFUSE_KEY_PURPOSE_5_ERR_S 12 /* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F #define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) #define EFUSE_KEY_PURPOSE_4_ERR_V 0xF #define EFUSE_KEY_PURPOSE_4_ERR_S 8 /* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F #define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) #define EFUSE_KEY_PURPOSE_3_ERR_V 0xF #define EFUSE_KEY_PURPOSE_3_ERR_S 4 /* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F #define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) #define EFUSE_KEY_PURPOSE_2_ERR_V 0xF #define EFUSE_KEY_PURPOSE_2_ERR_S 0 #define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1_ERR 0x00000003 -#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S)) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x3 -#define EFUSE_RPT4_RESERVED1_ERR_S 30 +/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Reserved..*/ +#define EFUSE_RPT4_RESERVED1_ERR (BIT(31)) +#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(31)) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED1_ERR_S 31 +/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define EFUSE_POWERGLITCH_EN_ERR (BIT(30)) +#define EFUSE_POWERGLITCH_EN_ERR_M (BIT(30)) +#define EFUSE_POWERGLITCH_EN_ERR_V 0x1 +#define EFUSE_POWERGLITCH_EN_ERR_S 30 /* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF #define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) #define EFUSE_SECURE_VERSION_ERR_V 0xFFFF #define EFUSE_SECURE_VERSION_ERR_S 14 /* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) #define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13)) #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 #define EFUSE_FORCE_SEND_RESUME_ERR_S 13 -/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If FLASH_ECC_EN_ERR is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_ECC_EN (BIT(12)) -#define EFUSE_FLASH_ECC_EN_M (BIT(12)) -#define EFUSE_FLASH_ECC_EN_V 0x1 -#define EFUSE_FLASH_ECC_EN_S 12 -/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: If any bits in FLASH_PAGE_SIZE is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_PAGE_SIZE 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_M ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S)) -#define EFUSE_FLASH_PAGE_SIZE_V 0x3 -#define EFUSE_FLASH_PAGE_SIZE_S 10 +/* EFUSE_FLASH_ECC_EN_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) +#define EFUSE_FLASH_ECC_EN_ERR_M (BIT(12)) +#define EFUSE_FLASH_ECC_EN_ERR_V 0x1 +#define EFUSE_FLASH_ECC_EN_ERR_S 12 +/* EFUSE_FLASH_PAGE_SIZE_ERR : RO ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003 +#define EFUSE_FLASH_PAGE_SIZE_ERR_M ((EFUSE_FLASH_PAGE_SIZE_ERR_V)<<(EFUSE_FLASH_PAGE_SIZE_ERR_S)) +#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x3 +#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 /* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If FLASH_TYPE is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) #define EFUSE_FLASH_TYPE_ERR_M (BIT(9)) #define EFUSE_FLASH_TYPE_ERR_V 0x1 #define EFUSE_FLASH_TYPE_ERR_S 9 /* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/ -#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) #define EFUSE_PIN_POWER_SELECTION_ERR_M (BIT(8)) #define EFUSE_PIN_POWER_SELECTION_ERR_V 0x1 #define EFUSE_PIN_POWER_SELECTION_ERR_S 8 /* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 #define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 #define EFUSE_UART_PRINT_CONTROL_ERR_S 6 /* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 /* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If DIS_USB_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) #define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (BIT(4)) #define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x1 #define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 /* EFUSE_FLASH_ECC_MODE_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: If FLASH_ECC_MODE is 1*/ -#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) #define EFUSE_FLASH_ECC_MODE_ERR_M (BIT(3)) #define EFUSE_FLASH_ECC_MODE_ERR_V 0x1 #define EFUSE_FLASH_ECC_MODE_ERR_S 3 /* EFUSE_UART_PRINT_CHANNEL_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) #define EFUSE_UART_PRINT_CHANNEL_ERR_M (BIT(2)) #define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x1 #define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 /* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: If DIS_LEGACY_SPI_BOOT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) #define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (BIT(1)) #define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x1 #define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 /* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 #define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) -/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_M ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S)) -#define EFUSE_RPT4_RESERVED4_ERR_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_S 0 +/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: If any bits in this filed are 1, then it indicates a programming error..*/ +#define EFUSE_RPT4_RESERVED2_ERR 0x00FFFFFF +#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) +#define EFUSE_RPT4_RESERVED2_ERR_V 0xFFFFFF +#define EFUSE_RPT4_RESERVED2_ERR_S 0 #define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1C0) /* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY4_FAIL (BIT(31)) +/*description: 0: Means no failure and that the data of key4 is reliable 1: Means that programm +ing key4 failed and the number of error bytes is over 6..*/ +#define EFUSE_KEY4_FAIL (BIT(31)) #define EFUSE_KEY4_FAIL_M (BIT(31)) #define EFUSE_KEY4_FAIL_V 0x1 #define EFUSE_KEY4_FAIL_S 31 /* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_KEY4_ERR_NUM 0x00000007 #define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) #define EFUSE_KEY4_ERR_NUM_V 0x7 #define EFUSE_KEY4_ERR_NUM_S 28 /* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY3_FAIL (BIT(27)) +/*description: 0: Means no failure and that the data of key3 is reliable 1: Means that programm +ing key3 failed and the number of error bytes is over 6..*/ +#define EFUSE_KEY3_FAIL (BIT(27)) #define EFUSE_KEY3_FAIL_M (BIT(27)) #define EFUSE_KEY3_FAIL_V 0x1 #define EFUSE_KEY3_FAIL_S 27 /* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_KEY3_ERR_NUM 0x00000007 #define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) #define EFUSE_KEY3_ERR_NUM_V 0x7 #define EFUSE_KEY3_ERR_NUM_S 24 /* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY2_FAIL (BIT(23)) +/*description: 0: Means no failure and that the data of key2 is reliable 1: Means that programm +ing key2 failed and the number of error bytes is over 6..*/ +#define EFUSE_KEY2_FAIL (BIT(23)) #define EFUSE_KEY2_FAIL_M (BIT(23)) #define EFUSE_KEY2_FAIL_V 0x1 #define EFUSE_KEY2_FAIL_S 23 /* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_KEY2_ERR_NUM 0x00000007 #define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) #define EFUSE_KEY2_ERR_NUM_V 0x7 #define EFUSE_KEY2_ERR_NUM_S 20 /* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY1_FAIL (BIT(19)) +/*description: 0: Means no failure and that the data of key1 is reliable 1: Means that programm +ing key1 failed and the number of error bytes is over 6..*/ +#define EFUSE_KEY1_FAIL (BIT(19)) #define EFUSE_KEY1_FAIL_M (BIT(19)) #define EFUSE_KEY1_FAIL_V 0x1 #define EFUSE_KEY1_FAIL_S 19 /* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_KEY1_ERR_NUM 0x00000007 #define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) #define EFUSE_KEY1_ERR_NUM_V 0x7 #define EFUSE_KEY1_ERR_NUM_S 16 /* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY0_FAIL (BIT(15)) +/*description: 0: Means no failure and that the data of key0 is reliable 1: Means that programm +ing key0 failed and the number of error bytes is over 6..*/ +#define EFUSE_KEY0_FAIL (BIT(15)) #define EFUSE_KEY0_FAIL_M (BIT(15)) #define EFUSE_KEY0_FAIL_V 0x1 #define EFUSE_KEY0_FAIL_S 15 /* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_KEY0_ERR_NUM 0x00000007 #define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) #define EFUSE_KEY0_ERR_NUM_V 0x7 #define EFUSE_KEY0_ERR_NUM_S 12 /* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the user data is reliable 1: Means - that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_USR_DATA_FAIL (BIT(11)) +/*description: 0: Means no failure and that the user data is reliable 1: Means that programming + user data failed and the number of error bytes is over 6..*/ +#define EFUSE_USR_DATA_FAIL (BIT(11)) #define EFUSE_USR_DATA_FAIL_M (BIT(11)) #define EFUSE_USR_DATA_FAIL_V 0x1 #define EFUSE_USR_DATA_FAIL_S 11 /* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007 #define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) #define EFUSE_USR_DATA_ERR_NUM_V 0x7 #define EFUSE_USR_DATA_ERR_NUM_S 8 /* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable - 1: Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) +/*description: 0: Means no failure and that the data of system part1 is reliable 1: Means that +programming user data failed and the number of error bytes is over 6..*/ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) #define EFUSE_SYS_PART1_FAIL_M (BIT(7)) #define EFUSE_SYS_PART1_FAIL_V 0x1 #define EFUSE_SYS_PART1_FAIL_S 7 /* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART1_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_SYS_PART1_NUM 0x00000007 #define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) #define EFUSE_SYS_PART1_NUM_V 0x7 #define EFUSE_SYS_PART1_NUM_S 4 /* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable - 1: Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that pr +ogramming user data failed and the number of error bytes is over 6..*/ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) #define EFUSE_MAC_SPI_8M_FAIL_M (BIT(3)) #define EFUSE_MAC_SPI_8M_FAIL_V 0x1 #define EFUSE_MAC_SPI_8M_FAIL_S 3 /* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 #define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) #define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 #define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 #define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1C4) /* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part2 is reliable - 1: Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) +/*description: 0: Means no failure and that the data of system part2 is reliable 1: Means that +programming user data failed and the number of error bytes is over 6..*/ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) #define EFUSE_SYS_PART2_FAIL_M (BIT(7)) #define EFUSE_SYS_PART2_FAIL_V 0x1 #define EFUSE_SYS_PART2_FAIL_S 7 /* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 #define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) #define EFUSE_SYS_PART2_ERR_NUM_V 0x7 #define EFUSE_SYS_PART2_ERR_NUM_S 4 /* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of KEY5 is reliable 1: - Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY5_FAIL (BIT(3)) +/*description: 0: Means no failure and that the data of KEY5 is reliable 1: Means that programm +ing user data failed and the number of error bytes is over 6..*/ +#define EFUSE_KEY5_FAIL (BIT(3)) #define EFUSE_KEY5_FAIL_M (BIT(3)) #define EFUSE_KEY5_FAIL_V 0x1 #define EFUSE_KEY5_FAIL_S 3 /* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 +/*description: The value of this signal means the number of error bytes..*/ +#define EFUSE_KEY5_ERR_NUM 0x00000007 #define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) #define EFUSE_KEY5_ERR_NUM_V 0x7 #define EFUSE_KEY5_ERR_NUM_S 0 #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1C8) /* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory.*/ -#define EFUSE_CLK_EN (BIT(16)) +/*description: Set this bit and force to enable clock signal of eFuse memory..*/ +#define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (BIT(16)) #define EFUSE_CLK_EN_V 0x1 #define EFUSE_CLK_EN_S 16 /* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode.*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) +/*description: Set this bit to force eFuse SRAM into working mode..*/ +#define EFUSE_MEM_FORCE_PU (BIT(2)) #define EFUSE_MEM_FORCE_PU_M (BIT(2)) #define EFUSE_MEM_FORCE_PU_V 0x1 #define EFUSE_MEM_FORCE_PU_S 2 /* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_V 0x1 #define EFUSE_MEM_CLK_FORCE_ON_S 1 /* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ -#define EFUSE_MEM_FORCE_PD (BIT(0)) +/*description: Set this bit to force eFuse SRAM into power-saving mode..*/ +#define EFUSE_MEM_FORCE_PD (BIT(0)) #define EFUSE_MEM_FORCE_PD_M (BIT(0)) #define EFUSE_MEM_FORCE_PD_V 0x1 #define EFUSE_MEM_FORCE_PD_S 0 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ -#define EFUSE_OP_CODE 0x0000FFFF +/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command..*/ +#define EFUSE_OP_CODE 0x0000FFFF #define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) #define EFUSE_OP_CODE_V 0xFFFF #define EFUSE_OP_CODE_S 0 #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0) /* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: Indicates the number of error bits during programming BLOCK0.*/ -#define EFUSE_REPEAT_ERR_CNT 0x000000FF +/*description: Indicates the number of error bits during programming BLOCK0..*/ +#define EFUSE_REPEAT_ERR_CNT 0x000000FF #define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) #define EFUSE_REPEAT_ERR_CNT_V 0xFF #define EFUSE_REPEAT_ERR_CNT_S 10 /* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_IS_SW.*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +/*description: The value of OTP_VDDQ_IS_SW..*/ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) #define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) #define EFUSE_OTP_VDDQ_IS_SW_V 0x1 #define EFUSE_OTP_VDDQ_IS_SW_S 9 /* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of OTP_PGENB_SW.*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) +/*description: The value of OTP_PGENB_SW..*/ +#define EFUSE_OTP_PGENB_SW (BIT(8)) #define EFUSE_OTP_PGENB_SW_M (BIT(8)) #define EFUSE_OTP_PGENB_SW_V 0x1 #define EFUSE_OTP_PGENB_SW_S 8 /* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of OTP_CSB_SW.*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) +/*description: The value of OTP_CSB_SW..*/ +#define EFUSE_OTP_CSB_SW (BIT(7)) #define EFUSE_OTP_CSB_SW_M (BIT(7)) #define EFUSE_OTP_CSB_SW_V 0x1 #define EFUSE_OTP_CSB_SW_S 7 /* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of OTP_STROBE_SW.*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) +/*description: The value of OTP_STROBE_SW..*/ +#define EFUSE_OTP_STROBE_SW (BIT(6)) #define EFUSE_OTP_STROBE_SW_M (BIT(6)) #define EFUSE_OTP_STROBE_SW_V 0x1 #define EFUSE_OTP_STROBE_SW_S 6 /* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2.*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +/*description: The value of OTP_VDDQ_C_SYNC2..*/ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) #define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) #define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 #define EFUSE_OTP_VDDQ_C_SYNC2_S 5 /* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of OTP_LOAD_SW.*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) +/*description: The value of OTP_LOAD_SW..*/ +#define EFUSE_OTP_LOAD_SW (BIT(4)) #define EFUSE_OTP_LOAD_SW_M (BIT(4)) #define EFUSE_OTP_LOAD_SW_V 0x1 #define EFUSE_OTP_LOAD_SW_S 4 /* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine.*/ -#define EFUSE_STATE 0x0000000F +/*description: Indicates the state of the eFuse state machine..*/ +#define EFUSE_STATE 0x0000000F #define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) #define EFUSE_STATE_V 0xF #define EFUSE_STATE_S 0 #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1D4) /* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds - to block number 0-10 respectively.*/ -#define EFUSE_BLK_NUM 0x0000000F +/*description: The serial number of the block to be programmed. Value 0-10 corresponds to block + number 0-10, respectively..*/ +#define EFUSE_BLK_NUM 0x0000000F #define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) #define EFUSE_BLK_NUM_V 0xF #define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to send programming command.*/ -#define EFUSE_PGM_CMD (BIT(1)) +/* EFUSE_PGM_CMD : R/WS/SC ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to send programming command..*/ +#define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (BIT(1)) #define EFUSE_PGM_CMD_V 0x1 #define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to send read command.*/ -#define EFUSE_READ_CMD (BIT(0)) +/* EFUSE_READ_CMD : R/WS/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to send read command..*/ +#define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (BIT(0)) #define EFUSE_READ_CMD_V 0x1 #define EFUSE_READ_CMD_S 0 #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1D8) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +/* EFUSE_PGM_DONE_INT_RAW : R/WC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit signal for pgm_done interrupt..*/ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) #define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) #define EFUSE_PGM_DONE_INT_RAW_V 0x1 #define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +/* EFUSE_READ_DONE_INT_RAW : R/WC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit signal for read_done interrupt..*/ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) #define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) #define EFUSE_READ_DONE_INT_RAW_V 0x1 #define EFUSE_READ_DONE_INT_RAW_S 0 #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1DC) /* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +/*description: The status signal for pgm_done interrupt..*/ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) #define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) #define EFUSE_PGM_DONE_INT_ST_V 0x1 #define EFUSE_PGM_DONE_INT_ST_S 1 /* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) +/*description: The status signal for read_done interrupt..*/ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) #define EFUSE_READ_DONE_INT_ST_M (BIT(0)) #define EFUSE_READ_DONE_INT_ST_V 0x1 #define EFUSE_READ_DONE_INT_ST_S 0 #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1E0) /* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +/*description: The enable signal for pgm_done interrupt..*/ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) #define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) #define EFUSE_PGM_DONE_INT_ENA_V 0x1 #define EFUSE_PGM_DONE_INT_ENA_S 1 /* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +/*description: The enable signal for read_done interrupt..*/ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) #define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) #define EFUSE_READ_DONE_INT_ENA_V 0x1 #define EFUSE_READ_DONE_INT_ENA_S 0 #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1E4) /* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +/*description: The clear signal for pgm_done interrupt..*/ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) #define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) #define EFUSE_PGM_DONE_INT_CLR_V 0x1 #define EFUSE_PGM_DONE_INT_CLR_S 1 /* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +/*description: The clear signal for read_done interrupt..*/ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) #define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) #define EFUSE_READ_DONE_INT_CLR_V 0x1 #define EFUSE_READ_DONE_INT_CLR_S 0 #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1E8) /* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Reduces the power supply of the programming voltage.*/ -#define EFUSE_OE_CLR (BIT(17)) +/*description: Reduces the power supply of the programming voltage..*/ +#define EFUSE_OE_CLR (BIT(17)) #define EFUSE_OE_CLR_M (BIT(17)) #define EFUSE_OE_CLR_V 0x1 #define EFUSE_OE_CLR_S 17 /* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage.*/ -#define EFUSE_DAC_NUM 0x000000FF +/*description: Controls the rising period of the programming voltage..*/ +#define EFUSE_DAC_NUM 0x000000FF #define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) #define EFUSE_DAC_NUM_V 0xFF #define EFUSE_DAC_NUM_S 9 /* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Don't care.*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +/*description: Don't care..*/ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) #define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) #define EFUSE_DAC_CLK_PAD_SEL_V 0x1 #define EFUSE_DAC_CLK_PAD_SEL_S 8 /* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage.*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF +/*description: Controls the division factor of the rising clock of the programming voltage..*/ +#define EFUSE_DAC_CLK_DIV 0x000000FF #define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) #define EFUSE_DAC_CLK_DIV_V 0xFF #define EFUSE_DAC_CLK_DIV_S 0 #define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1EC) /* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse.*/ -#define EFUSE_READ_INIT_NUM 0x000000FF +/*description: Configures the initial read time of eFuse..*/ +#define EFUSE_READ_INIT_NUM 0x000000FF #define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) #define EFUSE_READ_INIT_NUM_V 0xFF #define EFUSE_READ_INIT_NUM_S 24 -/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ -/*description: Configures the setup time of read operation.*/ -#define EFUSE_TSUR_A 0x000000FF -#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S)) -#define EFUSE_TSUR_A_V 0xFF -#define EFUSE_TSUR_A_S 16 -/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: Configures the length of pulse of read operation.*/ -#define EFUSE_TRD 0x000000FF -#define EFUSE_TRD_M ((EFUSE_TRD_V)<<(EFUSE_TRD_S)) -#define EFUSE_TRD_V 0xFF -#define EFUSE_TRD_S 8 -/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the hold time of read operation.*/ -#define EFUSE_THR_A 0x000000FF -#define EFUSE_THR_A_M ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S)) -#define EFUSE_THR_A_V 0xFF -#define EFUSE_THR_A_S 0 #define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) -/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */ -/*description: Configures the length of pulse during programming 1 to eFuse.*/ -#define EFUSE_TPGM 0x0000FFFF -#define EFUSE_TPGM_M ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S)) -#define EFUSE_TPGM_V 0xFFFF -#define EFUSE_TPGM_S 16 -/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: Configures the length of pulse during programming 0 to eFuse.*/ -#define EFUSE_TPGM_INACTIVE 0x000000FF -#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S)) -#define EFUSE_TPGM_INACTIVE_V 0xFF -#define EFUSE_TPGM_INACTIVE_S 8 -/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the hold time of programming operation.*/ -#define EFUSE_THP_A 0x000000FF -#define EFUSE_THP_A_M ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S)) -#define EFUSE_THP_A_V 0xFF -#define EFUSE_THP_A_S 0 #define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4) /* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ -/*description: Configures the power up time for VDDQ.*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF +/*description: Configures the power up time for VDDQ..*/ +#define EFUSE_PWR_ON_NUM 0x0000FFFF #define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) #define EFUSE_PWR_ON_NUM_V 0xFFFF #define EFUSE_PWR_ON_NUM_S 8 -/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: Configures the setup time of programming operation.*/ -#define EFUSE_TSUP_A 0x000000FF -#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S)) -#define EFUSE_TSUP_A_V 0xFF -#define EFUSE_TSUP_A_S 0 #define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8) /* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ.*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF +/*description: Configures the power outage time for VDDQ..*/ +#define EFUSE_PWR_OFF_NUM 0x0000FFFF #define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) #define EFUSE_PWR_OFF_NUM_V 0xFFFF #define EFUSE_PWR_OFF_NUM_S 0 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28’h2004270 ; */ -/*description: Stores eFuse version.*/ -#define EFUSE_DATE 0x0FFFFFFF +/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */ +/*description: Stores eFuse version..*/ +#define EFUSE_DATE 0x0FFFFFFF #define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) #define EFUSE_DATE_V 0xFFFFFFF #define EFUSE_DATE_S 0 + #ifdef __cplusplus } #endif + + + +#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h index e4fd4a65fc..a3d9e838ba 100644 --- a/components/soc/esp32s3/include/soc/efuse_struct.h +++ b/components/soc/esp32s3/include/soc/efuse_struct.h @@ -11,116 +11,303 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_EFUSE_STRUCT_H_ +#define _SOC_EFUSE_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { - uint32_t reserved_0; - uint32_t reserved_4; - uint32_t reserved_8; - uint32_t reserved_c; - uint32_t reserved_10; - uint32_t reserved_14; - uint32_t reserved_18; - uint32_t reserved_1c; - uint32_t reserved_20; - uint32_t reserved_24; - uint32_t reserved_28; - uint32_t reserved_2c; - uint32_t reserved_30; - uint32_t reserved_34; - uint32_t reserved_38; - uint32_t reserved_3c; - uint32_t reserved_40; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; + uint32_t pgm_data0; + uint32_t pgm_data1; + uint32_t pgm_data2; + uint32_t pgm_data3; + uint32_t pgm_data4; + uint32_t pgm_data5; + uint32_t pgm_data6; + uint32_t pgm_data7; + uint32_t pgm_check_value0; + uint32_t pgm_check_value1; + uint32_t pgm_check_value2; + uint32_t rd_wr_dis; + union { + struct { + uint32_t reg_rd_dis : 7; /*Set this bit to disable reading from BlOCK4-10.*/ + uint32_t reg_dis_rtc_ram_boot : 1; /*Set this bit to disable boot from RTC RAM.*/ + uint32_t reg_dis_icache : 1; /*Set this bit to disable Icache.*/ + uint32_t reg_dis_dcache : 1; /*Set this bit to disable Dcache.*/ + uint32_t reg_dis_download_icache : 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ + uint32_t reg_dis_download_dcache : 1; /*Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ + uint32_t reg_dis_force_download : 1; /*Set this bit to disable the function that forces chip into download mode.*/ + uint32_t reg_dis_usb : 1; /*Set this bit to disable USB function.*/ + uint32_t reg_dis_can : 1; /*Set this bit to disable CAN function.*/ + uint32_t reg_dis_app_cpu : 1; /*Disable app cpu.*/ + uint32_t reg_soft_dis_jtag : 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ + uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ + uint32_t reg_dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ + uint32_t reg_usb_drefh : 2; /*Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.*/ + uint32_t reg_usb_drefl : 2; /*Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.*/ + uint32_t reg_usb_exchg_pins : 1; /*Set this bit to exchange USB D+ and D- pins.*/ + uint32_t reg_ext_phy_enable : 1; /*Set this bit to enable external PHY.*/ + uint32_t reg_btlc_gpio_enable : 2; /*Enable btlc gpio.*/ + uint32_t reg_vdd_spi_modecurlim : 1; /*SPI regulator switches current limit mode.*/ + uint32_t reg_vdd_spi_drefh : 2; /*SPI regulator high voltage reference.*/ + }; + uint32_t val; + } rd_repeat_data0; + union { + struct { + uint32_t reg_vdd_spi_drefm : 2; /*SPI regulator medium voltage reference.*/ + uint32_t reg_vdd_spi_drefl : 2; /*SPI regulator low voltage reference.*/ + uint32_t reg_vdd_spi_xpd : 1; /*SPI regulator power up signal.*/ + uint32_t reg_vdd_spi_tieh : 1; /*SPI regulator output is short connected to VDD3P3_RTC_IO.*/ + uint32_t reg_vdd_spi_force : 1; /*Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ + uint32_t reg_vdd_spi_en_init : 1; /*Set SPI regulator to 0 to configure init[1:0]=0.*/ + uint32_t reg_vdd_spi_encurlim : 1; /*Set SPI regulator to 1 to enable output current limit.*/ + uint32_t reg_vdd_spi_dcurlim : 3; /*Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).*/ + uint32_t reg_vdd_spi_init : 2; /*Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/ + uint32_t reg_vdd_spi_dcap : 2; /*Prevents SPI regulator from overshoot.*/ + uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ + uint32_t reg_spi_boot_crypt_cnt : 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ + uint32_t reg_secure_boot_key_revoke0 : 1; /*Set this bit to enable revoking first secure boot key.*/ + uint32_t reg_secure_boot_key_revoke1 : 1; /*Set this bit to enable revoking second secure boot key.*/ + uint32_t reg_secure_boot_key_revoke2 : 1; /*Set this bit to enable revoking third secure boot key.*/ + uint32_t reg_key_purpose_0 : 4; /*Purpose of Key0.*/ + uint32_t reg_key_purpose_1 : 4; /*Purpose of Key1.*/ + }; + uint32_t val; + } rd_repeat_data1; + union { + struct { + uint32_t reg_key_purpose_2 : 4; /*Purpose of Key2.*/ + uint32_t reg_key_purpose_3 : 4; /*Purpose of Key3.*/ + uint32_t reg_key_purpose_4 : 4; /*Purpose of Key4.*/ + uint32_t reg_key_purpose_5 : 4; /*Purpose of Key5.*/ + uint32_t reg_rpt4_reserved0 : 4; /*Reserved (used for four backups method).*/ + uint32_t reg_secure_boot_en : 1; /*Set this bit to enable secure boot.*/ + uint32_t reg_secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ + uint32_t reg_dis_usb_jtag : 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ + uint32_t reg_dis_usb_device : 1; /*Set this bit to disable usb device.*/ + uint32_t reg_strap_jtag_sel : 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ + uint32_t reg_usb_phy_sel : 1; /*This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.*/ + uint32_t reg_power_glitch_dsense : 2; /*Sample delay configuration of power glitch.*/ + uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.*/ + }; + uint32_t val; + } rd_repeat_data2; + union { + struct { + uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).*/ + uint32_t reg_dis_legacy_spi_boot : 1; /*Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/ + uint32_t reg_uart_print_channel : 1; /*Selectes the default UART print channel. 0: UART0. 1: UART1.*/ + uint32_t reg_flash_ecc_mode : 1; /*Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/ + uint32_t reg_dis_usb_download_mode : 1; /*Set this bit to disable UART download mode through USB.*/ + uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/ + uint32_t reg_uart_print_control : 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ + uint32_t reg_pin_power_selection : 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/ + uint32_t reg_flash_type : 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/ + uint32_t reg_flash_page_size : 2; /*Set Flash page size.*/ + uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/ + uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ + uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ + uint32_t reg_powerglitch_en : 1; /*Set this bit to enable power glitch function.*/ + uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/ + }; + uint32_t val; + } rd_repeat_data3; + union { + struct { + uint32_t reg_rpt4_reserved2 : 24; /*Reserved (used for four backups method).*/ + uint32_t reserved24 : 8; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_data4; + uint32_t rd_mac_spi_sys_0; + union { + struct { + uint32_t reg_mac_1 : 16; /*Stores the high 16 bits of MAC address.*/ + uint32_t reg_spi_pad_conf_0 : 16; /*Stores the zeroth part of SPI_PAD_CONF.*/ + }; + uint32_t val; + } rd_mac_spi_sys_1; + uint32_t rd_mac_spi_sys_2; + union { + struct { + uint32_t reg_spi_pad_conf_2 : 18; /*Stores the second part of SPI_PAD_CONF.*/ + uint32_t reg_sys_data_part0_0 : 14; /*Stores the fist 14 bits of the zeroth part of system data.*/ + }; + uint32_t val; + } rd_mac_spi_sys_3; + uint32_t rd_mac_spi_sys_4; + uint32_t rd_mac_spi_sys_5; + uint32_t rd_sys_part1_data0; + uint32_t rd_sys_part1_data1; + uint32_t rd_sys_part1_data2; + uint32_t rd_sys_part1_data3; + uint32_t rd_sys_part1_data4; + uint32_t rd_sys_part1_data5; + uint32_t rd_sys_part1_data6; + uint32_t rd_sys_part1_data7; + uint32_t rd_usr_data0; + uint32_t rd_usr_data1; + uint32_t rd_usr_data2; + uint32_t rd_usr_data3; + uint32_t rd_usr_data4; + uint32_t rd_usr_data5; + uint32_t rd_usr_data6; + uint32_t rd_usr_data7; + uint32_t rd_key0_data0; + uint32_t rd_key0_data1; + uint32_t rd_key0_data2; + uint32_t rd_key0_data3; + uint32_t rd_key0_data4; + uint32_t rd_key0_data5; + uint32_t rd_key0_data6; + uint32_t rd_key0_data7; + uint32_t rd_key1_data0; + uint32_t rd_key1_data1; + uint32_t rd_key1_data2; + uint32_t rd_key1_data3; + uint32_t rd_key1_data4; + uint32_t rd_key1_data5; + uint32_t rd_key1_data6; + uint32_t rd_key1_data7; + uint32_t rd_key2_data0; + uint32_t rd_key2_data1; + uint32_t rd_key2_data2; + uint32_t rd_key2_data3; + uint32_t rd_key2_data4; + uint32_t rd_key2_data5; + uint32_t rd_key2_data6; + uint32_t rd_key2_data7; + uint32_t rd_key3_data0; + uint32_t rd_key3_data1; + uint32_t rd_key3_data2; + uint32_t rd_key3_data3; + uint32_t rd_key3_data4; + uint32_t rd_key3_data5; + uint32_t rd_key3_data6; + uint32_t rd_key3_data7; + uint32_t rd_key4_data0; + uint32_t rd_key4_data1; + uint32_t rd_key4_data2; + uint32_t rd_key4_data3; + uint32_t rd_key4_data4; + uint32_t rd_key4_data5; + uint32_t rd_key4_data6; + uint32_t rd_key4_data7; + uint32_t rd_key5_data0; + uint32_t rd_key5_data1; + uint32_t rd_key5_data2; + uint32_t rd_key5_data3; + uint32_t rd_key5_data4; + uint32_t rd_key5_data5; + uint32_t rd_key5_data6; + uint32_t rd_key5_data7; + uint32_t rd_sys_part2_data0; + uint32_t rd_sys_part2_data1; + uint32_t rd_sys_part2_data2; + uint32_t rd_sys_part2_data3; + uint32_t rd_sys_part2_data4; + uint32_t rd_sys_part2_data5; + uint32_t rd_sys_part2_data6; + uint32_t rd_sys_part2_data7; + union { + struct { + uint32_t reg_rd_dis_err : 7; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_rtc_ram_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_download_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_download_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_force_download_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_can_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_app_cpu_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_soft_dis_jtag_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_pad_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_usb_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_usb_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_usb_exchg_pins_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_ext_phy_enable_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_btlc_gpio_enable_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_modecurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err0; + union { + struct { + uint32_t reg_vdd_spi_drefm_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_xpd_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_tieh_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_force_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_en_init_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_encurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_dcurlim_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_init_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_dcap_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_wdt_delay_sel_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_spi_boot_crypt_cnt_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_key_revoke0_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_key_revoke1_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_key_revoke2_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_1_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err1; + union { + struct { + uint32_t reg_key_purpose_2_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_3_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_4_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_5_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_rpt4_reserved0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_aggressive_revoke_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_device_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_strap_jtag_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_usb_phy_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_power_glitch_dsense_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_tpuw_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err2; + union { + struct { + uint32_t reg_dis_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_legacy_spi_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_uart_print_channel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_ecc_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_enable_security_download_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_uart_print_control_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_pin_power_selection_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_type_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_page_size_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_powerglitch_en_err : 1; + uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_err3; uint32_t reserved_18c; - uint32_t reserved_190; + union { + struct { + uint32_t reg_rpt4_reserved2_err : 24; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reserved24 : 8; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_err4; uint32_t reserved_194; uint32_t reserved_198; uint32_t reserved_19c; @@ -248,21 +435,12 @@ typedef volatile struct { } dac_conf; union { struct { - uint32_t thr_a: 8; /*Configures the hold time of read operation.*/ - uint32_t trd: 8; /*Configures the length of pulse of read operation.*/ - uint32_t tsur_a: 8; /*Configures the setup time of read operation.*/ - uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/ + uint32_t reserved0 : 24; /*Reserved. (Default read timing parameter)*/ + uint32_t reg_read_init_num : 8; /*Configures the initial read time of eFuse.*/ }; uint32_t val; } rd_tim_conf; - union { - struct { - uint32_t thp_a: 8; /*Configures the hold time of programming operation.*/ - uint32_t tpgm_inactive: 8; /*Configures the length of pulse during programming 0 to eFuse.*/ - uint32_t tpgm: 16; /*Configures the length of pulse during programming 1 to eFuse.*/ - }; - uint32_t val; - } wr_tim_conf0; + uint32_t wr_tim_conf0; union { struct { uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/ @@ -292,3 +470,7 @@ extern efuse_dev_t EFUSE; #ifdef __cplusplus } #endif + + + +#endif /*_SOC_EFUSE_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/extmem_reg.h b/components/soc/esp32s3/include/soc/extmem_reg.h index a9d9e2bf5f..529ecc6ff8 100644 --- a/components/soc/esp32s3/include/soc/extmem_reg.h +++ b/components/soc/esp32s3/include/soc/extmem_reg.h @@ -16,1594 +16,1655 @@ #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) -/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ -#define EXTMEM_DCACHE_BLOCKSIZE_MODE (BIT(3)) -#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M (BIT(3)) -#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x1 +#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) +/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 byt +es.*/ +#define EXTMEM_DCACHE_BLOCKSIZE_MODE 0x00000003 +#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M ((EXTMEM_DCACHE_BLOCKSIZE_MODE_V)<<(EXTMEM_DCACHE_BLOCKSIZE_MODE_S)) +#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x3 #define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3 /* EXTMEM_DCACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to configure cache memory size.0: 32KB 1: 64KB*/ -#define EXTMEM_DCACHE_SIZE_MODE (BIT(2)) +/*description: The bit is used to configure cache memory size.0: 32KB, 1: 64KB.*/ +#define EXTMEM_DCACHE_SIZE_MODE (BIT(2)) #define EXTMEM_DCACHE_SIZE_MODE_M (BIT(2)) #define EXTMEM_DCACHE_SIZE_MODE_V 0x1 #define EXTMEM_DCACHE_SIZE_MODE_S 2 /* EXTMEM_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to activate the data cache. 0: disable 1: enable*/ -#define EXTMEM_DCACHE_ENABLE (BIT(0)) +/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/ +#define EXTMEM_DCACHE_ENABLE (BIT(0)) #define EXTMEM_DCACHE_ENABLE_M (BIT(0)) #define EXTMEM_DCACHE_ENABLE_V 0x1 #define EXTMEM_DCACHE_ENABLE_S 0 -#define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) +#define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) /* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to disable core1 dbus 0: enable 1: disable*/ -#define EXTMEM_DCACHE_SHUT_CORE1_BUS (BIT(1)) +/*description: The bit is used to disable core1 dbus, 0: enable, 1: disable.*/ +#define EXTMEM_DCACHE_SHUT_CORE1_BUS (BIT(1)) #define EXTMEM_DCACHE_SHUT_CORE1_BUS_M (BIT(1)) #define EXTMEM_DCACHE_SHUT_CORE1_BUS_V 0x1 #define EXTMEM_DCACHE_SHUT_CORE1_BUS_S 1 /* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to disable core0 dbus 0: enable 1: disable*/ -#define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0)) +/*description: The bit is used to disable core0 dbus, 0: enable, 1: disable.*/ +#define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0)) #define EXTMEM_DCACHE_SHUT_CORE0_BUS_M (BIT(0)) #define EXTMEM_DCACHE_SHUT_CORE0_BUS_V 0x1 #define EXTMEM_DCACHE_SHUT_CORE0_BUS_S 0 -#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) +#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8) /* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to power dcache tag memory up 0: follow rtc_lslp_pd - 1: power up*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) +/*description: The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power +up.*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(2)) #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 2 /* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd - 1: power down*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) +/*description: The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: powe +r down.*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(1)) #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 1 /* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of dcache tag memory. 1: - close gating 0: open clock gating.*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) +/*description: The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: +open clock gating..*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(0)) #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 0 -#define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C) +#define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0xC) /* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section of prelock function.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) +/*description: The bit is used to enable the second section of prelock function..*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1)) #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 /* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section of prelock function.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) +/*description: The bit is used to enable the first section of prelock function..*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0)) #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x010) +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x10) /* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to configure the first start virtual address - of data prelock which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the first start virtual address of data prelock, +which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)) #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014) +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x14) /* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to configure the second start virtual address - of data prelock which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the second start virtual address of data prelock, + which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)) #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018) +#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18) /* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The bits are used to configure the first length of data locking - which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000FFFF +/*description: The bits are used to configure the first length of data locking, which is combin +ed with DCACHE_PRELOCK_SCT0_ADDR_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000FFFF #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0xFFFF #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16 /* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the second length of data locking - which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000FFFF +/*description: The bits are used to configure the second length of data locking, which is combi +ned with DCACHE_PRELOCK_SCT1_ADDR_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000FFFF #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0xFFFF #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 0 -#define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x01C) -/* EXTMEM_DCACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate unlock/lock operation is finished.*/ -#define EXTMEM_DCACHE_LOCK_DONE (BIT(2)) +#define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x1C) +/* EXTMEM_DCACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to indicate unlock/lock operation is finished..*/ +#define EXTMEM_DCACHE_LOCK_DONE (BIT(2)) #define EXTMEM_DCACHE_LOCK_DONE_M (BIT(2)) #define EXTMEM_DCACHE_LOCK_DONE_V 0x1 #define EXTMEM_DCACHE_LOCK_DONE_S 2 /* EXTMEM_DCACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable unlock operation. It will be cleared - by hardware after unlock operation done.*/ -#define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1)) +/*description: The bit is used to enable unlock operation. It will be cleared by hardware after + unlock operation done..*/ +#define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1)) #define EXTMEM_DCACHE_UNLOCK_ENA_M (BIT(1)) #define EXTMEM_DCACHE_UNLOCK_ENA_V 0x1 #define EXTMEM_DCACHE_UNLOCK_ENA_S 1 /* EXTMEM_DCACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable lock operation. It will be cleared - by hardware after lock operation done.*/ -#define EXTMEM_DCACHE_LOCK_ENA (BIT(0)) +/*description: The bit is used to enable lock operation. It will be cleared by hardware after l +ock operation done..*/ +#define EXTMEM_DCACHE_LOCK_ENA (BIT(0)) #define EXTMEM_DCACHE_LOCK_ENA_M (BIT(0)) #define EXTMEM_DCACHE_LOCK_ENA_V 0x1 #define EXTMEM_DCACHE_LOCK_ENA_S 0 -#define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x020) +#define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x20) /* EXTMEM_DCACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.*/ -#define EXTMEM_DCACHE_LOCK_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address for lock operations. It + should be combined with DCACHE_LOCK_SIZE_REG..*/ +#define EXTMEM_DCACHE_LOCK_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_LOCK_ADDR_M ((EXTMEM_DCACHE_LOCK_ADDR_V)<<(EXTMEM_DCACHE_LOCK_ADDR_S)) #define EXTMEM_DCACHE_LOCK_ADDR_V 0xFFFFFFFF #define EXTMEM_DCACHE_LOCK_ADDR_S 0 -#define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x024) +#define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x24) /* EXTMEM_DCACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the length for lock operations. - The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/ -#define EXTMEM_DCACHE_LOCK_SIZE 0x0000FFFF +/*description: The bits are used to configure the length for lock operations. The bits are the +counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG..*/ +#define EXTMEM_DCACHE_LOCK_SIZE 0x0000FFFF #define EXTMEM_DCACHE_LOCK_SIZE_M ((EXTMEM_DCACHE_LOCK_SIZE_V)<<(EXTMEM_DCACHE_LOCK_SIZE_S)) #define EXTMEM_DCACHE_LOCK_SIZE_V 0xFFFF #define EXTMEM_DCACHE_LOCK_SIZE_S 0 -#define EXTMEM_DCACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x028) +#define EXTMEM_DCACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) /* EXTMEM_DCACHE_SYNC_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate clean/writeback/invalidate operation is finished.*/ -#define EXTMEM_DCACHE_SYNC_DONE (BIT(3)) +/*description: The bit is used to indicate clean/writeback/invalidate operation is finished..*/ +#define EXTMEM_DCACHE_SYNC_DONE (BIT(3)) #define EXTMEM_DCACHE_SYNC_DONE_M (BIT(3)) #define EXTMEM_DCACHE_SYNC_DONE_V 0x1 #define EXTMEM_DCACHE_SYNC_DONE_S 3 /* EXTMEM_DCACHE_CLEAN_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable clean operation. It will be cleared - by hardware after clean operation done.*/ -#define EXTMEM_DCACHE_CLEAN_ENA (BIT(2)) +/*description: The bit is used to enable clean operation. It will be cleared by hardware after +clean operation done..*/ +#define EXTMEM_DCACHE_CLEAN_ENA (BIT(2)) #define EXTMEM_DCACHE_CLEAN_ENA_M (BIT(2)) #define EXTMEM_DCACHE_CLEAN_ENA_V 0x1 #define EXTMEM_DCACHE_CLEAN_ENA_S 2 /* EXTMEM_DCACHE_WRITEBACK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable writeback operation. It will be cleared - by hardware after writeback operation done.*/ -#define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1)) +/*description: The bit is used to enable writeback operation. It will be cleared by hardware af +ter writeback operation done..*/ +#define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1)) #define EXTMEM_DCACHE_WRITEBACK_ENA_M (BIT(1)) #define EXTMEM_DCACHE_WRITEBACK_ENA_V 0x1 #define EXTMEM_DCACHE_WRITEBACK_ENA_S 1 /* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable invalidate operation. It will be cleared - by hardware after invalidate operation done.*/ -#define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0)) +/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a +fter invalidate operation done..*/ +#define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0)) #define EXTMEM_DCACHE_INVALIDATE_ENA_M (BIT(0)) #define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x1 #define EXTMEM_DCACHE_INVALIDATE_ENA_S 0 -#define EXTMEM_DCACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x02C) +#define EXTMEM_DCACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2C) /* EXTMEM_DCACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.*/ -#define EXTMEM_DCACHE_SYNC_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address for clean operations. I +t should be combined with DCACHE_SYNC_SIZE_REG..*/ +#define EXTMEM_DCACHE_SYNC_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_SYNC_ADDR_M ((EXTMEM_DCACHE_SYNC_ADDR_V)<<(EXTMEM_DCACHE_SYNC_ADDR_S)) #define EXTMEM_DCACHE_SYNC_ADDR_V 0xFFFFFFFF #define EXTMEM_DCACHE_SYNC_ADDR_S 0 -#define EXTMEM_DCACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x030) +#define EXTMEM_DCACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30) /* EXTMEM_DCACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ -/*description: The bits are used to configure the length for sync operations. - The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/ -#define EXTMEM_DCACHE_SYNC_SIZE 0x007FFFFF +/*description: The bits are used to configure the length for sync operations. The bits are the +counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG..*/ +#define EXTMEM_DCACHE_SYNC_SIZE 0x007FFFFF #define EXTMEM_DCACHE_SYNC_SIZE_M ((EXTMEM_DCACHE_SYNC_SIZE_V)<<(EXTMEM_DCACHE_SYNC_SIZE_S)) #define EXTMEM_DCACHE_SYNC_SIZE_V 0x7FFFFF #define EXTMEM_DCACHE_SYNC_SIZE_S 0 -#define EXTMEM_DCACHE_OCCUPY_CTRL_REG (DR_REG_EXTMEM_BASE + 0x034) -/* EXTMEM_DCACHE_OCCUPY_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate occupy operation is finished.*/ -#define EXTMEM_DCACHE_OCCUPY_DONE (BIT(1)) +#define EXTMEM_DCACHE_OCCUPY_CTRL_REG (DR_REG_EXTMEM_BASE + 0x34) +/* EXTMEM_DCACHE_OCCUPY_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to indicate occupy operation is finished..*/ +#define EXTMEM_DCACHE_OCCUPY_DONE (BIT(1)) #define EXTMEM_DCACHE_OCCUPY_DONE_M (BIT(1)) #define EXTMEM_DCACHE_OCCUPY_DONE_V 0x1 #define EXTMEM_DCACHE_OCCUPY_DONE_S 1 /* EXTMEM_DCACHE_OCCUPY_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable occupy operation. It will be cleared - by hardware after issuing Auot-Invalidate Operation.*/ -#define EXTMEM_DCACHE_OCCUPY_ENA (BIT(0)) +/*description: The bit is used to enable occupy operation. It will be cleared by hardware after + issuing Auot-Invalidate Operation..*/ +#define EXTMEM_DCACHE_OCCUPY_ENA (BIT(0)) #define EXTMEM_DCACHE_OCCUPY_ENA_M (BIT(0)) #define EXTMEM_DCACHE_OCCUPY_ENA_V 0x1 #define EXTMEM_DCACHE_OCCUPY_ENA_S 0 -#define EXTMEM_DCACHE_OCCUPY_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038) +#define EXTMEM_DCACHE_OCCUPY_ADDR_REG (DR_REG_EXTMEM_BASE + 0x38) /* EXTMEM_DCACHE_OCCUPY_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.*/ -#define EXTMEM_DCACHE_OCCUPY_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address for occupy operation. I +t should be combined with DCACHE_OCCUPY_SIZE_REG..*/ +#define EXTMEM_DCACHE_OCCUPY_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_OCCUPY_ADDR_M ((EXTMEM_DCACHE_OCCUPY_ADDR_V)<<(EXTMEM_DCACHE_OCCUPY_ADDR_S)) #define EXTMEM_DCACHE_OCCUPY_ADDR_V 0xFFFFFFFF #define EXTMEM_DCACHE_OCCUPY_ADDR_S 0 -#define EXTMEM_DCACHE_OCCUPY_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C) +#define EXTMEM_DCACHE_OCCUPY_SIZE_REG (DR_REG_EXTMEM_BASE + 0x3C) /* EXTMEM_DCACHE_OCCUPY_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the length for occupy operation. - The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/ -#define EXTMEM_DCACHE_OCCUPY_SIZE 0x0000FFFF +/*description: The bits are used to configure the length for occupy operation. The bits are the + counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG..*/ +#define EXTMEM_DCACHE_OCCUPY_SIZE 0x0000FFFF #define EXTMEM_DCACHE_OCCUPY_SIZE_M ((EXTMEM_DCACHE_OCCUPY_SIZE_V)<<(EXTMEM_DCACHE_OCCUPY_SIZE_S)) #define EXTMEM_DCACHE_OCCUPY_SIZE_V 0xFFFF #define EXTMEM_DCACHE_OCCUPY_SIZE_S 0 -#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040) +#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x40) /* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to configure the direction of preload operation. - 1: descending 0: ascending.*/ -#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) +/*description: The bit is used to configure the direction of preload operation. 1: descending, +0: ascending..*/ +#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) #define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2)) #define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1 #define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 -/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate preload operation is finished.*/ -#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) +/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to indicate preload operation is finished..*/ +#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) #define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1)) #define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1 #define EXTMEM_DCACHE_PRELOAD_DONE_S 1 /* EXTMEM_DCACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable preload operation. It will be cleared - by hardware after preload operation done.*/ -#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) +/*description: The bit is used to enable preload operation. It will be cleared by hardware afte +r preload operation done..*/ +#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) #define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0)) #define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1 #define EXTMEM_DCACHE_PRELOAD_ENA_S 0 -#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x044) +#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x44) /* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.*/ -#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address for preload operation. +It should be combined with DCACHE_PRELOAD_SIZE_REG..*/ +#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S)) #define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF #define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x048) +#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x48) /* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the length for preload operation. - The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/ -#define EXTMEM_DCACHE_PRELOAD_SIZE 0x0000FFFF +/*description: The bits are used to configure the length for preload operation. The bits are th +e counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG...*/ +#define EXTMEM_DCACHE_PRELOAD_SIZE 0x0000FFFF #define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S)) #define EXTMEM_DCACHE_PRELOAD_SIZE_V 0xFFFF #define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x04C) +#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4C) +/* EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to clear autoload buffer in dcache..*/ +#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9)) +#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_M (BIT(9)) +#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S 9 /* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */ -/*description: The bits are used to configure the numbers of the cache block - for the issuing autoload operation.*/ -#define EXTMEM_DCACHE_AUTOLOAD_SIZE 0x00000003 +/*description: The bits are used to configure the numbers of the cache block for the issuing au +toload operation..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SIZE 0x00000003 #define EXTMEM_DCACHE_AUTOLOAD_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SIZE_S)) #define EXTMEM_DCACHE_AUTOLOAD_SIZE_V 0x3 #define EXTMEM_DCACHE_AUTOLOAD_SIZE_S 7 /* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ -/*description: The bits are used to configure trigger conditions for autoload. - 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ -#define EXTMEM_DCACHE_AUTOLOAD_RQST 0x00000003 +/*description: The bits are used to configure trigger conditions for autoload. 0/3: cache miss, + 1: cache hit, 2: both cache miss and hit..*/ +#define EXTMEM_DCACHE_AUTOLOAD_RQST 0x00000003 #define EXTMEM_DCACHE_AUTOLOAD_RQST_M ((EXTMEM_DCACHE_AUTOLOAD_RQST_V)<<(EXTMEM_DCACHE_AUTOLOAD_RQST_S)) #define EXTMEM_DCACHE_AUTOLOAD_RQST_V 0x3 #define EXTMEM_DCACHE_AUTOLOAD_RQST_S 5 /* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bits are used to configure the direction of autoload. 1: - descending 0: ascending.*/ -#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4)) +/*description: The bits are used to configure the direction of autoload. 1: descending, 0: asce +nding..*/ +#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4)) #define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(4)) #define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1 #define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 4 -/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate autoload operation is finished.*/ -#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(3)) +/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: The bit is used to indicate autoload operation is finished..*/ +#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(3)) #define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(3)) #define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1 #define EXTMEM_DCACHE_AUTOLOAD_DONE_S 3 /* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable and disable autoload operation. It - is combined with dcache_autoload_done. 1: enable 0: disable.*/ -#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(2)) +/*description: The bit is used to enable and disable autoload operation. It is combined with dc +ache_autoload_done. 1: enable, 0: disable. .*/ +#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(2)) #define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(2)) #define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1 #define EXTMEM_DCACHE_AUTOLOAD_ENA_S 2 /* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bits are used to enable the second section for autoload operation.*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1)) +/*description: The bits are used to enable the second section for autoload operation..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1)) #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 1 /* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bits are used to enable the first section for autoload operation.*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(0)) +/*description: The bits are used to enable the first section for autoload operation..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(0)) #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x050) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x50) /* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of the - first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address of the first section fo +r autoload operation. It should be combined with dcache_autoload_sct0_ena..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x054) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x54) /* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: The bits are used to configure the length of the first section - for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF +/*description: The bits are used to configure the length of the first section for autoload oper +ation. It should be combined with dcache_autoload_sct0_ena..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)) #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x058) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x58) /* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of the - second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address of the second section f +or autoload operation. It should be combined with dcache_autoload_sct1_ena..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)) #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x05C) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x5C) /* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: The bits are used to configure the length of the second section - for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF +/*description: The bits are used to configure the length of the second section for autoload ope +ration. It should be combined with dcache_autoload_sct1_ena..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)) #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 -#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x060) +#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x60) /* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ -#define EXTMEM_ICACHE_BLOCKSIZE_MODE (BIT(3)) +/*description: The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes.*/ +#define EXTMEM_ICACHE_BLOCKSIZE_MODE (BIT(3)) #define EXTMEM_ICACHE_BLOCKSIZE_MODE_M (BIT(3)) #define EXTMEM_ICACHE_BLOCKSIZE_MODE_V 0x1 #define EXTMEM_ICACHE_BLOCKSIZE_MODE_S 3 /* EXTMEM_ICACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to configure cache memory size.0: 16KB 1: 32KB*/ -#define EXTMEM_ICACHE_SIZE_MODE (BIT(2)) +/*description: The bit is used to configure cache memory size.0: 16KB, 1: 32KB.*/ +#define EXTMEM_ICACHE_SIZE_MODE (BIT(2)) #define EXTMEM_ICACHE_SIZE_MODE_M (BIT(2)) #define EXTMEM_ICACHE_SIZE_MODE_V 0x1 #define EXTMEM_ICACHE_SIZE_MODE_S 2 /* EXTMEM_ICACHE_WAY_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to configure cache way mode.0: 4-way 1: 8-way*/ -#define EXTMEM_ICACHE_WAY_MODE (BIT(1)) +/*description: The bit is used to configure cache way mode.0: 4-way, 1: 8-way.*/ +#define EXTMEM_ICACHE_WAY_MODE (BIT(1)) #define EXTMEM_ICACHE_WAY_MODE_M (BIT(1)) #define EXTMEM_ICACHE_WAY_MODE_V 0x1 #define EXTMEM_ICACHE_WAY_MODE_S 1 /* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to activate the data cache. 0: disable 1: enable*/ -#define EXTMEM_ICACHE_ENABLE (BIT(0)) +/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/ +#define EXTMEM_ICACHE_ENABLE (BIT(0)) #define EXTMEM_ICACHE_ENABLE_M (BIT(0)) #define EXTMEM_ICACHE_ENABLE_V 0x1 #define EXTMEM_ICACHE_ENABLE_S 0 -#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x064) +#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x64) /* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to disable core1 ibus 0: enable 1: disable*/ -#define EXTMEM_ICACHE_SHUT_CORE1_BUS (BIT(1)) +/*description: The bit is used to disable core1 ibus, 0: enable, 1: disable.*/ +#define EXTMEM_ICACHE_SHUT_CORE1_BUS (BIT(1)) #define EXTMEM_ICACHE_SHUT_CORE1_BUS_M (BIT(1)) #define EXTMEM_ICACHE_SHUT_CORE1_BUS_V 0x1 #define EXTMEM_ICACHE_SHUT_CORE1_BUS_S 1 /* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to disable core0 ibus 0: enable 1: disable*/ -#define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0)) +/*description: The bit is used to disable core0 ibus, 0: enable, 1: disable.*/ +#define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0)) #define EXTMEM_ICACHE_SHUT_CORE0_BUS_M (BIT(0)) #define EXTMEM_ICACHE_SHUT_CORE0_BUS_V 0x1 #define EXTMEM_ICACHE_SHUT_CORE0_BUS_S 0 -#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x068) +#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x68) /* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/ -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) +/*description: The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up.*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 /* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to power icache tag memory down 0: follow rtc_lslp - 1: power down*/ -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) +/*description: The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power d +own.*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 /* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of icache tag memory. - 1: close gating 0: open clock gating.*/ -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) +/*description: The bit is used to close clock gating of icache tag memory. 1: close gating, 0: + open clock gating..*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 -#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x06C) +#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x6C) /* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section of prelock function.*/ -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) +/*description: The bit is used to enable the second section of prelock function..*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (BIT(1)) #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x1 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 /* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section of prelock function.*/ -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) +/*description: The bit is used to enable the first section of prelock function..*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (BIT(0)) #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x1 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x070) +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x70) /* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to configure the first start virtual address - of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/ -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the first start virtual address of data prelock, +which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG.*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S)) #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x074) +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x74) /* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to configure the second start virtual address - of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/ -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the second start virtual address of data prelock, + which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG.*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S)) #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 -#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x078) +#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x78) /* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The bits are used to configure the first length of data locking - which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF +/*description: The bits are used to configure the first length of data locking, which is combin +ed with ICACHE_PRELOCK_SCT0_ADDR_REG.*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)) #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 /* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the second length of data locking - which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF +/*description: The bits are used to configure the second length of data locking, which is combi +ned with ICACHE_PRELOCK_SCT1_ADDR_REG.*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)) #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 -#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x07C) -/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate unlock/lock operation is finished.*/ -#define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) +#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x7C) +/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to indicate unlock/lock operation is finished..*/ +#define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) #define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2)) #define EXTMEM_ICACHE_LOCK_DONE_V 0x1 #define EXTMEM_ICACHE_LOCK_DONE_S 2 /* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable unlock operation. It will be cleared - by hardware after unlock operation done.*/ -#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) +/*description: The bit is used to enable unlock operation. It will be cleared by hardware after + unlock operation done..*/ +#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) #define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1)) #define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1 #define EXTMEM_ICACHE_UNLOCK_ENA_S 1 /* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable lock operation. It will be cleared - by hardware after lock operation done.*/ -#define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) +/*description: The bit is used to enable lock operation. It will be cleared by hardware after l +ock operation done..*/ +#define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) #define EXTMEM_ICACHE_LOCK_ENA_M (BIT(0)) #define EXTMEM_ICACHE_LOCK_ENA_V 0x1 #define EXTMEM_ICACHE_LOCK_ENA_S 0 -#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x080) +#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) /* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/ -#define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address for lock operations. It + should be combined with ICACHE_LOCK_SIZE_REG..*/ +#define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF #define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S)) #define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF #define EXTMEM_ICACHE_LOCK_ADDR_S 0 -#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x084) +#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) /* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the length for lock operations. - The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ -#define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF +/*description: The bits are used to configure the length for lock operations. The bits are the +counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG..*/ +#define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF #define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S)) #define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF #define EXTMEM_ICACHE_LOCK_SIZE_S 0 -#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x088) +#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) /* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate invalidate operation is finished.*/ -#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) +/*description: The bit is used to indicate invalidate operation is finished..*/ +#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) #define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1)) #define EXTMEM_ICACHE_SYNC_DONE_V 0x1 #define EXTMEM_ICACHE_SYNC_DONE_S 1 /* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable invalidate operation. It will be cleared - by hardware after invalidate operation done.*/ -#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) +/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a +fter invalidate operation done..*/ +#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) #define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) #define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 #define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 -#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x08C) +#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x8C) /* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/ -#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address for clean operations. I +t should be combined with ICACHE_SYNC_SIZE_REG..*/ +#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF #define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S)) #define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF #define EXTMEM_ICACHE_SYNC_ADDR_S 0 -#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x090) +#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x90) /* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ -/*description: The bits are used to configure the length for sync operations. - The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ -#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF +/*description: The bits are used to configure the length for sync operations. The bits are the +counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG..*/ +#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF #define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S)) #define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF #define EXTMEM_ICACHE_SYNC_SIZE_S 0 -#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x094) +#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x94) /* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to configure the direction of preload operation. - 1: descending 0: ascending.*/ -#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) +/*description: The bit is used to configure the direction of preload operation. 1: descending, +0: ascending..*/ +#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) #define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2)) #define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1 #define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 -/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate preload operation is finished.*/ -#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) +/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to indicate preload operation is finished..*/ +#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_DONE_M (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_DONE_V 0x1 #define EXTMEM_ICACHE_PRELOAD_DONE_S 1 /* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable preload operation. It will be cleared - by hardware after preload operation done.*/ -#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) +/*description: The bit is used to enable preload operation. It will be cleared by hardware afte +r preload operation done..*/ +#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) #define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0)) #define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1 #define EXTMEM_ICACHE_PRELOAD_ENA_S 0 -#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x098) +#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x98) /* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/ -#define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address for preload operation. +It should be combined with ICACHE_PRELOAD_SIZE_REG..*/ +#define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF #define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S)) #define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF #define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 -#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x09C) +#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x9C) /* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the length for preload operation. - The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ -#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF +/*description: The bits are used to configure the length for preload operation. The bits are th +e counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG...*/ +#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF #define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S)) #define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF #define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 -#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0A0) +#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xA0) +/* EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to clear autoload buffer in icache..*/ +#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9)) +#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_M (BIT(9)) +#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S 9 /* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */ -/*description: The bits are used to configure the numbers of the cache block - for the issuing autoload operation.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SIZE 0x00000003 +/*description: The bits are used to configure the numbers of the cache block for the issuing au +toload operation..*/ +#define EXTMEM_ICACHE_AUTOLOAD_SIZE 0x00000003 #define EXTMEM_ICACHE_AUTOLOAD_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SIZE_S)) #define EXTMEM_ICACHE_AUTOLOAD_SIZE_V 0x3 #define EXTMEM_ICACHE_AUTOLOAD_SIZE_S 7 /* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ -/*description: The bits are used to configure trigger conditions for autoload. - 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ -#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 +/*description: The bits are used to configure trigger conditions for autoload. 0/3: cache miss, + 1: cache hit, 2: both cache miss and hit..*/ +#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 #define EXTMEM_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S)) #define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x3 #define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 /* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bits are used to configure the direction of autoload. 1: - descending 0: ascending.*/ -#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) +/*description: The bits are used to configure the direction of autoload. 1: descending, 0: asce +nding..*/ +#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) #define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4)) #define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 -/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate autoload operation is finished.*/ -#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) +/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: The bit is used to indicate autoload operation is finished..*/ +#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) #define EXTMEM_ICACHE_AUTOLOAD_DONE_M (BIT(3)) #define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x1 #define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 /* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable and disable autoload operation. It - is combined with dcache_autoload_done. 1: enable 0: disable.*/ -#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) +/*description: The bit is used to enable and disable autoload operation. It is combined with ic +ache_autoload_done. 1: enable, 0: disable. .*/ +#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) #define EXTMEM_ICACHE_AUTOLOAD_ENA_M (BIT(2)) #define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x1 #define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bits are used to enable the second section for autoload operation.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) +/*description: The bits are used to enable the second section for autoload operation..*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bits are used to enable the first section for autoload operation.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) +/*description: The bits are used to enable the first section for autoload operation..*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x0A4) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA4) /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of the - first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address of the first section fo +r autoload operation. It should be combined with icache_autoload_sct0_ena..*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)) #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x0A8) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA8) /* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: The bits are used to configure the length of the first section - for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF +/*description: The bits are used to configure the length of the first section for autoload oper +ation. It should be combined with icache_autoload_sct0_ena..*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S)) #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x0AC) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0xAC) /* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of the - second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address of the second section f +or autoload operation. It should be combined with icache_autoload_sct1_ena..*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S)) #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x0B0) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0xB0) /* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: The bits are used to configure the length of the second section - for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF +/*description: The bits are used to configure the length of the second section for autoload ope +ration. It should be combined with icache_autoload_sct1_ena..*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S)) #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0B4) +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xB4) /* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h44000000 ; */ -/*description: The bits are used to configure the start virtual address of ibus - to access flash. The register is used to give constraints to ibus access counter.*/ -#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address of ibus to access flash +. The register is used to give constraints to ibus access counter..*/ +#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF #define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S)) #define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF #define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0B8) +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xB8) /* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h47ffffff ; */ -/*description: The bits are used to configure the end virtual address of ibus - to access flash. The register is used to give constraints to ibus access counter.*/ -#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF +/*description: The bits are used to configure the end virtual address of ibus to access flash. +The register is used to give constraints to ibus access counter..*/ +#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF #define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S)) #define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF #define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0BC) +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xBC) /* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of dbus - to access flash. The register is used to give constraints to dbus access counter.*/ -#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF +/*description: The bits are used to configure the start virtual address of dbus to access flash +. The register is used to give constraints to dbus access counter..*/ +#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF #define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S)) #define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF #define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0C0) +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xC0) /* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the end virtual address of dbus - to access flash. The register is used to give constraints to dbus access counter.*/ -#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF +/*description: The bits are used to configure the end virtual address of dbus to access flash. +The register is used to give constraints to dbus access counter..*/ +#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF #define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S)) #define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF #define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 -#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0C4) +#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0xC4) /* EXTMEM_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear icache counter.*/ -#define EXTMEM_ICACHE_ACS_CNT_CLR (BIT(1)) +/*description: The bit is used to clear icache counter..*/ +#define EXTMEM_ICACHE_ACS_CNT_CLR (BIT(1)) #define EXTMEM_ICACHE_ACS_CNT_CLR_M (BIT(1)) #define EXTMEM_ICACHE_ACS_CNT_CLR_V 0x1 #define EXTMEM_ICACHE_ACS_CNT_CLR_S 1 /* EXTMEM_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear dcache counter.*/ -#define EXTMEM_DCACHE_ACS_CNT_CLR (BIT(0)) +/*description: The bit is used to clear dcache counter..*/ +#define EXTMEM_DCACHE_ACS_CNT_CLR (BIT(0)) #define EXTMEM_DCACHE_ACS_CNT_CLR_M (BIT(0)) #define EXTMEM_DCACHE_ACS_CNT_CLR_V 0x1 #define EXTMEM_DCACHE_ACS_CNT_CLR_S 0 -#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C8) +#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xC8) /* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of the cache miss caused - by ibus access flash/spiram.*/ -#define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF +/*description: The bits are used to count the number of the cache miss caused by ibus access fl +ash/spiram..*/ +#define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF #define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S)) #define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF #define EXTMEM_IBUS_ACS_MISS_CNT_S 0 -#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0CC) +#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xCC) /* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of ibus access flash/spiram - through icache.*/ -#define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF +/*description: The bits are used to count the number of ibus access flash/spiram through icache +..*/ +#define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF #define EXTMEM_IBUS_ACS_CNT_M ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S)) #define EXTMEM_IBUS_ACS_CNT_V 0xFFFFFFFF #define EXTMEM_IBUS_ACS_CNT_S 0 -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D0) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xD0) /* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of the cache miss caused - by dbus access flash.*/ -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF +/*description: The bits are used to count the number of the cache miss caused by dbus access fl +ash..*/ +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S)) #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xFFFFFFFF #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D4) +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xD4) /* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of the cache miss caused - by dbus access spiram.*/ -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xFFFFFFFF +/*description: The bits are used to count the number of the cache miss caused by dbus access sp +iram..*/ +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xFFFFFFFF #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M ((EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S)) #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V 0xFFFFFFFF #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S 0 -#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D8) +#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xD8) /* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of dbus access flash/spiram - through dcache.*/ -#define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF +/*description: The bits are used to count the number of dbus access flash/spiram through dcache +..*/ +#define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF #define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S)) #define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF #define EXTMEM_DBUS_ACS_CNT_S 0 -#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0DC) +#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xDC) /* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by dbus counter overflow.*/ -#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) +/*description: The bit is used to enable interrupt by dbus counter overflow..*/ +#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) #define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) #define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 /* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by ibus counter overflow.*/ -#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) +/*description: The bit is used to enable interrupt by ibus counter overflow..*/ +#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) #define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7)) #define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 /* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by dcache trying to replace - a line whose blocks all have been occupied by occupy-mode.*/ -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA (BIT(6)) +/*description: The bit is used to enable interrupt by dcache trying to replace a line whose blo +cks all have been occupied by occupy-mode..*/ +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA (BIT(6)) #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M (BIT(6)) #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V 0x1 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S 6 /* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by mmu entry fault.*/ -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) +/*description: The bit is used to enable interrupt by mmu entry fault..*/ +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5)) #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 /* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by dcache trying to write flash.*/ -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4)) +/*description: The bit is used to enable interrupt by dcache trying to write flash..*/ +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4)) #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (BIT(4)) #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x1 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 4 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by preload configurations fault.*/ -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(3)) +/*description: The bit is used to enable interrupt by preload configurations fault..*/ +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(3)) #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(3)) #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S 3 /* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by sync configurations fault.*/ -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA (BIT(2)) +/*description: The bit is used to enable interrupt by sync configurations fault..*/ +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA (BIT(2)) #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(2)) #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S 2 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by preload configurations fault.*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) +/*description: The bit is used to enable interrupt by preload configurations fault..*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 /* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by sync configurations fault.*/ -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) +/*description: The bit is used to enable interrupt by sync configurations fault..*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0)) #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 -#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0E0) +#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xE0) /* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by dbus counter overflow.*/ -#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) +/*description: The bit is used to clear interrupt by dbus counter overflow..*/ +#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) #define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8)) #define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 /* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by ibus counter overflow.*/ -#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) +/*description: The bit is used to clear interrupt by ibus counter overflow..*/ +#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) #define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7)) #define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 /* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by dcache trying to replace - a line whose blocks all have been occupied by occupy-mode.*/ -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6)) +/*description: The bit is used to clear interrupt by dcache trying to replace a line whose bloc +ks all have been occupied by occupy-mode..*/ +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6)) #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (BIT(6)) #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V 0x1 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S 6 /* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by mmu entry fault.*/ -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) +/*description: The bit is used to clear interrupt by mmu entry fault..*/ +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5)) #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 /* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by dcache trying to write flash.*/ -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4)) +/*description: The bit is used to clear interrupt by dcache trying to write flash..*/ +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4)) #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (BIT(4)) #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x1 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 4 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by preload configurations fault.*/ -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(3)) +/*description: The bit is used to clear interrupt by preload configurations fault..*/ +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(3)) #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(3)) #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S 3 /* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by sync configurations fault.*/ -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR (BIT(2)) +/*description: The bit is used to clear interrupt by sync configurations fault..*/ +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR (BIT(2)) #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(2)) #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S 2 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by preload configurations fault.*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) +/*description: The bit is used to clear interrupt by preload configurations fault..*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 /* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by sync configurations fault.*/ -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) +/*description: The bit is used to clear interrupt by sync configurations fault..*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0)) #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 -#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0E4) +#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xE4) /* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus access spiram miss - counter overflow.*/ -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST (BIT(11)) +/*description: The bit is used to indicate interrupt by dbus access spiram miss counter overflo +w..*/ +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST (BIT(11)) #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_M (BIT(11)) #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V 0x1 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S 11 /* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus access flash miss - counter overflow.*/ -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) +/*description: The bit is used to indicate interrupt by dbus access flash miss counter overflow +..*/ +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10)) #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 /* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus access flash/spiram - counter overflow.*/ -#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) +/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overfl +ow..*/ +#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) #define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) #define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 /* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus access flash/spiram - miss counter overflow.*/ -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) +/*description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter o +verflow..*/ +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8)) #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 /* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus access flash/spiram - counter overflow.*/ -#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) +/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overfl +ow..*/ +#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) #define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) #define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 /* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dcache trying to replace - a line whose blocks all have been occupied by occupy-mode.*/ -#define EXTMEM_DCACHE_OCCUPY_EXC_ST (BIT(6)) +/*description: The bit is used to indicate interrupt by dcache trying to replace a line whose b +locks all have been occupied by occupy-mode..*/ +#define EXTMEM_DCACHE_OCCUPY_EXC_ST (BIT(6)) #define EXTMEM_DCACHE_OCCUPY_EXC_ST_M (BIT(6)) #define EXTMEM_DCACHE_OCCUPY_EXC_ST_V 0x1 #define EXTMEM_DCACHE_OCCUPY_EXC_ST_S 6 /* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by mmu entry fault.*/ -#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) +/*description: The bit is used to indicate interrupt by mmu entry fault..*/ +#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) #define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5)) #define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 #define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 /* EXTMEM_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dcache trying to write flash.*/ -#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(4)) +/*description: The bit is used to indicate interrupt by dcache trying to write flash..*/ +#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(4)) #define EXTMEM_DCACHE_WRITE_FLASH_ST_M (BIT(4)) #define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x1 #define EXTMEM_DCACHE_WRITE_FLASH_ST_S 4 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by preload configurations fault.*/ -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST (BIT(3)) +/*description: The bit is used to indicate interrupt by preload configurations fault..*/ +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST (BIT(3)) #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_M (BIT(3)) #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V 0x1 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S 3 /* EXTMEM_DCACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by sync configurations fault.*/ -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST (BIT(2)) +/*description: The bit is used to indicate interrupt by sync configurations fault..*/ +#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST (BIT(2)) #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_M (BIT(2)) #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V 0x1 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S 2 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by preload configurations fault.*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) +/*description: The bit is used to indicate interrupt by preload configurations fault..*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 /* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by sync configurations fault.*/ -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) +/*description: The bit is used to indicate interrupt by sync configurations fault..*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0)) #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 -#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0E8) +#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xE8) /* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by authentication fail.*/ -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) +/*description: The bit is used to enable interrupt by authentication fail..*/ +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4)) #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 /* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by cpu access dcache while - the corresponding dbus is disabled which include speculative access.*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) +/*description: The bit is used to enable interrupt by cpu access dcache while the corresponding + dbus is disabled which include speculative access..*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3)) #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S 3 /* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by authentication fail.*/ -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) +/*description: The bit is used to enable interrupt by authentication fail..*/ +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2)) #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 /* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) +/*description: The bit is used to enable interrupt by ibus trying to write icache.*/ +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1)) #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 /* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by cpu access icache while - the corresponding ibus is disabled which include speculative access.*/ -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) +/*description: The bit is used to enable interrupt by cpu access icache while the corresponding + ibus is disabled which include speculative access..*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 -#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0EC) +#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xEC) /* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by authentication fail.*/ -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) +/*description: The bit is used to clear interrupt by authentication fail..*/ +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4)) #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 /* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by cpu access dcache while - the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) +/*description: The bit is used to clear interrupt by cpu access dcache while the corresponding +dbus is disabled or dcache is disabled which include speculative access..*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(3)) #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S 3 /* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by authentication fail.*/ -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) +/*description: The bit is used to clear interrupt by authentication fail..*/ +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2)) #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 /* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) +/*description: The bit is used to clear interrupt by ibus trying to write icache.*/ +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1)) #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 /* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by cpu access icache while - the corresponding ibus is disabled or icache is disabled which include speculative access.*/ -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) +/*description: The bit is used to clear interrupt by cpu access icache while the corresponding +ibus is disabled or icache is disabled which include speculative access..*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 -#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0F0) +#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xF0) /* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by authentication fail.*/ -#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) +/*description: The bit is used to indicate interrupt by authentication fail..*/ +#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) #define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4)) #define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1 #define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 /* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by cpu access dcache while - the core0_dbus is disabled or dcache is disabled which include speculative access.*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) +/*description: The bit is used to indicate interrupt by cpu access dcache while the core0_dbus +is disabled or dcache is disabled which include speculative access..*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_M (BIT(3)) #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V 0x1 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S 3 /* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by authentication fail.*/ -#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) +/*description: The bit is used to indicate interrupt by authentication fail..*/ +#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) #define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2)) #define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1 #define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 /* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) +/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/ +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1)) #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 /* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by cpu access icache while - the core0_ibus is disabled or icache is disabled which include speculative access.*/ -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) +/*description: The bit is used to indicate interrupt by cpu access icache while the core0_ibus + is disabled or icache is disabled which include speculative access..*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 -#define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0F4) +#define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xF4) /* EXTMEM_CORE1_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by authentication fail.*/ -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA (BIT(4)) +/*description: The bit is used to enable interrupt by authentication fail..*/ +#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA (BIT(4)) #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_M (BIT(4)) #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V 0x1 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S 4 /* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by cpu access dcache while - the corresponding dbus is disabled which include speculative access.*/ -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) +/*description: The bit is used to enable interrupt by cpu access dcache while the corresponding + dbus is disabled which include speculative access..*/ +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3)) #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S 3 /* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by authentication fail.*/ -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA (BIT(2)) +/*description: The bit is used to enable interrupt by authentication fail..*/ +#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA (BIT(2)) #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_M (BIT(2)) #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V 0x1 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S 2 /* EXTMEM_CORE1_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA (BIT(1)) +/*description: The bit is used to enable interrupt by ibus trying to write icache.*/ +#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA (BIT(1)) #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_M (BIT(1)) #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V 0x1 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S 1 /* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by cpu access icache while - the corresponding ibus is disabled which include speculative access.*/ -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) +/*description: The bit is used to enable interrupt by cpu access icache while the corresponding + ibus is disabled which include speculative access..*/ +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S 0 -#define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0F8) +#define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xF8) /* EXTMEM_CORE1_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by authentication fail.*/ -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR (BIT(4)) +/*description: The bit is used to clear interrupt by authentication fail..*/ +#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR (BIT(4)) #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_M (BIT(4)) #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V 0x1 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S 4 /* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by cpu access dcache while - the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) +/*description: The bit is used to clear interrupt by cpu access dcache while the corresponding +dbus is disabled or dcache is disabled which include speculative access..*/ +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(3)) #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S 3 /* EXTMEM_CORE1_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by authentication fail.*/ -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR (BIT(2)) +/*description: The bit is used to clear interrupt by authentication fail..*/ +#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR (BIT(2)) #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M (BIT(2)) #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V 0x1 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S 2 /* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR (BIT(1)) +/*description: The bit is used to clear interrupt by ibus trying to write icache.*/ +#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR (BIT(1)) #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_M (BIT(1)) #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V 0x1 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S 1 /* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by cpu access icache while - the corresponding ibus is disabled or icache is disabled which include speculative access.*/ -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) +/*description: The bit is used to clear interrupt by cpu access icache while the corresponding +ibus is disabled or icache is disabled which include speculative access..*/ +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S 0 -#define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0FC) +#define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xFC) /* EXTMEM_CORE1_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by authentication fail.*/ -#define EXTMEM_CORE1_DBUS_REJECT_ST (BIT(4)) +/*description: The bit is used to indicate interrupt by authentication fail..*/ +#define EXTMEM_CORE1_DBUS_REJECT_ST (BIT(4)) #define EXTMEM_CORE1_DBUS_REJECT_ST_M (BIT(4)) #define EXTMEM_CORE1_DBUS_REJECT_ST_V 0x1 #define EXTMEM_CORE1_DBUS_REJECT_ST_S 4 /* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by cpu access dcache while - the core1_dbus is disabled or dcache is disabled which include speculative access.*/ -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) +/*description: The bit is used to indicate interrupt by cpu access dcache while the core1_dbus +is disabled or dcache is disabled which include speculative access..*/ +#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_M (BIT(3)) #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V 0x1 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S 3 /* EXTMEM_CORE1_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by authentication fail.*/ -#define EXTMEM_CORE1_IBUS_REJECT_ST (BIT(2)) +/*description: The bit is used to indicate interrupt by authentication fail..*/ +#define EXTMEM_CORE1_IBUS_REJECT_ST (BIT(2)) #define EXTMEM_CORE1_IBUS_REJECT_ST_M (BIT(2)) #define EXTMEM_CORE1_IBUS_REJECT_ST_V 0x1 #define EXTMEM_CORE1_IBUS_REJECT_ST_S 2 /* EXTMEM_CORE1_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST (BIT(1)) +/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/ +#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST (BIT(1)) #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M (BIT(1)) #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V 0x1 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S 1 /* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by cpu access icache while - the core1_ibus is disabled or icache is disabled which include speculative access.*/ -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) +/*description: The bit is used to indicate interrupt by cpu access icache while the core1_ibus + is disabled or icache is disabled which include speculative access..*/ +#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V 0x1 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S 0 #define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x100) /* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the world of CPU access dbus when - authentication fail. 0: WORLD0 1: WORLD1*/ -#define EXTMEM_CORE0_DBUS_WORLD (BIT(6)) +/*description: The bit is used to indicate the world of CPU access dbus when authentication fai +l. 0: WORLD0, 1: WORLD1.*/ +#define EXTMEM_CORE0_DBUS_WORLD (BIT(6)) #define EXTMEM_CORE0_DBUS_WORLD_M (BIT(6)) #define EXTMEM_CORE0_DBUS_WORLD_V 0x1 #define EXTMEM_CORE0_DBUS_WORLD_S 6 /* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of CPU access dbus - when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ -#define EXTMEM_CORE0_DBUS_ATTR 0x00000007 +/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati +on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ +#define EXTMEM_CORE0_DBUS_ATTR 0x00000007 #define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S)) #define EXTMEM_CORE0_DBUS_ATTR_V 0x7 #define EXTMEM_CORE0_DBUS_ATTR_S 3 /* EXTMEM_CORE0_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of data from external - memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ -#define EXTMEM_CORE0_DBUS_TAG_ATTR 0x00000007 +/*description: The bits are used to indicate the attribute of data from external memory when au +thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ +#define EXTMEM_CORE0_DBUS_TAG_ATTR 0x00000007 #define EXTMEM_CORE0_DBUS_TAG_ATTR_M ((EXTMEM_CORE0_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_DBUS_TAG_ATTR_S)) #define EXTMEM_CORE0_DBUS_TAG_ATTR_V 0x7 #define EXTMEM_CORE0_DBUS_TAG_ATTR_S 0 #define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x104) /* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to indicate the virtual address of CPU access - dbus when authentication fail.*/ -#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF +/*description: The bits are used to indicate the virtual address of CPU access dbus when authen +tication fail..*/ +#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF #define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S)) #define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF #define EXTMEM_CORE0_DBUS_VADDR_S 0 #define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x108) /* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the world of CPU access ibus when - authentication fail. 0: WORLD0 1: WORLD1*/ -#define EXTMEM_CORE0_IBUS_WORLD (BIT(6)) +/*description: The bit is used to indicate the world of CPU access ibus when authentication fai +l. 0: WORLD0, 1: WORLD1.*/ +#define EXTMEM_CORE0_IBUS_WORLD (BIT(6)) #define EXTMEM_CORE0_IBUS_WORLD_M (BIT(6)) #define EXTMEM_CORE0_IBUS_WORLD_V 0x1 #define EXTMEM_CORE0_IBUS_WORLD_S 6 /* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of CPU access ibus - when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ -#define EXTMEM_CORE0_IBUS_ATTR 0x00000007 +/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati +on fail. 0: invalidate, 1: execute-able, 2: read-able.*/ +#define EXTMEM_CORE0_IBUS_ATTR 0x00000007 #define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S)) #define EXTMEM_CORE0_IBUS_ATTR_V 0x7 #define EXTMEM_CORE0_IBUS_ATTR_S 3 /* EXTMEM_CORE0_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of data from external - memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ -#define EXTMEM_CORE0_IBUS_TAG_ATTR 0x00000007 +/*description: The bits are used to indicate the attribute of data from external memory when au +thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ +#define EXTMEM_CORE0_IBUS_TAG_ATTR 0x00000007 #define EXTMEM_CORE0_IBUS_TAG_ATTR_M ((EXTMEM_CORE0_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_IBUS_TAG_ATTR_S)) #define EXTMEM_CORE0_IBUS_TAG_ATTR_V 0x7 #define EXTMEM_CORE0_IBUS_TAG_ATTR_S 0 #define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x10C) /* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to indicate the virtual address of CPU access - ibus when authentication fail.*/ -#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF +/*description: The bits are used to indicate the virtual address of CPU access ibus when authe +ntication fail..*/ +#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF #define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S)) #define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF #define EXTMEM_CORE0_IBUS_VADDR_S 0 #define EXTMEM_CORE1_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x110) /* EXTMEM_CORE1_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the world of CPU access dbus when - authentication fail. 0: WORLD0 1: WORLD1*/ -#define EXTMEM_CORE1_DBUS_WORLD (BIT(6)) +/*description: The bit is used to indicate the world of CPU access dbus when authentication fai +l. 0: WORLD0, 1: WORLD1.*/ +#define EXTMEM_CORE1_DBUS_WORLD (BIT(6)) #define EXTMEM_CORE1_DBUS_WORLD_M (BIT(6)) #define EXTMEM_CORE1_DBUS_WORLD_V 0x1 #define EXTMEM_CORE1_DBUS_WORLD_S 6 /* EXTMEM_CORE1_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of CPU access dbus - when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ -#define EXTMEM_CORE1_DBUS_ATTR 0x00000007 +/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati +on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ +#define EXTMEM_CORE1_DBUS_ATTR 0x00000007 #define EXTMEM_CORE1_DBUS_ATTR_M ((EXTMEM_CORE1_DBUS_ATTR_V)<<(EXTMEM_CORE1_DBUS_ATTR_S)) #define EXTMEM_CORE1_DBUS_ATTR_V 0x7 #define EXTMEM_CORE1_DBUS_ATTR_S 3 /* EXTMEM_CORE1_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of data from external - memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ -#define EXTMEM_CORE1_DBUS_TAG_ATTR 0x00000007 +/*description: The bits are used to indicate the attribute of data from external memory when au +thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ +#define EXTMEM_CORE1_DBUS_TAG_ATTR 0x00000007 #define EXTMEM_CORE1_DBUS_TAG_ATTR_M ((EXTMEM_CORE1_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_DBUS_TAG_ATTR_S)) #define EXTMEM_CORE1_DBUS_TAG_ATTR_V 0x7 #define EXTMEM_CORE1_DBUS_TAG_ATTR_S 0 #define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x114) /* EXTMEM_CORE1_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to indicate the virtual address of CPU access - dbus when authentication fail.*/ -#define EXTMEM_CORE1_DBUS_VADDR 0xFFFFFFFF +/*description: The bits are used to indicate the virtual address of CPU access dbus when authen +tication fail..*/ +#define EXTMEM_CORE1_DBUS_VADDR 0xFFFFFFFF #define EXTMEM_CORE1_DBUS_VADDR_M ((EXTMEM_CORE1_DBUS_VADDR_V)<<(EXTMEM_CORE1_DBUS_VADDR_S)) #define EXTMEM_CORE1_DBUS_VADDR_V 0xFFFFFFFF #define EXTMEM_CORE1_DBUS_VADDR_S 0 #define EXTMEM_CORE1_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x118) /* EXTMEM_CORE1_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the world of CPU access ibus when - authentication fail. 0: WORLD0 1: WORLD1*/ -#define EXTMEM_CORE1_IBUS_WORLD (BIT(6)) +/*description: The bit is used to indicate the world of CPU access ibus when authentication fai +l. 0: WORLD0, 1: WORLD1.*/ +#define EXTMEM_CORE1_IBUS_WORLD (BIT(6)) #define EXTMEM_CORE1_IBUS_WORLD_M (BIT(6)) #define EXTMEM_CORE1_IBUS_WORLD_V 0x1 #define EXTMEM_CORE1_IBUS_WORLD_S 6 /* EXTMEM_CORE1_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of CPU access ibus - when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ -#define EXTMEM_CORE1_IBUS_ATTR 0x00000007 +/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati +on fail. 0: invalidate, 1: execute-able, 2: read-able.*/ +#define EXTMEM_CORE1_IBUS_ATTR 0x00000007 #define EXTMEM_CORE1_IBUS_ATTR_M ((EXTMEM_CORE1_IBUS_ATTR_V)<<(EXTMEM_CORE1_IBUS_ATTR_S)) #define EXTMEM_CORE1_IBUS_ATTR_V 0x7 #define EXTMEM_CORE1_IBUS_ATTR_S 3 /* EXTMEM_CORE1_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of data from external - memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ -#define EXTMEM_CORE1_IBUS_TAG_ATTR 0x00000007 +/*description: The bits are used to indicate the attribute of data from external memory when au +thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ +#define EXTMEM_CORE1_IBUS_TAG_ATTR 0x00000007 #define EXTMEM_CORE1_IBUS_TAG_ATTR_M ((EXTMEM_CORE1_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_IBUS_TAG_ATTR_S)) #define EXTMEM_CORE1_IBUS_TAG_ATTR_V 0x7 #define EXTMEM_CORE1_IBUS_TAG_ATTR_S 0 #define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x11C) /* EXTMEM_CORE1_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to indicate the virtual address of CPU access - ibus when authentication fail.*/ -#define EXTMEM_CORE1_IBUS_VADDR 0xFFFFFFFF +/*description: The bits are used to indicate the virtual address of CPU access ibus when authe +ntication fail..*/ +#define EXTMEM_CORE1_IBUS_VADDR 0xFFFFFFFF #define EXTMEM_CORE1_IBUS_VADDR_M ((EXTMEM_CORE1_IBUS_VADDR_V)<<(EXTMEM_CORE1_IBUS_VADDR_S)) #define EXTMEM_CORE1_IBUS_VADDR_V 0xFFFFFFFF #define EXTMEM_CORE1_IBUS_VADDR_S 0 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x120) /* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: The right-most 3 bits are used to indicate the operations which - cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/ -#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F +/*description: The right-most 3 bits are used to indicate the operations which cause mmu fault +occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss +evict recovery address, 5: load miss evict recovery address, 6: external dma tx, + 7: external dma rx. The most significant bit is used to indicate this operation + occurs in which one icache. .*/ +#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F #define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S)) #define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF #define EXTMEM_CACHE_MMU_FAULT_CODE_S 16 /* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[15:0] ;default: 17'h0 ; */ -/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/ -#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x0000FFFF +/*description: The bits are used to indicate the content of mmu entry which cause mmu fault...*/ +#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x0000FFFF #define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S)) #define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0xFFFF #define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 #define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x124) /* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to indicate the virtual address which cause mmu fault..*/ -#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF +/*description: The bits are used to indicate the virtual address which cause mmu fault...*/ +#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF #define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S)) #define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF #define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 #define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128) /* EXTMEM_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable wrap around mode when read data from spiram.*/ -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) +/*description: The bit is used to enable wrap around mode when read data from spiram..*/ +#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_M (BIT(1)) #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V 0x1 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S 1 /* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable wrap around mode when read data from flash.*/ -#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) +/*description: The bit is used to enable wrap around mode when read data from flash..*/ +#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) #define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) #define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 #define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12C) /* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/ -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) +/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up.*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 /* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/ -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) +/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down.*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 /* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable clock gating to save power when access - mmu memory 0: enable 1: disable*/ -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) +/*description: The bit is used to enable clock gating to save power when access mmu memory, 0: +enable, 1: disable.*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 #define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x130) /* EXTMEM_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */ -/*description: The bit is used to indicate whether dcache main fsm is in idle - state or not. 1: in idle state 0: not in idle state*/ -#define EXTMEM_DCACHE_STATE 0x00000FFF +/*description: The bit is used to indicate whether dcache main fsm is in idle state or not. 1: +in idle state, 0: not in idle state.*/ +#define EXTMEM_DCACHE_STATE 0x00000FFF #define EXTMEM_DCACHE_STATE_M ((EXTMEM_DCACHE_STATE_V)<<(EXTMEM_DCACHE_STATE_S)) #define EXTMEM_DCACHE_STATE_V 0xFFF #define EXTMEM_DCACHE_STATE_S 12 /* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: The bit is used to indicate whether icache main fsm is in idle - state or not. 1: in idle state 0: not in idle state*/ -#define EXTMEM_ICACHE_STATE 0x00000FFF +/*description: The bit is used to indicate whether icache main fsm is in idle state or not. 1: + in idle state, 0: not in idle state.*/ +#define EXTMEM_ICACHE_STATE 0x00000FFF #define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S)) #define EXTMEM_ICACHE_STATE_V 0xFFF #define EXTMEM_ICACHE_STATE_S 0 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x134) /* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) +/*description: Reserved..*/ +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 /* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) +/*description: Reserved..*/ +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x138) /* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of external memory encrypt - and decrypt clock. 1: close gating 0: open clock gating.*/ -#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) +/*description: The bit is used to close clock gating of external memory encrypt and decrypt clo +ck. 1: close gating, 0: open clock gating..*/ +#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) #define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2)) #define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1 #define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 /* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of automatic crypt clock. - 1: close gating 0: open clock gating.*/ -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) +/*description: The bit is used to close clock gating of automatic crypt clock. 1: close gating, + 0: open clock gating..*/ +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1)) #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 /* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of manual crypt clock. - 1: close gating 0: open clock gating.*/ -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) +/*description: The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: + open clock gating..*/ +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0)) #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 #define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x13C) /* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) +/*description: Reserved..*/ +#define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) #define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (BIT(0)) #define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x1 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0 #define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x140) /* EXTMEM_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear the interrupt by dcache pre-load done.*/ -#define EXTMEM_DCACHE_PRELOAD_INT_CLR (BIT(5)) +/*description: The bit is used to clear the interrupt by dcache pre-load done..*/ +#define EXTMEM_DCACHE_PRELOAD_INT_CLR (BIT(5)) #define EXTMEM_DCACHE_PRELOAD_INT_CLR_M (BIT(5)) #define EXTMEM_DCACHE_PRELOAD_INT_CLR_V 0x1 #define EXTMEM_DCACHE_PRELOAD_INT_CLR_S 5 /* EXTMEM_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable the interrupt by dcache pre-load done.*/ -#define EXTMEM_DCACHE_PRELOAD_INT_ENA (BIT(4)) +/*description: The bit is used to enable the interrupt by dcache pre-load done..*/ +#define EXTMEM_DCACHE_PRELOAD_INT_ENA (BIT(4)) #define EXTMEM_DCACHE_PRELOAD_INT_ENA_M (BIT(4)) #define EXTMEM_DCACHE_PRELOAD_INT_ENA_V 0x1 #define EXTMEM_DCACHE_PRELOAD_INT_ENA_S 4 /* EXTMEM_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the interrupt by dcache pre-load done.*/ -#define EXTMEM_DCACHE_PRELOAD_INT_ST (BIT(3)) +/*description: The bit is used to indicate the interrupt by dcache pre-load done..*/ +#define EXTMEM_DCACHE_PRELOAD_INT_ST (BIT(3)) #define EXTMEM_DCACHE_PRELOAD_INT_ST_M (BIT(3)) #define EXTMEM_DCACHE_PRELOAD_INT_ST_V 0x1 #define EXTMEM_DCACHE_PRELOAD_INT_ST_S 3 /* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear the interrupt by icache pre-load done.*/ -#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) +/*description: The bit is used to clear the interrupt by icache pre-load done..*/ +#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) #define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) #define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 /* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable the interrupt by icache pre-load done.*/ -#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) +/*description: The bit is used to enable the interrupt by icache pre-load done..*/ +#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) #define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 /* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the interrupt by icache pre-load done.*/ -#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) +/*description: The bit is used to indicate the interrupt by icache pre-load done..*/ +#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) #define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0)) #define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1 #define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 #define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x144) /* EXTMEM_DCACHE_SYNC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear the interrupt by dcache sync done.*/ -#define EXTMEM_DCACHE_SYNC_INT_CLR (BIT(5)) +/*description: The bit is used to clear the interrupt by dcache sync done..*/ +#define EXTMEM_DCACHE_SYNC_INT_CLR (BIT(5)) #define EXTMEM_DCACHE_SYNC_INT_CLR_M (BIT(5)) #define EXTMEM_DCACHE_SYNC_INT_CLR_V 0x1 #define EXTMEM_DCACHE_SYNC_INT_CLR_S 5 /* EXTMEM_DCACHE_SYNC_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable the interrupt by dcache sync done.*/ -#define EXTMEM_DCACHE_SYNC_INT_ENA (BIT(4)) +/*description: The bit is used to enable the interrupt by dcache sync done..*/ +#define EXTMEM_DCACHE_SYNC_INT_ENA (BIT(4)) #define EXTMEM_DCACHE_SYNC_INT_ENA_M (BIT(4)) #define EXTMEM_DCACHE_SYNC_INT_ENA_V 0x1 #define EXTMEM_DCACHE_SYNC_INT_ENA_S 4 /* EXTMEM_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the interrupt by dcache sync done.*/ -#define EXTMEM_DCACHE_SYNC_INT_ST (BIT(3)) +/*description: The bit is used to indicate the interrupt by dcache sync done..*/ +#define EXTMEM_DCACHE_SYNC_INT_ST (BIT(3)) #define EXTMEM_DCACHE_SYNC_INT_ST_M (BIT(3)) #define EXTMEM_DCACHE_SYNC_INT_ST_V 0x1 #define EXTMEM_DCACHE_SYNC_INT_ST_S 3 /* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear the interrupt by icache sync done.*/ -#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) +/*description: The bit is used to clear the interrupt by icache sync done..*/ +#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) #define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2)) #define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1 #define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 /* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable the interrupt by icache sync done.*/ -#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) +/*description: The bit is used to enable the interrupt by icache sync done..*/ +#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) #define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1)) #define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1 #define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 /* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the interrupt by icache sync done.*/ -#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) +/*description: The bit is used to indicate the interrupt by icache sync done..*/ +#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) #define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0)) #define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1 #define EXTMEM_ICACHE_SYNC_INT_ST_S 0 #define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x148) /* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: The bits are used to specify the owner of MMU.bit0: icache bit1: - dcache bit2: dma bit3: reserved.*/ -#define EXTMEM_CACHE_MMU_OWNER 0x00FFFFFF +/*description: The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: +dma, bit3: reserved..*/ +#define EXTMEM_CACHE_MMU_OWNER 0x00FFFFFF #define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S)) #define EXTMEM_CACHE_MMU_OWNER_V 0xFFFFFF #define EXTMEM_CACHE_MMU_OWNER_S 0 #define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x14C) /* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to enable cache trace function.*/ -#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) +/*description: The bit is used to enable cache trace function..*/ +#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) #define EXTMEM_CACHE_TRACE_ENA_M (BIT(2)) #define EXTMEM_CACHE_TRACE_ENA_V 0x1 #define EXTMEM_CACHE_TRACE_ENA_S 2 /* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to disable checking mmu entry fault by sync operation.*/ -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) +/*description: The bit is used to disable checking mmu entry fault by sync operation..*/ +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 /* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to disable checking mmu entry fault by preload operation.*/ -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) +/*description: The bit is used to disable checking mmu entry fault by preload operation..*/ +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 #define EXTMEM_DCACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x150) -/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate dcache freeze success*/ -#define EXTMEM_DCACHE_FREEZE_DONE (BIT(2)) +/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to indicate dcache freeze success.*/ +#define EXTMEM_DCACHE_FREEZE_DONE (BIT(2)) #define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(2)) #define EXTMEM_DCACHE_FREEZE_DONE_V 0x1 #define EXTMEM_DCACHE_FREEZE_DONE_S 2 /* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to configure freeze mode 0: assert busy if - CPU miss 1: assert hit if CPU miss*/ -#define EXTMEM_DCACHE_FREEZE_MODE (BIT(1)) +/*description: The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert +hit if CPU miss.*/ +#define EXTMEM_DCACHE_FREEZE_MODE (BIT(1)) #define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(1)) #define EXTMEM_DCACHE_FREEZE_MODE_V 0x1 #define EXTMEM_DCACHE_FREEZE_MODE_S 1 /* EXTMEM_DCACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable dcache freeze mode*/ -#define EXTMEM_DCACHE_FREEZE_ENA (BIT(0)) +/*description: The bit is used to enable dcache freeze mode.*/ +#define EXTMEM_DCACHE_FREEZE_ENA (BIT(0)) #define EXTMEM_DCACHE_FREEZE_ENA_M (BIT(0)) #define EXTMEM_DCACHE_FREEZE_ENA_V 0x1 #define EXTMEM_DCACHE_FREEZE_ENA_S 0 #define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x154) -/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate icache freeze success*/ -#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) +/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to indicate icache freeze success.*/ +#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) #define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2)) #define EXTMEM_ICACHE_FREEZE_DONE_V 0x1 #define EXTMEM_ICACHE_FREEZE_DONE_S 2 /* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to configure freeze mode 0: assert busy if - CPU miss 1: assert hit if CPU miss*/ -#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) +/*description: The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert +hit if CPU miss.*/ +#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) #define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1)) #define EXTMEM_ICACHE_FREEZE_MODE_V 0x1 #define EXTMEM_ICACHE_FREEZE_MODE_S 1 /* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable icache freeze mode*/ -#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) +/*description: The bit is used to enable icache freeze mode.*/ +#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) #define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0)) #define EXTMEM_ICACHE_FREEZE_ENA_V 0x1 #define EXTMEM_ICACHE_FREEZE_ENA_S 0 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) /* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to activate icache atomic operation protection. - In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) +/*description: The bit is used to activate icache atomic operation protection. In this case, sy +nc/lock operation can not interrupt miss-work. This feature does not work during + invalidateAll operation..*/ +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x15C) /* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to activate dcache atomic operation protection. - In this case sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA (BIT(0)) +/*description: The bit is used to activate dcache atomic operation protection. In this case, sy +nc/lock/occupy operation can not interrupt miss-work. This feature does not work + during invalidateAll operation..*/ +#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA (BIT(0)) #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V 0x1 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S 0 #define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x160) /* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to disable request recording which could cause performance issue*/ -#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) +/*description: The bit is used to disable request recording which could cause performance issue.*/ +#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) #define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0)) #define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1 #define EXTMEM_CACHE_REQUEST_BYPASS_S 0 #define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x164) /* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Reserved.*/ -#define EXTMEM_CLK_EN (BIT(0)) +/*description: Reserved..*/ +#define EXTMEM_CLK_EN (BIT(0)) #define EXTMEM_CLK_EN_M (BIT(0)) #define EXTMEM_CLK_EN_V 0x1 #define EXTMEM_CLK_EN_S 0 +#define EXTMEM_CACHE_TAG_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x180) +/* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to set dcache tag memory as object. This bit should be onehot with +the others fields inside this register..*/ +#define EXTMEM_DCACHE_TAG_OBJECT (BIT(1)) +#define EXTMEM_DCACHE_TAG_OBJECT_M (BIT(1)) +#define EXTMEM_DCACHE_TAG_OBJECT_V 0x1 +#define EXTMEM_DCACHE_TAG_OBJECT_S 1 +/* EXTMEM_ICACHE_TAG_OBJECT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to set icache tag memory as object. This bit should be onehot with +the others fields inside this register..*/ +#define EXTMEM_ICACHE_TAG_OBJECT (BIT(0)) +#define EXTMEM_ICACHE_TAG_OBJECT_M (BIT(0)) +#define EXTMEM_ICACHE_TAG_OBJECT_V 0x1 +#define EXTMEM_ICACHE_TAG_OBJECT_S 0 + +#define EXTMEM_CACHE_TAG_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x184) +/* EXTMEM_CACHE_TAG_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1 +: way1, 2: way2, 3: way3, .., 7: way7..*/ +#define EXTMEM_CACHE_TAG_WAY_OBJECT 0x00000007 +#define EXTMEM_CACHE_TAG_WAY_OBJECT_M ((EXTMEM_CACHE_TAG_WAY_OBJECT_V)<<(EXTMEM_CACHE_TAG_WAY_OBJECT_S)) +#define EXTMEM_CACHE_TAG_WAY_OBJECT_V 0x7 +#define EXTMEM_CACHE_TAG_WAY_OBJECT_S 0 + +#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x188) +/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ +/*description: Those bits stores the virtual address which will decide where inside the specifi +ed tag memory object will be accessed..*/ +#define EXTMEM_CACHE_VADDR 0xFFFFFFFF +#define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S)) +#define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_VADDR_S 0 + +#define EXTMEM_CACHE_TAG_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x18C) +/* EXTMEM_CACHE_TAG_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This is a constant place where we can write data to or read data from the tag me +mory on the specified cache..*/ +#define EXTMEM_CACHE_TAG_CONTENT 0xFFFFFFFF +#define EXTMEM_CACHE_TAG_CONTENT_M ((EXTMEM_CACHE_TAG_CONTENT_V)<<(EXTMEM_CACHE_TAG_CONTENT_S)) +#define EXTMEM_CACHE_TAG_CONTENT_V 0xFFFFFFFF +#define EXTMEM_CACHE_TAG_CONTENT_S 0 + #define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) -/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003242 ; */ -/*description: Reserved.*/ -#define EXTMEM_DATE 0x0FFFFFFF +/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012310 ; */ +/*description: Reserved..*/ +#define EXTMEM_DATE 0x0FFFFFFF #define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) #define EXTMEM_DATE_V 0xFFFFFFF #define EXTMEM_DATE_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/extmem_struct.h b/components/soc/esp32s3/include/soc/extmem_struct.h index 362944a09d..79c79488d7 100644 --- a/components/soc/esp32s3/include/soc/extmem_struct.h +++ b/components/soc/esp32s3/include/soc/extmem_struct.h @@ -22,28 +22,28 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t dcache_enable: 1; /*The bit is used to activate the data cache. 0: disable 1: enable*/ - uint32_t reserved1: 1; /*Reserved*/ - uint32_t dcache_size_mode: 1; /*The bit is used to configure cache memory size.0: 32KB 1: 64KB*/ - uint32_t dcache_blocksize_mode: 1; /*The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ - uint32_t reserved4: 28; + uint32_t dcache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/ + uint32_t reserved1 : 1; /*Reserved*/ + uint32_t dcache_size_mode : 1; /*The bit is used to configure cache memory size.0: 32KB, 1: 64KB*/ + uint32_t dcache_blocksize_mode : 2; /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes*/ + uint32_t reserved5 : 27; }; uint32_t val; } dcache_ctrl; union { struct { - uint32_t dcache_shut_core0_bus: 1; /*The bit is used to disable core0 dbus 0: enable 1: disable*/ - uint32_t dcache_shut_core1_bus: 1; /*The bit is used to disable core1 dbus 0: enable 1: disable*/ - uint32_t reserved2: 30; + uint32_t dcache_shut_core0_bus : 1; /*The bit is used to disable core0 dbus, 0: enable, 1: disable*/ + uint32_t dcache_shut_core1_bus : 1; /*The bit is used to disable core1 dbus, 0: enable, 1: disable*/ + uint32_t reserved2 : 30; }; uint32_t val; } dcache_ctrl1; union { struct { - uint32_t dcache_tag_mem_force_on: 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating 0: open clock gating.*/ - uint32_t dcache_tag_mem_force_pd: 1; /*The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd 1: power down*/ - uint32_t dcache_tag_mem_force_pu: 1; /*The bit is used to power dcache tag memory up 0: follow rtc_lslp_pd 1: power up*/ - uint32_t reserved3: 29; + uint32_t dcache_tag_mem_force_on : 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.*/ + uint32_t dcache_tag_mem_force_pd : 1; /*The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down*/ + uint32_t dcache_tag_mem_force_pu : 1; /*The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up*/ + uint32_t reserved3 : 29; }; uint32_t val; } dcache_tag_power_ctrl; @@ -59,8 +59,8 @@ typedef volatile struct { uint32_t dcache_prelock_sct1_addr; /*The bits are used to configure the second start virtual address of data prelock which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG*/ union { struct { - uint32_t dcache_prelock_sct1_size: 16; /*The bits are used to configure the second length of data locking which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/ - uint32_t dcache_prelock_sct0_size: 16; /*The bits are used to configure the first length of data locking which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/ + uint32_t dcache_prelock_sct1_size:16; /*The bits are used to configure the second length of data locking which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/ + uint32_t dcache_prelock_sct0_size:16; /*The bits are used to configure the first length of data locking which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/ }; uint32_t val; } dcache_prelock_sct_size; @@ -76,7 +76,7 @@ typedef volatile struct { uint32_t dcache_lock_addr; /*The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.*/ union { struct { - uint32_t dcache_lock_size: 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/ + uint32_t dcache_lock_size:16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/ uint32_t reserved16: 16; }; uint32_t val; @@ -94,7 +94,7 @@ typedef volatile struct { uint32_t dcache_sync_addr; /*The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.*/ union { struct { - uint32_t dcache_sync_size: 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/ + uint32_t dcache_sync_size:23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/ uint32_t reserved23: 9; }; uint32_t val; @@ -110,7 +110,7 @@ typedef volatile struct { uint32_t dcache_occupy_addr; /*The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.*/ union { struct { - uint32_t dcache_occupy_size: 16; /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/ + uint32_t dcache_occupy_size:16; /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/ uint32_t reserved16: 16; }; uint32_t val; @@ -127,28 +127,29 @@ typedef volatile struct { uint32_t dcache_preload_addr; /*The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.*/ union { struct { - uint32_t dcache_preload_size: 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/ + uint32_t dcache_preload_size:16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/ uint32_t reserved16: 16; }; uint32_t val; } dcache_preload_size; union { struct { - uint32_t dcache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/ - uint32_t dcache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/ - uint32_t dcache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/ - uint32_t dcache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/ - uint32_t dcache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/ - uint32_t dcache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ - uint32_t dcache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/ - uint32_t reserved9: 23; + uint32_t dcache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/ + uint32_t dcache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/ + uint32_t dcache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/ + uint32_t dcache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/ + uint32_t dcache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/ + uint32_t dcache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ + uint32_t dcache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/ + uint32_t dcache_autoload_buffer_clear: 1; /*The bit is used to clear autoload buffer in dcache.*/ + uint32_t reserved10: 22; }; uint32_t val; } dcache_autoload_ctrl; uint32_t dcache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ union { struct { - uint32_t dcache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ + uint32_t dcache_autoload_sct0_size:27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ uint32_t reserved27: 5; }; uint32_t val; @@ -156,7 +157,7 @@ typedef volatile struct { uint32_t dcache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ union { struct { - uint32_t dcache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ + uint32_t dcache_autoload_sct1_size:27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ uint32_t reserved27: 5; }; uint32_t val; @@ -200,8 +201,8 @@ typedef volatile struct { uint32_t icache_prelock_sct1_addr; /*The bits are used to configure the second start virtual address of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/ union { struct { - uint32_t icache_prelock_sct1_size: 16; /*The bits are used to configure the second length of data locking which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ - uint32_t icache_prelock_sct0_size: 16; /*The bits are used to configure the first length of data locking which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ + uint32_t icache_prelock_sct1_size:16; /*The bits are used to configure the second length of data locking which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ + uint32_t icache_prelock_sct0_size:16; /*The bits are used to configure the first length of data locking which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ }; uint32_t val; } icache_prelock_sct_size; @@ -217,7 +218,7 @@ typedef volatile struct { uint32_t icache_lock_addr; /*The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/ union { struct { - uint32_t icache_lock_size: 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ + uint32_t icache_lock_size:16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ uint32_t reserved16: 16; }; uint32_t val; @@ -233,7 +234,7 @@ typedef volatile struct { uint32_t icache_sync_addr; /*The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/ union { struct { - uint32_t icache_sync_size: 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ + uint32_t icache_sync_size:23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ uint32_t reserved23: 9; }; uint32_t val; @@ -250,36 +251,37 @@ typedef volatile struct { uint32_t icache_preload_addr; /*The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/ union { struct { - uint32_t icache_preload_size: 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ + uint32_t icache_preload_size:16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ uint32_t reserved16: 16; }; uint32_t val; } icache_preload_size; union { struct { - uint32_t icache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/ - uint32_t icache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/ - uint32_t icache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/ - uint32_t icache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/ - uint32_t icache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/ - uint32_t icache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ - uint32_t icache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/ - uint32_t reserved9: 23; + uint32_t icache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/ + uint32_t icache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/ + uint32_t icache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable 0: disable.*/ + uint32_t icache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/ + uint32_t icache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/ + uint32_t icache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ + uint32_t icache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/ + uint32_t icache_autoload_buffer_clear: 1; /*The bit is used to clear autoload buffer in icache.*/ + uint32_t reserved10: 22; }; uint32_t val; } icache_autoload_ctrl; - uint32_t icache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ + uint32_t icache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ union { struct { - uint32_t icache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ + uint32_t icache_autoload_sct0_size:27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ uint32_t reserved27: 5; }; uint32_t val; } icache_autoload_sct0_size; - uint32_t icache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ + uint32_t icache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ union { struct { - uint32_t icache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ + uint32_t icache_autoload_sct1_size:27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ uint32_t reserved27: 5; }; uint32_t val; @@ -457,7 +459,7 @@ typedef volatile struct { uint32_t core1_ibus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access ibus when authentication fail.*/ union { struct { - uint32_t cache_mmu_fault_content: 16; /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/ + uint32_t cache_mmu_fault_content:16; /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/ uint32_t cache_mmu_fault_code: 4; /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/ uint32_t reserved20: 12; }; @@ -483,8 +485,8 @@ typedef volatile struct { } cache_mmu_power_ctrl; union { struct { - uint32_t icache_state: 12; /*The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/ - uint32_t dcache_state: 12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/ + uint32_t icache_state:12; /*The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/ + uint32_t dcache_state:12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/ uint32_t reserved24: 8; }; uint32_t val; @@ -515,32 +517,32 @@ typedef volatile struct { } cache_bridge_arbiter_ctrl; union { struct { - uint32_t icache_preload: 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/ - uint32_t icache_preload: 1; /*The bit is used to enable the interrupt by icache pre-load done.*/ - uint32_t icache_preload: 1; /*The bit is used to clear the interrupt by icache pre-load done.*/ - uint32_t dcache_preload: 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/ - uint32_t dcache_preload: 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/ - uint32_t dcache_preload: 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/ - uint32_t reserved6: 26; + uint32_t icache_preload_ist : 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/ + uint32_t icache_preload_iena : 1; /*The bit is used to enable the interrupt by icache pre-load done.*/ + uint32_t icache_preload_iclr : 1; /*The bit is used to clear the interrupt by icache pre-load done.*/ + uint32_t dcache_preload_ist : 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/ + uint32_t dcache_preload_iena : 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/ + uint32_t dcache_preload_iclr : 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/ + uint32_t reserved6 : 26; }; uint32_t val; } cache_preload_int_ctrl; union { struct { - uint32_t icache_sync: 1; /*The bit is used to indicate the interrupt by icache sync done.*/ - uint32_t icache_sync: 1; /*The bit is used to enable the interrupt by icache sync done.*/ - uint32_t icache_sync: 1; /*The bit is used to clear the interrupt by icache sync done.*/ - uint32_t dcache_sync: 1; /*The bit is used to indicate the interrupt by dcache sync done.*/ - uint32_t dcache_sync: 1; /*The bit is used to enable the interrupt by dcache sync done.*/ - uint32_t dcache_sync: 1; /*The bit is used to clear the interrupt by dcache sync done.*/ - uint32_t reserved6: 26; + uint32_t icache_sync_ist : 1; /*The bit is used to indicate the interrupt by icache sync done.*/ + uint32_t icache_sync_iena : 1; /*The bit is used to enable the interrupt by icache sync done.*/ + uint32_t icache_sync_iclr : 1; /*The bit is used to clear the interrupt by icache sync done.*/ + uint32_t dcache_sync_ist : 1; /*The bit is used to indicate the interrupt by dcache sync done.*/ + uint32_t dcache_sync_iena : 1; /*The bit is used to enable the interrupt by dcache sync done.*/ + uint32_t dcache_sync_iclr : 1; /*The bit is used to clear the interrupt by dcache sync done.*/ + uint32_t reserved6 : 26; }; uint32_t val; } cache_sync_int_ctrl; union { struct { - uint32_t cache_mmu_owner: 24; /*The bits are used to specify the owner of MMU.bit0: icache bit1: dcache bit2: dma bit3: reserved.*/ - uint32_t reserved24: 8; + uint32_t cache_mmu_owner : 24; /*The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.*/ + uint32_t reserved24 : 8; }; uint32_t val; } cache_mmu_owner; @@ -605,10 +607,23 @@ typedef volatile struct { uint32_t reserved_174; uint32_t reserved_178; uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; + union { + struct { + uint32_t icache_tag_object: 1; /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/ + uint32_t dcache_tag_object: 1; /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/ + uint32_t reserved2: 30; /*Reserved*/ + }; + uint32_t val; + } cache_tag_object_ctrl; + union { + struct { + uint32_t cache_tag_way_object: 3; /*Set this bits to select which way of the tag-object will be accessed. 0: way0 1: way1 2: way2 3: way3 .. 7: way7.*/ + uint32_t reserved3: 29; /*Reserved*/ + }; + uint32_t val; + } cache_tag_way_object; + uint32_t cache_vaddr; /*Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed.*/ + uint32_t cache_tag_content; /*This is a constant place where we can write data to or read data from the tag memory on the specified cache.*/ uint32_t reserved_190; uint32_t reserved_194; uint32_t reserved_198; diff --git a/components/soc/esp32s3/include/soc/gdma_reg.h b/components/soc/esp32s3/include/soc/gdma_reg.h index eee73a39a2..99e74dc6e8 100644 --- a/components/soc/esp32s3/include/soc/gdma_reg.h +++ b/components/soc/esp32s3/include/soc/gdma_reg.h @@ -1,4 +1,4 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,5164 +11,5421 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_GDMA_REG_H_ +#define _SOC_GDMA_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define GDMA_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x000) -/* GDMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory - to memory via DMA.*/ -#define GDMA_MEM_TRANS_EN_CH0 (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH0_M (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH0_V 0x1 -#define GDMA_MEM_TRANS_EN_CH0_S 10 -/* GDMA_IN_DATA_BURST_EN_CH0 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 0 receiving data when accessing internal SRAM.*/ -#define GDMA_IN_DATA_BURST_EN_CH0 (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH0_M (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH0_V 0x1 -#define GDMA_IN_DATA_BURST_EN_CH0_S 9 -/* GDMA_OUT_DATA_BURST_EN_CH0 : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 transmitting data when accessing internal SRAM.*/ -#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH0_M (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x1 -#define GDMA_OUT_DATA_BURST_EN_CH0_S 8 -/* GDMA_INDSCR_BURST_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 0 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_INDSCR_BURST_EN_CH0 (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH0_M (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH0_V 0x1 -#define GDMA_INDSCR_BURST_EN_CH0_S 7 -/* GDMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH0_M (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x1 -#define GDMA_OUTDSCR_BURST_EN_CH0_S 6 -/* GDMA_OUT_EOF_MODE_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ -#define GDMA_OUT_EOF_MODE_CH0 (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH0_M (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH0_V 0x1 -#define GDMA_OUT_EOF_MODE_CH0_S 5 -/* GDMA_OUT_AUTO_WRBACK_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the - data in tx buffer has been transmitted.*/ -#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH0_M (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x1 -#define GDMA_OUT_AUTO_WRBACK_CH0_S 4 -/* GDMA_OUT_LOOP_TEST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_LOOP_TEST_CH0 (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH0_M (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH0_V 0x1 -#define GDMA_OUT_LOOP_TEST_CH0_S 3 -/* GDMA_IN_LOOP_TEST_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_LOOP_TEST_CH0 (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH0_M (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH0_V 0x1 -#define GDMA_IN_LOOP_TEST_CH0_S 2 -/* GDMA_OUT_RST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ -#define GDMA_OUT_RST_CH0 (BIT(1)) -#define GDMA_OUT_RST_CH0_M (BIT(1)) -#define GDMA_OUT_RST_CH0_V 0x1 -#define GDMA_OUT_RST_CH0_S 1 +#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x0) +/* GDMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D +MA..*/ +#define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_M (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_V 0x1 +#define GDMA_MEM_TRANS_EN_CH0_S 4 +/* GDMA_IN_DATA_BURST_EN_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data +when accessing internal SRAM. .*/ +#define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH0_M (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH0_V 0x1 +#define GDMA_IN_DATA_BURST_EN_CH0_S 3 +/* GDMA_INDSCR_BURST_EN_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_M (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_V 0x1 +#define GDMA_INDSCR_BURST_EN_CH0_S 2 +/* GDMA_IN_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_M (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_V 0x1 +#define GDMA_IN_LOOP_TEST_CH0_S 1 /* GDMA_IN_RST_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ -#define GDMA_IN_RST_CH0 (BIT(0)) -#define GDMA_IN_RST_CH0_M (BIT(0)) -#define GDMA_IN_RST_CH0_V 0x1 -#define GDMA_IN_RST_CH0_S 0 +/*description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer..*/ +#define GDMA_IN_RST_CH0 (BIT(0)) +#define GDMA_IN_RST_CH0_M (BIT(0)) +#define GDMA_IN_RST_CH0_V 0x1 +#define GDMA_IN_RST_CH0_S 0 -#define GDMA_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x004) -/* GDMA_MEM_TRANS_EN_CH1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory - to memory via DMA.*/ -#define GDMA_MEM_TRANS_EN_CH1 (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH1_M (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH1_V 0x1 -#define GDMA_MEM_TRANS_EN_CH1_S 10 -/* GDMA_IN_DATA_BURST_EN_CH1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 1 receiving data when accessing internal SRAM.*/ -#define GDMA_IN_DATA_BURST_EN_CH1 (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH1_M (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH1_V 0x1 -#define GDMA_IN_DATA_BURST_EN_CH1_S 9 -/* GDMA_OUT_DATA_BURST_EN_CH1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 1 transmitting data when accessing internal SRAM.*/ -#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH1_M (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x1 -#define GDMA_OUT_DATA_BURST_EN_CH1_S 8 -/* GDMA_INDSCR_BURST_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 1 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_INDSCR_BURST_EN_CH1 (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH1_M (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH1_V 0x1 -#define GDMA_INDSCR_BURST_EN_CH1_S 7 -/* GDMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 1 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH1_M (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x1 -#define GDMA_OUTDSCR_BURST_EN_CH1_S 6 -/* GDMA_OUT_EOF_MODE_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA*/ -#define GDMA_OUT_EOF_MODE_CH1 (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH1_M (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH1_V 0x1 -#define GDMA_OUT_EOF_MODE_CH1_S 5 -/* GDMA_OUT_AUTO_WRBACK_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the - data in tx buffer has been transmitted.*/ -#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH1_M (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x1 -#define GDMA_OUT_AUTO_WRBACK_CH1_S 4 -/* GDMA_OUT_LOOP_TEST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_LOOP_TEST_CH1 (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH1_M (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH1_V 0x1 -#define GDMA_OUT_LOOP_TEST_CH1_S 3 -/* GDMA_IN_LOOP_TEST_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_LOOP_TEST_CH1 (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH1_M (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH1_V 0x1 -#define GDMA_IN_LOOP_TEST_CH1_S 2 -/* GDMA_OUT_RST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.*/ -#define GDMA_OUT_RST_CH1 (BIT(1)) -#define GDMA_OUT_RST_CH1_M (BIT(1)) -#define GDMA_OUT_RST_CH1_V 0x1 -#define GDMA_OUT_RST_CH1_S 1 -/* GDMA_IN_RST_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.*/ -#define GDMA_IN_RST_CH1 (BIT(0)) -#define GDMA_IN_RST_CH1_M (BIT(0)) -#define GDMA_IN_RST_CH1_V 0x1 -#define GDMA_IN_RST_CH1_S 0 +#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x4) +/* GDMA_IN_EXT_MEM_BK_SIZE_CH0 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_IN_EXT_MEM_BK_SIZE_CH0 0x00000003 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH0_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH0_V)<<(GDMA_IN_EXT_MEM_BK_SIZE_CH0_S)) +#define GDMA_IN_EXT_MEM_BK_SIZE_CH0_V 0x3 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH0_S 13 +/* GDMA_IN_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_M (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_V 0x1 +#define GDMA_IN_CHECK_OWNER_CH0_S 12 +/* GDMA_DMA_INFIFO_FULL_THRS_CH0 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann +el 0 received byte number in Rx FIFO is up to the value of the register..*/ +#define GDMA_DMA_INFIFO_FULL_THRS_CH0 0x00000FFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH0_M ((GDMA_DMA_INFIFO_FULL_THRS_CH0_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH0_S)) +#define GDMA_DMA_INFIFO_FULL_THRS_CH0_V 0xFFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH0_S 0 -#define GDMA_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x008) -/* GDMA_MEM_TRANS_EN_CH2 : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory - to memory via DMA.*/ -#define GDMA_MEM_TRANS_EN_CH2 (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH2_M (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH2_V 0x1 -#define GDMA_MEM_TRANS_EN_CH2_S 10 -/* GDMA_IN_DATA_BURST_EN_CH2 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 2 receiving data when accessing internal SRAM.*/ -#define GDMA_IN_DATA_BURST_EN_CH2 (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH2_M (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH2_V 0x1 -#define GDMA_IN_DATA_BURST_EN_CH2_S 9 -/* GDMA_OUT_DATA_BURST_EN_CH2 : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 2 transmitting data when accessing internal SRAM.*/ -#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH2_M (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x1 -#define GDMA_OUT_DATA_BURST_EN_CH2_S 8 -/* GDMA_INDSCR_BURST_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 2 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_INDSCR_BURST_EN_CH2 (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH2_M (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH2_V 0x1 -#define GDMA_INDSCR_BURST_EN_CH2_S 7 -/* GDMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 2 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH2_M (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH2_V 0x1 -#define GDMA_OUTDSCR_BURST_EN_CH2_S 6 -/* GDMA_OUT_EOF_MODE_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA*/ -#define GDMA_OUT_EOF_MODE_CH2 (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH2_M (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH2_V 0x1 -#define GDMA_OUT_EOF_MODE_CH2_S 5 -/* GDMA_OUT_AUTO_WRBACK_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the - data in tx buffer has been transmitted.*/ -#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH2_M (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x1 -#define GDMA_OUT_AUTO_WRBACK_CH2_S 4 -/* GDMA_OUT_LOOP_TEST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_LOOP_TEST_CH2 (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH2_M (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH2_V 0x1 -#define GDMA_OUT_LOOP_TEST_CH2_S 3 -/* GDMA_IN_LOOP_TEST_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_LOOP_TEST_CH2 (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH2_M (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH2_V 0x1 -#define GDMA_IN_LOOP_TEST_CH2_S 2 -/* GDMA_OUT_RST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.*/ -#define GDMA_OUT_RST_CH2 (BIT(1)) -#define GDMA_OUT_RST_CH2_M (BIT(1)) -#define GDMA_OUT_RST_CH2_V 0x1 -#define GDMA_OUT_RST_CH2_S 1 -/* GDMA_IN_RST_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.*/ -#define GDMA_IN_RST_CH2 (BIT(0)) -#define GDMA_IN_RST_CH2_M (BIT(0)) -#define GDMA_IN_RST_CH2_V 0x1 -#define GDMA_IN_RST_CH2_S 0 +#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x8) +/* GDMA_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH0_INT_RAW_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH0_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH0_INT_RAW_S 9 +/* GDMA_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_S 8 +/* GDMA_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L1_CH0_INT_RAW (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH0_INT_RAW_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH0_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH0_INT_RAW_S 7 +/* GDMA_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L1_CH0_INT_RAW (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_S 6 +/* GDMA_INFIFO_FULL_WM_CH0_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data byte number is up t +o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0..*/ +#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_S 5 +/* GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu +ll and receiving data is not completed, but there is no more inlink for Rx chann +el 0..*/ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/* GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink descriptor error +, including owner error, the second and third word error of inlink descriptor fo +r Rx channel 0..*/ +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/* GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is detected only in th +e case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, thi +s raw interrupt is reserved..*/ +#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x1 +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/* GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt b +it turns to high level when the last data pointed by one inlink descriptor has b +een received and no data error is detected for Rx channel 0..*/ +#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x1 +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/* GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 0..*/ +#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_M (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_V 0x1 +#define GDMA_IN_DONE_CH0_INT_RAW_S 0 -#define GDMA_CONF0_CH3_REG (DR_REG_GDMA_BASE + 0x00C) -/* GDMA_MEM_TRANS_EN_CH3 : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory - to memory via DMA.*/ -#define GDMA_MEM_TRANS_EN_CH3 (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH3_M (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH3_V 0x1 -#define GDMA_MEM_TRANS_EN_CH3_S 10 -/* GDMA_IN_DATA_BURST_EN_CH3 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 3 receiving data when accessing internal SRAM.*/ -#define GDMA_IN_DATA_BURST_EN_CH3 (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH3_M (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH3_V 0x1 -#define GDMA_IN_DATA_BURST_EN_CH3_S 9 -/* GDMA_OUT_DATA_BURST_EN_CH3 : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 3 transmitting data when accessing internal SRAM.*/ -#define GDMA_OUT_DATA_BURST_EN_CH3 (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH3_M (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH3_V 0x1 -#define GDMA_OUT_DATA_BURST_EN_CH3_S 8 -/* GDMA_INDSCR_BURST_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 3 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_INDSCR_BURST_EN_CH3 (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH3_M (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH3_V 0x1 -#define GDMA_INDSCR_BURST_EN_CH3_S 7 -/* GDMA_OUTDSCR_BURST_EN_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 3 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_OUTDSCR_BURST_EN_CH3 (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH3_M (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH3_V 0x1 -#define GDMA_OUTDSCR_BURST_EN_CH3_S 6 -/* GDMA_OUT_EOF_MODE_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 3 is generated when data need to transmit has been popped from FIFO in DMA*/ -#define GDMA_OUT_EOF_MODE_CH3 (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH3_M (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH3_V 0x1 -#define GDMA_OUT_EOF_MODE_CH3_S 5 -/* GDMA_OUT_AUTO_WRBACK_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the - data in tx buffer has been transmitted.*/ -#define GDMA_OUT_AUTO_WRBACK_CH3 (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH3_M (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH3_V 0x1 -#define GDMA_OUT_AUTO_WRBACK_CH3_S 4 -/* GDMA_OUT_LOOP_TEST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_LOOP_TEST_CH3 (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH3_M (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH3_V 0x1 -#define GDMA_OUT_LOOP_TEST_CH3_S 3 -/* GDMA_IN_LOOP_TEST_CH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_LOOP_TEST_CH3 (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH3_M (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH3_V 0x1 -#define GDMA_IN_LOOP_TEST_CH3_S 2 -/* GDMA_OUT_RST_CH3 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This bit is used to reset DMA channel 3 Tx FSM and Tx FIFO pointer.*/ -#define GDMA_OUT_RST_CH3 (BIT(1)) -#define GDMA_OUT_RST_CH3_M (BIT(1)) -#define GDMA_OUT_RST_CH3_V 0x1 -#define GDMA_OUT_RST_CH3_S 1 -/* GDMA_IN_RST_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: This bit is used to reset DMA channel 3 Rx FSM and Rx FIFO pointer.*/ -#define GDMA_IN_RST_CH3 (BIT(0)) -#define GDMA_IN_RST_CH3_M (BIT(0)) -#define GDMA_IN_RST_CH3_V 0x1 -#define GDMA_IN_RST_CH3_S 0 +#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0xC) +/* GDMA_INFIFO_UDF_L3_CH0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH0_INT_ST (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH0_INT_ST_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH0_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH0_INT_ST_S 9 +/* GDMA_INFIFO_OVF_L3_CH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH0_INT_ST (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH0_INT_ST_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH0_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH0_INT_ST_S 8 +/* GDMA_INFIFO_UDF_L1_CH0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH0_INT_ST (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_S 7 +/* GDMA_INFIFO_OVF_L1_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH0_INT_ST (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH0_INT_ST_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH0_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH0_INT_ST_S 6 +/* GDMA_INFIFO_FULL_WM_CH0_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH0_INT_ST (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH0_INT_ST_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH0_INT_ST_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH0_INT_ST_S 5 +/* GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/* GDMA_IN_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x1 +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/* GDMA_IN_ERR_EOF_CH0_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x1 +#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/* GDMA_IN_SUC_EOF_CH0_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x1 +#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/* GDMA_IN_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_M (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_V 0x1 +#define GDMA_IN_DONE_CH0_INT_ST_S 0 -#define GDMA_CONF0_CH4_REG (DR_REG_GDMA_BASE + 0x010) -/* GDMA_MEM_TRANS_EN_CH4 : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory - to memory via DMA.*/ -#define GDMA_MEM_TRANS_EN_CH4 (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH4_M (BIT(10)) -#define GDMA_MEM_TRANS_EN_CH4_V 0x1 -#define GDMA_MEM_TRANS_EN_CH4_S 10 -/* GDMA_IN_DATA_BURST_EN_CH4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 4 receiving data when accessing internal SRAM.*/ -#define GDMA_IN_DATA_BURST_EN_CH4 (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH4_M (BIT(9)) -#define GDMA_IN_DATA_BURST_EN_CH4_V 0x1 -#define GDMA_IN_DATA_BURST_EN_CH4_S 9 -/* GDMA_OUT_DATA_BURST_EN_CH4 : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 4 transmitting data when accessing internal SRAM.*/ -#define GDMA_OUT_DATA_BURST_EN_CH4 (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH4_M (BIT(8)) -#define GDMA_OUT_DATA_BURST_EN_CH4_V 0x1 -#define GDMA_OUT_DATA_BURST_EN_CH4_S 8 -/* GDMA_INDSCR_BURST_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 4 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_INDSCR_BURST_EN_CH4 (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH4_M (BIT(7)) -#define GDMA_INDSCR_BURST_EN_CH4_V 0x1 -#define GDMA_INDSCR_BURST_EN_CH4_S 7 -/* GDMA_OUTDSCR_BURST_EN_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 4 reading link descriptor when accessing internal SRAM.*/ -#define GDMA_OUTDSCR_BURST_EN_CH4 (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH4_M (BIT(6)) -#define GDMA_OUTDSCR_BURST_EN_CH4_V 0x1 -#define GDMA_OUTDSCR_BURST_EN_CH4_S 6 -/* GDMA_OUT_EOF_MODE_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 4 is generated when data need to transmit has been popped from FIFO in DMA*/ -#define GDMA_OUT_EOF_MODE_CH4 (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH4_M (BIT(5)) -#define GDMA_OUT_EOF_MODE_CH4_V 0x1 -#define GDMA_OUT_EOF_MODE_CH4_S 5 -/* GDMA_OUT_AUTO_WRBACK_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the - data in tx buffer has been transmitted.*/ -#define GDMA_OUT_AUTO_WRBACK_CH4 (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH4_M (BIT(4)) -#define GDMA_OUT_AUTO_WRBACK_CH4_V 0x1 -#define GDMA_OUT_AUTO_WRBACK_CH4_S 4 -/* GDMA_OUT_LOOP_TEST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_LOOP_TEST_CH4 (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH4_M (BIT(3)) -#define GDMA_OUT_LOOP_TEST_CH4_V 0x1 -#define GDMA_OUT_LOOP_TEST_CH4_S 3 -/* GDMA_IN_LOOP_TEST_CH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_LOOP_TEST_CH4 (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH4_M (BIT(2)) -#define GDMA_IN_LOOP_TEST_CH4_V 0x1 -#define GDMA_IN_LOOP_TEST_CH4_S 2 -/* GDMA_OUT_RST_CH4 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This bit is used to reset DMA channel 4 Tx FSM and Tx FIFO pointer.*/ -#define GDMA_OUT_RST_CH4 (BIT(1)) -#define GDMA_OUT_RST_CH4_M (BIT(1)) -#define GDMA_OUT_RST_CH4_V 0x1 -#define GDMA_OUT_RST_CH4_S 1 -/* GDMA_IN_RST_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: This bit is used to reset DMA channel 4 Rx FSM and Rx FIFO pointer.*/ -#define GDMA_IN_RST_CH4 (BIT(0)) -#define GDMA_IN_RST_CH4_M (BIT(0)) -#define GDMA_IN_RST_CH4_V 0x1 -#define GDMA_IN_RST_CH4_S 0 +#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x10) +/* GDMA_INFIFO_UDF_L3_CH0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH0_INT_ENA_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH0_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH0_INT_ENA_S 9 +/* GDMA_INFIFO_OVF_L3_CH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_S 8 +/* GDMA_INFIFO_UDF_L1_CH0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH0_INT_ENA (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH0_INT_ENA_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH0_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH0_INT_ENA_S 7 +/* GDMA_INFIFO_OVF_L1_CH0_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH0_INT_ENA (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH0_INT_ENA_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH0_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH0_INT_ENA_S 6 +/* GDMA_INFIFO_FULL_WM_CH0_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_S 5 +/* GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/* GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/* GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x1 +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/* GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x1 +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/* GDMA_IN_DONE_CH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_M (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_V 0x1 +#define GDMA_IN_DONE_CH0_INT_ENA_S 0 + +#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x14) +/* GDMA_INFIFO_UDF_L3_CH0_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_S 9 +/* GDMA_INFIFO_OVF_L3_CH0_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH0_INT_CLR_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH0_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH0_INT_CLR_S 8 +/* GDMA_INFIFO_UDF_L1_CH0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH0_INT_CLR (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH0_INT_CLR_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH0_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH0_INT_CLR_S 7 +/* GDMA_INFIFO_OVF_L1_CH0_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_S 6 +/* GDMA_DMA_INFIFO_FULL_WM_CH0_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_DMA_INFIFO_FULL_WM_CH0_INT_CLR (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH0_INT_CLR_M (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH0_INT_CLR_V 0x1 +#define GDMA_DMA_INFIFO_FULL_WM_CH0_INT_CLR_S 5 +/* GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/* GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/* GDMA_IN_ERR_EOF_CH0_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x1 +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/* GDMA_IN_SUC_EOF_CH0_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x1 +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/* GDMA_IN_DONE_CH0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_M (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_V 0x1 +#define GDMA_IN_DONE_CH0_INT_CLR_S 0 + +#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x18) +/* GDMA_IN_BUF_HUNGRY_CH0 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH0_M (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH0_V 0x1 +#define GDMA_IN_BUF_HUNGRY_CH0_S 28 +/* GDMA_IN_REMAIN_UNDER_4B_L3_CH0 : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0 (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0_M (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0_V 0x1 +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0_S 27 +/* GDMA_IN_REMAIN_UNDER_3B_L3_CH0 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH0 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH0_M (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH0_V 0x1 +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH0_S 26 +/* GDMA_IN_REMAIN_UNDER_2B_L3_CH0 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH0 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH0_M (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH0_V 0x1 +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH0_S 25 +/* GDMA_IN_REMAIN_UNDER_1B_L3_CH0 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_M (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_V 0x1 +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_S 24 +/* GDMA_INFIFO_CNT_L3_CH0 : RO ;bitpos:[23:19] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0..*/ +#define GDMA_INFIFO_CNT_L3_CH0 0x0000001F +#define GDMA_INFIFO_CNT_L3_CH0_M ((GDMA_INFIFO_CNT_L3_CH0_V)<<(GDMA_INFIFO_CNT_L3_CH0_S)) +#define GDMA_INFIFO_CNT_L3_CH0_V 0x1F +#define GDMA_INFIFO_CNT_L3_CH0_S 19 +/* GDMA_INFIFO_CNT_L2_CH0 : RO ;bitpos:[18:12] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0..*/ +#define GDMA_INFIFO_CNT_L2_CH0 0x0000007F +#define GDMA_INFIFO_CNT_L2_CH0_M ((GDMA_INFIFO_CNT_L2_CH0_V)<<(GDMA_INFIFO_CNT_L2_CH0_S)) +#define GDMA_INFIFO_CNT_L2_CH0_V 0x7F +#define GDMA_INFIFO_CNT_L2_CH0_S 12 +/* GDMA_INFIFO_CNT_L1_CH0 : RO ;bitpos:[11:6] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0..*/ +#define GDMA_INFIFO_CNT_L1_CH0 0x0000003F +#define GDMA_INFIFO_CNT_L1_CH0_M ((GDMA_INFIFO_CNT_L1_CH0_V)<<(GDMA_INFIFO_CNT_L1_CH0_S)) +#define GDMA_INFIFO_CNT_L1_CH0_V 0x3F +#define GDMA_INFIFO_CNT_L1_CH0_S 6 +/* GDMA_INFIFO_EMPTY_L3_CH0 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 0..*/ +#define GDMA_INFIFO_EMPTY_L3_CH0 (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH0_M (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH0_V 0x1 +#define GDMA_INFIFO_EMPTY_L3_CH0_S 5 +/* GDMA_INFIFO_FULL_L3_CH0 : RO ;bitpos:[4] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 0..*/ +#define GDMA_INFIFO_FULL_L3_CH0 (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH0_M (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH0_V 0x1 +#define GDMA_INFIFO_FULL_L3_CH0_S 4 +/* GDMA_INFIFO_EMPTY_L2_CH0 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 0..*/ +#define GDMA_INFIFO_EMPTY_L2_CH0 (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH0_M (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH0_V 0x1 +#define GDMA_INFIFO_EMPTY_L2_CH0_S 3 +/* GDMA_INFIFO_FULL_L2_CH0 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 0..*/ +#define GDMA_INFIFO_FULL_L2_CH0 (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH0_M (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH0_V 0x1 +#define GDMA_INFIFO_FULL_L2_CH0_S 2 +/* GDMA_INFIFO_EMPTY_L1_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 0..*/ +#define GDMA_INFIFO_EMPTY_L1_CH0 (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH0_M (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH0_V 0x1 +#define GDMA_INFIFO_EMPTY_L1_CH0_S 1 +/* GDMA_INFIFO_FULL_L1_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 0..*/ +#define GDMA_INFIFO_FULL_L1_CH0 (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH0_M (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH0_V 0x1 +#define GDMA_INFIFO_FULL_L1_CH0_S 0 + +#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x1C) +/* GDMA_INFIFO_POP_CH0 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO..*/ +#define GDMA_INFIFO_POP_CH0 (BIT(12)) +#define GDMA_INFIFO_POP_CH0_M (BIT(12)) +#define GDMA_INFIFO_POP_CH0_V 0x1 +#define GDMA_INFIFO_POP_CH0_S 12 +/* GDMA_INFIFO_RDATA_CH0 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: This register stores the data popping from DMA FIFO..*/ +#define GDMA_INFIFO_RDATA_CH0 0x00000FFF +#define GDMA_INFIFO_RDATA_CH0_M ((GDMA_INFIFO_RDATA_CH0_V)<<(GDMA_INFIFO_RDATA_CH0_S)) +#define GDMA_INFIFO_RDATA_CH0_V 0xFFF +#define GDMA_INFIFO_RDATA_CH0_S 0 + +#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x20) +/* GDMA_INLINK_PARK_CH0 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM + is working..*/ +#define GDMA_INLINK_PARK_CH0 (BIT(24)) +#define GDMA_INLINK_PARK_CH0_M (BIT(24)) +#define GDMA_INLINK_PARK_CH0_V 0x1 +#define GDMA_INLINK_PARK_CH0_S 24 +/* GDMA_INLINK_RESTART_CH0 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor..*/ +#define GDMA_INLINK_RESTART_CH0 (BIT(23)) +#define GDMA_INLINK_RESTART_CH0_M (BIT(23)) +#define GDMA_INLINK_RESTART_CH0_V 0x1 +#define GDMA_INLINK_RESTART_CH0_S 23 +/* GDMA_INLINK_START_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors..*/ +#define GDMA_INLINK_START_CH0 (BIT(22)) +#define GDMA_INLINK_START_CH0_M (BIT(22)) +#define GDMA_INLINK_START_CH0_V 0x1 +#define GDMA_INLINK_START_CH0_S 22 +/* GDMA_INLINK_STOP_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors..*/ +#define GDMA_INLINK_STOP_CH0 (BIT(21)) +#define GDMA_INLINK_STOP_CH0_M (BIT(21)) +#define GDMA_INLINK_STOP_CH0_V 0x1 +#define GDMA_INLINK_STOP_CH0_S 21 +/* GDMA_INLINK_AUTO_RET_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address, when there are so +me errors in current receiving data..*/ +#define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH0_M (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH0_V 0x1 +#define GDMA_INLINK_AUTO_RET_CH0_S 20 +/* GDMA_INLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first inlink descripto +r's address..*/ +#define GDMA_INLINK_ADDR_CH0 0x000FFFFF +#define GDMA_INLINK_ADDR_CH0_M ((GDMA_INLINK_ADDR_CH0_V)<<(GDMA_INLINK_ADDR_CH0_S)) +#define GDMA_INLINK_ADDR_CH0_V 0xFFFFF +#define GDMA_INLINK_ADDR_CH0_S 0 + +#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x24) +/* GDMA_IN_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_STATE_CH0 0x00000007 +#define GDMA_IN_STATE_CH0_M ((GDMA_IN_STATE_CH0_V)<<(GDMA_IN_STATE_CH0_S)) +#define GDMA_IN_STATE_CH0_V 0x7 +#define GDMA_IN_STATE_CH0_S 20 +/* GDMA_IN_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_DSCR_STATE_CH0 0x00000003 +#define GDMA_IN_DSCR_STATE_CH0_M ((GDMA_IN_DSCR_STATE_CH0_V)<<(GDMA_IN_DSCR_STATE_CH0_S)) +#define GDMA_IN_DSCR_STATE_CH0_V 0x3 +#define GDMA_IN_DSCR_STATE_CH0_S 18 +/* GDMA_INLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address..*/ +#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF +#define GDMA_INLINK_DSCR_ADDR_CH0_M ((GDMA_INLINK_DSCR_ADDR_CH0_V)<<(GDMA_INLINK_DSCR_ADDR_CH0_S)) +#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x3FFFF +#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 + +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x28) +/* GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when the EOF bit in th +is descriptor is 1..*/ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH0_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH0_S)) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x2C) +/* GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when there are some er +rors in current receiving data. Only used when peripheral is UHCI0..*/ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH0_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH0_S)) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x30) +/* GDMA_INLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x..*/ +#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH0_M ((GDMA_INLINK_DSCR_CH0_V)<<(GDMA_INLINK_DSCR_CH0_S)) +#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH0_S 0 + +#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x34) +/* GDMA_INLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1..*/ +#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH0_M ((GDMA_INLINK_DSCR_BF0_CH0_V)<<(GDMA_INLINK_DSCR_BF0_CH0_S)) +#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH0_S 0 + +#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x38) +/* GDMA_INLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH0_M ((GDMA_INLINK_DSCR_BF1_CH0_V)<<(GDMA_INLINK_DSCR_BF1_CH0_S)) +#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH0_S 0 + +#define GDMA_IN_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x3C) +/* GDMA_RX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Rx channel 0. .*/ +#define GDMA_RX_WEIGHT_CH0 0x0000000F +#define GDMA_RX_WEIGHT_CH0_M ((GDMA_RX_WEIGHT_CH0_V)<<(GDMA_RX_WEIGHT_CH0_S)) +#define GDMA_RX_WEIGHT_CH0_V 0xF +#define GDMA_RX_WEIGHT_CH0_S 8 + +#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x44) +/* GDMA_RX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 0. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_RX_PRI_CH0 0x0000000F +#define GDMA_RX_PRI_CH0_M ((GDMA_RX_PRI_CH0_V)<<(GDMA_RX_PRI_CH0_S)) +#define GDMA_RX_PRI_CH0_V 0xF +#define GDMA_RX_PRI_CH0_S 0 + +#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x48) +/* GDMA_PERI_IN_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_IN_SEL_CH0 0x0000003F +#define GDMA_PERI_IN_SEL_CH0_M ((GDMA_PERI_IN_SEL_CH0_V)<<(GDMA_PERI_IN_SEL_CH0_S)) +#define GDMA_PERI_IN_SEL_CH0_V 0x3F +#define GDMA_PERI_IN_SEL_CH0_S 0 + +#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x60) +/* GDMA_OUT_DATA_BURST_EN_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting da +ta when accessing internal SRAM. .*/ +#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH0_M (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x1 +#define GDMA_OUT_DATA_BURST_EN_CH0_S 5 +/* GDMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_M (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x1 +#define GDMA_OUTDSCR_BURST_EN_CH0_S 4 +/* GDMA_OUT_EOF_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + generated when data need to transmit has been popped from FIFO in DMA.*/ +#define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_M (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_V 0x1 +#define GDMA_OUT_EOF_MODE_CH0_S 3 +/* GDMA_OUT_AUTO_WRBACK_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe +r has been transmitted..*/ +#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_M (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x1 +#define GDMA_OUT_AUTO_WRBACK_CH0_S 2 +/* GDMA_OUT_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_M (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_V 0x1 +#define GDMA_OUT_LOOP_TEST_CH0_S 1 +/* GDMA_OUT_RST_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer..*/ +#define GDMA_OUT_RST_CH0 (BIT(0)) +#define GDMA_OUT_RST_CH0_M (BIT(0)) +#define GDMA_OUT_RST_CH0_V 0x1 +#define GDMA_OUT_RST_CH0_S 0 + +#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x64) +/* GDMA_OUT_EXT_MEM_BK_SIZE_CH0 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0 0x00000003 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V)<<(GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S)) +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V 0x3 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S 13 -#define GDMA_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x014) -/* GDMA_OUT_EXT_MEM_BK_SIZE_CH0 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ -/*description: Block size of Tx channel 0 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0 0x00000003 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V) << (GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S)) -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V 0x3 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S 15 /* Memory block size value supported by TX channel */ #define GDMA_OUT_EXT_MEM_BK_SIZE_16B (0) #define GDMA_OUT_EXT_MEM_BK_SIZE_32B (1) -/* GDMA_IN_EXT_MEM_BK_SIZE_CH0 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ -/*description: Block size of Rx channel 0 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_IN_EXT_MEM_BK_SIZE_CH0 0x00000003 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH0_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH0_V) << (GDMA_IN_EXT_MEM_BK_SIZE_CH0_S)) -#define GDMA_IN_EXT_MEM_BK_SIZE_CH0_V 0x3 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH0_S 13 + +/* GDMA_OUT_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_M (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_V 0x1 +#define GDMA_OUT_CHECK_OWNER_CH0_S 12 + +#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x68) +/* GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S 4 +/* GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc +ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +nnel 0..*/ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/* GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +r, including owner error, the second and third word error of outlink descriptor +for Tx channel 0..*/ +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/* GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been read from memory for Tx channel 0. .*/ +#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_M (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x1 +#define GDMA_OUT_EOF_CH0_INT_RAW_S 1 +/* GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been transmitted to peripherals for Tx channel 0..*/ +#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_M (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x1 +#define GDMA_OUT_DONE_CH0_INT_RAW_S 0 + +#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x6C) +/* GDMA_OUTFIFO_UDF_L3_CH0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ST (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ST_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ST_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH0_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ST_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ST_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_S 4 +/* GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/* GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/* GDMA_OUT_EOF_CH0_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_M (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_V 0x1 +#define GDMA_OUT_EOF_CH0_INT_ST_S 1 +/* GDMA_OUT_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_M (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_V 0x1 +#define GDMA_OUT_DONE_CH0_INT_ST_S 0 + +#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x70) +/* GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA_S 4 +/* GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/* GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/* GDMA_OUT_EOF_CH0_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_M (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x1 +#define GDMA_OUT_EOF_CH0_INT_ENA_S 1 +/* GDMA_OUT_DONE_CH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_M (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x1 +#define GDMA_OUT_DONE_CH0_INT_ENA_S 0 + +#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x74) +/* GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S 4 +/* GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/* GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/* GDMA_OUT_EOF_CH0_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_M (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x1 +#define GDMA_OUT_EOF_CH0_INT_CLR_S 1 +/* GDMA_OUT_DONE_CH0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_M (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x1 +#define GDMA_OUT_DONE_CH0_INT_CLR_S 0 + +#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) +/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH0 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH0 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH0_M (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH0_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH0_S 26 +/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH0 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH0 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH0_M (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH0_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH0_S 25 +/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH0 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_M (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_S 24 +/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH0 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH0 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH0_M (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH0_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH0_S 23 +/* GDMA_OUTFIFO_CNT_L3_CH0 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0..*/ +#define GDMA_OUTFIFO_CNT_L3_CH0 0x0000001F +#define GDMA_OUTFIFO_CNT_L3_CH0_M ((GDMA_OUTFIFO_CNT_L3_CH0_V)<<(GDMA_OUTFIFO_CNT_L3_CH0_S)) +#define GDMA_OUTFIFO_CNT_L3_CH0_V 0x1F +#define GDMA_OUTFIFO_CNT_L3_CH0_S 18 +/* GDMA_OUTFIFO_CNT_L2_CH0 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0..*/ +#define GDMA_OUTFIFO_CNT_L2_CH0 0x0000007F +#define GDMA_OUTFIFO_CNT_L2_CH0_M ((GDMA_OUTFIFO_CNT_L2_CH0_V)<<(GDMA_OUTFIFO_CNT_L2_CH0_S)) +#define GDMA_OUTFIFO_CNT_L2_CH0_V 0x7F +#define GDMA_OUTFIFO_CNT_L2_CH0_S 11 +/* GDMA_OUTFIFO_CNT_L1_CH0 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0..*/ +#define GDMA_OUTFIFO_CNT_L1_CH0 0x0000001F +#define GDMA_OUTFIFO_CNT_L1_CH0_M ((GDMA_OUTFIFO_CNT_L1_CH0_V)<<(GDMA_OUTFIFO_CNT_L1_CH0_S)) +#define GDMA_OUTFIFO_CNT_L1_CH0_V 0x1F +#define GDMA_OUTFIFO_CNT_L1_CH0_S 6 +/* GDMA_OUTFIFO_EMPTY_L3_CH0 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 0..*/ +#define GDMA_OUTFIFO_EMPTY_L3_CH0 (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH0_M (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH0_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L3_CH0_S 5 +/* GDMA_OUTFIFO_FULL_L3_CH0 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 0..*/ +#define GDMA_OUTFIFO_FULL_L3_CH0 (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH0_M (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH0_V 0x1 +#define GDMA_OUTFIFO_FULL_L3_CH0_S 4 +/* GDMA_OUTFIFO_EMPTY_L2_CH0 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 0..*/ +#define GDMA_OUTFIFO_EMPTY_L2_CH0 (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH0_M (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH0_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L2_CH0_S 3 +/* GDMA_OUTFIFO_FULL_L2_CH0 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 0..*/ +#define GDMA_OUTFIFO_FULL_L2_CH0 (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH0_M (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH0_V 0x1 +#define GDMA_OUTFIFO_FULL_L2_CH0_S 2 +/* GDMA_OUTFIFO_EMPTY_L1_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 0..*/ +#define GDMA_OUTFIFO_EMPTY_L1_CH0 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH0_M (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH0_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L1_CH0_S 1 +/* GDMA_OUTFIFO_FULL_L1_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 0..*/ +#define GDMA_OUTFIFO_FULL_L1_CH0 (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH0_M (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH0_V 0x1 +#define GDMA_OUTFIFO_FULL_L1_CH0_S 0 + +#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0x7C) +/* GDMA_OUTFIFO_PUSH_CH0 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO..*/ +#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_M (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_V 0x1 +#define GDMA_OUTFIFO_PUSH_CH0_S 9 +/* GDMA_OUTFIFO_WDATA_CH0 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO..*/ +#define GDMA_OUTFIFO_WDATA_CH0 0x000001FF +#define GDMA_OUTFIFO_WDATA_CH0_M ((GDMA_OUTFIFO_WDATA_CH0_V)<<(GDMA_OUTFIFO_WDATA_CH0_S)) +#define GDMA_OUTFIFO_WDATA_CH0_V 0x1FF +#define GDMA_OUTFIFO_WDATA_CH0_S 0 + +#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) +/* GDMA_OUTLINK_PARK_CH0 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F +SM is working..*/ +#define GDMA_OUTLINK_PARK_CH0 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH0_M (BIT(23)) +#define GDMA_OUTLINK_PARK_CH0_V 0x1 +#define GDMA_OUTLINK_PARK_CH0_S 23 +/* GDMA_OUTLINK_RESTART_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address. .*/ +#define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH0_M (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH0_V 0x1 +#define GDMA_OUTLINK_RESTART_CH0_S 22 +/* GDMA_OUTLINK_START_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_START_CH0 (BIT(21)) +#define GDMA_OUTLINK_START_CH0_M (BIT(21)) +#define GDMA_OUTLINK_START_CH0_V 0x1 +#define GDMA_OUTLINK_START_CH0_S 21 +/* GDMA_OUTLINK_STOP_CH0 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_STOP_CH0 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH0_M (BIT(20)) +#define GDMA_OUTLINK_STOP_CH0_V 0x1 +#define GDMA_OUTLINK_STOP_CH0_S 20 +/* GDMA_OUTLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first outlink descript +or's address..*/ +#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFF +#define GDMA_OUTLINK_ADDR_CH0_M ((GDMA_OUTLINK_ADDR_CH0_V)<<(GDMA_OUTLINK_ADDR_CH0_S)) +#define GDMA_OUTLINK_ADDR_CH0_V 0xFFFFF +#define GDMA_OUTLINK_ADDR_CH0_S 0 + +#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) +/* GDMA_OUT_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_STATE_CH0 0x00000007 +#define GDMA_OUT_STATE_CH0_M ((GDMA_OUT_STATE_CH0_V)<<(GDMA_OUT_STATE_CH0_S)) +#define GDMA_OUT_STATE_CH0_V 0x7 +#define GDMA_OUT_STATE_CH0_S 20 +/* GDMA_OUT_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_DSCR_STATE_CH0 0x00000003 +#define GDMA_OUT_DSCR_STATE_CH0_M ((GDMA_OUT_DSCR_STATE_CH0_V)<<(GDMA_OUT_DSCR_STATE_CH0_S)) +#define GDMA_OUT_DSCR_STATE_CH0_V 0x3 +#define GDMA_OUT_DSCR_STATE_CH0_S 18 +/* GDMA_OUTLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address..*/ +#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH0_M ((GDMA_OUTLINK_DSCR_ADDR_CH0_V)<<(GDMA_OUTLINK_DSCR_ADDR_CH0_S)) +#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x3FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 + +#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) +/* GDMA_OUT_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when the EOF bit in t +his descriptor is 1..*/ +#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH0_M ((GDMA_OUT_EOF_DES_ADDR_CH0_V)<<(GDMA_OUT_EOF_DES_ADDR_CH0_S)) +#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 + +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8C) +/* GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before the last outli +nk descriptor..*/ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S)) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) +/* GDMA_OUTLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y..*/ +#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH0_M ((GDMA_OUTLINK_DSCR_CH0_V)<<(GDMA_OUTLINK_DSCR_CH0_S)) +#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH0_S 0 + +#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) +/* GDMA_OUTLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1..*/ +#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH0_M ((GDMA_OUTLINK_DSCR_BF0_CH0_V)<<(GDMA_OUTLINK_DSCR_BF0_CH0_S)) +#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 + +#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) +/* GDMA_OUTLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH0_M ((GDMA_OUTLINK_DSCR_BF1_CH0_V)<<(GDMA_OUTLINK_DSCR_BF1_CH0_S)) +#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 + +#define GDMA_OUT_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x9C) +/* GDMA_TX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Tx channel 0. .*/ +#define GDMA_TX_WEIGHT_CH0 0x0000000F +#define GDMA_TX_WEIGHT_CH0_M ((GDMA_TX_WEIGHT_CH0_V)<<(GDMA_TX_WEIGHT_CH0_S)) +#define GDMA_TX_WEIGHT_CH0_V 0xF +#define GDMA_TX_WEIGHT_CH0_S 8 + +#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xA4) +/* GDMA_TX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 0. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_TX_PRI_CH0 0x0000000F +#define GDMA_TX_PRI_CH0_M ((GDMA_TX_PRI_CH0_V)<<(GDMA_TX_PRI_CH0_S)) +#define GDMA_TX_PRI_CH0_V 0xF +#define GDMA_TX_PRI_CH0_S 0 + +#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xA8) +/* GDMA_PERI_OUT_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_OUT_SEL_CH0 0x0000003F +#define GDMA_PERI_OUT_SEL_CH0_M ((GDMA_PERI_OUT_SEL_CH0_V)<<(GDMA_PERI_OUT_SEL_CH0_S)) +#define GDMA_PERI_OUT_SEL_CH0_V 0x3F +#define GDMA_PERI_OUT_SEL_CH0_S 0 + +#define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0xC0) +/* GDMA_MEM_TRANS_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D +MA..*/ +#define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_M (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_V 0x1 +#define GDMA_MEM_TRANS_EN_CH1_S 4 +/* GDMA_IN_DATA_BURST_EN_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data +when accessing internal SRAM. .*/ +#define GDMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH1_M (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH1_V 0x1 +#define GDMA_IN_DATA_BURST_EN_CH1_S 3 +/* GDMA_INDSCR_BURST_EN_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_M (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_V 0x1 +#define GDMA_INDSCR_BURST_EN_CH1_S 2 +/* GDMA_IN_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_M (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_V 0x1 +#define GDMA_IN_LOOP_TEST_CH1_S 1 +/* GDMA_IN_RST_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer..*/ +#define GDMA_IN_RST_CH1 (BIT(0)) +#define GDMA_IN_RST_CH1_M (BIT(0)) +#define GDMA_IN_RST_CH1_V 0x1 +#define GDMA_IN_RST_CH1_S 0 + +#define GDMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0xC4) +/* GDMA_IN_EXT_MEM_BK_SIZE_CH1 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 1 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_IN_EXT_MEM_BK_SIZE_CH1 0x00000003 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH1_V)<<(GDMA_IN_EXT_MEM_BK_SIZE_CH1_S)) +#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_V 0x3 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_S 13 + /* Memory block size value supported by RX channel */ #define GDMA_IN_EXT_MEM_BK_SIZE_16B (0) #define GDMA_IN_EXT_MEM_BK_SIZE_32B (1) -/* GDMA_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define GDMA_CHECK_OWNER_CH0 (BIT(12)) -#define GDMA_CHECK_OWNER_CH0_M (BIT(12)) -#define GDMA_CHECK_OWNER_CH0_V 0x1 -#define GDMA_CHECK_OWNER_CH0_S 12 -/* GDMA_INFIFO_FULL_THRS_CH0 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt - when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/ -#define GDMA_INFIFO_FULL_THRS_CH0 0x00000FFF -#define GDMA_INFIFO_FULL_THRS_CH0_M ((GDMA_INFIFO_FULL_THRS_CH0_V) << (GDMA_INFIFO_FULL_THRS_CH0_S)) -#define GDMA_INFIFO_FULL_THRS_CH0_V 0xFFF -#define GDMA_INFIFO_FULL_THRS_CH0_S 0 -#define GDMA_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x018) -/* GDMA_OUT_EXT_MEM_BK_SIZE_CH1 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ -/*description: Block size of Tx channel 1 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH1 0x00000003 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH1_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH1_V) << (GDMA_OUT_EXT_MEM_BK_SIZE_CH1_S)) -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH1_V 0x3 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH1_S 15 -/* GDMA_IN_EXT_MEM_BK_SIZE_CH1 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ -/*description: Block size of Rx channel 1 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_IN_EXT_MEM_BK_SIZE_CH1 0x00000003 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH1_V) << (GDMA_IN_EXT_MEM_BK_SIZE_CH1_S)) -#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_V 0x3 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH1_S 13 -/* GDMA_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define GDMA_CHECK_OWNER_CH1 (BIT(12)) -#define GDMA_CHECK_OWNER_CH1_M (BIT(12)) -#define GDMA_CHECK_OWNER_CH1_V 0x1 -#define GDMA_CHECK_OWNER_CH1_S 12 -/* GDMA_INFIFO_FULL_THRS_CH1 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt - when Rx channel 1 received byte number in Rx FIFO is up to the value of the register.*/ -#define GDMA_INFIFO_FULL_THRS_CH1 0x00000FFF -#define GDMA_INFIFO_FULL_THRS_CH1_M ((GDMA_INFIFO_FULL_THRS_CH1_V) << (GDMA_INFIFO_FULL_THRS_CH1_S)) -#define GDMA_INFIFO_FULL_THRS_CH1_V 0xFFF -#define GDMA_INFIFO_FULL_THRS_CH1_S 0 +/* GDMA_IN_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_M (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_V 0x1 +#define GDMA_IN_CHECK_OWNER_CH1_S 12 +/* GDMA_DMA_INFIFO_FULL_THRS_CH1 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann +el 0 received byte number in Rx FIFO is up to the value of the register..*/ +#define GDMA_DMA_INFIFO_FULL_THRS_CH1 0x00000FFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH1_M ((GDMA_DMA_INFIFO_FULL_THRS_CH1_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH1_S)) +#define GDMA_DMA_INFIFO_FULL_THRS_CH1_V 0xFFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH1_S 0 -#define GDMA_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x01C) -/* GDMA_OUT_EXT_MEM_BK_SIZE_CH2 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ -/*description: Block size of Tx channel 2 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH2 0x00000003 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH2_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH2_V) << (GDMA_OUT_EXT_MEM_BK_SIZE_CH2_S)) -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH2_V 0x3 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH2_S 15 -/* GDMA_IN_EXT_MEM_BK_SIZE_CH2 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ -/*description: Block size of Rx channel 2 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_IN_EXT_MEM_BK_SIZE_CH2 0x00000003 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH2_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH2_V) << (GDMA_IN_EXT_MEM_BK_SIZE_CH2_S)) -#define GDMA_IN_EXT_MEM_BK_SIZE_CH2_V 0x3 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH2_S 13 -/* GDMA_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define GDMA_CHECK_OWNER_CH2 (BIT(12)) -#define GDMA_CHECK_OWNER_CH2_M (BIT(12)) -#define GDMA_CHECK_OWNER_CH2_V 0x1 -#define GDMA_CHECK_OWNER_CH2_S 12 -/* GDMA_INFIFO_FULL_THRS_CH2 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt - when Rx channel 2 received byte number in Rx FIFO is up to the value of the register.*/ -#define GDMA_INFIFO_FULL_THRS_CH2 0x00000FFF -#define GDMA_INFIFO_FULL_THRS_CH2_M ((GDMA_INFIFO_FULL_THRS_CH2_V) << (GDMA_INFIFO_FULL_THRS_CH2_S)) -#define GDMA_INFIFO_FULL_THRS_CH2_V 0xFFF -#define GDMA_INFIFO_FULL_THRS_CH2_S 0 +#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0xC8) +/* GDMA_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 1 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH1_INT_RAW_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH1_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH1_INT_RAW_S 9 +/* GDMA_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 1 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_S 8 +/* GDMA_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L1_CH1_INT_RAW (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH1_INT_RAW_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH1_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH1_INT_RAW_S 7 +/* GDMA_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L1_CH1_INT_RAW (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_S 6 +/* GDMA_INFIFO_FULL_WM_CH1_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data byte number is up t +o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 1..*/ +#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_S 5 +/* GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu +ll and receiving data is not completed, but there is no more inlink for Rx chann +el 1..*/ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/* GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink descriptor error +, including owner error, the second and third word error of inlink descriptor fo +r Rx channel 1..*/ +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/* GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is detected only in th +e case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, thi +s raw interrupt is reserved..*/ +#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x1 +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/* GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt b +it turns to high level when the last data pointed by one inlink descriptor has b +een received and no data error is detected for Rx channel 0..*/ +#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x1 +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/* GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 1..*/ +#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_M (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_V 0x1 +#define GDMA_IN_DONE_CH1_INT_RAW_S 0 -#define GDMA_CONF1_CH3_REG (DR_REG_GDMA_BASE + 0x020) -/* GDMA_OUT_EXT_MEM_BK_SIZE_CH3 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ -/*description: Block size of Tx channel 3 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH3 0x00000003 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH3_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH3_V) << (GDMA_OUT_EXT_MEM_BK_SIZE_CH3_S)) -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH3_V 0x3 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH3_S 15 -/* GDMA_IN_EXT_MEM_BK_SIZE_CH3 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ -/*description: Block size of Rx channel 3 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_IN_EXT_MEM_BK_SIZE_CH3 0x00000003 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH3_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH3_V) << (GDMA_IN_EXT_MEM_BK_SIZE_CH3_S)) -#define GDMA_IN_EXT_MEM_BK_SIZE_CH3_V 0x3 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH3_S 13 -/* GDMA_CHECK_OWNER_CH3 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define GDMA_CHECK_OWNER_CH3 (BIT(12)) -#define GDMA_CHECK_OWNER_CH3_M (BIT(12)) -#define GDMA_CHECK_OWNER_CH3_V 0x1 -#define GDMA_CHECK_OWNER_CH3_S 12 -/* GDMA_INFIFO_FULL_THRS_CH3 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt - when Rx channel 3 received byte number in Rx FIFO is up to the value of the register.*/ -#define GDMA_INFIFO_FULL_THRS_CH3 0x00000FFF -#define GDMA_INFIFO_FULL_THRS_CH3_M ((GDMA_INFIFO_FULL_THRS_CH3_V) << (GDMA_INFIFO_FULL_THRS_CH3_S)) -#define GDMA_INFIFO_FULL_THRS_CH3_V 0xFFF -#define GDMA_INFIFO_FULL_THRS_CH3_S 0 - -#define GDMA_CONF1_CH4_REG (DR_REG_GDMA_BASE + 0x024) -/* GDMA_OUT_EXT_MEM_BK_SIZE_CH4 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ -/*description: Block size of Tx channel 4 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH4 0x00000003 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH4_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH4_V) << (GDMA_OUT_EXT_MEM_BK_SIZE_CH4_S)) -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH4_V 0x3 -#define GDMA_OUT_EXT_MEM_BK_SIZE_CH4_S 15 -/* GDMA_IN_EXT_MEM_BK_SIZE_CH4 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ -/*description: Block size of Rx channel 4 when DMA access external SRAM. 0: - 16 bytes 1: 32 bytes 2/3:reserved*/ -#define GDMA_IN_EXT_MEM_BK_SIZE_CH4 0x00000003 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH4_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH4_V) << (GDMA_IN_EXT_MEM_BK_SIZE_CH4_S)) -#define GDMA_IN_EXT_MEM_BK_SIZE_CH4_V 0x3 -#define GDMA_IN_EXT_MEM_BK_SIZE_CH4_S 13 -/* GDMA_CHECK_OWNER_CH4 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define GDMA_CHECK_OWNER_CH4 (BIT(12)) -#define GDMA_CHECK_OWNER_CH4_M (BIT(12)) -#define GDMA_CHECK_OWNER_CH4_V 0x1 -#define GDMA_CHECK_OWNER_CH4_S 12 -/* GDMA_INFIFO_FULL_THRS_CH4 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt - when Rx channel 4 received byte number in Rx FIFO is up to the value of the register.*/ -#define GDMA_INFIFO_FULL_THRS_CH4 0x00000FFF -#define GDMA_INFIFO_FULL_THRS_CH4_M ((GDMA_INFIFO_FULL_THRS_CH4_V) << (GDMA_INFIFO_FULL_THRS_CH4_S)) -#define GDMA_INFIFO_FULL_THRS_CH4_V 0xFFF -#define GDMA_INFIFO_FULL_THRS_CH4_S 0 - -#define GDMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x028) -/* GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 0 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_RAW_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 0 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_RAW_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S 14 -/* GDMA_INFIFO_UDF_L3_CH0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 0 is underflow.*/ -#define GDMA_INFIFO_UDF_L3_CH0_INT_RAW (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH0_INT_RAW_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH0_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH0_INT_RAW_S 13 -/* GDMA_INFIFO_OVF_L3_CH0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 0 is overflow.*/ -#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH0_INT_RAW_S 12 -/* GDMA_INFIFO_UDF_L1_CH0_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is underflow.*/ -#define GDMA_INFIFO_UDF_L1_CH0_INT_RAW (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH0_INT_RAW_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH0_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH0_INT_RAW_S 11 -/* GDMA_INFIFO_OVF_L1_CH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is overflow.*/ -#define GDMA_INFIFO_OVF_L1_CH0_INT_RAW (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_S 10 -/* GDMA_INFIFO_FULL_WM_CH0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data - byte number is up to threshold configured by REG_GDMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/ -#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_S 9 -/* GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ -#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8 -/* GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ -#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7 -/* GDMA_OUT_DSCR_ERR_CH0_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ -#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6 -/* GDMA_IN_DSCR_ERR_CH0_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ -#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 5 -/* GDMA_OUT_EOF_CH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ -#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(4)) -#define GDMA_OUT_EOF_CH0_INT_RAW_M (BIT(4)) -#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x1 -#define GDMA_OUT_EOF_CH0_INT_RAW_S 4 -/* GDMA_OUT_DONE_CH0_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ -#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(3)) -#define GDMA_OUT_DONE_CH0_INT_RAW_M (BIT(3)) -#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x1 -#define GDMA_OUT_DONE_CH0_INT_RAW_S 3 -/* GDMA_IN_ERR_EOF_CH0_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ -#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) -#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x1 -#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 -/* GDMA_IN_SUC_EOF_CH0_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ -#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) -#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x1 -#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 -/* GDMA_IN_DONE_CH0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 0.*/ -#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) -#define GDMA_IN_DONE_CH0_INT_RAW_M (BIT(0)) -#define GDMA_IN_DONE_CH0_INT_RAW_V 0x1 -#define GDMA_IN_DONE_CH0_INT_RAW_S 0 - -#define GDMA_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x02C) -/* GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 1 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 1 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 1 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 1 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S 14 -/* GDMA_INFIFO_UDF_L3_CH1_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 1 is underflow.*/ -#define GDMA_INFIFO_UDF_L3_CH1_INT_RAW (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH1_INT_RAW_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH1_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH1_INT_RAW_S 13 -/* GDMA_INFIFO_OVF_L3_CH1_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 1 is overflow.*/ -#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH1_INT_RAW_S 12 -/* GDMA_INFIFO_UDF_L1_CH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 1 is underflow.*/ -#define GDMA_INFIFO_UDF_L1_CH1_INT_RAW (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH1_INT_RAW_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH1_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH1_INT_RAW_S 11 -/* GDMA_INFIFO_OVF_L1_CH1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 1 is overflow.*/ -#define GDMA_INFIFO_OVF_L1_CH1_INT_RAW (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_S 10 -/* GDMA_INFIFO_FULL_WM_CH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data - byte number is up to threshold configured by REG_GDMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 1.*/ -#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_S 9 -/* GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.*/ -#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 8 -/* GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 1.*/ -#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 7 -/* GDMA_OUT_DSCR_ERR_CH1_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 1.*/ -#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 6 -/* GDMA_IN_DSCR_ERR_CH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 1.*/ -#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 5 -/* GDMA_OUT_EOF_CH1_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory for Tx channel 1.*/ -#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(4)) -#define GDMA_OUT_EOF_CH1_INT_RAW_M (BIT(4)) -#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x1 -#define GDMA_OUT_EOF_CH1_INT_RAW_S 4 -/* GDMA_OUT_DONE_CH1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.*/ -#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(3)) -#define GDMA_OUT_DONE_CH1_INT_RAW_M (BIT(3)) -#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x1 -#define GDMA_OUT_DONE_CH1_INT_RAW_S 3 -/* GDMA_IN_ERR_EOF_CH1_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw interrupt is reserved.*/ -#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) -#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x1 -#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 -/* GDMA_IN_SUC_EOF_CH1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.*/ -#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) -#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x1 -#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 -/* GDMA_IN_DONE_CH1_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 1.*/ -#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) -#define GDMA_IN_DONE_CH1_INT_RAW_M (BIT(0)) -#define GDMA_IN_DONE_CH1_INT_RAW_V 0x1 -#define GDMA_IN_DONE_CH1_INT_RAW_S 0 - -#define GDMA_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x030) -/* GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 2 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 2 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 2 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 2 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S 14 -/* GDMA_INFIFO_UDF_L3_CH2_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 2 is underflow.*/ -#define GDMA_INFIFO_UDF_L3_CH2_INT_RAW (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH2_INT_RAW_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH2_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH2_INT_RAW_S 13 -/* GDMA_INFIFO_OVF_L3_CH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 2 is overflow.*/ -#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_S 12 -/* GDMA_INFIFO_UDF_L1_CH2_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 2 is underflow.*/ -#define GDMA_INFIFO_UDF_L1_CH2_INT_RAW (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH2_INT_RAW_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH2_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH2_INT_RAW_S 11 -/* GDMA_INFIFO_OVF_L1_CH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 2 is overflow.*/ -#define GDMA_INFIFO_OVF_L1_CH2_INT_RAW (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_S 10 -/* GDMA_INFIFO_FULL_WM_CH2_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data - byte number is up to threshold configured by REG_GDMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 2.*/ -#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_S 9 -/* GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.*/ -#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 8 -/* GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 2.*/ -#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 7 -/* GDMA_OUT_DSCR_ERR_CH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 2.*/ -#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 6 -/* GDMA_IN_DSCR_ERR_CH2_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 2.*/ -#define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 5 -/* GDMA_OUT_EOF_CH2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory for Tx channel 2.*/ -#define GDMA_OUT_EOF_CH2_INT_RAW (BIT(4)) -#define GDMA_OUT_EOF_CH2_INT_RAW_M (BIT(4)) -#define GDMA_OUT_EOF_CH2_INT_RAW_V 0x1 -#define GDMA_OUT_EOF_CH2_INT_RAW_S 4 -/* GDMA_OUT_DONE_CH2_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.*/ -#define GDMA_OUT_DONE_CH2_INT_RAW (BIT(3)) -#define GDMA_OUT_DONE_CH2_INT_RAW_M (BIT(3)) -#define GDMA_OUT_DONE_CH2_INT_RAW_V 0x1 -#define GDMA_OUT_DONE_CH2_INT_RAW_S 3 -/* GDMA_IN_ERR_EOF_CH2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw interrupt is reserved.*/ -#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) -#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x1 -#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2 -/* GDMA_IN_SUC_EOF_CH2_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.*/ -#define GDMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) -#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V 0x1 -#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S 1 -/* GDMA_IN_DONE_CH2_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 2.*/ -#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0)) -#define GDMA_IN_DONE_CH2_INT_RAW_M (BIT(0)) -#define GDMA_IN_DONE_CH2_INT_RAW_V 0x1 -#define GDMA_IN_DONE_CH2_INT_RAW_S 0 - -#define GDMA_INT_RAW_CH3_REG (DR_REG_GDMA_BASE + 0x034) -/* GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 3 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 3 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 3 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 3 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S 14 -/* GDMA_INFIFO_UDF_L3_CH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 3 is underflow.*/ -#define GDMA_INFIFO_UDF_L3_CH3_INT_RAW (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH3_INT_RAW_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH3_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH3_INT_RAW_S 13 -/* GDMA_INFIFO_OVF_L3_CH3_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 3 is overflow.*/ -#define GDMA_INFIFO_OVF_L3_CH3_INT_RAW (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH3_INT_RAW_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH3_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH3_INT_RAW_S 12 -/* GDMA_INFIFO_UDF_L1_CH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 3 is underflow.*/ -#define GDMA_INFIFO_UDF_L1_CH3_INT_RAW (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH3_INT_RAW_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH3_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH3_INT_RAW_S 11 -/* GDMA_INFIFO_OVF_L1_CH3_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 3 is overflow.*/ -#define GDMA_INFIFO_OVF_L1_CH3_INT_RAW (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_S 10 -/* GDMA_INFIFO_FULL_WM_CH3_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data - byte number is up to threshold configured by REG_GDMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 3.*/ -#define GDMA_INFIFO_FULL_WM_CH3_INT_RAW (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_S 9 -/* GDMA_OUT_TOTAL_EOF_CH3_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 3.*/ -#define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_S 8 -/* GDMA_IN_DSCR_EMPTY_CH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 3.*/ -#define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_S 7 -/* GDMA_OUT_DSCR_ERR_CH3_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 3.*/ -#define GDMA_OUT_DSCR_ERR_CH3_INT_RAW (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_S 6 -/* GDMA_IN_DSCR_ERR_CH3_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 3.*/ -#define GDMA_IN_DSCR_ERR_CH3_INT_RAW (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH3_INT_RAW_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH3_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_ERR_CH3_INT_RAW_S 5 -/* GDMA_OUT_EOF_CH3_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory for Tx channel 3.*/ -#define GDMA_OUT_EOF_CH3_INT_RAW (BIT(4)) -#define GDMA_OUT_EOF_CH3_INT_RAW_M (BIT(4)) -#define GDMA_OUT_EOF_CH3_INT_RAW_V 0x1 -#define GDMA_OUT_EOF_CH3_INT_RAW_S 4 -/* GDMA_OUT_DONE_CH3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 3.*/ -#define GDMA_OUT_DONE_CH3_INT_RAW (BIT(3)) -#define GDMA_OUT_DONE_CH3_INT_RAW_M (BIT(3)) -#define GDMA_OUT_DONE_CH3_INT_RAW_V 0x1 -#define GDMA_OUT_DONE_CH3_INT_RAW_S 3 -/* GDMA_IN_ERR_EOF_CH3_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 for Rx channel 3. For other peripherals this raw interrupt is reserved.*/ -#define GDMA_IN_ERR_EOF_CH3_INT_RAW (BIT(2)) -#define GDMA_IN_ERR_EOF_CH3_INT_RAW_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH3_INT_RAW_V 0x1 -#define GDMA_IN_ERR_EOF_CH3_INT_RAW_S 2 -/* GDMA_IN_SUC_EOF_CH3_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 3. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 3.*/ -#define GDMA_IN_SUC_EOF_CH3_INT_RAW (BIT(1)) -#define GDMA_IN_SUC_EOF_CH3_INT_RAW_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH3_INT_RAW_V 0x1 -#define GDMA_IN_SUC_EOF_CH3_INT_RAW_S 1 -/* GDMA_IN_DONE_CH3_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 3.*/ -#define GDMA_IN_DONE_CH3_INT_RAW (BIT(0)) -#define GDMA_IN_DONE_CH3_INT_RAW_M (BIT(0)) -#define GDMA_IN_DONE_CH3_INT_RAW_V 0x1 -#define GDMA_IN_DONE_CH3_INT_RAW_S 0 - -#define GDMA_INT_RAW_CH4_REG (DR_REG_GDMA_BASE + 0x038) -/* GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 4 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Tx channel 4 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 4 is underflow.*/ -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 4 is overflow.*/ -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S 14 -/* GDMA_INFIFO_UDF_L3_CH4_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 4 is underflow.*/ -#define GDMA_INFIFO_UDF_L3_CH4_INT_RAW (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH4_INT_RAW_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH4_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH4_INT_RAW_S 13 -/* GDMA_INFIFO_OVF_L3_CH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 3 fifo - of Rx channel 4 is overflow.*/ -#define GDMA_INFIFO_OVF_L3_CH4_INT_RAW (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH4_INT_RAW_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH4_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH4_INT_RAW_S 12 -/* GDMA_INFIFO_UDF_L1_CH4_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 4 is underflow.*/ -#define GDMA_INFIFO_UDF_L1_CH4_INT_RAW (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH4_INT_RAW_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH4_INT_RAW_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH4_INT_RAW_S 11 -/* GDMA_INFIFO_OVF_L1_CH4_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 4 is overflow.*/ -#define GDMA_INFIFO_OVF_L1_CH4_INT_RAW (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_S 10 -/* GDMA_INFIFO_FULL_WM_CH4_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data - byte number is up to threshold configured by REG_GDMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 4.*/ -#define GDMA_INFIFO_FULL_WM_CH4_INT_RAW (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_S 9 -/* GDMA_OUT_TOTAL_EOF_CH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 4.*/ -#define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_S 8 -/* GDMA_IN_DSCR_EMPTY_CH4_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 4.*/ -#define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_S 7 -/* GDMA_OUT_DSCR_ERR_CH4_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 4.*/ -#define GDMA_OUT_DSCR_ERR_CH4_INT_RAW (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_S 6 -/* GDMA_IN_DSCR_ERR_CH4_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 4.*/ -#define GDMA_IN_DSCR_ERR_CH4_INT_RAW (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH4_INT_RAW_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH4_INT_RAW_V 0x1 -#define GDMA_IN_DSCR_ERR_CH4_INT_RAW_S 5 -/* GDMA_OUT_EOF_CH4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory for Tx channel 4.*/ -#define GDMA_OUT_EOF_CH4_INT_RAW (BIT(4)) -#define GDMA_OUT_EOF_CH4_INT_RAW_M (BIT(4)) -#define GDMA_OUT_EOF_CH4_INT_RAW_V 0x1 -#define GDMA_OUT_EOF_CH4_INT_RAW_S 4 -/* GDMA_OUT_DONE_CH4_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 4.*/ -#define GDMA_OUT_DONE_CH4_INT_RAW (BIT(3)) -#define GDMA_OUT_DONE_CH4_INT_RAW_M (BIT(3)) -#define GDMA_OUT_DONE_CH4_INT_RAW_V 0x1 -#define GDMA_OUT_DONE_CH4_INT_RAW_S 3 -/* GDMA_IN_ERR_EOF_CH4_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 for Rx channel 4. For other peripherals this raw interrupt is reserved.*/ -#define GDMA_IN_ERR_EOF_CH4_INT_RAW (BIT(2)) -#define GDMA_IN_ERR_EOF_CH4_INT_RAW_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH4_INT_RAW_V 0x1 -#define GDMA_IN_ERR_EOF_CH4_INT_RAW_S 2 -/* GDMA_IN_SUC_EOF_CH4_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 4. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 4.*/ -#define GDMA_IN_SUC_EOF_CH4_INT_RAW (BIT(1)) -#define GDMA_IN_SUC_EOF_CH4_INT_RAW_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH4_INT_RAW_V 0x1 -#define GDMA_IN_SUC_EOF_CH4_INT_RAW_S 1 -/* GDMA_IN_DONE_CH4_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 4.*/ -#define GDMA_IN_DONE_CH4_INT_RAW (BIT(0)) -#define GDMA_IN_DONE_CH4_INT_RAW_M (BIT(0)) -#define GDMA_IN_DONE_CH4_INT_RAW_V 0x1 -#define GDMA_IN_DONE_CH4_INT_RAW_S 0 - -#define GDMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x040) -/* GDMA_OUTFIFO_UDF_L3_CH0_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ST_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ST (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ST_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ST_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH0_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ST (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ST_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ST_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH0_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ST_S 14 -/* GDMA_INFIFO_UDF_L3_CH0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH0_INT_ST (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH0_INT_ST_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH0_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH0_INT_ST_S 13 -/* GDMA_INFIFO_OVF_L3_CH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH0_INT_ST (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH0_INT_ST_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH0_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH0_INT_ST_S 12 -/* GDMA_INFIFO_UDF_L1_CH0_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH0_INT_ST (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH0_INT_ST_S 11 -/* GDMA_INFIFO_OVF_L1_CH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH0_INT_ST (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH0_INT_ST_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH0_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH0_INT_ST_S 10 -/* GDMA_INFIFO_FULL_WM_CH0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH0_INT_ST (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH0_INT_ST_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH0_INT_ST_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH0_INT_ST_S 9 -/* GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8 -/* GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7 -/* GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 6 -/* GDMA_IN_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x1 -#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 5 -/* GDMA_OUT_EOF_CH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH0_INT_ST (BIT(4)) -#define GDMA_OUT_EOF_CH0_INT_ST_M (BIT(4)) -#define GDMA_OUT_EOF_CH0_INT_ST_V 0x1 -#define GDMA_OUT_EOF_CH0_INT_ST_S 4 -/* GDMA_OUT_DONE_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH0_INT_ST (BIT(3)) -#define GDMA_OUT_DONE_CH0_INT_ST_M (BIT(3)) -#define GDMA_OUT_DONE_CH0_INT_ST_V 0x1 -#define GDMA_OUT_DONE_CH0_INT_ST_S 3 -/* GDMA_IN_ERR_EOF_CH0_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) -#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x1 -#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 -/* GDMA_IN_SUC_EOF_CH0_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) -#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x1 -#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 -/* GDMA_IN_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) -#define GDMA_IN_DONE_CH0_INT_ST_M (BIT(0)) -#define GDMA_IN_DONE_CH0_INT_ST_V 0x1 -#define GDMA_IN_DONE_CH0_INT_ST_S 0 - -#define GDMA_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x044) -/* GDMA_OUTFIFO_UDF_L3_CH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH1_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ST (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ST_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ST_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH1_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ST (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ST_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ST_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH1_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_S 14 -/* GDMA_INFIFO_UDF_L3_CH1_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH1_INT_ST (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH1_INT_ST_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH1_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH1_INT_ST_S 13 -/* GDMA_INFIFO_OVF_L3_CH1_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH1_INT_ST (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH1_INT_ST_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH1_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH1_INT_ST_S 12 -/* GDMA_INFIFO_UDF_L1_CH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH1_INT_ST (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_S 11 -/* GDMA_INFIFO_OVF_L1_CH1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH1_INT_ST (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH1_INT_ST_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH1_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH1_INT_ST_S 10 -/* GDMA_INFIFO_FULL_WM_CH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH1_INT_ST (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH1_INT_ST_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH1_INT_ST_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH1_INT_ST_S 9 -/* GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 8 -/* GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 7 -/* GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 6 -/* GDMA_IN_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x1 -#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 5 -/* GDMA_OUT_EOF_CH1_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH1_INT_ST (BIT(4)) -#define GDMA_OUT_EOF_CH1_INT_ST_M (BIT(4)) -#define GDMA_OUT_EOF_CH1_INT_ST_V 0x1 -#define GDMA_OUT_EOF_CH1_INT_ST_S 4 -/* GDMA_OUT_DONE_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH1_INT_ST (BIT(3)) -#define GDMA_OUT_DONE_CH1_INT_ST_M (BIT(3)) -#define GDMA_OUT_DONE_CH1_INT_ST_V 0x1 -#define GDMA_OUT_DONE_CH1_INT_ST_S 3 +#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0xCC) +/* GDMA_INFIFO_UDF_L3_CH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH1_INT_ST (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH1_INT_ST_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH1_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH1_INT_ST_S 9 +/* GDMA_INFIFO_OVF_L3_CH1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH1_INT_ST (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH1_INT_ST_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH1_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH1_INT_ST_S 8 +/* GDMA_INFIFO_UDF_L1_CH1_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH1_INT_ST (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH1_INT_ST_S 7 +/* GDMA_INFIFO_OVF_L1_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH1_INT_ST (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH1_INT_ST_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH1_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH1_INT_ST_S 6 +/* GDMA_INFIFO_FULL_WM_CH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH1_INT_ST (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH1_INT_ST_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH1_INT_ST_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH1_INT_ST_S 5 +/* GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/* GDMA_IN_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x1 +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 3 /* GDMA_IN_ERR_EOF_CH1_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) -#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x1 -#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x1 +#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 /* GDMA_IN_SUC_EOF_CH1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) -#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x1 -#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x1 +#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 /* GDMA_IN_DONE_CH1_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) -#define GDMA_IN_DONE_CH1_INT_ST_M (BIT(0)) -#define GDMA_IN_DONE_CH1_INT_ST_V 0x1 -#define GDMA_IN_DONE_CH1_INT_ST_S 0 +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_M (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_V 0x1 +#define GDMA_IN_DONE_CH1_INT_ST_S 0 -#define GDMA_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x048) -/* GDMA_OUTFIFO_UDF_L3_CH2_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH2_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ST (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ST_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ST_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH2_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ST (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ST_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ST_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_S 14 -/* GDMA_INFIFO_UDF_L3_CH2_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH2_INT_ST (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH2_INT_ST_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH2_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH2_INT_ST_S 13 -/* GDMA_INFIFO_OVF_L3_CH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH2_INT_ST (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH2_INT_ST_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH2_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH2_INT_ST_S 12 -/* GDMA_INFIFO_UDF_L1_CH2_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH2_INT_ST (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_S 11 -/* GDMA_INFIFO_OVF_L1_CH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH2_INT_ST (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH2_INT_ST_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH2_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH2_INT_ST_S 10 -/* GDMA_INFIFO_FULL_WM_CH2_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH2_INT_ST (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH2_INT_ST_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH2_INT_ST_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH2_INT_ST_S 9 -/* GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S 8 -/* GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 7 -/* GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S 6 -/* GDMA_IN_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH2_INT_ST (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V 0x1 -#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S 5 -/* GDMA_OUT_EOF_CH2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH2_INT_ST (BIT(4)) -#define GDMA_OUT_EOF_CH2_INT_ST_M (BIT(4)) -#define GDMA_OUT_EOF_CH2_INT_ST_V 0x1 -#define GDMA_OUT_EOF_CH2_INT_ST_S 4 -/* GDMA_OUT_DONE_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH2_INT_ST (BIT(3)) -#define GDMA_OUT_DONE_CH2_INT_ST_M (BIT(3)) -#define GDMA_OUT_DONE_CH2_INT_ST_V 0x1 -#define GDMA_OUT_DONE_CH2_INT_ST_S 3 -/* GDMA_IN_ERR_EOF_CH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) -#define GDMA_IN_ERR_EOF_CH2_INT_ST_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH2_INT_ST_V 0x1 -#define GDMA_IN_ERR_EOF_CH2_INT_ST_S 2 -/* GDMA_IN_SUC_EOF_CH2_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) -#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x1 -#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1 -/* GDMA_IN_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH2_INT_ST (BIT(0)) -#define GDMA_IN_DONE_CH2_INT_ST_M (BIT(0)) -#define GDMA_IN_DONE_CH2_INT_ST_V 0x1 -#define GDMA_IN_DONE_CH2_INT_ST_S 0 - -#define GDMA_INT_ST_CH3_REG (DR_REG_GDMA_BASE + 0x04C) -/* GDMA_OUTFIFO_UDF_L3_CH3_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ST_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ST_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH3_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ST_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ST_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH3_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ST_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ST_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH3_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ST_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ST_S 14 -/* GDMA_INFIFO_UDF_L3_CH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH3_INT_ST (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH3_INT_ST_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH3_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH3_INT_ST_S 13 -/* GDMA_INFIFO_OVF_L3_CH3_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH3_INT_ST (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH3_INT_ST_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH3_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH3_INT_ST_S 12 -/* GDMA_INFIFO_UDF_L1_CH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH3_INT_ST (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH3_INT_ST_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH3_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH3_INT_ST_S 11 -/* GDMA_INFIFO_OVF_L1_CH3_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH3_INT_ST (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH3_INT_ST_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH3_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH3_INT_ST_S 10 -/* GDMA_INFIFO_FULL_WM_CH3_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH3_INT_ST (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH3_INT_ST_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH3_INT_ST_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH3_INT_ST_S 9 -/* GDMA_OUT_TOTAL_EOF_CH3_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH3_INT_ST (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH3_INT_ST_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH3_INT_ST_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH3_INT_ST_S 8 -/* GDMA_IN_DSCR_EMPTY_CH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH3_INT_ST (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH3_INT_ST_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH3_INT_ST_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH3_INT_ST_S 7 -/* GDMA_OUT_DSCR_ERR_CH3_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH3_INT_ST (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH3_INT_ST_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH3_INT_ST_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH3_INT_ST_S 6 -/* GDMA_IN_DSCR_ERR_CH3_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH3_INT_ST (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH3_INT_ST_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH3_INT_ST_V 0x1 -#define GDMA_IN_DSCR_ERR_CH3_INT_ST_S 5 -/* GDMA_OUT_EOF_CH3_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH3_INT_ST (BIT(4)) -#define GDMA_OUT_EOF_CH3_INT_ST_M (BIT(4)) -#define GDMA_OUT_EOF_CH3_INT_ST_V 0x1 -#define GDMA_OUT_EOF_CH3_INT_ST_S 4 -/* GDMA_OUT_DONE_CH3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH3_INT_ST (BIT(3)) -#define GDMA_OUT_DONE_CH3_INT_ST_M (BIT(3)) -#define GDMA_OUT_DONE_CH3_INT_ST_V 0x1 -#define GDMA_OUT_DONE_CH3_INT_ST_S 3 -/* GDMA_IN_ERR_EOF_CH3_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH3_INT_ST (BIT(2)) -#define GDMA_IN_ERR_EOF_CH3_INT_ST_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH3_INT_ST_V 0x1 -#define GDMA_IN_ERR_EOF_CH3_INT_ST_S 2 -/* GDMA_IN_SUC_EOF_CH3_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH3_INT_ST (BIT(1)) -#define GDMA_IN_SUC_EOF_CH3_INT_ST_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH3_INT_ST_V 0x1 -#define GDMA_IN_SUC_EOF_CH3_INT_ST_S 1 -/* GDMA_IN_DONE_CH3_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH3_INT_ST (BIT(0)) -#define GDMA_IN_DONE_CH3_INT_ST_M (BIT(0)) -#define GDMA_IN_DONE_CH3_INT_ST_V 0x1 -#define GDMA_IN_DONE_CH3_INT_ST_S 0 - -#define GDMA_INT_ST_CH4_REG (DR_REG_GDMA_BASE + 0x050) -/* GDMA_OUTFIFO_UDF_L3_CH4_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ST (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ST_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ST_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH4_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ST (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ST_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ST_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH4_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ST (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ST_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ST_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ST_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ST (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ST_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ST_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ST_S 14 -/* GDMA_INFIFO_UDF_L3_CH4_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH4_INT_ST (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH4_INT_ST_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH4_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH4_INT_ST_S 13 -/* GDMA_INFIFO_OVF_L3_CH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH4_INT_ST (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH4_INT_ST_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH4_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH4_INT_ST_S 12 -/* GDMA_INFIFO_UDF_L1_CH4_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH4_INT_ST (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH4_INT_ST_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH4_INT_ST_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH4_INT_ST_S 11 -/* GDMA_INFIFO_OVF_L1_CH4_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH4_INT_ST (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH4_INT_ST_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH4_INT_ST_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH4_INT_ST_S 10 -/* GDMA_INFIFO_FULL_WM_CH4_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH4_INT_ST (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH4_INT_ST_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH4_INT_ST_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH4_INT_ST_S 9 -/* GDMA_OUT_TOTAL_EOF_CH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH4_INT_ST (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH4_INT_ST_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH4_INT_ST_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH4_INT_ST_S 8 -/* GDMA_IN_DSCR_EMPTY_CH4_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH4_INT_ST (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH4_INT_ST_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH4_INT_ST_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH4_INT_ST_S 7 -/* GDMA_OUT_DSCR_ERR_CH4_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH4_INT_ST (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH4_INT_ST_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH4_INT_ST_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH4_INT_ST_S 6 -/* GDMA_IN_DSCR_ERR_CH4_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH4_INT_ST (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH4_INT_ST_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH4_INT_ST_V 0x1 -#define GDMA_IN_DSCR_ERR_CH4_INT_ST_S 5 -/* GDMA_OUT_EOF_CH4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH4_INT_ST (BIT(4)) -#define GDMA_OUT_EOF_CH4_INT_ST_M (BIT(4)) -#define GDMA_OUT_EOF_CH4_INT_ST_V 0x1 -#define GDMA_OUT_EOF_CH4_INT_ST_S 4 -/* GDMA_OUT_DONE_CH4_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH4_INT_ST (BIT(3)) -#define GDMA_OUT_DONE_CH4_INT_ST_M (BIT(3)) -#define GDMA_OUT_DONE_CH4_INT_ST_V 0x1 -#define GDMA_OUT_DONE_CH4_INT_ST_S 3 -/* GDMA_IN_ERR_EOF_CH4_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH4_INT_ST (BIT(2)) -#define GDMA_IN_ERR_EOF_CH4_INT_ST_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH4_INT_ST_V 0x1 -#define GDMA_IN_ERR_EOF_CH4_INT_ST_S 2 -/* GDMA_IN_SUC_EOF_CH4_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH4_INT_ST (BIT(1)) -#define GDMA_IN_SUC_EOF_CH4_INT_ST_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH4_INT_ST_V 0x1 -#define GDMA_IN_SUC_EOF_CH4_INT_ST_S 1 -/* GDMA_IN_DONE_CH4_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH4_INT_ST (BIT(0)) -#define GDMA_IN_DONE_CH4_INT_ST_M (BIT(0)) -#define GDMA_IN_DONE_CH4_INT_ST_V 0x1 -#define GDMA_IN_DONE_CH4_INT_ST_S 0 - -#define GDMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x054) -/* GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_ENA_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_ENA_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_ENA_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_ENA_S 14 -/* GDMA_INFIFO_UDF_L3_CH0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH0_INT_ENA (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH0_INT_ENA_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH0_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH0_INT_ENA_S 13 -/* GDMA_INFIFO_OVF_L3_CH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH0_INT_ENA_S 12 -/* GDMA_INFIFO_UDF_L1_CH0_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH0_INT_ENA (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH0_INT_ENA_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH0_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH0_INT_ENA_S 11 -/* GDMA_INFIFO_OVF_L1_CH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH0_INT_ENA (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH0_INT_ENA_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH0_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH0_INT_ENA_S 10 -/* GDMA_INFIFO_FULL_WM_CH0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH0_INT_ENA_S 9 -/* GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8 -/* GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7 -/* GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6 -/* GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 5 -/* GDMA_OUT_EOF_CH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(4)) -#define GDMA_OUT_EOF_CH0_INT_ENA_M (BIT(4)) -#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x1 -#define GDMA_OUT_EOF_CH0_INT_ENA_S 4 -/* GDMA_OUT_DONE_CH0_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(3)) -#define GDMA_OUT_DONE_CH0_INT_ENA_M (BIT(3)) -#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x1 -#define GDMA_OUT_DONE_CH0_INT_ENA_S 3 -/* GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) -#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x1 -#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 -/* GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) -#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x1 -#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 -/* GDMA_IN_DONE_CH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) -#define GDMA_IN_DONE_CH0_INT_ENA_M (BIT(0)) -#define GDMA_IN_DONE_CH0_INT_ENA_V 0x1 -#define GDMA_IN_DONE_CH0_INT_ENA_S 0 - -#define GDMA_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x058) -/* GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA_S 14 -/* GDMA_INFIFO_UDF_L3_CH1_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH1_INT_ENA (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH1_INT_ENA_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH1_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH1_INT_ENA_S 13 -/* GDMA_INFIFO_OVF_L3_CH1_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_S 12 -/* GDMA_INFIFO_UDF_L1_CH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH1_INT_ENA (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH1_INT_ENA_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH1_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH1_INT_ENA_S 11 -/* GDMA_INFIFO_OVF_L1_CH1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH1_INT_ENA (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH1_INT_ENA_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH1_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH1_INT_ENA_S 10 -/* GDMA_INFIFO_FULL_WM_CH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_S 9 -/* GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 8 -/* GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 7 -/* GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 6 -/* GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 5 -/* GDMA_OUT_EOF_CH1_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(4)) -#define GDMA_OUT_EOF_CH1_INT_ENA_M (BIT(4)) -#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x1 -#define GDMA_OUT_EOF_CH1_INT_ENA_S 4 -/* GDMA_OUT_DONE_CH1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(3)) -#define GDMA_OUT_DONE_CH1_INT_ENA_M (BIT(3)) -#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x1 -#define GDMA_OUT_DONE_CH1_INT_ENA_S 3 +#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0xD0) +/* GDMA_INFIFO_UDF_L3_CH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH1_INT_ENA_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH1_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH1_INT_ENA_S 9 +/* GDMA_INFIFO_OVF_L3_CH1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH1_INT_ENA_S 8 +/* GDMA_INFIFO_UDF_L1_CH1_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH1_INT_ENA (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH1_INT_ENA_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH1_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH1_INT_ENA_S 7 +/* GDMA_INFIFO_OVF_L1_CH1_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH1_INT_ENA (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH1_INT_ENA_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH1_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH1_INT_ENA_S 6 +/* GDMA_INFIFO_FULL_WM_CH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH1_INT_ENA_S 5 +/* GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/* GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 /* GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) -#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x1 -#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x1 +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 /* GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) -#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x1 -#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x1 +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 /* GDMA_IN_DONE_CH1_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) -#define GDMA_IN_DONE_CH1_INT_ENA_M (BIT(0)) -#define GDMA_IN_DONE_CH1_INT_ENA_V 0x1 -#define GDMA_IN_DONE_CH1_INT_ENA_S 0 +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_M (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_V 0x1 +#define GDMA_IN_DONE_CH1_INT_ENA_S 0 -#define GDMA_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x05C) -/* GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA_S 14 -/* GDMA_INFIFO_UDF_L3_CH2_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH2_INT_ENA (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH2_INT_ENA_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH2_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH2_INT_ENA_S 13 -/* GDMA_INFIFO_OVF_L3_CH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_S 12 -/* GDMA_INFIFO_UDF_L1_CH2_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH2_INT_ENA (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH2_INT_ENA_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH2_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH2_INT_ENA_S 11 -/* GDMA_INFIFO_OVF_L1_CH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH2_INT_ENA (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH2_INT_ENA_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH2_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH2_INT_ENA_S 10 -/* GDMA_INFIFO_FULL_WM_CH2_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_S 9 -/* GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 8 -/* GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 7 -/* GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S 6 -/* GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S 5 -/* GDMA_OUT_EOF_CH2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH2_INT_ENA (BIT(4)) -#define GDMA_OUT_EOF_CH2_INT_ENA_M (BIT(4)) -#define GDMA_OUT_EOF_CH2_INT_ENA_V 0x1 -#define GDMA_OUT_EOF_CH2_INT_ENA_S 4 -/* GDMA_OUT_DONE_CH2_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH2_INT_ENA (BIT(3)) -#define GDMA_OUT_DONE_CH2_INT_ENA_M (BIT(3)) -#define GDMA_OUT_DONE_CH2_INT_ENA_V 0x1 -#define GDMA_OUT_DONE_CH2_INT_ENA_S 3 -/* GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) -#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x1 -#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2 -/* GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) -#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V 0x1 -#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S 1 -/* GDMA_IN_DONE_CH2_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH2_INT_ENA (BIT(0)) -#define GDMA_IN_DONE_CH2_INT_ENA_M (BIT(0)) -#define GDMA_IN_DONE_CH2_INT_ENA_V 0x1 -#define GDMA_IN_DONE_CH2_INT_ENA_S 0 +#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0xD4) +/* GDMA_INFIFO_UDF_L3_CH1_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_S 9 +/* GDMA_INFIFO_OVF_L3_CH1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH1_INT_CLR_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH1_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH1_INT_CLR_S 8 +/* GDMA_INFIFO_UDF_L1_CH1_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH1_INT_CLR (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH1_INT_CLR_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH1_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH1_INT_CLR_S 7 +/* GDMA_INFIFO_OVF_L1_CH1_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_S 6 +/* GDMA_DMA_INFIFO_FULL_WM_CH1_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_DMA_INFIFO_FULL_WM_CH1_INT_CLR (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH1_INT_CLR_M (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH1_INT_CLR_V 0x1 +#define GDMA_DMA_INFIFO_FULL_WM_CH1_INT_CLR_S 5 +/* GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/* GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/* GDMA_IN_ERR_EOF_CH1_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x1 +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/* GDMA_IN_SUC_EOF_CH1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x1 +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/* GDMA_IN_DONE_CH1_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_M (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_V 0x1 +#define GDMA_IN_DONE_CH1_INT_CLR_S 0 -#define GDMA_INT_ENA_CH3_REG (DR_REG_GDMA_BASE + 0x060) -/* GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA_S 14 -/* GDMA_INFIFO_UDF_L3_CH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH3_INT_ENA (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH3_INT_ENA_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH3_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH3_INT_ENA_S 13 -/* GDMA_INFIFO_OVF_L3_CH3_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH3_INT_ENA (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH3_INT_ENA_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH3_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH3_INT_ENA_S 12 -/* GDMA_INFIFO_UDF_L1_CH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH3_INT_ENA (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH3_INT_ENA_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH3_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH3_INT_ENA_S 11 -/* GDMA_INFIFO_OVF_L1_CH3_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH3_INT_ENA (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH3_INT_ENA_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH3_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH3_INT_ENA_S 10 -/* GDMA_INFIFO_FULL_WM_CH3_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH3_INT_ENA (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH3_INT_ENA_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH3_INT_ENA_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH3_INT_ENA_S 9 -/* GDMA_OUT_TOTAL_EOF_CH3_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH3_INT_ENA_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH3_INT_ENA_S 8 -/* GDMA_IN_DSCR_EMPTY_CH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH3_INT_ENA (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH3_INT_ENA_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH3_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH3_INT_ENA_S 7 -/* GDMA_OUT_DSCR_ERR_CH3_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH3_INT_ENA (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH3_INT_ENA_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH3_INT_ENA_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH3_INT_ENA_S 6 -/* GDMA_IN_DSCR_ERR_CH3_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH3_INT_ENA (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH3_INT_ENA_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH3_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_ERR_CH3_INT_ENA_S 5 -/* GDMA_OUT_EOF_CH3_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH3_INT_ENA (BIT(4)) -#define GDMA_OUT_EOF_CH3_INT_ENA_M (BIT(4)) -#define GDMA_OUT_EOF_CH3_INT_ENA_V 0x1 -#define GDMA_OUT_EOF_CH3_INT_ENA_S 4 -/* GDMA_OUT_DONE_CH3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH3_INT_ENA (BIT(3)) -#define GDMA_OUT_DONE_CH3_INT_ENA_M (BIT(3)) -#define GDMA_OUT_DONE_CH3_INT_ENA_V 0x1 -#define GDMA_OUT_DONE_CH3_INT_ENA_S 3 -/* GDMA_IN_ERR_EOF_CH3_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH3_INT_ENA (BIT(2)) -#define GDMA_IN_ERR_EOF_CH3_INT_ENA_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH3_INT_ENA_V 0x1 -#define GDMA_IN_ERR_EOF_CH3_INT_ENA_S 2 -/* GDMA_IN_SUC_EOF_CH3_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH3_INT_ENA (BIT(1)) -#define GDMA_IN_SUC_EOF_CH3_INT_ENA_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH3_INT_ENA_V 0x1 -#define GDMA_IN_SUC_EOF_CH3_INT_ENA_S 1 -/* GDMA_IN_DONE_CH3_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH3_INT_ENA (BIT(0)) -#define GDMA_IN_DONE_CH3_INT_ENA_M (BIT(0)) -#define GDMA_IN_DONE_CH3_INT_ENA_V 0x1 -#define GDMA_IN_DONE_CH3_INT_ENA_S 0 - -#define GDMA_INT_ENA_CH4_REG (DR_REG_GDMA_BASE + 0x064) -/* GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA_S 14 -/* GDMA_INFIFO_UDF_L3_CH4_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH4_INT_ENA (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH4_INT_ENA_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH4_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH4_INT_ENA_S 13 -/* GDMA_INFIFO_OVF_L3_CH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH4_INT_ENA (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH4_INT_ENA_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH4_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH4_INT_ENA_S 12 -/* GDMA_INFIFO_UDF_L1_CH4_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH4_INT_ENA (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH4_INT_ENA_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH4_INT_ENA_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH4_INT_ENA_S 11 -/* GDMA_INFIFO_OVF_L1_CH4_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH4_INT_ENA (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH4_INT_ENA_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH4_INT_ENA_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH4_INT_ENA_S 10 -/* GDMA_INFIFO_FULL_WM_CH4_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH4_INT_ENA (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH4_INT_ENA_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH4_INT_ENA_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH4_INT_ENA_S 9 -/* GDMA_OUT_TOTAL_EOF_CH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH4_INT_ENA (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH4_INT_ENA_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH4_INT_ENA_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH4_INT_ENA_S 8 -/* GDMA_IN_DSCR_EMPTY_CH4_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH4_INT_ENA (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH4_INT_ENA_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH4_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH4_INT_ENA_S 7 -/* GDMA_OUT_DSCR_ERR_CH4_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH4_INT_ENA (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH4_INT_ENA_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH4_INT_ENA_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH4_INT_ENA_S 6 -/* GDMA_IN_DSCR_ERR_CH4_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH4_INT_ENA (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH4_INT_ENA_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH4_INT_ENA_V 0x1 -#define GDMA_IN_DSCR_ERR_CH4_INT_ENA_S 5 -/* GDMA_OUT_EOF_CH4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH4_INT_ENA (BIT(4)) -#define GDMA_OUT_EOF_CH4_INT_ENA_M (BIT(4)) -#define GDMA_OUT_EOF_CH4_INT_ENA_V 0x1 -#define GDMA_OUT_EOF_CH4_INT_ENA_S 4 -/* GDMA_OUT_DONE_CH4_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH4_INT_ENA (BIT(3)) -#define GDMA_OUT_DONE_CH4_INT_ENA_M (BIT(3)) -#define GDMA_OUT_DONE_CH4_INT_ENA_V 0x1 -#define GDMA_OUT_DONE_CH4_INT_ENA_S 3 -/* GDMA_IN_ERR_EOF_CH4_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH4_INT_ENA (BIT(2)) -#define GDMA_IN_ERR_EOF_CH4_INT_ENA_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH4_INT_ENA_V 0x1 -#define GDMA_IN_ERR_EOF_CH4_INT_ENA_S 2 -/* GDMA_IN_SUC_EOF_CH4_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH4_INT_ENA (BIT(1)) -#define GDMA_IN_SUC_EOF_CH4_INT_ENA_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH4_INT_ENA_V 0x1 -#define GDMA_IN_SUC_EOF_CH4_INT_ENA_S 1 -/* GDMA_IN_DONE_CH4_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH4_INT_ENA (BIT(0)) -#define GDMA_IN_DONE_CH4_INT_ENA_M (BIT(0)) -#define GDMA_IN_DONE_CH4_INT_ENA_V 0x1 -#define GDMA_IN_DONE_CH4_INT_ENA_S 0 - -#define GDMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x068) -/* GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH0_INT_CLR_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH0_INT_CLR_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH0_INT_CLR_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S 14 -/* GDMA_INFIFO_UDF_L3_CH0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH0_INT_CLR_S 13 -/* GDMA_INFIFO_OVF_L3_CH0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH0_INT_CLR (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH0_INT_CLR_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH0_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH0_INT_CLR_S 12 -/* GDMA_INFIFO_UDF_L1_CH0_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH0_INT_CLR (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH0_INT_CLR_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH0_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH0_INT_CLR_S 11 -/* GDMA_INFIFO_OVF_L1_CH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH0_INT_CLR_S 10 -/* GDMA_INFIFO_FULL_WM_CH0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH0_INT_CLR (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH0_INT_CLR_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH0_INT_CLR_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH0_INT_CLR_S 9 -/* GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8 -/* GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7 -/* GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6 -/* GDMA_IN_DSCR_ERR_CH0_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 5 -/* GDMA_OUT_EOF_CH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(4)) -#define GDMA_OUT_EOF_CH0_INT_CLR_M (BIT(4)) -#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x1 -#define GDMA_OUT_EOF_CH0_INT_CLR_S 4 -/* GDMA_OUT_DONE_CH0_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(3)) -#define GDMA_OUT_DONE_CH0_INT_CLR_M (BIT(3)) -#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x1 -#define GDMA_OUT_DONE_CH0_INT_CLR_S 3 -/* GDMA_IN_ERR_EOF_CH0_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) -#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x1 -#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 -/* GDMA_IN_SUC_EOF_CH0_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) -#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x1 -#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 -/* GDMA_IN_DONE_CH0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) -#define GDMA_IN_DONE_CH0_INT_CLR_M (BIT(0)) -#define GDMA_IN_DONE_CH0_INT_CLR_V 0x1 -#define GDMA_IN_DONE_CH0_INT_CLR_S 0 - -#define GDMA_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x06C) -/* GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S 14 -/* GDMA_INFIFO_UDF_L3_CH1_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH1_INT_CLR_S 13 -/* GDMA_INFIFO_OVF_L3_CH1_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH1_INT_CLR (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH1_INT_CLR_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH1_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH1_INT_CLR_S 12 -/* GDMA_INFIFO_UDF_L1_CH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH1_INT_CLR (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH1_INT_CLR_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH1_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH1_INT_CLR_S 11 -/* GDMA_INFIFO_OVF_L1_CH1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH1_INT_CLR_S 10 -/* GDMA_INFIFO_FULL_WM_CH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH1_INT_CLR (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH1_INT_CLR_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH1_INT_CLR_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH1_INT_CLR_S 9 -/* GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 8 -/* GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 7 -/* GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 6 -/* GDMA_IN_DSCR_ERR_CH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 5 -/* GDMA_OUT_EOF_CH1_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(4)) -#define GDMA_OUT_EOF_CH1_INT_CLR_M (BIT(4)) -#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x1 -#define GDMA_OUT_EOF_CH1_INT_CLR_S 4 -/* GDMA_OUT_DONE_CH1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(3)) -#define GDMA_OUT_DONE_CH1_INT_CLR_M (BIT(3)) -#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x1 -#define GDMA_OUT_DONE_CH1_INT_CLR_S 3 -/* GDMA_IN_ERR_EOF_CH1_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) -#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x1 -#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 -/* GDMA_IN_SUC_EOF_CH1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) -#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x1 -#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 -/* GDMA_IN_DONE_CH1_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) -#define GDMA_IN_DONE_CH1_INT_CLR_M (BIT(0)) -#define GDMA_IN_DONE_CH1_INT_CLR_V 0x1 -#define GDMA_IN_DONE_CH1_INT_CLR_S 0 - -#define GDMA_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x070) -/* GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S 14 -/* GDMA_INFIFO_UDF_L3_CH2_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_S 13 -/* GDMA_INFIFO_OVF_L3_CH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH2_INT_CLR (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH2_INT_CLR_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH2_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH2_INT_CLR_S 12 -/* GDMA_INFIFO_UDF_L1_CH2_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH2_INT_CLR (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH2_INT_CLR_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH2_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH2_INT_CLR_S 11 -/* GDMA_INFIFO_OVF_L1_CH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_S 10 -/* GDMA_INFIFO_FULL_WM_CH2_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH2_INT_CLR (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH2_INT_CLR_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH2_INT_CLR_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH2_INT_CLR_S 9 -/* GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 8 -/* GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 7 -/* GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S 6 -/* GDMA_IN_DSCR_ERR_CH2_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 5 -/* GDMA_OUT_EOF_CH2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(4)) -#define GDMA_OUT_EOF_CH2_INT_CLR_M (BIT(4)) -#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x1 -#define GDMA_OUT_EOF_CH2_INT_CLR_S 4 -/* GDMA_OUT_DONE_CH2_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH2_INT_CLR (BIT(3)) -#define GDMA_OUT_DONE_CH2_INT_CLR_M (BIT(3)) -#define GDMA_OUT_DONE_CH2_INT_CLR_V 0x1 -#define GDMA_OUT_DONE_CH2_INT_CLR_S 3 -/* GDMA_IN_ERR_EOF_CH2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) -#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V 0x1 -#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S 2 -/* GDMA_IN_SUC_EOF_CH2_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) -#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V 0x1 -#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S 1 -/* GDMA_IN_DONE_CH2_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH2_INT_CLR (BIT(0)) -#define GDMA_IN_DONE_CH2_INT_CLR_M (BIT(0)) -#define GDMA_IN_DONE_CH2_INT_CLR_V 0x1 -#define GDMA_IN_DONE_CH2_INT_CLR_S 0 - -#define GDMA_INT_CLR_CH3_REG (DR_REG_GDMA_BASE + 0x074) -/* GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR_S 14 -/* GDMA_INFIFO_UDF_L3_CH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH3_INT_CLR (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH3_INT_CLR_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH3_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH3_INT_CLR_S 13 -/* GDMA_INFIFO_OVF_L3_CH3_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH3_INT_CLR (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH3_INT_CLR_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH3_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH3_INT_CLR_S 12 -/* GDMA_INFIFO_UDF_L1_CH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH3_INT_CLR (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH3_INT_CLR_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH3_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH3_INT_CLR_S 11 -/* GDMA_INFIFO_OVF_L1_CH3_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH3_INT_CLR (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH3_INT_CLR_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH3_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH3_INT_CLR_S 10 -/* GDMA_INFIFO_FULL_WM_CH3_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH3_INT_CLR (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH3_INT_CLR_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH3_INT_CLR_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH3_INT_CLR_S 9 -/* GDMA_OUT_TOTAL_EOF_CH3_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH3_INT_CLR_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH3_INT_CLR_S 8 -/* GDMA_IN_DSCR_EMPTY_CH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH3_INT_CLR (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH3_INT_CLR_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH3_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH3_INT_CLR_S 7 -/* GDMA_OUT_DSCR_ERR_CH3_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH3_INT_CLR (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH3_INT_CLR_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH3_INT_CLR_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH3_INT_CLR_S 6 -/* GDMA_IN_DSCR_ERR_CH3_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH3_INT_CLR (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH3_INT_CLR_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH3_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_ERR_CH3_INT_CLR_S 5 -/* GDMA_OUT_EOF_CH3_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH3_INT_CLR (BIT(4)) -#define GDMA_OUT_EOF_CH3_INT_CLR_M (BIT(4)) -#define GDMA_OUT_EOF_CH3_INT_CLR_V 0x1 -#define GDMA_OUT_EOF_CH3_INT_CLR_S 4 -/* GDMA_OUT_DONE_CH3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH3_INT_CLR (BIT(3)) -#define GDMA_OUT_DONE_CH3_INT_CLR_M (BIT(3)) -#define GDMA_OUT_DONE_CH3_INT_CLR_V 0x1 -#define GDMA_OUT_DONE_CH3_INT_CLR_S 3 -/* GDMA_IN_ERR_EOF_CH3_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH3_INT_CLR (BIT(2)) -#define GDMA_IN_ERR_EOF_CH3_INT_CLR_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH3_INT_CLR_V 0x1 -#define GDMA_IN_ERR_EOF_CH3_INT_CLR_S 2 -/* GDMA_IN_SUC_EOF_CH3_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH3_INT_CLR (BIT(1)) -#define GDMA_IN_SUC_EOF_CH3_INT_CLR_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH3_INT_CLR_V 0x1 -#define GDMA_IN_SUC_EOF_CH3_INT_CLR_S 1 -/* GDMA_IN_DONE_CH3_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH3_INT_CLR (BIT(0)) -#define GDMA_IN_DONE_CH3_INT_CLR_M (BIT(0)) -#define GDMA_IN_DONE_CH3_INT_CLR_V 0x1 -#define GDMA_IN_DONE_CH3_INT_CLR_S 0 - -#define GDMA_INT_CLR_CH4_REG (DR_REG_GDMA_BASE + 0x078) -/* GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR_M (BIT(17)) -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR_S 17 -/* GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR_M (BIT(16)) -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR_S 16 -/* GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR_M (BIT(15)) -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR_S 15 -/* GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR_M (BIT(14)) -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR_V 0x1 -#define GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR_S 14 -/* GDMA_INFIFO_UDF_L3_CH4_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L3_CH4_INT_CLR (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH4_INT_CLR_M (BIT(13)) -#define GDMA_INFIFO_UDF_L3_CH4_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L3_CH4_INT_CLR_S 13 -/* GDMA_INFIFO_OVF_L3_CH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L3_CH4_INT_CLR (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH4_INT_CLR_M (BIT(12)) -#define GDMA_INFIFO_OVF_L3_CH4_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L3_CH4_INT_CLR_S 12 -/* GDMA_INFIFO_UDF_L1_CH4_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_UDF_L1_CH4_INT_CLR (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH4_INT_CLR_M (BIT(11)) -#define GDMA_INFIFO_UDF_L1_CH4_INT_CLR_V 0x1 -#define GDMA_INFIFO_UDF_L1_CH4_INT_CLR_S 11 -/* GDMA_INFIFO_OVF_L1_CH4_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define GDMA_INFIFO_OVF_L1_CH4_INT_CLR (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH4_INT_CLR_M (BIT(10)) -#define GDMA_INFIFO_OVF_L1_CH4_INT_CLR_V 0x1 -#define GDMA_INFIFO_OVF_L1_CH4_INT_CLR_S 10 -/* GDMA_INFIFO_FULL_WM_CH4_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ -#define GDMA_INFIFO_FULL_WM_CH4_INT_CLR (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH4_INT_CLR_M (BIT(9)) -#define GDMA_INFIFO_FULL_WM_CH4_INT_CLR_V 0x1 -#define GDMA_INFIFO_FULL_WM_CH4_INT_CLR_S 9 -/* GDMA_OUT_TOTAL_EOF_CH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_TOTAL_EOF_CH4_INT_CLR (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH4_INT_CLR_M (BIT(8)) -#define GDMA_OUT_TOTAL_EOF_CH4_INT_CLR_V 0x1 -#define GDMA_OUT_TOTAL_EOF_CH4_INT_CLR_S 8 -/* GDMA_IN_DSCR_EMPTY_CH4_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_EMPTY_CH4_INT_CLR (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH4_INT_CLR_M (BIT(7)) -#define GDMA_IN_DSCR_EMPTY_CH4_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_EMPTY_CH4_INT_CLR_S 7 -/* GDMA_OUT_DSCR_ERR_CH4_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_OUT_DSCR_ERR_CH4_INT_CLR (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH4_INT_CLR_M (BIT(6)) -#define GDMA_OUT_DSCR_ERR_CH4_INT_CLR_V 0x1 -#define GDMA_OUT_DSCR_ERR_CH4_INT_CLR_S 6 -/* GDMA_IN_DSCR_ERR_CH4_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ -#define GDMA_IN_DSCR_ERR_CH4_INT_CLR (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH4_INT_CLR_M (BIT(5)) -#define GDMA_IN_DSCR_ERR_CH4_INT_CLR_V 0x1 -#define GDMA_IN_DSCR_ERR_CH4_INT_CLR_S 5 -/* GDMA_OUT_EOF_CH4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ -#define GDMA_OUT_EOF_CH4_INT_CLR (BIT(4)) -#define GDMA_OUT_EOF_CH4_INT_CLR_M (BIT(4)) -#define GDMA_OUT_EOF_CH4_INT_CLR_V 0x1 -#define GDMA_OUT_EOF_CH4_INT_CLR_S 4 -/* GDMA_OUT_DONE_CH4_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ -#define GDMA_OUT_DONE_CH4_INT_CLR (BIT(3)) -#define GDMA_OUT_DONE_CH4_INT_CLR_M (BIT(3)) -#define GDMA_OUT_DONE_CH4_INT_CLR_V 0x1 -#define GDMA_OUT_DONE_CH4_INT_CLR_S 3 -/* GDMA_IN_ERR_EOF_CH4_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ -#define GDMA_IN_ERR_EOF_CH4_INT_CLR (BIT(2)) -#define GDMA_IN_ERR_EOF_CH4_INT_CLR_M (BIT(2)) -#define GDMA_IN_ERR_EOF_CH4_INT_CLR_V 0x1 -#define GDMA_IN_ERR_EOF_CH4_INT_CLR_S 2 -/* GDMA_IN_SUC_EOF_CH4_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ -#define GDMA_IN_SUC_EOF_CH4_INT_CLR (BIT(1)) -#define GDMA_IN_SUC_EOF_CH4_INT_CLR_M (BIT(1)) -#define GDMA_IN_SUC_EOF_CH4_INT_CLR_V 0x1 -#define GDMA_IN_SUC_EOF_CH4_INT_CLR_S 1 -/* GDMA_IN_DONE_CH4_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ -#define GDMA_IN_DONE_CH4_INT_CLR (BIT(0)) -#define GDMA_IN_DONE_CH4_INT_CLR_M (BIT(0)) -#define GDMA_IN_DONE_CH4_INT_CLR_V 0x1 -#define GDMA_IN_DONE_CH4_INT_CLR_S 0 - -#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x07C) -/* GDMA_IN_BUF_HUNGRY_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH0_M (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH0_V 0x1 -#define GDMA_IN_BUF_HUNGRY_CH0_S 27 -/* GDMA_IN_REMAIN_UNDER_4B_L3_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0 (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0_M (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0_V 0x1 -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH0_S 26 -/* GDMA_IN_REMAIN_UNDER_3B_L3_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH0 (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH0_M (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH0_V 0x1 -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH0_S 25 -/* GDMA_IN_REMAIN_UNDER_2B_L3_CH0 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH0 (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH0_M (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH0_V 0x1 -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH0_S 24 -/* GDMA_IN_REMAIN_UNDER_1B_L3_CH0 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0 (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_M (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_V 0x1 -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH0_S 23 -/* GDMA_INFIFO_CNT_L3_CH0 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/ -#define GDMA_INFIFO_CNT_L3_CH0 0x0000001F -#define GDMA_INFIFO_CNT_L3_CH0_M ((GDMA_INFIFO_CNT_L3_CH0_V) << (GDMA_INFIFO_CNT_L3_CH0_S)) -#define GDMA_INFIFO_CNT_L3_CH0_V 0x1F -#define GDMA_INFIFO_CNT_L3_CH0_S 18 -/* GDMA_INFIFO_CNT_L2_CH0 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/ -#define GDMA_INFIFO_CNT_L2_CH0 0x0000007F -#define GDMA_INFIFO_CNT_L2_CH0_M ((GDMA_INFIFO_CNT_L2_CH0_V) << (GDMA_INFIFO_CNT_L2_CH0_S)) -#define GDMA_INFIFO_CNT_L2_CH0_V 0x7F -#define GDMA_INFIFO_CNT_L2_CH0_S 11 -/* GDMA_INFIFO_CNT_L1_CH0 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ -#define GDMA_INFIFO_CNT_L1_CH0 0x0000001F -#define GDMA_INFIFO_CNT_L1_CH0_M ((GDMA_INFIFO_CNT_L1_CH0_V) << (GDMA_INFIFO_CNT_L1_CH0_S)) -#define GDMA_INFIFO_CNT_L1_CH0_V 0x1F -#define GDMA_INFIFO_CNT_L1_CH0_S 6 -/* GDMA_INFIFO_EMPTY_L3_CH0 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Rx FIFO empty signal for Rx channel 0.*/ -#define GDMA_INFIFO_EMPTY_L3_CH0 (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH0_M (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH0_V 0x1 -#define GDMA_INFIFO_EMPTY_L3_CH0_S 5 -/* GDMA_INFIFO_FULL_L3_CH0 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Rx FIFO full signal for Rx channel 0.*/ -#define GDMA_INFIFO_FULL_L3_CH0 (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH0_M (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH0_V 0x1 -#define GDMA_INFIFO_FULL_L3_CH0_S 4 -/* GDMA_INFIFO_EMPTY_L2_CH0 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Rx FIFO empty signal for Rx channel 0.*/ -#define GDMA_INFIFO_EMPTY_L2_CH0 (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH0_M (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH0_V 0x1 -#define GDMA_INFIFO_EMPTY_L2_CH0_S 3 -/* GDMA_INFIFO_FULL_L2_CH0 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Rx FIFO full signal for Rx channel 0.*/ -#define GDMA_INFIFO_FULL_L2_CH0 (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH0_M (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH0_V 0x1 -#define GDMA_INFIFO_FULL_L2_CH0_S 2 -/* GDMA_INFIFO_EMPTY_L1_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO empty signal for Rx channel 0.*/ -#define GDMA_INFIFO_EMPTY_L1_CH0 (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH0_M (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH0_V 0x1 -#define GDMA_INFIFO_EMPTY_L1_CH0_S 1 -/* GDMA_INFIFO_FULL_L1_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Rx FIFO full signal for Rx channel 0.*/ -#define GDMA_INFIFO_FULL_L1_CH0 (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH0_M (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH0_V 0x1 -#define GDMA_INFIFO_FULL_L1_CH0_S 0 - -#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x080) -/* GDMA_IN_BUF_HUNGRY_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH1_M (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH1_V 0x1 -#define GDMA_IN_BUF_HUNGRY_CH1_S 27 -/* GDMA_IN_REMAIN_UNDER_4B_L3_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1 (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1_M (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1_V 0x1 -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1_S 26 -/* GDMA_IN_REMAIN_UNDER_3B_L3_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH1 (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH1_M (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH1_V 0x1 -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH1_S 25 -/* GDMA_IN_REMAIN_UNDER_2B_L3_CH1 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH1 (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH1_M (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH1_V 0x1 -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH1_S 24 -/* GDMA_IN_REMAIN_UNDER_1B_L3_CH1 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1 (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_M (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_V 0x1 -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_S 23 -/* GDMA_INFIFO_CNT_L3_CH1 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 1.*/ -#define GDMA_INFIFO_CNT_L3_CH1 0x0000001F -#define GDMA_INFIFO_CNT_L3_CH1_M ((GDMA_INFIFO_CNT_L3_CH1_V) << (GDMA_INFIFO_CNT_L3_CH1_S)) -#define GDMA_INFIFO_CNT_L3_CH1_V 0x1F -#define GDMA_INFIFO_CNT_L3_CH1_S 18 -/* GDMA_INFIFO_CNT_L2_CH1 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 1.*/ -#define GDMA_INFIFO_CNT_L2_CH1 0x0000007F -#define GDMA_INFIFO_CNT_L2_CH1_M ((GDMA_INFIFO_CNT_L2_CH1_V) << (GDMA_INFIFO_CNT_L2_CH1_S)) -#define GDMA_INFIFO_CNT_L2_CH1_V 0x7F -#define GDMA_INFIFO_CNT_L2_CH1_S 11 -/* GDMA_INFIFO_CNT_L1_CH1 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.*/ -#define GDMA_INFIFO_CNT_L1_CH1 0x0000001F -#define GDMA_INFIFO_CNT_L1_CH1_M ((GDMA_INFIFO_CNT_L1_CH1_V) << (GDMA_INFIFO_CNT_L1_CH1_S)) -#define GDMA_INFIFO_CNT_L1_CH1_V 0x1F -#define GDMA_INFIFO_CNT_L1_CH1_S 6 +#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0xD8) +/* GDMA_IN_BUF_HUNGRY_CH1 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH1_M (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH1_V 0x1 +#define GDMA_IN_BUF_HUNGRY_CH1_S 28 +/* GDMA_IN_REMAIN_UNDER_4B_L3_CH1 : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1 (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1_M (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1_V 0x1 +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH1_S 27 +/* GDMA_IN_REMAIN_UNDER_3B_L3_CH1 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH1 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH1_M (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH1_V 0x1 +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH1_S 26 +/* GDMA_IN_REMAIN_UNDER_2B_L3_CH1 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH1 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH1_M (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH1_V 0x1 +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH1_S 25 +/* GDMA_IN_REMAIN_UNDER_1B_L3_CH1 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_M (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_V 0x1 +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH1_S 24 +/* GDMA_INFIFO_CNT_L3_CH1 : RO ;bitpos:[23:19] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 1..*/ +#define GDMA_INFIFO_CNT_L3_CH1 0x0000001F +#define GDMA_INFIFO_CNT_L3_CH1_M ((GDMA_INFIFO_CNT_L3_CH1_V)<<(GDMA_INFIFO_CNT_L3_CH1_S)) +#define GDMA_INFIFO_CNT_L3_CH1_V 0x1F +#define GDMA_INFIFO_CNT_L3_CH1_S 19 +/* GDMA_INFIFO_CNT_L2_CH1 : RO ;bitpos:[18:12] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 1..*/ +#define GDMA_INFIFO_CNT_L2_CH1 0x0000007F +#define GDMA_INFIFO_CNT_L2_CH1_M ((GDMA_INFIFO_CNT_L2_CH1_V)<<(GDMA_INFIFO_CNT_L2_CH1_S)) +#define GDMA_INFIFO_CNT_L2_CH1_V 0x7F +#define GDMA_INFIFO_CNT_L2_CH1_S 12 +/* GDMA_INFIFO_CNT_L1_CH1 : RO ;bitpos:[11:6] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1..*/ +#define GDMA_INFIFO_CNT_L1_CH1 0x0000003F +#define GDMA_INFIFO_CNT_L1_CH1_M ((GDMA_INFIFO_CNT_L1_CH1_V)<<(GDMA_INFIFO_CNT_L1_CH1_S)) +#define GDMA_INFIFO_CNT_L1_CH1_V 0x3F +#define GDMA_INFIFO_CNT_L1_CH1_S 6 /* GDMA_INFIFO_EMPTY_L3_CH1 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Rx FIFO empty signal for Rx channel 1.*/ -#define GDMA_INFIFO_EMPTY_L3_CH1 (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH1_M (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH1_V 0x1 -#define GDMA_INFIFO_EMPTY_L3_CH1_S 5 -/* GDMA_INFIFO_FULL_L3_CH1 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Rx FIFO full signal for Rx channel 1.*/ -#define GDMA_INFIFO_FULL_L3_CH1 (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH1_M (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH1_V 0x1 -#define GDMA_INFIFO_FULL_L3_CH1_S 4 +/*description: L3 Rx FIFO empty signal for Rx channel 1..*/ +#define GDMA_INFIFO_EMPTY_L3_CH1 (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH1_M (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH1_V 0x1 +#define GDMA_INFIFO_EMPTY_L3_CH1_S 5 +/* GDMA_INFIFO_FULL_L3_CH1 : RO ;bitpos:[4] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 1..*/ +#define GDMA_INFIFO_FULL_L3_CH1 (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH1_M (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH1_V 0x1 +#define GDMA_INFIFO_FULL_L3_CH1_S 4 /* GDMA_INFIFO_EMPTY_L2_CH1 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Rx FIFO empty signal for Rx channel 1.*/ -#define GDMA_INFIFO_EMPTY_L2_CH1 (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH1_M (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH1_V 0x1 -#define GDMA_INFIFO_EMPTY_L2_CH1_S 3 +/*description: L2 Rx FIFO empty signal for Rx channel 1..*/ +#define GDMA_INFIFO_EMPTY_L2_CH1 (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH1_M (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH1_V 0x1 +#define GDMA_INFIFO_EMPTY_L2_CH1_S 3 /* GDMA_INFIFO_FULL_L2_CH1 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Rx FIFO full signal for Rx channel 1.*/ -#define GDMA_INFIFO_FULL_L2_CH1 (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH1_M (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH1_V 0x1 -#define GDMA_INFIFO_FULL_L2_CH1_S 2 +/*description: L2 Rx FIFO full signal for Rx channel 1..*/ +#define GDMA_INFIFO_FULL_L2_CH1 (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH1_M (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH1_V 0x1 +#define GDMA_INFIFO_FULL_L2_CH1_S 2 /* GDMA_INFIFO_EMPTY_L1_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO empty signal for Rx channel 1.*/ -#define GDMA_INFIFO_EMPTY_L1_CH1 (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH1_M (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH1_V 0x1 -#define GDMA_INFIFO_EMPTY_L1_CH1_S 1 +/*description: L1 Rx FIFO empty signal for Rx channel 1..*/ +#define GDMA_INFIFO_EMPTY_L1_CH1 (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH1_M (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH1_V 0x1 +#define GDMA_INFIFO_EMPTY_L1_CH1_S 1 /* GDMA_INFIFO_FULL_L1_CH1 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Rx FIFO full signal for Rx channel 1.*/ -#define GDMA_INFIFO_FULL_L1_CH1 (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH1_M (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH1_V 0x1 -#define GDMA_INFIFO_FULL_L1_CH1_S 0 +/*description: L1 Rx FIFO full signal for Rx channel 1..*/ +#define GDMA_INFIFO_FULL_L1_CH1 (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH1_M (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH1_V 0x1 +#define GDMA_INFIFO_FULL_L1_CH1_S 0 -#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x084) -/* GDMA_IN_BUF_HUNGRY_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH2_M (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH2_V 0x1 -#define GDMA_IN_BUF_HUNGRY_CH2_S 27 -/* GDMA_IN_REMAIN_UNDER_4B_L3_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2 (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2_M (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2_V 0x1 -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2_S 26 -/* GDMA_IN_REMAIN_UNDER_3B_L3_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH2 (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH2_M (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH2_V 0x1 -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH2_S 25 -/* GDMA_IN_REMAIN_UNDER_2B_L3_CH2 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH2 (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH2_M (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH2_V 0x1 -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH2_S 24 -/* GDMA_IN_REMAIN_UNDER_1B_L3_CH2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2 (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_M (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_V 0x1 -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_S 23 -/* GDMA_INFIFO_CNT_L3_CH2 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 2.*/ -#define GDMA_INFIFO_CNT_L3_CH2 0x0000001F -#define GDMA_INFIFO_CNT_L3_CH2_M ((GDMA_INFIFO_CNT_L3_CH2_V) << (GDMA_INFIFO_CNT_L3_CH2_S)) -#define GDMA_INFIFO_CNT_L3_CH2_V 0x1F -#define GDMA_INFIFO_CNT_L3_CH2_S 18 -/* GDMA_INFIFO_CNT_L2_CH2 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 2.*/ -#define GDMA_INFIFO_CNT_L2_CH2 0x0000007F -#define GDMA_INFIFO_CNT_L2_CH2_M ((GDMA_INFIFO_CNT_L2_CH2_V) << (GDMA_INFIFO_CNT_L2_CH2_S)) -#define GDMA_INFIFO_CNT_L2_CH2_V 0x7F -#define GDMA_INFIFO_CNT_L2_CH2_S 11 -/* GDMA_INFIFO_CNT_L1_CH2 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.*/ -#define GDMA_INFIFO_CNT_L1_CH2 0x0000001F -#define GDMA_INFIFO_CNT_L1_CH2_M ((GDMA_INFIFO_CNT_L1_CH2_V) << (GDMA_INFIFO_CNT_L1_CH2_S)) -#define GDMA_INFIFO_CNT_L1_CH2_V 0x1F -#define GDMA_INFIFO_CNT_L1_CH2_S 6 -/* GDMA_INFIFO_EMPTY_L3_CH2 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Rx FIFO empty signal for Rx channel 2.*/ -#define GDMA_INFIFO_EMPTY_L3_CH2 (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH2_M (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH2_V 0x1 -#define GDMA_INFIFO_EMPTY_L3_CH2_S 5 -/* GDMA_INFIFO_FULL_L3_CH2 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Rx FIFO full signal for Rx channel 2.*/ -#define GDMA_INFIFO_FULL_L3_CH2 (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH2_M (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH2_V 0x1 -#define GDMA_INFIFO_FULL_L3_CH2_S 4 -/* GDMA_INFIFO_EMPTY_L2_CH2 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Rx FIFO empty signal for Rx channel 2.*/ -#define GDMA_INFIFO_EMPTY_L2_CH2 (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH2_M (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH2_V 0x1 -#define GDMA_INFIFO_EMPTY_L2_CH2_S 3 -/* GDMA_INFIFO_FULL_L2_CH2 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Rx FIFO full signal for Rx channel 2.*/ -#define GDMA_INFIFO_FULL_L2_CH2 (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH2_M (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH2_V 0x1 -#define GDMA_INFIFO_FULL_L2_CH2_S 2 -/* GDMA_INFIFO_EMPTY_L1_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO empty signal for Rx channel 2.*/ -#define GDMA_INFIFO_EMPTY_L1_CH2 (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH2_M (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH2_V 0x1 -#define GDMA_INFIFO_EMPTY_L1_CH2_S 1 -/* GDMA_INFIFO_FULL_L1_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Rx FIFO full signal for Rx channel 2.*/ -#define GDMA_INFIFO_FULL_L1_CH2 (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH2_M (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH2_V 0x1 -#define GDMA_INFIFO_FULL_L1_CH2_S 0 +#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0xDC) +/* GDMA_INFIFO_POP_CH1 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO..*/ +#define GDMA_INFIFO_POP_CH1 (BIT(12)) +#define GDMA_INFIFO_POP_CH1_M (BIT(12)) +#define GDMA_INFIFO_POP_CH1_V 0x1 +#define GDMA_INFIFO_POP_CH1_S 12 +/* GDMA_INFIFO_RDATA_CH1 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: This register stores the data popping from DMA FIFO..*/ +#define GDMA_INFIFO_RDATA_CH1 0x00000FFF +#define GDMA_INFIFO_RDATA_CH1_M ((GDMA_INFIFO_RDATA_CH1_V)<<(GDMA_INFIFO_RDATA_CH1_S)) +#define GDMA_INFIFO_RDATA_CH1_V 0xFFF +#define GDMA_INFIFO_RDATA_CH1_S 0 -#define GDMA_INFIFO_STATUS_CH3_REG (DR_REG_GDMA_BASE + 0x088) -/* GDMA_IN_BUF_HUNGRY_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_BUF_HUNGRY_CH3 (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH3_M (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH3_V 0x1 -#define GDMA_IN_BUF_HUNGRY_CH3_S 27 -/* GDMA_IN_REMAIN_UNDER_4B_L3_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH3 (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH3_M (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH3_V 0x1 -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH3_S 26 -/* GDMA_IN_REMAIN_UNDER_3B_L3_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH3 (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH3_M (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH3_V 0x1 -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH3_S 25 -/* GDMA_IN_REMAIN_UNDER_2B_L3_CH3 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH3 (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH3_M (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH3_V 0x1 -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH3_S 24 -/* GDMA_IN_REMAIN_UNDER_1B_L3_CH3 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH3 (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH3_M (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH3_V 0x1 -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH3_S 23 -/* GDMA_INFIFO_CNT_L3_CH3 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 3.*/ -#define GDMA_INFIFO_CNT_L3_CH3 0x0000001F -#define GDMA_INFIFO_CNT_L3_CH3_M ((GDMA_INFIFO_CNT_L3_CH3_V) << (GDMA_INFIFO_CNT_L3_CH3_S)) -#define GDMA_INFIFO_CNT_L3_CH3_V 0x1F -#define GDMA_INFIFO_CNT_L3_CH3_S 18 -/* GDMA_INFIFO_CNT_L2_CH3 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 3.*/ -#define GDMA_INFIFO_CNT_L2_CH3 0x0000007F -#define GDMA_INFIFO_CNT_L2_CH3_M ((GDMA_INFIFO_CNT_L2_CH3_V) << (GDMA_INFIFO_CNT_L2_CH3_S)) -#define GDMA_INFIFO_CNT_L2_CH3_V 0x7F -#define GDMA_INFIFO_CNT_L2_CH3_S 11 -/* GDMA_INFIFO_CNT_L1_CH3 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 3.*/ -#define GDMA_INFIFO_CNT_L1_CH3 0x0000001F -#define GDMA_INFIFO_CNT_L1_CH3_M ((GDMA_INFIFO_CNT_L1_CH3_V) << (GDMA_INFIFO_CNT_L1_CH3_S)) -#define GDMA_INFIFO_CNT_L1_CH3_V 0x1F -#define GDMA_INFIFO_CNT_L1_CH3_S 6 -/* GDMA_INFIFO_EMPTY_L3_CH3 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Rx FIFO empty signal for Rx channel 3.*/ -#define GDMA_INFIFO_EMPTY_L3_CH3 (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH3_M (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH3_V 0x1 -#define GDMA_INFIFO_EMPTY_L3_CH3_S 5 -/* GDMA_INFIFO_FULL_L3_CH3 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Rx FIFO full signal for Rx channel 3.*/ -#define GDMA_INFIFO_FULL_L3_CH3 (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH3_M (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH3_V 0x1 -#define GDMA_INFIFO_FULL_L3_CH3_S 4 -/* GDMA_INFIFO_EMPTY_L2_CH3 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Rx FIFO empty signal for Rx channel 3.*/ -#define GDMA_INFIFO_EMPTY_L2_CH3 (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH3_M (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH3_V 0x1 -#define GDMA_INFIFO_EMPTY_L2_CH3_S 3 -/* GDMA_INFIFO_FULL_L2_CH3 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Rx FIFO full signal for Rx channel 3.*/ -#define GDMA_INFIFO_FULL_L2_CH3 (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH3_M (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH3_V 0x1 -#define GDMA_INFIFO_FULL_L2_CH3_S 2 -/* GDMA_INFIFO_EMPTY_L1_CH3 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO empty signal for Rx channel 3.*/ -#define GDMA_INFIFO_EMPTY_L1_CH3 (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH3_M (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH3_V 0x1 -#define GDMA_INFIFO_EMPTY_L1_CH3_S 1 -/* GDMA_INFIFO_FULL_L1_CH3 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Rx FIFO full signal for Rx channel 3.*/ -#define GDMA_INFIFO_FULL_L1_CH3 (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH3_M (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH3_V 0x1 -#define GDMA_INFIFO_FULL_L1_CH3_S 0 - -#define GDMA_INFIFO_STATUS_CH4_REG (DR_REG_GDMA_BASE + 0x08C) -/* GDMA_IN_BUF_HUNGRY_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_BUF_HUNGRY_CH4 (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH4_M (BIT(27)) -#define GDMA_IN_BUF_HUNGRY_CH4_V 0x1 -#define GDMA_IN_BUF_HUNGRY_CH4_S 27 -/* GDMA_IN_REMAIN_UNDER_4B_L3_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH4 (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH4_M (BIT(26)) -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH4_V 0x1 -#define GDMA_IN_REMAIN_UNDER_4B_L3_CH4_S 26 -/* GDMA_IN_REMAIN_UNDER_3B_L3_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH4 (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH4_M (BIT(25)) -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH4_V 0x1 -#define GDMA_IN_REMAIN_UNDER_3B_L3_CH4_S 25 -/* GDMA_IN_REMAIN_UNDER_2B_L3_CH4 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH4 (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH4_M (BIT(24)) -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH4_V 0x1 -#define GDMA_IN_REMAIN_UNDER_2B_L3_CH4_S 24 -/* GDMA_IN_REMAIN_UNDER_1B_L3_CH4 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH4 (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH4_M (BIT(23)) -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH4_V 0x1 -#define GDMA_IN_REMAIN_UNDER_1B_L3_CH4_S 23 -/* GDMA_INFIFO_CNT_L3_CH4 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 4.*/ -#define GDMA_INFIFO_CNT_L3_CH4 0x0000001F -#define GDMA_INFIFO_CNT_L3_CH4_M ((GDMA_INFIFO_CNT_L3_CH4_V) << (GDMA_INFIFO_CNT_L3_CH4_S)) -#define GDMA_INFIFO_CNT_L3_CH4_V 0x1F -#define GDMA_INFIFO_CNT_L3_CH4_S 18 -/* GDMA_INFIFO_CNT_L2_CH4 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 4.*/ -#define GDMA_INFIFO_CNT_L2_CH4 0x0000007F -#define GDMA_INFIFO_CNT_L2_CH4_M ((GDMA_INFIFO_CNT_L2_CH4_V) << (GDMA_INFIFO_CNT_L2_CH4_S)) -#define GDMA_INFIFO_CNT_L2_CH4_V 0x7F -#define GDMA_INFIFO_CNT_L2_CH4_S 11 -/* GDMA_INFIFO_CNT_L1_CH4 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 4.*/ -#define GDMA_INFIFO_CNT_L1_CH4 0x0000001F -#define GDMA_INFIFO_CNT_L1_CH4_M ((GDMA_INFIFO_CNT_L1_CH4_V) << (GDMA_INFIFO_CNT_L1_CH4_S)) -#define GDMA_INFIFO_CNT_L1_CH4_V 0x1F -#define GDMA_INFIFO_CNT_L1_CH4_S 6 -/* GDMA_INFIFO_EMPTY_L3_CH4 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Rx FIFO empty signal for Rx channel 4.*/ -#define GDMA_INFIFO_EMPTY_L3_CH4 (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH4_M (BIT(5)) -#define GDMA_INFIFO_EMPTY_L3_CH4_V 0x1 -#define GDMA_INFIFO_EMPTY_L3_CH4_S 5 -/* GDMA_INFIFO_FULL_L3_CH4 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Rx FIFO full signal for Rx channel 4.*/ -#define GDMA_INFIFO_FULL_L3_CH4 (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH4_M (BIT(4)) -#define GDMA_INFIFO_FULL_L3_CH4_V 0x1 -#define GDMA_INFIFO_FULL_L3_CH4_S 4 -/* GDMA_INFIFO_EMPTY_L2_CH4 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Rx FIFO empty signal for Rx channel 4.*/ -#define GDMA_INFIFO_EMPTY_L2_CH4 (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH4_M (BIT(3)) -#define GDMA_INFIFO_EMPTY_L2_CH4_V 0x1 -#define GDMA_INFIFO_EMPTY_L2_CH4_S 3 -/* GDMA_INFIFO_FULL_L2_CH4 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Rx FIFO full signal for Rx channel 4.*/ -#define GDMA_INFIFO_FULL_L2_CH4 (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH4_M (BIT(2)) -#define GDMA_INFIFO_FULL_L2_CH4_V 0x1 -#define GDMA_INFIFO_FULL_L2_CH4_S 2 -/* GDMA_INFIFO_EMPTY_L1_CH4 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO empty signal for Rx channel 4.*/ -#define GDMA_INFIFO_EMPTY_L1_CH4 (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH4_M (BIT(1)) -#define GDMA_INFIFO_EMPTY_L1_CH4_V 0x1 -#define GDMA_INFIFO_EMPTY_L1_CH4_S 1 -/* GDMA_INFIFO_FULL_L1_CH4 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Rx FIFO full signal for Rx channel 4.*/ -#define GDMA_INFIFO_FULL_L1_CH4 (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH4_M (BIT(0)) -#define GDMA_INFIFO_FULL_L1_CH4_V 0x1 -#define GDMA_INFIFO_FULL_L1_CH4_S 0 - -#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x090) -/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH0 (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH0_M (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH0_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH0_S 26 -/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH0 (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH0_M (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH0_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH0_S 25 -/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH0 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0 (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_M (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH0_S 24 -/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH0 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH0 (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH0_M (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH0_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH0_S 23 -/* GDMA_OUTFIFO_CNT_L3_CH0 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/ -#define GDMA_OUTFIFO_CNT_L3_CH0 0x0000001F -#define GDMA_OUTFIFO_CNT_L3_CH0_M ((GDMA_OUTFIFO_CNT_L3_CH0_V) << (GDMA_OUTFIFO_CNT_L3_CH0_S)) -#define GDMA_OUTFIFO_CNT_L3_CH0_V 0x1F -#define GDMA_OUTFIFO_CNT_L3_CH0_S 18 -/* GDMA_OUTFIFO_CNT_L2_CH0 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/ -#define GDMA_OUTFIFO_CNT_L2_CH0 0x0000007F -#define GDMA_OUTFIFO_CNT_L2_CH0_M ((GDMA_OUTFIFO_CNT_L2_CH0_V) << (GDMA_OUTFIFO_CNT_L2_CH0_S)) -#define GDMA_OUTFIFO_CNT_L2_CH0_V 0x7F -#define GDMA_OUTFIFO_CNT_L2_CH0_S 11 -/* GDMA_OUTFIFO_CNT_L1_CH0 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ -#define GDMA_OUTFIFO_CNT_L1_CH0 0x0000001F -#define GDMA_OUTFIFO_CNT_L1_CH0_M ((GDMA_OUTFIFO_CNT_L1_CH0_V) << (GDMA_OUTFIFO_CNT_L1_CH0_S)) -#define GDMA_OUTFIFO_CNT_L1_CH0_V 0x1F -#define GDMA_OUTFIFO_CNT_L1_CH0_S 6 -/* GDMA_OUTFIFO_EMPTY_L3_CH0 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Tx FIFO empty signal for Tx channel 0.*/ -#define GDMA_OUTFIFO_EMPTY_L3_CH0 (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH0_M (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH0_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L3_CH0_S 5 -/* GDMA_OUTFIFO_FULL_L3_CH0 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Tx FIFO full signal for Tx channel 0.*/ -#define GDMA_OUTFIFO_FULL_L3_CH0 (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH0_M (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH0_V 0x1 -#define GDMA_OUTFIFO_FULL_L3_CH0_S 4 -/* GDMA_OUTFIFO_EMPTY_L2_CH0 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Tx FIFO empty signal for Tx channel 0.*/ -#define GDMA_OUTFIFO_EMPTY_L2_CH0 (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH0_M (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH0_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L2_CH0_S 3 -/* GDMA_OUTFIFO_FULL_L2_CH0 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Tx FIFO full signal for Tx channel 0.*/ -#define GDMA_OUTFIFO_FULL_L2_CH0 (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH0_M (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH0_V 0x1 -#define GDMA_OUTFIFO_FULL_L2_CH0_S 2 -/* GDMA_OUTFIFO_EMPTY_L1_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Tx FIFO empty signal for Tx channel 0.*/ -#define GDMA_OUTFIFO_EMPTY_L1_CH0 (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH0_M (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH0_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L1_CH0_S 1 -/* GDMA_OUTFIFO_FULL_L1_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Tx FIFO full signal for Tx channel 0.*/ -#define GDMA_OUTFIFO_FULL_L1_CH0 (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH0_M (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH0_V 0x1 -#define GDMA_OUTFIFO_FULL_L1_CH0_S 0 - -#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x094) -/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH1 (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH1_M (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH1_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH1_S 26 -/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH1 (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH1_M (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH1_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH1_S 25 -/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH1 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1 (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_M (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_S 24 -/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH1 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH1 (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH1_M (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH1_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH1_S 23 -/* GDMA_OUTFIFO_CNT_L3_CH1 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 1.*/ -#define GDMA_OUTFIFO_CNT_L3_CH1 0x0000001F -#define GDMA_OUTFIFO_CNT_L3_CH1_M ((GDMA_OUTFIFO_CNT_L3_CH1_V) << (GDMA_OUTFIFO_CNT_L3_CH1_S)) -#define GDMA_OUTFIFO_CNT_L3_CH1_V 0x1F -#define GDMA_OUTFIFO_CNT_L3_CH1_S 18 -/* GDMA_OUTFIFO_CNT_L2_CH1 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 1.*/ -#define GDMA_OUTFIFO_CNT_L2_CH1 0x0000007F -#define GDMA_OUTFIFO_CNT_L2_CH1_M ((GDMA_OUTFIFO_CNT_L2_CH1_V) << (GDMA_OUTFIFO_CNT_L2_CH1_S)) -#define GDMA_OUTFIFO_CNT_L2_CH1_V 0x7F -#define GDMA_OUTFIFO_CNT_L2_CH1_S 11 -/* GDMA_OUTFIFO_CNT_L1_CH1 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.*/ -#define GDMA_OUTFIFO_CNT_L1_CH1 0x0000001F -#define GDMA_OUTFIFO_CNT_L1_CH1_M ((GDMA_OUTFIFO_CNT_L1_CH1_V) << (GDMA_OUTFIFO_CNT_L1_CH1_S)) -#define GDMA_OUTFIFO_CNT_L1_CH1_V 0x1F -#define GDMA_OUTFIFO_CNT_L1_CH1_S 6 -/* GDMA_OUTFIFO_EMPTY_L3_CH1 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Tx FIFO empty signal for Tx channel 1.*/ -#define GDMA_OUTFIFO_EMPTY_L3_CH1 (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH1_M (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH1_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L3_CH1_S 5 -/* GDMA_OUTFIFO_FULL_L3_CH1 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Tx FIFO full signal for Tx channel 1.*/ -#define GDMA_OUTFIFO_FULL_L3_CH1 (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH1_M (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH1_V 0x1 -#define GDMA_OUTFIFO_FULL_L3_CH1_S 4 -/* GDMA_OUTFIFO_EMPTY_L2_CH1 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Tx FIFO empty signal for Tx channel 1.*/ -#define GDMA_OUTFIFO_EMPTY_L2_CH1 (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH1_M (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH1_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L2_CH1_S 3 -/* GDMA_OUTFIFO_FULL_L2_CH1 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Tx FIFO full signal for Tx channel 1.*/ -#define GDMA_OUTFIFO_FULL_L2_CH1 (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH1_M (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH1_V 0x1 -#define GDMA_OUTFIFO_FULL_L2_CH1_S 2 -/* GDMA_OUTFIFO_EMPTY_L1_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Tx FIFO empty signal for Tx channel 1.*/ -#define GDMA_OUTFIFO_EMPTY_L1_CH1 (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH1_M (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH1_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L1_CH1_S 1 -/* GDMA_OUTFIFO_FULL_L1_CH1 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Tx FIFO full signal for Tx channel 1.*/ -#define GDMA_OUTFIFO_FULL_L1_CH1 (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH1_M (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH1_V 0x1 -#define GDMA_OUTFIFO_FULL_L1_CH1_S 0 - -#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x098) -/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH2 (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH2_M (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH2_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH2_S 26 -/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH2 (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH2_M (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH2_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH2_S 25 -/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH2 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2 (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_M (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_S 24 -/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH2 (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH2_M (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH2_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH2_S 23 -/* GDMA_OUTFIFO_CNT_L3_CH2 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 2.*/ -#define GDMA_OUTFIFO_CNT_L3_CH2 0x0000001F -#define GDMA_OUTFIFO_CNT_L3_CH2_M ((GDMA_OUTFIFO_CNT_L3_CH2_V) << (GDMA_OUTFIFO_CNT_L3_CH2_S)) -#define GDMA_OUTFIFO_CNT_L3_CH2_V 0x1F -#define GDMA_OUTFIFO_CNT_L3_CH2_S 18 -/* GDMA_OUTFIFO_CNT_L2_CH2 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 2.*/ -#define GDMA_OUTFIFO_CNT_L2_CH2 0x0000007F -#define GDMA_OUTFIFO_CNT_L2_CH2_M ((GDMA_OUTFIFO_CNT_L2_CH2_V) << (GDMA_OUTFIFO_CNT_L2_CH2_S)) -#define GDMA_OUTFIFO_CNT_L2_CH2_V 0x7F -#define GDMA_OUTFIFO_CNT_L2_CH2_S 11 -/* GDMA_OUTFIFO_CNT_L1_CH2 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.*/ -#define GDMA_OUTFIFO_CNT_L1_CH2 0x0000001F -#define GDMA_OUTFIFO_CNT_L1_CH2_M ((GDMA_OUTFIFO_CNT_L1_CH2_V) << (GDMA_OUTFIFO_CNT_L1_CH2_S)) -#define GDMA_OUTFIFO_CNT_L1_CH2_V 0x1F -#define GDMA_OUTFIFO_CNT_L1_CH2_S 6 -/* GDMA_OUTFIFO_EMPTY_L3_CH2 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Tx FIFO empty signal for Tx channel 2.*/ -#define GDMA_OUTFIFO_EMPTY_L3_CH2 (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH2_M (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH2_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L3_CH2_S 5 -/* GDMA_OUTFIFO_FULL_L3_CH2 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Tx FIFO full signal for Tx channel 2.*/ -#define GDMA_OUTFIFO_FULL_L3_CH2 (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH2_M (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH2_V 0x1 -#define GDMA_OUTFIFO_FULL_L3_CH2_S 4 -/* GDMA_OUTFIFO_EMPTY_L2_CH2 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Tx FIFO empty signal for Tx channel 2.*/ -#define GDMA_OUTFIFO_EMPTY_L2_CH2 (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH2_M (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH2_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L2_CH2_S 3 -/* GDMA_OUTFIFO_FULL_L2_CH2 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Tx FIFO full signal for Tx channel 2.*/ -#define GDMA_OUTFIFO_FULL_L2_CH2 (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH2_M (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH2_V 0x1 -#define GDMA_OUTFIFO_FULL_L2_CH2_S 2 -/* GDMA_OUTFIFO_EMPTY_L1_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Tx FIFO empty signal for Tx channel 2.*/ -#define GDMA_OUTFIFO_EMPTY_L1_CH2 (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH2_M (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH2_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L1_CH2_S 1 -/* GDMA_OUTFIFO_FULL_L1_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Tx FIFO full signal for Tx channel 2.*/ -#define GDMA_OUTFIFO_FULL_L1_CH2 (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH2_M (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH2_V 0x1 -#define GDMA_OUTFIFO_FULL_L1_CH2_S 0 - -#define GDMA_OUTFIFO_STATUS_CH3_REG (DR_REG_GDMA_BASE + 0x09C) -/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH3 (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH3_M (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH3_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH3_S 26 -/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH3 (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH3_M (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH3_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH3_S 25 -/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH3 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH3 (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH3_M (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH3_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH3_S 24 -/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH3 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH3 (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH3_M (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH3_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH3_S 23 -/* GDMA_OUTFIFO_CNT_L3_CH3 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 3.*/ -#define GDMA_OUTFIFO_CNT_L3_CH3 0x0000001F -#define GDMA_OUTFIFO_CNT_L3_CH3_M ((GDMA_OUTFIFO_CNT_L3_CH3_V) << (GDMA_OUTFIFO_CNT_L3_CH3_S)) -#define GDMA_OUTFIFO_CNT_L3_CH3_V 0x1F -#define GDMA_OUTFIFO_CNT_L3_CH3_S 18 -/* GDMA_OUTFIFO_CNT_L2_CH3 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 3.*/ -#define GDMA_OUTFIFO_CNT_L2_CH3 0x0000007F -#define GDMA_OUTFIFO_CNT_L2_CH3_M ((GDMA_OUTFIFO_CNT_L2_CH3_V) << (GDMA_OUTFIFO_CNT_L2_CH3_S)) -#define GDMA_OUTFIFO_CNT_L2_CH3_V 0x7F -#define GDMA_OUTFIFO_CNT_L2_CH3_S 11 -/* GDMA_OUTFIFO_CNT_L1_CH3 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 3.*/ -#define GDMA_OUTFIFO_CNT_L1_CH3 0x0000001F -#define GDMA_OUTFIFO_CNT_L1_CH3_M ((GDMA_OUTFIFO_CNT_L1_CH3_V) << (GDMA_OUTFIFO_CNT_L1_CH3_S)) -#define GDMA_OUTFIFO_CNT_L1_CH3_V 0x1F -#define GDMA_OUTFIFO_CNT_L1_CH3_S 6 -/* GDMA_OUTFIFO_EMPTY_L3_CH3 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Tx FIFO empty signal for Tx channel 3.*/ -#define GDMA_OUTFIFO_EMPTY_L3_CH3 (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH3_M (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH3_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L3_CH3_S 5 -/* GDMA_OUTFIFO_FULL_L3_CH3 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Tx FIFO full signal for Tx channel 3.*/ -#define GDMA_OUTFIFO_FULL_L3_CH3 (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH3_M (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH3_V 0x1 -#define GDMA_OUTFIFO_FULL_L3_CH3_S 4 -/* GDMA_OUTFIFO_EMPTY_L2_CH3 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Tx FIFO empty signal for Tx channel 3.*/ -#define GDMA_OUTFIFO_EMPTY_L2_CH3 (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH3_M (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH3_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L2_CH3_S 3 -/* GDMA_OUTFIFO_FULL_L2_CH3 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Tx FIFO full signal for Tx channel 3.*/ -#define GDMA_OUTFIFO_FULL_L2_CH3 (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH3_M (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH3_V 0x1 -#define GDMA_OUTFIFO_FULL_L2_CH3_S 2 -/* GDMA_OUTFIFO_EMPTY_L1_CH3 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Tx FIFO empty signal for Tx channel 3.*/ -#define GDMA_OUTFIFO_EMPTY_L1_CH3 (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH3_M (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH3_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L1_CH3_S 1 -/* GDMA_OUTFIFO_FULL_L1_CH3 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Tx FIFO full signal for Tx channel 3.*/ -#define GDMA_OUTFIFO_FULL_L1_CH3 (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH3_M (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH3_V 0x1 -#define GDMA_OUTFIFO_FULL_L1_CH3_S 0 - -#define GDMA_OUTFIFO_STATUS_CH4_REG (DR_REG_GDMA_BASE + 0x0A0) -/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH4 (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH4_M (BIT(26)) -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH4_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH4_S 26 -/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH4 (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH4_M (BIT(25)) -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH4_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH4_S 25 -/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH4 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH4 (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH4_M (BIT(24)) -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH4_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH4_S 24 -/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH4 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH4 (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH4_M (BIT(23)) -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH4_V 0x1 -#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH4_S 23 -/* GDMA_OUTFIFO_CNT_L3_CH4 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 4.*/ -#define GDMA_OUTFIFO_CNT_L3_CH4 0x0000001F -#define GDMA_OUTFIFO_CNT_L3_CH4_M ((GDMA_OUTFIFO_CNT_L3_CH4_V) << (GDMA_OUTFIFO_CNT_L3_CH4_S)) -#define GDMA_OUTFIFO_CNT_L3_CH4_V 0x1F -#define GDMA_OUTFIFO_CNT_L3_CH4_S 18 -/* GDMA_OUTFIFO_CNT_L2_CH4 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ -/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 4.*/ -#define GDMA_OUTFIFO_CNT_L2_CH4 0x0000007F -#define GDMA_OUTFIFO_CNT_L2_CH4_M ((GDMA_OUTFIFO_CNT_L2_CH4_V) << (GDMA_OUTFIFO_CNT_L2_CH4_S)) -#define GDMA_OUTFIFO_CNT_L2_CH4_V 0x7F -#define GDMA_OUTFIFO_CNT_L2_CH4_S 11 -/* GDMA_OUTFIFO_CNT_L1_CH4 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ -/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 4.*/ -#define GDMA_OUTFIFO_CNT_L1_CH4 0x0000001F -#define GDMA_OUTFIFO_CNT_L1_CH4_M ((GDMA_OUTFIFO_CNT_L1_CH4_V) << (GDMA_OUTFIFO_CNT_L1_CH4_S)) -#define GDMA_OUTFIFO_CNT_L1_CH4_V 0x1F -#define GDMA_OUTFIFO_CNT_L1_CH4_S 6 -/* GDMA_OUTFIFO_EMPTY_L3_CH4 : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: L3 Tx FIFO empty signal for Tx channel 4.*/ -#define GDMA_OUTFIFO_EMPTY_L3_CH4 (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH4_M (BIT(5)) -#define GDMA_OUTFIFO_EMPTY_L3_CH4_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L3_CH4_S 5 -/* GDMA_OUTFIFO_FULL_L3_CH4 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: L3 Tx FIFO full signal for Tx channel 4.*/ -#define GDMA_OUTFIFO_FULL_L3_CH4 (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH4_M (BIT(4)) -#define GDMA_OUTFIFO_FULL_L3_CH4_V 0x1 -#define GDMA_OUTFIFO_FULL_L3_CH4_S 4 -/* GDMA_OUTFIFO_EMPTY_L2_CH4 : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: L2 Tx FIFO empty signal for Tx channel 4.*/ -#define GDMA_OUTFIFO_EMPTY_L2_CH4 (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH4_M (BIT(3)) -#define GDMA_OUTFIFO_EMPTY_L2_CH4_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L2_CH4_S 3 -/* GDMA_OUTFIFO_FULL_L2_CH4 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: L2 Tx FIFO full signal for Tx channel 4.*/ -#define GDMA_OUTFIFO_FULL_L2_CH4 (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH4_M (BIT(2)) -#define GDMA_OUTFIFO_FULL_L2_CH4_V 0x1 -#define GDMA_OUTFIFO_FULL_L2_CH4_S 2 -/* GDMA_OUTFIFO_EMPTY_L1_CH4 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Tx FIFO empty signal for Tx channel 4.*/ -#define GDMA_OUTFIFO_EMPTY_L1_CH4 (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH4_M (BIT(1)) -#define GDMA_OUTFIFO_EMPTY_L1_CH4_V 0x1 -#define GDMA_OUTFIFO_EMPTY_L1_CH4_S 1 -/* GDMA_OUTFIFO_FULL_L1_CH4 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Tx FIFO full signal for Tx channel 4.*/ -#define GDMA_OUTFIFO_FULL_L1_CH4 (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH4_M (BIT(0)) -#define GDMA_OUTFIFO_FULL_L1_CH4_V 0x1 -#define GDMA_OUTFIFO_FULL_L1_CH4_S 0 - -#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0x0A4) -/* GDMA_OUTFIFO_PUSH_CH0 : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to push data into DMA FIFO.*/ -#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH0_M (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH0_V 0x1 -#define GDMA_OUTFIFO_PUSH_CH0_S 9 -/* GDMA_OUTFIFO_WDATA_CH0 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: This register stores the data that need to be pushed into DMA FIFO.*/ -#define GDMA_OUTFIFO_WDATA_CH0 0x000001FF -#define GDMA_OUTFIFO_WDATA_CH0_M ((GDMA_OUTFIFO_WDATA_CH0_V) << (GDMA_OUTFIFO_WDATA_CH0_S)) -#define GDMA_OUTFIFO_WDATA_CH0_V 0x1FF -#define GDMA_OUTFIFO_WDATA_CH0_S 0 - -#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x0A8) -/* GDMA_OUTFIFO_PUSH_CH1 : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to push data into DMA FIFO.*/ -#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH1_M (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH1_V 0x1 -#define GDMA_OUTFIFO_PUSH_CH1_S 9 -/* GDMA_OUTFIFO_WDATA_CH1 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: This register stores the data that need to be pushed into DMA FIFO.*/ -#define GDMA_OUTFIFO_WDATA_CH1 0x000001FF -#define GDMA_OUTFIFO_WDATA_CH1_M ((GDMA_OUTFIFO_WDATA_CH1_V) << (GDMA_OUTFIFO_WDATA_CH1_S)) -#define GDMA_OUTFIFO_WDATA_CH1_V 0x1FF -#define GDMA_OUTFIFO_WDATA_CH1_S 0 - -#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x0AC) -/* GDMA_OUTFIFO_PUSH_CH2 : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to push data into DMA FIFO.*/ -#define GDMA_OUTFIFO_PUSH_CH2 (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH2_M (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH2_V 0x1 -#define GDMA_OUTFIFO_PUSH_CH2_S 9 -/* GDMA_OUTFIFO_WDATA_CH2 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: This register stores the data that need to be pushed into DMA FIFO.*/ -#define GDMA_OUTFIFO_WDATA_CH2 0x000001FF -#define GDMA_OUTFIFO_WDATA_CH2_M ((GDMA_OUTFIFO_WDATA_CH2_V) << (GDMA_OUTFIFO_WDATA_CH2_S)) -#define GDMA_OUTFIFO_WDATA_CH2_V 0x1FF -#define GDMA_OUTFIFO_WDATA_CH2_S 0 - -#define GDMA_OUT_PUSH_CH3_REG (DR_REG_GDMA_BASE + 0x0B0) -/* GDMA_OUTFIFO_PUSH_CH3 : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to push data into DMA FIFO.*/ -#define GDMA_OUTFIFO_PUSH_CH3 (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH3_M (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH3_V 0x1 -#define GDMA_OUTFIFO_PUSH_CH3_S 9 -/* GDMA_OUTFIFO_WDATA_CH3 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: This register stores the data that need to be pushed into DMA FIFO.*/ -#define GDMA_OUTFIFO_WDATA_CH3 0x000001FF -#define GDMA_OUTFIFO_WDATA_CH3_M ((GDMA_OUTFIFO_WDATA_CH3_V) << (GDMA_OUTFIFO_WDATA_CH3_S)) -#define GDMA_OUTFIFO_WDATA_CH3_V 0x1FF -#define GDMA_OUTFIFO_WDATA_CH3_S 0 - -#define GDMA_OUT_PUSH_CH4_REG (DR_REG_GDMA_BASE + 0x0B4) -/* GDMA_OUTFIFO_PUSH_CH4 : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to push data into DMA FIFO.*/ -#define GDMA_OUTFIFO_PUSH_CH4 (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH4_M (BIT(9)) -#define GDMA_OUTFIFO_PUSH_CH4_V 0x1 -#define GDMA_OUTFIFO_PUSH_CH4_S 9 -/* GDMA_OUTFIFO_WDATA_CH4 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: This register stores the data that need to be pushed into DMA FIFO.*/ -#define GDMA_OUTFIFO_WDATA_CH4 0x000001FF -#define GDMA_OUTFIFO_WDATA_CH4_M ((GDMA_OUTFIFO_WDATA_CH4_V) << (GDMA_OUTFIFO_WDATA_CH4_S)) -#define GDMA_OUTFIFO_WDATA_CH4_V 0x1FF -#define GDMA_OUTFIFO_WDATA_CH4_S 0 - -#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x0B8) -/* GDMA_INFIFO_POP_CH0 : R/W ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to pop data from DMA FIFO.*/ -#define GDMA_INFIFO_POP_CH0 (BIT(12)) -#define GDMA_INFIFO_POP_CH0_M (BIT(12)) -#define GDMA_INFIFO_POP_CH0_V 0x1 -#define GDMA_INFIFO_POP_CH0_S 12 -/* GDMA_INFIFO_RDATA_CH0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: This register stores the data popping from DMA FIFO.*/ -#define GDMA_INFIFO_RDATA_CH0 0x00000FFF -#define GDMA_INFIFO_RDATA_CH0_M ((GDMA_INFIFO_RDATA_CH0_V) << (GDMA_INFIFO_RDATA_CH0_S)) -#define GDMA_INFIFO_RDATA_CH0_V 0xFFF -#define GDMA_INFIFO_RDATA_CH0_S 0 - -#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x0BC) -/* GDMA_INFIFO_POP_CH1 : R/W ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to pop data from DMA FIFO.*/ -#define GDMA_INFIFO_POP_CH1 (BIT(12)) -#define GDMA_INFIFO_POP_CH1_M (BIT(12)) -#define GDMA_INFIFO_POP_CH1_V 0x1 -#define GDMA_INFIFO_POP_CH1_S 12 -/* GDMA_INFIFO_RDATA_CH1 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: This register stores the data popping from DMA FIFO.*/ -#define GDMA_INFIFO_RDATA_CH1 0x00000FFF -#define GDMA_INFIFO_RDATA_CH1_M ((GDMA_INFIFO_RDATA_CH1_V) << (GDMA_INFIFO_RDATA_CH1_S)) -#define GDMA_INFIFO_RDATA_CH1_V 0xFFF -#define GDMA_INFIFO_RDATA_CH1_S 0 - -#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x0C0) -/* GDMA_INFIFO_POP_CH2 : R/W ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to pop data from DMA FIFO.*/ -#define GDMA_INFIFO_POP_CH2 (BIT(12)) -#define GDMA_INFIFO_POP_CH2_M (BIT(12)) -#define GDMA_INFIFO_POP_CH2_V 0x1 -#define GDMA_INFIFO_POP_CH2_S 12 -/* GDMA_INFIFO_RDATA_CH2 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: This register stores the data popping from DMA FIFO.*/ -#define GDMA_INFIFO_RDATA_CH2 0x00000FFF -#define GDMA_INFIFO_RDATA_CH2_M ((GDMA_INFIFO_RDATA_CH2_V) << (GDMA_INFIFO_RDATA_CH2_S)) -#define GDMA_INFIFO_RDATA_CH2_V 0xFFF -#define GDMA_INFIFO_RDATA_CH2_S 0 - -#define GDMA_IN_POP_CH3_REG (DR_REG_GDMA_BASE + 0x0C4) -/* GDMA_INFIFO_POP_CH3 : R/W ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to pop data from DMA FIFO.*/ -#define GDMA_INFIFO_POP_CH3 (BIT(12)) -#define GDMA_INFIFO_POP_CH3_M (BIT(12)) -#define GDMA_INFIFO_POP_CH3_V 0x1 -#define GDMA_INFIFO_POP_CH3_S 12 -/* GDMA_INFIFO_RDATA_CH3 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: This register stores the data popping from DMA FIFO.*/ -#define GDMA_INFIFO_RDATA_CH3 0x00000FFF -#define GDMA_INFIFO_RDATA_CH3_M ((GDMA_INFIFO_RDATA_CH3_V) << (GDMA_INFIFO_RDATA_CH3_S)) -#define GDMA_INFIFO_RDATA_CH3_V 0xFFF -#define GDMA_INFIFO_RDATA_CH3_S 0 - -#define GDMA_IN_POP_CH4_REG (DR_REG_GDMA_BASE + 0x0C8) -/* GDMA_INFIFO_POP_CH4 : R/W ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to pop data from DMA FIFO.*/ -#define GDMA_INFIFO_POP_CH4 (BIT(12)) -#define GDMA_INFIFO_POP_CH4_M (BIT(12)) -#define GDMA_INFIFO_POP_CH4_V 0x1 -#define GDMA_INFIFO_POP_CH4_S 12 -/* GDMA_INFIFO_RDATA_CH4 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: This register stores the data popping from DMA FIFO.*/ -#define GDMA_INFIFO_RDATA_CH4 0x00000FFF -#define GDMA_INFIFO_RDATA_CH4_M ((GDMA_INFIFO_RDATA_CH4_V) << (GDMA_INFIFO_RDATA_CH4_S)) -#define GDMA_INFIFO_RDATA_CH4_V 0xFFF -#define GDMA_INFIFO_RDATA_CH4_S 0 - -#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x0CC) -/* GDMA_OUTLINK_PARK_CH0 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working.*/ -#define GDMA_OUTLINK_PARK_CH0 (BIT(23)) -#define GDMA_OUTLINK_PARK_CH0_M (BIT(23)) -#define GDMA_OUTLINK_PARK_CH0_V 0x1 -#define GDMA_OUTLINK_PARK_CH0_S 23 -/* GDMA_OUTLINK_RESTART_CH0 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to restart a new outlink from the last address.*/ -#define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH0_M (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH0_V 0x1 -#define GDMA_OUTLINK_RESTART_CH0_S 22 -/* GDMA_OUTLINK_START_CH0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_START_CH0 (BIT(21)) -#define GDMA_OUTLINK_START_CH0_M (BIT(21)) -#define GDMA_OUTLINK_START_CH0_V 0x1 -#define GDMA_OUTLINK_START_CH0_S 21 -/* GDMA_OUTLINK_STOP_CH0 : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_STOP_CH0 (BIT(20)) -#define GDMA_OUTLINK_STOP_CH0_M (BIT(20)) -#define GDMA_OUTLINK_STOP_CH0_V 0x1 -#define GDMA_OUTLINK_STOP_CH0_S 20 -/* GDMA_OUTLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - outlink descriptor's address.*/ -#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFF -#define GDMA_OUTLINK_ADDR_CH0_M ((GDMA_OUTLINK_ADDR_CH0_V) << (GDMA_OUTLINK_ADDR_CH0_S)) -#define GDMA_OUTLINK_ADDR_CH0_V 0xFFFFF -#define GDMA_OUTLINK_ADDR_CH0_S 0 - -#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x0D0) -/* GDMA_OUTLINK_PARK_CH1 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working.*/ -#define GDMA_OUTLINK_PARK_CH1 (BIT(23)) -#define GDMA_OUTLINK_PARK_CH1_M (BIT(23)) -#define GDMA_OUTLINK_PARK_CH1_V 0x1 -#define GDMA_OUTLINK_PARK_CH1_S 23 -/* GDMA_OUTLINK_RESTART_CH1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to restart a new outlink from the last address.*/ -#define GDMA_OUTLINK_RESTART_CH1 (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH1_M (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH1_V 0x1 -#define GDMA_OUTLINK_RESTART_CH1_S 22 -/* GDMA_OUTLINK_START_CH1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_START_CH1 (BIT(21)) -#define GDMA_OUTLINK_START_CH1_M (BIT(21)) -#define GDMA_OUTLINK_START_CH1_V 0x1 -#define GDMA_OUTLINK_START_CH1_S 21 -/* GDMA_OUTLINK_STOP_CH1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_STOP_CH1 (BIT(20)) -#define GDMA_OUTLINK_STOP_CH1_M (BIT(20)) -#define GDMA_OUTLINK_STOP_CH1_V 0x1 -#define GDMA_OUTLINK_STOP_CH1_S 20 -/* GDMA_OUTLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - outlink descriptor's address.*/ -#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFF -#define GDMA_OUTLINK_ADDR_CH1_M ((GDMA_OUTLINK_ADDR_CH1_V) << (GDMA_OUTLINK_ADDR_CH1_S)) -#define GDMA_OUTLINK_ADDR_CH1_V 0xFFFFF -#define GDMA_OUTLINK_ADDR_CH1_S 0 - -#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x0D4) -/* GDMA_OUTLINK_PARK_CH2 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working.*/ -#define GDMA_OUTLINK_PARK_CH2 (BIT(23)) -#define GDMA_OUTLINK_PARK_CH2_M (BIT(23)) -#define GDMA_OUTLINK_PARK_CH2_V 0x1 -#define GDMA_OUTLINK_PARK_CH2_S 23 -/* GDMA_OUTLINK_RESTART_CH2 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to restart a new outlink from the last address.*/ -#define GDMA_OUTLINK_RESTART_CH2 (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH2_M (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH2_V 0x1 -#define GDMA_OUTLINK_RESTART_CH2_S 22 -/* GDMA_OUTLINK_START_CH2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_START_CH2 (BIT(21)) -#define GDMA_OUTLINK_START_CH2_M (BIT(21)) -#define GDMA_OUTLINK_START_CH2_V 0x1 -#define GDMA_OUTLINK_START_CH2_S 21 -/* GDMA_OUTLINK_STOP_CH2 : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_STOP_CH2 (BIT(20)) -#define GDMA_OUTLINK_STOP_CH2_M (BIT(20)) -#define GDMA_OUTLINK_STOP_CH2_V 0x1 -#define GDMA_OUTLINK_STOP_CH2_S 20 -/* GDMA_OUTLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - outlink descriptor's address.*/ -#define GDMA_OUTLINK_ADDR_CH2 0x000FFFFF -#define GDMA_OUTLINK_ADDR_CH2_M ((GDMA_OUTLINK_ADDR_CH2_V) << (GDMA_OUTLINK_ADDR_CH2_S)) -#define GDMA_OUTLINK_ADDR_CH2_V 0xFFFFF -#define GDMA_OUTLINK_ADDR_CH2_S 0 - -#define GDMA_OUT_LINK_CH3_REG (DR_REG_GDMA_BASE + 0x0D8) -/* GDMA_OUTLINK_PARK_CH3 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working.*/ -#define GDMA_OUTLINK_PARK_CH3 (BIT(23)) -#define GDMA_OUTLINK_PARK_CH3_M (BIT(23)) -#define GDMA_OUTLINK_PARK_CH3_V 0x1 -#define GDMA_OUTLINK_PARK_CH3_S 23 -/* GDMA_OUTLINK_RESTART_CH3 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to restart a new outlink from the last address.*/ -#define GDMA_OUTLINK_RESTART_CH3 (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH3_M (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH3_V 0x1 -#define GDMA_OUTLINK_RESTART_CH3_S 22 -/* GDMA_OUTLINK_START_CH3 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_START_CH3 (BIT(21)) -#define GDMA_OUTLINK_START_CH3_M (BIT(21)) -#define GDMA_OUTLINK_START_CH3_V 0x1 -#define GDMA_OUTLINK_START_CH3_S 21 -/* GDMA_OUTLINK_STOP_CH3 : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_STOP_CH3 (BIT(20)) -#define GDMA_OUTLINK_STOP_CH3_M (BIT(20)) -#define GDMA_OUTLINK_STOP_CH3_V 0x1 -#define GDMA_OUTLINK_STOP_CH3_S 20 -/* GDMA_OUTLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - outlink descriptor's address.*/ -#define GDMA_OUTLINK_ADDR_CH3 0x000FFFFF -#define GDMA_OUTLINK_ADDR_CH3_M ((GDMA_OUTLINK_ADDR_CH3_V) << (GDMA_OUTLINK_ADDR_CH3_S)) -#define GDMA_OUTLINK_ADDR_CH3_V 0xFFFFF -#define GDMA_OUTLINK_ADDR_CH3_S 0 - -#define GDMA_OUT_LINK_CH4_REG (DR_REG_GDMA_BASE + 0x0DC) -/* GDMA_OUTLINK_PARK_CH4 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working.*/ -#define GDMA_OUTLINK_PARK_CH4 (BIT(23)) -#define GDMA_OUTLINK_PARK_CH4_M (BIT(23)) -#define GDMA_OUTLINK_PARK_CH4_V 0x1 -#define GDMA_OUTLINK_PARK_CH4_S 23 -/* GDMA_OUTLINK_RESTART_CH4 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to restart a new outlink from the last address.*/ -#define GDMA_OUTLINK_RESTART_CH4 (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH4_M (BIT(22)) -#define GDMA_OUTLINK_RESTART_CH4_V 0x1 -#define GDMA_OUTLINK_RESTART_CH4_S 22 -/* GDMA_OUTLINK_START_CH4 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_START_CH4 (BIT(21)) -#define GDMA_OUTLINK_START_CH4_M (BIT(21)) -#define GDMA_OUTLINK_START_CH4_V 0x1 -#define GDMA_OUTLINK_START_CH4_S 21 -/* GDMA_OUTLINK_STOP_CH4 : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the outlink descriptors.*/ -#define GDMA_OUTLINK_STOP_CH4 (BIT(20)) -#define GDMA_OUTLINK_STOP_CH4_M (BIT(20)) -#define GDMA_OUTLINK_STOP_CH4_V 0x1 -#define GDMA_OUTLINK_STOP_CH4_S 20 -/* GDMA_OUTLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - outlink descriptor's address.*/ -#define GDMA_OUTLINK_ADDR_CH4 0x000FFFFF -#define GDMA_OUTLINK_ADDR_CH4_M ((GDMA_OUTLINK_ADDR_CH4_V) << (GDMA_OUTLINK_ADDR_CH4_S)) -#define GDMA_OUTLINK_ADDR_CH4_V 0xFFFFF -#define GDMA_OUTLINK_ADDR_CH4_S 0 - -#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x0E0) -/* GDMA_INLINK_PARK_CH0 : RO ;bitpos:[24] ;default: 1'h1 ; */ -/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working.*/ -#define GDMA_INLINK_PARK_CH0 (BIT(24)) -#define GDMA_INLINK_PARK_CH0_M (BIT(24)) -#define GDMA_INLINK_PARK_CH0_V 0x1 -#define GDMA_INLINK_PARK_CH0_S 24 -/* GDMA_INLINK_RESTART_CH0 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to mount a new inlink descriptor.*/ -#define GDMA_INLINK_RESTART_CH0 (BIT(23)) -#define GDMA_INLINK_RESTART_CH0_M (BIT(23)) -#define GDMA_INLINK_RESTART_CH0_V 0x1 -#define GDMA_INLINK_RESTART_CH0_S 23 -/* GDMA_INLINK_START_CH0 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the inlink descriptors.*/ -#define GDMA_INLINK_START_CH0 (BIT(22)) -#define GDMA_INLINK_START_CH0_M (BIT(22)) -#define GDMA_INLINK_START_CH0_V 0x1 -#define GDMA_INLINK_START_CH0_S 22 -/* GDMA_INLINK_STOP_CH0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the inlink descriptors.*/ -#define GDMA_INLINK_STOP_CH0 (BIT(21)) -#define GDMA_INLINK_STOP_CH0_M (BIT(21)) -#define GDMA_INLINK_STOP_CH0_V 0x1 -#define GDMA_INLINK_STOP_CH0_S 21 -/* GDMA_INLINK_AUTO_RET_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data.*/ -#define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH0_M (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH0_V 0x1 -#define GDMA_INLINK_AUTO_RET_CH0_S 20 -/* GDMA_INLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - inlink descriptor's address.*/ -#define GDMA_INLINK_ADDR_CH0 0x000FFFFF -#define GDMA_INLINK_ADDR_CH0_M ((GDMA_INLINK_ADDR_CH0_V) << (GDMA_INLINK_ADDR_CH0_S)) -#define GDMA_INLINK_ADDR_CH0_V 0xFFFFF -#define GDMA_INLINK_ADDR_CH0_S 0 - -#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x0E4) +#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0xE0) /* GDMA_INLINK_PARK_CH1 : RO ;bitpos:[24] ;default: 1'h1 ; */ -/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working.*/ -#define GDMA_INLINK_PARK_CH1 (BIT(24)) -#define GDMA_INLINK_PARK_CH1_M (BIT(24)) -#define GDMA_INLINK_PARK_CH1_V 0x1 -#define GDMA_INLINK_PARK_CH1_S 24 -/* GDMA_INLINK_RESTART_CH1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to mount a new inlink descriptor.*/ -#define GDMA_INLINK_RESTART_CH1 (BIT(23)) -#define GDMA_INLINK_RESTART_CH1_M (BIT(23)) -#define GDMA_INLINK_RESTART_CH1_V 0x1 -#define GDMA_INLINK_RESTART_CH1_S 23 -/* GDMA_INLINK_START_CH1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the inlink descriptors.*/ -#define GDMA_INLINK_START_CH1 (BIT(22)) -#define GDMA_INLINK_START_CH1_M (BIT(22)) -#define GDMA_INLINK_START_CH1_V 0x1 -#define GDMA_INLINK_START_CH1_S 22 -/* GDMA_INLINK_STOP_CH1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the inlink descriptors.*/ -#define GDMA_INLINK_STOP_CH1 (BIT(21)) -#define GDMA_INLINK_STOP_CH1_M (BIT(21)) -#define GDMA_INLINK_STOP_CH1_V 0x1 -#define GDMA_INLINK_STOP_CH1_S 21 +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM + is working..*/ +#define GDMA_INLINK_PARK_CH1 (BIT(24)) +#define GDMA_INLINK_PARK_CH1_M (BIT(24)) +#define GDMA_INLINK_PARK_CH1_V 0x1 +#define GDMA_INLINK_PARK_CH1_S 24 +/* GDMA_INLINK_RESTART_CH1 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor..*/ +#define GDMA_INLINK_RESTART_CH1 (BIT(23)) +#define GDMA_INLINK_RESTART_CH1_M (BIT(23)) +#define GDMA_INLINK_RESTART_CH1_V 0x1 +#define GDMA_INLINK_RESTART_CH1_S 23 +/* GDMA_INLINK_START_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors..*/ +#define GDMA_INLINK_START_CH1 (BIT(22)) +#define GDMA_INLINK_START_CH1_M (BIT(22)) +#define GDMA_INLINK_START_CH1_V 0x1 +#define GDMA_INLINK_START_CH1_S 22 +/* GDMA_INLINK_STOP_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors..*/ +#define GDMA_INLINK_STOP_CH1 (BIT(21)) +#define GDMA_INLINK_STOP_CH1_M (BIT(21)) +#define GDMA_INLINK_STOP_CH1_V 0x1 +#define GDMA_INLINK_STOP_CH1_S 21 /* GDMA_INLINK_AUTO_RET_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data.*/ -#define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH1_M (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH1_V 0x1 -#define GDMA_INLINK_AUTO_RET_CH1_S 20 +/*description: Set this bit to return to current inlink descriptor's address, when there are so +me errors in current receiving data..*/ +#define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH1_M (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH1_V 0x1 +#define GDMA_INLINK_AUTO_RET_CH1_S 20 /* GDMA_INLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - inlink descriptor's address.*/ -#define GDMA_INLINK_ADDR_CH1 0x000FFFFF -#define GDMA_INLINK_ADDR_CH1_M ((GDMA_INLINK_ADDR_CH1_V) << (GDMA_INLINK_ADDR_CH1_S)) -#define GDMA_INLINK_ADDR_CH1_V 0xFFFFF -#define GDMA_INLINK_ADDR_CH1_S 0 +/*description: This register stores the 20 least significant bits of the first inlink descripto +r's address..*/ +#define GDMA_INLINK_ADDR_CH1 0x000FFFFF +#define GDMA_INLINK_ADDR_CH1_M ((GDMA_INLINK_ADDR_CH1_V)<<(GDMA_INLINK_ADDR_CH1_S)) +#define GDMA_INLINK_ADDR_CH1_V 0xFFFFF +#define GDMA_INLINK_ADDR_CH1_S 0 -#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x0E8) -/* GDMA_INLINK_PARK_CH2 : RO ;bitpos:[24] ;default: 1'h1 ; */ -/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working.*/ -#define GDMA_INLINK_PARK_CH2 (BIT(24)) -#define GDMA_INLINK_PARK_CH2_M (BIT(24)) -#define GDMA_INLINK_PARK_CH2_V 0x1 -#define GDMA_INLINK_PARK_CH2_S 24 -/* GDMA_INLINK_RESTART_CH2 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to mount a new inlink descriptor.*/ -#define GDMA_INLINK_RESTART_CH2 (BIT(23)) -#define GDMA_INLINK_RESTART_CH2_M (BIT(23)) -#define GDMA_INLINK_RESTART_CH2_V 0x1 -#define GDMA_INLINK_RESTART_CH2_S 23 -/* GDMA_INLINK_START_CH2 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the inlink descriptors.*/ -#define GDMA_INLINK_START_CH2 (BIT(22)) -#define GDMA_INLINK_START_CH2_M (BIT(22)) -#define GDMA_INLINK_START_CH2_V 0x1 -#define GDMA_INLINK_START_CH2_S 22 -/* GDMA_INLINK_STOP_CH2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the inlink descriptors.*/ -#define GDMA_INLINK_STOP_CH2 (BIT(21)) -#define GDMA_INLINK_STOP_CH2_M (BIT(21)) -#define GDMA_INLINK_STOP_CH2_V 0x1 -#define GDMA_INLINK_STOP_CH2_S 21 -/* GDMA_INLINK_AUTO_RET_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data.*/ -#define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH2_M (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH2_V 0x1 -#define GDMA_INLINK_AUTO_RET_CH2_S 20 -/* GDMA_INLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - inlink descriptor's address.*/ -#define GDMA_INLINK_ADDR_CH2 0x000FFFFF -#define GDMA_INLINK_ADDR_CH2_M ((GDMA_INLINK_ADDR_CH2_V) << (GDMA_INLINK_ADDR_CH2_S)) -#define GDMA_INLINK_ADDR_CH2_V 0xFFFFF -#define GDMA_INLINK_ADDR_CH2_S 0 - -#define GDMA_IN_LINK_CH3_REG (DR_REG_GDMA_BASE + 0x0EC) -/* GDMA_INLINK_PARK_CH3 : RO ;bitpos:[24] ;default: 1'h1 ; */ -/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working.*/ -#define GDMA_INLINK_PARK_CH3 (BIT(24)) -#define GDMA_INLINK_PARK_CH3_M (BIT(24)) -#define GDMA_INLINK_PARK_CH3_V 0x1 -#define GDMA_INLINK_PARK_CH3_S 24 -/* GDMA_INLINK_RESTART_CH3 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to mount a new inlink descriptor.*/ -#define GDMA_INLINK_RESTART_CH3 (BIT(23)) -#define GDMA_INLINK_RESTART_CH3_M (BIT(23)) -#define GDMA_INLINK_RESTART_CH3_V 0x1 -#define GDMA_INLINK_RESTART_CH3_S 23 -/* GDMA_INLINK_START_CH3 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the inlink descriptors.*/ -#define GDMA_INLINK_START_CH3 (BIT(22)) -#define GDMA_INLINK_START_CH3_M (BIT(22)) -#define GDMA_INLINK_START_CH3_V 0x1 -#define GDMA_INLINK_START_CH3_S 22 -/* GDMA_INLINK_STOP_CH3 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the inlink descriptors.*/ -#define GDMA_INLINK_STOP_CH3 (BIT(21)) -#define GDMA_INLINK_STOP_CH3_M (BIT(21)) -#define GDMA_INLINK_STOP_CH3_V 0x1 -#define GDMA_INLINK_STOP_CH3_S 21 -/* GDMA_INLINK_AUTO_RET_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data.*/ -#define GDMA_INLINK_AUTO_RET_CH3 (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH3_M (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH3_V 0x1 -#define GDMA_INLINK_AUTO_RET_CH3_S 20 -/* GDMA_INLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - inlink descriptor's address.*/ -#define GDMA_INLINK_ADDR_CH3 0x000FFFFF -#define GDMA_INLINK_ADDR_CH3_M ((GDMA_INLINK_ADDR_CH3_V) << (GDMA_INLINK_ADDR_CH3_S)) -#define GDMA_INLINK_ADDR_CH3_V 0xFFFFF -#define GDMA_INLINK_ADDR_CH3_S 0 - -#define GDMA_IN_LINK_CH4_REG (DR_REG_GDMA_BASE + 0x0F0) -/* GDMA_INLINK_PARK_CH4 : RO ;bitpos:[24] ;default: 1'h1 ; */ -/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working.*/ -#define GDMA_INLINK_PARK_CH4 (BIT(24)) -#define GDMA_INLINK_PARK_CH4_M (BIT(24)) -#define GDMA_INLINK_PARK_CH4_V 0x1 -#define GDMA_INLINK_PARK_CH4_S 24 -/* GDMA_INLINK_RESTART_CH4 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to mount a new inlink descriptor.*/ -#define GDMA_INLINK_RESTART_CH4 (BIT(23)) -#define GDMA_INLINK_RESTART_CH4_M (BIT(23)) -#define GDMA_INLINK_RESTART_CH4_V 0x1 -#define GDMA_INLINK_RESTART_CH4_S 23 -/* GDMA_INLINK_START_CH4 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the inlink descriptors.*/ -#define GDMA_INLINK_START_CH4 (BIT(22)) -#define GDMA_INLINK_START_CH4_M (BIT(22)) -#define GDMA_INLINK_START_CH4_V 0x1 -#define GDMA_INLINK_START_CH4_S 22 -/* GDMA_INLINK_STOP_CH4 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the inlink descriptors.*/ -#define GDMA_INLINK_STOP_CH4 (BIT(21)) -#define GDMA_INLINK_STOP_CH4_M (BIT(21)) -#define GDMA_INLINK_STOP_CH4_V 0x1 -#define GDMA_INLINK_STOP_CH4_S 21 -/* GDMA_INLINK_AUTO_RET_CH4 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data.*/ -#define GDMA_INLINK_AUTO_RET_CH4 (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH4_M (BIT(20)) -#define GDMA_INLINK_AUTO_RET_CH4_V 0x1 -#define GDMA_INLINK_AUTO_RET_CH4_S 20 -/* GDMA_INLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - inlink descriptor's address.*/ -#define GDMA_INLINK_ADDR_CH4 0x000FFFFF -#define GDMA_INLINK_ADDR_CH4_M ((GDMA_INLINK_ADDR_CH4_V) << (GDMA_INLINK_ADDR_CH4_S)) -#define GDMA_INLINK_ADDR_CH4_V 0xFFFFF -#define GDMA_INLINK_ADDR_CH4_S 0 - -#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x0F4) -/* GDMA_IN_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_STATE_CH0 0x00000007 -#define GDMA_IN_STATE_CH0_M ((GDMA_IN_STATE_CH0_V) << (GDMA_IN_STATE_CH0_S)) -#define GDMA_IN_STATE_CH0_V 0x7 -#define GDMA_IN_STATE_CH0_S 20 -/* GDMA_IN_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_DSCR_STATE_CH0 0x00000003 -#define GDMA_IN_DSCR_STATE_CH0_M ((GDMA_IN_DSCR_STATE_CH0_V) << (GDMA_IN_DSCR_STATE_CH0_S)) -#define GDMA_IN_DSCR_STATE_CH0_V 0x3 -#define GDMA_IN_DSCR_STATE_CH0_S 18 -/* GDMA_INLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current inlink descriptor's address.*/ -#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF -#define GDMA_INLINK_DSCR_ADDR_CH0_M ((GDMA_INLINK_DSCR_ADDR_CH0_V) << (GDMA_INLINK_DSCR_ADDR_CH0_S)) -#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x3FFFF -#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 - -#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x0F8) +#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0xE4) /* GDMA_IN_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_STATE_CH1 0x00000007 -#define GDMA_IN_STATE_CH1_M ((GDMA_IN_STATE_CH1_V) << (GDMA_IN_STATE_CH1_S)) -#define GDMA_IN_STATE_CH1_V 0x7 -#define GDMA_IN_STATE_CH1_S 20 +/*description: reserved.*/ +#define GDMA_IN_STATE_CH1 0x00000007 +#define GDMA_IN_STATE_CH1_M ((GDMA_IN_STATE_CH1_V)<<(GDMA_IN_STATE_CH1_S)) +#define GDMA_IN_STATE_CH1_V 0x7 +#define GDMA_IN_STATE_CH1_S 20 /* GDMA_IN_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_DSCR_STATE_CH1 0x00000003 -#define GDMA_IN_DSCR_STATE_CH1_M ((GDMA_IN_DSCR_STATE_CH1_V) << (GDMA_IN_DSCR_STATE_CH1_S)) -#define GDMA_IN_DSCR_STATE_CH1_V 0x3 -#define GDMA_IN_DSCR_STATE_CH1_S 18 +/*description: reserved.*/ +#define GDMA_IN_DSCR_STATE_CH1 0x00000003 +#define GDMA_IN_DSCR_STATE_CH1_M ((GDMA_IN_DSCR_STATE_CH1_V)<<(GDMA_IN_DSCR_STATE_CH1_S)) +#define GDMA_IN_DSCR_STATE_CH1_V 0x3 +#define GDMA_IN_DSCR_STATE_CH1_S 18 /* GDMA_INLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current inlink descriptor's address.*/ -#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF -#define GDMA_INLINK_DSCR_ADDR_CH1_M ((GDMA_INLINK_DSCR_ADDR_CH1_V) << (GDMA_INLINK_DSCR_ADDR_CH1_S)) -#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x3FFFF -#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 +/*description: This register stores the current inlink descriptor's address..*/ +#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF +#define GDMA_INLINK_DSCR_ADDR_CH1_M ((GDMA_INLINK_DSCR_ADDR_CH1_V)<<(GDMA_INLINK_DSCR_ADDR_CH1_S)) +#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x3FFFF +#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 -#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x0FC) -/* GDMA_IN_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_STATE_CH2 0x00000007 -#define GDMA_IN_STATE_CH2_M ((GDMA_IN_STATE_CH2_V) << (GDMA_IN_STATE_CH2_S)) -#define GDMA_IN_STATE_CH2_V 0x7 -#define GDMA_IN_STATE_CH2_S 20 -/* GDMA_IN_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_DSCR_STATE_CH2 0x00000003 -#define GDMA_IN_DSCR_STATE_CH2_M ((GDMA_IN_DSCR_STATE_CH2_V) << (GDMA_IN_DSCR_STATE_CH2_S)) -#define GDMA_IN_DSCR_STATE_CH2_V 0x3 -#define GDMA_IN_DSCR_STATE_CH2_S 18 -/* GDMA_INLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current inlink descriptor's address.*/ -#define GDMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF -#define GDMA_INLINK_DSCR_ADDR_CH2_M ((GDMA_INLINK_DSCR_ADDR_CH2_V) << (GDMA_INLINK_DSCR_ADDR_CH2_S)) -#define GDMA_INLINK_DSCR_ADDR_CH2_V 0x3FFFF -#define GDMA_INLINK_DSCR_ADDR_CH2_S 0 - -#define GDMA_IN_STATE_CH3_REG (DR_REG_GDMA_BASE + 0x100) -/* GDMA_IN_STATE_CH3 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_STATE_CH3 0x00000007 -#define GDMA_IN_STATE_CH3_M ((GDMA_IN_STATE_CH3_V) << (GDMA_IN_STATE_CH3_S)) -#define GDMA_IN_STATE_CH3_V 0x7 -#define GDMA_IN_STATE_CH3_S 20 -/* GDMA_IN_DSCR_STATE_CH3 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_DSCR_STATE_CH3 0x00000003 -#define GDMA_IN_DSCR_STATE_CH3_M ((GDMA_IN_DSCR_STATE_CH3_V) << (GDMA_IN_DSCR_STATE_CH3_S)) -#define GDMA_IN_DSCR_STATE_CH3_V 0x3 -#define GDMA_IN_DSCR_STATE_CH3_S 18 -/* GDMA_INLINK_DSCR_ADDR_CH3 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current inlink descriptor's address.*/ -#define GDMA_INLINK_DSCR_ADDR_CH3 0x0003FFFF -#define GDMA_INLINK_DSCR_ADDR_CH3_M ((GDMA_INLINK_DSCR_ADDR_CH3_V) << (GDMA_INLINK_DSCR_ADDR_CH3_S)) -#define GDMA_INLINK_DSCR_ADDR_CH3_V 0x3FFFF -#define GDMA_INLINK_DSCR_ADDR_CH3_S 0 - -#define GDMA_IN_STATE_CH4_REG (DR_REG_GDMA_BASE + 0x104) -/* GDMA_IN_STATE_CH4 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_STATE_CH4 0x00000007 -#define GDMA_IN_STATE_CH4_M ((GDMA_IN_STATE_CH4_V) << (GDMA_IN_STATE_CH4_S)) -#define GDMA_IN_STATE_CH4_V 0x7 -#define GDMA_IN_STATE_CH4_S 20 -/* GDMA_IN_DSCR_STATE_CH4 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_IN_DSCR_STATE_CH4 0x00000003 -#define GDMA_IN_DSCR_STATE_CH4_M ((GDMA_IN_DSCR_STATE_CH4_V) << (GDMA_IN_DSCR_STATE_CH4_S)) -#define GDMA_IN_DSCR_STATE_CH4_V 0x3 -#define GDMA_IN_DSCR_STATE_CH4_S 18 -/* GDMA_INLINK_DSCR_ADDR_CH4 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current inlink descriptor's address.*/ -#define GDMA_INLINK_DSCR_ADDR_CH4 0x0003FFFF -#define GDMA_INLINK_DSCR_ADDR_CH4_M ((GDMA_INLINK_DSCR_ADDR_CH4_V) << (GDMA_INLINK_DSCR_ADDR_CH4_S)) -#define GDMA_INLINK_DSCR_ADDR_CH4_V 0x3FFFF -#define GDMA_INLINK_DSCR_ADDR_CH4_S 0 - -#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x108) -/* GDMA_OUT_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_STATE_CH0 0x00000007 -#define GDMA_OUT_STATE_CH0_M ((GDMA_OUT_STATE_CH0_V) << (GDMA_OUT_STATE_CH0_S)) -#define GDMA_OUT_STATE_CH0_V 0x7 -#define GDMA_OUT_STATE_CH0_S 20 -/* GDMA_OUT_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_DSCR_STATE_CH0 0x00000003 -#define GDMA_OUT_DSCR_STATE_CH0_M ((GDMA_OUT_DSCR_STATE_CH0_V) << (GDMA_OUT_DSCR_STATE_CH0_S)) -#define GDMA_OUT_DSCR_STATE_CH0_V 0x3 -#define GDMA_OUT_DSCR_STATE_CH0_S 18 -/* GDMA_OUTLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current outlink descriptor's address.*/ -#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH0_M ((GDMA_OUTLINK_DSCR_ADDR_CH0_V) << (GDMA_OUTLINK_DSCR_ADDR_CH0_S)) -#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x3FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 - -#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x10C) -/* GDMA_OUT_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_STATE_CH1 0x00000007 -#define GDMA_OUT_STATE_CH1_M ((GDMA_OUT_STATE_CH1_V) << (GDMA_OUT_STATE_CH1_S)) -#define GDMA_OUT_STATE_CH1_V 0x7 -#define GDMA_OUT_STATE_CH1_S 20 -/* GDMA_OUT_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_DSCR_STATE_CH1 0x00000003 -#define GDMA_OUT_DSCR_STATE_CH1_M ((GDMA_OUT_DSCR_STATE_CH1_V) << (GDMA_OUT_DSCR_STATE_CH1_S)) -#define GDMA_OUT_DSCR_STATE_CH1_V 0x3 -#define GDMA_OUT_DSCR_STATE_CH1_S 18 -/* GDMA_OUTLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current outlink descriptor's address.*/ -#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH1_M ((GDMA_OUTLINK_DSCR_ADDR_CH1_V) << (GDMA_OUTLINK_DSCR_ADDR_CH1_S)) -#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x3FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 - -#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x110) -/* GDMA_OUT_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_STATE_CH2 0x00000007 -#define GDMA_OUT_STATE_CH2_M ((GDMA_OUT_STATE_CH2_V) << (GDMA_OUT_STATE_CH2_S)) -#define GDMA_OUT_STATE_CH2_V 0x7 -#define GDMA_OUT_STATE_CH2_S 20 -/* GDMA_OUT_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_DSCR_STATE_CH2 0x00000003 -#define GDMA_OUT_DSCR_STATE_CH2_M ((GDMA_OUT_DSCR_STATE_CH2_V) << (GDMA_OUT_DSCR_STATE_CH2_S)) -#define GDMA_OUT_DSCR_STATE_CH2_V 0x3 -#define GDMA_OUT_DSCR_STATE_CH2_S 18 -/* GDMA_OUTLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current outlink descriptor's address.*/ -#define GDMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH2_M ((GDMA_OUTLINK_DSCR_ADDR_CH2_V) << (GDMA_OUTLINK_DSCR_ADDR_CH2_S)) -#define GDMA_OUTLINK_DSCR_ADDR_CH2_V 0x3FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH2_S 0 - -#define GDMA_OUT_STATE_CH3_REG (DR_REG_GDMA_BASE + 0x114) -/* GDMA_OUT_STATE_CH3 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_STATE_CH3 0x00000007 -#define GDMA_OUT_STATE_CH3_M ((GDMA_OUT_STATE_CH3_V) << (GDMA_OUT_STATE_CH3_S)) -#define GDMA_OUT_STATE_CH3_V 0x7 -#define GDMA_OUT_STATE_CH3_S 20 -/* GDMA_OUT_DSCR_STATE_CH3 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_DSCR_STATE_CH3 0x00000003 -#define GDMA_OUT_DSCR_STATE_CH3_M ((GDMA_OUT_DSCR_STATE_CH3_V) << (GDMA_OUT_DSCR_STATE_CH3_S)) -#define GDMA_OUT_DSCR_STATE_CH3_V 0x3 -#define GDMA_OUT_DSCR_STATE_CH3_S 18 -/* GDMA_OUTLINK_DSCR_ADDR_CH3 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current outlink descriptor's address.*/ -#define GDMA_OUTLINK_DSCR_ADDR_CH3 0x0003FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH3_M ((GDMA_OUTLINK_DSCR_ADDR_CH3_V) << (GDMA_OUTLINK_DSCR_ADDR_CH3_S)) -#define GDMA_OUTLINK_DSCR_ADDR_CH3_V 0x3FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH3_S 0 - -#define GDMA_OUT_STATE_CH4_REG (DR_REG_GDMA_BASE + 0x118) -/* GDMA_OUT_STATE_CH4 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_STATE_CH4 0x00000007 -#define GDMA_OUT_STATE_CH4_M ((GDMA_OUT_STATE_CH4_V) << (GDMA_OUT_STATE_CH4_S)) -#define GDMA_OUT_STATE_CH4_V 0x7 -#define GDMA_OUT_STATE_CH4_S 20 -/* GDMA_OUT_DSCR_STATE_CH4 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_OUT_DSCR_STATE_CH4 0x00000003 -#define GDMA_OUT_DSCR_STATE_CH4_M ((GDMA_OUT_DSCR_STATE_CH4_V) << (GDMA_OUT_DSCR_STATE_CH4_S)) -#define GDMA_OUT_DSCR_STATE_CH4_V 0x3 -#define GDMA_OUT_DSCR_STATE_CH4_S 18 -/* GDMA_OUTLINK_DSCR_ADDR_CH4 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current outlink descriptor's address.*/ -#define GDMA_OUTLINK_DSCR_ADDR_CH4 0x0003FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH4_M ((GDMA_OUTLINK_DSCR_ADDR_CH4_V) << (GDMA_OUTLINK_DSCR_ADDR_CH4_S)) -#define GDMA_OUTLINK_DSCR_ADDR_CH4_V 0x3FFFF -#define GDMA_OUTLINK_DSCR_ADDR_CH4_S 0 - -#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x11C) -/* GDMA_OUT_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH0_M ((GDMA_OUT_EOF_DES_ADDR_CH0_V) << (GDMA_OUT_EOF_DES_ADDR_CH0_S)) -#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 - -#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x120) -/* GDMA_OUT_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH1_M ((GDMA_OUT_EOF_DES_ADDR_CH1_V) << (GDMA_OUT_EOF_DES_ADDR_CH1_S)) -#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 - -#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x124) -/* GDMA_OUT_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH2_M ((GDMA_OUT_EOF_DES_ADDR_CH2_V) << (GDMA_OUT_EOF_DES_ADDR_CH2_S)) -#define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH2_S 0 - -#define GDMA_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x128) -/* GDMA_OUT_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH3_M ((GDMA_OUT_EOF_DES_ADDR_CH3_V) << (GDMA_OUT_EOF_DES_ADDR_CH3_S)) -#define GDMA_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH3_S 0 - -#define GDMA_OUT_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x12C) -/* GDMA_OUT_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_OUT_EOF_DES_ADDR_CH4 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH4_M ((GDMA_OUT_EOF_DES_ADDR_CH4_V) << (GDMA_OUT_EOF_DES_ADDR_CH4_S)) -#define GDMA_OUT_EOF_DES_ADDR_CH4_V 0xFFFFFFFF -#define GDMA_OUT_EOF_DES_ADDR_CH4_S 0 - -#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x130) -/* GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH0_V) << (GDMA_IN_SUC_EOF_DES_ADDR_CH0_S)) -#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 - -#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x134) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0xE8) /* GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH1_V) << (GDMA_IN_SUC_EOF_DES_ADDR_CH1_S)) -#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 +/*description: This register stores the address of the inlink descriptor when the EOF bit in th +is descriptor is 1..*/ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH1_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH1_S)) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 -#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x138) -/* GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH2_V) << (GDMA_IN_SUC_EOF_DES_ADDR_CH2_S)) -#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 - -#define GDMA_IN_SUC_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x13C) -/* GDMA_IN_SUC_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_IN_SUC_EOF_DES_ADDR_CH3 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH3_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH3_V) << (GDMA_IN_SUC_EOF_DES_ADDR_CH3_S)) -#define GDMA_IN_SUC_EOF_DES_ADDR_CH3_V 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH3_S 0 - -#define GDMA_IN_SUC_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x140) -/* GDMA_IN_SUC_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define GDMA_IN_SUC_EOF_DES_ADDR_CH4 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH4_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH4_V) << (GDMA_IN_SUC_EOF_DES_ADDR_CH4_S)) -#define GDMA_IN_SUC_EOF_DES_ADDR_CH4_V 0xFFFFFFFF -#define GDMA_IN_SUC_EOF_DES_ADDR_CH4_S 0 - -#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x144) -/* GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ -#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH0_V) << (GDMA_IN_ERR_EOF_DES_ADDR_CH0_S)) -#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 - -#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0xEC) /* GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ -#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH1_V) << (GDMA_IN_ERR_EOF_DES_ADDR_CH1_S)) -#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 +/*description: This register stores the address of the inlink descriptor when there are some er +rors in current receiving data. Only used when peripheral is UHCI0..*/ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH1_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH1_S)) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 -#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x14C) -/* GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ -#define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH2_V) << (GDMA_IN_ERR_EOF_DES_ADDR_CH2_S)) -#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 - -#define GDMA_IN_ERR_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x150) -/* GDMA_IN_ERR_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ -#define GDMA_IN_ERR_EOF_DES_ADDR_CH3 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH3_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH3_V) << (GDMA_IN_ERR_EOF_DES_ADDR_CH3_S)) -#define GDMA_IN_ERR_EOF_DES_ADDR_CH3_V 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH3_S 0 - -#define GDMA_IN_ERR_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x154) -/* GDMA_IN_ERR_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ -#define GDMA_IN_ERR_EOF_DES_ADDR_CH4 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH4_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH4_V) << (GDMA_IN_ERR_EOF_DES_ADDR_CH4_S)) -#define GDMA_IN_ERR_EOF_DES_ADDR_CH4_V 0xFFFFFFFF -#define GDMA_IN_ERR_EOF_DES_ADDR_CH4_S 0 - -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x158) -/* GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before - the last outlink descriptor.*/ -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V) << (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S)) -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 - -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x15C) -/* GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before - the last outlink descriptor.*/ -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V) << (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S)) -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 - -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x160) -/* GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before - the last outlink descriptor.*/ -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V) << (GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S)) -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 - -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x164) -/* GDMA_OUT_EOF_BFR_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before - the last outlink descriptor.*/ -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V) << (GDMA_OUT_EOF_BFR_DES_ADDR_CH3_S)) -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_S 0 - -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x168) -/* GDMA_OUT_EOF_BFR_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before - the last outlink descriptor.*/ -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V) << (GDMA_OUT_EOF_BFR_DES_ADDR_CH4_S)) -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V 0xFFFFFFFF -#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_S 0 - -#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x16C) -/* GDMA_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: reserved*/ -#define GDMA_AHB_TESTADDR 0x00000003 -#define GDMA_AHB_TESTADDR_M ((GDMA_AHB_TESTADDR_V) << (GDMA_AHB_TESTADDR_S)) -#define GDMA_AHB_TESTADDR_V 0x3 -#define GDMA_AHB_TESTADDR_S 4 -/* GDMA_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: reserved*/ -#define GDMA_AHB_TESTMODE 0x00000007 -#define GDMA_AHB_TESTMODE_M ((GDMA_AHB_TESTMODE_V) << (GDMA_AHB_TESTMODE_S)) -#define GDMA_AHB_TESTMODE_V 0x7 -#define GDMA_AHB_TESTMODE_S 0 - -#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x170) -/* GDMA_INLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current inlink descriptor x.*/ -#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH0_M ((GDMA_INLINK_DSCR_CH0_V) << (GDMA_INLINK_DSCR_CH0_S)) -#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH0_S 0 - -#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x174) +#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0xF0) /* GDMA_INLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current inlink descriptor x.*/ -#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH1_M ((GDMA_INLINK_DSCR_CH1_V) << (GDMA_INLINK_DSCR_CH1_S)) -#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH1_S 0 +/*description: The address of the current inlink descriptor x..*/ +#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH1_M ((GDMA_INLINK_DSCR_CH1_V)<<(GDMA_INLINK_DSCR_CH1_S)) +#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH1_S 0 -#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x178) -/* GDMA_INLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current inlink descriptor x.*/ -#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH2_M ((GDMA_INLINK_DSCR_CH2_V) << (GDMA_INLINK_DSCR_CH2_S)) -#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH2_S 0 - -#define GDMA_IN_DSCR_CH3_REG (DR_REG_GDMA_BASE + 0x17C) -/* GDMA_INLINK_DSCR_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current inlink descriptor x.*/ -#define GDMA_INLINK_DSCR_CH3 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH3_M ((GDMA_INLINK_DSCR_CH3_V) << (GDMA_INLINK_DSCR_CH3_S)) -#define GDMA_INLINK_DSCR_CH3_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH3_S 0 - -#define GDMA_IN_DSCR_CH4_REG (DR_REG_GDMA_BASE + 0x180) -/* GDMA_INLINK_DSCR_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current inlink descriptor x.*/ -#define GDMA_INLINK_DSCR_CH4 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH4_M ((GDMA_INLINK_DSCR_CH4_V) << (GDMA_INLINK_DSCR_CH4_S)) -#define GDMA_INLINK_DSCR_CH4_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_CH4_S 0 - -#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x184) -/* GDMA_INLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last inlink descriptor x-1.*/ -#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH0_M ((GDMA_INLINK_DSCR_BF0_CH0_V) << (GDMA_INLINK_DSCR_BF0_CH0_S)) -#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH0_S 0 - -#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x188) +#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0xF4) /* GDMA_INLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last inlink descriptor x-1.*/ -#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH1_M ((GDMA_INLINK_DSCR_BF0_CH1_V) << (GDMA_INLINK_DSCR_BF0_CH1_S)) -#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH1_S 0 +/*description: The address of the last inlink descriptor x-1..*/ +#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH1_M ((GDMA_INLINK_DSCR_BF0_CH1_V)<<(GDMA_INLINK_DSCR_BF0_CH1_S)) +#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH1_S 0 -#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x18C) -/* GDMA_INLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last inlink descriptor x-1.*/ -#define GDMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH2_M ((GDMA_INLINK_DSCR_BF0_CH2_V) << (GDMA_INLINK_DSCR_BF0_CH2_S)) -#define GDMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH2_S 0 - -#define GDMA_IN_DSCR_BF0_CH3_REG (DR_REG_GDMA_BASE + 0x190) -/* GDMA_INLINK_DSCR_BF0_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last inlink descriptor x-1.*/ -#define GDMA_INLINK_DSCR_BF0_CH3 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH3_M ((GDMA_INLINK_DSCR_BF0_CH3_V) << (GDMA_INLINK_DSCR_BF0_CH3_S)) -#define GDMA_INLINK_DSCR_BF0_CH3_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH3_S 0 - -#define GDMA_IN_DSCR_BF0_CH4_REG (DR_REG_GDMA_BASE + 0x194) -/* GDMA_INLINK_DSCR_BF0_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last inlink descriptor x-1.*/ -#define GDMA_INLINK_DSCR_BF0_CH4 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH4_M ((GDMA_INLINK_DSCR_BF0_CH4_V) << (GDMA_INLINK_DSCR_BF0_CH4_S)) -#define GDMA_INLINK_DSCR_BF0_CH4_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF0_CH4_S 0 - -#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x198) -/* GDMA_INLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH0_M ((GDMA_INLINK_DSCR_BF1_CH0_V) << (GDMA_INLINK_DSCR_BF1_CH0_S)) -#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH0_S 0 - -#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x19C) +#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0xF8) /* GDMA_INLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH1_M ((GDMA_INLINK_DSCR_BF1_CH1_V) << (GDMA_INLINK_DSCR_BF1_CH1_S)) -#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH1_S 0 +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH1_M ((GDMA_INLINK_DSCR_BF1_CH1_V)<<(GDMA_INLINK_DSCR_BF1_CH1_S)) +#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH1_S 0 -#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x1A0) -/* GDMA_INLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH2_M ((GDMA_INLINK_DSCR_BF1_CH2_V) << (GDMA_INLINK_DSCR_BF1_CH2_S)) -#define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH2_S 0 +#define GDMA_IN_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0xFC) +/* GDMA_RX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Rx channel 1. .*/ +#define GDMA_RX_WEIGHT_CH1 0x0000000F +#define GDMA_RX_WEIGHT_CH1_M ((GDMA_RX_WEIGHT_CH1_V)<<(GDMA_RX_WEIGHT_CH1_S)) +#define GDMA_RX_WEIGHT_CH1_V 0xF +#define GDMA_RX_WEIGHT_CH1_S 8 -#define GDMA_IN_DSCR_BF1_CH3_REG (DR_REG_GDMA_BASE + 0x1A4) -/* GDMA_INLINK_DSCR_BF1_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_INLINK_DSCR_BF1_CH3 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH3_M ((GDMA_INLINK_DSCR_BF1_CH3_V) << (GDMA_INLINK_DSCR_BF1_CH3_S)) -#define GDMA_INLINK_DSCR_BF1_CH3_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH3_S 0 +#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x104) +/* GDMA_RX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 1. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_RX_PRI_CH1 0x0000000F +#define GDMA_RX_PRI_CH1_M ((GDMA_RX_PRI_CH1_V)<<(GDMA_RX_PRI_CH1_S)) +#define GDMA_RX_PRI_CH1_V 0xF +#define GDMA_RX_PRI_CH1_S 0 -#define GDMA_IN_DSCR_BF1_CH4_REG (DR_REG_GDMA_BASE + 0x1A8) -/* GDMA_INLINK_DSCR_BF1_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_INLINK_DSCR_BF1_CH4 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH4_M ((GDMA_INLINK_DSCR_BF1_CH4_V) << (GDMA_INLINK_DSCR_BF1_CH4_S)) -#define GDMA_INLINK_DSCR_BF1_CH4_V 0xFFFFFFFF -#define GDMA_INLINK_DSCR_BF1_CH4_S 0 +#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x108) +/* GDMA_PERI_IN_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_IN_SEL_CH1 0x0000003F +#define GDMA_PERI_IN_SEL_CH1_M ((GDMA_PERI_IN_SEL_CH1_V)<<(GDMA_PERI_IN_SEL_CH1_S)) +#define GDMA_PERI_IN_SEL_CH1_V 0x3F +#define GDMA_PERI_IN_SEL_CH1_S 0 -#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x1AC) -/* GDMA_OUTLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current outlink descriptor y.*/ -#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH0_M ((GDMA_OUTLINK_DSCR_CH0_V) << (GDMA_OUTLINK_DSCR_CH0_S)) -#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH0_S 0 +#define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x120) +/* GDMA_OUT_DATA_BURST_EN_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting da +ta when accessing internal SRAM. .*/ +#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH1_M (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x1 +#define GDMA_OUT_DATA_BURST_EN_CH1_S 5 +/* GDMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_M (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x1 +#define GDMA_OUTDSCR_BURST_EN_CH1_S 4 +/* GDMA_OUT_EOF_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + generated when data need to transmit has been popped from FIFO in DMA.*/ +#define GDMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_M (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_V 0x1 +#define GDMA_OUT_EOF_MODE_CH1_S 3 +/* GDMA_OUT_AUTO_WRBACK_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe +r has been transmitted..*/ +#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_M (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x1 +#define GDMA_OUT_AUTO_WRBACK_CH1_S 2 +/* GDMA_OUT_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_M (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_V 0x1 +#define GDMA_OUT_LOOP_TEST_CH1_S 1 +/* GDMA_OUT_RST_CH1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer..*/ +#define GDMA_OUT_RST_CH1 (BIT(0)) +#define GDMA_OUT_RST_CH1_M (BIT(0)) +#define GDMA_OUT_RST_CH1_V 0x1 +#define GDMA_OUT_RST_CH1_S 0 -#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1B0) +#define GDMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x124) +/* GDMA_OUT_EXT_MEM_BK_SIZE_CH1 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 1 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH1 0x00000003 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH1_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH1_V)<<(GDMA_OUT_EXT_MEM_BK_SIZE_CH1_S)) +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH1_V 0x3 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH1_S 13 +/* GDMA_OUT_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_M (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_V 0x1 +#define GDMA_OUT_CHECK_OWNER_CH1_S 12 + +#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x128) +/* GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 1 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_RAW_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 1 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_RAW_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S 4 +/* GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc +ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +nnel 1..*/ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/* GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +r, including owner error, the second and third word error of outlink descriptor +for Tx channel 1..*/ +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/* GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been read from memory for Tx channel 1. .*/ +#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_M (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x1 +#define GDMA_OUT_EOF_CH1_INT_RAW_S 1 +/* GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been transmitted to peripherals for Tx channel 1..*/ +#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_M (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x1 +#define GDMA_OUT_DONE_CH1_INT_RAW_S 0 + +#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x12C) +/* GDMA_OUTFIFO_UDF_L3_CH1_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ST_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ST (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ST_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ST_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ST_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ST_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH1_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ST_S 4 +/* GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/* GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/* GDMA_OUT_EOF_CH1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_M (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_V 0x1 +#define GDMA_OUT_EOF_CH1_INT_ST_S 1 +/* GDMA_OUT_DONE_CH1_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_M (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_V 0x1 +#define GDMA_OUT_DONE_CH1_INT_ST_S 0 + +#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x130) +/* GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_ENA_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_ENA_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_ENA_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_ENA_S 4 +/* GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/* GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/* GDMA_OUT_EOF_CH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_M (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x1 +#define GDMA_OUT_EOF_CH1_INT_ENA_S 1 +/* GDMA_OUT_DONE_CH1_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_M (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x1 +#define GDMA_OUT_DONE_CH1_INT_ENA_S 0 + +#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x134) +/* GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH1_INT_CLR_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH1_INT_CLR_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH1_INT_CLR_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S 4 +/* GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/* GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/* GDMA_OUT_EOF_CH1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_M (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x1 +#define GDMA_OUT_EOF_CH1_INT_CLR_S 1 +/* GDMA_OUT_DONE_CH1_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_M (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x1 +#define GDMA_OUT_DONE_CH1_INT_CLR_S 0 + +#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) +/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH1 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH1 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH1_M (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH1_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH1_S 26 +/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH1 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH1 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH1_M (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH1_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH1_S 25 +/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH1 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_M (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH1_S 24 +/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH1 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH1 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH1_M (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH1_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH1_S 23 +/* GDMA_OUTFIFO_CNT_L3_CH1 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 1..*/ +#define GDMA_OUTFIFO_CNT_L3_CH1 0x0000001F +#define GDMA_OUTFIFO_CNT_L3_CH1_M ((GDMA_OUTFIFO_CNT_L3_CH1_V)<<(GDMA_OUTFIFO_CNT_L3_CH1_S)) +#define GDMA_OUTFIFO_CNT_L3_CH1_V 0x1F +#define GDMA_OUTFIFO_CNT_L3_CH1_S 18 +/* GDMA_OUTFIFO_CNT_L2_CH1 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 1..*/ +#define GDMA_OUTFIFO_CNT_L2_CH1 0x0000007F +#define GDMA_OUTFIFO_CNT_L2_CH1_M ((GDMA_OUTFIFO_CNT_L2_CH1_V)<<(GDMA_OUTFIFO_CNT_L2_CH1_S)) +#define GDMA_OUTFIFO_CNT_L2_CH1_V 0x7F +#define GDMA_OUTFIFO_CNT_L2_CH1_S 11 +/* GDMA_OUTFIFO_CNT_L1_CH1 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1..*/ +#define GDMA_OUTFIFO_CNT_L1_CH1 0x0000001F +#define GDMA_OUTFIFO_CNT_L1_CH1_M ((GDMA_OUTFIFO_CNT_L1_CH1_V)<<(GDMA_OUTFIFO_CNT_L1_CH1_S)) +#define GDMA_OUTFIFO_CNT_L1_CH1_V 0x1F +#define GDMA_OUTFIFO_CNT_L1_CH1_S 6 +/* GDMA_OUTFIFO_EMPTY_L3_CH1 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 1..*/ +#define GDMA_OUTFIFO_EMPTY_L3_CH1 (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH1_M (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH1_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L3_CH1_S 5 +/* GDMA_OUTFIFO_FULL_L3_CH1 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 1..*/ +#define GDMA_OUTFIFO_FULL_L3_CH1 (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH1_M (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH1_V 0x1 +#define GDMA_OUTFIFO_FULL_L3_CH1_S 4 +/* GDMA_OUTFIFO_EMPTY_L2_CH1 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 1..*/ +#define GDMA_OUTFIFO_EMPTY_L2_CH1 (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH1_M (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH1_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L2_CH1_S 3 +/* GDMA_OUTFIFO_FULL_L2_CH1 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 1..*/ +#define GDMA_OUTFIFO_FULL_L2_CH1 (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH1_M (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH1_V 0x1 +#define GDMA_OUTFIFO_FULL_L2_CH1_S 2 +/* GDMA_OUTFIFO_EMPTY_L1_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 1..*/ +#define GDMA_OUTFIFO_EMPTY_L1_CH1 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH1_M (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH1_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L1_CH1_S 1 +/* GDMA_OUTFIFO_FULL_L1_CH1 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 1..*/ +#define GDMA_OUTFIFO_FULL_L1_CH1 (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH1_M (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH1_V 0x1 +#define GDMA_OUTFIFO_FULL_L1_CH1_S 0 + +#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x13C) +/* GDMA_OUTFIFO_PUSH_CH1 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO..*/ +#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_M (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_V 0x1 +#define GDMA_OUTFIFO_PUSH_CH1_S 9 +/* GDMA_OUTFIFO_WDATA_CH1 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO..*/ +#define GDMA_OUTFIFO_WDATA_CH1 0x000001FF +#define GDMA_OUTFIFO_WDATA_CH1_M ((GDMA_OUTFIFO_WDATA_CH1_V)<<(GDMA_OUTFIFO_WDATA_CH1_S)) +#define GDMA_OUTFIFO_WDATA_CH1_V 0x1FF +#define GDMA_OUTFIFO_WDATA_CH1_S 0 + +#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) +/* GDMA_OUTLINK_PARK_CH1 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F +SM is working..*/ +#define GDMA_OUTLINK_PARK_CH1 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH1_M (BIT(23)) +#define GDMA_OUTLINK_PARK_CH1_V 0x1 +#define GDMA_OUTLINK_PARK_CH1_S 23 +/* GDMA_OUTLINK_RESTART_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address. .*/ +#define GDMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH1_M (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH1_V 0x1 +#define GDMA_OUTLINK_RESTART_CH1_S 22 +/* GDMA_OUTLINK_START_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_START_CH1 (BIT(21)) +#define GDMA_OUTLINK_START_CH1_M (BIT(21)) +#define GDMA_OUTLINK_START_CH1_V 0x1 +#define GDMA_OUTLINK_START_CH1_S 21 +/* GDMA_OUTLINK_STOP_CH1 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_STOP_CH1 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH1_M (BIT(20)) +#define GDMA_OUTLINK_STOP_CH1_V 0x1 +#define GDMA_OUTLINK_STOP_CH1_S 20 +/* GDMA_OUTLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first outlink descript +or's address..*/ +#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFF +#define GDMA_OUTLINK_ADDR_CH1_M ((GDMA_OUTLINK_ADDR_CH1_V)<<(GDMA_OUTLINK_ADDR_CH1_S)) +#define GDMA_OUTLINK_ADDR_CH1_V 0xFFFFF +#define GDMA_OUTLINK_ADDR_CH1_S 0 + +#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) +/* GDMA_OUT_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_STATE_CH1 0x00000007 +#define GDMA_OUT_STATE_CH1_M ((GDMA_OUT_STATE_CH1_V)<<(GDMA_OUT_STATE_CH1_S)) +#define GDMA_OUT_STATE_CH1_V 0x7 +#define GDMA_OUT_STATE_CH1_S 20 +/* GDMA_OUT_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_DSCR_STATE_CH1 0x00000003 +#define GDMA_OUT_DSCR_STATE_CH1_M ((GDMA_OUT_DSCR_STATE_CH1_V)<<(GDMA_OUT_DSCR_STATE_CH1_S)) +#define GDMA_OUT_DSCR_STATE_CH1_V 0x3 +#define GDMA_OUT_DSCR_STATE_CH1_S 18 +/* GDMA_OUTLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address..*/ +#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH1_M ((GDMA_OUTLINK_DSCR_ADDR_CH1_V)<<(GDMA_OUTLINK_DSCR_ADDR_CH1_S)) +#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x3FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 + +#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +/* GDMA_OUT_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when the EOF bit in t +his descriptor is 1..*/ +#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH1_M ((GDMA_OUT_EOF_DES_ADDR_CH1_V)<<(GDMA_OUT_EOF_DES_ADDR_CH1_S)) +#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 + +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14C) +/* GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before the last outli +nk descriptor..*/ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S)) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) /* GDMA_OUTLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current outlink descriptor y.*/ -#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH1_M ((GDMA_OUTLINK_DSCR_CH1_V) << (GDMA_OUTLINK_DSCR_CH1_S)) -#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH1_S 0 +/*description: The address of the current outlink descriptor y..*/ +#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH1_M ((GDMA_OUTLINK_DSCR_CH1_V)<<(GDMA_OUTLINK_DSCR_CH1_S)) +#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH1_S 0 -#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x1B4) -/* GDMA_OUTLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current outlink descriptor y.*/ -#define GDMA_OUTLINK_DSCR_CH2 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH2_M ((GDMA_OUTLINK_DSCR_CH2_V) << (GDMA_OUTLINK_DSCR_CH2_S)) -#define GDMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH2_S 0 - -#define GDMA_OUT_DSCR_CH3_REG (DR_REG_GDMA_BASE + 0x1B8) -/* GDMA_OUTLINK_DSCR_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current outlink descriptor y.*/ -#define GDMA_OUTLINK_DSCR_CH3 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH3_M ((GDMA_OUTLINK_DSCR_CH3_V) << (GDMA_OUTLINK_DSCR_CH3_S)) -#define GDMA_OUTLINK_DSCR_CH3_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH3_S 0 - -#define GDMA_OUT_DSCR_CH4_REG (DR_REG_GDMA_BASE + 0x1BC) -/* GDMA_OUTLINK_DSCR_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current outlink descriptor y.*/ -#define GDMA_OUTLINK_DSCR_CH4 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH4_M ((GDMA_OUTLINK_DSCR_CH4_V) << (GDMA_OUTLINK_DSCR_CH4_S)) -#define GDMA_OUTLINK_DSCR_CH4_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_CH4_S 0 - -#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x1C0) -/* GDMA_OUTLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last outlink descriptor y-1.*/ -#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH0_M ((GDMA_OUTLINK_DSCR_BF0_CH0_V) << (GDMA_OUTLINK_DSCR_BF0_CH0_S)) -#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 - -#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1C4) +#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) /* GDMA_OUTLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last outlink descriptor y-1.*/ -#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH1_M ((GDMA_OUTLINK_DSCR_BF0_CH1_V) << (GDMA_OUTLINK_DSCR_BF0_CH1_S)) -#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 +/*description: The address of the last outlink descriptor y-1..*/ +#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH1_M ((GDMA_OUTLINK_DSCR_BF0_CH1_V)<<(GDMA_OUTLINK_DSCR_BF0_CH1_S)) +#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 -#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x1C8) -/* GDMA_OUTLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last outlink descriptor y-1.*/ -#define GDMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH2_M ((GDMA_OUTLINK_DSCR_BF0_CH2_V) << (GDMA_OUTLINK_DSCR_BF0_CH2_S)) -#define GDMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH2_S 0 - -#define GDMA_OUT_DSCR_BF0_CH3_REG (DR_REG_GDMA_BASE + 0x1CC) -/* GDMA_OUTLINK_DSCR_BF0_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last outlink descriptor y-1.*/ -#define GDMA_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH3_M ((GDMA_OUTLINK_DSCR_BF0_CH3_V) << (GDMA_OUTLINK_DSCR_BF0_CH3_S)) -#define GDMA_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH3_S 0 - -#define GDMA_OUT_DSCR_BF0_CH4_REG (DR_REG_GDMA_BASE + 0x1D0) -/* GDMA_OUTLINK_DSCR_BF0_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last outlink descriptor y-1.*/ -#define GDMA_OUTLINK_DSCR_BF0_CH4 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH4_M ((GDMA_OUTLINK_DSCR_BF0_CH4_V) << (GDMA_OUTLINK_DSCR_BF0_CH4_S)) -#define GDMA_OUTLINK_DSCR_BF0_CH4_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF0_CH4_S 0 - -#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x1D4) -/* GDMA_OUTLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH0_M ((GDMA_OUTLINK_DSCR_BF1_CH0_V) << (GDMA_OUTLINK_DSCR_BF1_CH0_S)) -#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 - -#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1D8) +#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) /* GDMA_OUTLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH1_M ((GDMA_OUTLINK_DSCR_BF1_CH1_V) << (GDMA_OUTLINK_DSCR_BF1_CH1_S)) -#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH1_M ((GDMA_OUTLINK_DSCR_BF1_CH1_V)<<(GDMA_OUTLINK_DSCR_BF1_CH1_S)) +#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 -#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x1DC) -/* GDMA_OUTLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH2_M ((GDMA_OUTLINK_DSCR_BF1_CH2_V) << (GDMA_OUTLINK_DSCR_BF1_CH2_S)) -#define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 +#define GDMA_OUT_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x15C) +/* GDMA_TX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Tx channel 1. .*/ +#define GDMA_TX_WEIGHT_CH1 0x0000000F +#define GDMA_TX_WEIGHT_CH1_M ((GDMA_TX_WEIGHT_CH1_V)<<(GDMA_TX_WEIGHT_CH1_S)) +#define GDMA_TX_WEIGHT_CH1_V 0xF +#define GDMA_TX_WEIGHT_CH1_S 8 -#define GDMA_OUT_DSCR_BF1_CH3_REG (DR_REG_GDMA_BASE + 0x1E0) -/* GDMA_OUTLINK_DSCR_BF1_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH3_M ((GDMA_OUTLINK_DSCR_BF1_CH3_V) << (GDMA_OUTLINK_DSCR_BF1_CH3_S)) -#define GDMA_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH3_S 0 - -#define GDMA_OUT_DSCR_BF1_CH4_REG (DR_REG_GDMA_BASE + 0x1E4) -/* GDMA_OUTLINK_DSCR_BF1_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define GDMA_OUTLINK_DSCR_BF1_CH4 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH4_M ((GDMA_OUTLINK_DSCR_BF1_CH4_V) << (GDMA_OUTLINK_DSCR_BF1_CH4_S)) -#define GDMA_OUTLINK_DSCR_BF1_CH4_V 0xFFFFFFFF -#define GDMA_OUTLINK_DSCR_BF1_CH4_S 0 - -#define GDMA_PD_CONF_REG (DR_REG_GDMA_BASE + 0x1E8) -/* GDMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: Force to open the clock and bypass the gate-clock when accessing - the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/ -#define GDMA_RAM_CLK_FO (BIT(6)) -#define GDMA_RAM_CLK_FO_M (BIT(6)) -#define GDMA_RAM_CLK_FO_V 0x1 -#define GDMA_RAM_CLK_FO_S 6 -/* GDMA_RAM_FORCE_PU : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define GDMA_RAM_FORCE_PU (BIT(5)) -#define GDMA_RAM_FORCE_PU_M (BIT(5)) -#define GDMA_RAM_FORCE_PU_V 0x1 -#define GDMA_RAM_FORCE_PU_S 5 -/* GDMA_RAM_FORCE_PD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: power down*/ -#define GDMA_RAM_FORCE_PD (BIT(4)) -#define GDMA_RAM_FORCE_PD_M (BIT(4)) -#define GDMA_RAM_FORCE_PD_V 0x1 -#define GDMA_RAM_FORCE_PD_S 4 - -#define GDMA_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x1EC) -/* GDMA_RX_WEIGHT_CH0 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ -/*description: The weight of Rx channel 0.*/ -#define GDMA_RX_WEIGHT_CH0 0x0000000F -#define GDMA_RX_WEIGHT_CH0_M ((GDMA_RX_WEIGHT_CH0_V) << (GDMA_RX_WEIGHT_CH0_S)) -#define GDMA_RX_WEIGHT_CH0_V 0xF -#define GDMA_RX_WEIGHT_CH0_S 4 -/* GDMA_TX_WEIGHT_CH0 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ -/*description: The weight of Tx channel 0.*/ -#define GDMA_TX_WEIGHT_CH0 0x0000000F -#define GDMA_TX_WEIGHT_CH0_M ((GDMA_TX_WEIGHT_CH0_V) << (GDMA_TX_WEIGHT_CH0_S)) -#define GDMA_TX_WEIGHT_CH0_V 0xF -#define GDMA_TX_WEIGHT_CH0_S 0 - -#define GDMA_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x1F0) -/* GDMA_RX_WEIGHT_CH1 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ -/*description: The weight of Rx channel 1.*/ -#define GDMA_RX_WEIGHT_CH1 0x0000000F -#define GDMA_RX_WEIGHT_CH1_M ((GDMA_RX_WEIGHT_CH1_V) << (GDMA_RX_WEIGHT_CH1_S)) -#define GDMA_RX_WEIGHT_CH1_V 0xF -#define GDMA_RX_WEIGHT_CH1_S 4 -/* GDMA_TX_WEIGHT_CH1 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ -/*description: The weight of Tx channel 1.*/ -#define GDMA_TX_WEIGHT_CH1 0x0000000F -#define GDMA_TX_WEIGHT_CH1_M ((GDMA_TX_WEIGHT_CH1_V) << (GDMA_TX_WEIGHT_CH1_S)) -#define GDMA_TX_WEIGHT_CH1_V 0xF -#define GDMA_TX_WEIGHT_CH1_S 0 - -#define GDMA_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x1F4) -/* GDMA_RX_WEIGHT_CH2 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ -/*description: The weight of Rx channel 2.*/ -#define GDMA_RX_WEIGHT_CH2 0x0000000F -#define GDMA_RX_WEIGHT_CH2_M ((GDMA_RX_WEIGHT_CH2_V) << (GDMA_RX_WEIGHT_CH2_S)) -#define GDMA_RX_WEIGHT_CH2_V 0xF -#define GDMA_RX_WEIGHT_CH2_S 4 -/* GDMA_TX_WEIGHT_CH2 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ -/*description: The weight of Tx channel 2.*/ -#define GDMA_TX_WEIGHT_CH2 0x0000000F -#define GDMA_TX_WEIGHT_CH2_M ((GDMA_TX_WEIGHT_CH2_V) << (GDMA_TX_WEIGHT_CH2_S)) -#define GDMA_TX_WEIGHT_CH2_V 0xF -#define GDMA_TX_WEIGHT_CH2_S 0 - -#define GDMA_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x1F8) -/* GDMA_RX_WEIGHT_CH3 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ -/*description: The weight of Rx channel 3.*/ -#define GDMA_RX_WEIGHT_CH3 0x0000000F -#define GDMA_RX_WEIGHT_CH3_M ((GDMA_RX_WEIGHT_CH3_V) << (GDMA_RX_WEIGHT_CH3_S)) -#define GDMA_RX_WEIGHT_CH3_V 0xF -#define GDMA_RX_WEIGHT_CH3_S 4 -/* GDMA_TX_WEIGHT_CH3 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ -/*description: The weight of Tx channel 3.*/ -#define GDMA_TX_WEIGHT_CH3 0x0000000F -#define GDMA_TX_WEIGHT_CH3_M ((GDMA_TX_WEIGHT_CH3_V) << (GDMA_TX_WEIGHT_CH3_S)) -#define GDMA_TX_WEIGHT_CH3_V 0xF -#define GDMA_TX_WEIGHT_CH3_S 0 - -#define GDMA_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x1FC) -/* GDMA_RX_WEIGHT_CH4 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ -/*description: The weight of Rx channel 4.*/ -#define GDMA_RX_WEIGHT_CH4 0x0000000F -#define GDMA_RX_WEIGHT_CH4_M ((GDMA_RX_WEIGHT_CH4_V) << (GDMA_RX_WEIGHT_CH4_S)) -#define GDMA_RX_WEIGHT_CH4_V 0xF -#define GDMA_RX_WEIGHT_CH4_S 4 -/* GDMA_TX_WEIGHT_CH4 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ -/*description: The weight of Tx channel 4.*/ -#define GDMA_TX_WEIGHT_CH4 0x0000000F -#define GDMA_TX_WEIGHT_CH4_M ((GDMA_TX_WEIGHT_CH4_V) << (GDMA_TX_WEIGHT_CH4_S)) -#define GDMA_TX_WEIGHT_CH4_V 0xF -#define GDMA_TX_WEIGHT_CH4_S 0 - -#define GDMA_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x200) -/* GDMA_RX_PRI_CH0 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 0. The larger of the value the higher - of the priority.*/ -#define GDMA_RX_PRI_CH0 0x0000000F -#define GDMA_RX_PRI_CH0_M ((GDMA_RX_PRI_CH0_V) << (GDMA_RX_PRI_CH0_S)) -#define GDMA_RX_PRI_CH0_V 0xF -#define GDMA_RX_PRI_CH0_S 4 -/* GDMA_TX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 0. The larger of the value the higher - of the priority.*/ -#define GDMA_TX_PRI_CH0 0x0000000F -#define GDMA_TX_PRI_CH0_M ((GDMA_TX_PRI_CH0_V) << (GDMA_TX_PRI_CH0_S)) -#define GDMA_TX_PRI_CH0_V 0xF -#define GDMA_TX_PRI_CH0_S 0 - -#define GDMA_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x204) -/* GDMA_RX_PRI_CH1 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 1. The larger of the value the higher - of the priority.*/ -#define GDMA_RX_PRI_CH1 0x0000000F -#define GDMA_RX_PRI_CH1_M ((GDMA_RX_PRI_CH1_V) << (GDMA_RX_PRI_CH1_S)) -#define GDMA_RX_PRI_CH1_V 0xF -#define GDMA_RX_PRI_CH1_S 4 +#define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x164) /* GDMA_TX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 1. The larger of the value the higher - of the priority.*/ -#define GDMA_TX_PRI_CH1 0x0000000F -#define GDMA_TX_PRI_CH1_M ((GDMA_TX_PRI_CH1_V) << (GDMA_TX_PRI_CH1_S)) -#define GDMA_TX_PRI_CH1_V 0xF -#define GDMA_TX_PRI_CH1_S 0 +/*description: The priority of Tx channel 1. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_TX_PRI_CH1 0x0000000F +#define GDMA_TX_PRI_CH1_M ((GDMA_TX_PRI_CH1_V)<<(GDMA_TX_PRI_CH1_S)) +#define GDMA_TX_PRI_CH1_V 0xF +#define GDMA_TX_PRI_CH1_S 0 -#define GDMA_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x208) -/* GDMA_RX_PRI_CH2 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 2. The larger of the value the higher - of the priority.*/ -#define GDMA_RX_PRI_CH2 0x0000000F -#define GDMA_RX_PRI_CH2_M ((GDMA_RX_PRI_CH2_V) << (GDMA_RX_PRI_CH2_S)) -#define GDMA_RX_PRI_CH2_V 0xF -#define GDMA_RX_PRI_CH2_S 4 +#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x168) +/* GDMA_PERI_OUT_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_OUT_SEL_CH1 0x0000003F +#define GDMA_PERI_OUT_SEL_CH1_M ((GDMA_PERI_OUT_SEL_CH1_V)<<(GDMA_PERI_OUT_SEL_CH1_S)) +#define GDMA_PERI_OUT_SEL_CH1_V 0x3F +#define GDMA_PERI_OUT_SEL_CH1_S 0 + +#define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x180) +/* GDMA_MEM_TRANS_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D +MA..*/ +#define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH2_M (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH2_V 0x1 +#define GDMA_MEM_TRANS_EN_CH2_S 4 +/* GDMA_IN_DATA_BURST_EN_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data +when accessing internal SRAM. .*/ +#define GDMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH2_M (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH2_V 0x1 +#define GDMA_IN_DATA_BURST_EN_CH2_S 3 +/* GDMA_INDSCR_BURST_EN_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH2_M (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH2_V 0x1 +#define GDMA_INDSCR_BURST_EN_CH2_S 2 +/* GDMA_IN_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH2_M (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH2_V 0x1 +#define GDMA_IN_LOOP_TEST_CH2_S 1 +/* GDMA_IN_RST_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer..*/ +#define GDMA_IN_RST_CH2 (BIT(0)) +#define GDMA_IN_RST_CH2_M (BIT(0)) +#define GDMA_IN_RST_CH2_V 0x1 +#define GDMA_IN_RST_CH2_S 0 + +#define GDMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x184) +/* GDMA_IN_EXT_MEM_BK_SIZE_CH2 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 2 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_IN_EXT_MEM_BK_SIZE_CH2 0x00000003 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH2_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH2_V)<<(GDMA_IN_EXT_MEM_BK_SIZE_CH2_S)) +#define GDMA_IN_EXT_MEM_BK_SIZE_CH2_V 0x3 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH2_S 13 +/* GDMA_IN_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH2_M (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH2_V 0x1 +#define GDMA_IN_CHECK_OWNER_CH2_S 12 +/* GDMA_DMA_INFIFO_FULL_THRS_CH2 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann +el 2 received byte number in Rx FIFO is up to the value of the register..*/ +#define GDMA_DMA_INFIFO_FULL_THRS_CH2 0x00000FFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH2_M ((GDMA_DMA_INFIFO_FULL_THRS_CH2_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH2_S)) +#define GDMA_DMA_INFIFO_FULL_THRS_CH2_V 0xFFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH2_S 0 + +#define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x188) +/* GDMA_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 2 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH2_INT_RAW_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH2_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH2_INT_RAW_S 9 +/* GDMA_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 2 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH2_INT_RAW_S 8 +/* GDMA_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L1_CH2_INT_RAW (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH2_INT_RAW_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH2_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH2_INT_RAW_S 7 +/* GDMA_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L1_CH2_INT_RAW (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_S 6 +/* GDMA_INFIFO_FULL_WM_CH2_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data byte number is up t +o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 2..*/ +#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_S 5 +/* GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu +ll and receiving data is not completed, but there is no more inlink for Rx chann +el 2..*/ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 +/* GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink descriptor error +, including owner error, the second and third word error of inlink descriptor fo +r Rx channel 2..*/ +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/* GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is detected only in th +e case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, thi +s raw interrupt is reserved..*/ +#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x1 +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/* GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt b +it turns to high level when the last data pointed by one inlink descriptor has b +een received and no data error is detected for Rx channel 0..*/ +#define GDMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V 0x1 +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/* GDMA_IN_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 2..*/ +#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_RAW_M (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_RAW_V 0x1 +#define GDMA_IN_DONE_CH2_INT_RAW_S 0 + +#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x18C) +/* GDMA_INFIFO_UDF_L3_CH2_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH2_INT_ST (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH2_INT_ST_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH2_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH2_INT_ST_S 9 +/* GDMA_INFIFO_OVF_L3_CH2_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH2_INT_ST (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH2_INT_ST_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH2_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH2_INT_ST_S 8 +/* GDMA_INFIFO_UDF_L1_CH2_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH2_INT_ST (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH2_INT_ST_S 7 +/* GDMA_INFIFO_OVF_L1_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH2_INT_ST (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH2_INT_ST_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH2_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH2_INT_ST_S 6 +/* GDMA_INFIFO_FULL_WM_CH2_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH2_INT_ST (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH2_INT_ST_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH2_INT_ST_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH2_INT_ST_S 5 +/* GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 +/* GDMA_IN_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V 0x1 +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S 3 +/* GDMA_IN_ERR_EOF_CH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_V 0x1 +#define GDMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/* GDMA_IN_SUC_EOF_CH2_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x1 +#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/* GDMA_IN_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ST_M (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ST_V 0x1 +#define GDMA_IN_DONE_CH2_INT_ST_S 0 + +#define GDMA_IN_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x190) +/* GDMA_INFIFO_UDF_L3_CH2_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH2_INT_ENA_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH2_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH2_INT_ENA_S 9 +/* GDMA_INFIFO_OVF_L3_CH2_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH2_INT_ENA_S 8 +/* GDMA_INFIFO_UDF_L1_CH2_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH2_INT_ENA (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH2_INT_ENA_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH2_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH2_INT_ENA_S 7 +/* GDMA_INFIFO_OVF_L1_CH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH2_INT_ENA (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH2_INT_ENA_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH2_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH2_INT_ENA_S 6 +/* GDMA_INFIFO_FULL_WM_CH2_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH2_INT_ENA_S 5 +/* GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 +/* GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/* GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x1 +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/* GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V 0x1 +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/* GDMA_IN_DONE_CH2_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ENA_M (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ENA_V 0x1 +#define GDMA_IN_DONE_CH2_INT_ENA_S 0 + +#define GDMA_IN_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x194) +/* GDMA_INFIFO_UDF_L3_CH2_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH2_INT_CLR_S 9 +/* GDMA_INFIFO_OVF_L3_CH2_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH2_INT_CLR_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH2_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH2_INT_CLR_S 8 +/* GDMA_INFIFO_UDF_L1_CH2_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH2_INT_CLR (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH2_INT_CLR_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH2_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH2_INT_CLR_S 7 +/* GDMA_INFIFO_OVF_L1_CH2_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH2_INT_CLR_S 6 +/* GDMA_DMA_INFIFO_FULL_WM_CH2_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_DMA_INFIFO_FULL_WM_CH2_INT_CLR (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH2_INT_CLR_M (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH2_INT_CLR_V 0x1 +#define GDMA_DMA_INFIFO_FULL_WM_CH2_INT_CLR_S 5 +/* GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 +/* GDMA_IN_DSCR_ERR_CH2_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/* GDMA_IN_ERR_EOF_CH2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V 0x1 +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/* GDMA_IN_SUC_EOF_CH2_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V 0x1 +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/* GDMA_IN_DONE_CH2_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_CLR_M (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_CLR_V 0x1 +#define GDMA_IN_DONE_CH2_INT_CLR_S 0 + +#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x198) +/* GDMA_IN_BUF_HUNGRY_CH2 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH2_M (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH2_V 0x1 +#define GDMA_IN_BUF_HUNGRY_CH2_S 28 +/* GDMA_IN_REMAIN_UNDER_4B_L3_CH2 : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2 (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2_M (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2_V 0x1 +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH2_S 27 +/* GDMA_IN_REMAIN_UNDER_3B_L3_CH2 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH2 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH2_M (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH2_V 0x1 +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH2_S 26 +/* GDMA_IN_REMAIN_UNDER_2B_L3_CH2 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH2 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH2_M (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH2_V 0x1 +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH2_S 25 +/* GDMA_IN_REMAIN_UNDER_1B_L3_CH2 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_M (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_V 0x1 +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH2_S 24 +/* GDMA_INFIFO_CNT_L3_CH2 : RO ;bitpos:[23:19] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 2..*/ +#define GDMA_INFIFO_CNT_L3_CH2 0x0000001F +#define GDMA_INFIFO_CNT_L3_CH2_M ((GDMA_INFIFO_CNT_L3_CH2_V)<<(GDMA_INFIFO_CNT_L3_CH2_S)) +#define GDMA_INFIFO_CNT_L3_CH2_V 0x1F +#define GDMA_INFIFO_CNT_L3_CH2_S 19 +/* GDMA_INFIFO_CNT_L2_CH2 : RO ;bitpos:[18:12] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 2..*/ +#define GDMA_INFIFO_CNT_L2_CH2 0x0000007F +#define GDMA_INFIFO_CNT_L2_CH2_M ((GDMA_INFIFO_CNT_L2_CH2_V)<<(GDMA_INFIFO_CNT_L2_CH2_S)) +#define GDMA_INFIFO_CNT_L2_CH2_V 0x7F +#define GDMA_INFIFO_CNT_L2_CH2_S 12 +/* GDMA_INFIFO_CNT_L1_CH2 : RO ;bitpos:[11:6] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2..*/ +#define GDMA_INFIFO_CNT_L1_CH2 0x0000003F +#define GDMA_INFIFO_CNT_L1_CH2_M ((GDMA_INFIFO_CNT_L1_CH2_V)<<(GDMA_INFIFO_CNT_L1_CH2_S)) +#define GDMA_INFIFO_CNT_L1_CH2_V 0x3F +#define GDMA_INFIFO_CNT_L1_CH2_S 6 +/* GDMA_INFIFO_EMPTY_L3_CH2 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 2..*/ +#define GDMA_INFIFO_EMPTY_L3_CH2 (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH2_M (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH2_V 0x1 +#define GDMA_INFIFO_EMPTY_L3_CH2_S 5 +/* GDMA_INFIFO_FULL_L3_CH2 : RO ;bitpos:[4] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 2..*/ +#define GDMA_INFIFO_FULL_L3_CH2 (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH2_M (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH2_V 0x1 +#define GDMA_INFIFO_FULL_L3_CH2_S 4 +/* GDMA_INFIFO_EMPTY_L2_CH2 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 2..*/ +#define GDMA_INFIFO_EMPTY_L2_CH2 (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH2_M (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH2_V 0x1 +#define GDMA_INFIFO_EMPTY_L2_CH2_S 3 +/* GDMA_INFIFO_FULL_L2_CH2 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 2..*/ +#define GDMA_INFIFO_FULL_L2_CH2 (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH2_M (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH2_V 0x1 +#define GDMA_INFIFO_FULL_L2_CH2_S 2 +/* GDMA_INFIFO_EMPTY_L1_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 2..*/ +#define GDMA_INFIFO_EMPTY_L1_CH2 (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH2_M (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH2_V 0x1 +#define GDMA_INFIFO_EMPTY_L1_CH2_S 1 +/* GDMA_INFIFO_FULL_L1_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 2..*/ +#define GDMA_INFIFO_FULL_L1_CH2 (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH2_M (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH2_V 0x1 +#define GDMA_INFIFO_FULL_L1_CH2_S 0 + +#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x19C) +/* GDMA_INFIFO_POP_CH2 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO..*/ +#define GDMA_INFIFO_POP_CH2 (BIT(12)) +#define GDMA_INFIFO_POP_CH2_M (BIT(12)) +#define GDMA_INFIFO_POP_CH2_V 0x1 +#define GDMA_INFIFO_POP_CH2_S 12 +/* GDMA_INFIFO_RDATA_CH2 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: This register stores the data popping from DMA FIFO..*/ +#define GDMA_INFIFO_RDATA_CH2 0x00000FFF +#define GDMA_INFIFO_RDATA_CH2_M ((GDMA_INFIFO_RDATA_CH2_V)<<(GDMA_INFIFO_RDATA_CH2_S)) +#define GDMA_INFIFO_RDATA_CH2_V 0xFFF +#define GDMA_INFIFO_RDATA_CH2_S 0 + +#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x1A0) +/* GDMA_INLINK_PARK_CH2 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM + is working..*/ +#define GDMA_INLINK_PARK_CH2 (BIT(24)) +#define GDMA_INLINK_PARK_CH2_M (BIT(24)) +#define GDMA_INLINK_PARK_CH2_V 0x1 +#define GDMA_INLINK_PARK_CH2_S 24 +/* GDMA_INLINK_RESTART_CH2 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor..*/ +#define GDMA_INLINK_RESTART_CH2 (BIT(23)) +#define GDMA_INLINK_RESTART_CH2_M (BIT(23)) +#define GDMA_INLINK_RESTART_CH2_V 0x1 +#define GDMA_INLINK_RESTART_CH2_S 23 +/* GDMA_INLINK_START_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors..*/ +#define GDMA_INLINK_START_CH2 (BIT(22)) +#define GDMA_INLINK_START_CH2_M (BIT(22)) +#define GDMA_INLINK_START_CH2_V 0x1 +#define GDMA_INLINK_START_CH2_S 22 +/* GDMA_INLINK_STOP_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors..*/ +#define GDMA_INLINK_STOP_CH2 (BIT(21)) +#define GDMA_INLINK_STOP_CH2_M (BIT(21)) +#define GDMA_INLINK_STOP_CH2_V 0x1 +#define GDMA_INLINK_STOP_CH2_S 21 +/* GDMA_INLINK_AUTO_RET_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address, when there are so +me errors in current receiving data..*/ +#define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH2_M (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH2_V 0x1 +#define GDMA_INLINK_AUTO_RET_CH2_S 20 +/* GDMA_INLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first inlink descripto +r's address..*/ +#define GDMA_INLINK_ADDR_CH2 0x000FFFFF +#define GDMA_INLINK_ADDR_CH2_M ((GDMA_INLINK_ADDR_CH2_V)<<(GDMA_INLINK_ADDR_CH2_S)) +#define GDMA_INLINK_ADDR_CH2_V 0xFFFFF +#define GDMA_INLINK_ADDR_CH2_S 0 + +#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x1A4) +/* GDMA_IN_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_STATE_CH2 0x00000007 +#define GDMA_IN_STATE_CH2_M ((GDMA_IN_STATE_CH2_V)<<(GDMA_IN_STATE_CH2_S)) +#define GDMA_IN_STATE_CH2_V 0x7 +#define GDMA_IN_STATE_CH2_S 20 +/* GDMA_IN_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_DSCR_STATE_CH2 0x00000003 +#define GDMA_IN_DSCR_STATE_CH2_M ((GDMA_IN_DSCR_STATE_CH2_V)<<(GDMA_IN_DSCR_STATE_CH2_S)) +#define GDMA_IN_DSCR_STATE_CH2_V 0x3 +#define GDMA_IN_DSCR_STATE_CH2_S 18 +/* GDMA_INLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address..*/ +#define GDMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF +#define GDMA_INLINK_DSCR_ADDR_CH2_M ((GDMA_INLINK_DSCR_ADDR_CH2_V)<<(GDMA_INLINK_DSCR_ADDR_CH2_S)) +#define GDMA_INLINK_DSCR_ADDR_CH2_V 0x3FFFF +#define GDMA_INLINK_DSCR_ADDR_CH2_S 0 + +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x1A8) +/* GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when the EOF bit in th +is descriptor is 1..*/ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH2_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH2_S)) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x1AC) +/* GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when there are some er +rors in current receiving data. Only used when peripheral is UHCI0..*/ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH2_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH2_S)) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x1B0) +/* GDMA_INLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x..*/ +#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH2_M ((GDMA_INLINK_DSCR_CH2_V)<<(GDMA_INLINK_DSCR_CH2_S)) +#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH2_S 0 + +#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x1B4) +/* GDMA_INLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1..*/ +#define GDMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH2_M ((GDMA_INLINK_DSCR_BF0_CH2_V)<<(GDMA_INLINK_DSCR_BF0_CH2_S)) +#define GDMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH2_S 0 + +#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x1B8) +/* GDMA_INLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH2_M ((GDMA_INLINK_DSCR_BF1_CH2_V)<<(GDMA_INLINK_DSCR_BF1_CH2_S)) +#define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH2_S 0 + +#define GDMA_IN_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x1BC) +/* GDMA_RX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Rx channel 2. .*/ +#define GDMA_RX_WEIGHT_CH2 0x0000000F +#define GDMA_RX_WEIGHT_CH2_M ((GDMA_RX_WEIGHT_CH2_V)<<(GDMA_RX_WEIGHT_CH2_S)) +#define GDMA_RX_WEIGHT_CH2_V 0xF +#define GDMA_RX_WEIGHT_CH2_S 8 + +#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x1C4) +/* GDMA_RX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 2. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_RX_PRI_CH2 0x0000000F +#define GDMA_RX_PRI_CH2_M ((GDMA_RX_PRI_CH2_V)<<(GDMA_RX_PRI_CH2_S)) +#define GDMA_RX_PRI_CH2_V 0xF +#define GDMA_RX_PRI_CH2_S 0 + +#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x1C8) +/* GDMA_PERI_IN_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_IN_SEL_CH2 0x0000003F +#define GDMA_PERI_IN_SEL_CH2_M ((GDMA_PERI_IN_SEL_CH2_V)<<(GDMA_PERI_IN_SEL_CH2_S)) +#define GDMA_PERI_IN_SEL_CH2_V 0x3F +#define GDMA_PERI_IN_SEL_CH2_S 0 + +#define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1E0) +/* GDMA_OUT_DATA_BURST_EN_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting da +ta when accessing internal SRAM. .*/ +#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH2_M (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x1 +#define GDMA_OUT_DATA_BURST_EN_CH2_S 5 +/* GDMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH2_M (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH2_V 0x1 +#define GDMA_OUTDSCR_BURST_EN_CH2_S 4 +/* GDMA_OUT_EOF_MODE_CH2 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + generated when data need to transmit has been popped from FIFO in DMA.*/ +#define GDMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH2_M (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH2_V 0x1 +#define GDMA_OUT_EOF_MODE_CH2_S 3 +/* GDMA_OUT_AUTO_WRBACK_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe +r has been transmitted..*/ +#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH2_M (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x1 +#define GDMA_OUT_AUTO_WRBACK_CH2_S 2 +/* GDMA_OUT_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH2_M (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH2_V 0x1 +#define GDMA_OUT_LOOP_TEST_CH2_S 1 +/* GDMA_OUT_RST_CH2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer..*/ +#define GDMA_OUT_RST_CH2 (BIT(0)) +#define GDMA_OUT_RST_CH2_M (BIT(0)) +#define GDMA_OUT_RST_CH2_V 0x1 +#define GDMA_OUT_RST_CH2_S 0 + +#define GDMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1E4) +/* GDMA_OUT_EXT_MEM_BK_SIZE_CH2 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 2 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH2 0x00000003 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH2_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH2_V)<<(GDMA_OUT_EXT_MEM_BK_SIZE_CH2_S)) +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH2_V 0x3 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH2_S 13 +/* GDMA_OUT_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH2_M (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH2_V 0x1 +#define GDMA_OUT_CHECK_OWNER_CH2_S 12 + +#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x1E8) +/* GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 2 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_RAW_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 2 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_RAW_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S 4 +/* GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc +ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +nnel 2..*/ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 +/* GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +r, including owner error, the second and third word error of outlink descriptor +for Tx channel 2..*/ +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 +/* GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been read from memory for Tx channel 2. .*/ +#define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_RAW_M (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_RAW_V 0x1 +#define GDMA_OUT_EOF_CH2_INT_RAW_S 1 +/* GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been transmitted to peripherals for Tx channel 2..*/ +#define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_RAW_M (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_RAW_V 0x1 +#define GDMA_OUT_DONE_CH2_INT_RAW_S 0 + +#define GDMA_OUT_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x1EC) +/* GDMA_OUTFIFO_UDF_L3_CH2_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ST_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ST (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ST_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ST_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH2_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ST_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ST_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ST_S 4 +/* GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 +/* GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 +/* GDMA_OUT_EOF_CH2_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ST_M (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ST_V 0x1 +#define GDMA_OUT_EOF_CH2_INT_ST_S 1 +/* GDMA_OUT_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ST_M (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ST_V 0x1 +#define GDMA_OUT_DONE_CH2_INT_ST_S 0 + +#define GDMA_OUT_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x1F0) +/* GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_ENA_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_ENA_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_ENA_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_ENA_S 4 +/* GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 +/* GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 +/* GDMA_OUT_EOF_CH2_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ENA_M (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ENA_V 0x1 +#define GDMA_OUT_EOF_CH2_INT_ENA_S 1 +/* GDMA_OUT_DONE_CH2_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ENA_M (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ENA_V 0x1 +#define GDMA_OUT_DONE_CH2_INT_ENA_S 0 + +#define GDMA_OUT_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x1F4) +/* GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH2_INT_CLR_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH2_INT_CLR_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH2_INT_CLR_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S 4 +/* GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 +/* GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 +/* GDMA_OUT_EOF_CH2_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_CLR_M (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x1 +#define GDMA_OUT_EOF_CH2_INT_CLR_S 1 +/* GDMA_OUT_DONE_CH2_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_CLR_M (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_CLR_V 0x1 +#define GDMA_OUT_DONE_CH2_INT_CLR_S 0 + +#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1F8) +/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH2 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH2 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH2_M (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH2_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH2_S 26 +/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH2 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH2 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH2_M (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH2_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH2_S 25 +/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH2 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_M (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH2_S 24 +/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH2 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH2 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH2_M (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH2_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH2_S 23 +/* GDMA_OUTFIFO_CNT_L3_CH2 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 2..*/ +#define GDMA_OUTFIFO_CNT_L3_CH2 0x0000001F +#define GDMA_OUTFIFO_CNT_L3_CH2_M ((GDMA_OUTFIFO_CNT_L3_CH2_V)<<(GDMA_OUTFIFO_CNT_L3_CH2_S)) +#define GDMA_OUTFIFO_CNT_L3_CH2_V 0x1F +#define GDMA_OUTFIFO_CNT_L3_CH2_S 18 +/* GDMA_OUTFIFO_CNT_L2_CH2 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 2..*/ +#define GDMA_OUTFIFO_CNT_L2_CH2 0x0000007F +#define GDMA_OUTFIFO_CNT_L2_CH2_M ((GDMA_OUTFIFO_CNT_L2_CH2_V)<<(GDMA_OUTFIFO_CNT_L2_CH2_S)) +#define GDMA_OUTFIFO_CNT_L2_CH2_V 0x7F +#define GDMA_OUTFIFO_CNT_L2_CH2_S 11 +/* GDMA_OUTFIFO_CNT_L1_CH2 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2..*/ +#define GDMA_OUTFIFO_CNT_L1_CH2 0x0000001F +#define GDMA_OUTFIFO_CNT_L1_CH2_M ((GDMA_OUTFIFO_CNT_L1_CH2_V)<<(GDMA_OUTFIFO_CNT_L1_CH2_S)) +#define GDMA_OUTFIFO_CNT_L1_CH2_V 0x1F +#define GDMA_OUTFIFO_CNT_L1_CH2_S 6 +/* GDMA_OUTFIFO_EMPTY_L3_CH2 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 2..*/ +#define GDMA_OUTFIFO_EMPTY_L3_CH2 (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH2_M (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH2_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L3_CH2_S 5 +/* GDMA_OUTFIFO_FULL_L3_CH2 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 2..*/ +#define GDMA_OUTFIFO_FULL_L3_CH2 (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH2_M (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH2_V 0x1 +#define GDMA_OUTFIFO_FULL_L3_CH2_S 4 +/* GDMA_OUTFIFO_EMPTY_L2_CH2 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 2..*/ +#define GDMA_OUTFIFO_EMPTY_L2_CH2 (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH2_M (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH2_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L2_CH2_S 3 +/* GDMA_OUTFIFO_FULL_L2_CH2 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 2..*/ +#define GDMA_OUTFIFO_FULL_L2_CH2 (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH2_M (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH2_V 0x1 +#define GDMA_OUTFIFO_FULL_L2_CH2_S 2 +/* GDMA_OUTFIFO_EMPTY_L1_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 2..*/ +#define GDMA_OUTFIFO_EMPTY_L1_CH2 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH2_M (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH2_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L1_CH2_S 1 +/* GDMA_OUTFIFO_FULL_L1_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 2..*/ +#define GDMA_OUTFIFO_FULL_L1_CH2 (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH2_M (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH2_V 0x1 +#define GDMA_OUTFIFO_FULL_L1_CH2_S 0 + +#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x1FC) +/* GDMA_OUTFIFO_PUSH_CH2 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO..*/ +#define GDMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH2_M (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH2_V 0x1 +#define GDMA_OUTFIFO_PUSH_CH2_S 9 +/* GDMA_OUTFIFO_WDATA_CH2 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO..*/ +#define GDMA_OUTFIFO_WDATA_CH2 0x000001FF +#define GDMA_OUTFIFO_WDATA_CH2_M ((GDMA_OUTFIFO_WDATA_CH2_V)<<(GDMA_OUTFIFO_WDATA_CH2_S)) +#define GDMA_OUTFIFO_WDATA_CH2_V 0x1FF +#define GDMA_OUTFIFO_WDATA_CH2_S 0 + +#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) +/* GDMA_OUTLINK_PARK_CH2 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F +SM is working..*/ +#define GDMA_OUTLINK_PARK_CH2 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH2_M (BIT(23)) +#define GDMA_OUTLINK_PARK_CH2_V 0x1 +#define GDMA_OUTLINK_PARK_CH2_S 23 +/* GDMA_OUTLINK_RESTART_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address. .*/ +#define GDMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH2_M (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH2_V 0x1 +#define GDMA_OUTLINK_RESTART_CH2_S 22 +/* GDMA_OUTLINK_START_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_START_CH2 (BIT(21)) +#define GDMA_OUTLINK_START_CH2_M (BIT(21)) +#define GDMA_OUTLINK_START_CH2_V 0x1 +#define GDMA_OUTLINK_START_CH2_S 21 +/* GDMA_OUTLINK_STOP_CH2 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_STOP_CH2 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH2_M (BIT(20)) +#define GDMA_OUTLINK_STOP_CH2_V 0x1 +#define GDMA_OUTLINK_STOP_CH2_S 20 +/* GDMA_OUTLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first outlink descript +or's address..*/ +#define GDMA_OUTLINK_ADDR_CH2 0x000FFFFF +#define GDMA_OUTLINK_ADDR_CH2_M ((GDMA_OUTLINK_ADDR_CH2_V)<<(GDMA_OUTLINK_ADDR_CH2_S)) +#define GDMA_OUTLINK_ADDR_CH2_V 0xFFFFF +#define GDMA_OUTLINK_ADDR_CH2_S 0 + +#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) +/* GDMA_OUT_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_STATE_CH2 0x00000007 +#define GDMA_OUT_STATE_CH2_M ((GDMA_OUT_STATE_CH2_V)<<(GDMA_OUT_STATE_CH2_S)) +#define GDMA_OUT_STATE_CH2_V 0x7 +#define GDMA_OUT_STATE_CH2_S 20 +/* GDMA_OUT_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_DSCR_STATE_CH2 0x00000003 +#define GDMA_OUT_DSCR_STATE_CH2_M ((GDMA_OUT_DSCR_STATE_CH2_V)<<(GDMA_OUT_DSCR_STATE_CH2_S)) +#define GDMA_OUT_DSCR_STATE_CH2_V 0x3 +#define GDMA_OUT_DSCR_STATE_CH2_S 18 +/* GDMA_OUTLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address..*/ +#define GDMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH2_M ((GDMA_OUTLINK_DSCR_ADDR_CH2_V)<<(GDMA_OUTLINK_DSCR_ADDR_CH2_S)) +#define GDMA_OUTLINK_DSCR_ADDR_CH2_V 0x3FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH2_S 0 + +#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) +/* GDMA_OUT_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when the EOF bit in t +his descriptor is 1..*/ +#define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH2_M ((GDMA_OUT_EOF_DES_ADDR_CH2_V)<<(GDMA_OUT_EOF_DES_ADDR_CH2_S)) +#define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH2_S 0 + +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20C) +/* GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before the last outli +nk descriptor..*/ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S)) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) +/* GDMA_OUTLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y..*/ +#define GDMA_OUTLINK_DSCR_CH2 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH2_M ((GDMA_OUTLINK_DSCR_CH2_V)<<(GDMA_OUTLINK_DSCR_CH2_S)) +#define GDMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH2_S 0 + +#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) +/* GDMA_OUTLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1..*/ +#define GDMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH2_M ((GDMA_OUTLINK_DSCR_BF0_CH2_V)<<(GDMA_OUTLINK_DSCR_BF0_CH2_S)) +#define GDMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH2_S 0 + +#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) +/* GDMA_OUTLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH2_M ((GDMA_OUTLINK_DSCR_BF1_CH2_V)<<(GDMA_OUTLINK_DSCR_BF1_CH2_S)) +#define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 + +#define GDMA_OUT_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x21C) +/* GDMA_TX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Tx channel 2. .*/ +#define GDMA_TX_WEIGHT_CH2 0x0000000F +#define GDMA_TX_WEIGHT_CH2_M ((GDMA_TX_WEIGHT_CH2_V)<<(GDMA_TX_WEIGHT_CH2_S)) +#define GDMA_TX_WEIGHT_CH2_V 0xF +#define GDMA_TX_WEIGHT_CH2_S 8 + +#define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x224) /* GDMA_TX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 2. The larger of the value the higher - of the priority.*/ -#define GDMA_TX_PRI_CH2 0x0000000F -#define GDMA_TX_PRI_CH2_M ((GDMA_TX_PRI_CH2_V) << (GDMA_TX_PRI_CH2_S)) -#define GDMA_TX_PRI_CH2_V 0xF -#define GDMA_TX_PRI_CH2_S 0 +/*description: The priority of Tx channel 2. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_TX_PRI_CH2 0x0000000F +#define GDMA_TX_PRI_CH2_M ((GDMA_TX_PRI_CH2_V)<<(GDMA_TX_PRI_CH2_S)) +#define GDMA_TX_PRI_CH2_V 0xF +#define GDMA_TX_PRI_CH2_S 0 -#define GDMA_PRI_CH3_REG (DR_REG_GDMA_BASE + 0x20C) -/* GDMA_RX_PRI_CH3 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 3. The larger of the value the higher - of the priority.*/ -#define GDMA_RX_PRI_CH3 0x0000000F -#define GDMA_RX_PRI_CH3_M ((GDMA_RX_PRI_CH3_V) << (GDMA_RX_PRI_CH3_S)) -#define GDMA_RX_PRI_CH3_V 0xF -#define GDMA_RX_PRI_CH3_S 4 +#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x228) +/* GDMA_PERI_OUT_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_OUT_SEL_CH2 0x0000003F +#define GDMA_PERI_OUT_SEL_CH2_M ((GDMA_PERI_OUT_SEL_CH2_V)<<(GDMA_PERI_OUT_SEL_CH2_S)) +#define GDMA_PERI_OUT_SEL_CH2_V 0x3F +#define GDMA_PERI_OUT_SEL_CH2_S 0 + +#define GDMA_IN_CONF0_CH3_REG (DR_REG_GDMA_BASE + 0x240) +/* GDMA_MEM_TRANS_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D +MA..*/ +#define GDMA_MEM_TRANS_EN_CH3 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH3_M (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH3_V 0x1 +#define GDMA_MEM_TRANS_EN_CH3_S 4 +/* GDMA_IN_DATA_BURST_EN_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data +when accessing internal SRAM. .*/ +#define GDMA_IN_DATA_BURST_EN_CH3 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH3_M (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH3_V 0x1 +#define GDMA_IN_DATA_BURST_EN_CH3_S 3 +/* GDMA_INDSCR_BURST_EN_CH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_INDSCR_BURST_EN_CH3 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH3_M (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH3_V 0x1 +#define GDMA_INDSCR_BURST_EN_CH3_S 2 +/* GDMA_IN_LOOP_TEST_CH3 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_LOOP_TEST_CH3 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH3_M (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH3_V 0x1 +#define GDMA_IN_LOOP_TEST_CH3_S 1 +/* GDMA_IN_RST_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 3 Rx FSM and Rx FIFO pointer..*/ +#define GDMA_IN_RST_CH3 (BIT(0)) +#define GDMA_IN_RST_CH3_M (BIT(0)) +#define GDMA_IN_RST_CH3_V 0x1 +#define GDMA_IN_RST_CH3_S 0 + +#define GDMA_IN_CONF1_CH3_REG (DR_REG_GDMA_BASE + 0x244) +/* GDMA_IN_EXT_MEM_BK_SIZE_CH3 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 3 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_IN_EXT_MEM_BK_SIZE_CH3 0x00000003 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH3_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH3_V)<<(GDMA_IN_EXT_MEM_BK_SIZE_CH3_S)) +#define GDMA_IN_EXT_MEM_BK_SIZE_CH3_V 0x3 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH3_S 13 +/* GDMA_IN_CHECK_OWNER_CH3 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_IN_CHECK_OWNER_CH3 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH3_M (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH3_V 0x1 +#define GDMA_IN_CHECK_OWNER_CH3_S 12 +/* GDMA_DMA_INFIFO_FULL_THRS_CH3 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann +el 3 received byte number in Rx FIFO is up to the value of the register..*/ +#define GDMA_DMA_INFIFO_FULL_THRS_CH3 0x00000FFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH3_M ((GDMA_DMA_INFIFO_FULL_THRS_CH3_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH3_S)) +#define GDMA_DMA_INFIFO_FULL_THRS_CH3_V 0xFFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH3_S 0 + +#define GDMA_IN_INT_RAW_CH3_REG (DR_REG_GDMA_BASE + 0x248) +/* GDMA_INFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 3 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L3_CH3_INT_RAW (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH3_INT_RAW_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH3_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH3_INT_RAW_S 9 +/* GDMA_INFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 3 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L3_CH3_INT_RAW (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH3_INT_RAW_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH3_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH3_INT_RAW_S 8 +/* GDMA_INFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 3 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L1_CH3_INT_RAW (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH3_INT_RAW_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH3_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH3_INT_RAW_S 7 +/* GDMA_INFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 3 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L1_CH3_INT_RAW (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_S 6 +/* GDMA_INFIFO_FULL_WM_CH3_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data byte number is up t +o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 3..*/ +#define GDMA_INFIFO_FULL_WM_CH3_INT_RAW (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_S 5 +/* GDMA_IN_DSCR_EMPTY_CH3_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu +ll and receiving data is not completed, but there is no more inlink for Rx chann +el 3..*/ +#define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_S 4 +/* GDMA_IN_DSCR_ERR_CH3_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink descriptor error +, including owner error, the second and third word error of inlink descriptor fo +r Rx channel 3..*/ +#define GDMA_IN_DSCR_ERR_CH3_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH3_INT_RAW_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH3_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_ERR_CH3_INT_RAW_S 3 +/* GDMA_IN_ERR_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is detected only in th +e case that the peripheral is UHCI0 for Rx channel 3. For other peripherals, thi +s raw interrupt is reserved..*/ +#define GDMA_IN_ERR_EOF_CH3_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH3_INT_RAW_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH3_INT_RAW_V 0x1 +#define GDMA_IN_ERR_EOF_CH3_INT_RAW_S 2 +/* GDMA_IN_SUC_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 3. For UHCI0, the raw interrupt b +it turns to high level when the last data pointed by one inlink descriptor has b +een received and no data error is detected for Rx channel 0..*/ +#define GDMA_IN_SUC_EOF_CH3_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH3_INT_RAW_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH3_INT_RAW_V 0x1 +#define GDMA_IN_SUC_EOF_CH3_INT_RAW_S 1 +/* GDMA_IN_DONE_CH3_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 3..*/ +#define GDMA_IN_DONE_CH3_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH3_INT_RAW_M (BIT(0)) +#define GDMA_IN_DONE_CH3_INT_RAW_V 0x1 +#define GDMA_IN_DONE_CH3_INT_RAW_S 0 + +#define GDMA_IN_INT_ST_CH3_REG (DR_REG_GDMA_BASE + 0x24C) +/* GDMA_INFIFO_UDF_L3_CH3_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH3_INT_ST (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH3_INT_ST_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH3_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH3_INT_ST_S 9 +/* GDMA_INFIFO_OVF_L3_CH3_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH3_INT_ST (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH3_INT_ST_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH3_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH3_INT_ST_S 8 +/* GDMA_INFIFO_UDF_L1_CH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH3_INT_ST (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH3_INT_ST_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH3_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH3_INT_ST_S 7 +/* GDMA_INFIFO_OVF_L1_CH3_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH3_INT_ST (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH3_INT_ST_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH3_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH3_INT_ST_S 6 +/* GDMA_INFIFO_FULL_WM_CH3_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH3_INT_ST (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH3_INT_ST_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH3_INT_ST_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH3_INT_ST_S 5 +/* GDMA_IN_DSCR_EMPTY_CH3_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH3_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH3_INT_ST_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH3_INT_ST_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH3_INT_ST_S 4 +/* GDMA_IN_DSCR_ERR_CH3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH3_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH3_INT_ST_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH3_INT_ST_V 0x1 +#define GDMA_IN_DSCR_ERR_CH3_INT_ST_S 3 +/* GDMA_IN_ERR_EOF_CH3_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH3_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH3_INT_ST_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH3_INT_ST_V 0x1 +#define GDMA_IN_ERR_EOF_CH3_INT_ST_S 2 +/* GDMA_IN_SUC_EOF_CH3_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH3_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH3_INT_ST_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH3_INT_ST_V 0x1 +#define GDMA_IN_SUC_EOF_CH3_INT_ST_S 1 +/* GDMA_IN_DONE_CH3_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH3_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH3_INT_ST_M (BIT(0)) +#define GDMA_IN_DONE_CH3_INT_ST_V 0x1 +#define GDMA_IN_DONE_CH3_INT_ST_S 0 + +#define GDMA_IN_INT_ENA_CH3_REG (DR_REG_GDMA_BASE + 0x250) +/* GDMA_INFIFO_UDF_L3_CH3_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH3_INT_ENA (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH3_INT_ENA_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH3_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH3_INT_ENA_S 9 +/* GDMA_INFIFO_OVF_L3_CH3_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH3_INT_ENA (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH3_INT_ENA_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH3_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH3_INT_ENA_S 8 +/* GDMA_INFIFO_UDF_L1_CH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH3_INT_ENA (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH3_INT_ENA_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH3_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH3_INT_ENA_S 7 +/* GDMA_INFIFO_OVF_L1_CH3_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH3_INT_ENA (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH3_INT_ENA_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH3_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH3_INT_ENA_S 6 +/* GDMA_INFIFO_FULL_WM_CH3_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH3_INT_ENA (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH3_INT_ENA_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH3_INT_ENA_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH3_INT_ENA_S 5 +/* GDMA_IN_DSCR_EMPTY_CH3_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH3_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH3_INT_ENA_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH3_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH3_INT_ENA_S 4 +/* GDMA_IN_DSCR_ERR_CH3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH3_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH3_INT_ENA_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH3_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_ERR_CH3_INT_ENA_S 3 +/* GDMA_IN_ERR_EOF_CH3_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH3_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH3_INT_ENA_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH3_INT_ENA_V 0x1 +#define GDMA_IN_ERR_EOF_CH3_INT_ENA_S 2 +/* GDMA_IN_SUC_EOF_CH3_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH3_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH3_INT_ENA_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH3_INT_ENA_V 0x1 +#define GDMA_IN_SUC_EOF_CH3_INT_ENA_S 1 +/* GDMA_IN_DONE_CH3_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH3_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH3_INT_ENA_M (BIT(0)) +#define GDMA_IN_DONE_CH3_INT_ENA_V 0x1 +#define GDMA_IN_DONE_CH3_INT_ENA_S 0 + +#define GDMA_IN_INT_CLR_CH3_REG (DR_REG_GDMA_BASE + 0x254) +/* GDMA_INFIFO_UDF_L3_CH3_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH3_INT_CLR (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH3_INT_CLR_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH3_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH3_INT_CLR_S 9 +/* GDMA_INFIFO_OVF_L3_CH3_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH3_INT_CLR (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH3_INT_CLR_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH3_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH3_INT_CLR_S 8 +/* GDMA_INFIFO_UDF_L1_CH3_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH3_INT_CLR (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH3_INT_CLR_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH3_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH3_INT_CLR_S 7 +/* GDMA_INFIFO_OVF_L1_CH3_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH3_INT_CLR (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH3_INT_CLR_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH3_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH3_INT_CLR_S 6 +/* GDMA_DMA_INFIFO_FULL_WM_CH3_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_DMA_INFIFO_FULL_WM_CH3_INT_CLR (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH3_INT_CLR_M (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH3_INT_CLR_V 0x1 +#define GDMA_DMA_INFIFO_FULL_WM_CH3_INT_CLR_S 5 +/* GDMA_IN_DSCR_EMPTY_CH3_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH3_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH3_INT_CLR_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH3_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH3_INT_CLR_S 4 +/* GDMA_IN_DSCR_ERR_CH3_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH3_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH3_INT_CLR_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH3_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_ERR_CH3_INT_CLR_S 3 +/* GDMA_IN_ERR_EOF_CH3_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH3_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH3_INT_CLR_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH3_INT_CLR_V 0x1 +#define GDMA_IN_ERR_EOF_CH3_INT_CLR_S 2 +/* GDMA_IN_SUC_EOF_CH3_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH3_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH3_INT_CLR_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH3_INT_CLR_V 0x1 +#define GDMA_IN_SUC_EOF_CH3_INT_CLR_S 1 +/* GDMA_IN_DONE_CH3_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH3_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH3_INT_CLR_M (BIT(0)) +#define GDMA_IN_DONE_CH3_INT_CLR_V 0x1 +#define GDMA_IN_DONE_CH3_INT_CLR_S 0 + +#define GDMA_INFIFO_STATUS_CH3_REG (DR_REG_GDMA_BASE + 0x258) +/* GDMA_IN_BUF_HUNGRY_CH3 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_BUF_HUNGRY_CH3 (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH3_M (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH3_V 0x1 +#define GDMA_IN_BUF_HUNGRY_CH3_S 28 +/* GDMA_IN_REMAIN_UNDER_4B_L3_CH3 : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH3 (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH3_M (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH3_V 0x1 +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH3_S 27 +/* GDMA_IN_REMAIN_UNDER_3B_L3_CH3 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH3 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH3_M (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH3_V 0x1 +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH3_S 26 +/* GDMA_IN_REMAIN_UNDER_2B_L3_CH3 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH3 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH3_M (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH3_V 0x1 +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH3_S 25 +/* GDMA_IN_REMAIN_UNDER_1B_L3_CH3 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH3 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH3_M (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH3_V 0x1 +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH3_S 24 +/* GDMA_INFIFO_CNT_L3_CH3 : RO ;bitpos:[23:19] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 3..*/ +#define GDMA_INFIFO_CNT_L3_CH3 0x0000001F +#define GDMA_INFIFO_CNT_L3_CH3_M ((GDMA_INFIFO_CNT_L3_CH3_V)<<(GDMA_INFIFO_CNT_L3_CH3_S)) +#define GDMA_INFIFO_CNT_L3_CH3_V 0x1F +#define GDMA_INFIFO_CNT_L3_CH3_S 19 +/* GDMA_INFIFO_CNT_L2_CH3 : RO ;bitpos:[18:12] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 3..*/ +#define GDMA_INFIFO_CNT_L2_CH3 0x0000007F +#define GDMA_INFIFO_CNT_L2_CH3_M ((GDMA_INFIFO_CNT_L2_CH3_V)<<(GDMA_INFIFO_CNT_L2_CH3_S)) +#define GDMA_INFIFO_CNT_L2_CH3_V 0x7F +#define GDMA_INFIFO_CNT_L2_CH3_S 12 +/* GDMA_INFIFO_CNT_L1_CH3 : RO ;bitpos:[11:6] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 3..*/ +#define GDMA_INFIFO_CNT_L1_CH3 0x0000003F +#define GDMA_INFIFO_CNT_L1_CH3_M ((GDMA_INFIFO_CNT_L1_CH3_V)<<(GDMA_INFIFO_CNT_L1_CH3_S)) +#define GDMA_INFIFO_CNT_L1_CH3_V 0x3F +#define GDMA_INFIFO_CNT_L1_CH3_S 6 +/* GDMA_INFIFO_EMPTY_L3_CH3 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 3..*/ +#define GDMA_INFIFO_EMPTY_L3_CH3 (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH3_M (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH3_V 0x1 +#define GDMA_INFIFO_EMPTY_L3_CH3_S 5 +/* GDMA_INFIFO_FULL_L3_CH3 : RO ;bitpos:[4] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 3..*/ +#define GDMA_INFIFO_FULL_L3_CH3 (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH3_M (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH3_V 0x1 +#define GDMA_INFIFO_FULL_L3_CH3_S 4 +/* GDMA_INFIFO_EMPTY_L2_CH3 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 3..*/ +#define GDMA_INFIFO_EMPTY_L2_CH3 (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH3_M (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH3_V 0x1 +#define GDMA_INFIFO_EMPTY_L2_CH3_S 3 +/* GDMA_INFIFO_FULL_L2_CH3 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 3..*/ +#define GDMA_INFIFO_FULL_L2_CH3 (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH3_M (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH3_V 0x1 +#define GDMA_INFIFO_FULL_L2_CH3_S 2 +/* GDMA_INFIFO_EMPTY_L1_CH3 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 3..*/ +#define GDMA_INFIFO_EMPTY_L1_CH3 (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH3_M (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH3_V 0x1 +#define GDMA_INFIFO_EMPTY_L1_CH3_S 1 +/* GDMA_INFIFO_FULL_L1_CH3 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 3..*/ +#define GDMA_INFIFO_FULL_L1_CH3 (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH3_M (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH3_V 0x1 +#define GDMA_INFIFO_FULL_L1_CH3_S 0 + +#define GDMA_IN_POP_CH3_REG (DR_REG_GDMA_BASE + 0x25C) +/* GDMA_INFIFO_POP_CH3 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO..*/ +#define GDMA_INFIFO_POP_CH3 (BIT(12)) +#define GDMA_INFIFO_POP_CH3_M (BIT(12)) +#define GDMA_INFIFO_POP_CH3_V 0x1 +#define GDMA_INFIFO_POP_CH3_S 12 +/* GDMA_INFIFO_RDATA_CH3 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: This register stores the data popping from DMA FIFO..*/ +#define GDMA_INFIFO_RDATA_CH3 0x00000FFF +#define GDMA_INFIFO_RDATA_CH3_M ((GDMA_INFIFO_RDATA_CH3_V)<<(GDMA_INFIFO_RDATA_CH3_S)) +#define GDMA_INFIFO_RDATA_CH3_V 0xFFF +#define GDMA_INFIFO_RDATA_CH3_S 0 + +#define GDMA_IN_LINK_CH3_REG (DR_REG_GDMA_BASE + 0x260) +/* GDMA_INLINK_PARK_CH3 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM + is working..*/ +#define GDMA_INLINK_PARK_CH3 (BIT(24)) +#define GDMA_INLINK_PARK_CH3_M (BIT(24)) +#define GDMA_INLINK_PARK_CH3_V 0x1 +#define GDMA_INLINK_PARK_CH3_S 24 +/* GDMA_INLINK_RESTART_CH3 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor..*/ +#define GDMA_INLINK_RESTART_CH3 (BIT(23)) +#define GDMA_INLINK_RESTART_CH3_M (BIT(23)) +#define GDMA_INLINK_RESTART_CH3_V 0x1 +#define GDMA_INLINK_RESTART_CH3_S 23 +/* GDMA_INLINK_START_CH3 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors..*/ +#define GDMA_INLINK_START_CH3 (BIT(22)) +#define GDMA_INLINK_START_CH3_M (BIT(22)) +#define GDMA_INLINK_START_CH3_V 0x1 +#define GDMA_INLINK_START_CH3_S 22 +/* GDMA_INLINK_STOP_CH3 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors..*/ +#define GDMA_INLINK_STOP_CH3 (BIT(21)) +#define GDMA_INLINK_STOP_CH3_M (BIT(21)) +#define GDMA_INLINK_STOP_CH3_V 0x1 +#define GDMA_INLINK_STOP_CH3_S 21 +/* GDMA_INLINK_AUTO_RET_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address, when there are so +me errors in current receiving data..*/ +#define GDMA_INLINK_AUTO_RET_CH3 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH3_M (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH3_V 0x1 +#define GDMA_INLINK_AUTO_RET_CH3_S 20 +/* GDMA_INLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first inlink descripto +r's address..*/ +#define GDMA_INLINK_ADDR_CH3 0x000FFFFF +#define GDMA_INLINK_ADDR_CH3_M ((GDMA_INLINK_ADDR_CH3_V)<<(GDMA_INLINK_ADDR_CH3_S)) +#define GDMA_INLINK_ADDR_CH3_V 0xFFFFF +#define GDMA_INLINK_ADDR_CH3_S 0 + +#define GDMA_IN_STATE_CH3_REG (DR_REG_GDMA_BASE + 0x264) +/* GDMA_IN_STATE_CH3 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_STATE_CH3 0x00000007 +#define GDMA_IN_STATE_CH3_M ((GDMA_IN_STATE_CH3_V)<<(GDMA_IN_STATE_CH3_S)) +#define GDMA_IN_STATE_CH3_V 0x7 +#define GDMA_IN_STATE_CH3_S 20 +/* GDMA_IN_DSCR_STATE_CH3 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_DSCR_STATE_CH3 0x00000003 +#define GDMA_IN_DSCR_STATE_CH3_M ((GDMA_IN_DSCR_STATE_CH3_V)<<(GDMA_IN_DSCR_STATE_CH3_S)) +#define GDMA_IN_DSCR_STATE_CH3_V 0x3 +#define GDMA_IN_DSCR_STATE_CH3_S 18 +/* GDMA_INLINK_DSCR_ADDR_CH3 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address..*/ +#define GDMA_INLINK_DSCR_ADDR_CH3 0x0003FFFF +#define GDMA_INLINK_DSCR_ADDR_CH3_M ((GDMA_INLINK_DSCR_ADDR_CH3_V)<<(GDMA_INLINK_DSCR_ADDR_CH3_S)) +#define GDMA_INLINK_DSCR_ADDR_CH3_V 0x3FFFF +#define GDMA_INLINK_DSCR_ADDR_CH3_S 0 + +#define GDMA_IN_SUC_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x268) +/* GDMA_IN_SUC_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when the EOF bit in th +is descriptor is 1..*/ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH3 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH3_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH3_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH3_S)) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH3_V 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH3_S 0 + +#define GDMA_IN_ERR_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x26C) +/* GDMA_IN_ERR_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when there are some er +rors in current receiving data. Only used when peripheral is UHCI0..*/ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH3 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH3_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH3_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH3_S)) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH3_V 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH3_S 0 + +#define GDMA_IN_DSCR_CH3_REG (DR_REG_GDMA_BASE + 0x270) +/* GDMA_INLINK_DSCR_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x..*/ +#define GDMA_INLINK_DSCR_CH3 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH3_M ((GDMA_INLINK_DSCR_CH3_V)<<(GDMA_INLINK_DSCR_CH3_S)) +#define GDMA_INLINK_DSCR_CH3_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH3_S 0 + +#define GDMA_IN_DSCR_BF0_CH3_REG (DR_REG_GDMA_BASE + 0x274) +/* GDMA_INLINK_DSCR_BF0_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1..*/ +#define GDMA_INLINK_DSCR_BF0_CH3 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH3_M ((GDMA_INLINK_DSCR_BF0_CH3_V)<<(GDMA_INLINK_DSCR_BF0_CH3_S)) +#define GDMA_INLINK_DSCR_BF0_CH3_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH3_S 0 + +#define GDMA_IN_DSCR_BF1_CH3_REG (DR_REG_GDMA_BASE + 0x278) +/* GDMA_INLINK_DSCR_BF1_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_INLINK_DSCR_BF1_CH3 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH3_M ((GDMA_INLINK_DSCR_BF1_CH3_V)<<(GDMA_INLINK_DSCR_BF1_CH3_S)) +#define GDMA_INLINK_DSCR_BF1_CH3_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH3_S 0 + +#define GDMA_IN_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x27C) +/* GDMA_RX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Rx channel 3. .*/ +#define GDMA_RX_WEIGHT_CH3 0x0000000F +#define GDMA_RX_WEIGHT_CH3_M ((GDMA_RX_WEIGHT_CH3_V)<<(GDMA_RX_WEIGHT_CH3_S)) +#define GDMA_RX_WEIGHT_CH3_V 0xF +#define GDMA_RX_WEIGHT_CH3_S 8 + +#define GDMA_IN_PRI_CH3_REG (DR_REG_GDMA_BASE + 0x284) +/* GDMA_RX_PRI_CH3 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 3. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_RX_PRI_CH3 0x0000000F +#define GDMA_RX_PRI_CH3_M ((GDMA_RX_PRI_CH3_V)<<(GDMA_RX_PRI_CH3_S)) +#define GDMA_RX_PRI_CH3_V 0xF +#define GDMA_RX_PRI_CH3_S 0 + +#define GDMA_IN_PERI_SEL_CH3_REG (DR_REG_GDMA_BASE + 0x288) +/* GDMA_PERI_IN_SEL_CH3 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Rx channel 3. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_IN_SEL_CH3 0x0000003F +#define GDMA_PERI_IN_SEL_CH3_M ((GDMA_PERI_IN_SEL_CH3_V)<<(GDMA_PERI_IN_SEL_CH3_S)) +#define GDMA_PERI_IN_SEL_CH3_V 0x3F +#define GDMA_PERI_IN_SEL_CH3_S 0 + +#define GDMA_OUT_CONF0_CH3_REG (DR_REG_GDMA_BASE + 0x2A0) +/* GDMA_OUT_DATA_BURST_EN_CH3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 transmitting da +ta when accessing internal SRAM. .*/ +#define GDMA_OUT_DATA_BURST_EN_CH3 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH3_M (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH3_V 0x1 +#define GDMA_OUT_DATA_BURST_EN_CH3_S 5 +/* GDMA_OUTDSCR_BURST_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_OUTDSCR_BURST_EN_CH3 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH3_M (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH3_V 0x1 +#define GDMA_OUTDSCR_BURST_EN_CH3_S 4 +/* GDMA_OUT_EOF_MODE_CH3 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 3 is + generated when data need to transmit has been popped from FIFO in DMA.*/ +#define GDMA_OUT_EOF_MODE_CH3 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH3_M (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH3_V 0x1 +#define GDMA_OUT_EOF_MODE_CH3_S 3 +/* GDMA_OUT_AUTO_WRBACK_CH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe +r has been transmitted..*/ +#define GDMA_OUT_AUTO_WRBACK_CH3 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH3_M (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH3_V 0x1 +#define GDMA_OUT_AUTO_WRBACK_CH3_S 2 +/* GDMA_OUT_LOOP_TEST_CH3 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_LOOP_TEST_CH3 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH3_M (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH3_V 0x1 +#define GDMA_OUT_LOOP_TEST_CH3_S 1 +/* GDMA_OUT_RST_CH3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 3 Tx FSM and Tx FIFO pointer..*/ +#define GDMA_OUT_RST_CH3 (BIT(0)) +#define GDMA_OUT_RST_CH3_M (BIT(0)) +#define GDMA_OUT_RST_CH3_V 0x1 +#define GDMA_OUT_RST_CH3_S 0 + +#define GDMA_OUT_CONF1_CH3_REG (DR_REG_GDMA_BASE + 0x2A4) +/* GDMA_OUT_EXT_MEM_BK_SIZE_CH3 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 3 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH3 0x00000003 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH3_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH3_V)<<(GDMA_OUT_EXT_MEM_BK_SIZE_CH3_S)) +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH3_V 0x3 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH3_S 13 +/* GDMA_OUT_CHECK_OWNER_CH3 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_OUT_CHECK_OWNER_CH3 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH3_M (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH3_V 0x1 +#define GDMA_OUT_CHECK_OWNER_CH3_S 12 + +#define GDMA_OUT_INT_RAW_CH3_REG (DR_REG_GDMA_BASE + 0x2A8) +/* GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 3 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_RAW_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 3 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_RAW_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 3 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_RAW_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 3 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 +/* GDMA_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc +ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +nnel 3..*/ +#define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 +/* GDMA_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +r, including owner error, the second and third word error of outlink descriptor +for Tx channel 3..*/ +#define GDMA_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_S 2 +/* GDMA_OUT_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been read from memory for Tx channel 3. .*/ +#define GDMA_OUT_EOF_CH3_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH3_INT_RAW_M (BIT(1)) +#define GDMA_OUT_EOF_CH3_INT_RAW_V 0x1 +#define GDMA_OUT_EOF_CH3_INT_RAW_S 1 +/* GDMA_OUT_DONE_CH3_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been transmitted to peripherals for Tx channel 3..*/ +#define GDMA_OUT_DONE_CH3_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH3_INT_RAW_M (BIT(0)) +#define GDMA_OUT_DONE_CH3_INT_RAW_V 0x1 +#define GDMA_OUT_DONE_CH3_INT_RAW_S 0 + +#define GDMA_OUT_INT_ST_CH3_REG (DR_REG_GDMA_BASE + 0x2AC) +/* GDMA_OUTFIFO_UDF_L3_CH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ST_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ST_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH3_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ST_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ST_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH3_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ST_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ST_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH3_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ST_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ST_S 4 +/* GDMA_OUT_TOTAL_EOF_CH3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH3_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH3_INT_ST_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH3_INT_ST_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH3_INT_ST_S 3 +/* GDMA_OUT_DSCR_ERR_CH3_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH3_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH3_INT_ST_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH3_INT_ST_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH3_INT_ST_S 2 +/* GDMA_OUT_EOF_CH3_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH3_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH3_INT_ST_M (BIT(1)) +#define GDMA_OUT_EOF_CH3_INT_ST_V 0x1 +#define GDMA_OUT_EOF_CH3_INT_ST_S 1 +/* GDMA_OUT_DONE_CH3_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH3_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH3_INT_ST_M (BIT(0)) +#define GDMA_OUT_DONE_CH3_INT_ST_V 0x1 +#define GDMA_OUT_DONE_CH3_INT_ST_S 0 + +#define GDMA_OUT_INT_ENA_CH3_REG (DR_REG_GDMA_BASE + 0x2B0) +/* GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_ENA_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_ENA_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_ENA_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_ENA_S 4 +/* GDMA_OUT_TOTAL_EOF_CH3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH3_INT_ENA_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH3_INT_ENA_S 3 +/* GDMA_OUT_DSCR_ERR_CH3_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH3_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH3_INT_ENA_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH3_INT_ENA_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH3_INT_ENA_S 2 +/* GDMA_OUT_EOF_CH3_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH3_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH3_INT_ENA_M (BIT(1)) +#define GDMA_OUT_EOF_CH3_INT_ENA_V 0x1 +#define GDMA_OUT_EOF_CH3_INT_ENA_S 1 +/* GDMA_OUT_DONE_CH3_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH3_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH3_INT_ENA_M (BIT(0)) +#define GDMA_OUT_DONE_CH3_INT_ENA_V 0x1 +#define GDMA_OUT_DONE_CH3_INT_ENA_S 0 + +#define GDMA_OUT_INT_CLR_CH3_REG (DR_REG_GDMA_BASE + 0x2B4) +/* GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH3_INT_CLR_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH3_INT_CLR_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH3_INT_CLR_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH3_INT_CLR_S 4 +/* GDMA_OUT_TOTAL_EOF_CH3_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH3_INT_CLR_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH3_INT_CLR_S 3 +/* GDMA_OUT_DSCR_ERR_CH3_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH3_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH3_INT_CLR_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH3_INT_CLR_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH3_INT_CLR_S 2 +/* GDMA_OUT_EOF_CH3_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH3_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH3_INT_CLR_M (BIT(1)) +#define GDMA_OUT_EOF_CH3_INT_CLR_V 0x1 +#define GDMA_OUT_EOF_CH3_INT_CLR_S 1 +/* GDMA_OUT_DONE_CH3_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH3_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH3_INT_CLR_M (BIT(0)) +#define GDMA_OUT_DONE_CH3_INT_CLR_V 0x1 +#define GDMA_OUT_DONE_CH3_INT_CLR_S 0 + +#define GDMA_OUTFIFO_STATUS_CH3_REG (DR_REG_GDMA_BASE + 0x2B8) +/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH3 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH3 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH3_M (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH3_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH3_S 26 +/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH3 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH3 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH3_M (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH3_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH3_S 25 +/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH3 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH3 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH3_M (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH3_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH3_S 24 +/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH3 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH3 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH3_M (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH3_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH3_S 23 +/* GDMA_OUTFIFO_CNT_L3_CH3 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 3..*/ +#define GDMA_OUTFIFO_CNT_L3_CH3 0x0000001F +#define GDMA_OUTFIFO_CNT_L3_CH3_M ((GDMA_OUTFIFO_CNT_L3_CH3_V)<<(GDMA_OUTFIFO_CNT_L3_CH3_S)) +#define GDMA_OUTFIFO_CNT_L3_CH3_V 0x1F +#define GDMA_OUTFIFO_CNT_L3_CH3_S 18 +/* GDMA_OUTFIFO_CNT_L2_CH3 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 3..*/ +#define GDMA_OUTFIFO_CNT_L2_CH3 0x0000007F +#define GDMA_OUTFIFO_CNT_L2_CH3_M ((GDMA_OUTFIFO_CNT_L2_CH3_V)<<(GDMA_OUTFIFO_CNT_L2_CH3_S)) +#define GDMA_OUTFIFO_CNT_L2_CH3_V 0x7F +#define GDMA_OUTFIFO_CNT_L2_CH3_S 11 +/* GDMA_OUTFIFO_CNT_L1_CH3 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 3..*/ +#define GDMA_OUTFIFO_CNT_L1_CH3 0x0000001F +#define GDMA_OUTFIFO_CNT_L1_CH3_M ((GDMA_OUTFIFO_CNT_L1_CH3_V)<<(GDMA_OUTFIFO_CNT_L1_CH3_S)) +#define GDMA_OUTFIFO_CNT_L1_CH3_V 0x1F +#define GDMA_OUTFIFO_CNT_L1_CH3_S 6 +/* GDMA_OUTFIFO_EMPTY_L3_CH3 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 3..*/ +#define GDMA_OUTFIFO_EMPTY_L3_CH3 (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH3_M (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH3_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L3_CH3_S 5 +/* GDMA_OUTFIFO_FULL_L3_CH3 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 3..*/ +#define GDMA_OUTFIFO_FULL_L3_CH3 (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH3_M (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH3_V 0x1 +#define GDMA_OUTFIFO_FULL_L3_CH3_S 4 +/* GDMA_OUTFIFO_EMPTY_L2_CH3 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 3..*/ +#define GDMA_OUTFIFO_EMPTY_L2_CH3 (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH3_M (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH3_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L2_CH3_S 3 +/* GDMA_OUTFIFO_FULL_L2_CH3 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 3..*/ +#define GDMA_OUTFIFO_FULL_L2_CH3 (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH3_M (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH3_V 0x1 +#define GDMA_OUTFIFO_FULL_L2_CH3_S 2 +/* GDMA_OUTFIFO_EMPTY_L1_CH3 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 3..*/ +#define GDMA_OUTFIFO_EMPTY_L1_CH3 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH3_M (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH3_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L1_CH3_S 1 +/* GDMA_OUTFIFO_FULL_L1_CH3 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 3..*/ +#define GDMA_OUTFIFO_FULL_L1_CH3 (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH3_M (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH3_V 0x1 +#define GDMA_OUTFIFO_FULL_L1_CH3_S 0 + +#define GDMA_OUT_PUSH_CH3_REG (DR_REG_GDMA_BASE + 0x2BC) +/* GDMA_OUTFIFO_PUSH_CH3 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO..*/ +#define GDMA_OUTFIFO_PUSH_CH3 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH3_M (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH3_V 0x1 +#define GDMA_OUTFIFO_PUSH_CH3_S 9 +/* GDMA_OUTFIFO_WDATA_CH3 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO..*/ +#define GDMA_OUTFIFO_WDATA_CH3 0x000001FF +#define GDMA_OUTFIFO_WDATA_CH3_M ((GDMA_OUTFIFO_WDATA_CH3_V)<<(GDMA_OUTFIFO_WDATA_CH3_S)) +#define GDMA_OUTFIFO_WDATA_CH3_V 0x1FF +#define GDMA_OUTFIFO_WDATA_CH3_S 0 + +#define GDMA_OUT_LINK_CH3_REG (DR_REG_GDMA_BASE + 0x2C0) +/* GDMA_OUTLINK_PARK_CH3 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F +SM is working..*/ +#define GDMA_OUTLINK_PARK_CH3 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH3_M (BIT(23)) +#define GDMA_OUTLINK_PARK_CH3_V 0x1 +#define GDMA_OUTLINK_PARK_CH3_S 23 +/* GDMA_OUTLINK_RESTART_CH3 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address. .*/ +#define GDMA_OUTLINK_RESTART_CH3 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH3_M (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH3_V 0x1 +#define GDMA_OUTLINK_RESTART_CH3_S 22 +/* GDMA_OUTLINK_START_CH3 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_START_CH3 (BIT(21)) +#define GDMA_OUTLINK_START_CH3_M (BIT(21)) +#define GDMA_OUTLINK_START_CH3_V 0x1 +#define GDMA_OUTLINK_START_CH3_S 21 +/* GDMA_OUTLINK_STOP_CH3 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_STOP_CH3 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH3_M (BIT(20)) +#define GDMA_OUTLINK_STOP_CH3_V 0x1 +#define GDMA_OUTLINK_STOP_CH3_S 20 +/* GDMA_OUTLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first outlink descript +or's address..*/ +#define GDMA_OUTLINK_ADDR_CH3 0x000FFFFF +#define GDMA_OUTLINK_ADDR_CH3_M ((GDMA_OUTLINK_ADDR_CH3_V)<<(GDMA_OUTLINK_ADDR_CH3_S)) +#define GDMA_OUTLINK_ADDR_CH3_V 0xFFFFF +#define GDMA_OUTLINK_ADDR_CH3_S 0 + +#define GDMA_OUT_STATE_CH3_REG (DR_REG_GDMA_BASE + 0x2C4) +/* GDMA_OUT_STATE_CH3 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_STATE_CH3 0x00000007 +#define GDMA_OUT_STATE_CH3_M ((GDMA_OUT_STATE_CH3_V)<<(GDMA_OUT_STATE_CH3_S)) +#define GDMA_OUT_STATE_CH3_V 0x7 +#define GDMA_OUT_STATE_CH3_S 20 +/* GDMA_OUT_DSCR_STATE_CH3 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_DSCR_STATE_CH3 0x00000003 +#define GDMA_OUT_DSCR_STATE_CH3_M ((GDMA_OUT_DSCR_STATE_CH3_V)<<(GDMA_OUT_DSCR_STATE_CH3_S)) +#define GDMA_OUT_DSCR_STATE_CH3_V 0x3 +#define GDMA_OUT_DSCR_STATE_CH3_S 18 +/* GDMA_OUTLINK_DSCR_ADDR_CH3 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address..*/ +#define GDMA_OUTLINK_DSCR_ADDR_CH3 0x0003FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH3_M ((GDMA_OUTLINK_DSCR_ADDR_CH3_V)<<(GDMA_OUTLINK_DSCR_ADDR_CH3_S)) +#define GDMA_OUTLINK_DSCR_ADDR_CH3_V 0x3FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH3_S 0 + +#define GDMA_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x2C8) +/* GDMA_OUT_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when the EOF bit in t +his descriptor is 1..*/ +#define GDMA_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH3_M ((GDMA_OUT_EOF_DES_ADDR_CH3_V)<<(GDMA_OUT_EOF_DES_ADDR_CH3_S)) +#define GDMA_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH3_S 0 + +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x2CC) +/* GDMA_OUT_EOF_BFR_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before the last outli +nk descriptor..*/ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH3_S)) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_S 0 + +#define GDMA_OUT_DSCR_CH3_REG (DR_REG_GDMA_BASE + 0x2D0) +/* GDMA_OUTLINK_DSCR_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y..*/ +#define GDMA_OUTLINK_DSCR_CH3 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH3_M ((GDMA_OUTLINK_DSCR_CH3_V)<<(GDMA_OUTLINK_DSCR_CH3_S)) +#define GDMA_OUTLINK_DSCR_CH3_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH3_S 0 + +#define GDMA_OUT_DSCR_BF0_CH3_REG (DR_REG_GDMA_BASE + 0x2D4) +/* GDMA_OUTLINK_DSCR_BF0_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1..*/ +#define GDMA_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH3_M ((GDMA_OUTLINK_DSCR_BF0_CH3_V)<<(GDMA_OUTLINK_DSCR_BF0_CH3_S)) +#define GDMA_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH3_S 0 + +#define GDMA_OUT_DSCR_BF1_CH3_REG (DR_REG_GDMA_BASE + 0x2D8) +/* GDMA_OUTLINK_DSCR_BF1_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH3_M ((GDMA_OUTLINK_DSCR_BF1_CH3_V)<<(GDMA_OUTLINK_DSCR_BF1_CH3_S)) +#define GDMA_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH3_S 0 + +#define GDMA_OUT_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x2DC) +/* GDMA_TX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Tx channel 3. .*/ +#define GDMA_TX_WEIGHT_CH3 0x0000000F +#define GDMA_TX_WEIGHT_CH3_M ((GDMA_TX_WEIGHT_CH3_V)<<(GDMA_TX_WEIGHT_CH3_S)) +#define GDMA_TX_WEIGHT_CH3_V 0xF +#define GDMA_TX_WEIGHT_CH3_S 8 + +#define GDMA_OUT_PRI_CH3_REG (DR_REG_GDMA_BASE + 0x2E4) /* GDMA_TX_PRI_CH3 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 3. The larger of the value the higher - of the priority.*/ -#define GDMA_TX_PRI_CH3 0x0000000F -#define GDMA_TX_PRI_CH3_M ((GDMA_TX_PRI_CH3_V) << (GDMA_TX_PRI_CH3_S)) -#define GDMA_TX_PRI_CH3_V 0xF -#define GDMA_TX_PRI_CH3_S 0 +/*description: The priority of Tx channel 3. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_TX_PRI_CH3 0x0000000F +#define GDMA_TX_PRI_CH3_M ((GDMA_TX_PRI_CH3_V)<<(GDMA_TX_PRI_CH3_S)) +#define GDMA_TX_PRI_CH3_V 0xF +#define GDMA_TX_PRI_CH3_S 0 -#define GDMA_PRI_CH4_REG (DR_REG_GDMA_BASE + 0x210) -/* GDMA_RX_PRI_CH4 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 4. The larger of the value the higher - of the priority.*/ -#define GDMA_RX_PRI_CH4 0x0000000F -#define GDMA_RX_PRI_CH4_M ((GDMA_RX_PRI_CH4_V) << (GDMA_RX_PRI_CH4_S)) -#define GDMA_RX_PRI_CH4_V 0xF -#define GDMA_RX_PRI_CH4_S 4 +#define GDMA_OUT_PERI_SEL_CH3_REG (DR_REG_GDMA_BASE + 0x2E8) +/* GDMA_PERI_OUT_SEL_CH3 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Tx channel 3. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_OUT_SEL_CH3 0x0000003F +#define GDMA_PERI_OUT_SEL_CH3_M ((GDMA_PERI_OUT_SEL_CH3_V)<<(GDMA_PERI_OUT_SEL_CH3_S)) +#define GDMA_PERI_OUT_SEL_CH3_V 0x3F +#define GDMA_PERI_OUT_SEL_CH3_S 0 + +#define GDMA_IN_CONF0_CH4_REG (DR_REG_GDMA_BASE + 0x300) +/* GDMA_MEM_TRANS_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D +MA..*/ +#define GDMA_MEM_TRANS_EN_CH4 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH4_M (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH4_V 0x1 +#define GDMA_MEM_TRANS_EN_CH4_S 4 +/* GDMA_IN_DATA_BURST_EN_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data +when accessing internal SRAM. .*/ +#define GDMA_IN_DATA_BURST_EN_CH4 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH4_M (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH4_V 0x1 +#define GDMA_IN_DATA_BURST_EN_CH4_S 3 +/* GDMA_INDSCR_BURST_EN_CH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_INDSCR_BURST_EN_CH4 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH4_M (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH4_V 0x1 +#define GDMA_INDSCR_BURST_EN_CH4_S 2 +/* GDMA_IN_LOOP_TEST_CH4 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_LOOP_TEST_CH4 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH4_M (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH4_V 0x1 +#define GDMA_IN_LOOP_TEST_CH4_S 1 +/* GDMA_IN_RST_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 4 Rx FSM and Rx FIFO pointer..*/ +#define GDMA_IN_RST_CH4 (BIT(0)) +#define GDMA_IN_RST_CH4_M (BIT(0)) +#define GDMA_IN_RST_CH4_V 0x1 +#define GDMA_IN_RST_CH4_S 0 + +#define GDMA_IN_CONF1_CH4_REG (DR_REG_GDMA_BASE + 0x304) +/* GDMA_IN_EXT_MEM_BK_SIZE_CH4 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 4 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_IN_EXT_MEM_BK_SIZE_CH4 0x00000003 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH4_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH4_V)<<(GDMA_IN_EXT_MEM_BK_SIZE_CH4_S)) +#define GDMA_IN_EXT_MEM_BK_SIZE_CH4_V 0x3 +#define GDMA_IN_EXT_MEM_BK_SIZE_CH4_S 13 +/* GDMA_IN_CHECK_OWNER_CH4 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_IN_CHECK_OWNER_CH4 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH4_M (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH4_V 0x1 +#define GDMA_IN_CHECK_OWNER_CH4_S 12 +/* GDMA_DMA_INFIFO_FULL_THRS_CH4 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann +el 4 received byte number in Rx FIFO is up to the value of the register..*/ +#define GDMA_DMA_INFIFO_FULL_THRS_CH4 0x00000FFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH4_M ((GDMA_DMA_INFIFO_FULL_THRS_CH4_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH4_S)) +#define GDMA_DMA_INFIFO_FULL_THRS_CH4_V 0xFFF +#define GDMA_DMA_INFIFO_FULL_THRS_CH4_S 0 + +#define GDMA_IN_INT_RAW_CH4_REG (DR_REG_GDMA_BASE + 0x308) +/* GDMA_INFIFO_UDF_L3_CH4_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 4 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L3_CH4_INT_RAW (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH4_INT_RAW_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH4_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH4_INT_RAW_S 9 +/* GDMA_INFIFO_OVF_L3_CH4_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 4 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L3_CH4_INT_RAW (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH4_INT_RAW_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH4_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH4_INT_RAW_S 8 +/* GDMA_INFIFO_UDF_L1_CH4_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 4 is +underflow. .*/ +#define GDMA_INFIFO_UDF_L1_CH4_INT_RAW (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH4_INT_RAW_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH4_INT_RAW_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH4_INT_RAW_S 7 +/* GDMA_INFIFO_OVF_L1_CH4_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 4 is +overflow. .*/ +#define GDMA_INFIFO_OVF_L1_CH4_INT_RAW (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_S 6 +/* GDMA_INFIFO_FULL_WM_CH4_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data byte number is up t +o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 4..*/ +#define GDMA_INFIFO_FULL_WM_CH4_INT_RAW (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_S 5 +/* GDMA_IN_DSCR_EMPTY_CH4_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu +ll and receiving data is not completed, but there is no more inlink for Rx chann +el 4..*/ +#define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_S 4 +/* GDMA_IN_DSCR_ERR_CH4_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink descriptor error +, including owner error, the second and third word error of inlink descriptor fo +r Rx channel 4..*/ +#define GDMA_IN_DSCR_ERR_CH4_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH4_INT_RAW_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH4_INT_RAW_V 0x1 +#define GDMA_IN_DSCR_ERR_CH4_INT_RAW_S 3 +/* GDMA_IN_ERR_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is detected only in th +e case that the peripheral is UHCI0 for Rx channel 4. For other peripherals, thi +s raw interrupt is reserved..*/ +#define GDMA_IN_ERR_EOF_CH4_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH4_INT_RAW_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH4_INT_RAW_V 0x1 +#define GDMA_IN_ERR_EOF_CH4_INT_RAW_S 2 +/* GDMA_IN_SUC_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 4. For UHCI0, the raw interrupt b +it turns to high level when the last data pointed by one inlink descriptor has b +een received and no data error is detected for Rx channel 0..*/ +#define GDMA_IN_SUC_EOF_CH4_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH4_INT_RAW_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH4_INT_RAW_V 0x1 +#define GDMA_IN_SUC_EOF_CH4_INT_RAW_S 1 +/* GDMA_IN_DONE_CH4_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one inli +nk descriptor has been received for Rx channel 4..*/ +#define GDMA_IN_DONE_CH4_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH4_INT_RAW_M (BIT(0)) +#define GDMA_IN_DONE_CH4_INT_RAW_V 0x1 +#define GDMA_IN_DONE_CH4_INT_RAW_S 0 + +#define GDMA_IN_INT_ST_CH4_REG (DR_REG_GDMA_BASE + 0x30C) +/* GDMA_INFIFO_UDF_L3_CH4_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH4_INT_ST (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH4_INT_ST_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH4_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH4_INT_ST_S 9 +/* GDMA_INFIFO_OVF_L3_CH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH4_INT_ST (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH4_INT_ST_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH4_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH4_INT_ST_S 8 +/* GDMA_INFIFO_UDF_L1_CH4_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH4_INT_ST (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH4_INT_ST_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH4_INT_ST_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH4_INT_ST_S 7 +/* GDMA_INFIFO_OVF_L1_CH4_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH4_INT_ST (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH4_INT_ST_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH4_INT_ST_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH4_INT_ST_S 6 +/* GDMA_INFIFO_FULL_WM_CH4_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH4_INT_ST (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH4_INT_ST_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH4_INT_ST_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH4_INT_ST_S 5 +/* GDMA_IN_DSCR_EMPTY_CH4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH4_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH4_INT_ST_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH4_INT_ST_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH4_INT_ST_S 4 +/* GDMA_IN_DSCR_ERR_CH4_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH4_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH4_INT_ST_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH4_INT_ST_V 0x1 +#define GDMA_IN_DSCR_ERR_CH4_INT_ST_S 3 +/* GDMA_IN_ERR_EOF_CH4_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH4_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH4_INT_ST_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH4_INT_ST_V 0x1 +#define GDMA_IN_ERR_EOF_CH4_INT_ST_S 2 +/* GDMA_IN_SUC_EOF_CH4_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH4_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH4_INT_ST_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH4_INT_ST_V 0x1 +#define GDMA_IN_SUC_EOF_CH4_INT_ST_S 1 +/* GDMA_IN_DONE_CH4_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH4_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH4_INT_ST_M (BIT(0)) +#define GDMA_IN_DONE_CH4_INT_ST_V 0x1 +#define GDMA_IN_DONE_CH4_INT_ST_S 0 + +#define GDMA_IN_INT_ENA_CH4_REG (DR_REG_GDMA_BASE + 0x310) +/* GDMA_INFIFO_UDF_L3_CH4_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH4_INT_ENA (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH4_INT_ENA_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH4_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH4_INT_ENA_S 9 +/* GDMA_INFIFO_OVF_L3_CH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH4_INT_ENA (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH4_INT_ENA_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH4_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH4_INT_ENA_S 8 +/* GDMA_INFIFO_UDF_L1_CH4_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH4_INT_ENA (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH4_INT_ENA_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH4_INT_ENA_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH4_INT_ENA_S 7 +/* GDMA_INFIFO_OVF_L1_CH4_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH4_INT_ENA (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH4_INT_ENA_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH4_INT_ENA_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH4_INT_ENA_S 6 +/* GDMA_INFIFO_FULL_WM_CH4_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_INFIFO_FULL_WM_CH4_INT_ENA (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH4_INT_ENA_M (BIT(5)) +#define GDMA_INFIFO_FULL_WM_CH4_INT_ENA_V 0x1 +#define GDMA_INFIFO_FULL_WM_CH4_INT_ENA_S 5 +/* GDMA_IN_DSCR_EMPTY_CH4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH4_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH4_INT_ENA_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH4_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH4_INT_ENA_S 4 +/* GDMA_IN_DSCR_ERR_CH4_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH4_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH4_INT_ENA_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH4_INT_ENA_V 0x1 +#define GDMA_IN_DSCR_ERR_CH4_INT_ENA_S 3 +/* GDMA_IN_ERR_EOF_CH4_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH4_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH4_INT_ENA_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH4_INT_ENA_V 0x1 +#define GDMA_IN_ERR_EOF_CH4_INT_ENA_S 2 +/* GDMA_IN_SUC_EOF_CH4_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH4_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH4_INT_ENA_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH4_INT_ENA_V 0x1 +#define GDMA_IN_SUC_EOF_CH4_INT_ENA_S 1 +/* GDMA_IN_DONE_CH4_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH4_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH4_INT_ENA_M (BIT(0)) +#define GDMA_IN_DONE_CH4_INT_ENA_V 0x1 +#define GDMA_IN_DONE_CH4_INT_ENA_S 0 + +#define GDMA_IN_INT_CLR_CH4_REG (DR_REG_GDMA_BASE + 0x314) +/* GDMA_INFIFO_UDF_L3_CH4_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L3_CH4_INT_CLR (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH4_INT_CLR_M (BIT(9)) +#define GDMA_INFIFO_UDF_L3_CH4_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L3_CH4_INT_CLR_S 9 +/* GDMA_INFIFO_OVF_L3_CH4_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L3_CH4_INT_CLR (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH4_INT_CLR_M (BIT(8)) +#define GDMA_INFIFO_OVF_L3_CH4_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L3_CH4_INT_CLR_S 8 +/* GDMA_INFIFO_UDF_L1_CH4_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_UDF_L1_CH4_INT_CLR (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH4_INT_CLR_M (BIT(7)) +#define GDMA_INFIFO_UDF_L1_CH4_INT_CLR_V 0x1 +#define GDMA_INFIFO_UDF_L1_CH4_INT_CLR_S 7 +/* GDMA_INFIFO_OVF_L1_CH4_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_INFIFO_OVF_L1_CH4_INT_CLR (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH4_INT_CLR_M (BIT(6)) +#define GDMA_INFIFO_OVF_L1_CH4_INT_CLR_V 0x1 +#define GDMA_INFIFO_OVF_L1_CH4_INT_CLR_S 6 +/* GDMA_DMA_INFIFO_FULL_WM_CH4_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt..*/ +#define GDMA_DMA_INFIFO_FULL_WM_CH4_INT_CLR (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH4_INT_CLR_M (BIT(5)) +#define GDMA_DMA_INFIFO_FULL_WM_CH4_INT_CLR_V 0x1 +#define GDMA_DMA_INFIFO_FULL_WM_CH4_INT_CLR_S 5 +/* GDMA_IN_DSCR_EMPTY_CH4_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_EMPTY_CH4_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH4_INT_CLR_M (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH4_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_EMPTY_CH4_INT_CLR_S 4 +/* GDMA_IN_DSCR_ERR_CH4_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_IN_DSCR_ERR_CH4_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH4_INT_CLR_M (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH4_INT_CLR_V 0x1 +#define GDMA_IN_DSCR_ERR_CH4_INT_CLR_S 3 +/* GDMA_IN_ERR_EOF_CH4_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt..*/ +#define GDMA_IN_ERR_EOF_CH4_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH4_INT_CLR_M (BIT(2)) +#define GDMA_IN_ERR_EOF_CH4_INT_CLR_V 0x1 +#define GDMA_IN_ERR_EOF_CH4_INT_CLR_S 2 +/* GDMA_IN_SUC_EOF_CH4_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt..*/ +#define GDMA_IN_SUC_EOF_CH4_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH4_INT_CLR_M (BIT(1)) +#define GDMA_IN_SUC_EOF_CH4_INT_CLR_V 0x1 +#define GDMA_IN_SUC_EOF_CH4_INT_CLR_S 1 +/* GDMA_IN_DONE_CH4_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt..*/ +#define GDMA_IN_DONE_CH4_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH4_INT_CLR_M (BIT(0)) +#define GDMA_IN_DONE_CH4_INT_CLR_V 0x1 +#define GDMA_IN_DONE_CH4_INT_CLR_S 0 + +#define GDMA_INFIFO_STATUS_CH4_REG (DR_REG_GDMA_BASE + 0x318) +/* GDMA_IN_BUF_HUNGRY_CH4 : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_BUF_HUNGRY_CH4 (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH4_M (BIT(28)) +#define GDMA_IN_BUF_HUNGRY_CH4_V 0x1 +#define GDMA_IN_BUF_HUNGRY_CH4_S 28 +/* GDMA_IN_REMAIN_UNDER_4B_L3_CH4 : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH4 (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH4_M (BIT(27)) +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH4_V 0x1 +#define GDMA_IN_REMAIN_UNDER_4B_L3_CH4_S 27 +/* GDMA_IN_REMAIN_UNDER_3B_L3_CH4 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH4 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH4_M (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH4_V 0x1 +#define GDMA_IN_REMAIN_UNDER_3B_L3_CH4_S 26 +/* GDMA_IN_REMAIN_UNDER_2B_L3_CH4 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH4 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH4_M (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH4_V 0x1 +#define GDMA_IN_REMAIN_UNDER_2B_L3_CH4_S 25 +/* GDMA_IN_REMAIN_UNDER_1B_L3_CH4 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH4 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH4_M (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH4_V 0x1 +#define GDMA_IN_REMAIN_UNDER_1B_L3_CH4_S 24 +/* GDMA_INFIFO_CNT_L3_CH4 : RO ;bitpos:[23:19] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 4..*/ +#define GDMA_INFIFO_CNT_L3_CH4 0x0000001F +#define GDMA_INFIFO_CNT_L3_CH4_M ((GDMA_INFIFO_CNT_L3_CH4_V)<<(GDMA_INFIFO_CNT_L3_CH4_S)) +#define GDMA_INFIFO_CNT_L3_CH4_V 0x1F +#define GDMA_INFIFO_CNT_L3_CH4_S 19 +/* GDMA_INFIFO_CNT_L2_CH4 : RO ;bitpos:[18:12] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 4..*/ +#define GDMA_INFIFO_CNT_L2_CH4 0x0000007F +#define GDMA_INFIFO_CNT_L2_CH4_M ((GDMA_INFIFO_CNT_L2_CH4_V)<<(GDMA_INFIFO_CNT_L2_CH4_S)) +#define GDMA_INFIFO_CNT_L2_CH4_V 0x7F +#define GDMA_INFIFO_CNT_L2_CH4_S 12 +/* GDMA_INFIFO_CNT_L1_CH4 : RO ;bitpos:[11:6] ;default: 6'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 4..*/ +#define GDMA_INFIFO_CNT_L1_CH4 0x0000003F +#define GDMA_INFIFO_CNT_L1_CH4_M ((GDMA_INFIFO_CNT_L1_CH4_V)<<(GDMA_INFIFO_CNT_L1_CH4_S)) +#define GDMA_INFIFO_CNT_L1_CH4_V 0x3F +#define GDMA_INFIFO_CNT_L1_CH4_S 6 +/* GDMA_INFIFO_EMPTY_L3_CH4 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 4..*/ +#define GDMA_INFIFO_EMPTY_L3_CH4 (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH4_M (BIT(5)) +#define GDMA_INFIFO_EMPTY_L3_CH4_V 0x1 +#define GDMA_INFIFO_EMPTY_L3_CH4_S 5 +/* GDMA_INFIFO_FULL_L3_CH4 : RO ;bitpos:[4] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 4..*/ +#define GDMA_INFIFO_FULL_L3_CH4 (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH4_M (BIT(4)) +#define GDMA_INFIFO_FULL_L3_CH4_V 0x1 +#define GDMA_INFIFO_FULL_L3_CH4_S 4 +/* GDMA_INFIFO_EMPTY_L2_CH4 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 4..*/ +#define GDMA_INFIFO_EMPTY_L2_CH4 (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH4_M (BIT(3)) +#define GDMA_INFIFO_EMPTY_L2_CH4_V 0x1 +#define GDMA_INFIFO_EMPTY_L2_CH4_S 3 +/* GDMA_INFIFO_FULL_L2_CH4 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 4..*/ +#define GDMA_INFIFO_FULL_L2_CH4 (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH4_M (BIT(2)) +#define GDMA_INFIFO_FULL_L2_CH4_V 0x1 +#define GDMA_INFIFO_FULL_L2_CH4_S 2 +/* GDMA_INFIFO_EMPTY_L1_CH4 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 4..*/ +#define GDMA_INFIFO_EMPTY_L1_CH4 (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH4_M (BIT(1)) +#define GDMA_INFIFO_EMPTY_L1_CH4_V 0x1 +#define GDMA_INFIFO_EMPTY_L1_CH4_S 1 +/* GDMA_INFIFO_FULL_L1_CH4 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 4..*/ +#define GDMA_INFIFO_FULL_L1_CH4 (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH4_M (BIT(0)) +#define GDMA_INFIFO_FULL_L1_CH4_V 0x1 +#define GDMA_INFIFO_FULL_L1_CH4_S 0 + +#define GDMA_IN_POP_CH4_REG (DR_REG_GDMA_BASE + 0x31C) +/* GDMA_INFIFO_POP_CH4 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO..*/ +#define GDMA_INFIFO_POP_CH4 (BIT(12)) +#define GDMA_INFIFO_POP_CH4_M (BIT(12)) +#define GDMA_INFIFO_POP_CH4_V 0x1 +#define GDMA_INFIFO_POP_CH4_S 12 +/* GDMA_INFIFO_RDATA_CH4 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ +/*description: This register stores the data popping from DMA FIFO..*/ +#define GDMA_INFIFO_RDATA_CH4 0x00000FFF +#define GDMA_INFIFO_RDATA_CH4_M ((GDMA_INFIFO_RDATA_CH4_V)<<(GDMA_INFIFO_RDATA_CH4_S)) +#define GDMA_INFIFO_RDATA_CH4_V 0xFFF +#define GDMA_INFIFO_RDATA_CH4_S 0 + +#define GDMA_IN_LINK_CH4_REG (DR_REG_GDMA_BASE + 0x320) +/* GDMA_INLINK_PARK_CH4 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM + is working..*/ +#define GDMA_INLINK_PARK_CH4 (BIT(24)) +#define GDMA_INLINK_PARK_CH4_M (BIT(24)) +#define GDMA_INLINK_PARK_CH4_V 0x1 +#define GDMA_INLINK_PARK_CH4_S 24 +/* GDMA_INLINK_RESTART_CH4 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor..*/ +#define GDMA_INLINK_RESTART_CH4 (BIT(23)) +#define GDMA_INLINK_RESTART_CH4_M (BIT(23)) +#define GDMA_INLINK_RESTART_CH4_V 0x1 +#define GDMA_INLINK_RESTART_CH4_S 23 +/* GDMA_INLINK_START_CH4 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors..*/ +#define GDMA_INLINK_START_CH4 (BIT(22)) +#define GDMA_INLINK_START_CH4_M (BIT(22)) +#define GDMA_INLINK_START_CH4_V 0x1 +#define GDMA_INLINK_START_CH4_S 22 +/* GDMA_INLINK_STOP_CH4 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors..*/ +#define GDMA_INLINK_STOP_CH4 (BIT(21)) +#define GDMA_INLINK_STOP_CH4_M (BIT(21)) +#define GDMA_INLINK_STOP_CH4_V 0x1 +#define GDMA_INLINK_STOP_CH4_S 21 +/* GDMA_INLINK_AUTO_RET_CH4 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address, when there are so +me errors in current receiving data..*/ +#define GDMA_INLINK_AUTO_RET_CH4 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH4_M (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH4_V 0x1 +#define GDMA_INLINK_AUTO_RET_CH4_S 20 +/* GDMA_INLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first inlink descripto +r's address..*/ +#define GDMA_INLINK_ADDR_CH4 0x000FFFFF +#define GDMA_INLINK_ADDR_CH4_M ((GDMA_INLINK_ADDR_CH4_V)<<(GDMA_INLINK_ADDR_CH4_S)) +#define GDMA_INLINK_ADDR_CH4_V 0xFFFFF +#define GDMA_INLINK_ADDR_CH4_S 0 + +#define GDMA_IN_STATE_CH4_REG (DR_REG_GDMA_BASE + 0x324) +/* GDMA_IN_STATE_CH4 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_STATE_CH4 0x00000007 +#define GDMA_IN_STATE_CH4_M ((GDMA_IN_STATE_CH4_V)<<(GDMA_IN_STATE_CH4_S)) +#define GDMA_IN_STATE_CH4_V 0x7 +#define GDMA_IN_STATE_CH4_S 20 +/* GDMA_IN_DSCR_STATE_CH4 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_IN_DSCR_STATE_CH4 0x00000003 +#define GDMA_IN_DSCR_STATE_CH4_M ((GDMA_IN_DSCR_STATE_CH4_V)<<(GDMA_IN_DSCR_STATE_CH4_S)) +#define GDMA_IN_DSCR_STATE_CH4_V 0x3 +#define GDMA_IN_DSCR_STATE_CH4_S 18 +/* GDMA_INLINK_DSCR_ADDR_CH4 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address..*/ +#define GDMA_INLINK_DSCR_ADDR_CH4 0x0003FFFF +#define GDMA_INLINK_DSCR_ADDR_CH4_M ((GDMA_INLINK_DSCR_ADDR_CH4_V)<<(GDMA_INLINK_DSCR_ADDR_CH4_S)) +#define GDMA_INLINK_DSCR_ADDR_CH4_V 0x3FFFF +#define GDMA_INLINK_DSCR_ADDR_CH4_S 0 + +#define GDMA_IN_SUC_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x328) +/* GDMA_IN_SUC_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when the EOF bit in th +is descriptor is 1..*/ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH4 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH4_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH4_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH4_S)) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH4_V 0xFFFFFFFF +#define GDMA_IN_SUC_EOF_DES_ADDR_CH4_S 0 + +#define GDMA_IN_ERR_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x32C) +/* GDMA_IN_ERR_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when there are some er +rors in current receiving data. Only used when peripheral is UHCI0..*/ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH4 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH4_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH4_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH4_S)) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH4_V 0xFFFFFFFF +#define GDMA_IN_ERR_EOF_DES_ADDR_CH4_S 0 + +#define GDMA_IN_DSCR_CH4_REG (DR_REG_GDMA_BASE + 0x330) +/* GDMA_INLINK_DSCR_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x..*/ +#define GDMA_INLINK_DSCR_CH4 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH4_M ((GDMA_INLINK_DSCR_CH4_V)<<(GDMA_INLINK_DSCR_CH4_S)) +#define GDMA_INLINK_DSCR_CH4_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_CH4_S 0 + +#define GDMA_IN_DSCR_BF0_CH4_REG (DR_REG_GDMA_BASE + 0x334) +/* GDMA_INLINK_DSCR_BF0_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1..*/ +#define GDMA_INLINK_DSCR_BF0_CH4 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH4_M ((GDMA_INLINK_DSCR_BF0_CH4_V)<<(GDMA_INLINK_DSCR_BF0_CH4_S)) +#define GDMA_INLINK_DSCR_BF0_CH4_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF0_CH4_S 0 + +#define GDMA_IN_DSCR_BF1_CH4_REG (DR_REG_GDMA_BASE + 0x338) +/* GDMA_INLINK_DSCR_BF1_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_INLINK_DSCR_BF1_CH4 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH4_M ((GDMA_INLINK_DSCR_BF1_CH4_V)<<(GDMA_INLINK_DSCR_BF1_CH4_S)) +#define GDMA_INLINK_DSCR_BF1_CH4_V 0xFFFFFFFF +#define GDMA_INLINK_DSCR_BF1_CH4_S 0 + +#define GDMA_IN_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x33C) +/* GDMA_RX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Rx channel 4. .*/ +#define GDMA_RX_WEIGHT_CH4 0x0000000F +#define GDMA_RX_WEIGHT_CH4_M ((GDMA_RX_WEIGHT_CH4_V)<<(GDMA_RX_WEIGHT_CH4_S)) +#define GDMA_RX_WEIGHT_CH4_V 0xF +#define GDMA_RX_WEIGHT_CH4_S 8 + +#define GDMA_IN_PRI_CH4_REG (DR_REG_GDMA_BASE + 0x344) +/* GDMA_RX_PRI_CH4 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 4. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_RX_PRI_CH4 0x0000000F +#define GDMA_RX_PRI_CH4_M ((GDMA_RX_PRI_CH4_V)<<(GDMA_RX_PRI_CH4_S)) +#define GDMA_RX_PRI_CH4_V 0xF +#define GDMA_RX_PRI_CH4_S 0 + +#define GDMA_IN_PERI_SEL_CH4_REG (DR_REG_GDMA_BASE + 0x348) +/* GDMA_PERI_IN_SEL_CH4 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Rx channel 5. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_IN_SEL_CH4 0x0000003F +#define GDMA_PERI_IN_SEL_CH4_M ((GDMA_PERI_IN_SEL_CH4_V)<<(GDMA_PERI_IN_SEL_CH4_S)) +#define GDMA_PERI_IN_SEL_CH4_V 0x3F +#define GDMA_PERI_IN_SEL_CH4_S 0 + +#define GDMA_OUT_CONF0_CH4_REG (DR_REG_GDMA_BASE + 0x360) +/* GDMA_OUT_DATA_BURST_EN_CH4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 transmitting da +ta when accessing internal SRAM. .*/ +#define GDMA_OUT_DATA_BURST_EN_CH4 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH4_M (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH4_V 0x1 +#define GDMA_OUT_DATA_BURST_EN_CH4_S 5 +/* GDMA_OUTDSCR_BURST_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 reading link de +scriptor when accessing internal SRAM. .*/ +#define GDMA_OUTDSCR_BURST_EN_CH4 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH4_M (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH4_V 0x1 +#define GDMA_OUTDSCR_BURST_EN_CH4_S 4 +/* GDMA_OUT_EOF_MODE_CH4 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 4 is + generated when data need to transmit has been popped from FIFO in DMA.*/ +#define GDMA_OUT_EOF_MODE_CH4 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH4_M (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH4_V 0x1 +#define GDMA_OUT_EOF_MODE_CH4_S 3 +/* GDMA_OUT_AUTO_WRBACK_CH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe +r has been transmitted..*/ +#define GDMA_OUT_AUTO_WRBACK_CH4 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH4_M (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH4_V 0x1 +#define GDMA_OUT_AUTO_WRBACK_CH4_S 2 +/* GDMA_OUT_LOOP_TEST_CH4 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_LOOP_TEST_CH4 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH4_M (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH4_V 0x1 +#define GDMA_OUT_LOOP_TEST_CH4_S 1 +/* GDMA_OUT_RST_CH4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 4 Tx FSM and Tx FIFO pointer..*/ +#define GDMA_OUT_RST_CH4 (BIT(0)) +#define GDMA_OUT_RST_CH4_M (BIT(0)) +#define GDMA_OUT_RST_CH4_V 0x1 +#define GDMA_OUT_RST_CH4_S 0 + +#define GDMA_OUT_CONF1_CH4_REG (DR_REG_GDMA_BASE + 0x364) +/* GDMA_OUT_EXT_MEM_BK_SIZE_CH4 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 4 when DMA access external SRAM. 0: 16 bytes 1: 32 + bytes 2/3:reserved.*/ +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH4 0x00000003 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH4_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH4_V)<<(GDMA_OUT_EXT_MEM_BK_SIZE_CH4_S)) +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH4_V 0x3 +#define GDMA_OUT_EXT_MEM_BK_SIZE_CH4_S 13 +/* GDMA_OUT_CHECK_OWNER_CH4 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ +#define GDMA_OUT_CHECK_OWNER_CH4 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH4_M (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH4_V 0x1 +#define GDMA_OUT_CHECK_OWNER_CH4_S 12 + +#define GDMA_OUT_INT_RAW_CH4_REG (DR_REG_GDMA_BASE + 0x368) +/* GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 4 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_RAW_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 4 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_RAW_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 4 is +underflow. .*/ +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_RAW_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 4 is +overflow. .*/ +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S 4 +/* GDMA_OUT_TOTAL_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc +ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +nnel 4..*/ +#define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_S 3 +/* GDMA_OUT_DSCR_ERR_CH4_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +r, including owner error, the second and third word error of outlink descriptor +for Tx channel 4..*/ +#define GDMA_OUT_DSCR_ERR_CH4_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_S 2 +/* GDMA_OUT_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been read from memory for Tx channel 4. .*/ +#define GDMA_OUT_EOF_CH4_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH4_INT_RAW_M (BIT(1)) +#define GDMA_OUT_EOF_CH4_INT_RAW_V 0x1 +#define GDMA_OUT_EOF_CH4_INT_RAW_S 1 +/* GDMA_OUT_DONE_CH4_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data pointed by one outl +ink descriptor has been transmitted to peripherals for Tx channel 4..*/ +#define GDMA_OUT_DONE_CH4_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH4_INT_RAW_M (BIT(0)) +#define GDMA_OUT_DONE_CH4_INT_RAW_V 0x1 +#define GDMA_OUT_DONE_CH4_INT_RAW_S 0 + +#define GDMA_OUT_INT_ST_CH4_REG (DR_REG_GDMA_BASE + 0x36C) +/* GDMA_OUTFIFO_UDF_L3_CH4_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ST (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ST_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ST_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH4_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ST (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ST_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ST_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH4_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ST_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ST_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ST_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ST_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ST_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ST_S 4 +/* GDMA_OUT_TOTAL_EOF_CH4_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH4_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH4_INT_ST_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH4_INT_ST_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH4_INT_ST_S 3 +/* GDMA_OUT_DSCR_ERR_CH4_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH4_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH4_INT_ST_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH4_INT_ST_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH4_INT_ST_S 2 +/* GDMA_OUT_EOF_CH4_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH4_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH4_INT_ST_M (BIT(1)) +#define GDMA_OUT_EOF_CH4_INT_ST_V 0x1 +#define GDMA_OUT_EOF_CH4_INT_ST_S 1 +/* GDMA_OUT_DONE_CH4_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH4_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH4_INT_ST_M (BIT(0)) +#define GDMA_OUT_DONE_CH4_INT_ST_V 0x1 +#define GDMA_OUT_DONE_CH4_INT_ST_S 0 + +#define GDMA_OUT_INT_ENA_CH4_REG (DR_REG_GDMA_BASE + 0x370) +/* GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_ENA_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_ENA_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_ENA_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_ENA_S 4 +/* GDMA_OUT_TOTAL_EOF_CH4_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH4_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH4_INT_ENA_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH4_INT_ENA_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH4_INT_ENA_S 3 +/* GDMA_OUT_DSCR_ERR_CH4_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH4_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH4_INT_ENA_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH4_INT_ENA_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH4_INT_ENA_S 2 +/* GDMA_OUT_EOF_CH4_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH4_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH4_INT_ENA_M (BIT(1)) +#define GDMA_OUT_EOF_CH4_INT_ENA_V 0x1 +#define GDMA_OUT_EOF_CH4_INT_ENA_S 1 +/* GDMA_OUT_DONE_CH4_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH4_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH4_INT_ENA_M (BIT(0)) +#define GDMA_OUT_DONE_CH4_INT_ENA_V 0x1 +#define GDMA_OUT_DONE_CH4_INT_ENA_S 0 + +#define GDMA_OUT_INT_CLR_CH4_REG (DR_REG_GDMA_BASE + 0x374) +/* GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR_M (BIT(7)) +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L3_CH4_INT_CLR_S 7 +/* GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR_M (BIT(6)) +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L3_CH4_INT_CLR_S 6 +/* GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR_M (BIT(5)) +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_UDF_L1_CH4_INT_CLR_S 5 +/* GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt..*/ +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR_M (BIT(4)) +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR_V 0x1 +#define GDMA_OUTFIFO_OVF_L1_CH4_INT_CLR_S 4 +/* GDMA_OUT_TOTAL_EOF_CH4_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_TOTAL_EOF_CH4_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH4_INT_CLR_M (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH4_INT_CLR_V 0x1 +#define GDMA_OUT_TOTAL_EOF_CH4_INT_CLR_S 3 +/* GDMA_OUT_DSCR_ERR_CH4_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt..*/ +#define GDMA_OUT_DSCR_ERR_CH4_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH4_INT_CLR_M (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH4_INT_CLR_V 0x1 +#define GDMA_OUT_DSCR_ERR_CH4_INT_CLR_S 2 +/* GDMA_OUT_EOF_CH4_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt..*/ +#define GDMA_OUT_EOF_CH4_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH4_INT_CLR_M (BIT(1)) +#define GDMA_OUT_EOF_CH4_INT_CLR_V 0x1 +#define GDMA_OUT_EOF_CH4_INT_CLR_S 1 +/* GDMA_OUT_DONE_CH4_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt..*/ +#define GDMA_OUT_DONE_CH4_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH4_INT_CLR_M (BIT(0)) +#define GDMA_OUT_DONE_CH4_INT_CLR_V 0x1 +#define GDMA_OUT_DONE_CH4_INT_CLR_S 0 + +#define GDMA_OUTFIFO_STATUS_CH4_REG (DR_REG_GDMA_BASE + 0x378) +/* GDMA_OUT_REMAIN_UNDER_4B_L3_CH4 : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH4 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH4_M (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH4_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_4B_L3_CH4_S 26 +/* GDMA_OUT_REMAIN_UNDER_3B_L3_CH4 : RO ;bitpos:[25] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH4 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH4_M (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH4_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_3B_L3_CH4_S 25 +/* GDMA_OUT_REMAIN_UNDER_2B_L3_CH4 : RO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH4 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH4_M (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH4_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_2B_L3_CH4_S 24 +/* GDMA_OUT_REMAIN_UNDER_1B_L3_CH4 : RO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: reserved.*/ +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH4 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH4_M (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH4_V 0x1 +#define GDMA_OUT_REMAIN_UNDER_1B_L3_CH4_S 23 +/* GDMA_OUTFIFO_CNT_L3_CH4 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 4..*/ +#define GDMA_OUTFIFO_CNT_L3_CH4 0x0000001F +#define GDMA_OUTFIFO_CNT_L3_CH4_M ((GDMA_OUTFIFO_CNT_L3_CH4_V)<<(GDMA_OUTFIFO_CNT_L3_CH4_S)) +#define GDMA_OUTFIFO_CNT_L3_CH4_V 0x1F +#define GDMA_OUTFIFO_CNT_L3_CH4_S 18 +/* GDMA_OUTFIFO_CNT_L2_CH4 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 4..*/ +#define GDMA_OUTFIFO_CNT_L2_CH4 0x0000007F +#define GDMA_OUTFIFO_CNT_L2_CH4_M ((GDMA_OUTFIFO_CNT_L2_CH4_V)<<(GDMA_OUTFIFO_CNT_L2_CH4_S)) +#define GDMA_OUTFIFO_CNT_L2_CH4_V 0x7F +#define GDMA_OUTFIFO_CNT_L2_CH4_S 11 +/* GDMA_OUTFIFO_CNT_L1_CH4 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 4..*/ +#define GDMA_OUTFIFO_CNT_L1_CH4 0x0000001F +#define GDMA_OUTFIFO_CNT_L1_CH4_M ((GDMA_OUTFIFO_CNT_L1_CH4_V)<<(GDMA_OUTFIFO_CNT_L1_CH4_S)) +#define GDMA_OUTFIFO_CNT_L1_CH4_V 0x1F +#define GDMA_OUTFIFO_CNT_L1_CH4_S 6 +/* GDMA_OUTFIFO_EMPTY_L3_CH4 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 4..*/ +#define GDMA_OUTFIFO_EMPTY_L3_CH4 (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH4_M (BIT(5)) +#define GDMA_OUTFIFO_EMPTY_L3_CH4_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L3_CH4_S 5 +/* GDMA_OUTFIFO_FULL_L3_CH4 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 4..*/ +#define GDMA_OUTFIFO_FULL_L3_CH4 (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH4_M (BIT(4)) +#define GDMA_OUTFIFO_FULL_L3_CH4_V 0x1 +#define GDMA_OUTFIFO_FULL_L3_CH4_S 4 +/* GDMA_OUTFIFO_EMPTY_L2_CH4 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 4..*/ +#define GDMA_OUTFIFO_EMPTY_L2_CH4 (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH4_M (BIT(3)) +#define GDMA_OUTFIFO_EMPTY_L2_CH4_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L2_CH4_S 3 +/* GDMA_OUTFIFO_FULL_L2_CH4 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 4..*/ +#define GDMA_OUTFIFO_FULL_L2_CH4 (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH4_M (BIT(2)) +#define GDMA_OUTFIFO_FULL_L2_CH4_V 0x1 +#define GDMA_OUTFIFO_FULL_L2_CH4_S 2 +/* GDMA_OUTFIFO_EMPTY_L1_CH4 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 4..*/ +#define GDMA_OUTFIFO_EMPTY_L1_CH4 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH4_M (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_L1_CH4_V 0x1 +#define GDMA_OUTFIFO_EMPTY_L1_CH4_S 1 +/* GDMA_OUTFIFO_FULL_L1_CH4 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 4..*/ +#define GDMA_OUTFIFO_FULL_L1_CH4 (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH4_M (BIT(0)) +#define GDMA_OUTFIFO_FULL_L1_CH4_V 0x1 +#define GDMA_OUTFIFO_FULL_L1_CH4_S 0 + +#define GDMA_OUT_PUSH_CH4_REG (DR_REG_GDMA_BASE + 0x37C) +/* GDMA_OUTFIFO_PUSH_CH4 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO..*/ +#define GDMA_OUTFIFO_PUSH_CH4 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH4_M (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH4_V 0x1 +#define GDMA_OUTFIFO_PUSH_CH4_S 9 +/* GDMA_OUTFIFO_WDATA_CH4 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO..*/ +#define GDMA_OUTFIFO_WDATA_CH4 0x000001FF +#define GDMA_OUTFIFO_WDATA_CH4_M ((GDMA_OUTFIFO_WDATA_CH4_V)<<(GDMA_OUTFIFO_WDATA_CH4_S)) +#define GDMA_OUTFIFO_WDATA_CH4_V 0x1FF +#define GDMA_OUTFIFO_WDATA_CH4_S 0 + +#define GDMA_OUT_LINK_CH4_REG (DR_REG_GDMA_BASE + 0x380) +/* GDMA_OUTLINK_PARK_CH4 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F +SM is working..*/ +#define GDMA_OUTLINK_PARK_CH4 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH4_M (BIT(23)) +#define GDMA_OUTLINK_PARK_CH4_V 0x1 +#define GDMA_OUTLINK_PARK_CH4_S 23 +/* GDMA_OUTLINK_RESTART_CH4 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address. .*/ +#define GDMA_OUTLINK_RESTART_CH4 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH4_M (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH4_V 0x1 +#define GDMA_OUTLINK_RESTART_CH4_S 22 +/* GDMA_OUTLINK_START_CH4 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_START_CH4 (BIT(21)) +#define GDMA_OUTLINK_START_CH4_M (BIT(21)) +#define GDMA_OUTLINK_START_CH4_V 0x1 +#define GDMA_OUTLINK_START_CH4_S 21 +/* GDMA_OUTLINK_STOP_CH4 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors..*/ +#define GDMA_OUTLINK_STOP_CH4 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH4_M (BIT(20)) +#define GDMA_OUTLINK_STOP_CH4_V 0x1 +#define GDMA_OUTLINK_STOP_CH4_S 20 +/* GDMA_OUTLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first outlink descript +or's address..*/ +#define GDMA_OUTLINK_ADDR_CH4 0x000FFFFF +#define GDMA_OUTLINK_ADDR_CH4_M ((GDMA_OUTLINK_ADDR_CH4_V)<<(GDMA_OUTLINK_ADDR_CH4_S)) +#define GDMA_OUTLINK_ADDR_CH4_V 0xFFFFF +#define GDMA_OUTLINK_ADDR_CH4_S 0 + +#define GDMA_OUT_STATE_CH4_REG (DR_REG_GDMA_BASE + 0x384) +/* GDMA_OUT_STATE_CH4 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_STATE_CH4 0x00000007 +#define GDMA_OUT_STATE_CH4_M ((GDMA_OUT_STATE_CH4_V)<<(GDMA_OUT_STATE_CH4_S)) +#define GDMA_OUT_STATE_CH4_V 0x7 +#define GDMA_OUT_STATE_CH4_S 20 +/* GDMA_OUT_DSCR_STATE_CH4 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_OUT_DSCR_STATE_CH4 0x00000003 +#define GDMA_OUT_DSCR_STATE_CH4_M ((GDMA_OUT_DSCR_STATE_CH4_V)<<(GDMA_OUT_DSCR_STATE_CH4_S)) +#define GDMA_OUT_DSCR_STATE_CH4_V 0x3 +#define GDMA_OUT_DSCR_STATE_CH4_S 18 +/* GDMA_OUTLINK_DSCR_ADDR_CH4 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address..*/ +#define GDMA_OUTLINK_DSCR_ADDR_CH4 0x0003FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH4_M ((GDMA_OUTLINK_DSCR_ADDR_CH4_V)<<(GDMA_OUTLINK_DSCR_ADDR_CH4_S)) +#define GDMA_OUTLINK_DSCR_ADDR_CH4_V 0x3FFFF +#define GDMA_OUTLINK_DSCR_ADDR_CH4_S 0 + +#define GDMA_OUT_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x388) +/* GDMA_OUT_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when the EOF bit in t +his descriptor is 1..*/ +#define GDMA_OUT_EOF_DES_ADDR_CH4 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH4_M ((GDMA_OUT_EOF_DES_ADDR_CH4_V)<<(GDMA_OUT_EOF_DES_ADDR_CH4_S)) +#define GDMA_OUT_EOF_DES_ADDR_CH4_V 0xFFFFFFFF +#define GDMA_OUT_EOF_DES_ADDR_CH4_S 0 + +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x38C) +/* GDMA_OUT_EOF_BFR_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before the last outli +nk descriptor..*/ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH4_S)) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V 0xFFFFFFFF +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_S 0 + +#define GDMA_OUT_DSCR_CH4_REG (DR_REG_GDMA_BASE + 0x390) +/* GDMA_OUTLINK_DSCR_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y..*/ +#define GDMA_OUTLINK_DSCR_CH4 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH4_M ((GDMA_OUTLINK_DSCR_CH4_V)<<(GDMA_OUTLINK_DSCR_CH4_S)) +#define GDMA_OUTLINK_DSCR_CH4_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_CH4_S 0 + +#define GDMA_OUT_DSCR_BF0_CH4_REG (DR_REG_GDMA_BASE + 0x394) +/* GDMA_OUTLINK_DSCR_BF0_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1..*/ +#define GDMA_OUTLINK_DSCR_BF0_CH4 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH4_M ((GDMA_OUTLINK_DSCR_BF0_CH4_V)<<(GDMA_OUTLINK_DSCR_BF0_CH4_S)) +#define GDMA_OUTLINK_DSCR_BF0_CH4_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF0_CH4_S 0 + +#define GDMA_OUT_DSCR_BF1_CH4_REG (DR_REG_GDMA_BASE + 0x398) +/* GDMA_OUTLINK_DSCR_BF1_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2..*/ +#define GDMA_OUTLINK_DSCR_BF1_CH4 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH4_M ((GDMA_OUTLINK_DSCR_BF1_CH4_V)<<(GDMA_OUTLINK_DSCR_BF1_CH4_S)) +#define GDMA_OUTLINK_DSCR_BF1_CH4_V 0xFFFFFFFF +#define GDMA_OUTLINK_DSCR_BF1_CH4_S 0 + +#define GDMA_OUT_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x39C) +/* GDMA_TX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The weight of Tx channel 4. .*/ +#define GDMA_TX_WEIGHT_CH4 0x0000000F +#define GDMA_TX_WEIGHT_CH4_M ((GDMA_TX_WEIGHT_CH4_V)<<(GDMA_TX_WEIGHT_CH4_S)) +#define GDMA_TX_WEIGHT_CH4_V 0xF +#define GDMA_TX_WEIGHT_CH4_S 8 + +#define GDMA_OUT_PRI_CH4_REG (DR_REG_GDMA_BASE + 0x3A4) /* GDMA_TX_PRI_CH4 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 4. The larger of the value the higher - of the priority.*/ -#define GDMA_TX_PRI_CH4 0x0000000F -#define GDMA_TX_PRI_CH4_M ((GDMA_TX_PRI_CH4_V) << (GDMA_TX_PRI_CH4_S)) -#define GDMA_TX_PRI_CH4_V 0xF -#define GDMA_TX_PRI_CH4_S 0 +/*description: The priority of Tx channel 4. The larger of the value, the higher of the priorit +y..*/ +#define GDMA_TX_PRI_CH4 0x0000000F +#define GDMA_TX_PRI_CH4_M ((GDMA_TX_PRI_CH4_V)<<(GDMA_TX_PRI_CH4_S)) +#define GDMA_TX_PRI_CH4_V 0xF +#define GDMA_TX_PRI_CH4_S 0 -#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x214) -/* GDMA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define GDMA_CLK_EN (BIT(3)) -#define GDMA_CLK_EN_M (BIT(3)) -#define GDMA_CLK_EN_V 0x1 -#define GDMA_CLK_EN_S 3 +#define GDMA_OUT_PERI_SEL_CH4_REG (DR_REG_GDMA_BASE + 0x3A8) +/* GDMA_PERI_OUT_SEL_CH4 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: This register is used to select peripheral for Tx channel 4. 0:SPI2. 1: SPI3. 2: + UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ +#define GDMA_PERI_OUT_SEL_CH4 0x0000003F +#define GDMA_PERI_OUT_SEL_CH4_M ((GDMA_PERI_OUT_SEL_CH4_V)<<(GDMA_PERI_OUT_SEL_CH4_S)) +#define GDMA_PERI_OUT_SEL_CH4_V 0x3F +#define GDMA_PERI_OUT_SEL_CH4_S 0 + +#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x3C0) +/* GDMA_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: reserved.*/ +#define GDMA_AHB_TESTADDR 0x00000003 +#define GDMA_AHB_TESTADDR_M ((GDMA_AHB_TESTADDR_V)<<(GDMA_AHB_TESTADDR_S)) +#define GDMA_AHB_TESTADDR_V 0x3 +#define GDMA_AHB_TESTADDR_S 4 +/* GDMA_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: reserved.*/ +#define GDMA_AHB_TESTMODE 0x00000007 +#define GDMA_AHB_TESTMODE_M ((GDMA_AHB_TESTMODE_V)<<(GDMA_AHB_TESTMODE_S)) +#define GDMA_AHB_TESTMODE_V 0x7 +#define GDMA_AHB_TESTMODE_S 0 + +#define GDMA_PD_CONF_REG (DR_REG_GDMA_BASE + 0x3C4) +/* GDMA_DMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Force to open the clock and bypass the gate-clock when accessing the RAM in D +MA. 0: A gate-clock will be used when accessing the RAM in DMA..*/ +#define GDMA_DMA_RAM_CLK_FO (BIT(6)) +#define GDMA_DMA_RAM_CLK_FO_M (BIT(6)) +#define GDMA_DMA_RAM_CLK_FO_V 0x1 +#define GDMA_DMA_RAM_CLK_FO_S 6 +/* GDMA_DMA_RAM_FORCE_PU : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: .*/ +#define GDMA_DMA_RAM_FORCE_PU (BIT(5)) +#define GDMA_DMA_RAM_FORCE_PU_M (BIT(5)) +#define GDMA_DMA_RAM_FORCE_PU_V 0x1 +#define GDMA_DMA_RAM_FORCE_PU_S 5 +/* GDMA_DMA_RAM_FORCE_PD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: power down.*/ +#define GDMA_DMA_RAM_FORCE_PD (BIT(4)) +#define GDMA_DMA_RAM_FORCE_PD_M (BIT(4)) +#define GDMA_DMA_RAM_FORCE_PD_V 0x1 +#define GDMA_DMA_RAM_FORCE_PD_S 4 + +#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x3C8) +/* GDMA_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define GDMA_CLK_EN (BIT(4)) +#define GDMA_CLK_EN_M (BIT(4)) +#define GDMA_CLK_EN_V 0x1 +#define GDMA_CLK_EN_S 4 /* GDMA_ARB_PRI_DIS : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to disable priority arbitration function.*/ -#define GDMA_ARB_PRI_DIS (BIT(2)) -#define GDMA_ARB_PRI_DIS_M (BIT(2)) -#define GDMA_ARB_PRI_DIS_V 0x1 -#define GDMA_ARB_PRI_DIS_S 2 +/*description: Set this bit to disable priority arbitration function..*/ +#define GDMA_ARB_PRI_DIS (BIT(2)) +#define GDMA_ARB_PRI_DIS_M (BIT(2)) +#define GDMA_ARB_PRI_DIS_V 0x1 +#define GDMA_ARB_PRI_DIS_S 2 /* GDMA_AHBM_RST_EXTER : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit then clear this bit to reset the external ahb FSM.*/ -#define GDMA_AHBM_RST_EXTER (BIT(1)) -#define GDMA_AHBM_RST_EXTER_M (BIT(1)) -#define GDMA_AHBM_RST_EXTER_V 0x1 -#define GDMA_AHBM_RST_EXTER_S 1 +/*description: Set this bit, then clear this bit to reset the external ahb FSM..*/ +#define GDMA_AHBM_RST_EXTER (BIT(1)) +#define GDMA_AHBM_RST_EXTER_M (BIT(1)) +#define GDMA_AHBM_RST_EXTER_V 0x1 +#define GDMA_AHBM_RST_EXTER_S 1 /* GDMA_AHBM_RST_INTER : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit then clear this bit to reset the internal ahb FSM.*/ -#define GDMA_AHBM_RST_INTER (BIT(0)) -#define GDMA_AHBM_RST_INTER_M (BIT(0)) -#define GDMA_AHBM_RST_INTER_V 0x1 -#define GDMA_AHBM_RST_INTER_S 0 +/*description: Set this bit, then clear this bit to reset the internal ahb FSM..*/ +#define GDMA_AHBM_RST_INTER (BIT(0)) +#define GDMA_AHBM_RST_INTER_M (BIT(0)) +#define GDMA_AHBM_RST_INTER_V 0x1 +#define GDMA_AHBM_RST_INTER_S 0 -#define GDMA_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x218) -/* GDMA_PERI_OUT_SEL_CH0 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Tx channel 0. 0:SPI2*/ -#define GDMA_PERI_OUT_SEL_CH0 0x0000003F -#define GDMA_PERI_OUT_SEL_CH0_M ((GDMA_PERI_OUT_SEL_CH0_V) << (GDMA_PERI_OUT_SEL_CH0_S)) -#define GDMA_PERI_OUT_SEL_CH0_V 0x3F -#define GDMA_PERI_OUT_SEL_CH0_S 6 -/* GDMA_PERI_IN_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Rx channel 0. 0:SPI2*/ -#define GDMA_PERI_IN_SEL_CH0 0x0000003F -#define GDMA_PERI_IN_SEL_CH0_M ((GDMA_PERI_IN_SEL_CH0_V) << (GDMA_PERI_IN_SEL_CH0_S)) -#define GDMA_PERI_IN_SEL_CH0_V 0x3F -#define GDMA_PERI_IN_SEL_CH0_S 0 +#define GDMA_IN_SRAM_SIZE_CH0_REG (DR_REG_GDMA_BASE + 0x3CC) +/* GDMA_IN_SIZE_CH0 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_IN_SIZE_CH0 0x0000007F +#define GDMA_IN_SIZE_CH0_M ((GDMA_IN_SIZE_CH0_V)<<(GDMA_IN_SIZE_CH0_S)) +#define GDMA_IN_SIZE_CH0_V 0x7F +#define GDMA_IN_SIZE_CH0_S 0 -#define GDMA_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x21C) -/* GDMA_PERI_OUT_SEL_CH1 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Tx channel 1. 0:SPI2*/ -#define GDMA_PERI_OUT_SEL_CH1 0x0000003F -#define GDMA_PERI_OUT_SEL_CH1_M ((GDMA_PERI_OUT_SEL_CH1_V) << (GDMA_PERI_OUT_SEL_CH1_S)) -#define GDMA_PERI_OUT_SEL_CH1_V 0x3F -#define GDMA_PERI_OUT_SEL_CH1_S 6 -/* GDMA_PERI_IN_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Rx channel 1. 0:SPI2*/ -#define GDMA_PERI_IN_SEL_CH1 0x0000003F -#define GDMA_PERI_IN_SEL_CH1_M ((GDMA_PERI_IN_SEL_CH1_V) << (GDMA_PERI_IN_SEL_CH1_S)) -#define GDMA_PERI_IN_SEL_CH1_V 0x3F -#define GDMA_PERI_IN_SEL_CH1_S 0 +#define GDMA_OUT_SRAM_SIZE_CH0_REG (DR_REG_GDMA_BASE + 0x3D0) +/* GDMA_OUT_SIZE_CH0 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_OUT_SIZE_CH0 0x0000007F +#define GDMA_OUT_SIZE_CH0_M ((GDMA_OUT_SIZE_CH0_V)<<(GDMA_OUT_SIZE_CH0_S)) +#define GDMA_OUT_SIZE_CH0_V 0x7F +#define GDMA_OUT_SIZE_CH0_S 0 -#define GDMA_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) -/* GDMA_PERI_OUT_SEL_CH2 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Tx channel 2. 0:SPI2*/ -#define GDMA_PERI_OUT_SEL_CH2 0x0000003F -#define GDMA_PERI_OUT_SEL_CH2_M ((GDMA_PERI_OUT_SEL_CH2_V) << (GDMA_PERI_OUT_SEL_CH2_S)) -#define GDMA_PERI_OUT_SEL_CH2_V 0x3F -#define GDMA_PERI_OUT_SEL_CH2_S 6 -/* GDMA_PERI_IN_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Rx channel 2. 0:SPI2*/ -#define GDMA_PERI_IN_SEL_CH2 0x0000003F -#define GDMA_PERI_IN_SEL_CH2_M ((GDMA_PERI_IN_SEL_CH2_V) << (GDMA_PERI_IN_SEL_CH2_S)) -#define GDMA_PERI_IN_SEL_CH2_V 0x3F -#define GDMA_PERI_IN_SEL_CH2_S 0 +#define GDMA_IN_SRAM_SIZE_CH1_REG (DR_REG_GDMA_BASE + 0x3D4) +/* GDMA_IN_SIZE_CH1 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Rx channel 1. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_IN_SIZE_CH1 0x0000007F +#define GDMA_IN_SIZE_CH1_M ((GDMA_IN_SIZE_CH1_V)<<(GDMA_IN_SIZE_CH1_S)) +#define GDMA_IN_SIZE_CH1_V 0x7F +#define GDMA_IN_SIZE_CH1_S 0 -#define GDMA_PERI_SEL_CH3_REG (DR_REG_GDMA_BASE + 0x224) -/* GDMA_PERI_OUT_SEL_CH3 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Tx channel 3. 0:SPI2*/ -#define GDMA_PERI_OUT_SEL_CH3 0x0000003F -#define GDMA_PERI_OUT_SEL_CH3_M ((GDMA_PERI_OUT_SEL_CH3_V) << (GDMA_PERI_OUT_SEL_CH3_S)) -#define GDMA_PERI_OUT_SEL_CH3_V 0x3F -#define GDMA_PERI_OUT_SEL_CH3_S 6 -/* GDMA_PERI_IN_SEL_CH3 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Rx channel 3. 0:SPI2*/ -#define GDMA_PERI_IN_SEL_CH3 0x0000003F -#define GDMA_PERI_IN_SEL_CH3_M ((GDMA_PERI_IN_SEL_CH3_V) << (GDMA_PERI_IN_SEL_CH3_S)) -#define GDMA_PERI_IN_SEL_CH3_V 0x3F -#define GDMA_PERI_IN_SEL_CH3_S 0 +#define GDMA_OUT_SRAM_SIZE_CH1_REG (DR_REG_GDMA_BASE + 0x3D8) +/* GDMA_OUT_SIZE_CH1 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Tx channel 1. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_OUT_SIZE_CH1 0x0000007F +#define GDMA_OUT_SIZE_CH1_M ((GDMA_OUT_SIZE_CH1_V)<<(GDMA_OUT_SIZE_CH1_S)) +#define GDMA_OUT_SIZE_CH1_V 0x7F +#define GDMA_OUT_SIZE_CH1_S 0 -#define GDMA_PERI_SEL_CH4_REG (DR_REG_GDMA_BASE + 0x228) -/* GDMA_PERI_OUT_SEL_CH4 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Tx channel 4. 0:SPI2*/ -#define GDMA_PERI_OUT_SEL_CH4 0x0000003F -#define GDMA_PERI_OUT_SEL_CH4_M ((GDMA_PERI_OUT_SEL_CH4_V) << (GDMA_PERI_OUT_SEL_CH4_S)) -#define GDMA_PERI_OUT_SEL_CH4_V 0x3F -#define GDMA_PERI_OUT_SEL_CH4_S 6 -/* GDMA_PERI_IN_SEL_CH4 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Rx channel 4. 0:SPI2*/ -#define GDMA_PERI_IN_SEL_CH4 0x0000003F -#define GDMA_PERI_IN_SEL_CH4_M ((GDMA_PERI_IN_SEL_CH4_V) << (GDMA_PERI_IN_SEL_CH4_S)) -#define GDMA_PERI_IN_SEL_CH4_V 0x3F -#define GDMA_PERI_IN_SEL_CH4_S 0 +#define GDMA_IN_SRAM_SIZE_CH2_REG (DR_REG_GDMA_BASE + 0x3DC) +/* GDMA_IN_SIZE_CH2 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Rx channel 2. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_IN_SIZE_CH2 0x0000007F +#define GDMA_IN_SIZE_CH2_M ((GDMA_IN_SIZE_CH2_V)<<(GDMA_IN_SIZE_CH2_S)) +#define GDMA_IN_SIZE_CH2_V 0x7F +#define GDMA_IN_SIZE_CH2_S 0 -#define GDMA_SRAM_SIZE_CH0_REG (DR_REG_GDMA_BASE + 0x22C) -/* GDMA_OUT_SIZE_CH0 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Tx FIFO for - Tx channel 0. 0:16 bytes*/ -#define GDMA_OUT_SIZE_CH0 0x0000001F -#define GDMA_OUT_SIZE_CH0_M ((GDMA_OUT_SIZE_CH0_V) << (GDMA_OUT_SIZE_CH0_S)) -#define GDMA_OUT_SIZE_CH0_V 0x1F -#define GDMA_OUT_SIZE_CH0_S 5 -/* GDMA_IN_SIZE_CH0 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Rx FIFO for - Rx channel 0. 0:16 bytes*/ -#define GDMA_IN_SIZE_CH0 0x0000001F -#define GDMA_IN_SIZE_CH0_M ((GDMA_IN_SIZE_CH0_V) << (GDMA_IN_SIZE_CH0_S)) -#define GDMA_IN_SIZE_CH0_V 0x1F -#define GDMA_IN_SIZE_CH0_S 0 +#define GDMA_OUT_SRAM_SIZE_CH2_REG (DR_REG_GDMA_BASE + 0x3E0) +/* GDMA_OUT_SIZE_CH2 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Tx channel 2. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_OUT_SIZE_CH2 0x0000007F +#define GDMA_OUT_SIZE_CH2_M ((GDMA_OUT_SIZE_CH2_V)<<(GDMA_OUT_SIZE_CH2_S)) +#define GDMA_OUT_SIZE_CH2_V 0x7F +#define GDMA_OUT_SIZE_CH2_S 0 -#define GDMA_SRAM_SIZE_CH1_REG (DR_REG_GDMA_BASE + 0x230) -/* GDMA_OUT_SIZE_CH1 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Tx FIFO for - Tx channel 1. 0:16 bytes*/ -#define GDMA_OUT_SIZE_CH1 0x0000001F -#define GDMA_OUT_SIZE_CH1_M ((GDMA_OUT_SIZE_CH1_V) << (GDMA_OUT_SIZE_CH1_S)) -#define GDMA_OUT_SIZE_CH1_V 0x1F -#define GDMA_OUT_SIZE_CH1_S 5 -/* GDMA_IN_SIZE_CH1 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Rx FIFO for - Rx channel 1. 0:16 bytes*/ -#define GDMA_IN_SIZE_CH1 0x0000001F -#define GDMA_IN_SIZE_CH1_M ((GDMA_IN_SIZE_CH1_V) << (GDMA_IN_SIZE_CH1_S)) -#define GDMA_IN_SIZE_CH1_V 0x1F -#define GDMA_IN_SIZE_CH1_S 0 +#define GDMA_IN_SRAM_SIZE_CH3_REG (DR_REG_GDMA_BASE + 0x3E4) +/* GDMA_IN_SIZE_CH3 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Rx channel 3. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_IN_SIZE_CH3 0x0000007F +#define GDMA_IN_SIZE_CH3_M ((GDMA_IN_SIZE_CH3_V)<<(GDMA_IN_SIZE_CH3_S)) +#define GDMA_IN_SIZE_CH3_V 0x7F +#define GDMA_IN_SIZE_CH3_S 0 -#define GDMA_SRAM_SIZE_CH2_REG (DR_REG_GDMA_BASE + 0x234) -/* GDMA_OUT_SIZE_CH2 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Tx FIFO for - Tx channel 2. 0:16 bytes*/ -#define GDMA_OUT_SIZE_CH2 0x0000001F -#define GDMA_OUT_SIZE_CH2_M ((GDMA_OUT_SIZE_CH2_V) << (GDMA_OUT_SIZE_CH2_S)) -#define GDMA_OUT_SIZE_CH2_V 0x1F -#define GDMA_OUT_SIZE_CH2_S 5 -/* GDMA_IN_SIZE_CH2 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Rx FIFO for - Rx channel 2. 0:16 bytes*/ -#define GDMA_IN_SIZE_CH2 0x0000001F -#define GDMA_IN_SIZE_CH2_M ((GDMA_IN_SIZE_CH2_V) << (GDMA_IN_SIZE_CH2_S)) -#define GDMA_IN_SIZE_CH2_V 0x1F -#define GDMA_IN_SIZE_CH2_S 0 +#define GDMA_OUT_SRAM_SIZE_CH3_REG (DR_REG_GDMA_BASE + 0x3E8) +/* GDMA_OUT_SIZE_CH3 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Tx channel 3. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_OUT_SIZE_CH3 0x0000007F +#define GDMA_OUT_SIZE_CH3_M ((GDMA_OUT_SIZE_CH3_V)<<(GDMA_OUT_SIZE_CH3_S)) +#define GDMA_OUT_SIZE_CH3_V 0x7F +#define GDMA_OUT_SIZE_CH3_S 0 -#define GDMA_SRAM_SIZE_CH3_REG (DR_REG_GDMA_BASE + 0x238) -/* GDMA_OUT_SIZE_CH3 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Tx FIFO for - Tx channel 3. 0:16 bytes*/ -#define GDMA_OUT_SIZE_CH3 0x0000001F -#define GDMA_OUT_SIZE_CH3_M ((GDMA_OUT_SIZE_CH3_V) << (GDMA_OUT_SIZE_CH3_S)) -#define GDMA_OUT_SIZE_CH3_V 0x1F -#define GDMA_OUT_SIZE_CH3_S 5 -/* GDMA_IN_SIZE_CH3 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Rx FIFO for - Rx channel 3. 0:16 bytes*/ -#define GDMA_IN_SIZE_CH3 0x0000001F -#define GDMA_IN_SIZE_CH3_M ((GDMA_IN_SIZE_CH3_V) << (GDMA_IN_SIZE_CH3_S)) -#define GDMA_IN_SIZE_CH3_V 0x1F -#define GDMA_IN_SIZE_CH3_S 0 +#define GDMA_IN_SRAM_SIZE_CH4_REG (DR_REG_GDMA_BASE + 0x3EC) +/* GDMA_IN_SIZE_CH4 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Rx channel 4. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_IN_SIZE_CH4 0x0000007F +#define GDMA_IN_SIZE_CH4_M ((GDMA_IN_SIZE_CH4_V)<<(GDMA_IN_SIZE_CH4_S)) +#define GDMA_IN_SIZE_CH4_V 0x7F +#define GDMA_IN_SIZE_CH4_S 0 -#define GDMA_SRAM_SIZE_CH4_REG (DR_REG_GDMA_BASE + 0x23C) -/* GDMA_OUT_SIZE_CH4 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Tx FIFO for - Tx channel 4. 0:16 bytes*/ -#define GDMA_OUT_SIZE_CH4 0x0000001F -#define GDMA_OUT_SIZE_CH4_M ((GDMA_OUT_SIZE_CH4_V) << (GDMA_OUT_SIZE_CH4_S)) -#define GDMA_OUT_SIZE_CH4_V 0x1F -#define GDMA_OUT_SIZE_CH4_S 5 -/* GDMA_IN_SIZE_CH4 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This register is used to configure the size of L2 Rx FIFO for - Rx channel 4. 0:16 bytes*/ -#define GDMA_IN_SIZE_CH4 0x0000001F -#define GDMA_IN_SIZE_CH4_M ((GDMA_IN_SIZE_CH4_V) << (GDMA_IN_SIZE_CH4_S)) -#define GDMA_IN_SIZE_CH4_V 0x1F -#define GDMA_IN_SIZE_CH4_S 0 +#define GDMA_OUT_SRAM_SIZE_CH4_REG (DR_REG_GDMA_BASE + 0x3F0) +/* GDMA_OUT_SIZE_CH4 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for Tx channel 4. 0:16 + bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 byte +s. 7: 72 bytes. 8: 80 bytes..*/ +#define GDMA_OUT_SIZE_CH4 0x0000007F +#define GDMA_OUT_SIZE_CH4_M ((GDMA_OUT_SIZE_CH4_V)<<(GDMA_OUT_SIZE_CH4_S)) +#define GDMA_OUT_SIZE_CH4_V 0x7F +#define GDMA_OUT_SIZE_CH4_S 0 + +#define GDMA_EXTMEM_REJECT_ADDR_REG (DR_REG_GDMA_BASE + 0x3F4) +/* GDMA_EXTMEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: This register store the first address rejected by permission control when access +ing external RAM..*/ +#define GDMA_EXTMEM_REJECT_ADDR 0xFFFFFFFF +#define GDMA_EXTMEM_REJECT_ADDR_M ((GDMA_EXTMEM_REJECT_ADDR_V)<<(GDMA_EXTMEM_REJECT_ADDR_S)) +#define GDMA_EXTMEM_REJECT_ADDR_V 0xFFFFFFFF +#define GDMA_EXTMEM_REJECT_ADDR_S 0 + +#define GDMA_EXTMEM_REJECT_ST_REG (DR_REG_GDMA_BASE + 0x3F8) +/* GDMA_EXTMEM_REJECT_PERI_NUM : RO ;bitpos:[11:6] ;default: 6'b0 ; */ +/*description: This register indicate reject accessing from which peripheral..*/ +#define GDMA_EXTMEM_REJECT_PERI_NUM 0x0000003F +#define GDMA_EXTMEM_REJECT_PERI_NUM_M ((GDMA_EXTMEM_REJECT_PERI_NUM_V)<<(GDMA_EXTMEM_REJECT_PERI_NUM_S)) +#define GDMA_EXTMEM_REJECT_PERI_NUM_V 0x3F +#define GDMA_EXTMEM_REJECT_PERI_NUM_S 6 +/* GDMA_EXTMEM_REJECT_CHANNEL_NUM : RO ;bitpos:[5:2] ;default: 4'b0 ; */ +/*description: The register indicate the reject accessing from which channel..*/ +#define GDMA_EXTMEM_REJECT_CHANNEL_NUM 0x0000000F +#define GDMA_EXTMEM_REJECT_CHANNEL_NUM_M ((GDMA_EXTMEM_REJECT_CHANNEL_NUM_V)<<(GDMA_EXTMEM_REJECT_CHANNEL_NUM_S)) +#define GDMA_EXTMEM_REJECT_CHANNEL_NUM_V 0xF +#define GDMA_EXTMEM_REJECT_CHANNEL_NUM_S 2 +/* GDMA_EXTMEM_REJECT_ATTR : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: The reject operation. Bit 0 is 1 indicate write data.*/ +#define GDMA_EXTMEM_REJECT_ATTR 0x00000003 +#define GDMA_EXTMEM_REJECT_ATTR_M ((GDMA_EXTMEM_REJECT_ATTR_V)<<(GDMA_EXTMEM_REJECT_ATTR_S)) +#define GDMA_EXTMEM_REJECT_ATTR_V 0x3 +#define GDMA_EXTMEM_REJECT_ATTR_S 0 + +#define GDMA_EXTMEM_REJECT_INT_RAW_REG (DR_REG_GDMA_BASE + 0x3FC) +/* GDMA_EXTMEM_REJECT_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when accessing external RAM is rejecte +d by permission control..*/ +#define GDMA_EXTMEM_REJECT_INT_RAW (BIT(0)) +#define GDMA_EXTMEM_REJECT_INT_RAW_M (BIT(0)) +#define GDMA_EXTMEM_REJECT_INT_RAW_V 0x1 +#define GDMA_EXTMEM_REJECT_INT_RAW_S 0 + +#define GDMA_EXTMEM_REJECT_INT_ST_REG (DR_REG_GDMA_BASE + 0x400) +/* GDMA_EXTMEM_REJECT_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt..*/ +#define GDMA_EXTMEM_REJECT_INT_ST (BIT(0)) +#define GDMA_EXTMEM_REJECT_INT_ST_M (BIT(0)) +#define GDMA_EXTMEM_REJECT_INT_ST_V 0x1 +#define GDMA_EXTMEM_REJECT_INT_ST_S 0 + +#define GDMA_EXTMEM_REJECT_INT_ENA_REG (DR_REG_GDMA_BASE + 0x404) +/* GDMA_EXTMEM_REJECT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the EXTMEM_REJECT_INT interrupt..*/ +#define GDMA_EXTMEM_REJECT_INT_ENA (BIT(0)) +#define GDMA_EXTMEM_REJECT_INT_ENA_M (BIT(0)) +#define GDMA_EXTMEM_REJECT_INT_ENA_V 0x1 +#define GDMA_EXTMEM_REJECT_INT_ENA_S 0 + +#define GDMA_EXTMEM_REJECT_INT_CLR_REG (DR_REG_GDMA_BASE + 0x408) +/* GDMA_EXTMEM_REJECT_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the EXTMEM_REJECT_INT interrupt..*/ +#define GDMA_EXTMEM_REJECT_INT_CLR (BIT(0)) +#define GDMA_EXTMEM_REJECT_INT_CLR_M (BIT(0)) +#define GDMA_EXTMEM_REJECT_INT_CLR_V 0x1 +#define GDMA_EXTMEM_REJECT_INT_CLR_S 0 + +#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x40C) +/* GDMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101080 ; */ +/*description: register version..*/ +#define GDMA_DATE 0xFFFFFFFF +#define GDMA_DATE_M ((GDMA_DATE_V)<<(GDMA_DATE_S)) +#define GDMA_DATE_V 0xFFFFFFFF +#define GDMA_DATE_S 0 -#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x240) -/* GDMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2002260 ; */ -/*description: register version.*/ -#define GDMA_DATE 0xFFFFFFFF -#define GDMA_DATE_M ((GDMA_DATE_V) << (GDMA_DATE_S)) -#define GDMA_DATE_V 0xFFFFFFFF -#define GDMA_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_GDMA_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/gdma_struct.h b/components/soc/esp32s3/include/soc/gdma_struct.h index c2a76bf3ef..9c6582ce0a 100644 --- a/components/soc/esp32s3/include/soc/gdma_struct.h +++ b/components/soc/esp32s3/include/soc/gdma_struct.h @@ -1,4 +1,4 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,312 +13,383 @@ // limitations under the License. #pragma once -#ifdef __cplusplus -extern "C" -{ -#endif - #include + +#ifdef __cplusplus +extern "C" { +#endif + typedef volatile struct { + struct { + union { + struct { + uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ + uint32_t in_loop_test : 1; /*reserved*/ + uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */ + uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */ + uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t dma_infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/ + uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved15 : 17; /*reserved*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/ + uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ + uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/ + uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/ + uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/ + uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/ + uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */ + uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */ + uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. */ + uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. */ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t dma_infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ + uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/ + uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/ + uint32_t in_remain_under_1b_l3 : 1; /*reserved*/ + uint32_t in_remain_under_2b_l3 : 1; /*reserved*/ + uint32_t in_remain_under_3b_l3 : 1; /*reserved*/ + uint32_t in_remain_under_4b_l3 : 1; /*reserved*/ + uint32_t in_buf_hungry : 1; /*reserved*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } infifo_status; + union { + struct { + uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/ + uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/ + uint32_t reserved13 : 19; /*reserved*/ + }; + uint32_t val; + } pop; + union { + struct { + uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ + uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/ + uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/ + uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/ + uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/ + uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ + uint32_t reserved25 : 7; + }; + uint32_t val; + } link; + union { + struct { + uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/ + uint32_t in_dscr_state : 2; /*reserved*/ + uint32_t in_state : 3; /*reserved*/ + uint32_t reserved23 : 9; /*reserved*/ + }; + uint32_t val; + } state; + uint32_t suc_eof_des_addr; + uint32_t err_eof_des_addr; + uint32_t dscr; + uint32_t dscr_bf0; + uint32_t dscr_bf1; + union { + struct { + uint32_t rx_weight : 4; /*The weight of Rx channel 0. */ + uint32_t reserved4 : 28; + }; + uint32_t val; + } wight; + union { + struct { + uint32_t in_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/ + uint32_t reserved5 : 27; + }; + uint32_t val; + } sram_size; + union { + struct { + uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/ + uint32_t reserved4 : 28; + }; + uint32_t val; + } pri; + union { + struct { + uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/ + uint32_t reserved6 : 26; + }; + uint32_t val; + } peri_sel; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + } in[5]; + struct { + union { + struct { + uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ + uint32_t out_loop_test : 1; /*reserved*/ + uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ + uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ + uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */ + uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */ + uint32_t reserved6 : 26; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t reserved0 : 12; + uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved15 : 17; /*reserved*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ + uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */ + uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/ + uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ + uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */ + uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */ + uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. */ + uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. */ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ + uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ + uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/ + uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/ + uint32_t out_remain_under_1b_l3 : 1; /*reserved*/ + uint32_t out_remain_under_2b_l3 : 1; /*reserved*/ + uint32_t out_remain_under_3b_l3 : 1; /*reserved*/ + uint32_t out_remain_under_4b_l3 : 1; /*reserved*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } outfifo_status; + union { + struct { + uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ + uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } push; + union { + struct { + uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ + uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/ + uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/ + uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address. */ + uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ + uint32_t reserved24 : 8; + }; + uint32_t val; + } link; + union { + struct { + uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/ + uint32_t out_dscr_state : 2; /*reserved*/ + uint32_t out_state : 3; /*reserved*/ + uint32_t reserved23 : 9; /*reserved*/ + }; + uint32_t val; + } state; + uint32_t eof_des_addr; + uint32_t eof_bfr_des_addr; + uint32_t dscr; + uint32_t dscr_bf0; + uint32_t dscr_bf1; + union { + struct { + uint32_t tx_weight : 4; /*The weight of Tx channel 0. */ + uint32_t reserved4 : 28; + }; + uint32_t val; + } wight; + union { + struct { + uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/ + uint32_t reserved5 : 27; + }; + uint32_t val; + } sram_size; + union { + struct { + uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/ + uint32_t reserved4 : 28; + }; + uint32_t val; + } pri; + union { + struct { + uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/ + uint32_t reserved6 : 26; + }; + uint32_t val; + } peri_sel; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + } out[5]; union { struct { - uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ - uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ - uint32_t in_loop_test : 1; /*reserved*/ - uint32_t out_loop_test : 1; /*reserved*/ - uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ - uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ - uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/ - uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.*/ - uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/ - uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/ - uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ - uint32_t reserved11 : 21; /*reserved*/ - }; - uint32_t val; - } conf0[5]; - union { - struct { - uint32_t infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/ - uint32_t check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ - uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ - uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ - uint32_t reserved17 : 15; /*reserved*/ - }; - uint32_t val; - } conf1[5]; - union { - struct { - uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/ - uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ - uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ - uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ - uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ - uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ - uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ - uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ - uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ - uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/ - uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/ - uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/ - uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow.*/ - uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow.*/ - uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/ - uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/ - uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow.*/ - uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow.*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } int_raw[5]; - uint32_t reserved_3c; - union { - struct { - uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ - uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } int_st[5]; - union { - struct { - uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ - uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } int_ena[5]; - union { - struct { - uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ - uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } int_clr[5]; - union { - struct { - uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/ - uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/ - uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/ - uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/ - uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/ - uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/ - uint32_t infifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ - uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/ - uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/ - uint32_t in_remain_under_1b_l3 : 1; /*reserved*/ - uint32_t in_remain_under_2b_l3 : 1; /*reserved*/ - uint32_t in_remain_under_3b_l3 : 1; /*reserved*/ - uint32_t in_remain_under_4b_l3 : 1; /*reserved*/ - uint32_t in_buf_hungry : 1; /*reserved*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } infifo_status[5]; - union { - struct { - uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/ - uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/ - uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/ - uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/ - uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/ - uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/ - uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ - uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/ - uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/ - uint32_t out_remain_under_1b_l3 : 1; /*reserved*/ - uint32_t out_remain_under_2b_l3 : 1; /*reserved*/ - uint32_t out_remain_under_3b_l3 : 1; /*reserved*/ - uint32_t out_remain_under_4b_l3 : 1; /*reserved*/ - uint32_t reserved27 : 5; /*reserved*/ - }; - uint32_t val; - } outfifo_status[5]; - union { - struct { - uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ - uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/ - uint32_t reserved10 : 22; /*reserved*/ - }; - uint32_t val; - } out_push[5]; - union { - struct { - uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/ - uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/ - uint32_t reserved13 : 19; /*reserved*/ - }; - uint32_t val; - } in_pop[5]; - union { - struct { - uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ - uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/ - uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/ - uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address.*/ - uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ - uint32_t reserved24 : 8; - }; - uint32_t val; - } out_link[5]; - union { - struct { - uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ - uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ - uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/ - uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/ - uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/ - uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ - uint32_t reserved25 : 7; - }; - uint32_t val; - } in_link[5]; - union { - struct { - uint32_t inlink_dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/ - uint32_t in_dscr_state : 2; /*reserved*/ - uint32_t in_state : 3; /*reserved*/ - uint32_t reserved23 : 9; /*reserved*/ - }; - uint32_t val; - } in_state[5]; - union { - struct { - uint32_t outlink_dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/ - uint32_t out_dscr_state : 2; /*reserved*/ - uint32_t out_state : 3; /*reserved*/ - uint32_t reserved23 : 9; /*reserved*/ - }; - uint32_t val; - } out_state[5]; - uint32_t out_eof_des_addr[5]; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/ - uint32_t in_suc_eof_des_addr[5]; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/ - uint32_t in_err_eof_des_addr[5]; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ - uint32_t out_eof_bfr_des_addr[5]; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/ - union { - struct { - uint32_t ahb_testmode : 3; /*reserved*/ - uint32_t reserved3 : 1; /*reserved*/ - uint32_t ahb_testaddr : 2; /*reserved*/ - uint32_t reserved6 : 26; /*reserved*/ + uint32_t ahb_testmode : 3; /*reserved*/ + uint32_t reserved3 : 1; /*reserved*/ + uint32_t ahb_testaddr : 2; /*reserved*/ + uint32_t reserved6 : 26; /*reserved*/ }; uint32_t val; } ahb_test; - uint32_t in_dscr[5]; /*The address of the current inlink descriptor x.*/ - uint32_t in_dscr_bf0[5]; /*The address of the last inlink descriptor x-1.*/ - uint32_t in_dscr_bf1[5]; /*The address of the second-to-last inlink descriptor x-2.*/ - uint32_t out_dscr[5]; /*The address of the current outlink descriptor y.*/ - uint32_t out_dscr_bf0[5]; /*The address of the last outlink descriptor y-1.*/ - uint32_t out_dscr_bf1[5]; /*The address of the second-to-last inlink descriptor y-2.*/ union { struct { - uint32_t reserved0 : 4; /*reserved*/ - uint32_t ram_force_pd : 1; /*power down*/ - uint32_t ram_force_pu : 1; - uint32_t ram_clk_fo : 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/ - uint32_t reserved7 : 25; /*reserved*/ + uint32_t reserved0 : 4; /*reserved*/ + uint32_t dma_ram_force_pd : 1; /*power down*/ + uint32_t dma_ram_force_pu : 1; + uint32_t dma_ram_clk_fo : 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/ + uint32_t reserved7 : 25; }; uint32_t val; } pd_conf; union { struct { - uint32_t tx_weight : 4; /*The weight of Tx channel 0.*/ - uint32_t rx_weight : 4; /*The weight of Rx channel 0.*/ - uint32_t reserved8 : 24; - }; - uint32_t val; - } wight[5]; - union { - struct { - uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value the higher of the priority.*/ - uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value the higher of the priority.*/ - uint32_t reserved8 : 24; - }; - uint32_t val; - } pri[5]; - union { - struct { - uint32_t ahbm_rst_inter : 1; /*Set this bit then clear this bit to reset the internal ahb FSM.*/ - uint32_t ahbm_rst_exter : 1; /*Set this bit then clear this bit to reset the external ahb FSM.*/ - uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/ - uint32_t clk_en : 1; - uint32_t reserved4 : 28; + uint32_t ahbm_rst_inter : 1; /*Set this bit, then clear this bit to reset the internal ahb FSM.*/ + uint32_t ahbm_rst_exter : 1; /*Set this bit, then clear this bit to reset the external ahb FSM.*/ + uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/ + uint32_t clk_en : 1; + uint32_t reserved4 : 28; }; uint32_t val; } misc_conf; - union { - struct { - uint32_t peri_in_sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2*/ - uint32_t peri_out_sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2*/ - uint32_t reserved12 : 20; - }; - uint32_t val; - } peri_sel[5]; - union { - struct { - uint32_t in_size : 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 0. 0:16 bytes*/ - uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes*/ - uint32_t reserved10 : 22; - }; - uint32_t val; - } sram_size[5]; - uint32_t date; /*register version.*/ + uint32_t date; } gdma_dev_t; - -_Static_assert(sizeof(gdma_dev_t) == 0x244, "incorrect size of gdma_dev_t."); - extern gdma_dev_t GDMA; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/gpio_sd_reg.h b/components/soc/esp32s3/include/soc/gpio_sd_reg.h index 625a06c339..87fe9ab2ec 100644 --- a/components/soc/esp32s3/include/soc/gpio_sd_reg.h +++ b/components/soc/esp32s3/include/soc/gpio_sd_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,156 +11,162 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_GPIO_SD_REG_H_ +#define _SOC_GPIO_SD_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000) +#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0) /* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD0_PRESCALE 0x000000FF -#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V) << (GPIO_SD0_PRESCALE_S)) -#define GPIO_SD0_PRESCALE_V 0xFF -#define GPIO_SD0_PRESCALE_S 8 +/*description: .*/ +#define GPIO_SD0_PRESCALE 0x000000FF +#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S)) +#define GPIO_SD0_PRESCALE_V 0xFF +#define GPIO_SD0_PRESCALE_S 8 /* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD0_IN 0x000000FF -#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V) << (GPIO_SD0_IN_S)) -#define GPIO_SD0_IN_V 0xFF -#define GPIO_SD0_IN_S 0 +/*description: .*/ +#define GPIO_SD0_IN 0x000000FF +#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S)) +#define GPIO_SD0_IN_V 0xFF +#define GPIO_SD0_IN_S 0 -#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004) +#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4) /* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD1_PRESCALE 0x000000FF -#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V) << (GPIO_SD1_PRESCALE_S)) -#define GPIO_SD1_PRESCALE_V 0xFF -#define GPIO_SD1_PRESCALE_S 8 +/*description: .*/ +#define GPIO_SD1_PRESCALE 0x000000FF +#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S)) +#define GPIO_SD1_PRESCALE_V 0xFF +#define GPIO_SD1_PRESCALE_S 8 /* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD1_IN 0x000000FF -#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V) << (GPIO_SD1_IN_S)) -#define GPIO_SD1_IN_V 0xFF -#define GPIO_SD1_IN_S 0 +/*description: .*/ +#define GPIO_SD1_IN 0x000000FF +#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S)) +#define GPIO_SD1_IN_V 0xFF +#define GPIO_SD1_IN_S 0 -#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008) +#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8) /* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD2_PRESCALE 0x000000FF -#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V) << (GPIO_SD2_PRESCALE_S)) -#define GPIO_SD2_PRESCALE_V 0xFF -#define GPIO_SD2_PRESCALE_S 8 +/*description: .*/ +#define GPIO_SD2_PRESCALE 0x000000FF +#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S)) +#define GPIO_SD2_PRESCALE_V 0xFF +#define GPIO_SD2_PRESCALE_S 8 /* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD2_IN 0x000000FF -#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V) << (GPIO_SD2_IN_S)) -#define GPIO_SD2_IN_V 0xFF -#define GPIO_SD2_IN_S 0 +/*description: .*/ +#define GPIO_SD2_IN 0x000000FF +#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S)) +#define GPIO_SD2_IN_V 0xFF +#define GPIO_SD2_IN_S 0 -#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c) +#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xC) /* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD3_PRESCALE 0x000000FF -#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V) << (GPIO_SD3_PRESCALE_S)) -#define GPIO_SD3_PRESCALE_V 0xFF -#define GPIO_SD3_PRESCALE_S 8 +/*description: .*/ +#define GPIO_SD3_PRESCALE 0x000000FF +#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S)) +#define GPIO_SD3_PRESCALE_V 0xFF +#define GPIO_SD3_PRESCALE_S 8 /* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD3_IN 0x000000FF -#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V) << (GPIO_SD3_IN_S)) -#define GPIO_SD3_IN_V 0xFF -#define GPIO_SD3_IN_S 0 +/*description: .*/ +#define GPIO_SD3_IN 0x000000FF +#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S)) +#define GPIO_SD3_IN_V 0xFF +#define GPIO_SD3_IN_S 0 -#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010) +#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x10) /* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD4_PRESCALE 0x000000FF -#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V) << (GPIO_SD4_PRESCALE_S)) -#define GPIO_SD4_PRESCALE_V 0xFF -#define GPIO_SD4_PRESCALE_S 8 +/*description: .*/ +#define GPIO_SD4_PRESCALE 0x000000FF +#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S)) +#define GPIO_SD4_PRESCALE_V 0xFF +#define GPIO_SD4_PRESCALE_S 8 /* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD4_IN 0x000000FF -#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V) << (GPIO_SD4_IN_S)) -#define GPIO_SD4_IN_V 0xFF -#define GPIO_SD4_IN_S 0 +/*description: .*/ +#define GPIO_SD4_IN 0x000000FF +#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S)) +#define GPIO_SD4_IN_V 0xFF +#define GPIO_SD4_IN_S 0 -#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014) +#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x14) /* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD5_PRESCALE 0x000000FF -#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V) << (GPIO_SD5_PRESCALE_S)) -#define GPIO_SD5_PRESCALE_V 0xFF -#define GPIO_SD5_PRESCALE_S 8 +/*description: .*/ +#define GPIO_SD5_PRESCALE 0x000000FF +#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S)) +#define GPIO_SD5_PRESCALE_V 0xFF +#define GPIO_SD5_PRESCALE_S 8 /* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD5_IN 0x000000FF -#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V) << (GPIO_SD5_IN_S)) -#define GPIO_SD5_IN_V 0xFF -#define GPIO_SD5_IN_S 0 +/*description: .*/ +#define GPIO_SD5_IN 0x000000FF +#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S)) +#define GPIO_SD5_IN_V 0xFF +#define GPIO_SD5_IN_S 0 -#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018) +#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x18) /* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD6_PRESCALE 0x000000FF -#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V) << (GPIO_SD6_PRESCALE_S)) -#define GPIO_SD6_PRESCALE_V 0xFF -#define GPIO_SD6_PRESCALE_S 8 +/*description: .*/ +#define GPIO_SD6_PRESCALE 0x000000FF +#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S)) +#define GPIO_SD6_PRESCALE_V 0xFF +#define GPIO_SD6_PRESCALE_S 8 /* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD6_IN 0x000000FF -#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V) << (GPIO_SD6_IN_S)) -#define GPIO_SD6_IN_V 0xFF -#define GPIO_SD6_IN_S 0 +/*description: .*/ +#define GPIO_SD6_IN 0x000000FF +#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S)) +#define GPIO_SD6_IN_V 0xFF +#define GPIO_SD6_IN_S 0 -#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c) +#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x1C) /* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD7_PRESCALE 0x000000FF -#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V) << (GPIO_SD7_PRESCALE_S)) -#define GPIO_SD7_PRESCALE_V 0xFF -#define GPIO_SD7_PRESCALE_S 8 +/*description: .*/ +#define GPIO_SD7_PRESCALE 0x000000FF +#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S)) +#define GPIO_SD7_PRESCALE_V 0xFF +#define GPIO_SD7_PRESCALE_S 8 /* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD7_IN 0x000000FF -#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V) << (GPIO_SD7_IN_S)) -#define GPIO_SD7_IN_V 0xFF -#define GPIO_SD7_IN_S 0 +/*description: .*/ +#define GPIO_SD7_IN 0x000000FF +#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S)) +#define GPIO_SD7_IN_V 0xFF +#define GPIO_SD7_IN_S 0 -#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020) +#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20) /* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SD_CLK_EN (BIT(31)) -#define GPIO_SD_CLK_EN_M (BIT(31)) -#define GPIO_SD_CLK_EN_V 0x1 -#define GPIO_SD_CLK_EN_S 31 +/*description: .*/ +#define GPIO_SD_CLK_EN (BIT(31)) +#define GPIO_SD_CLK_EN_M (BIT(31)) +#define GPIO_SD_CLK_EN_V 0x1 +#define GPIO_SD_CLK_EN_S 31 -#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024) +#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24) /* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SPI_SWAP (BIT(31)) -#define GPIO_SPI_SWAP_M (BIT(31)) -#define GPIO_SPI_SWAP_V 0x1 -#define GPIO_SPI_SWAP_S 31 +/*description: .*/ +#define GPIO_SPI_SWAP (BIT(31)) +#define GPIO_SPI_SWAP_M (BIT(31)) +#define GPIO_SPI_SWAP_V 0x1 +#define GPIO_SPI_SWAP_S 31 /* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: */ -#define GPIO_FUNCTION_CLK_EN (BIT(30)) -#define GPIO_FUNCTION_CLK_EN_M (BIT(30)) -#define GPIO_FUNCTION_CLK_EN_V 0x1 -#define GPIO_FUNCTION_CLK_EN_S 30 +/*description: .*/ +#define GPIO_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_M (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_V 0x1 +#define GPIO_FUNCTION_CLK_EN_S 30 -#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028) +#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x28) /* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */ -/*description: */ -#define GPIO_SD_DATE 0x0FFFFFFF -#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V) << (GPIO_SD_DATE_S)) -#define GPIO_SD_DATE_V 0xFFFFFFF -#define GPIO_SD_DATE_S 0 +/*description: .*/ +#define GPIO_SD_DATE 0x0FFFFFFF +#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S)) +#define GPIO_SD_DATE_V 0xFFFFFFF +#define GPIO_SD_DATE_S 0 + #ifdef __cplusplus } #endif + + + +#endif /*_SOC_GPIO_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/gpio_sd_struct.h b/components/soc/esp32s3/include/soc/gpio_sd_struct.h index 43d9a8030b..3791b0aec6 100644 --- a/components/soc/esp32s3/include/soc/gpio_sd_struct.h +++ b/components/soc/esp32s3/include/soc/gpio_sd_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,49 +11,52 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_GPIO_SD_STRUCT_H_ +#define _SOC_GPIO_SD_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { union { struct { - uint32_t duty: 8; - uint32_t prescale: 8; - uint32_t reserved16: 16; + uint32_t duty : 8; + uint32_t prescale : 8; + uint32_t reserved16 : 16; }; uint32_t val; } channel[8]; union { struct { - uint32_t reserved0: 31; - uint32_t clk_en: 1; + uint32_t reserved0 : 31; + uint32_t clk_en : 1; }; uint32_t val; } cg; union { struct { - uint32_t reserved0: 30; - uint32_t function_clk_en: 1; - uint32_t spi_swap: 1; + uint32_t reserved0 : 30; + uint32_t function_clk_en : 1; + uint32_t spi_swap : 1; }; uint32_t val; } misc; union { struct { - uint32_t date: 28; - uint32_t reserved28: 4; + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } version; } gpio_sd_dev_t; - extern gpio_sd_dev_t SIGMADELTA; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_GPIO_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/gpio_sig_map.h b/components/soc/esp32s3/include/soc/gpio_sig_map.h index 225549face..d2009a2b04 100644 --- a/components/soc/esp32s3/include/soc/gpio_sig_map.h +++ b/components/soc/esp32s3/include/soc/gpio_sig_map.h @@ -118,7 +118,8 @@ #define BB_DIAG17_IDX 52 #define I2S0I_SD3_IN_IDX 53 #define BB_DIAG18_IDX 53 -#define BB_DIAG19_IDX 54 +#define CORE1_GPIO_IN7_IDX 54 +#define CORE1_GPIO_OUT7_IDX 54 #define USB_EXTPHY_VP_IDX 55 #define USB_EXTPHY_OEN_IDX 55 #define USB_EXTPHY_VM_IDX 56 @@ -168,6 +169,10 @@ #define RMT_SIG_OUT2_IDX 83 #define RMT_SIG_IN3_IDX 84 #define RMT_SIG_OUT3_IDX 84 +#define USB_JTAG_TCK_IDX 85 +#define USB_JTAG_TMS_IDX 86 +#define USB_JTAG_TDI_IDX 87 +#define USB_JTAG_TDO_IDX 88 #define I2CEXT0_SCL_IN_IDX 89 #define I2CEXT0_SCL_OUT_IDX 89 #define I2CEXT0_SDA_IN_IDX 90 @@ -226,6 +231,13 @@ #define SUBSPICS1_OUT_IDX 125 #define FSPIDQS_OUT_IDX 126 #define SPI3_CS2_OUT_IDX 127 +#define I2S0O_SD1_OUT_IDX 128 +#define CORE1_GPIO_IN0_IDX 129 +#define CORE1_GPIO_OUT0_IDX 129 +#define CORE1_GPIO_IN1_IDX 130 +#define CORE1_GPIO_OUT1_IDX 130 +#define CORE1_GPIO_IN2_IDX 131 +#define CORE1_GPIO_OUT2_IDX 131 #define LCD_CS_IDX 132 #define CAM_DATA_IN0_IDX 133 #define LCD_DATA_OUT0_IDX 133 @@ -367,16 +379,16 @@ #define ANT_SEL5_IDX 205 #define ANT_SEL6_IDX 206 #define ANT_SEL7_IDX 207 -#define SIG_IN_FUNC_223_IDX 208 -#define SIG_IN_FUNC223_IDX 208 -#define SIG_IN_FUNC_224_IDX 209 -#define SIG_IN_FUNC224_IDX 209 -#define SIG_IN_FUNC_225_IDX 210 -#define SIG_IN_FUNC225_IDX 210 -#define SIG_IN_FUNC_226_IDX 211 -#define SIG_IN_FUNC226_IDX 211 -#define SIG_IN_FUNC_227_IDX 212 -#define SIG_IN_FUNC227_IDX 212 +#define SIG_IN_FUNC_208_IDX 208 +#define SIG_IN_FUNC208_IDX 208 +#define SIG_IN_FUNC_209_IDX 209 +#define SIG_IN_FUNC209_IDX 209 +#define SIG_IN_FUNC_210_IDX 210 +#define SIG_IN_FUNC210_IDX 210 +#define SIG_IN_FUNC_211_IDX 211 +#define SIG_IN_FUNC211_IDX 211 +#define SIG_IN_FUNC_212_IDX 212 +#define SIG_IN_FUNC212_IDX 212 #define SDHOST_CDATA_IN_20_IDX 213 #define SDHOST_CDATA_OUT_20_IDX 213 #define SDHOST_CDATA_IN_21_IDX 214 @@ -431,4 +443,13 @@ #define RX_STATUS_IDX 248 #define CLK_GPIO_IDX 249 #define NBT_BLE_IDX 250 +#define USB_JTAG_TRST_IDX 251 +#define CORE1_GPIO_IN3_IDX 252 +#define CORE1_GPIO_OUT3_IDX 252 +#define CORE1_GPIO_IN4_IDX 253 +#define CORE1_GPIO_OUT4_IDX 253 +#define CORE1_GPIO_IN5_IDX 254 +#define CORE1_GPIO_OUT5_IDX 254 +#define CORE1_GPIO_IN6_IDX 255 +#define CORE1_GPIO_OUT6_IDX 255 #define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32s3/include/soc/host_struct.h b/components/soc/esp32s3/include/soc/host_struct.h index 53afef485d..ee18195a93 100644 --- a/components/soc/esp32s3/include/soc/host_struct.h +++ b/components/soc/esp32s3/include/soc/host_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,13 +11,14 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_HOST_STRUCT_H_ +#define _SOC_HOST_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { uint32_t reserved_0; @@ -30,8 +31,8 @@ typedef volatile struct { uint32_t reserved_1c; union { struct { - uint32_t func1_mdstat: 1; - uint32_t reserved1: 31; + uint32_t func1_mdstat : 1; + uint32_t reserved1 : 31; }; uint32_t val; } func2_2; @@ -39,384 +40,384 @@ typedef volatile struct { uint32_t reserved_28; uint32_t reserved_2c; uint32_t reserved_30; - uint32_t gpio_status0; /**/ + uint32_t gpio_status0; union { struct { - uint32_t sdio_int1: 22; - uint32_t reserved22: 10; + uint32_t sdio_int1 : 22; + uint32_t reserved22 : 10; }; uint32_t val; } gpio_status1; - uint32_t gpio_in0; /**/ + uint32_t gpio_in0; union { struct { - uint32_t sdio_in1: 22; - uint32_t reserved22: 10; + uint32_t sdio_in1 : 22; + uint32_t reserved22 : 10; }; uint32_t val; } gpio_in1; union { struct { - uint32_t token0: 12; - uint32_t rx_pf_valid: 1; - uint32_t reserved13: 3; - uint32_t reg_token1: 12; - uint32_t rx_pf_eof: 4; + uint32_t token0 : 12; + uint32_t rx_pf_valid : 1; + uint32_t reserved13 : 3; + uint32_t reg_token1 : 12; + uint32_t rx_pf_eof : 4; }; uint32_t val; } slc0_token_rdata; - uint32_t slc0_pf; /**/ + uint32_t slc0_pf; uint32_t reserved_4c; union { struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; + uint32_t tohost_bit0 : 1; + uint32_t tohost_bit1 : 1; + uint32_t tohost_bit2 : 1; + uint32_t tohost_bit3 : 1; + uint32_t tohost_bit4 : 1; + uint32_t tohost_bit5 : 1; + uint32_t tohost_bit6 : 1; + uint32_t tohost_bit7 : 1; + uint32_t token0_1to0 : 1; + uint32_t token1_1to0 : 1; + uint32_t token0_0to1 : 1; + uint32_t token1_0to1 : 1; + uint32_t rx_sof : 1; + uint32_t rx_eof : 1; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_udf : 1; + uint32_t tx_ovf : 1; + uint32_t rx_pf_valid : 1; + uint32_t ext_bit0 : 1; + uint32_t ext_bit1 : 1; + uint32_t ext_bit2 : 1; + uint32_t ext_bit3 : 1; + uint32_t rx_new_packet : 1; + uint32_t rd_retry : 1; + uint32_t gpio_sdio : 1; + uint32_t reserved26 : 6; }; uint32_t val; } slc0_int_raw; uint32_t reserved_54; union { struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; + uint32_t tohost_bit0 : 1; + uint32_t tohost_bit1 : 1; + uint32_t tohost_bit2 : 1; + uint32_t tohost_bit3 : 1; + uint32_t tohost_bit4 : 1; + uint32_t tohost_bit5 : 1; + uint32_t tohost_bit6 : 1; + uint32_t tohost_bit7 : 1; + uint32_t token0_1to0 : 1; + uint32_t token1_1to0 : 1; + uint32_t token0_0to1 : 1; + uint32_t token1_0to1 : 1; + uint32_t rx_sof : 1; + uint32_t rx_eof : 1; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_udf : 1; + uint32_t tx_ovf : 1; + uint32_t rx_pf_valid : 1; + uint32_t ext_bit0 : 1; + uint32_t ext_bit1 : 1; + uint32_t ext_bit2 : 1; + uint32_t ext_bit3 : 1; + uint32_t rx_new_packet : 1; + uint32_t rd_retry : 1; + uint32_t gpio_sdio : 1; + uint32_t reserved26 : 6; }; uint32_t val; } slc0_int_st; uint32_t reserved_5c; union { struct { - uint32_t reg_slc0_len: 20; - uint32_t reg_slc0_len_check: 12; + uint32_t reg_slc0_len : 20; + uint32_t reg_slc0_len_check : 12; }; uint32_t val; } pkt_len; union { struct { - uint32_t state0: 8; - uint32_t state1: 8; - uint32_t state2: 8; - uint32_t state3: 8; + uint32_t state0 : 8; + uint32_t state1 : 8; + uint32_t state2 : 8; + uint32_t state3 : 8; }; uint32_t val; } state_w0; union { struct { - uint32_t state4: 8; - uint32_t state5: 8; - uint32_t state6: 8; - uint32_t state7: 8; + uint32_t state4 : 8; + uint32_t state5 : 8; + uint32_t state6 : 8; + uint32_t state7 : 8; }; uint32_t val; } state_w1; union { struct { - uint32_t conf0: 8; - uint32_t conf1: 8; - uint32_t conf2: 8; - uint32_t conf3: 8; + uint32_t conf0 : 8; + uint32_t conf1 : 8; + uint32_t conf2 : 8; + uint32_t conf3 : 8; }; uint32_t val; } conf_w0; union { struct { - uint32_t conf4: 8; - uint32_t conf5: 8; - uint32_t conf6: 8; - uint32_t conf7: 8; + uint32_t conf4 : 8; + uint32_t conf5 : 8; + uint32_t conf6 : 8; + uint32_t conf7 : 8; }; uint32_t val; } conf_w1; union { struct { - uint32_t conf8: 8; - uint32_t conf9: 8; - uint32_t conf10: 8; - uint32_t conf11: 8; + uint32_t conf8 : 8; + uint32_t conf9 : 8; + uint32_t conf10 : 8; + uint32_t conf11 : 8; }; uint32_t val; } conf_w2; union { struct { - uint32_t conf12: 8; - uint32_t conf13: 8; - uint32_t conf14: 8; - uint32_t conf15: 8; + uint32_t conf12 : 8; + uint32_t conf13 : 8; + uint32_t conf14 : 8; + uint32_t conf15 : 8; }; uint32_t val; } conf_w3; union { struct { - uint32_t conf16: 8; /*SLC timeout value*/ - uint32_t conf17: 8; /*SLC timeout enable*/ - uint32_t conf18: 8; - uint32_t conf19: 8; /*Interrupt to target CPU*/ + uint32_t conf16 : 8; /*SLC timeout value*/ + uint32_t conf17 : 8; /*SLC timeout enable*/ + uint32_t conf18 : 8; + uint32_t conf19 : 8; /*Interrupt to target CPU*/ }; uint32_t val; } conf_w4; union { struct { - uint32_t conf20: 8; - uint32_t conf21: 8; - uint32_t conf22: 8; - uint32_t conf23: 8; + uint32_t conf20 : 8; + uint32_t conf21 : 8; + uint32_t conf22 : 8; + uint32_t conf23 : 8; }; uint32_t val; } conf_w5; union { struct { - uint32_t win_cmd: 16; - uint32_t reserved16: 16; + uint32_t win_cmd : 16; + uint32_t reserved16 : 16; }; uint32_t val; } win_cmd; union { struct { - uint32_t conf24: 8; - uint32_t conf25: 8; - uint32_t conf26: 8; - uint32_t conf27: 8; + uint32_t conf24 : 8; + uint32_t conf25 : 8; + uint32_t conf26 : 8; + uint32_t conf27 : 8; }; uint32_t val; } conf_w6; union { struct { - uint32_t conf28: 8; - uint32_t conf29: 8; - uint32_t conf30: 8; - uint32_t conf31: 8; + uint32_t conf28 : 8; + uint32_t conf29 : 8; + uint32_t conf30 : 8; + uint32_t conf31 : 8; }; uint32_t val; } conf_w7; union { struct { - uint32_t reg_slc0_len0: 20; - uint32_t reg_slc0_len0_check: 12; + uint32_t reg_slc0_len0 : 20; + uint32_t reg_slc0_len0_check : 12; }; uint32_t val; } pkt_len0; union { struct { - uint32_t reg_slc0_len1: 20; - uint32_t reg_slc0_len1_check: 12; + uint32_t reg_slc0_len1 : 20; + uint32_t reg_slc0_len1_check : 12; }; uint32_t val; } pkt_len1; union { struct { - uint32_t reg_slc0_len2: 20; - uint32_t reg_slc0_len2_check: 12; + uint32_t reg_slc0_len2 : 20; + uint32_t reg_slc0_len2_check : 12; }; uint32_t val; } pkt_len2; union { struct { - uint32_t conf32: 8; - uint32_t conf33: 8; - uint32_t conf34: 8; - uint32_t conf35: 8; + uint32_t conf32 : 8; + uint32_t conf33 : 8; + uint32_t conf34 : 8; + uint32_t conf35 : 8; }; uint32_t val; } conf_w8; union { struct { - uint32_t conf36: 8; - uint32_t conf37: 8; - uint32_t conf38: 8; - uint32_t conf39: 8; + uint32_t conf36 : 8; + uint32_t conf37 : 8; + uint32_t conf38 : 8; + uint32_t conf39 : 8; }; uint32_t val; } conf_w9; union { struct { - uint32_t conf40: 8; - uint32_t conf41: 8; - uint32_t conf42: 8; - uint32_t conf43: 8; + uint32_t conf40 : 8; + uint32_t conf41 : 8; + uint32_t conf42 : 8; + uint32_t conf43 : 8; }; uint32_t val; } conf_w10; union { struct { - uint32_t conf44: 8; - uint32_t conf45: 8; - uint32_t conf46: 8; - uint32_t conf47: 8; + uint32_t conf44 : 8; + uint32_t conf45 : 8; + uint32_t conf46 : 8; + uint32_t conf47 : 8; }; uint32_t val; } conf_w11; union { struct { - uint32_t conf48: 8; - uint32_t conf49: 8; - uint32_t conf50: 8; - uint32_t conf51: 8; + uint32_t conf48 : 8; + uint32_t conf49 : 8; + uint32_t conf50 : 8; + uint32_t conf51 : 8; }; uint32_t val; } conf_w12; union { struct { - uint32_t conf52: 8; - uint32_t conf53: 8; - uint32_t conf54: 8; - uint32_t conf55: 8; + uint32_t conf52 : 8; + uint32_t conf53 : 8; + uint32_t conf54 : 8; + uint32_t conf55 : 8; }; uint32_t val; } conf_w13; union { struct { - uint32_t conf56: 8; - uint32_t conf57: 8; - uint32_t conf58: 8; - uint32_t conf59: 8; + uint32_t conf56 : 8; + uint32_t conf57 : 8; + uint32_t conf58 : 8; + uint32_t conf59 : 8; }; uint32_t val; } conf_w14; union { struct { - uint32_t conf60: 8; - uint32_t conf61: 8; - uint32_t conf62: 8; - uint32_t conf63: 8; + uint32_t conf60 : 8; + uint32_t conf61 : 8; + uint32_t conf62 : 8; + uint32_t conf63 : 8; }; uint32_t val; } conf_w15; - uint32_t check_sum0; /**/ - uint32_t check_sum1; /**/ + uint32_t check_sum0; + uint32_t check_sum1; uint32_t reserved_c4; union { struct { - uint32_t token0_wd: 12; - uint32_t reserved12: 4; - uint32_t token1_wd: 12; - uint32_t reserved28: 4; + uint32_t token0_wd : 12; + uint32_t reserved12 : 4; + uint32_t token1_wd : 12; + uint32_t reserved28 : 4; }; uint32_t val; } slc0_token_wdata; uint32_t reserved_cc; union { struct { - uint32_t slc0_token0_dec: 1; - uint32_t slc0_token1_dec: 1; - uint32_t slc0_token0_wr: 1; - uint32_t slc0_token1_wr: 1; - uint32_t reserved4: 4; - uint32_t slc0_len_wr: 1; - uint32_t reserved9: 23; + uint32_t slc0_token0_dec : 1; + uint32_t slc0_token1_dec : 1; + uint32_t slc0_token0_wr : 1; + uint32_t slc0_token1_wr : 1; + uint32_t reserved4 : 4; + uint32_t slc0_len_wr : 1; + uint32_t reserved9 : 23; }; uint32_t val; } token_con; union { struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; + uint32_t tohost_bit0 : 1; + uint32_t tohost_bit1 : 1; + uint32_t tohost_bit2 : 1; + uint32_t tohost_bit3 : 1; + uint32_t tohost_bit4 : 1; + uint32_t tohost_bit5 : 1; + uint32_t tohost_bit6 : 1; + uint32_t tohost_bit7 : 1; + uint32_t token0_1to0 : 1; + uint32_t token1_1to0 : 1; + uint32_t token0_0to1 : 1; + uint32_t token1_0to1 : 1; + uint32_t rx_sof : 1; + uint32_t rx_eof : 1; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_udf : 1; + uint32_t tx_ovf : 1; + uint32_t rx_pf_valid : 1; + uint32_t ext_bit0 : 1; + uint32_t ext_bit1 : 1; + uint32_t ext_bit2 : 1; + uint32_t ext_bit3 : 1; + uint32_t rx_new_packet : 1; + uint32_t rd_retry : 1; + uint32_t gpio_sdio : 1; + uint32_t reserved26 : 6; }; uint32_t val; } slc0_int_clr; uint32_t reserved_d8; union { struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; + uint32_t tohost_bit0 : 1; + uint32_t tohost_bit1 : 1; + uint32_t tohost_bit2 : 1; + uint32_t tohost_bit3 : 1; + uint32_t tohost_bit4 : 1; + uint32_t tohost_bit5 : 1; + uint32_t tohost_bit6 : 1; + uint32_t tohost_bit7 : 1; + uint32_t token0_1to0 : 1; + uint32_t token1_1to0 : 1; + uint32_t token0_0to1 : 1; + uint32_t token1_0to1 : 1; + uint32_t rx_sof : 1; + uint32_t rx_eof : 1; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_udf : 1; + uint32_t tx_ovf : 1; + uint32_t rx_pf_valid : 1; + uint32_t ext_bit0 : 1; + uint32_t ext_bit1 : 1; + uint32_t ext_bit2 : 1; + uint32_t ext_bit3 : 1; + uint32_t rx_new_packet : 1; + uint32_t rd_retry : 1; + uint32_t gpio_sdio : 1; + uint32_t reserved26 : 6; }; uint32_t val; } slc0_func1_int_ena; @@ -425,96 +426,96 @@ typedef volatile struct { uint32_t reserved_e8; union { struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; + uint32_t tohost_bit0 : 1; + uint32_t tohost_bit1 : 1; + uint32_t tohost_bit2 : 1; + uint32_t tohost_bit3 : 1; + uint32_t tohost_bit4 : 1; + uint32_t tohost_bit5 : 1; + uint32_t tohost_bit6 : 1; + uint32_t tohost_bit7 : 1; + uint32_t token0_1to0 : 1; + uint32_t token1_1to0 : 1; + uint32_t token0_0to1 : 1; + uint32_t token1_0to1 : 1; + uint32_t rx_sof : 1; + uint32_t rx_eof : 1; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_udf : 1; + uint32_t tx_ovf : 1; + uint32_t rx_pf_valid : 1; + uint32_t ext_bit0 : 1; + uint32_t ext_bit1 : 1; + uint32_t ext_bit2 : 1; + uint32_t ext_bit3 : 1; + uint32_t rx_new_packet : 1; + uint32_t rd_retry : 1; + uint32_t gpio_sdio : 1; + uint32_t reserved26 : 6; }; uint32_t val; } slc0_int_ena; uint32_t reserved_f0; union { struct { - uint32_t infor: 20; - uint32_t reserved20: 12; + uint32_t infor : 20; + uint32_t reserved20 : 12; }; uint32_t val; } slc0_rx_infor; uint32_t reserved_f8; - uint32_t slc0_len_wd; /**/ - uint32_t apbwin_wdata; /**/ + uint32_t slc0_len_wd; + uint32_t apbwin_wdata; union { struct { - uint32_t addr: 28; - uint32_t wr: 1; - uint32_t start: 1; - uint32_t bus: 1; - uint32_t reserved31: 1; + uint32_t addr : 28; + uint32_t wr : 1; + uint32_t start : 1; + uint32_t bus : 1; + uint32_t reserved31 : 1; }; uint32_t val; } apbwin_conf; - uint32_t apbwin_rdata; /**/ + uint32_t apbwin_rdata; union { struct { - uint32_t bit7_clraddr: 9; - uint32_t bit6_clraddr: 9; - uint32_t reserved18: 14; + uint32_t bit7_clraddr : 9; + uint32_t bit6_clraddr : 9; + uint32_t reserved18 : 14; }; uint32_t val; } slc0_rdclr; uint32_t reserved_110; union { struct { - uint32_t tohost_bit01: 1; - uint32_t tohost_bit11: 1; - uint32_t tohost_bit21: 1; - uint32_t tohost_bit31: 1; - uint32_t tohost_bit41: 1; - uint32_t tohost_bit51: 1; - uint32_t tohost_bit61: 1; - uint32_t tohost_bit71: 1; - uint32_t token0_1to01: 1; - uint32_t token1_1to01: 1; - uint32_t token0_0to11: 1; - uint32_t token1_0to11: 1; - uint32_t rx_sof1: 1; - uint32_t rx_eof1: 1; - uint32_t rx_start1: 1; - uint32_t tx_start1: 1; - uint32_t rx_udf1: 1; - uint32_t tx_ovf1: 1; - uint32_t rx_pf_valid1: 1; - uint32_t ext_bit01: 1; - uint32_t ext_bit11: 1; - uint32_t ext_bit21: 1; - uint32_t ext_bit31: 1; - uint32_t rx_new_packet1: 1; - uint32_t rd_retry1: 1; - uint32_t gpio_sdio1: 1; - uint32_t reserved26: 6; + uint32_t tohost_bit01 : 1; + uint32_t tohost_bit11 : 1; + uint32_t tohost_bit21 : 1; + uint32_t tohost_bit31 : 1; + uint32_t tohost_bit41 : 1; + uint32_t tohost_bit51 : 1; + uint32_t tohost_bit61 : 1; + uint32_t tohost_bit71 : 1; + uint32_t token0_1to01 : 1; + uint32_t token1_1to01 : 1; + uint32_t token0_0to11 : 1; + uint32_t token1_0to11 : 1; + uint32_t rx_sof1 : 1; + uint32_t rx_eof1 : 1; + uint32_t rx_start1 : 1; + uint32_t tx_start1 : 1; + uint32_t rx_udf1 : 1; + uint32_t tx_ovf1 : 1; + uint32_t rx_pf_valid1 : 1; + uint32_t ext_bit01 : 1; + uint32_t ext_bit11 : 1; + uint32_t ext_bit21 : 1; + uint32_t ext_bit31 : 1; + uint32_t rx_new_packet1 : 1; + uint32_t rd_retry1 : 1; + uint32_t gpio_sdio1 : 1; + uint32_t reserved26 : 6; }; uint32_t val; } slc0_int_ena1; @@ -542,8 +543,8 @@ typedef volatile struct { uint32_t reserved_16c; uint32_t reserved_170; uint32_t reserved_174; - uint32_t date; /**/ - uint32_t id; /**/ + uint32_t date; + uint32_t id; uint32_t reserved_180; uint32_t reserved_184; uint32_t reserved_188; @@ -574,31 +575,33 @@ typedef volatile struct { uint32_t reserved_1ec; union { struct { - uint32_t frc_sdio11: 5; - uint32_t frc_sdio20: 5; - uint32_t frc_neg_samp: 5; - uint32_t frc_pos_samp: 5; - uint32_t frc_quick_in: 5; - uint32_t sdio20_int_delay: 1; - uint32_t sdio_pad_pullup: 1; - uint32_t hspeed_con_en: 1; - uint32_t reserved28: 4; + uint32_t frc_sdio11 : 5; + uint32_t frc_sdio20 : 5; + uint32_t frc_neg_samp : 5; + uint32_t frc_pos_samp : 5; + uint32_t frc_quick_in : 5; + uint32_t sdio20_int_delay : 1; + uint32_t sdio_pad_pullup : 1; + uint32_t hspeed_con_en : 1; + uint32_t reserved28 : 4; }; uint32_t val; } conf; union { struct { - uint32_t sdio20_mode: 5; - uint32_t sdio_neg_samp: 5; - uint32_t sdio_quick_in: 5; - uint32_t reserved15: 17; + uint32_t sdio20_mode : 5; + uint32_t sdio_neg_samp : 5; + uint32_t sdio_quick_in : 5; + uint32_t reserved15 : 17; }; uint32_t val; } inf_st; } host_dev_t; - extern host_dev_t HOST; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_HOST_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/i2c_reg.h b/components/soc/esp32s3/include/soc/i2c_reg.h index 42fa9980f5..451f2b8256 100644 --- a/components/soc/esp32s3/include/soc/i2c_reg.h +++ b/components/soc/esp32s3/include/soc/i2c_reg.h @@ -1,4 +1,4 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -16,974 +16,1042 @@ #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) - /* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ - /*description: */ -#define I2C_SCL_LOW_PERIOD 0x000001FF +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: .*/ +#define I2C_SCL_LOW_PERIOD 0x000001FF #define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) #define I2C_SCL_LOW_PERIOD_V 0x1FF #define I2C_SCL_LOW_PERIOD_S 0 -#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) - /* I2C_CONF_UPGATE : WO ;bitpos:[11] ;default: 1'b0 ; */ - /*description: */ -#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) +/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_V 0x1 +#define I2C_ADDR_BROADCASTING_EN_S 14 +/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x1 +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 +/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_V 0x1 +#define I2C_SLV_TX_AUTO_START_EN_S 12 +/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_CONF_UPGATE (BIT(11)) #define I2C_CONF_UPGATE_M (BIT(11)) #define I2C_CONF_UPGATE_V 0x1 #define I2C_CONF_UPGATE_S 11 - /* I2C_FSM_RST : WO ;bitpos:[10] ;default: 1'b0 ; */ - /*description: */ -#define I2C_FSM_RST (BIT(10)) +/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_FSM_RST (BIT(10)) #define I2C_FSM_RST_M (BIT(10)) #define I2C_FSM_RST_V 0x1 #define I2C_FSM_RST_S 10 - /* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ - /*description: */ -#define I2C_ARBITRATION_EN (BIT(9)) +/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_ARBITRATION_EN (BIT(9)) #define I2C_ARBITRATION_EN_M (BIT(9)) #define I2C_ARBITRATION_EN_V 0x1 #define I2C_ARBITRATION_EN_S 9 - /* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ - /*description: */ -#define I2C_CLK_EN (BIT(8)) +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_CLK_EN (BIT(8)) #define I2C_CLK_EN_M (BIT(8)) #define I2C_CLK_EN_V 0x1 #define I2C_CLK_EN_S 8 - /* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ - /*description: */ -#define I2C_RX_LSB_FIRST (BIT(7)) +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_RX_LSB_FIRST (BIT(7)) #define I2C_RX_LSB_FIRST_M (BIT(7)) #define I2C_RX_LSB_FIRST_V 0x1 #define I2C_RX_LSB_FIRST_S 7 - /* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TX_LSB_FIRST (BIT(6)) +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TX_LSB_FIRST (BIT(6)) #define I2C_TX_LSB_FIRST_M (BIT(6)) #define I2C_TX_LSB_FIRST_V 0x1 #define I2C_TX_LSB_FIRST_S 6 - /* I2C_TRANS_START : WO ;bitpos:[5] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_START (BIT(5)) +/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START (BIT(5)) #define I2C_TRANS_START_M (BIT(5)) #define I2C_TRANS_START_V 0x1 #define I2C_TRANS_START_S 5 - /* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ - /*description: */ -#define I2C_MS_MODE (BIT(4)) +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MS_MODE (BIT(4)) #define I2C_MS_MODE_M (BIT(4)) #define I2C_MS_MODE_V 0x1 #define I2C_MS_MODE_S 4 - /* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ - /*description: */ -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) #define I2C_RX_FULL_ACK_LEVEL_M (BIT(3)) #define I2C_RX_FULL_ACK_LEVEL_V 0x1 #define I2C_RX_FULL_ACK_LEVEL_S 3 - /* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) #define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) #define I2C_SAMPLE_SCL_LEVEL_V 0x1 #define I2C_SAMPLE_SCL_LEVEL_S 2 - /* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ - /*description: */ -#define I2C_SCL_FORCE_OUT (BIT(1)) +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SCL_FORCE_OUT (BIT(1)) #define I2C_SCL_FORCE_OUT_M (BIT(1)) #define I2C_SCL_FORCE_OUT_V 0x1 #define I2C_SCL_FORCE_OUT_S 1 - /* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ - /*description: */ -#define I2C_SDA_FORCE_OUT (BIT(0)) +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SDA_FORCE_OUT (BIT(0)) #define I2C_SDA_FORCE_OUT_M (BIT(0)) #define I2C_SDA_FORCE_OUT_V 0x1 #define I2C_SDA_FORCE_OUT_S 0 -#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) - /* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ - /*description: */ -#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: .*/ +#define I2C_SCL_STATE_LAST 0x00000007 #define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) #define I2C_SCL_STATE_LAST_V 0x7 #define I2C_SCL_STATE_LAST_S 28 - /* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ - /*description: */ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 #define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) #define I2C_SCL_MAIN_STATE_LAST_V 0x7 #define I2C_SCL_MAIN_STATE_LAST_S 24 - /* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ - /*description: */ -#define I2C_TXFIFO_CNT 0x0000003F +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_CNT 0x0000003F #define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) #define I2C_TXFIFO_CNT_V 0x3F #define I2C_TXFIFO_CNT_S 18 - /* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */ - /*description: */ -#define I2C_STRETCH_CAUSE 0x00000003 +/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */ +/*description: .*/ +#define I2C_STRETCH_CAUSE 0x00000003 #define I2C_STRETCH_CAUSE_M ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S)) #define I2C_STRETCH_CAUSE_V 0x3 #define I2C_STRETCH_CAUSE_S 14 - /* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ - /*description: */ -#define I2C_RXFIFO_CNT 0x0000003F +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_CNT 0x0000003F #define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) #define I2C_RXFIFO_CNT_V 0x3F #define I2C_RXFIFO_CNT_S 8 - /* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SLAVE_ADDRESSED (BIT(5)) +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_ADDRESSED (BIT(5)) #define I2C_SLAVE_ADDRESSED_M (BIT(5)) #define I2C_SLAVE_ADDRESSED_V 0x1 #define I2C_SLAVE_ADDRESSED_S 5 - /* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ - /*description: */ -#define I2C_BUS_BUSY (BIT(4)) +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BUS_BUSY (BIT(4)) #define I2C_BUS_BUSY_M (BIT(4)) #define I2C_BUS_BUSY_V 0x1 #define I2C_BUS_BUSY_S 4 - /* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ - /*description: */ -#define I2C_ARB_LOST (BIT(3)) +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARB_LOST (BIT(3)) #define I2C_ARB_LOST_M (BIT(3)) #define I2C_ARB_LOST_V 0x1 #define I2C_ARB_LOST_S 3 - /* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SLAVE_RW (BIT(1)) +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_RW (BIT(1)) #define I2C_SLAVE_RW_M (BIT(1)) #define I2C_SLAVE_RW_V 0x1 #define I2C_SLAVE_RW_S 1 - /* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RESP_REC (BIT(0)) +/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RESP_REC (BIT(0)) #define I2C_RESP_REC_M (BIT(0)) #define I2C_RESP_REC_V 0x1 #define I2C_RESP_REC_S 0 -#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) - /* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xC) +/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_EN (BIT(5)) #define I2C_TIME_OUT_EN_M (BIT(5)) #define I2C_TIME_OUT_EN_V 0x1 #define I2C_TIME_OUT_EN_S 5 - /* I2C_TIME_OUT_VALUE : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ - /*description: */ -#define I2C_TIME_OUT_REG 0x0000001F -#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) -#define I2C_TIME_OUT_REG_V 0x1F -#define I2C_TIME_OUT_REG_S 0 +/* I2C_TIME_OUT_VALUE : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ +/*description: .*/ +#define I2C_TIME_OUT_VALUE 0x0000001F +#define I2C_TIME_OUT_VALUE_M ((I2C_TIME_OUT_VALUE_V)<<(I2C_TIME_OUT_VALUE_S)) +#define I2C_TIME_OUT_VALUE_V 0x1F +#define I2C_TIME_OUT_VALUE_S 0 -#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) - /* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ADDR_10BIT_EN (BIT(31)) #define I2C_ADDR_10BIT_EN_M (BIT(31)) #define I2C_ADDR_10BIT_EN_V 0x1 #define I2C_ADDR_10BIT_EN_S 31 - /* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ - /*description: */ -#define I2C_SLAVE_ADDR 0x00007FFF +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_ADDR 0x00007FFF #define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) #define I2C_SLAVE_ADDR_V 0x7FFF #define I2C_SLAVE_ADDR_S 0 -#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) - /* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ - /*description: */ -#define I2C_SLAVE_RW_POINT 0x000000FF +#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) +/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_RW_POINT 0x000000FF #define I2C_SLAVE_RW_POINT_M ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S)) #define I2C_SLAVE_RW_POINT_V 0xFF #define I2C_SLAVE_RW_POINT_S 22 - /* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ - /*description: */ -#define I2C_TXFIFO_WADDR 0x0000001F +/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_WADDR 0x0000001F #define I2C_TXFIFO_WADDR_M ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S)) #define I2C_TXFIFO_WADDR_V 0x1F #define I2C_TXFIFO_WADDR_S 15 - /* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ - /*description: */ -#define I2C_TXFIFO_RADDR 0x0000001F +/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_RADDR 0x0000001F #define I2C_TXFIFO_RADDR_M ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S)) #define I2C_TXFIFO_RADDR_V 0x1F #define I2C_TXFIFO_RADDR_S 10 - /* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ - /*description: */ -#define I2C_RXFIFO_WADDR 0x0000001F +/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WADDR 0x0000001F #define I2C_RXFIFO_WADDR_M ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S)) #define I2C_RXFIFO_WADDR_V 0x1F #define I2C_RXFIFO_WADDR_S 5 - /* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ - /*description: */ -#define I2C_RXFIFO_RADDR 0x0000001F +/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_RADDR 0x0000001F #define I2C_RXFIFO_RADDR_M ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S)) #define I2C_RXFIFO_RADDR_V 0x1F #define I2C_RXFIFO_RADDR_S 0 -#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) - /* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) +/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (BIT(14)) +#define I2C_FIFO_PRT_EN_V 0x1 +#define I2C_FIFO_PRT_EN_S 14 +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TX_FIFO_RST (BIT(13)) #define I2C_TX_FIFO_RST_M (BIT(13)) #define I2C_TX_FIFO_RST_V 0x1 #define I2C_TX_FIFO_RST_S 13 - /* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RX_FIFO_RST (BIT(12)) +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RX_FIFO_RST (BIT(12)) #define I2C_RX_FIFO_RST_M (BIT(12)) #define I2C_RX_FIFO_RST_V 0x1 #define I2C_RX_FIFO_RST_S 12 - /* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ - /*description: */ -#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) #define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) #define I2C_FIFO_ADDR_CFG_EN_V 0x1 #define I2C_FIFO_ADDR_CFG_EN_S 11 - /* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ - /*description: */ -#define I2C_NONFIFO_EN (BIT(10)) +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NONFIFO_EN (BIT(10)) #define I2C_NONFIFO_EN_M (BIT(10)) #define I2C_NONFIFO_EN_V 0x1 #define I2C_NONFIFO_EN_S 10 - /* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ - /*description: */ -#define I2C_TXFIFO_WM_THRHD 0x0000001F +/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_THRHD 0x0000001F #define I2C_TXFIFO_WM_THRHD_M ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S)) #define I2C_TXFIFO_WM_THRHD_V 0x1F #define I2C_TXFIFO_WM_THRHD_S 5 - /* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ - /*description: */ -#define I2C_RXFIFO_WM_THRHD 0x0000001F +/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_THRHD 0x0000001F #define I2C_RXFIFO_WM_THRHD_M ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S)) #define I2C_RXFIFO_WM_THRHD_V 0x1F #define I2C_RXFIFO_WM_THRHD_S 0 -#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) - /* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ - /*description: */ -#define I2C_FIFO_RDATA 0x000000FF +#define I2C_DATA_APB_REG(i) (0x60013000 + (i)*0x14000 + 0x001c) + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1C) +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: .*/ +#define I2C_FIFO_RDATA 0x000000FF #define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) #define I2C_FIFO_RDATA_V 0xFF #define I2C_FIFO_RDATA_S 0 -#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) - /* I2C_SLAVE_STRETCH_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) +/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_V 0x1 +#define I2C_GENERAL_CALL_INT_RAW_S 17 +/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) #define I2C_SLAVE_STRETCH_INT_RAW_M (BIT(16)) #define I2C_SLAVE_STRETCH_INT_RAW_V 0x1 #define I2C_SLAVE_STRETCH_INT_RAW_S 16 - /* I2C_DET_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ - /*description: */ -#define I2C_DET_START_INT_RAW (BIT(15)) +/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_DET_START_INT_RAW (BIT(15)) #define I2C_DET_START_INT_RAW_M (BIT(15)) #define I2C_DET_START_INT_RAW_V 0x1 #define I2C_DET_START_INT_RAW_S 15 - /* I2C_SCL_MAIN_ST_TO_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1 #define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 - /* I2C_SCL_ST_TO_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) #define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) #define I2C_SCL_ST_TO_INT_RAW_V 0x1 #define I2C_SCL_ST_TO_INT_RAW_S 13 - /* I2C_RXFIFO_UDF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) #define I2C_RXFIFO_UDF_INT_RAW_M (BIT(12)) #define I2C_RXFIFO_UDF_INT_RAW_V 0x1 #define I2C_RXFIFO_UDF_INT_RAW_S 12 - /* I2C_TXFIFO_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) #define I2C_TXFIFO_OVF_INT_RAW_M (BIT(11)) #define I2C_TXFIFO_OVF_INT_RAW_V 0x1 #define I2C_TXFIFO_OVF_INT_RAW_S 11 - /* I2C_NACK_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ - /*description: */ -#define I2C_NACK_INT_RAW (BIT(10)) +/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NACK_INT_RAW (BIT(10)) #define I2C_NACK_INT_RAW_M (BIT(10)) #define I2C_NACK_INT_RAW_V 0x1 #define I2C_NACK_INT_RAW_S 10 - /* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_START_INT_RAW (BIT(9)) +/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START_INT_RAW (BIT(9)) #define I2C_TRANS_START_INT_RAW_M (BIT(9)) #define I2C_TRANS_START_INT_RAW_V 0x1 #define I2C_TRANS_START_INT_RAW_S 9 - /* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) +/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) #define I2C_TIME_OUT_INT_RAW_M (BIT(8)) #define I2C_TIME_OUT_INT_RAW_V 0x1 #define I2C_TIME_OUT_INT_RAW_S 8 - /* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) #define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 #define I2C_TRANS_COMPLETE_INT_RAW_S 7 - /* I2C_MST_TXFIFO_UDF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ - /*description: */ -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_RAW_M (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x1 #define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 - /* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ - /*description: */ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) #define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 #define I2C_ARBITRATION_LOST_INT_RAW_S 5 - /* I2C_BYTE_TRANS_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ - /*description: */ -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_RAW_M (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x1 #define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 - /* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ - /*description: */ -#define I2C_END_DETECT_INT_RAW (BIT(3)) +/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_END_DETECT_INT_RAW (BIT(3)) #define I2C_END_DETECT_INT_RAW_M (BIT(3)) #define I2C_END_DETECT_INT_RAW_V 0x1 #define I2C_END_DETECT_INT_RAW_S 3 - /* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) #define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_RAW_V 0x1 #define I2C_RXFIFO_OVF_INT_RAW_S 2 - /* I2C_TXFIFO_WM_INT_RAW : RO ;bitpos:[1] ;default: 1'b1 ; */ - /*description: */ -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) #define I2C_TXFIFO_WM_INT_RAW_M (BIT(1)) #define I2C_TXFIFO_WM_INT_RAW_V 0x1 #define I2C_TXFIFO_WM_INT_RAW_S 1 - /* I2C_RXFIFO_WM_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) #define I2C_RXFIFO_WM_INT_RAW_M (BIT(0)) #define I2C_RXFIFO_WM_INT_RAW_V 0x1 #define I2C_RXFIFO_WM_INT_RAW_S 0 -#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) - /* I2C_SLAVE_STRETCH_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) +/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_V 0x1 +#define I2C_GENERAL_CALL_INT_CLR_S 17 +/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) #define I2C_SLAVE_STRETCH_INT_CLR_M (BIT(16)) #define I2C_SLAVE_STRETCH_INT_CLR_V 0x1 #define I2C_SLAVE_STRETCH_INT_CLR_S 16 - /* I2C_DET_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ - /*description: */ -#define I2C_DET_START_INT_CLR (BIT(15)) +/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_DET_START_INT_CLR (BIT(15)) #define I2C_DET_START_INT_CLR_M (BIT(15)) #define I2C_DET_START_INT_CLR_V 0x1 #define I2C_DET_START_INT_CLR_S 15 - /* I2C_SCL_MAIN_ST_TO_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1 #define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 - /* I2C_SCL_ST_TO_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) #define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) #define I2C_SCL_ST_TO_INT_CLR_V 0x1 #define I2C_SCL_ST_TO_INT_CLR_S 13 - /* I2C_RXFIFO_UDF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) #define I2C_RXFIFO_UDF_INT_CLR_M (BIT(12)) #define I2C_RXFIFO_UDF_INT_CLR_V 0x1 #define I2C_RXFIFO_UDF_INT_CLR_S 12 - /* I2C_TXFIFO_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) #define I2C_TXFIFO_OVF_INT_CLR_M (BIT(11)) #define I2C_TXFIFO_OVF_INT_CLR_V 0x1 #define I2C_TXFIFO_OVF_INT_CLR_S 11 - /* I2C_NACK_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ - /*description: */ -#define I2C_NACK_INT_CLR (BIT(10)) +/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NACK_INT_CLR (BIT(10)) #define I2C_NACK_INT_CLR_M (BIT(10)) #define I2C_NACK_INT_CLR_V 0x1 #define I2C_NACK_INT_CLR_S 10 - /* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_START_INT_CLR (BIT(9)) +/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START_INT_CLR (BIT(9)) #define I2C_TRANS_START_INT_CLR_M (BIT(9)) #define I2C_TRANS_START_INT_CLR_V 0x1 #define I2C_TRANS_START_INT_CLR_S 9 - /* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) +/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) #define I2C_TIME_OUT_INT_CLR_M (BIT(8)) #define I2C_TIME_OUT_INT_CLR_V 0x1 #define I2C_TIME_OUT_INT_CLR_S 8 - /* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) #define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 #define I2C_TRANS_COMPLETE_INT_CLR_S 7 - /* I2C_MST_TXFIFO_UDF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ - /*description: */ -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_CLR_M (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x1 #define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 - /* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ - /*description: */ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) #define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 #define I2C_ARBITRATION_LOST_INT_CLR_S 5 - /* I2C_BYTE_TRANS_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ - /*description: */ -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_CLR_M (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x1 #define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 - /* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ - /*description: */ -#define I2C_END_DETECT_INT_CLR (BIT(3)) +/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_END_DETECT_INT_CLR (BIT(3)) #define I2C_END_DETECT_INT_CLR_M (BIT(3)) #define I2C_END_DETECT_INT_CLR_V 0x1 #define I2C_END_DETECT_INT_CLR_S 3 - /* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) #define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_CLR_V 0x1 #define I2C_RXFIFO_OVF_INT_CLR_S 2 - /* I2C_TXFIFO_WM_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) #define I2C_TXFIFO_WM_INT_CLR_M (BIT(1)) #define I2C_TXFIFO_WM_INT_CLR_V 0x1 #define I2C_TXFIFO_WM_INT_CLR_S 1 - /* I2C_RXFIFO_WM_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) #define I2C_RXFIFO_WM_INT_CLR_M (BIT(0)) #define I2C_RXFIFO_WM_INT_CLR_V 0x1 #define I2C_RXFIFO_WM_INT_CLR_S 0 -#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) - /* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) +/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_V 0x1 +#define I2C_GENERAL_CALL_INT_ENA_S 17 +/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) #define I2C_SLAVE_STRETCH_INT_ENA_M (BIT(16)) #define I2C_SLAVE_STRETCH_INT_ENA_V 0x1 #define I2C_SLAVE_STRETCH_INT_ENA_S 16 - /* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ - /*description: */ -#define I2C_DET_START_INT_ENA (BIT(15)) +/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_DET_START_INT_ENA (BIT(15)) #define I2C_DET_START_INT_ENA_M (BIT(15)) #define I2C_DET_START_INT_ENA_V 0x1 #define I2C_DET_START_INT_ENA_S 15 - /* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1 #define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 - /* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) #define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) #define I2C_SCL_ST_TO_INT_ENA_V 0x1 #define I2C_SCL_ST_TO_INT_ENA_S 13 - /* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) #define I2C_RXFIFO_UDF_INT_ENA_M (BIT(12)) #define I2C_RXFIFO_UDF_INT_ENA_V 0x1 #define I2C_RXFIFO_UDF_INT_ENA_S 12 - /* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) #define I2C_TXFIFO_OVF_INT_ENA_M (BIT(11)) #define I2C_TXFIFO_OVF_INT_ENA_V 0x1 #define I2C_TXFIFO_OVF_INT_ENA_S 11 - /* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ - /*description: */ -#define I2C_NACK_INT_ENA (BIT(10)) +/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NACK_INT_ENA (BIT(10)) #define I2C_NACK_INT_ENA_M (BIT(10)) #define I2C_NACK_INT_ENA_V 0x1 #define I2C_NACK_INT_ENA_S 10 - /* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_START_INT_ENA (BIT(9)) +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START_INT_ENA (BIT(9)) #define I2C_TRANS_START_INT_ENA_M (BIT(9)) #define I2C_TRANS_START_INT_ENA_V 0x1 #define I2C_TRANS_START_INT_ENA_S 9 - /* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) #define I2C_TIME_OUT_INT_ENA_M (BIT(8)) #define I2C_TIME_OUT_INT_ENA_V 0x1 #define I2C_TIME_OUT_INT_ENA_S 8 - /* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 #define I2C_TRANS_COMPLETE_INT_ENA_S 7 - /* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ - /*description: */ -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_ENA_M (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x1 #define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 - /* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ - /*description: */ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 #define I2C_ARBITRATION_LOST_INT_ENA_S 5 - /* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ - /*description: */ -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_ENA_M (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x1 #define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 - /* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ - /*description: */ -#define I2C_END_DETECT_INT_ENA (BIT(3)) +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_END_DETECT_INT_ENA (BIT(3)) #define I2C_END_DETECT_INT_ENA_M (BIT(3)) #define I2C_END_DETECT_INT_ENA_V 0x1 #define I2C_END_DETECT_INT_ENA_S 3 - /* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) #define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_ENA_V 0x1 #define I2C_RXFIFO_OVF_INT_ENA_S 2 - /* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) #define I2C_TXFIFO_WM_INT_ENA_M (BIT(1)) #define I2C_TXFIFO_WM_INT_ENA_V 0x1 #define I2C_TXFIFO_WM_INT_ENA_S 1 - /* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) #define I2C_RXFIFO_WM_INT_ENA_M (BIT(0)) #define I2C_RXFIFO_WM_INT_ENA_V 0x1 #define I2C_RXFIFO_WM_INT_ENA_S 0 -#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) - /* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) +/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_V 0x1 +#define I2C_GENERAL_CALL_INT_ST_S 17 +/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) #define I2C_SLAVE_STRETCH_INT_ST_M (BIT(16)) #define I2C_SLAVE_STRETCH_INT_ST_V 0x1 #define I2C_SLAVE_STRETCH_INT_ST_S 16 - /* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ - /*description: */ -#define I2C_DET_START_INT_ST (BIT(15)) +/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_DET_START_INT_ST (BIT(15)) #define I2C_DET_START_INT_ST_M (BIT(15)) #define I2C_DET_START_INT_ST_V 0x1 #define I2C_DET_START_INT_ST_S 15 - /* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1 #define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 - /* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) #define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) #define I2C_SCL_ST_TO_INT_ST_V 0x1 #define I2C_SCL_ST_TO_INT_ST_S 13 - /* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) #define I2C_RXFIFO_UDF_INT_ST_M (BIT(12)) #define I2C_RXFIFO_UDF_INT_ST_V 0x1 #define I2C_RXFIFO_UDF_INT_ST_S 12 - /* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) #define I2C_TXFIFO_OVF_INT_ST_M (BIT(11)) #define I2C_TXFIFO_OVF_INT_ST_V 0x1 #define I2C_TXFIFO_OVF_INT_ST_S 11 - /* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ - /*description: */ -#define I2C_NACK_INT_ST (BIT(10)) +/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_NACK_INT_ST (BIT(10)) #define I2C_NACK_INT_ST_M (BIT(10)) #define I2C_NACK_INT_ST_V 0x1 #define I2C_NACK_INT_ST_S 10 - /* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_START_INT_ST (BIT(9)) +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_START_INT_ST (BIT(9)) #define I2C_TRANS_START_INT_ST_M (BIT(9)) #define I2C_TRANS_START_INT_ST_V 0x1 #define I2C_TRANS_START_INT_ST_S 9 - /* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TIME_OUT_INT_ST (BIT(8)) +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TIME_OUT_INT_ST (BIT(8)) #define I2C_TIME_OUT_INT_ST_M (BIT(8)) #define I2C_TIME_OUT_INT_ST_V 0x1 #define I2C_TIME_OUT_INT_ST_S 8 - /* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ST_V 0x1 #define I2C_TRANS_COMPLETE_INT_ST_S 7 - /* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ - /*description: */ -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_ST_M (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_ST_V 0x1 #define I2C_MST_TXFIFO_UDF_INT_ST_S 6 - /* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ - /*description: */ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ST_V 0x1 #define I2C_ARBITRATION_LOST_INT_ST_S 5 - /* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ - /*description: */ -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_ST_M (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_ST_V 0x1 #define I2C_BYTE_TRANS_DONE_INT_ST_S 4 - /* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ - /*description: */ -#define I2C_END_DETECT_INT_ST (BIT(3)) +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_END_DETECT_INT_ST (BIT(3)) #define I2C_END_DETECT_INT_ST_M (BIT(3)) #define I2C_END_DETECT_INT_ST_V 0x1 #define I2C_END_DETECT_INT_ST_S 3 - /* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) #define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_ST_V 0x1 #define I2C_RXFIFO_OVF_INT_ST_S 2 - /* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ - /*description: */ -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) #define I2C_TXFIFO_WM_INT_ST_M (BIT(1)) #define I2C_TXFIFO_WM_INT_ST_V 0x1 #define I2C_TXFIFO_WM_INT_ST_S 1 - /* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ - /*description: */ -#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) #define I2C_RXFIFO_WM_INT_ST_M (BIT(0)) #define I2C_RXFIFO_WM_INT_ST_V 0x1 #define I2C_RXFIFO_WM_INT_ST_S 0 -#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) - /* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ - /*description: */ -#define I2C_SDA_HOLD_TIME 0x000001FF +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: .*/ +#define I2C_SDA_HOLD_TIME 0x000001FF #define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) #define I2C_SDA_HOLD_TIME_V 0x1FF #define I2C_SDA_HOLD_TIME_S 0 -#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) - /* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ - /*description: */ -#define I2C_SDA_SAMPLE_TIME 0x000001FF +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: .*/ +#define I2C_SDA_SAMPLE_TIME 0x000001FF #define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) #define I2C_SDA_SAMPLE_TIME_V 0x1FF #define I2C_SDA_SAMPLE_TIME_S 0 -#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) - /* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */ - /*description: */ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) +/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */ +/*description: .*/ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F #define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S)) #define I2C_SCL_WAIT_HIGH_PERIOD_V 0x7F #define I2C_SCL_WAIT_HIGH_PERIOD_S 9 - /* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ - /*description: */ -#define I2C_SCL_HIGH_PERIOD 0x000001FF +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: .*/ +#define I2C_SCL_HIGH_PERIOD 0x000001FF #define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) #define I2C_SCL_HIGH_PERIOD_V 0x1FF #define I2C_SCL_HIGH_PERIOD_S 0 -#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) - /* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ - /*description: */ -#define I2C_SCL_START_HOLD_TIME 0x000001FF +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ +/*description: .*/ +#define I2C_SCL_START_HOLD_TIME 0x000001FF #define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) #define I2C_SCL_START_HOLD_TIME_V 0x1FF #define I2C_SCL_START_HOLD_TIME_S 0 -#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) - /* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ - /*description: */ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ +/*description: .*/ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF #define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) #define I2C_SCL_RSTART_SETUP_TIME_V 0x1FF #define I2C_SCL_RSTART_SETUP_TIME_S 0 -#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) - /* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ - /*description: */ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FF +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ +/*description: .*/ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FF #define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) #define I2C_SCL_STOP_HOLD_TIME_V 0x1FF #define I2C_SCL_STOP_HOLD_TIME_S 0 -#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) - /* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ - /*description: */ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FF +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4C) +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ +/*description: .*/ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FF #define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) #define I2C_SCL_STOP_SETUP_TIME_V 0x1FF #define I2C_SCL_STOP_SETUP_TIME_S 0 -#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) - /* I2C_SDA_FILTER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ - /*description: */ -#define I2C_SDA_FILTER_EN (BIT(5)) -#define I2C_SDA_FILTER_EN_M (BIT(5)) +#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (BIT(9)) #define I2C_SDA_FILTER_EN_V 0x1 -#define I2C_SDA_FILTER_EN_S 5 - /* I2C_SCL_FILTER_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ - /*description: */ -#define I2C_SCL_FILTER_EN (BIT(4)) -#define I2C_SCL_FILTER_EN_M (BIT(4)) +#define I2C_SDA_FILTER_EN_S 9 +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (BIT(8)) #define I2C_SCL_FILTER_EN_V 0x1 -#define I2C_SCL_FILTER_EN_S 4 - /* I2C_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ - /*description: */ -#define I2C_FILTER_THRES 0x0000000F -#define I2C_FILTER_THRES_M ((I2C_FILTER_THRES_V)<<(I2C_FILTER_THRES_S)) -#define I2C_FILTER_THRES_V 0xF -#define I2C_FILTER_THRES_S 0 +#define I2C_SCL_FILTER_EN_S 8 +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: .*/ +#define I2C_SDA_FILTER_THRES 0x0000000F +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0xF +#define I2C_SDA_FILTER_THRES_S 4 +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: .*/ +#define I2C_SCL_FILTER_THRES 0x0000000F +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0xF +#define I2C_SCL_FILTER_THRES_S 0 -#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x0054) - /* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */ - /*description: */ -#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54) +/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: .*/ +#define I2C_SCLK_ACTIVE (BIT(21)) #define I2C_SCLK_ACTIVE_M (BIT(21)) #define I2C_SCLK_ACTIVE_V 0x1 #define I2C_SCLK_ACTIVE_S 21 - /* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCLK_SEL (BIT(20)) +/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCLK_SEL (BIT(20)) #define I2C_SCLK_SEL_M (BIT(20)) #define I2C_SCLK_SEL_V 0x1 #define I2C_SCLK_SEL_S 20 - /* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */ - /*description: */ -#define I2C_SCLK_DIV_B 0x0000003F +/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */ +/*description: .*/ +#define I2C_SCLK_DIV_B 0x0000003F #define I2C_SCLK_DIV_B_M ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S)) #define I2C_SCLK_DIV_B_V 0x3F #define I2C_SCLK_DIV_B_S 14 - /* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */ - /*description: */ -#define I2C_SCLK_DIV_A 0x0000003F +/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: .*/ +#define I2C_SCLK_DIV_A 0x0000003F #define I2C_SCLK_DIV_A_M ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S)) #define I2C_SCLK_DIV_A_V 0x3F #define I2C_SCLK_DIV_A_S 8 - /* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ - /*description: */ -#define I2C_SCLK_DIV_NUM 0x000000FF +/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: .*/ +#define I2C_SCLK_DIV_NUM 0x000000FF #define I2C_SCLK_DIV_NUM_M ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S)) #define I2C_SCLK_DIV_NUM_V 0xFF #define I2C_SCLK_DIV_NUM_S 0 -#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) - /* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) +/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND0_DONE (BIT(31)) #define I2C_COMMAND0_DONE_M (BIT(31)) #define I2C_COMMAND0_DONE_V 0x1 #define I2C_COMMAND0_DONE_S 31 - /* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - /*description: */ -#define I2C_COMMAND0 0x00003FFF +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND0 0x00003FFF #define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) #define I2C_COMMAND0_V 0x3FFF #define I2C_COMMAND0_S 0 -#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) - /* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5C) +/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND1_DONE (BIT(31)) #define I2C_COMMAND1_DONE_M (BIT(31)) #define I2C_COMMAND1_DONE_V 0x1 #define I2C_COMMAND1_DONE_S 31 - /* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - /*description: */ -#define I2C_COMMAND1 0x00003FFF +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND1 0x00003FFF #define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) #define I2C_COMMAND1_V 0x3FFF #define I2C_COMMAND1_S 0 -#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) - /* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) +/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND2_DONE (BIT(31)) #define I2C_COMMAND2_DONE_M (BIT(31)) #define I2C_COMMAND2_DONE_V 0x1 #define I2C_COMMAND2_DONE_S 31 - /* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - /*description: */ -#define I2C_COMMAND2 0x00003FFF +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND2 0x00003FFF #define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) #define I2C_COMMAND2_V 0x3FFF #define I2C_COMMAND2_S 0 -#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) - /* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) +/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND3_DONE (BIT(31)) #define I2C_COMMAND3_DONE_M (BIT(31)) #define I2C_COMMAND3_DONE_V 0x1 #define I2C_COMMAND3_DONE_S 31 - /* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - /*description: */ -#define I2C_COMMAND3 0x00003FFF +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND3 0x00003FFF #define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) #define I2C_COMMAND3_V 0x3FFF #define I2C_COMMAND3_S 0 -#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) - /* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) +/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND4_DONE (BIT(31)) #define I2C_COMMAND4_DONE_M (BIT(31)) #define I2C_COMMAND4_DONE_V 0x1 #define I2C_COMMAND4_DONE_S 31 - /* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - /*description: */ -#define I2C_COMMAND4 0x00003FFF +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND4 0x00003FFF #define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) #define I2C_COMMAND4_V 0x3FFF #define I2C_COMMAND4_S 0 -#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) - /* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6C) +/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND5_DONE (BIT(31)) #define I2C_COMMAND5_DONE_M (BIT(31)) #define I2C_COMMAND5_DONE_V 0x1 #define I2C_COMMAND5_DONE_S 31 - /* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - /*description: */ -#define I2C_COMMAND5 0x00003FFF +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND5 0x00003FFF #define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) #define I2C_COMMAND5_V 0x3FFF #define I2C_COMMAND5_S 0 -#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) - /* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) +/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND6_DONE (BIT(31)) #define I2C_COMMAND6_DONE_M (BIT(31)) #define I2C_COMMAND6_DONE_V 0x1 #define I2C_COMMAND6_DONE_S 31 - /* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - /*description: */ -#define I2C_COMMAND6 0x00003FFF +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND6 0x00003FFF #define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) #define I2C_COMMAND6_V 0x3FFF #define I2C_COMMAND6_S 0 -#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) - /* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ - /*description: */ -#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) +/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_COMMAND7_DONE (BIT(31)) #define I2C_COMMAND7_DONE_M (BIT(31)) #define I2C_COMMAND7_DONE_V 0x1 #define I2C_COMMAND7_DONE_S 31 - /* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - /*description: */ -#define I2C_COMMAND7 0x00003FFF +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define I2C_COMMAND7 0x00003FFF #define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) #define I2C_COMMAND7_V 0x3FFF #define I2C_COMMAND7_S 0 -#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x0078) - /* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ - /*description: */ -#define I2C_SCL_ST_TO_REG 0x0000001F +#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) +/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ +/*description: no more than 23.*/ +#define I2C_SCL_ST_TO_REG 0x0000001F #define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S)) #define I2C_SCL_ST_TO_REG_V 0x1F #define I2C_SCL_ST_TO_REG_S 0 -#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x007c) - /* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ - /*description: */ -#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F +#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7C) +/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ +/*description: no more than 23.*/ +#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F #define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S)) #define I2C_SCL_MAIN_ST_TO_REG_V 0x1F #define I2C_SCL_MAIN_ST_TO_REG_S 0 -#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x0080) - /* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) +/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SDA_PD_EN (BIT(7)) #define I2C_SDA_PD_EN_M (BIT(7)) #define I2C_SDA_PD_EN_V 0x1 #define I2C_SDA_PD_EN_S 7 - /* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_PD_EN (BIT(6)) +/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_PD_EN (BIT(6)) #define I2C_SCL_PD_EN_M (BIT(6)) #define I2C_SCL_PD_EN_V 0x1 #define I2C_SCL_PD_EN_S 6 - /* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ - /*description: */ -#define I2C_SCL_RST_SLV_NUM 0x0000001F +/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ +/*description: .*/ +#define I2C_SCL_RST_SLV_NUM 0x0000001F #define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S)) #define I2C_SCL_RST_SLV_NUM_V 0x1F #define I2C_SCL_RST_SLV_NUM_S 1 - /* I2C_SCL_RST_SLV_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SCL_RST_SLV_EN (BIT(0)) +/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SCL_RST_SLV_EN (BIT(0)) #define I2C_SCL_RST_SLV_EN_M (BIT(0)) #define I2C_SCL_RST_SLV_EN_V 0x1 #define I2C_SCL_RST_SLV_EN_S 0 -#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x0084) - /* I2C_SLAVE_SCL_STRETCH_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) +/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x1 +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 +/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x1 +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 +/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) #define I2C_SLAVE_SCL_STRETCH_CLR_M (BIT(11)) #define I2C_SLAVE_SCL_STRETCH_CLR_V 0x1 #define I2C_SLAVE_SCL_STRETCH_CLR_S 11 - /* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ - /*description: */ -#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) #define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10)) #define I2C_SLAVE_SCL_STRETCH_EN_V 0x1 #define I2C_SLAVE_SCL_STRETCH_EN_S 10 - /* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ - /*description: */ -#define I2C_STRETCH_PROTECT_NUM 0x000003FF +/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: .*/ +#define I2C_STRETCH_PROTECT_NUM 0x000003FF #define I2C_STRETCH_PROTECT_NUM_M ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S)) #define I2C_STRETCH_PROTECT_NUM_V 0x3FF #define I2C_STRETCH_PROTECT_NUM_S 0 -#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) - /* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20011601 ; */ - /*description: */ -#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xF8) +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */ +/*description: .*/ +#define I2C_DATE 0xFFFFFFFF #define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) #define I2C_DATE_V 0xFFFFFFFF #define I2C_DATE_S 0 -#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) +#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) + +#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) -#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0180) #ifdef __cplusplus } diff --git a/components/soc/esp32s3/include/soc/i2c_struct.h b/components/soc/esp32s3/include/soc/i2c_struct.h index a24795bdcf..69c5d568d4 100644 --- a/components/soc/esp32s3/include/soc/i2c_struct.h +++ b/components/soc/esp32s3/include/soc/i2c_struct.h @@ -1,4 +1,4 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -22,56 +22,58 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t period: 9; - uint32_t reserved9: 23; + uint32_t period : 9; + uint32_t reserved9 : 23; }; uint32_t val; } scl_low_period; union { struct { - uint32_t sda_force_out: 1; - uint32_t scl_force_out: 1; - uint32_t sample_scl_level: 1; - uint32_t rx_full_ack_level: 1; - uint32_t ms_mode: 1; - uint32_t trans_start: 1; - uint32_t tx_lsb_first: 1; - uint32_t rx_lsb_first: 1; - uint32_t clk_en: 1; - uint32_t arbitration_en: 1; - uint32_t fsm_rst: 1; - uint32_t conf_upgate: 1; - uint32_t slv_tx_auto_start_en: 1; - uint32_t reserved13: 19; + uint32_t sda_force_out : 1; + uint32_t scl_force_out : 1; + uint32_t sample_scl_level : 1; + uint32_t rx_full_ack_level : 1; + uint32_t ms_mode : 1; + uint32_t trans_start : 1; + uint32_t tx_lsb_first : 1; + uint32_t rx_lsb_first : 1; + uint32_t clk_en : 1; + uint32_t arbitration_en : 1; + uint32_t fsm_rst : 1; + uint32_t conf_upgate : 1; + uint32_t slv_tx_auto_start_en : 1; + uint32_t addr_10bit_rw_check_en : 1; + uint32_t addr_broadcasting_en : 1; + uint32_t reserved15 : 17; }; uint32_t val; } ctr; union { struct { - uint32_t resp_rec: 1; - uint32_t slave_rw: 1; - uint32_t reserved2: 1; - uint32_t arb_lost: 1; - uint32_t bus_busy: 1; - uint32_t slave_addressed: 1; - uint32_t reserved6: 1; - uint32_t reserved7: 1; - uint32_t rx_fifo_cnt: 6; - uint32_t stretch_cause: 2; - uint32_t reserved16: 2; - uint32_t tx_fifo_cnt: 6; - uint32_t scl_main_state_last: 3; - uint32_t reserved27: 1; - uint32_t scl_state_last: 3; - uint32_t reserved31: 1; + uint32_t resp_rec : 1; + uint32_t slave_rw : 1; + uint32_t reserved2 : 1; + uint32_t arb_lost : 1; + uint32_t bus_busy : 1; + uint32_t slave_addressed : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t rx_fifo_cnt : 6; + uint32_t stretch_cause : 2; + uint32_t reserved16 : 2; + uint32_t tx_fifo_cnt : 6; + uint32_t scl_main_state_last : 3; + uint32_t reserved27 : 1; + uint32_t scl_state_last : 3; + uint32_t reserved31 : 1; }; uint32_t val; - } status_reg; + } sr; union { struct { - uint32_t time_out_value: 5; - uint32_t time_out_en: 1; - uint32_t reserved6: 26; + uint32_t tout : 5; + uint32_t time_out_en : 1; + uint32_t reserved6 : 26; }; uint32_t val; } timeout; @@ -85,206 +87,215 @@ typedef volatile struct { } slave_addr; union { struct { - uint32_t rx_fifo_raddr: 5; - uint32_t rx_fifo_waddr: 5; - uint32_t tx_fifo_raddr: 5; - uint32_t tx_fifo_waddr: 5; - uint32_t reserved20: 1; - uint32_t reserved21: 1; - uint32_t slave_rw_point: 8; - uint32_t reserved30: 2; + uint32_t rx_fifo_raddr : 5; + uint32_t rx_fifo_waddr : 5; + uint32_t tx_fifo_raddr : 5; + uint32_t tx_fifo_waddr : 5; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t slave_rw_point : 8; + uint32_t reserved30 : 2; }; uint32_t val; } fifo_st; union { struct { - uint32_t rx_fifo_wm_thrhd: 5; - uint32_t tx_fifo_wm_thrhd: 5; - uint32_t nonfifo_en: 1; - uint32_t fifo_addr_cfg_en: 1; - uint32_t rx_fifo_rst: 1; - uint32_t tx_fifo_rst: 1; - uint32_t fifo_prt_en: 1; - uint32_t reserved15: 5; - uint32_t reserved20: 6; - uint32_t reserved26: 1; - uint32_t reserved27: 5; + uint32_t rx_fifo_wm_thrhd : 5; + uint32_t tx_fifo_wm_thrhd : 5; + uint32_t nonfifo_en : 1; + uint32_t fifo_addr_cfg_en : 1; + uint32_t rx_fifo_rst : 1; + uint32_t tx_fifo_rst : 1; + uint32_t fifo_prt_en : 1; + uint32_t reserved15 : 5; + uint32_t reserved20 : 6; + uint32_t reserved26 : 1; + uint32_t reserved27 : 5; }; uint32_t val; } fifo_conf; union { struct { - uint32_t data; + uint8_t data; + uint8_t reserved[3]; }; uint32_t val; } fifo_data; union { struct { - uint32_t rx_fifo_wm: 1; - uint32_t tx_fifo_wm: 1; - uint32_t rx_fifo_ovf: 1; - uint32_t end_detect: 1; - uint32_t byte_trans_done: 1; - uint32_t arbitration_lost: 1; - uint32_t mst_tx_fifo_udf: 1; - uint32_t trans_complete: 1; - uint32_t time_out: 1; - uint32_t trans_start: 1; - uint32_t nack: 1; - uint32_t tx_fifo_ovf: 1; - uint32_t rx_fifo_udf: 1; - uint32_t scl_st_to: 1; - uint32_t scl_main_st_to: 1; - uint32_t det_start: 1; - uint32_t slave_stretch: 1; - uint32_t reserved17: 15; + uint32_t rx_fifo_wm : 1; + uint32_t tx_fifo_wm : 1; + uint32_t rx_fifo_ovf : 1; + uint32_t end_detect : 1; + uint32_t byte_trans_done : 1; + uint32_t arbitration_lost : 1; + uint32_t mst_tx_fifo_udf : 1; + uint32_t trans_complete : 1; + uint32_t time_out : 1; + uint32_t trans_start : 1; + uint32_t nack : 1; + uint32_t tx_fifo_ovf : 1; + uint32_t rx_fifo_udf : 1; + uint32_t scl_st_to : 1; + uint32_t scl_main_st_to : 1; + uint32_t det_start : 1; + uint32_t slave_stretch : 1; + uint32_t general_call : 1; + uint32_t reserved18 : 14; }; uint32_t val; } int_raw; union { struct { - uint32_t rx_fifo_wm: 1; - uint32_t tx_fifo_wm: 1; - uint32_t rx_fifo_ovf: 1; - uint32_t end_detect: 1; - uint32_t byte_trans_done: 1; - uint32_t arbitration_lost: 1; - uint32_t mst_tx_fifo_udf: 1; - uint32_t trans_complete: 1; - uint32_t time_out: 1; - uint32_t trans_start: 1; - uint32_t nack: 1; - uint32_t tx_fifo_ovf: 1; - uint32_t rx_fifo_udf: 1; - uint32_t scl_st_to: 1; - uint32_t scl_main_st_to: 1; - uint32_t det_start: 1; - uint32_t slave_stretch: 1; - uint32_t reserved17: 15; + uint32_t rx_fifo_wm : 1; + uint32_t tx_fifo_wm : 1; + uint32_t rx_fifo_ovf : 1; + uint32_t end_detect : 1; + uint32_t byte_trans_done : 1; + uint32_t arbitration_lost : 1; + uint32_t mst_tx_fifo_udf : 1; + uint32_t trans_complete : 1; + uint32_t time_out : 1; + uint32_t trans_start : 1; + uint32_t nack : 1; + uint32_t tx_fifo_ovf : 1; + uint32_t rx_fifo_udf : 1; + uint32_t scl_st_to : 1; + uint32_t scl_main_st_to : 1; + uint32_t det_start : 1; + uint32_t slave_stretch : 1; + uint32_t general_call : 1; + uint32_t reserved18 : 14; }; uint32_t val; } int_clr; union { struct { - uint32_t rx_fifo_wm: 1; - uint32_t tx_fifo_wm: 1; - uint32_t rx_fifo_ovf: 1; - uint32_t end_detect: 1; - uint32_t byte_trans_done: 1; - uint32_t arbitration_lost: 1; - uint32_t mst_tx_fifo_udf: 1; - uint32_t trans_complete: 1; - uint32_t time_out: 1; - uint32_t trans_start: 1; - uint32_t nack: 1; - uint32_t tx_fifo_ovf: 1; - uint32_t rx_fifo_udf: 1; - uint32_t scl_st_to: 1; - uint32_t scl_main_st_to: 1; - uint32_t det_start: 1; - uint32_t slave_stretch: 1; - uint32_t reserved17: 15; + uint32_t rx_fifo_wm : 1; + uint32_t tx_fifo_wm : 1; + uint32_t rx_fifo_ovf : 1; + uint32_t end_detect : 1; + uint32_t byte_trans_done : 1; + uint32_t arbitration_lost : 1; + uint32_t mst_tx_fifo_udf : 1; + uint32_t trans_complete : 1; + uint32_t time_out : 1; + uint32_t trans_start : 1; + uint32_t nack : 1; + uint32_t tx_fifo_ovf : 1; + uint32_t rx_fifo_udf : 1; + uint32_t scl_st_to : 1; + uint32_t scl_main_st_to : 1; + uint32_t det_start : 1; + uint32_t slave_stretch : 1; + uint32_t general_call : 1; + uint32_t reserved18 : 14; }; uint32_t val; } int_ena; union { struct { - uint32_t rx_fifo_wm: 1; - uint32_t tx_fifo_wm: 1; - uint32_t rx_fifo_ovf: 1; - uint32_t end_detect: 1; - uint32_t byte_trans_done: 1; - uint32_t arbitration_lost: 1; - uint32_t mst_tx_fifo_udf: 1; - uint32_t trans_complete: 1; - uint32_t time_out: 1; - uint32_t trans_start: 1; - uint32_t nack: 1; - uint32_t tx_fifo_ovf: 1; - uint32_t rx_fifo_udf: 1; - uint32_t scl_st_to: 1; - uint32_t scl_main_st_to: 1; - uint32_t det_start: 1; - uint32_t slave_stretch: 1; - uint32_t reserved17: 15; + uint32_t rx_fifo_wm : 1; + uint32_t tx_fifo_wm : 1; + uint32_t rx_fifo_ovf : 1; + uint32_t end_detect : 1; + uint32_t byte_trans_done : 1; + uint32_t arbitration_lost : 1; + uint32_t mst_tx_fifo_udf : 1; + uint32_t trans_complete : 1; + uint32_t time_out : 1; + uint32_t trans_start : 1; + uint32_t nack : 1; + uint32_t tx_fifo_ovf : 1; + uint32_t rx_fifo_udf : 1; + uint32_t scl_st_to : 1; + uint32_t scl_main_st_to : 1; + uint32_t det_start : 1; + uint32_t slave_stretch : 1; + uint32_t general_call : 1; + uint32_t reserved18 : 14; }; uint32_t val; } int_status; union { struct { - uint32_t time: 9; - uint32_t reserved9: 23; + uint32_t time : 9; + uint32_t reserved9 : 23; }; uint32_t val; } sda_hold; union { struct { - uint32_t time: 9; - uint32_t reserved9: 23; + uint32_t time : 9; + uint32_t reserved9 : 23; }; uint32_t val; } sda_sample; union { struct { - uint32_t period: 9; - uint32_t scl_wait_high_period: 7; - uint32_t reserved16: 16; + uint32_t period : 9; + uint32_t scl_wait_high_period : 7; + uint32_t reserved16 : 16; }; uint32_t val; } scl_high_period; uint32_t reserved_3c; union { struct { - uint32_t time: 9; - uint32_t reserved9: 23; + uint32_t time : 9; + uint32_t reserved9 : 23; }; uint32_t val; } scl_start_hold; union { struct { - uint32_t time: 9; - uint32_t reserved9: 23; + uint32_t time : 9; + uint32_t reserved9 : 23; }; uint32_t val; } scl_rstart_setup; union { struct { - uint32_t time: 9; - uint32_t reserved9: 23; + uint32_t time : 9; + uint32_t reserved9 : 23; }; uint32_t val; } scl_stop_hold; union { struct { - uint32_t time: 9; - uint32_t reserved9: 23; + uint32_t time : 9; + uint32_t reserved9 : 23; }; uint32_t val; } scl_stop_setup; union { struct { - uint32_t scl_thres: 4; - uint32_t sda_thres: 4; - uint32_t scl_en: 1; - uint32_t sda_en: 1; - uint32_t reserved10: 22; + uint32_t scl_thres : 4; + uint32_t sda_thres : 4; + uint32_t scl_en : 1; + uint32_t sda_en : 1; + uint32_t reserved10 : 22; }; uint32_t val; } filter_cfg; union { struct { - uint32_t sclk_div_num: 8; - uint32_t sclk_div_a: 6; - uint32_t sclk_div_b: 6; - uint32_t sclk_sel: 1; - uint32_t sclk_active: 1; - uint32_t reserved22: 10; + uint32_t sclk_div_num : 8; + uint32_t sclk_div_a : 6; + uint32_t sclk_div_b : 6; + uint32_t sclk_sel : 1; + uint32_t sclk_active : 1; + uint32_t reserved22 : 10; }; uint32_t val; } clk_conf; union { struct { - uint32_t command0: 14; + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ uint32_t reserved14: 17; uint32_t done: 1; }; @@ -292,34 +303,36 @@ typedef volatile struct { } command[8]; union { struct { - uint32_t scl_st_to: 5; /*no more than 23*/ - uint32_t reserved5: 27; + uint32_t scl_st_to : 5; /*no more than 23*/ + uint32_t reserved5 : 27; }; uint32_t val; } scl_st_time_out; union { struct { - uint32_t scl_main_st_to: 5; /*no more than 23*/ - uint32_t reserved5: 27; + uint32_t scl_main_st_to : 5; /*no more than 23*/ + uint32_t reserved5 : 27; }; uint32_t val; } scl_main_st_time_out; union { struct { - uint32_t scl_rst_slv_en: 1; - uint32_t scl_rst_slv_num: 5; - uint32_t scl_pd_en: 1; - uint32_t sda_pd_en: 1; - uint32_t reserved8: 24; + uint32_t scl_rst_slv_en : 1; + uint32_t scl_rst_slv_num : 5; + uint32_t scl_pd_en : 1; + uint32_t sda_pd_en : 1; + uint32_t reserved8 : 24; }; uint32_t val; } scl_sp_conf; union { struct { - uint32_t stretch_protect_num: 10; - uint32_t slave_scl_stretch_en: 1; - uint32_t slave_scl_stretch_clr: 1; - uint32_t reserved12: 20; + uint32_t stretch_protect_num : 10; + uint32_t slave_scl_stretch_en : 1; + uint32_t slave_scl_stretch_clr : 1; + uint32_t slave_byte_ack_ctl_en : 1; + uint32_t slave_byte_ack_level : 1; + uint32_t reserved14 : 18; }; uint32_t val; } scl_stretch_conf; @@ -351,9 +364,9 @@ typedef volatile struct { uint32_t reserved_ec; uint32_t reserved_f0; uint32_t reserved_f4; - uint32_t date; /**/ + uint32_t date; uint32_t reserved_fc; - uint32_t txfifo_start_addr; /**/ + uint32_t txfifo_start_addr; uint32_t reserved_104; uint32_t reserved_108; uint32_t reserved_10c; @@ -385,12 +398,10 @@ typedef volatile struct { uint32_t reserved_174; uint32_t reserved_178; uint32_t reserved_17c; - uint32_t fifo_start_addr; /**/ + uint32_t rxfifo_start_addr; } i2c_dev_t; - extern i2c_dev_t I2C0; extern i2c_dev_t I2C1; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/i2s_reg.h b/components/soc/esp32s3/include/soc/i2s_reg.h index 8b1240f10f..c0803de1df 100644 --- a/components/soc/esp32s3/include/soc/i2s_reg.h +++ b/components/soc/esp32s3/include/soc/i2s_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,961 +11,1095 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_I2S_REG_H_ +#define _SOC_I2S_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) -/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ -#define I2S_TX_HUNG_INT_RAW (BIT(3)) -#define I2S_TX_HUNG_INT_RAW_M (BIT(3)) -#define I2S_TX_HUNG_INT_RAW_V 0x1 -#define I2S_TX_HUNG_INT_RAW_S 3 -/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ -#define I2S_RX_HUNG_INT_RAW (BIT(2)) -#define I2S_RX_HUNG_INT_RAW_M (BIT(2)) -#define I2S_RX_HUNG_INT_RAW_V 0x1 -#define I2S_RX_HUNG_INT_RAW_S 2 -/* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the i2s_tx_done_int interrupt*/ -#define I2S_TX_DONE_INT_RAW (BIT(1)) -#define I2S_TX_DONE_INT_RAW_M (BIT(1)) -#define I2S_TX_DONE_INT_RAW_V 0x1 -#define I2S_TX_DONE_INT_RAW_S 1 -/* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the i2s_rx_done_int interrupt*/ -#define I2S_RX_DONE_INT_RAW (BIT(0)) -#define I2S_RX_DONE_INT_RAW_M (BIT(0)) -#define I2S_RX_DONE_INT_RAW_V 0x1 -#define I2S_RX_DONE_INT_RAW_S 0 +#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xC) +/* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.*/ +#define I2S_TX_HUNG_INT_RAW (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_M (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_V 0x1 +#define I2S_TX_HUNG_INT_RAW_S 3 +/* I2S_RX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_rx_hung_int interrupt.*/ +#define I2S_RX_HUNG_INT_RAW (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_M (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_V 0x1 +#define I2S_RX_HUNG_INT_RAW_S 2 +/* I2S_TX_DONE_INT_RAW : RO/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_tx_done_int interrupt.*/ +#define I2S_TX_DONE_INT_RAW (BIT(1)) +#define I2S_TX_DONE_INT_RAW_M (BIT(1)) +#define I2S_TX_DONE_INT_RAW_V 0x1 +#define I2S_TX_DONE_INT_RAW_S 1 +/* I2S_RX_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_rx_done_int interrupt.*/ +#define I2S_RX_DONE_INT_RAW (BIT(0)) +#define I2S_RX_DONE_INT_RAW_M (BIT(0)) +#define I2S_RX_DONE_INT_RAW_V 0x1 +#define I2S_RX_DONE_INT_RAW_S 0 -#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) +#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10) /* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ -#define I2S_TX_HUNG_INT_ST (BIT(3)) -#define I2S_TX_HUNG_INT_ST_M (BIT(3)) -#define I2S_TX_HUNG_INT_ST_V 0x1 -#define I2S_TX_HUNG_INT_ST_S 3 +/*description: The masked interrupt status bit for the i2s_tx_hung_int interrupt.*/ +#define I2S_TX_HUNG_INT_ST (BIT(3)) +#define I2S_TX_HUNG_INT_ST_M (BIT(3)) +#define I2S_TX_HUNG_INT_ST_V 0x1 +#define I2S_TX_HUNG_INT_ST_S 3 /* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ -#define I2S_RX_HUNG_INT_ST (BIT(2)) -#define I2S_RX_HUNG_INT_ST_M (BIT(2)) -#define I2S_RX_HUNG_INT_ST_V 0x1 -#define I2S_RX_HUNG_INT_ST_S 2 +/*description: The masked interrupt status bit for the i2s_rx_hung_int interrupt.*/ +#define I2S_RX_HUNG_INT_ST (BIT(2)) +#define I2S_RX_HUNG_INT_ST_M (BIT(2)) +#define I2S_RX_HUNG_INT_ST_V 0x1 +#define I2S_RX_HUNG_INT_ST_S 2 /* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the i2s_tx_done_int interrupt*/ -#define I2S_TX_DONE_INT_ST (BIT(1)) -#define I2S_TX_DONE_INT_ST_M (BIT(1)) -#define I2S_TX_DONE_INT_ST_V 0x1 -#define I2S_TX_DONE_INT_ST_S 1 +/*description: The masked interrupt status bit for the i2s_tx_done_int interrupt.*/ +#define I2S_TX_DONE_INT_ST (BIT(1)) +#define I2S_TX_DONE_INT_ST_M (BIT(1)) +#define I2S_TX_DONE_INT_ST_V 0x1 +#define I2S_TX_DONE_INT_ST_S 1 /* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the i2s_rx_done_int interrupt*/ -#define I2S_RX_DONE_INT_ST (BIT(0)) -#define I2S_RX_DONE_INT_ST_M (BIT(0)) -#define I2S_RX_DONE_INT_ST_V 0x1 -#define I2S_RX_DONE_INT_ST_S 0 +/*description: The masked interrupt status bit for the i2s_rx_done_int interrupt.*/ +#define I2S_RX_DONE_INT_ST (BIT(0)) +#define I2S_RX_DONE_INT_ST_M (BIT(0)) +#define I2S_RX_DONE_INT_ST_V 0x1 +#define I2S_RX_DONE_INT_ST_S 0 -#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) +#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14) /* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the i2s_tx_hung_int interrupt*/ -#define I2S_TX_HUNG_INT_ENA (BIT(3)) -#define I2S_TX_HUNG_INT_ENA_M (BIT(3)) -#define I2S_TX_HUNG_INT_ENA_V 0x1 -#define I2S_TX_HUNG_INT_ENA_S 3 +/*description: The interrupt enable bit for the i2s_tx_hung_int interrupt.*/ +#define I2S_TX_HUNG_INT_ENA (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_M (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_V 0x1 +#define I2S_TX_HUNG_INT_ENA_S 3 /* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the i2s_rx_hung_int interrupt*/ -#define I2S_RX_HUNG_INT_ENA (BIT(2)) -#define I2S_RX_HUNG_INT_ENA_M (BIT(2)) -#define I2S_RX_HUNG_INT_ENA_V 0x1 -#define I2S_RX_HUNG_INT_ENA_S 2 +/*description: The interrupt enable bit for the i2s_rx_hung_int interrupt.*/ +#define I2S_RX_HUNG_INT_ENA (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_M (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_V 0x1 +#define I2S_RX_HUNG_INT_ENA_S 2 /* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the i2s_tx_done_int interrupt*/ -#define I2S_TX_DONE_INT_ENA (BIT(1)) -#define I2S_TX_DONE_INT_ENA_M (BIT(1)) -#define I2S_TX_DONE_INT_ENA_V 0x1 -#define I2S_TX_DONE_INT_ENA_S 1 +/*description: The interrupt enable bit for the i2s_tx_done_int interrupt.*/ +#define I2S_TX_DONE_INT_ENA (BIT(1)) +#define I2S_TX_DONE_INT_ENA_M (BIT(1)) +#define I2S_TX_DONE_INT_ENA_V 0x1 +#define I2S_TX_DONE_INT_ENA_S 1 /* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the i2s_rx_done_int interrupt*/ -#define I2S_RX_DONE_INT_ENA (BIT(0)) -#define I2S_RX_DONE_INT_ENA_M (BIT(0)) -#define I2S_RX_DONE_INT_ENA_V 0x1 -#define I2S_RX_DONE_INT_ENA_S 0 +/*description: The interrupt enable bit for the i2s_rx_done_int interrupt.*/ +#define I2S_RX_DONE_INT_ENA (BIT(0)) +#define I2S_RX_DONE_INT_ENA_M (BIT(0)) +#define I2S_RX_DONE_INT_ENA_V 0x1 +#define I2S_RX_DONE_INT_ENA_S 0 -#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) -/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/ -#define I2S_TX_HUNG_INT_CLR (BIT(3)) -#define I2S_TX_HUNG_INT_CLR_M (BIT(3)) -#define I2S_TX_HUNG_INT_CLR_V 0x1 -#define I2S_TX_HUNG_INT_CLR_S 3 -/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/ -#define I2S_RX_HUNG_INT_CLR (BIT(2)) -#define I2S_RX_HUNG_INT_CLR_M (BIT(2)) -#define I2S_RX_HUNG_INT_CLR_V 0x1 -#define I2S_RX_HUNG_INT_CLR_S 2 -/* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the i2s_tx_done_int interrupt*/ -#define I2S_TX_DONE_INT_CLR (BIT(1)) -#define I2S_TX_DONE_INT_CLR_M (BIT(1)) -#define I2S_TX_DONE_INT_CLR_V 0x1 -#define I2S_TX_DONE_INT_CLR_S 1 -/* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the i2s_rx_done_int interrupt*/ -#define I2S_RX_DONE_INT_CLR (BIT(0)) -#define I2S_RX_DONE_INT_CLR_M (BIT(0)) -#define I2S_RX_DONE_INT_CLR_V 0x1 -#define I2S_RX_DONE_INT_CLR_S 0 +#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18) +/* I2S_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_tx_hung_int interrupt.*/ +#define I2S_TX_HUNG_INT_CLR (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_M (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_V 0x1 +#define I2S_TX_HUNG_INT_CLR_S 3 +/* I2S_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_rx_hung_int interrupt.*/ +#define I2S_RX_HUNG_INT_CLR (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_M (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_V 0x1 +#define I2S_RX_HUNG_INT_CLR_S 2 +/* I2S_TX_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_tx_done_int interrupt.*/ +#define I2S_TX_DONE_INT_CLR (BIT(1)) +#define I2S_TX_DONE_INT_CLR_M (BIT(1)) +#define I2S_TX_DONE_INT_CLR_V 0x1 +#define I2S_TX_DONE_INT_CLR_S 1 +/* I2S_RX_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_rx_done_int interrupt.*/ +#define I2S_RX_DONE_INT_CLR (BIT(0)) +#define I2S_RX_DONE_INT_CLR_M (BIT(0)) +#define I2S_RX_DONE_INT_CLR_V 0x1 +#define I2S_RX_DONE_INT_CLR_S 0 -#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) +#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20) /* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: */ -#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(22)) -#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(22)) -#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 -#define I2S_RX_PDM_SINC_DSR_16_EN_S 22 +/*description: Configure the down sampling rate of PDM RX filter group1 module. 1: The down sa +mpling rate is 128. 0: down sampling rate is 64..*/ +#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(22)) +#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(22)) +#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 +#define I2S_RX_PDM_SINC_DSR_16_EN_S 22 /* I2S_RX_PDM2PCM_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: 1: Enable PDM2PCM RX mode. 0: DIsable.*/ -#define I2S_RX_PDM2PCM_EN (BIT(21)) -#define I2S_RX_PDM2PCM_EN_M (BIT(21)) -#define I2S_RX_PDM2PCM_EN_V 0x1 -#define I2S_RX_PDM2PCM_EN_S 21 +/*description: 1: Enable PDM2PCM RX mode. 0: DIsable..*/ +#define I2S_RX_PDM2PCM_EN (BIT(21)) +#define I2S_RX_PDM2PCM_EN_M (BIT(21)) +#define I2S_RX_PDM2PCM_EN_V 0x1 +#define I2S_RX_PDM2PCM_EN_S 21 /* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/ -#define I2S_RX_PDM_EN (BIT(20)) -#define I2S_RX_PDM_EN_M (BIT(20)) -#define I2S_RX_PDM_EN_V 0x1 -#define I2S_RX_PDM_EN_S 20 +/*description: 1: Enable I2S PDM Rx mode . 0: Disable..*/ +#define I2S_RX_PDM_EN (BIT(20)) +#define I2S_RX_PDM_EN_M (BIT(20)) +#define I2S_RX_PDM_EN_V 0x1 +#define I2S_RX_PDM_EN_S 20 /* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/ -#define I2S_RX_TDM_EN (BIT(19)) -#define I2S_RX_TDM_EN_M (BIT(19)) -#define I2S_RX_TDM_EN_V 0x1 -#define I2S_RX_TDM_EN_S 19 +/*description: 1: Enable I2S TDM Rx mode . 0: Disable..*/ +#define I2S_RX_TDM_EN (BIT(19)) +#define I2S_RX_TDM_EN_M (BIT(19)) +#define I2S_RX_TDM_EN_V 0x1 +#define I2S_RX_TDM_EN_S 19 /* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: I2S Rx bit endian. 1:small endian the LSB is received first. - 0:big endian the MSB is received first.*/ -#define I2S_RX_BIT_ORDER (BIT(18)) -#define I2S_RX_BIT_ORDER_M (BIT(18)) -#define I2S_RX_BIT_ORDER_V 0x1 -#define I2S_RX_BIT_ORDER_S 18 +/*description: I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the +MSB is received first..*/ +#define I2S_RX_BIT_ORDER (BIT(18)) +#define I2S_RX_BIT_ORDER_M (BIT(18)) +#define I2S_RX_BIT_ORDER_V 0x1 +#define I2S_RX_BIT_ORDER_S 18 /* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: 0: WS should be 0 when receiving left channel data and WS is - 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ -#define I2S_RX_WS_IDLE_POL (BIT(17)) -#define I2S_RX_WS_IDLE_POL_M (BIT(17)) -#define I2S_RX_WS_IDLE_POL_V 0x1 -#define I2S_RX_WS_IDLE_POL_S 17 +/*description: 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + 1: WS should be 1 when receiving left channel data, and WS is 0in right channe +l. .*/ +#define I2S_RX_WS_IDLE_POL (BIT(17)) +#define I2S_RX_WS_IDLE_POL_M (BIT(17)) +#define I2S_RX_WS_IDLE_POL_V 0x1 +#define I2S_RX_WS_IDLE_POL_S 17 /* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ -#define I2S_RX_24_FILL_EN (BIT(16)) -#define I2S_RX_24_FILL_EN_M (BIT(16)) -#define I2S_RX_24_FILL_EN_V 0x1 -#define I2S_RX_24_FILL_EN_S 16 +/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits..*/ +#define I2S_RX_24_FILL_EN (BIT(16)) +#define I2S_RX_24_FILL_EN_M (BIT(16)) +#define I2S_RX_24_FILL_EN_V 0x1 +#define I2S_RX_24_FILL_EN_S 16 /* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ -#define I2S_RX_LEFT_ALIGN (BIT(15)) -#define I2S_RX_LEFT_ALIGN_M (BIT(15)) -#define I2S_RX_LEFT_ALIGN_V 0x1 -#define I2S_RX_LEFT_ALIGN_S 15 +/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode..*/ +#define I2S_RX_LEFT_ALIGN (BIT(15)) +#define I2S_RX_LEFT_ALIGN_M (BIT(15)) +#define I2S_RX_LEFT_ALIGN_V 0x1 +#define I2S_RX_LEFT_ALIGN_S 15 /* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */ -/*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop - when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ -#define I2S_RX_STOP_MODE 0x00000003 -#define I2S_RX_STOP_MODE_M ((I2S_RX_STOP_MODE_V) << (I2S_RX_STOP_MODE_S)) -#define I2S_RX_STOP_MODE_V 0x3 -#define I2S_RX_STOP_MODE_S 13 +/*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start +is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is +full..*/ +#define I2S_RX_STOP_MODE 0x00000003 +#define I2S_RX_STOP_MODE_M ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S)) +#define I2S_RX_STOP_MODE_V 0x3 +#define I2S_RX_STOP_MODE_S 13 /* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: Set this bit to bypass Compress/Decompress module for received data.*/ -#define I2S_RX_PCM_BYPASS (BIT(12)) -#define I2S_RX_PCM_BYPASS_M (BIT(12)) -#define I2S_RX_PCM_BYPASS_V 0x1 -#define I2S_RX_PCM_BYPASS_S 12 +/*description: Set this bit to bypass Compress/Decompress module for received data..*/ +#define I2S_RX_PCM_BYPASS (BIT(12)) +#define I2S_RX_PCM_BYPASS_M (BIT(12)) +#define I2S_RX_PCM_BYPASS_V 0x1 +#define I2S_RX_PCM_BYPASS_S 12 /* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */ -/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law - decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ -#define I2S_RX_PCM_CONF 0x00000003 -#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V) << (I2S_RX_PCM_CONF_S)) -#define I2S_RX_PCM_CONF_V 0x3 -#define I2S_RX_PCM_CONF_S 10 +/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (l +toa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &.*/ +#define I2S_RX_PCM_CONF 0x00000003 +#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S)) +#define I2S_RX_PCM_CONF_V 0x3 +#define I2S_RX_PCM_CONF_S 10 /* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: 1: The first channel data value is valid in I2S RX mono mode. - 0: The second channel data value is valid in I2S RX mono mode.*/ -#define I2S_RX_MONO_FST_VLD (BIT(9)) -#define I2S_RX_MONO_FST_VLD_M (BIT(9)) -#define I2S_RX_MONO_FST_VLD_V 0x1 -#define I2S_RX_MONO_FST_VLD_S 9 -/* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set 1 to update I2S RX registers from APB clock domain to I2S - RX clock domain. This bit will be cleared by hardware after update register done.*/ -#define I2S_RX_UPDATE (BIT(8)) -#define I2S_RX_UPDATE_M (BIT(8)) -#define I2S_RX_UPDATE_V 0x1 -#define I2S_RX_UPDATE_S 8 +/*description: 1: The first channel data value is valid in I2S RX mono mode. 0: The second ch +annel data value is valid in I2S RX mono mode..*/ +#define I2S_RX_MONO_FST_VLD (BIT(9)) +#define I2S_RX_MONO_FST_VLD_M (BIT(9)) +#define I2S_RX_MONO_FST_VLD_V 0x1 +#define I2S_RX_MONO_FST_VLD_S 9 +/* I2S_RX_UPDATE : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. T +his bit will be cleared by hardware after update register done..*/ +#define I2S_RX_UPDATE (BIT(8)) +#define I2S_RX_UPDATE_M (BIT(8)) +#define I2S_RX_UPDATE_V 0x1 +#define I2S_RX_UPDATE_S 8 /* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: I2S Rx byte endian 1: low addr value to high addr. 0: low addr - with low addr value.*/ -#define I2S_RX_BIG_ENDIAN (BIT(7)) -#define I2S_RX_BIG_ENDIAN_M (BIT(7)) -#define I2S_RX_BIG_ENDIAN_V 0x1 -#define I2S_RX_BIG_ENDIAN_S 7 +/*description: I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr va +lue..*/ +#define I2S_RX_BIG_ENDIAN (BIT(7)) +#define I2S_RX_BIG_ENDIAN_M (BIT(7)) +#define I2S_RX_BIG_ENDIAN_V 0x1 +#define I2S_RX_BIG_ENDIAN_S 7 /* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable receiver in mono mode*/ -#define I2S_RX_MONO (BIT(5)) -#define I2S_RX_MONO_M (BIT(5)) -#define I2S_RX_MONO_V 0x1 -#define I2S_RX_MONO_S 5 +/*description: Set this bit to enable receiver in mono mode.*/ +#define I2S_RX_MONO (BIT(5)) +#define I2S_RX_MONO_M (BIT(5)) +#define I2S_RX_MONO_V 0x1 +#define I2S_RX_MONO_S 5 /* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable slave receiver mode*/ -#define I2S_RX_SLAVE_MOD (BIT(3)) -#define I2S_RX_SLAVE_MOD_M (BIT(3)) -#define I2S_RX_SLAVE_MOD_V 0x1 -#define I2S_RX_SLAVE_MOD_S 3 +/*description: Set this bit to enable slave receiver mode.*/ +#define I2S_RX_SLAVE_MOD (BIT(3)) +#define I2S_RX_SLAVE_MOD_M (BIT(3)) +#define I2S_RX_SLAVE_MOD_V 0x1 +#define I2S_RX_SLAVE_MOD_S 3 /* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to start receiving data*/ -#define I2S_RX_START (BIT(2)) -#define I2S_RX_START_M (BIT(2)) -#define I2S_RX_START_V 0x1 -#define I2S_RX_START_S 2 -/* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset Rx AFIFO*/ -#define I2S_RX_FIFO_RESET (BIT(1)) -#define I2S_RX_FIFO_RESET_M (BIT(1)) -#define I2S_RX_FIFO_RESET_V 0x1 -#define I2S_RX_FIFO_RESET_S 1 -/* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to reset receiver*/ -#define I2S_RX_RESET (BIT(0)) -#define I2S_RX_RESET_M (BIT(0)) -#define I2S_RX_RESET_V 0x1 -#define I2S_RX_RESET_S 0 +/*description: Set this bit to start receiving data.*/ +#define I2S_RX_START (BIT(2)) +#define I2S_RX_START_M (BIT(2)) +#define I2S_RX_START_V 0x1 +#define I2S_RX_START_S 2 +/* I2S_RX_FIFO_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset Rx AFIFO.*/ +#define I2S_RX_FIFO_RESET (BIT(1)) +#define I2S_RX_FIFO_RESET_M (BIT(1)) +#define I2S_RX_FIFO_RESET_V 0x1 +#define I2S_RX_FIFO_RESET_S 1 +/* I2S_RX_RESET : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to reset receiver.*/ +#define I2S_RX_RESET (BIT(0)) +#define I2S_RX_RESET_M (BIT(0)) +#define I2S_RX_RESET_V 0x1 +#define I2S_RX_RESET_S 0 -#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0024) +#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24) /* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Enable signal loop back mode with transmitter module and receiver - module sharing the same WS and BCK signals.*/ -#define I2S_SIG_LOOPBACK (BIT(27)) -#define I2S_SIG_LOOPBACK_M (BIT(27)) -#define I2S_SIG_LOOPBACK_V 0x1 -#define I2S_SIG_LOOPBACK_S 27 +/*description: Enable signal loop back mode with transmitter module and receiver module sharing + the same WS and BCK signals..*/ +#define I2S_SIG_LOOPBACK (BIT(27)) +#define I2S_SIG_LOOPBACK_M (BIT(27)) +#define I2S_SIG_LOOPBACK_V 0x1 +#define I2S_SIG_LOOPBACK_S 27 /* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: I2S transmitter channel mode configuration bits.*/ -#define I2S_TX_CHAN_MOD 0x00000007 -#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V) << (I2S_TX_CHAN_MOD_S)) -#define I2S_TX_CHAN_MOD_V 0x7 -#define I2S_TX_CHAN_MOD_S 24 +/*description: I2S transmitter channel mode configuration bits..*/ +#define I2S_TX_CHAN_MOD 0x00000007 +#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S)) +#define I2S_TX_CHAN_MOD_V 0x7 +#define I2S_TX_CHAN_MOD_S 24 /* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/ -#define I2S_TX_PDM_EN (BIT(20)) -#define I2S_TX_PDM_EN_M (BIT(20)) -#define I2S_TX_PDM_EN_V 0x1 -#define I2S_TX_PDM_EN_S 20 +/*description: 1: Enable I2S PDM Tx mode . 0: Disable..*/ +#define I2S_TX_PDM_EN (BIT(20)) +#define I2S_TX_PDM_EN_M (BIT(20)) +#define I2S_TX_PDM_EN_V 0x1 +#define I2S_TX_PDM_EN_S 20 /* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/ -#define I2S_TX_TDM_EN (BIT(19)) -#define I2S_TX_TDM_EN_M (BIT(19)) -#define I2S_TX_TDM_EN_V 0x1 -#define I2S_TX_TDM_EN_S 19 +/*description: 1: Enable I2S TDM Tx mode . 0: Disable..*/ +#define I2S_TX_TDM_EN (BIT(19)) +#define I2S_TX_TDM_EN_M (BIT(19)) +#define I2S_TX_TDM_EN_V 0x1 +#define I2S_TX_TDM_EN_S 19 /* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big - endian the MSB is sent first.*/ -#define I2S_TX_BIT_ORDER (BIT(18)) -#define I2S_TX_BIT_ORDER_M (BIT(18)) -#define I2S_TX_BIT_ORDER_V 0x1 -#define I2S_TX_BIT_ORDER_S 18 +/*description: I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB +is sent first..*/ +#define I2S_TX_BIT_ORDER (BIT(18)) +#define I2S_TX_BIT_ORDER_M (BIT(18)) +#define I2S_TX_BIT_ORDER_V 0x1 +#define I2S_TX_BIT_ORDER_S 18 /* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: 0: WS should be 0 when sending left channel data and WS is 1in - right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ -#define I2S_TX_WS_IDLE_POL (BIT(17)) -#define I2S_TX_WS_IDLE_POL_M (BIT(17)) -#define I2S_TX_WS_IDLE_POL_V 0x1 -#define I2S_TX_WS_IDLE_POL_S 17 +/*description: 0: WS should be 0 when sending left channel data, and WS is 1in right channel. +1: WS should be 1 when sending left channel data, and WS is 0in right channel. .*/ +#define I2S_TX_WS_IDLE_POL (BIT(17)) +#define I2S_TX_WS_IDLE_POL_M (BIT(17)) +#define I2S_TX_WS_IDLE_POL_V 0x1 +#define I2S_TX_WS_IDLE_POL_S 17 /* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ -#define I2S_TX_24_FILL_EN (BIT(16)) -#define I2S_TX_24_FILL_EN_M (BIT(16)) -#define I2S_TX_24_FILL_EN_V 0x1 -#define I2S_TX_24_FILL_EN_S 16 +/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode.*/ +#define I2S_TX_24_FILL_EN (BIT(16)) +#define I2S_TX_24_FILL_EN_M (BIT(16)) +#define I2S_TX_24_FILL_EN_V 0x1 +#define I2S_TX_24_FILL_EN_S 16 /* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */ -/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ -#define I2S_TX_LEFT_ALIGN (BIT(15)) -#define I2S_TX_LEFT_ALIGN_M (BIT(15)) -#define I2S_TX_LEFT_ALIGN_V 0x1 -#define I2S_TX_LEFT_ALIGN_S 15 +/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode..*/ +#define I2S_TX_LEFT_ALIGN (BIT(15)) +#define I2S_TX_LEFT_ALIGN_M (BIT(15)) +#define I2S_TX_LEFT_ALIGN_V 0x1 +#define I2S_TX_LEFT_ALIGN_S 15 /* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: Set this bit to stop disable output BCK signal and WS signal - when tx FIFO is emtpy*/ -#define I2S_TX_STOP_EN (BIT(13)) -#define I2S_TX_STOP_EN_M (BIT(13)) -#define I2S_TX_STOP_EN_V 0x1 -#define I2S_TX_STOP_EN_S 13 +/*description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emt +py.*/ +#define I2S_TX_STOP_EN (BIT(13)) +#define I2S_TX_STOP_EN_M (BIT(13)) +#define I2S_TX_STOP_EN_V 0x1 +#define I2S_TX_STOP_EN_S 13 /* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: Set this bit to bypass Compress/Decompress module for transmitted data.*/ -#define I2S_TX_PCM_BYPASS (BIT(12)) -#define I2S_TX_PCM_BYPASS_M (BIT(12)) -#define I2S_TX_PCM_BYPASS_V 0x1 -#define I2S_TX_PCM_BYPASS_S 12 +/*description: Set this bit to bypass Compress/Decompress module for transmitted data..*/ +#define I2S_TX_PCM_BYPASS (BIT(12)) +#define I2S_TX_PCM_BYPASS_M (BIT(12)) +#define I2S_TX_PCM_BYPASS_V 0x1 +#define I2S_TX_PCM_BYPASS_S 12 /* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law - decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ -#define I2S_TX_PCM_CONF 0x00000003 -#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V) << (I2S_TX_PCM_CONF_S)) -#define I2S_TX_PCM_CONF_V 0x3 -#define I2S_TX_PCM_CONF_S 10 +/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (l +toa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &.*/ +#define I2S_TX_PCM_CONF 0x00000003 +#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S)) +#define I2S_TX_PCM_CONF_V 0x3 +#define I2S_TX_PCM_CONF_S 10 /* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: 1: The first channel data value is valid in I2S TX mono mode. - 0: The second channel data value is valid in I2S TX mono mode.*/ -#define I2S_TX_MONO_FST_VLD (BIT(9)) -#define I2S_TX_MONO_FST_VLD_M (BIT(9)) -#define I2S_TX_MONO_FST_VLD_V 0x1 -#define I2S_TX_MONO_FST_VLD_S 9 -/* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set 1 to update I2S TX registers from APB clock domain to I2S - TX clock domain. This bit will be cleared by hardware after update register done.*/ -#define I2S_TX_UPDATE (BIT(8)) -#define I2S_TX_UPDATE_M (BIT(8)) -#define I2S_TX_UPDATE_V 0x1 -#define I2S_TX_UPDATE_S 8 +/*description: 1: The first channel data value is valid in I2S TX mono mode. 0: The second ch +annel data value is valid in I2S TX mono mode..*/ +#define I2S_TX_MONO_FST_VLD (BIT(9)) +#define I2S_TX_MONO_FST_VLD_M (BIT(9)) +#define I2S_TX_MONO_FST_VLD_V 0x1 +#define I2S_TX_MONO_FST_VLD_S 9 +/* I2S_TX_UPDATE : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. T +his bit will be cleared by hardware after update register done..*/ +#define I2S_TX_UPDATE (BIT(8)) +#define I2S_TX_UPDATE_M (BIT(8)) +#define I2S_TX_UPDATE_V 0x1 +#define I2S_TX_UPDATE_S 8 /* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: I2S Tx byte endian 1: low addr value to high addr. 0: low addr - with low addr value.*/ -#define I2S_TX_BIG_ENDIAN (BIT(7)) -#define I2S_TX_BIG_ENDIAN_M (BIT(7)) -#define I2S_TX_BIG_ENDIAN_V 0x1 -#define I2S_TX_BIG_ENDIAN_S 7 +/*description: I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr v +alue..*/ +#define I2S_TX_BIG_ENDIAN (BIT(7)) +#define I2S_TX_BIG_ENDIAN_M (BIT(7)) +#define I2S_TX_BIG_ENDIAN_V 0x1 +#define I2S_TX_BIG_ENDIAN_S 7 /* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: The value of Left channel data is equal to the value of right - channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ -#define I2S_TX_CHAN_EQUAL (BIT(6)) -#define I2S_TX_CHAN_EQUAL_M (BIT(6)) -#define I2S_TX_CHAN_EQUAL_V 0x1 -#define I2S_TX_CHAN_EQUAL_S 6 +/*description: 1: The value of Left channel data is equal to the value of right channel data in + I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg +_i2s_single_data in I2S TX mono mode or TDM channel select mode..*/ +#define I2S_TX_CHAN_EQUAL (BIT(6)) +#define I2S_TX_CHAN_EQUAL_M (BIT(6)) +#define I2S_TX_CHAN_EQUAL_V 0x1 +#define I2S_TX_CHAN_EQUAL_S 6 /* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable transmitter in mono mode*/ -#define I2S_TX_MONO (BIT(5)) -#define I2S_TX_MONO_M (BIT(5)) -#define I2S_TX_MONO_V 0x1 -#define I2S_TX_MONO_S 5 +/*description: Set this bit to enable transmitter in mono mode .*/ +#define I2S_TX_MONO (BIT(5)) +#define I2S_TX_MONO_M (BIT(5)) +#define I2S_TX_MONO_V 0x1 +#define I2S_TX_MONO_S 5 /* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable slave transmitter mode*/ -#define I2S_TX_SLAVE_MOD (BIT(3)) -#define I2S_TX_SLAVE_MOD_M (BIT(3)) -#define I2S_TX_SLAVE_MOD_V 0x1 -#define I2S_TX_SLAVE_MOD_S 3 +/*description: Set this bit to enable slave transmitter mode .*/ +#define I2S_TX_SLAVE_MOD (BIT(3)) +#define I2S_TX_SLAVE_MOD_M (BIT(3)) +#define I2S_TX_SLAVE_MOD_V 0x1 +#define I2S_TX_SLAVE_MOD_S 3 /* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to start transmitting data*/ -#define I2S_TX_START (BIT(2)) -#define I2S_TX_START_M (BIT(2)) -#define I2S_TX_START_V 0x1 -#define I2S_TX_START_S 2 -/* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset Tx AFIFO*/ -#define I2S_TX_FIFO_RESET (BIT(1)) -#define I2S_TX_FIFO_RESET_M (BIT(1)) -#define I2S_TX_FIFO_RESET_V 0x1 -#define I2S_TX_FIFO_RESET_S 1 -/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to reset transmitter*/ -#define I2S_TX_RESET (BIT(0)) -#define I2S_TX_RESET_M (BIT(0)) -#define I2S_TX_RESET_V 0x1 -#define I2S_TX_RESET_S 0 +/*description: Set this bit to start transmitting data .*/ +#define I2S_TX_START (BIT(2)) +#define I2S_TX_START_M (BIT(2)) +#define I2S_TX_START_V 0x1 +#define I2S_TX_START_S 2 +/* I2S_TX_FIFO_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset Tx AFIFO.*/ +#define I2S_TX_FIFO_RESET (BIT(1)) +#define I2S_TX_FIFO_RESET_M (BIT(1)) +#define I2S_TX_FIFO_RESET_V 0x1 +#define I2S_TX_FIFO_RESET_S 1 +/* I2S_TX_RESET : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to reset transmitter.*/ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (BIT(0)) +#define I2S_TX_RESET_V 0x1 +#define I2S_TX_RESET_S 0 -#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0028) +#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28) /* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: Set this bit to enable receiver in Phillips standard mode*/ -#define I2S_RX_MSB_SHIFT (BIT(29)) -#define I2S_RX_MSB_SHIFT_M (BIT(29)) -#define I2S_RX_MSB_SHIFT_V 0x1 -#define I2S_RX_MSB_SHIFT_S 29 -/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ -/*description: The Rx bit number for each channel minus 1in TDM mode.*/ -#define I2S_RX_TDM_CHAN_BITS 0x0000001F -#define I2S_RX_TDM_CHAN_BITS_M ((I2S_RX_TDM_CHAN_BITS_V) << (I2S_RX_TDM_CHAN_BITS_S)) -#define I2S_RX_TDM_CHAN_BITS_V 0x1F -#define I2S_RX_TDM_CHAN_BITS_S 24 -/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ -/*description: I2S Rx half sample bits -1.*/ -#define I2S_RX_HALF_SAMPLE_BITS 0x0000003F -#define I2S_RX_HALF_SAMPLE_BITS_M ((I2S_RX_HALF_SAMPLE_BITS_V) << (I2S_RX_HALF_SAMPLE_BITS_S)) -#define I2S_RX_HALF_SAMPLE_BITS_V 0x3F -#define I2S_RX_HALF_SAMPLE_BITS_S 18 -/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ -/*description: Set the bits to configure bit length of I2S receiver channel.*/ -#define I2S_RX_BITS_MOD 0x0000001F -#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V) << (I2S_RX_BITS_MOD_S)) -#define I2S_RX_BITS_MOD_V 0x1F -#define I2S_RX_BITS_MOD_S 13 +/*description: Set this bit to enable receiver in Phillips standard mode.*/ +#define I2S_RX_MSB_SHIFT (BIT(29)) +#define I2S_RX_MSB_SHIFT_M (BIT(29)) +#define I2S_RX_MSB_SHIFT_V 0x1 +#define I2S_RX_MSB_SHIFT_S 29 +/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hf ; */ +/*description: The Rx bit number for each channel minus 1in TDM mode..*/ +#define I2S_RX_TDM_CHAN_BITS 0x0000001F +#define I2S_RX_TDM_CHAN_BITS_M ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S)) +#define I2S_RX_TDM_CHAN_BITS_V 0x1F +#define I2S_RX_TDM_CHAN_BITS_S 24 +/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hf ; */ +/*description: I2S Rx half sample bits -1..*/ +#define I2S_RX_HALF_SAMPLE_BITS 0x0000003F +#define I2S_RX_HALF_SAMPLE_BITS_M ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S)) +#define I2S_RX_HALF_SAMPLE_BITS_V 0x3F +#define I2S_RX_HALF_SAMPLE_BITS_S 18 +/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hf ; */ +/*description: Set the bits to configure the valid data bit length of I2S receiver channel. 7: +all the valid channel data is in 8-bit-mode. 15: all the valid channel data is i +n 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the vali +d channel data is in 32-bit-mode..*/ +#define I2S_RX_BITS_MOD 0x0000001F +#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S)) +#define I2S_RX_BITS_MOD_V 0x1F +#define I2S_RX_BITS_MOD_S 13 /* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ -/*description: Bit clock configuration bits in receiver mode.*/ -#define I2S_RX_BCK_DIV_NUM 0x0000003F -#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V) << (I2S_RX_BCK_DIV_NUM_S)) -#define I2S_RX_BCK_DIV_NUM_V 0x3F -#define I2S_RX_BCK_DIV_NUM_S 7 +/*description: Bit clock configuration bits in receiver mode. .*/ +#define I2S_RX_BCK_DIV_NUM 0x0000003F +#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S)) +#define I2S_RX_BCK_DIV_NUM_V 0x3F +#define I2S_RX_BCK_DIV_NUM_S 7 /* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ -#define I2S_RX_TDM_WS_WIDTH 0x0000007F -#define I2S_RX_TDM_WS_WIDTH_M ((I2S_RX_TDM_WS_WIDTH_V) << (I2S_RX_TDM_WS_WIDTH_S)) -#define I2S_RX_TDM_WS_WIDTH_V 0x7F -#define I2S_RX_TDM_WS_WIDTH_S 0 +/*description: The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck.*/ +#define I2S_RX_TDM_WS_WIDTH 0x0000007F +#define I2S_RX_TDM_WS_WIDTH_M ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S)) +#define I2S_RX_TDM_WS_WIDTH_V 0x7F +#define I2S_RX_TDM_WS_WIDTH_S 0 -#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x002C) +#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2C) +/* I2S_TX_BCK_NO_DLY : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed + to generate pos/neg edge in master mode..*/ +#define I2S_TX_BCK_NO_DLY (BIT(30)) +#define I2S_TX_BCK_NO_DLY_M (BIT(30)) +#define I2S_TX_BCK_NO_DLY_V 0x1 +#define I2S_TX_BCK_NO_DLY_S 30 /* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: Set this bit to enable transmitter in Phillips standard mode*/ -#define I2S_TX_MSB_SHIFT (BIT(29)) -#define I2S_TX_MSB_SHIFT_M (BIT(29)) -#define I2S_TX_MSB_SHIFT_V 0x1 -#define I2S_TX_MSB_SHIFT_S 29 -/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ -/*description: The Tx bit number for each channel minus 1in TDM mode.*/ -#define I2S_TX_TDM_CHAN_BITS 0x0000001F -#define I2S_TX_TDM_CHAN_BITS_M ((I2S_TX_TDM_CHAN_BITS_V) << (I2S_TX_TDM_CHAN_BITS_S)) -#define I2S_TX_TDM_CHAN_BITS_V 0x1F -#define I2S_TX_TDM_CHAN_BITS_S 24 -/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ -/*description: I2S Tx half sample bits -1.*/ -#define I2S_TX_HALF_SAMPLE_BITS 0x0000003F -#define I2S_TX_HALF_SAMPLE_BITS_M ((I2S_TX_HALF_SAMPLE_BITS_V) << (I2S_TX_HALF_SAMPLE_BITS_S)) -#define I2S_TX_HALF_SAMPLE_BITS_V 0x3F -#define I2S_TX_HALF_SAMPLE_BITS_S 18 -/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ -/*description: Set the bits to configure bit length of I2S transmitter channel.*/ -#define I2S_TX_BITS_MOD 0x0000001F -#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V) << (I2S_TX_BITS_MOD_S)) -#define I2S_TX_BITS_MOD_V 0x1F -#define I2S_TX_BITS_MOD_S 13 +/*description: Set this bit to enable transmitter in Phillips standard mode.*/ +#define I2S_TX_MSB_SHIFT (BIT(29)) +#define I2S_TX_MSB_SHIFT_M (BIT(29)) +#define I2S_TX_MSB_SHIFT_V 0x1 +#define I2S_TX_MSB_SHIFT_S 29 +/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hf ; */ +/*description: The Tx bit number for each channel minus 1in TDM mode..*/ +#define I2S_TX_TDM_CHAN_BITS 0x0000001F +#define I2S_TX_TDM_CHAN_BITS_M ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S)) +#define I2S_TX_TDM_CHAN_BITS_V 0x1F +#define I2S_TX_TDM_CHAN_BITS_S 24 +/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hf ; */ +/*description: I2S Tx half sample bits -1..*/ +#define I2S_TX_HALF_SAMPLE_BITS 0x0000003F +#define I2S_TX_HALF_SAMPLE_BITS_M ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S)) +#define I2S_TX_HALF_SAMPLE_BITS_V 0x3F +#define I2S_TX_HALF_SAMPLE_BITS_S 18 +/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hf ; */ +/*description: Set the bits to configure the valid data bit length of I2S transmitter channel. +7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data i +s in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the v +alid channel data is in 32-bit-mode..*/ +#define I2S_TX_BITS_MOD 0x0000001F +#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S)) +#define I2S_TX_BITS_MOD_V 0x1F +#define I2S_TX_BITS_MOD_S 13 /* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ -/*description: Bit clock configuration bits in transmitter mode.*/ -#define I2S_TX_BCK_DIV_NUM 0x0000003F -#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V) << (I2S_TX_BCK_DIV_NUM_S)) -#define I2S_TX_BCK_DIV_NUM_V 0x3F -#define I2S_TX_BCK_DIV_NUM_S 7 +/*description: Bit clock configuration bits in transmitter mode. .*/ +#define I2S_TX_BCK_DIV_NUM 0x0000003F +#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S)) +#define I2S_TX_BCK_DIV_NUM_V 0x3F +#define I2S_TX_BCK_DIV_NUM_S 7 /* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ -#define I2S_TX_TDM_WS_WIDTH 0x0000007F -#define I2S_TX_TDM_WS_WIDTH_M ((I2S_TX_TDM_WS_WIDTH_V) << (I2S_TX_TDM_WS_WIDTH_S)) -#define I2S_TX_TDM_WS_WIDTH_V 0x7F -#define I2S_TX_TDM_WS_WIDTH_S 0 +/*description: The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck.*/ +#define I2S_TX_TDM_WS_WIDTH 0x0000007F +#define I2S_TX_TDM_WS_WIDTH_M ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S)) +#define I2S_TX_TDM_WS_WIDTH_V 0x7F +#define I2S_TX_TDM_WS_WIDTH_S 0 -#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0030) +#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x30) /* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module - clock as I2S_MCLK_OUT.*/ -#define I2S_MCLK_SEL (BIT(29)) -#define I2S_MCLK_SEL_M (BIT(29)) -#define I2S_MCLK_SEL_V 0x1 -#define I2S_MCLK_SEL_S 29 +/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MC +LK_OUT. .*/ +#define I2S_MCLK_SEL (BIT(29)) +#define I2S_MCLK_SEL_M (BIT(29)) +#define I2S_MCLK_SEL_V 0x1 +#define I2S_MCLK_SEL_S 29 /* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. - 3: I2S_MCLK_in.*/ -#define I2S_RX_CLK_SEL 0x00000003 -#define I2S_RX_CLK_SEL_M ((I2S_RX_CLK_SEL_V) << (I2S_RX_CLK_SEL_S)) -#define I2S_RX_CLK_SEL_V 0x3 -#define I2S_RX_CLK_SEL_S 27 +/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_ +in..*/ +#define I2S_RX_CLK_SEL 0x00000003 +#define I2S_RX_CLK_SEL_M ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S)) +#define I2S_RX_CLK_SEL_V 0x3 +#define I2S_RX_CLK_SEL_S 27 /* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: I2S Rx module clock enable signal.*/ -#define I2S_RX_CLK_ACTIVE (BIT(26)) -#define I2S_RX_CLK_ACTIVE_M (BIT(26)) -#define I2S_RX_CLK_ACTIVE_V 0x1 -#define I2S_RX_CLK_ACTIVE_S 26 +/*description: I2S Rx module clock enable signal..*/ +#define I2S_RX_CLK_ACTIVE (BIT(26)) +#define I2S_RX_CLK_ACTIVE_M (BIT(26)) +#define I2S_RX_CLK_ACTIVE_V 0x1 +#define I2S_RX_CLK_ACTIVE_S 26 /* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: Integral I2S clock divider value*/ -#define I2S_RX_CLKM_DIV_NUM 0x000000FF -#define I2S_RX_CLKM_DIV_NUM_M ((I2S_RX_CLKM_DIV_NUM_V) << (I2S_RX_CLKM_DIV_NUM_S)) -#define I2S_RX_CLKM_DIV_NUM_V 0xFF -#define I2S_RX_CLKM_DIV_NUM_S 0 +/*description: Integral I2S clock divider value.*/ +#define I2S_RX_CLKM_DIV_NUM 0x000000FF +#define I2S_RX_CLKM_DIV_NUM_M ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S)) +#define I2S_RX_CLKM_DIV_NUM_V 0xFF +#define I2S_RX_CLKM_DIV_NUM_S 0 -#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0034) +#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x34) /* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable clk gate*/ -#define I2S_CLK_EN (BIT(29)) -#define I2S_CLK_EN_M (BIT(29)) -#define I2S_CLK_EN_V 0x1 -#define I2S_CLK_EN_S 29 +/*description: Set this bit to enable clk gate.*/ +#define I2S_CLK_EN (BIT(29)) +#define I2S_CLK_EN_M (BIT(29)) +#define I2S_CLK_EN_V 0x1 +#define I2S_CLK_EN_S 29 /* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: - CLK160. 3: I2S_MCLK_in.*/ -#define I2S_TX_CLK_SEL 0x00000003 -#define I2S_TX_CLK_SEL_M ((I2S_TX_CLK_SEL_V) << (I2S_TX_CLK_SEL_S)) -#define I2S_TX_CLK_SEL_V 0x3 -#define I2S_TX_CLK_SEL_S 27 +/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCL +K_in..*/ +#define I2S_TX_CLK_SEL 0x00000003 +#define I2S_TX_CLK_SEL_M ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S)) +#define I2S_TX_CLK_SEL_V 0x3 +#define I2S_TX_CLK_SEL_S 27 /* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: I2S Tx module clock enable signal.*/ -#define I2S_TX_CLK_ACTIVE (BIT(26)) -#define I2S_TX_CLK_ACTIVE_M (BIT(26)) -#define I2S_TX_CLK_ACTIVE_V 0x1 -#define I2S_TX_CLK_ACTIVE_S 26 +/*description: I2S Tx module clock enable signal..*/ +#define I2S_TX_CLK_ACTIVE (BIT(26)) +#define I2S_TX_CLK_ACTIVE_M (BIT(26)) +#define I2S_TX_CLK_ACTIVE_V 0x1 +#define I2S_TX_CLK_ACTIVE_S 26 /* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). - There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ -#define I2S_TX_CLKM_DIV_NUM 0x000000FF -#define I2S_TX_CLKM_DIV_NUM_M ((I2S_TX_CLKM_DIV_NUM_V) << (I2S_TX_CLKM_DIV_NUM_S)) -#define I2S_TX_CLKM_DIV_NUM_V 0xFF -#define I2S_TX_CLKM_DIV_NUM_S 0 +/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will + be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b + <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * +(n+1)-div] + y * (n+1)-div. .*/ +#define I2S_TX_CLKM_DIV_NUM 0x000000FF +#define I2S_TX_CLKM_DIV_NUM_M ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S)) +#define I2S_TX_CLKM_DIV_NUM_V 0xFF +#define I2S_TX_CLKM_DIV_NUM_S 0 -#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x0038) +#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x38) /* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > - a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ -#define I2S_RX_CLKM_DIV_YN1 (BIT(27)) -#define I2S_RX_CLKM_DIV_YN1_M (BIT(27)) -#define I2S_RX_CLKM_DIV_YN1_V 0x1 -#define I2S_RX_CLKM_DIV_YN1_S 27 +/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of +I2S_RX_CLKM_DIV_YN1 is 1. .*/ +#define I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_RX_CLKM_DIV_YN1_M (BIT(27)) +#define I2S_RX_CLKM_DIV_YN1_V 0x1 +#define I2S_RX_CLKM_DIV_YN1_S 27 /* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ -/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For - b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ -#define I2S_RX_CLKM_DIV_X 0x000001FF -#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V) << (I2S_RX_CLKM_DIV_X_S)) -#define I2S_RX_CLKM_DIV_X_V 0x1FF -#define I2S_RX_CLKM_DIV_X_S 18 +/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the valu +e of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. .*/ +#define I2S_RX_CLKM_DIV_X 0x000001FF +#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S)) +#define I2S_RX_CLKM_DIV_X_V 0x1FF +#define I2S_RX_CLKM_DIV_X_S 18 /* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ -/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b - > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ -#define I2S_RX_CLKM_DIV_Y 0x000001FF -#define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V) << (I2S_RX_CLKM_DIV_Y_S)) -#define I2S_RX_CLKM_DIV_Y_V 0x1FF -#define I2S_RX_CLKM_DIV_Y_S 9 +/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value o +f I2S_RX_CLKM_DIV_Y is (a%(a-b)). .*/ +#define I2S_RX_CLKM_DIV_Y 0x000001FF +#define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S)) +#define I2S_RX_CLKM_DIV_Y_V 0x1FF +#define I2S_RX_CLKM_DIV_Y_S 9 /* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 - the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ -#define I2S_RX_CLKM_DIV_Z 0x000001FF -#define I2S_RX_CLKM_DIV_Z_M ((I2S_RX_CLKM_DIV_Z_V) << (I2S_RX_CLKM_DIV_Z_S)) -#define I2S_RX_CLKM_DIV_Z_V 0x1FF -#define I2S_RX_CLKM_DIV_Z_S 0 +/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S +_RX_CLKM_DIV_Z is (a-b). .*/ +#define I2S_RX_CLKM_DIV_Z 0x000001FF +#define I2S_RX_CLKM_DIV_Z_M ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S)) +#define I2S_RX_CLKM_DIV_Z_V 0x1FF +#define I2S_RX_CLKM_DIV_Z_S 0 -#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x003C) +#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x3C) /* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > - a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ -#define I2S_TX_CLKM_DIV_YN1 (BIT(27)) -#define I2S_TX_CLKM_DIV_YN1_M (BIT(27)) -#define I2S_TX_CLKM_DIV_YN1_V 0x1 -#define I2S_TX_CLKM_DIV_YN1_S 27 +/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of +I2S_TX_CLKM_DIV_YN1 is 1. .*/ +#define I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_TX_CLKM_DIV_YN1_M (BIT(27)) +#define I2S_TX_CLKM_DIV_YN1_V 0x1 +#define I2S_TX_CLKM_DIV_YN1_S 27 /* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ -/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For - b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ -#define I2S_TX_CLKM_DIV_X 0x000001FF -#define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V) << (I2S_TX_CLKM_DIV_X_S)) -#define I2S_TX_CLKM_DIV_X_V 0x1FF -#define I2S_TX_CLKM_DIV_X_S 18 +/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the valu +e of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. .*/ +#define I2S_TX_CLKM_DIV_X 0x000001FF +#define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S)) +#define I2S_TX_CLKM_DIV_X_V 0x1FF +#define I2S_TX_CLKM_DIV_X_S 18 /* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ -/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b - > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ -#define I2S_TX_CLKM_DIV_Y 0x000001FF -#define I2S_TX_CLKM_DIV_Y_M ((I2S_TX_CLKM_DIV_Y_V) << (I2S_TX_CLKM_DIV_Y_S)) -#define I2S_TX_CLKM_DIV_Y_V 0x1FF -#define I2S_TX_CLKM_DIV_Y_S 9 +/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value o +f I2S_TX_CLKM_DIV_Y is (a%(a-b)). .*/ +#define I2S_TX_CLKM_DIV_Y 0x000001FF +#define I2S_TX_CLKM_DIV_Y_M ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S)) +#define I2S_TX_CLKM_DIV_Y_V 0x1FF +#define I2S_TX_CLKM_DIV_Y_S 9 /* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 - the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ -#define I2S_TX_CLKM_DIV_Z 0x000001FF -#define I2S_TX_CLKM_DIV_Z_M ((I2S_TX_CLKM_DIV_Z_V) << (I2S_TX_CLKM_DIV_Z_S)) -#define I2S_TX_CLKM_DIV_Z_V 0x1FF -#define I2S_TX_CLKM_DIV_Z_S 0 +/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S +_TX_CLKM_DIV_Z is (a-b). .*/ +#define I2S_TX_CLKM_DIV_Z 0x000001FF +#define I2S_TX_CLKM_DIV_Z_M ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S)) +#define I2S_TX_CLKM_DIV_Z_V 0x1FF +#define I2S_TX_CLKM_DIV_Z_S 0 -#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0050) +#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40) +/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: I2S TX PDM Converter enable.*/ +#define I2S_PCM2PDM_CONV_EN (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_M (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_V 0x1 +#define I2S_PCM2PDM_CONV_EN_S 25 +/* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: I2S TX PDM dac 2channel enable.*/ +#define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_M (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_V 0x1 +#define I2S_TX_PDM_DAC_MODE_EN_S 24 +/* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: I2S TX PDM dac mode enable.*/ +#define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_M (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_V 0x1 +#define I2S_TX_PDM_DAC_2OUT_EN_S 23 +/* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: I2S TX PDM sigmadelta dither value.*/ +#define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_M (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x1 +#define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 +/* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: I2S TX PDM sigmadelta dither2 value.*/ +#define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_M (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x1 +#define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 +/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */ +/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 +/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */ +/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S)) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_SINC_IN_SHIFT_S 17 +/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */ +/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S)) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_LP_IN_SHIFT_S 15 +/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ +/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003 +#define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S)) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x3 +#define I2S_TX_PDM_HP_IN_SHIFT_S 13 +/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */ +/*description: I2S TX PDM prescale for sigmadelta.*/ +#define I2S_TX_PDM_PRESCALE 0x000000FF +#define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S)) +#define I2S_TX_PDM_PRESCALE_V 0xFF +#define I2S_TX_PDM_PRESCALE_S 5 +/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */ +/*description: I2S TX PDM OSR2 value.*/ +#define I2S_TX_PDM_SINC_OSR2 0x0000000F +#define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S)) +#define I2S_TX_PDM_SINC_OSR2_V 0xF +#define I2S_TX_PDM_SINC_OSR2_S 1 +/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/ +#define I2S_TX_PDM_HP_BYPASS (BIT(0)) +#define I2S_TX_PDM_HP_BYPASS_M (BIT(0)) +#define I2S_TX_PDM_HP_BYPASS_V 0x1 +#define I2S_TX_PDM_HP_BYPASS_S 0 + +#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44) +/* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */ +/*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL +T12_0[2:0]).*/ +#define I2S_TX_IIR_HP_MULT12_0 0x00000007 +#define I2S_TX_IIR_HP_MULT12_0_M ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S)) +#define I2S_TX_IIR_HP_MULT12_0_V 0x7 +#define I2S_TX_IIR_HP_MULT12_0_S 23 +/* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */ +/*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL +T12_5[2:0]).*/ +#define I2S_TX_IIR_HP_MULT12_5 0x00000007 +#define I2S_TX_IIR_HP_MULT12_5_M ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S)) +#define I2S_TX_IIR_HP_MULT12_5_V 0x7 +#define I2S_TX_IIR_HP_MULT12_5_S 20 +/* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */ +/*description: I2S TX PDM Fs.*/ +#define I2S_TX_PDM_FS 0x000003FF +#define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S)) +#define I2S_TX_PDM_FS_V 0x3FF +#define I2S_TX_PDM_FS_S 10 +/* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */ +/*description: I2S TX PDM Fp.*/ +#define I2S_TX_PDM_FP 0x000003FF +#define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S)) +#define I2S_TX_PDM_FP_V 0x3FF +#define I2S_TX_PDM_FP_S 0 + +#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50) /* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: The total channel number of I2S TX TDM mode.*/ -#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000F -#define I2S_RX_TDM_TOT_CHAN_NUM_M ((I2S_RX_TDM_TOT_CHAN_NUM_V) << (I2S_RX_TDM_TOT_CHAN_NUM_S)) -#define I2S_RX_TDM_TOT_CHAN_NUM_V 0xF -#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 +/*description: The total channel number of I2S TX TDM mode..*/ +#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000F +#define I2S_RX_TDM_TOT_CHAN_NUM_M ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S)) +#define I2S_RX_TDM_TOT_CHAN_NUM_V 0xF +#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 /* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN15_EN (BIT(15)) -#define I2S_RX_TDM_CHAN15_EN_M (BIT(15)) -#define I2S_RX_TDM_CHAN15_EN_V 0x1 -#define I2S_RX_TDM_CHAN15_EN_S 15 +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input + 0 in this channel..*/ +#define I2S_RX_TDM_CHAN15_EN (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_M (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_V 0x1 +#define I2S_RX_TDM_CHAN15_EN_S 15 /* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN14_EN (BIT(14)) -#define I2S_RX_TDM_CHAN14_EN_M (BIT(14)) -#define I2S_RX_TDM_CHAN14_EN_V 0x1 -#define I2S_RX_TDM_CHAN14_EN_S 14 +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input + 0 in this channel..*/ +#define I2S_RX_TDM_CHAN14_EN (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_M (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_V 0x1 +#define I2S_RX_TDM_CHAN14_EN_S 14 /* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN13_EN (BIT(13)) -#define I2S_RX_TDM_CHAN13_EN_M (BIT(13)) -#define I2S_RX_TDM_CHAN13_EN_V 0x1 -#define I2S_RX_TDM_CHAN13_EN_S 13 +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input + 0 in this channel..*/ +#define I2S_RX_TDM_CHAN13_EN (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_M (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_V 0x1 +#define I2S_RX_TDM_CHAN13_EN_S 13 /* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN12_EN (BIT(12)) -#define I2S_RX_TDM_CHAN12_EN_M (BIT(12)) -#define I2S_RX_TDM_CHAN12_EN_V 0x1 -#define I2S_RX_TDM_CHAN12_EN_S 12 +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input + 0 in this channel..*/ +#define I2S_RX_TDM_CHAN12_EN (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_M (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_V 0x1 +#define I2S_RX_TDM_CHAN12_EN_S 12 /* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN11_EN (BIT(11)) -#define I2S_RX_TDM_CHAN11_EN_M (BIT(11)) -#define I2S_RX_TDM_CHAN11_EN_V 0x1 -#define I2S_RX_TDM_CHAN11_EN_S 11 +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input + 0 in this channel..*/ +#define I2S_RX_TDM_CHAN11_EN (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_M (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_V 0x1 +#define I2S_RX_TDM_CHAN11_EN_S 11 /* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN10_EN (BIT(10)) -#define I2S_RX_TDM_CHAN10_EN_M (BIT(10)) -#define I2S_RX_TDM_CHAN10_EN_V 0x1 -#define I2S_RX_TDM_CHAN10_EN_S 10 +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input + 0 in this channel..*/ +#define I2S_RX_TDM_CHAN10_EN (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_M (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_V 0x1 +#define I2S_RX_TDM_CHAN10_EN_S 10 /* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN9_EN (BIT(9)) -#define I2S_RX_TDM_CHAN9_EN_M (BIT(9)) -#define I2S_RX_TDM_CHAN9_EN_V 0x1 -#define I2S_RX_TDM_CHAN9_EN_S 9 +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input + 0 in this channel..*/ +#define I2S_RX_TDM_CHAN9_EN (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_M (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_V 0x1 +#define I2S_RX_TDM_CHAN9_EN_S 9 /* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN8_EN (BIT(8)) -#define I2S_RX_TDM_CHAN8_EN_M (BIT(8)) -#define I2S_RX_TDM_CHAN8_EN_V 0x1 -#define I2S_RX_TDM_CHAN8_EN_S 8 +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input + 0 in this channel..*/ +#define I2S_RX_TDM_CHAN8_EN (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_M (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_V 0x1 +#define I2S_RX_TDM_CHAN8_EN_S 8 /* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) -#define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7)) -#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +t input 0 in this channel..*/ +#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 /* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) -#define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6)) -#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +t input 0 in this channel..*/ +#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 /* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) -#define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5)) -#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +t input 0 in this channel..*/ +#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 /* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) -#define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4)) -#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +t input 0 in this channel..*/ +#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 /* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) -#define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3)) -#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +t input 0 in this channel..*/ +#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 /* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) -#define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2)) -#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +t input 0 in this channel..*/ +#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 /* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) -#define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1)) -#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +t input 0 in this channel..*/ +#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 /* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) -#define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0)) -#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, jus +t input 0 in this channel..*/ +#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 -#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0054) +#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54) /* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM - + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ -#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) -#define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20)) -#define I2S_TX_TDM_SKIP_MSK_EN_V 0x1 -#define I2S_TX_TDM_SKIP_MSK_EN_S 20 +/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, a +nd only the data of the enabled channels is sent, then this bit should be set. C +lear it when all the data stored in DMA TX buffer is for enabled channels..*/ +#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_V 0x1 +#define I2S_TX_TDM_SKIP_MSK_EN_S 20 /* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: The total channel number minus 1 of I2S TX TDM mode.*/ -#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000F -#define I2S_TX_TDM_TOT_CHAN_NUM_M ((I2S_TX_TDM_TOT_CHAN_NUM_V) << (I2S_TX_TDM_TOT_CHAN_NUM_S)) -#define I2S_TX_TDM_TOT_CHAN_NUM_V 0xF -#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 +/*description: The total channel number of I2S TX TDM mode..*/ +#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000F +#define I2S_TX_TDM_TOT_CHAN_NUM_M ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S)) +#define I2S_TX_TDM_TOT_CHAN_NUM_V 0xF +#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 /* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN15_EN (BIT(15)) -#define I2S_TX_TDM_CHAN15_EN_M (BIT(15)) -#define I2S_TX_TDM_CHAN15_EN_V 0x1 -#define I2S_TX_TDM_CHAN15_EN_S 15 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN15_EN (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_M (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_V 0x1 +#define I2S_TX_TDM_CHAN15_EN_S 15 /* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN14_EN (BIT(14)) -#define I2S_TX_TDM_CHAN14_EN_M (BIT(14)) -#define I2S_TX_TDM_CHAN14_EN_V 0x1 -#define I2S_TX_TDM_CHAN14_EN_S 14 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN14_EN (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_M (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_V 0x1 +#define I2S_TX_TDM_CHAN14_EN_S 14 /* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN13_EN (BIT(13)) -#define I2S_TX_TDM_CHAN13_EN_M (BIT(13)) -#define I2S_TX_TDM_CHAN13_EN_V 0x1 -#define I2S_TX_TDM_CHAN13_EN_S 13 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN13_EN (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_M (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_V 0x1 +#define I2S_TX_TDM_CHAN13_EN_S 13 /* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN12_EN (BIT(12)) -#define I2S_TX_TDM_CHAN12_EN_M (BIT(12)) -#define I2S_TX_TDM_CHAN12_EN_V 0x1 -#define I2S_TX_TDM_CHAN12_EN_S 12 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN12_EN (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_M (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_V 0x1 +#define I2S_TX_TDM_CHAN12_EN_S 12 /* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN11_EN (BIT(11)) -#define I2S_TX_TDM_CHAN11_EN_M (BIT(11)) -#define I2S_TX_TDM_CHAN11_EN_V 0x1 -#define I2S_TX_TDM_CHAN11_EN_S 11 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN11_EN (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_M (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_V 0x1 +#define I2S_TX_TDM_CHAN11_EN_S 11 /* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN10_EN (BIT(10)) -#define I2S_TX_TDM_CHAN10_EN_M (BIT(10)) -#define I2S_TX_TDM_CHAN10_EN_V 0x1 -#define I2S_TX_TDM_CHAN10_EN_S 10 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN10_EN (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_M (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_V 0x1 +#define I2S_TX_TDM_CHAN10_EN_S 10 /* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN9_EN (BIT(9)) -#define I2S_TX_TDM_CHAN9_EN_M (BIT(9)) -#define I2S_TX_TDM_CHAN9_EN_V 0x1 -#define I2S_TX_TDM_CHAN9_EN_S 9 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN9_EN (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_M (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_V 0x1 +#define I2S_TX_TDM_CHAN9_EN_S 9 /* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN8_EN (BIT(8)) -#define I2S_TX_TDM_CHAN8_EN_M (BIT(8)) -#define I2S_TX_TDM_CHAN8_EN_V 0x1 -#define I2S_TX_TDM_CHAN8_EN_S 8 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN8_EN (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_M (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_V 0x1 +#define I2S_TX_TDM_CHAN8_EN_S 8 /* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN7_EN (BIT(7)) -#define I2S_TX_TDM_CHAN7_EN_M (BIT(7)) -#define I2S_TX_TDM_CHAN7_EN_V 0x1 -#define I2S_TX_TDM_CHAN7_EN_S 7 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN7_EN (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_M (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_V 0x1 +#define I2S_TX_TDM_CHAN7_EN_S 7 /* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN6_EN (BIT(6)) -#define I2S_TX_TDM_CHAN6_EN_M (BIT(6)) -#define I2S_TX_TDM_CHAN6_EN_V 0x1 -#define I2S_TX_TDM_CHAN6_EN_S 6 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN6_EN (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_M (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_V 0x1 +#define I2S_TX_TDM_CHAN6_EN_S 6 /* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN5_EN (BIT(5)) -#define I2S_TX_TDM_CHAN5_EN_M (BIT(5)) -#define I2S_TX_TDM_CHAN5_EN_V 0x1 -#define I2S_TX_TDM_CHAN5_EN_S 5 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN5_EN (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_M (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_V 0x1 +#define I2S_TX_TDM_CHAN5_EN_S 5 /* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN4_EN (BIT(4)) -#define I2S_TX_TDM_CHAN4_EN_M (BIT(4)) -#define I2S_TX_TDM_CHAN4_EN_V 0x1 -#define I2S_TX_TDM_CHAN4_EN_S 4 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN4_EN (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_M (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_V 0x1 +#define I2S_TX_TDM_CHAN4_EN_S 4 /* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN3_EN (BIT(3)) -#define I2S_TX_TDM_CHAN3_EN_M (BIT(3)) -#define I2S_TX_TDM_CHAN3_EN_V 0x1 -#define I2S_TX_TDM_CHAN3_EN_S 3 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN3_EN (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_M (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_V 0x1 +#define I2S_TX_TDM_CHAN3_EN_S 3 /* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN2_EN (BIT(2)) -#define I2S_TX_TDM_CHAN2_EN_M (BIT(2)) -#define I2S_TX_TDM_CHAN2_EN_V 0x1 -#define I2S_TX_TDM_CHAN2_EN_S 2 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN2_EN (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_M (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_V 0x1 +#define I2S_TX_TDM_CHAN2_EN_S 2 /* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN1_EN (BIT(1)) -#define I2S_TX_TDM_CHAN1_EN_M (BIT(1)) -#define I2S_TX_TDM_CHAN1_EN_V 0x1 -#define I2S_TX_TDM_CHAN1_EN_S 1 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN1_EN (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_M (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_V 0x1 +#define I2S_TX_TDM_CHAN1_EN_S 1 /* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN0_EN (BIT(0)) -#define I2S_TX_TDM_CHAN0_EN_M (BIT(0)) -#define I2S_TX_TDM_CHAN0_EN_V 0x1 -#define I2S_TX_TDM_CHAN0_EN_S 0 +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just outp +ut 0 in this channel..*/ +#define I2S_TX_TDM_CHAN0_EN (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_M (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_V 0x1 +#define I2S_TX_TDM_CHAN0_EN_S 0 -#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x0058) +#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58) /* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_BCK_IN_DM 0x00000003 -#define I2S_RX_BCK_IN_DM_M ((I2S_RX_BCK_IN_DM_V) << (I2S_RX_BCK_IN_DM_S)) -#define I2S_RX_BCK_IN_DM_V 0x3 -#define I2S_RX_BCK_IN_DM_S 28 +/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: +delay by neg edge. 3: not used..*/ +#define I2S_RX_BCK_IN_DM 0x00000003 +#define I2S_RX_BCK_IN_DM_M ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S)) +#define I2S_RX_BCK_IN_DM_V 0x3 +#define I2S_RX_BCK_IN_DM_S 28 /* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_WS_IN_DM 0x00000003 -#define I2S_RX_WS_IN_DM_M ((I2S_RX_WS_IN_DM_V) << (I2S_RX_WS_IN_DM_S)) -#define I2S_RX_WS_IN_DM_V 0x3 -#define I2S_RX_WS_IN_DM_S 24 +/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: d +elay by neg edge. 3: not used..*/ +#define I2S_RX_WS_IN_DM 0x00000003 +#define I2S_RX_WS_IN_DM_M ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S)) +#define I2S_RX_WS_IN_DM_V 0x3 +#define I2S_RX_WS_IN_DM_S 24 /* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_BCK_OUT_DM 0x00000003 -#define I2S_RX_BCK_OUT_DM_M ((I2S_RX_BCK_OUT_DM_V) << (I2S_RX_BCK_OUT_DM_S)) -#define I2S_RX_BCK_OUT_DM_V 0x3 -#define I2S_RX_BCK_OUT_DM_S 20 +/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + delay by neg edge. 3: not used..*/ +#define I2S_RX_BCK_OUT_DM 0x00000003 +#define I2S_RX_BCK_OUT_DM_M ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S)) +#define I2S_RX_BCK_OUT_DM_V 0x3 +#define I2S_RX_BCK_OUT_DM_S 20 /* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_WS_OUT_DM 0x00000003 -#define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V) << (I2S_RX_WS_OUT_DM_S)) -#define I2S_RX_WS_OUT_DM_V 0x3 -#define I2S_RX_WS_OUT_DM_S 16 +/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: +delay by neg edge. 3: not used..*/ +#define I2S_RX_WS_OUT_DM 0x00000003 +#define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S)) +#define I2S_RX_WS_OUT_DM_V 0x3 +#define I2S_RX_WS_OUT_DM_S 16 /* I2S_RX_SD3_IN_DM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_SD3_IN_DM 0x00000003 -#define I2S_RX_SD3_IN_DM_M ((I2S_RX_SD3_IN_DM_V) << (I2S_RX_SD3_IN_DM_S)) -#define I2S_RX_SD3_IN_DM_V 0x3 -#define I2S_RX_SD3_IN_DM_S 12 +/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: +delay by neg edge. 3: not used..*/ +#define I2S_RX_SD3_IN_DM 0x00000003 +#define I2S_RX_SD3_IN_DM_M ((I2S_RX_SD3_IN_DM_V)<<(I2S_RX_SD3_IN_DM_S)) +#define I2S_RX_SD3_IN_DM_V 0x3 +#define I2S_RX_SD3_IN_DM_S 12 /* I2S_RX_SD2_IN_DM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_SD2_IN_DM 0x00000003 -#define I2S_RX_SD2_IN_DM_M ((I2S_RX_SD2_IN_DM_V) << (I2S_RX_SD2_IN_DM_S)) -#define I2S_RX_SD2_IN_DM_V 0x3 -#define I2S_RX_SD2_IN_DM_S 8 +/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: +delay by neg edge. 3: not used..*/ +#define I2S_RX_SD2_IN_DM 0x00000003 +#define I2S_RX_SD2_IN_DM_M ((I2S_RX_SD2_IN_DM_V)<<(I2S_RX_SD2_IN_DM_S)) +#define I2S_RX_SD2_IN_DM_V 0x3 +#define I2S_RX_SD2_IN_DM_S 8 /* I2S_RX_SD1_IN_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_SD1_IN_DM 0x00000003 -#define I2S_RX_SD1_IN_DM_M ((I2S_RX_SD1_IN_DM_V) << (I2S_RX_SD1_IN_DM_S)) -#define I2S_RX_SD1_IN_DM_V 0x3 -#define I2S_RX_SD1_IN_DM_S 4 +/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: +delay by neg edge. 3: not used..*/ +#define I2S_RX_SD1_IN_DM 0x00000003 +#define I2S_RX_SD1_IN_DM_M ((I2S_RX_SD1_IN_DM_V)<<(I2S_RX_SD1_IN_DM_S)) +#define I2S_RX_SD1_IN_DM_V 0x3 +#define I2S_RX_SD1_IN_DM_S 4 /* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_SD_IN_DM 0x00000003 -#define I2S_RX_SD_IN_DM_M ((I2S_RX_SD_IN_DM_V) << (I2S_RX_SD_IN_DM_S)) -#define I2S_RX_SD_IN_DM_V 0x3 -#define I2S_RX_SD_IN_DM_S 0 +/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: d +elay by neg edge. 3: not used..*/ +#define I2S_RX_SD_IN_DM 0x00000003 +#define I2S_RX_SD_IN_DM_M ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S)) +#define I2S_RX_SD_IN_DM_V 0x3 +#define I2S_RX_SD_IN_DM_S 0 -#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x005C) +#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5C) /* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_BCK_IN_DM 0x00000003 -#define I2S_TX_BCK_IN_DM_M ((I2S_TX_BCK_IN_DM_V) << (I2S_TX_BCK_IN_DM_S)) -#define I2S_TX_BCK_IN_DM_V 0x3 -#define I2S_TX_BCK_IN_DM_S 28 +/*description: The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: +delay by neg edge. 3: not used..*/ +#define I2S_TX_BCK_IN_DM 0x00000003 +#define I2S_TX_BCK_IN_DM_M ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S)) +#define I2S_TX_BCK_IN_DM_V 0x3 +#define I2S_TX_BCK_IN_DM_S 28 /* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_WS_IN_DM 0x00000003 -#define I2S_TX_WS_IN_DM_M ((I2S_TX_WS_IN_DM_V) << (I2S_TX_WS_IN_DM_S)) -#define I2S_TX_WS_IN_DM_V 0x3 -#define I2S_TX_WS_IN_DM_S 24 +/*description: The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: d +elay by neg edge. 3: not used..*/ +#define I2S_TX_WS_IN_DM 0x00000003 +#define I2S_TX_WS_IN_DM_M ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S)) +#define I2S_TX_WS_IN_DM_V 0x3 +#define I2S_TX_WS_IN_DM_S 24 /* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_BCK_OUT_DM 0x00000003 -#define I2S_TX_BCK_OUT_DM_M ((I2S_TX_BCK_OUT_DM_V) << (I2S_TX_BCK_OUT_DM_S)) -#define I2S_TX_BCK_OUT_DM_V 0x3 -#define I2S_TX_BCK_OUT_DM_S 20 +/*description: The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + delay by neg edge. 3: not used..*/ +#define I2S_TX_BCK_OUT_DM 0x00000003 +#define I2S_TX_BCK_OUT_DM_M ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S)) +#define I2S_TX_BCK_OUT_DM_V 0x3 +#define I2S_TX_BCK_OUT_DM_S 20 /* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_WS_OUT_DM 0x00000003 -#define I2S_TX_WS_OUT_DM_M ((I2S_TX_WS_OUT_DM_V) << (I2S_TX_WS_OUT_DM_S)) -#define I2S_TX_WS_OUT_DM_V 0x3 -#define I2S_TX_WS_OUT_DM_S 16 +/*description: The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: +delay by neg edge. 3: not used..*/ +#define I2S_TX_WS_OUT_DM 0x00000003 +#define I2S_TX_WS_OUT_DM_M ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S)) +#define I2S_TX_WS_OUT_DM_V 0x3 +#define I2S_TX_WS_OUT_DM_S 16 +/* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + delay by neg edge. 3: not used..*/ +#define I2S_TX_SD1_OUT_DM 0x00000003 +#define I2S_TX_SD1_OUT_DM_M ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S)) +#define I2S_TX_SD1_OUT_DM_V 0x3 +#define I2S_TX_SD1_OUT_DM_S 4 /* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_SD_OUT_DM 0x00000003 -#define I2S_TX_SD_OUT_DM_M ((I2S_TX_SD_OUT_DM_V) << (I2S_TX_SD_OUT_DM_S)) -#define I2S_TX_SD_OUT_DM_V 0x3 -#define I2S_TX_SD_OUT_DM_S 0 +/*description: The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: +delay by neg edge. 3: not used..*/ +#define I2S_TX_SD_OUT_DM 0x00000003 +#define I2S_TX_SD_OUT_DM_M ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S)) +#define I2S_TX_SD_OUT_DM_V 0x3 +#define I2S_TX_SD_OUT_DM_S 0 -#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) +#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60) /* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: The enable bit for FIFO timeout*/ -#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) -#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) -#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 -#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 +/*description: The enable bit for FIFO timeout.*/ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 /* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: The bits are used to scale tick counter threshold. The tick counter - is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ -#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 -#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V) << (I2S_LC_FIFO_TIMEOUT_SHIFT_S)) -#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 -#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/*description: The bits are used to scale tick counter threshold. The tick counter is reset whe +n counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 /* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ -/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt - will be triggered when fifo hung counter is equal to this value*/ -#define I2S_LC_FIFO_TIMEOUT 0x000000FF -#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V) << (I2S_LC_FIFO_TIMEOUT_S)) -#define I2S_LC_FIFO_TIMEOUT_V 0xFF -#define I2S_LC_FIFO_TIMEOUT_S 0 +/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + when fifo hung counter is equal to this value .*/ +#define I2S_LC_FIFO_TIMEOUT 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S)) +#define I2S_LC_FIFO_TIMEOUT_V 0xFF +#define I2S_LC_FIFO_TIMEOUT_S 0 -#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0064) +#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64) /* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */ -/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ -#define I2S_RX_EOF_NUM 0x00000FFF -#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V) << (I2S_RX_EOF_NUM_S)) -#define I2S_RX_EOF_NUM_V 0xFFF -#define I2S_RX_EOF_NUM_S 0 +/*description: The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0 +] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel..*/ +#define I2S_RX_EOF_NUM 0x00000FFF +#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S)) +#define I2S_RX_EOF_NUM_V 0xFFF +#define I2S_RX_EOF_NUM_S 0 -#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0068) +#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68) /* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: the right channel or left channel put out constant value stored - in this register according to tx_chan_mod and reg_tx_msb_right*/ -#define I2S_SINGLE_DATA 0xFFFFFFFF -#define I2S_SINGLE_DATA_M ((I2S_SINGLE_DATA_V) << (I2S_SINGLE_DATA_S)) -#define I2S_SINGLE_DATA_V 0xFFFFFFFF -#define I2S_SINGLE_DATA_S 0 +/*description: The configured constant channel data to be sent out..*/ +#define I2S_SINGLE_DATA 0xFFFFFFFF +#define I2S_SINGLE_DATA_M ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S)) +#define I2S_SINGLE_DATA_V 0xFFFFFFFF +#define I2S_SINGLE_DATA_S 0 -#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x006C) +#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6C) /* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/ -#define I2S_TX_IDLE (BIT(0)) -#define I2S_TX_IDLE_M (BIT(0)) -#define I2S_TX_IDLE_V 0x1 -#define I2S_TX_IDLE_S 0 +/*description: 1: i2s_tx is idle state. 0: i2s_tx is working..*/ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (BIT(0)) +#define I2S_TX_IDLE_V 0x1 +#define I2S_TX_IDLE_S 0 -#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x0080) -/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */ -/*description: Version control register*/ -#define I2S_DATE 0x0FFFFFFF -#define I2S_DATE_M ((I2S_DATE_V) << (I2S_DATE_S)) -#define I2S_DATE_V 0xFFFFFFF -#define I2S_DATE_S 0 +#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80) +/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2009070 ; */ +/*description: I2S version control register.*/ +#define I2S_DATE 0x0FFFFFFF +#define I2S_DATE_M ((I2S_DATE_V)<<(I2S_DATE_S)) +#define I2S_DATE_V 0xFFFFFFF +#define I2S_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_I2S_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/i2s_struct.h b/components/soc/esp32s3/include/soc/i2s_struct.h index dc3fe097a6..3f1e3f3f11 100644 --- a/components/soc/esp32s3/include/soc/i2s_struct.h +++ b/components/soc/esp32s3/include/soc/i2s_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,289 +11,316 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_I2S_STRUCT_H_ +#define _SOC_I2S_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif -#include - typedef volatile struct { uint32_t reserved_0; uint32_t reserved_4; uint32_t reserved_8; union { struct { - uint32_t rx_done: 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/ - uint32_t tx_done: 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/ - uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ - uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ - uint32_t reserved4: 28; /*Reserve*/ + uint32_t rx_done : 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done : 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung : 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung : 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4 : 28; /*Reserve*/ }; uint32_t val; } int_raw; union { struct { - uint32_t rx_done: 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/ - uint32_t tx_done: 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/ - uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ - uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ - uint32_t reserved4: 28; /*Reserve*/ + uint32_t rx_done : 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done : 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung : 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung : 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4 : 28; /*Reserve*/ }; uint32_t val; } int_st; union { struct { - uint32_t rx_done: 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/ - uint32_t tx_done: 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/ - uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/ - uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/ - uint32_t reserved4: 28; /*Reserve*/ + uint32_t rx_done : 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done : 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung : 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung : 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4 : 28; /*Reserve*/ }; uint32_t val; } int_ena; union { struct { - uint32_t rx_done: 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/ - uint32_t tx_done: 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/ - uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/ - uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/ - uint32_t reserved4: 28; /*Reserve*/ + uint32_t rx_done : 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/ + uint32_t tx_done : 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/ + uint32_t rx_hung : 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung : 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/ + uint32_t reserved4 : 28; /*Reserve*/ }; uint32_t val; } int_clr; uint32_t reserved_1c; union { struct { - uint32_t rx_reset: 1; /*Set this bit to reset receiver*/ - uint32_t rx_fifo_reset: 1; /*Set this bit to reset Rx AFIFO*/ - uint32_t rx_start: 1; /*Set this bit to start receiving data*/ - uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/ - uint32_t reserved4: 1; /*Reserved*/ - uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/ - uint32_t reserved6: 1; - uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/ - uint32_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/ - uint32_t rx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/ - uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ - uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/ - uint32_t rx_stop_mode: 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ - uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ - uint32_t rx_24_fill_en: 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ - uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ - uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/ - uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/ - uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/ - uint32_t rx_pdm2pcm_en: 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/ - uint32_t rx_sinc_dsr_16_en: 1; - uint32_t reserved23: 9; /*Reserve*/ + uint32_t rx_reset : 1; /*Set this bit to reset receiver*/ + uint32_t rx_fifo_reset : 1; /*Set this bit to reset Rx AFIFO*/ + uint32_t rx_start : 1; /*Set this bit to start receiving data*/ + uint32_t rx_slave_mod : 1; /*Set this bit to enable slave receiver mode*/ + uint32_t reserved4 : 1; /* Reserved*/ + uint32_t rx_mono : 1; /*Set this bit to enable receiver in mono mode*/ + uint32_t reserved6 : 1; /*Reserve*/ + uint32_t rx_big_endian : 1; /*I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/ + uint32_t rx_update : 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/ + uint32_t rx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/ + uint32_t rx_pcm_conf : 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/ + uint32_t rx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for received data.*/ + uint32_t rx_stop_mode : 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ + uint32_t rx_left_align : 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ + uint32_t rx_24_fill_en : 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ + uint32_t rx_ws_idle_pol : 1; /*0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. */ + uint32_t rx_bit_order : 1; /*I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.*/ + uint32_t rx_tdm_en : 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/ + uint32_t rx_pdm_en : 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/ + uint32_t rx_pdm2pcm_en : 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/ + uint32_t rx_pdm_sinc_dsr_16_en : 1; /*Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64.*/ + uint32_t reserved23 : 9; /*Reserve*/ }; uint32_t val; } rx_conf; union { struct { - uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/ - uint32_t tx_fifo_reset: 1; /*Set this bit to reset Tx AFIFO*/ - uint32_t tx_start: 1; /*Set this bit to start transmitting data*/ - uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/ - uint32_t reserved4: 1; /*Reserved*/ - uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/ - uint32_t tx_chan_equal: 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ - uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/ - uint32_t tx_update: 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/ - uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/ - uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ - uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/ - uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/ - uint32_t reserved14: 1; - uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ - uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ - uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ - uint32_t tx_bit_order: 1; /*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/ - uint32_t tx_tdm_en: 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/ - uint32_t tx_pdm_en: 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/ - uint32_t reserved21: 3; /*Reserved*/ - uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/ - uint32_t sig_loopback: 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/ - uint32_t reserved28: 4; /*Reserved*/ + uint32_t tx_reset : 1; /*Set this bit to reset transmitter*/ + uint32_t tx_fifo_reset : 1; /*Set this bit to reset Tx AFIFO*/ + uint32_t tx_start : 1; /*Set this bit to start transmitting data */ + uint32_t tx_slave_mod : 1; /*Set this bit to enable slave transmitter mode */ + uint32_t reserved4 : 1; /* Reserved*/ + uint32_t tx_mono : 1; /*Set this bit to enable transmitter in mono mode */ + uint32_t tx_chan_equal : 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ + uint32_t tx_big_endian : 1; /*I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/ + uint32_t tx_update : 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/ + uint32_t tx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/ + uint32_t tx_pcm_conf : 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/ + uint32_t tx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/ + uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/ + uint32_t reserved14 : 1; /* Reserved*/ + uint32_t tx_left_align : 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ + uint32_t tx_24_fill_en : 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ + uint32_t tx_ws_idle_pol : 1; /*0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. */ + uint32_t tx_bit_order : 1; /*I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.*/ + uint32_t tx_tdm_en : 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/ + uint32_t tx_pdm_en : 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/ + uint32_t reserved21 : 3; /*Reserved*/ + uint32_t tx_chan_mod : 3; /*I2S transmitter channel mode configuration bits.*/ + uint32_t sig_loopback : 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/ + uint32_t reserved28 : 4; /*Reserve*/ }; uint32_t val; } tx_conf; union { struct { - uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ - uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/ - uint32_t rx_bits_mod: 5; /*Set the bits to configure bit length of I2S receiver channel.*/ - uint32_t rx_half_sample_bits: 6; /*I2S Rx half sample bits -1.*/ - uint32_t rx_tdm_chan_bits: 5; /*The Rx bit number for each channel minus 1in TDM mode.*/ - uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/ - uint32_t reserved30: 2; /*Reserved*/ + uint32_t rx_tdm_ws_width : 7; /* The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck*/ + uint32_t rx_bck_div_num : 6; /*Bit clock configuration bits in receiver mode. */ + uint32_t rx_bits_mod : 5; /*Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/ + uint32_t rx_half_sample_bits : 6; /*I2S Rx half sample bits -1.*/ + uint32_t rx_tdm_chan_bits : 5; /*The Rx bit number for each channel minus 1in TDM mode.*/ + uint32_t rx_msb_shift : 1; /*Set this bit to enable receiver in Phillips standard mode*/ + uint32_t reserved30 : 2; /* Reserved*/ }; uint32_t val; } rx_conf1; union { struct { - uint32_t tx_tdm_ws_width: 7; /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ - uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/ - uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/ - uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/ - uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/ - uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/ - uint32_t reserved30: 2; /*Reserved*/ + uint32_t tx_tdm_ws_width : 7; /* The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck*/ + uint32_t tx_bck_div_num : 6; /*Bit clock configuration bits in transmitter mode. */ + uint32_t tx_bits_mod : 5; /*Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/ + uint32_t tx_half_sample_bits : 6; /* I2S Tx half sample bits -1.*/ + uint32_t tx_tdm_chan_bits : 5; /*The Tx bit number for each channel minus 1in TDM mode.*/ + uint32_t tx_msb_shift : 1; /*Set this bit to enable transmitter in Phillips standard mode*/ + uint32_t tx_bck_no_dly : 1; /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/ + uint32_t reserved31 : 1; /* Reserved*/ }; uint32_t val; } tx_conf1; union { struct { - uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/ - uint32_t reserved8: 18; /*Reserved*/ - uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/ - uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ - uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/ - uint32_t reserved30: 2; /*Reserved*/ + uint32_t rx_clkm_div_num : 8; /*Integral I2S clock divider value*/ + uint32_t reserved8 : 18; /* Reserved*/ + uint32_t rx_clk_active : 1; /*I2S Rx module clock enable signal.*/ + uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t mclk_sel : 1; /* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. */ + uint32_t reserved30 : 2; /* Reserved*/ }; uint32_t val; } rx_clkm_conf; union { struct { - uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ - uint32_t reserved8: 18; /*Reserved*/ - uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/ - uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ - uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ - uint32_t reserved30: 2; /*Reserved*/ + uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ + uint32_t reserved8: 18; /*Reserved*/ + uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/ + uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ + uint32_t reserved30: 2; /*Reserved*/ }; uint32_t val; } tx_clkm_conf; union { struct { - uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ - uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ - uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ - uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ - uint32_t reserved28: 4; /*Reserved*/ + uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ + uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ + uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ + uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ + uint32_t reserved28: 4; /*Reserved*/ }; uint32_t val; } rx_clkm_div_conf; union { struct { - uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ - uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ - uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ - uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ - uint32_t reserved28: 4; /*Reserved*/ + uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ + uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ + uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ + uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ + uint32_t reserved28: 4; /*Reserved*/ }; uint32_t val; } tx_clkm_div_conf; - uint32_t reserved_40; - uint32_t reserved_44; + union { + struct { + uint32_t txhp_bypass: 1; /*I2S TX PDM bypass hp filter or not. The option has been removed.*/ + uint32_t tx_sinc_osr2: 4; /*I2S TX PDM OSR2 value*/ + uint32_t tx_prescale: 8; /*I2S TX PDM prescale for sigmadelta*/ + uint32_t tx_hp_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/ + uint32_t tx_lp_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/ + uint32_t tx_sinc_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/ + uint32_t tx_sigmadelta_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/ + uint32_t tx_sigmadelta_dither2: 1; /*I2S TX PDM sigmadelta dither2 value*/ + uint32_t tx_sigmadelta_dither: 1; /*I2S TX PDM sigmadelta dither value*/ + uint32_t tx_dac_2out_en: 1; /*I2S TX PDM dac mode enable*/ + uint32_t tx_dac_mode_en: 1; /*I2S TX PDM dac 2channel enable*/ + uint32_t pcm2pdm_conv_en: 1; /*I2S TX PDM Converter enable*/ + uint32_t reserved26: 6; /*Reserved*/ + }; + uint32_t val; + } tx_pcm2pdm_conf; + union { + struct { + uint32_t tx_pdm_fp: 10; /*I2S TX PDM Fp*/ + uint32_t tx_pdm_fs: 10; /*I2S TX PDM Fs*/ + uint32_t tx_iir_hp_mult12_5: 3; /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/ + uint32_t tx_iir_hp_mult12_0: 3; /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/ + uint32_t reserved26: 6; /*Reserved*/ + }; + uint32_t val; + } tx_pcm2pdm_conf1; uint32_t reserved_48; uint32_t reserved_4c; union { struct { - uint32_t rx_tdm_chan0_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan1_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan2_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan3_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan4_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan5_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan6_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan7_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan8_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan9_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan10_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan11_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan12_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan13_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan14_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_chan15_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ - uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/ - uint32_t reserved20: 12; /*Reserved*/ + uint32_t rx_tdm_chan0_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan1_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan2_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan3_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan4_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan5_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan6_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan7_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan8_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan9_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan10_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan11_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan12_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan13_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan14_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan15_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/ + uint32_t reserved20: 12; /*Reserved*/ }; uint32_t val; } rx_tdm_ctrl; union { struct { - uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/ - uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ - uint32_t reserved21: 11; /*Reserved*/ + uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/ + uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ + uint32_t reserved21: 11; /*Reserved*/ }; uint32_t val; } tx_tdm_ctrl; union { struct { - uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ uint32_t reserved2: 2; - uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ uint32_t reserved6: 2; - uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ uint32_t reserved10: 2; - uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ uint32_t reserved14: 2; - uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved18: 2; - uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved22: 2; - uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved26: 2; - uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved30: 2; + uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved18: 2; /*Reserved*/ + uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved22: 2; /*Reserved*/ + uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved26: 2; /*Reserved*/ + uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved30: 2; /*Reserved*/ }; uint32_t val; } rx_timing; union { struct { - uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved2: 14; /*Reserved*/ - uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved18: 2; - uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved22: 2; - uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved26: 2; - uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved30: 2; + uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved2: 2; /*Reserved*/ + uint32_t tx_sd1_out_dm: 2; /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved6: 10; /*Reserved*/ + uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved18: 2; /*Reserved*/ + uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved22: 2; /*Reserved*/ + uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved26: 2; /*Reserved*/ + uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved30: 2; /*Reserved*/ }; uint32_t val; } tx_timing; union { struct { - uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/ - uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ - uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/ - uint32_t reserved12: 20; /*Reserved*/ + uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/ + uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ + uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/ + uint32_t reserved12: 20; /*Reserved*/ }; uint32_t val; } lc_hung_conf; union { struct { - uint32_t rx_eof_num: 12; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ - uint32_t reserved12: 20; /*Reserved*/ + uint32_t rx_eof_num:12; /*The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/ + uint32_t reserved12:20; /*Reserved*/ }; uint32_t val; - } rx_eof_num; - uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/ + } rxeof_num; + uint32_t conf_sigle_data; /*I2S signal data register*/ union { struct { - uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/ - uint32_t reserved1: 31; /*Reserved*/ + uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/ + uint32_t reserved1: 31; /*Reserved*/ }; uint32_t val; } state; @@ -303,16 +330,16 @@ typedef volatile struct { uint32_t reserved_7c; union { struct { - uint32_t date: 28; /*Version control register*/ - uint32_t reserved28: 4; /*Reserved*/ + uint32_t date: 28; /*I2S version control register*/ + uint32_t reserved28: 4; /*Reserved*/ }; uint32_t val; } date; } i2s_dev_t; - extern i2s_dev_t I2S0; extern i2s_dev_t I2S1; - #ifdef __cplusplus } #endif + +#endif /* _SOC_I2S_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/interrupt_core0_reg.h b/components/soc/esp32s3/include/soc/interrupt_core0_reg.h index ab335cf3c9..481de0d047 100644 --- a/components/soc/esp32s3/include/soc/interrupt_core0_reg.h +++ b/components/soc/esp32s3/include/soc/interrupt_core0_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,774 +11,861 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_INTERRUPT_CORE0_REG_H_ +#define _SOC_INTERRUPT_CORE0_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000) +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE + +#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000) /* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V) << (INTERRUPT_CORE0_MAC_INTR_MAP_S)) -#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0 +#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S)) +#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0 -#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004) +#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004) /* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V) << (INTERRUPT_CORE0_MAC_NMI_MAP_S)) -#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0 +#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S)) +#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0 -#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008) +#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008) /* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V) << (INTERRUPT_CORE0_PWR_INTR_MAP_S)) -#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0 +#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0 -#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C) +#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C) /* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V) << (INTERRUPT_CORE0_BB_INT_MAP_S)) -#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_BB_INT_MAP_S 0 +#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S)) +#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BB_INT_MAP_S 0 -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010) +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010) /* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V) << (INTERRUPT_CORE0_BT_MAC_INT_MAP_S)) -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0 +#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S)) +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0 -#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014) +#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014) /* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V) << (INTERRUPT_CORE0_BT_BB_INT_MAP_S)) -#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0 +#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S)) +#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0 -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018) /* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V) << (INTERRUPT_CORE0_BT_BB_NMI_MAP_S)) -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S)) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C) +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C) /* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V) << (INTERRUPT_CORE0_RWBT_IRQ_MAP_S)) -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0 +#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S)) +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0 -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020) +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020) /* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V) << (INTERRUPT_CORE0_RWBLE_IRQ_MAP_S)) -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0 +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S)) +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0 -#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x024) +#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x024) /* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V) << (INTERRUPT_CORE0_RWBT_NMI_MAP_S)) -#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0 +#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S)) +#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0 -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x028) +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x028) /* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V) << (INTERRUPT_CORE0_RWBLE_NMI_MAP_S)) -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0 +#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S)) +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0 -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x02C) +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x02C) /* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V) << (INTERRUPT_CORE0_I2C_MST_INT_MAP_S)) -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0 +#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S)) +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0 -#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x030) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x030) /* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V) << (INTERRUPT_CORE0_SLC0_INTR_MAP_S)) -#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S)) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 -#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x034) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x034) /* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V) << (INTERRUPT_CORE0_SLC1_INTR_MAP_S)) -#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S)) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x038) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x038) /* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V) << (INTERRUPT_CORE0_UHCI0_INTR_MAP_S)) -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 +#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S)) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 -#define INTERRUPT_CORE0_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x03C) +#define INTERRUPT_CORE0_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x03C) /* INTERRUPT_CORE0_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_UHCI1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UHCI1_INTR_MAP_M ((INTERRUPT_CORE0_UHCI1_INTR_MAP_V) << (INTERRUPT_CORE0_UHCI1_INTR_MAP_S)) -#define INTERRUPT_CORE0_UHCI1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_UHCI1_INTR_MAP_S 0 +#define INTERRUPT_CORE0_UHCI1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UHCI1_INTR_MAP_M ((INTERRUPT_CORE0_UHCI1_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI1_INTR_MAP_S)) +#define INTERRUPT_CORE0_UHCI1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UHCI1_INTR_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x040) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x040) /* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x044) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x044) /* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x048) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x048) /* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP 0x0000001F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V 0x1F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S 0 +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S 0 -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x04C) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x04C) /* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S 0 +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S 0 -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050) +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050) /* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_1_MAP_S)) -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0 +#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0 -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054) +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054) /* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_2_MAP_S)) -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0 +#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0 -#define INTERRUPT_CORE0_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x058) +#define INTERRUPT_CORE0_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x058) /* INTERRUPT_CORE0_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SPI_INTR_3_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_INTR_3_MAP_M ((INTERRUPT_CORE0_SPI_INTR_3_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_3_MAP_S)) -#define INTERRUPT_CORE0_SPI_INTR_3_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI_INTR_3_MAP_S 0 +#define INTERRUPT_CORE0_SPI_INTR_3_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_3_MAP_M ((INTERRUPT_CORE0_SPI_INTR_3_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_3_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_3_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_3_MAP_S 0 -#define INTERRUPT_CORE0_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x05C) +#define INTERRUPT_CORE0_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x05C) /* INTERRUPT_CORE0_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SPI_INTR_4_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_INTR_4_MAP_M ((INTERRUPT_CORE0_SPI_INTR_4_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_4_MAP_S)) -#define INTERRUPT_CORE0_SPI_INTR_4_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI_INTR_4_MAP_S 0 +#define INTERRUPT_CORE0_SPI_INTR_4_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_4_MAP_M ((INTERRUPT_CORE0_SPI_INTR_4_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_4_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_4_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_4_MAP_S 0 -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x060) +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x060) /* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V) << (INTERRUPT_CORE0_LCD_CAM_INT_MAP_S)) -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S 0 +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE0_LCD_CAM_INT_MAP_S)) +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S 0 -#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064) +#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064) /* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_I2S0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_I2S0_INT_MAP_M ((INTERRUPT_CORE0_I2S0_INT_MAP_V) << (INTERRUPT_CORE0_I2S0_INT_MAP_S)) -#define INTERRUPT_CORE0_I2S0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_I2S0_INT_MAP_S 0 +#define INTERRUPT_CORE0_I2S0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2S0_INT_MAP_M ((INTERRUPT_CORE0_I2S0_INT_MAP_V)<<(INTERRUPT_CORE0_I2S0_INT_MAP_S)) +#define INTERRUPT_CORE0_I2S0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2S0_INT_MAP_S 0 -#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068) +#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068) /* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V) << (INTERRUPT_CORE0_I2S1_INT_MAP_S)) -#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 +#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S)) +#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 -#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x06C) +#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x06C) /* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V) << (INTERRUPT_CORE0_UART_INTR_MAP_S)) -#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_UART_INTR_MAP_S 0 +#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART_INTR_MAP_S 0 -#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x070) +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x070) /* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V) << (INTERRUPT_CORE0_UART1_INTR_MAP_S)) -#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 -#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x074) +#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x074) /* INTERRUPT_CORE0_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_UART2_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UART2_INTR_MAP_M ((INTERRUPT_CORE0_UART2_INTR_MAP_V) << (INTERRUPT_CORE0_UART2_INTR_MAP_S)) -#define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_UART2_INTR_MAP_S 0 +#define INTERRUPT_CORE0_UART2_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART2_INTR_MAP_M ((INTERRUPT_CORE0_UART2_INTR_MAP_V)<<(INTERRUPT_CORE0_UART2_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART2_INTR_MAP_S 0 -#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x078) +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x078) /* INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP 0x0000001F -#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V) << (INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S)) -#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V 0x1F -#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S 0 +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V)<<(INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S)) +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S 0 -#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x07C) +#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x07C) /* INTERRUPT_CORE0_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_PWM0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_PWM0_INTR_MAP_M ((INTERRUPT_CORE0_PWM0_INTR_MAP_V) << (INTERRUPT_CORE0_PWM0_INTR_MAP_S)) -#define INTERRUPT_CORE0_PWM0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_PWM0_INTR_MAP_S 0 +#define INTERRUPT_CORE0_PWM0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWM0_INTR_MAP_M ((INTERRUPT_CORE0_PWM0_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM0_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWM0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWM0_INTR_MAP_S 0 -#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x080) +#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x080) /* INTERRUPT_CORE0_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_PWM1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_PWM1_INTR_MAP_M ((INTERRUPT_CORE0_PWM1_INTR_MAP_V) << (INTERRUPT_CORE0_PWM1_INTR_MAP_S)) -#define INTERRUPT_CORE0_PWM1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_PWM1_INTR_MAP_S 0 +#define INTERRUPT_CORE0_PWM1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWM1_INTR_MAP_M ((INTERRUPT_CORE0_PWM1_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM1_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWM1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWM1_INTR_MAP_S 0 -#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x084) +#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x084) /* INTERRUPT_CORE0_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_PWM2_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_PWM2_INTR_MAP_M ((INTERRUPT_CORE0_PWM2_INTR_MAP_V) << (INTERRUPT_CORE0_PWM2_INTR_MAP_S)) -#define INTERRUPT_CORE0_PWM2_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_PWM2_INTR_MAP_S 0 +#define INTERRUPT_CORE0_PWM2_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWM2_INTR_MAP_M ((INTERRUPT_CORE0_PWM2_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM2_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWM2_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWM2_INTR_MAP_S 0 -#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x088) +#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x088) /* INTERRUPT_CORE0_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_PWM3_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_PWM3_INTR_MAP_M ((INTERRUPT_CORE0_PWM3_INTR_MAP_V) << (INTERRUPT_CORE0_PWM3_INTR_MAP_S)) -#define INTERRUPT_CORE0_PWM3_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_PWM3_INTR_MAP_S 0 +#define INTERRUPT_CORE0_PWM3_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWM3_INTR_MAP_M ((INTERRUPT_CORE0_PWM3_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM3_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWM3_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWM3_INTR_MAP_S 0 -#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x08C) +#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x08C) /* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V) << (INTERRUPT_CORE0_LEDC_INT_MAP_S)) -#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 +#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S)) +#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 -#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x090) +#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x090) /* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V) << (INTERRUPT_CORE0_EFUSE_INT_MAP_S)) -#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0 +#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S)) +#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0 -#define INTERRUPT_CORE0_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094) -/* INTERRUPT_CORE0_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE0_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094) +/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TWAI_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TWAI_INT_MAP_M ((INTERRUPT_CORE0_TWAI_INT_MAP_V) << (INTERRUPT_CORE0_TWAI_INT_MAP_S)) -#define INTERRUPT_CORE0_TWAI_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TWAI_INT_MAP_S 0 +#define INTERRUPT_CORE0_CAN_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CAN_INT_MAP_M ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S)) +#define INTERRUPT_CORE0_CAN_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CAN_INT_MAP_S 0 -#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098) +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098) /* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V) << (INTERRUPT_CORE0_USB_INTR_MAP_S)) -#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 +#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S)) +#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x09C) +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x09C) /* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V) << (INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S)) -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S)) +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0) +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0) /* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V) << (INTERRUPT_CORE0_RMT_INTR_MAP_S)) -#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 +#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S)) +#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 -#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4) +#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4) /* INTERRUPT_CORE0_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_PCNT_INTR_MAP_M ((INTERRUPT_CORE0_PCNT_INTR_MAP_V) << (INTERRUPT_CORE0_PCNT_INTR_MAP_S)) -#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0 +#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PCNT_INTR_MAP_M ((INTERRUPT_CORE0_PCNT_INTR_MAP_V)<<(INTERRUPT_CORE0_PCNT_INTR_MAP_S)) +#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0 -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8) /* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V) << (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)) -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 -#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC) +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC) /* INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V) << (INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S)) -#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S 0 +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S)) +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S 0 -#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0) +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0) /* INTERRUPT_CORE0_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S)) -#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S 0 +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S)) +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S 0 -#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4) +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4) /* INTERRUPT_CORE0_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S)) -#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S 0 +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S)) +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S 0 -#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8) +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8) /* INTERRUPT_CORE0_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S)) -#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S 0 +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S)) +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S 0 -#define INTERRUPT_CORE0_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC) +#define INTERRUPT_CORE0_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC) /* INTERRUPT_CORE0_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_WDG_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_WDG_INT_MAP_M ((INTERRUPT_CORE0_WDG_INT_MAP_V) << (INTERRUPT_CORE0_WDG_INT_MAP_S)) -#define INTERRUPT_CORE0_WDG_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_WDG_INT_MAP_S 0 +#define INTERRUPT_CORE0_WDG_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_WDG_INT_MAP_M ((INTERRUPT_CORE0_WDG_INT_MAP_V)<<(INTERRUPT_CORE0_WDG_INT_MAP_S)) +#define INTERRUPT_CORE0_WDG_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_WDG_INT_MAP_S 0 -#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0) +#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0) /* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F -#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V) << (INTERRUPT_CORE0_TIMER_INT1_MAP_S)) -#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F -#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0 +#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F +#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S)) +#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F +#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0 -#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4) +#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4) /* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F -#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V) << (INTERRUPT_CORE0_TIMER_INT2_MAP_S)) -#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F -#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0 +#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F +#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S)) +#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F +#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0 -#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8) +#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8) /* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V) << (INTERRUPT_CORE0_TG_T0_INT_MAP_S)) -#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0 +#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0 -#define INTERRUPT_CORE0_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC) +#define INTERRUPT_CORE0_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC) /* INTERRUPT_CORE0_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TG_T1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG_T1_INT_MAP_M ((INTERRUPT_CORE0_TG_T1_INT_MAP_V) << (INTERRUPT_CORE0_TG_T1_INT_MAP_S)) -#define INTERRUPT_CORE0_TG_T1_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG_T1_INT_MAP_S 0 +#define INTERRUPT_CORE0_TG_T1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_T1_INT_MAP_M ((INTERRUPT_CORE0_TG_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T1_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_T1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_T1_INT_MAP_S 0 -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0) +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0) /* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V) << (INTERRUPT_CORE0_TG_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0 +#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4) +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4) /* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V) << (INTERRUPT_CORE0_TG1_T0_INT_MAP_S)) -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0 +#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0 -#define INTERRUPT_CORE0_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8) +#define INTERRUPT_CORE0_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8) /* INTERRUPT_CORE0_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TG1_T1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG1_T1_INT_MAP_M ((INTERRUPT_CORE0_TG1_T1_INT_MAP_V) << (INTERRUPT_CORE0_TG1_T1_INT_MAP_S)) -#define INTERRUPT_CORE0_TG1_T1_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG1_T1_INT_MAP_S 0 +#define INTERRUPT_CORE0_TG1_T1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_T1_INT_MAP_M ((INTERRUPT_CORE0_TG1_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T1_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_T1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_T1_INT_MAP_S 0 -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC) +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC) /* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V) << (INTERRUPT_CORE0_TG1_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0 +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0) +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0) /* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_IA_INT_MAP_S)) -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0 +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4) /* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8) /* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC) /* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0) +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0) /* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V) << (INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S)) -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0 +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S)) +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0 -#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4) +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4) /* INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S)) -#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S 0 +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S 0 -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8) +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8) /* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S)) -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0 +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0 -#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC) +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC) /* INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S)) -#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S 0 +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S 0 -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) /* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S)) -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0 +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0 -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) /* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V) << (INTERRUPT_CORE0_APB_ADC_INT_MAP_S)) -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0 +#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S)) +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) -/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/* INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0 +#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) -/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) +/* INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0 +#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) -/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/* INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0 +#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) -/* INTERRUPT_CORE0_DMA_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/* INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_DMA_CH3_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH3_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH3_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_S 0 +#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S 0 -#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) -/* INTERRUPT_CORE0_DMA_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/* INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_DMA_CH4_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH4_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH4_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_S 0 +#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S 0 -#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) +/* INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/* INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/* INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/* INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) +/* INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S 0 + +#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) /* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V) << (INTERRUPT_CORE0_RSA_INT_MAP_S)) -#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_RSA_INT_MAP_S 0 +#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S)) +#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_RSA_INT_MAP_S 0 -#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) /* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V) << (INTERRUPT_CORE0_AES_INT_MAP_S)) -#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_AES_INT_MAP_S 0 +#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S)) +#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_AES_INT_MAP_S 0 -#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) /* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V) << (INTERRUPT_CORE0_SHA_INT_MAP_S)) -#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SHA_INT_MAP_S 0 +#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S)) +#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SHA_INT_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) /* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) /* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) /* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) /* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) /* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V) << (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)) -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) /* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) /* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) /* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) /* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) /* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) /* INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) /* INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) /* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) /* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) /* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S)) -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 -#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C) /* INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S)) -#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S 0 +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) +/* INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M ((INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S)) +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S 0 + +#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) +/* INTERRUPT_CORE0_PERI_BACKUP_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_M ((INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V)<<(INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S)) +#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) +/* INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_M ((INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C) /* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V) << (INTERRUPT_CORE0_INTR_STATUS_0_S)) -#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_0_S 0 +#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S)) +#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_0_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) +#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) /* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V) << (INTERRUPT_CORE0_INTR_STATUS_1_S)) -#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_1_S 0 +#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S)) +#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_1_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) /* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V) << (INTERRUPT_CORE0_INTR_STATUS_2_S)) -#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_2_S 0 +#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S)) +#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_2_S 0 -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +#define INTERRUPT_CORE0_INTR_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) +/* INTERRUPT_CORE0_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTR_STATUS_3 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_3_M ((INTERRUPT_CORE0_INTR_STATUS_3_V)<<(INTERRUPT_CORE0_INTR_STATUS_3_S)) +#define INTERRUPT_CORE0_INTR_STATUS_3_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_3_S 0 + +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c) /* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ -#define INTERRUPT_CORE0_CLK_EN (BIT(0)) -#define INTERRUPT_CORE0_CLK_EN_M (BIT(0)) -#define INTERRUPT_CORE0_CLK_EN_V 0x1 -#define INTERRUPT_CORE0_CLK_EN_S 0 +#define INTERRUPT_CORE0_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_CLK_EN_M (BIT(0)) +#define INTERRUPT_CORE0_CLK_EN_V 0x1 +#define INTERRUPT_CORE0_CLK_EN_S 0 -#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC) -/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */ +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC) +/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */ /*description: */ -#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF -#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V) << (INTERRUPT_CORE0_INTERRUPT_DATE_S)) -#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF -#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 +#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF +#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S)) +#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF +#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/interrupt_core0_struct.h b/components/soc/esp32s3/include/soc/interrupt_core0_struct.h index 94d7661f00..574c9aab2f 100644 --- a/components/soc/esp32s3/include/soc/interrupt_core0_struct.h +++ b/components/soc/esp32s3/include/soc/interrupt_core0_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,14 +11,12 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_INTERRUPT_CORE0_STRUCT_H_ +#define _SOC_INTERRUPT_CORE0_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif -#include - typedef volatile struct { union { struct { @@ -484,39 +482,74 @@ typedef volatile struct { } core0_apb_adc_int_map; union { struct { - uint32_t core0_dma_ch0_int_map: 5; - uint32_t reserved5: 27; + uint32_t core0_dma_in_ch0_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core0_dma_ch0_int_map; + } core0_dma_in_ch0_int_map; union { struct { - uint32_t core0_dma_ch1_int_map: 5; - uint32_t reserved5: 27; + uint32_t core0_dma_in_ch1_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core0_dma_ch1_int_map; + } core0_dma_in_ch1_int_map; union { struct { - uint32_t core0_dma_ch2_int_map: 5; - uint32_t reserved5: 27; + uint32_t core0_dma_in_ch2_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core0_dma_ch2_int_map; + } core0_dma_in_ch2_int_map; union { struct { - uint32_t core0_dma_ch3_int_map: 5; - uint32_t reserved5: 27; + uint32_t core0_dma_in_ch3_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core0_dma_ch3_int_map; + } core0_dma_in_ch3_int_map; union { struct { - uint32_t core0_dma_ch4_int_map: 5; - uint32_t reserved5: 27; + uint32_t core0_dma_in_ch4_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core0_dma_ch4_int_map; + } core0_dma_in_ch4_int_map; + union { + struct { + uint32_t core0_dma_out_ch0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_out_ch0_int_map; + union { + struct { + uint32_t core0_dma_out_ch1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_out_ch1_int_map; + union { + struct { + uint32_t core0_dma_out_ch2_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_out_ch2_int_map; + union { + struct { + uint32_t core0_dma_out_ch3_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_out_ch3_int_map; + union { + struct { + uint32_t core0_dma_out_ch4_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_out_ch4_int_map; union { struct { uint32_t core0_rsa_int_map: 5; @@ -636,6 +669,13 @@ typedef volatile struct { }; uint32_t val; } core0_core_1_pif_pms_monitor_violate_size_intr_map; + union { + struct { + uint32_t core0_backup_pms_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_backup_pms_violate_intr_map; union { struct { uint32_t core0_cache_core0_acs_int_map: 5; @@ -650,9 +690,31 @@ typedef volatile struct { }; uint32_t val; } core0_cache_core1_acs_int_map; + union { + struct { + uint32_t core0_usb_device_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_usb_device_int_map; + union { + struct { + uint32_t core0_peri_backup_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_peri_backup_int_map; + union { + struct { + uint32_t core0_dma_extmem_reject_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_extmem_reject_int_map; uint32_t core0_intr_status_0; /**/ uint32_t core0_intr_status_1; /**/ uint32_t core0_intr_status_2; /**/ + uint32_t core0_intr_status_3; /**/ union { struct { uint32_t core0_clk_en: 1; @@ -660,16 +722,6 @@ typedef volatile struct { }; uint32_t val; } core0_clock_gate; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; uint32_t reserved_1a0; uint32_t reserved_1a4; uint32_t reserved_1a8; @@ -1079,15 +1131,15 @@ typedef volatile struct { uint32_t reserved_7f8; union { struct { - uint32_t core0_interrupt_date: 28; + uint32_t core0_interrupt_date:28; uint32_t reserved28: 4; }; uint32_t val; } core0_interrupt_date; } interrupt_core0_dev_t; - extern interrupt_core0_dev_t INTERRUPT_CORE0; - #ifdef __cplusplus } #endif + +#endif /* _SOC_INTERRUPT_CORE0_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/interrupt_core1_reg.h b/components/soc/esp32s3/include/soc/interrupt_core1_reg.h index 9c223d3f3f..5b4dc56e39 100644 --- a/components/soc/esp32s3/include/soc/interrupt_core1_reg.h +++ b/components/soc/esp32s3/include/soc/interrupt_core1_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,774 +11,861 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_INTERRUPT_CORE1_REG_H_ +#define _SOC_INTERRUPT_CORE1_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define INTERRUPT_CORE1_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x800) +#define DR_REG_INTERRUPT_CORE1_BASE DR_REG_INTERRUPT_BASE + +#define INTERRUPT_CORE1_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x800) /* INTERRUPT_CORE1_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_MAC_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_MAC_INTR_MAP_M ((INTERRUPT_CORE1_MAC_INTR_MAP_V) << (INTERRUPT_CORE1_MAC_INTR_MAP_S)) -#define INTERRUPT_CORE1_MAC_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_MAC_INTR_MAP_S 0 +#define INTERRUPT_CORE1_MAC_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_MAC_INTR_MAP_M ((INTERRUPT_CORE1_MAC_INTR_MAP_V)<<(INTERRUPT_CORE1_MAC_INTR_MAP_S)) +#define INTERRUPT_CORE1_MAC_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_MAC_INTR_MAP_S 0 -#define INTERRUPT_CORE1_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x804) +#define INTERRUPT_CORE1_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x804) /* INTERRUPT_CORE1_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_MAC_NMI_MAP 0x0000001F -#define INTERRUPT_CORE1_MAC_NMI_MAP_M ((INTERRUPT_CORE1_MAC_NMI_MAP_V) << (INTERRUPT_CORE1_MAC_NMI_MAP_S)) -#define INTERRUPT_CORE1_MAC_NMI_MAP_V 0x1F -#define INTERRUPT_CORE1_MAC_NMI_MAP_S 0 +#define INTERRUPT_CORE1_MAC_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_MAC_NMI_MAP_M ((INTERRUPT_CORE1_MAC_NMI_MAP_V)<<(INTERRUPT_CORE1_MAC_NMI_MAP_S)) +#define INTERRUPT_CORE1_MAC_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_MAC_NMI_MAP_S 0 -#define INTERRUPT_CORE1_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x808) +#define INTERRUPT_CORE1_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x808) /* INTERRUPT_CORE1_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_PWR_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_PWR_INTR_MAP_M ((INTERRUPT_CORE1_PWR_INTR_MAP_V) << (INTERRUPT_CORE1_PWR_INTR_MAP_S)) -#define INTERRUPT_CORE1_PWR_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_PWR_INTR_MAP_S 0 +#define INTERRUPT_CORE1_PWR_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWR_INTR_MAP_M ((INTERRUPT_CORE1_PWR_INTR_MAP_V)<<(INTERRUPT_CORE1_PWR_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWR_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWR_INTR_MAP_S 0 -#define INTERRUPT_CORE1_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80C) +#define INTERRUPT_CORE1_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80C) /* INTERRUPT_CORE1_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_BB_INT_MAP_M ((INTERRUPT_CORE1_BB_INT_MAP_V) << (INTERRUPT_CORE1_BB_INT_MAP_S)) -#define INTERRUPT_CORE1_BB_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_BB_INT_MAP_S 0 +#define INTERRUPT_CORE1_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_BB_INT_MAP_M ((INTERRUPT_CORE1_BB_INT_MAP_V)<<(INTERRUPT_CORE1_BB_INT_MAP_S)) +#define INTERRUPT_CORE1_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_BB_INT_MAP_S 0 -#define INTERRUPT_CORE1_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x810) +#define INTERRUPT_CORE1_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x810) /* INTERRUPT_CORE1_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_BT_MAC_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_BT_MAC_INT_MAP_M ((INTERRUPT_CORE1_BT_MAC_INT_MAP_V) << (INTERRUPT_CORE1_BT_MAC_INT_MAP_S)) -#define INTERRUPT_CORE1_BT_MAC_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_BT_MAC_INT_MAP_S 0 +#define INTERRUPT_CORE1_BT_MAC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_BT_MAC_INT_MAP_M ((INTERRUPT_CORE1_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE1_BT_MAC_INT_MAP_S)) +#define INTERRUPT_CORE1_BT_MAC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_BT_MAC_INT_MAP_S 0 -#define INTERRUPT_CORE1_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x814) +#define INTERRUPT_CORE1_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x814) /* INTERRUPT_CORE1_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_BT_BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_BT_BB_INT_MAP_M ((INTERRUPT_CORE1_BT_BB_INT_MAP_V) << (INTERRUPT_CORE1_BT_BB_INT_MAP_S)) -#define INTERRUPT_CORE1_BT_BB_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_BT_BB_INT_MAP_S 0 +#define INTERRUPT_CORE1_BT_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_BT_BB_INT_MAP_M ((INTERRUPT_CORE1_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE1_BT_BB_INT_MAP_S)) +#define INTERRUPT_CORE1_BT_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_BT_BB_INT_MAP_S 0 -#define INTERRUPT_CORE1_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x818) +#define INTERRUPT_CORE1_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x818) /* INTERRUPT_CORE1_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_BT_BB_NMI_MAP 0x0000001F -#define INTERRUPT_CORE1_BT_BB_NMI_MAP_M ((INTERRUPT_CORE1_BT_BB_NMI_MAP_V) << (INTERRUPT_CORE1_BT_BB_NMI_MAP_S)) -#define INTERRUPT_CORE1_BT_BB_NMI_MAP_V 0x1F -#define INTERRUPT_CORE1_BT_BB_NMI_MAP_S 0 +#define INTERRUPT_CORE1_BT_BB_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_BT_BB_NMI_MAP_M ((INTERRUPT_CORE1_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE1_BT_BB_NMI_MAP_S)) +#define INTERRUPT_CORE1_BT_BB_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_BT_BB_NMI_MAP_S 0 -#define INTERRUPT_CORE1_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x81C) +#define INTERRUPT_CORE1_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x81C) /* INTERRUPT_CORE1_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_RWBT_IRQ_MAP 0x0000001F -#define INTERRUPT_CORE1_RWBT_IRQ_MAP_M ((INTERRUPT_CORE1_RWBT_IRQ_MAP_V) << (INTERRUPT_CORE1_RWBT_IRQ_MAP_S)) -#define INTERRUPT_CORE1_RWBT_IRQ_MAP_V 0x1F -#define INTERRUPT_CORE1_RWBT_IRQ_MAP_S 0 +#define INTERRUPT_CORE1_RWBT_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE1_RWBT_IRQ_MAP_M ((INTERRUPT_CORE1_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE1_RWBT_IRQ_MAP_S)) +#define INTERRUPT_CORE1_RWBT_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE1_RWBT_IRQ_MAP_S 0 -#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x820) +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x820) /* INTERRUPT_CORE1_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_RWBLE_IRQ_MAP 0x0000001F -#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE1_RWBLE_IRQ_MAP_V) << (INTERRUPT_CORE1_RWBLE_IRQ_MAP_S)) -#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_V 0x1F -#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_S 0 +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE1_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE1_RWBLE_IRQ_MAP_S)) +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_S 0 -#define INTERRUPT_CORE1_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x824) +#define INTERRUPT_CORE1_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x824) /* INTERRUPT_CORE1_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_RWBT_NMI_MAP 0x0000001F -#define INTERRUPT_CORE1_RWBT_NMI_MAP_M ((INTERRUPT_CORE1_RWBT_NMI_MAP_V) << (INTERRUPT_CORE1_RWBT_NMI_MAP_S)) -#define INTERRUPT_CORE1_RWBT_NMI_MAP_V 0x1F -#define INTERRUPT_CORE1_RWBT_NMI_MAP_S 0 +#define INTERRUPT_CORE1_RWBT_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_RWBT_NMI_MAP_M ((INTERRUPT_CORE1_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE1_RWBT_NMI_MAP_S)) +#define INTERRUPT_CORE1_RWBT_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_RWBT_NMI_MAP_S 0 -#define INTERRUPT_CORE1_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x828) +#define INTERRUPT_CORE1_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x828) /* INTERRUPT_CORE1_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_RWBLE_NMI_MAP 0x0000001F -#define INTERRUPT_CORE1_RWBLE_NMI_MAP_M ((INTERRUPT_CORE1_RWBLE_NMI_MAP_V) << (INTERRUPT_CORE1_RWBLE_NMI_MAP_S)) -#define INTERRUPT_CORE1_RWBLE_NMI_MAP_V 0x1F -#define INTERRUPT_CORE1_RWBLE_NMI_MAP_S 0 +#define INTERRUPT_CORE1_RWBLE_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_RWBLE_NMI_MAP_M ((INTERRUPT_CORE1_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE1_RWBLE_NMI_MAP_S)) +#define INTERRUPT_CORE1_RWBLE_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_RWBLE_NMI_MAP_S 0 -#define INTERRUPT_CORE1_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x82C) +#define INTERRUPT_CORE1_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x82C) /* INTERRUPT_CORE1_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_I2C_MST_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_I2C_MST_INT_MAP_M ((INTERRUPT_CORE1_I2C_MST_INT_MAP_V) << (INTERRUPT_CORE1_I2C_MST_INT_MAP_S)) -#define INTERRUPT_CORE1_I2C_MST_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_I2C_MST_INT_MAP_S 0 +#define INTERRUPT_CORE1_I2C_MST_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_I2C_MST_INT_MAP_M ((INTERRUPT_CORE1_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE1_I2C_MST_INT_MAP_S)) +#define INTERRUPT_CORE1_I2C_MST_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_I2C_MST_INT_MAP_S 0 -#define INTERRUPT_CORE1_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x830) +#define INTERRUPT_CORE1_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x830) /* INTERRUPT_CORE1_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SLC0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_SLC0_INTR_MAP_M ((INTERRUPT_CORE1_SLC0_INTR_MAP_V) << (INTERRUPT_CORE1_SLC0_INTR_MAP_S)) -#define INTERRUPT_CORE1_SLC0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_SLC0_INTR_MAP_S 0 +#define INTERRUPT_CORE1_SLC0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_SLC0_INTR_MAP_M ((INTERRUPT_CORE1_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE1_SLC0_INTR_MAP_S)) +#define INTERRUPT_CORE1_SLC0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_SLC0_INTR_MAP_S 0 -#define INTERRUPT_CORE1_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x834) +#define INTERRUPT_CORE1_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x834) /* INTERRUPT_CORE1_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SLC1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_SLC1_INTR_MAP_M ((INTERRUPT_CORE1_SLC1_INTR_MAP_V) << (INTERRUPT_CORE1_SLC1_INTR_MAP_S)) -#define INTERRUPT_CORE1_SLC1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_SLC1_INTR_MAP_S 0 +#define INTERRUPT_CORE1_SLC1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_SLC1_INTR_MAP_M ((INTERRUPT_CORE1_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE1_SLC1_INTR_MAP_S)) +#define INTERRUPT_CORE1_SLC1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_SLC1_INTR_MAP_S 0 -#define INTERRUPT_CORE1_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x838) +#define INTERRUPT_CORE1_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x838) /* INTERRUPT_CORE1_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_UHCI0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_UHCI0_INTR_MAP_M ((INTERRUPT_CORE1_UHCI0_INTR_MAP_V) << (INTERRUPT_CORE1_UHCI0_INTR_MAP_S)) -#define INTERRUPT_CORE1_UHCI0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_UHCI0_INTR_MAP_S 0 +#define INTERRUPT_CORE1_UHCI0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UHCI0_INTR_MAP_M ((INTERRUPT_CORE1_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE1_UHCI0_INTR_MAP_S)) +#define INTERRUPT_CORE1_UHCI0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UHCI0_INTR_MAP_S 0 -#define INTERRUPT_CORE1_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x83C) +#define INTERRUPT_CORE1_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x83C) /* INTERRUPT_CORE1_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_UHCI1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_UHCI1_INTR_MAP_M ((INTERRUPT_CORE1_UHCI1_INTR_MAP_V) << (INTERRUPT_CORE1_UHCI1_INTR_MAP_S)) -#define INTERRUPT_CORE1_UHCI1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_UHCI1_INTR_MAP_S 0 +#define INTERRUPT_CORE1_UHCI1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UHCI1_INTR_MAP_M ((INTERRUPT_CORE1_UHCI1_INTR_MAP_V)<<(INTERRUPT_CORE1_UHCI1_INTR_MAP_S)) +#define INTERRUPT_CORE1_UHCI1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UHCI1_INTR_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x840) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x840) /* INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP 0x0000001F -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S)) -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V 0x1F -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S 0 +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S)) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x844) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x844) /* INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S)) -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F -#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x848) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x848) /* INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP 0x0000001F -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S)) -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V 0x1F -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S 0 +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V)<<(INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S)) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V 0x1F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S 0 -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84C) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84C) /* INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S)) -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F -#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S 0 +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S)) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S 0 -#define INTERRUPT_CORE1_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x850) +#define INTERRUPT_CORE1_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x850) /* INTERRUPT_CORE1_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SPI_INTR_1_MAP 0x0000001F -#define INTERRUPT_CORE1_SPI_INTR_1_MAP_M ((INTERRUPT_CORE1_SPI_INTR_1_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_1_MAP_S)) -#define INTERRUPT_CORE1_SPI_INTR_1_MAP_V 0x1F -#define INTERRUPT_CORE1_SPI_INTR_1_MAP_S 0 +#define INTERRUPT_CORE1_SPI_INTR_1_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_INTR_1_MAP_M ((INTERRUPT_CORE1_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE1_SPI_INTR_1_MAP_S)) +#define INTERRUPT_CORE1_SPI_INTR_1_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_INTR_1_MAP_S 0 -#define INTERRUPT_CORE1_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x854) +#define INTERRUPT_CORE1_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x854) /* INTERRUPT_CORE1_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SPI_INTR_2_MAP 0x0000001F -#define INTERRUPT_CORE1_SPI_INTR_2_MAP_M ((INTERRUPT_CORE1_SPI_INTR_2_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_2_MAP_S)) -#define INTERRUPT_CORE1_SPI_INTR_2_MAP_V 0x1F -#define INTERRUPT_CORE1_SPI_INTR_2_MAP_S 0 +#define INTERRUPT_CORE1_SPI_INTR_2_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_INTR_2_MAP_M ((INTERRUPT_CORE1_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE1_SPI_INTR_2_MAP_S)) +#define INTERRUPT_CORE1_SPI_INTR_2_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_INTR_2_MAP_S 0 -#define INTERRUPT_CORE1_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x858) +#define INTERRUPT_CORE1_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x858) /* INTERRUPT_CORE1_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SPI_INTR_3_MAP 0x0000001F -#define INTERRUPT_CORE1_SPI_INTR_3_MAP_M ((INTERRUPT_CORE1_SPI_INTR_3_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_3_MAP_S)) -#define INTERRUPT_CORE1_SPI_INTR_3_MAP_V 0x1F -#define INTERRUPT_CORE1_SPI_INTR_3_MAP_S 0 +#define INTERRUPT_CORE1_SPI_INTR_3_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_INTR_3_MAP_M ((INTERRUPT_CORE1_SPI_INTR_3_MAP_V)<<(INTERRUPT_CORE1_SPI_INTR_3_MAP_S)) +#define INTERRUPT_CORE1_SPI_INTR_3_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_INTR_3_MAP_S 0 -#define INTERRUPT_CORE1_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x85C) +#define INTERRUPT_CORE1_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x85C) /* INTERRUPT_CORE1_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SPI_INTR_4_MAP 0x0000001F -#define INTERRUPT_CORE1_SPI_INTR_4_MAP_M ((INTERRUPT_CORE1_SPI_INTR_4_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_4_MAP_S)) -#define INTERRUPT_CORE1_SPI_INTR_4_MAP_V 0x1F -#define INTERRUPT_CORE1_SPI_INTR_4_MAP_S 0 +#define INTERRUPT_CORE1_SPI_INTR_4_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_INTR_4_MAP_M ((INTERRUPT_CORE1_SPI_INTR_4_MAP_V)<<(INTERRUPT_CORE1_SPI_INTR_4_MAP_S)) +#define INTERRUPT_CORE1_SPI_INTR_4_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_INTR_4_MAP_S 0 -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x860) +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x860) /* INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE1_LCD_CAM_INT_MAP_V) << (INTERRUPT_CORE1_LCD_CAM_INT_MAP_S)) -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S 0 +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE1_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE1_LCD_CAM_INT_MAP_S)) +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S 0 -#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x864) +#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x864) /* INTERRUPT_CORE1_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_I2S0_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_I2S0_INT_MAP_M ((INTERRUPT_CORE1_I2S0_INT_MAP_V) << (INTERRUPT_CORE1_I2S0_INT_MAP_S)) -#define INTERRUPT_CORE1_I2S0_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_I2S0_INT_MAP_S 0 +#define INTERRUPT_CORE1_I2S0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_I2S0_INT_MAP_M ((INTERRUPT_CORE1_I2S0_INT_MAP_V)<<(INTERRUPT_CORE1_I2S0_INT_MAP_S)) +#define INTERRUPT_CORE1_I2S0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_I2S0_INT_MAP_S 0 -#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x868) +#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x868) /* INTERRUPT_CORE1_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_I2S1_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_I2S1_INT_MAP_M ((INTERRUPT_CORE1_I2S1_INT_MAP_V) << (INTERRUPT_CORE1_I2S1_INT_MAP_S)) -#define INTERRUPT_CORE1_I2S1_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_I2S1_INT_MAP_S 0 +#define INTERRUPT_CORE1_I2S1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_I2S1_INT_MAP_M ((INTERRUPT_CORE1_I2S1_INT_MAP_V)<<(INTERRUPT_CORE1_I2S1_INT_MAP_S)) +#define INTERRUPT_CORE1_I2S1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_I2S1_INT_MAP_S 0 -#define INTERRUPT_CORE1_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x86C) +#define INTERRUPT_CORE1_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x86C) /* INTERRUPT_CORE1_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_UART_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_UART_INTR_MAP_M ((INTERRUPT_CORE1_UART_INTR_MAP_V) << (INTERRUPT_CORE1_UART_INTR_MAP_S)) -#define INTERRUPT_CORE1_UART_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_UART_INTR_MAP_S 0 +#define INTERRUPT_CORE1_UART_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UART_INTR_MAP_M ((INTERRUPT_CORE1_UART_INTR_MAP_V)<<(INTERRUPT_CORE1_UART_INTR_MAP_S)) +#define INTERRUPT_CORE1_UART_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UART_INTR_MAP_S 0 -#define INTERRUPT_CORE1_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x870) +#define INTERRUPT_CORE1_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x870) /* INTERRUPT_CORE1_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_UART1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_UART1_INTR_MAP_M ((INTERRUPT_CORE1_UART1_INTR_MAP_V) << (INTERRUPT_CORE1_UART1_INTR_MAP_S)) -#define INTERRUPT_CORE1_UART1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_UART1_INTR_MAP_S 0 +#define INTERRUPT_CORE1_UART1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UART1_INTR_MAP_M ((INTERRUPT_CORE1_UART1_INTR_MAP_V)<<(INTERRUPT_CORE1_UART1_INTR_MAP_S)) +#define INTERRUPT_CORE1_UART1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UART1_INTR_MAP_S 0 -#define INTERRUPT_CORE1_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x874) +#define INTERRUPT_CORE1_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x874) /* INTERRUPT_CORE1_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_UART2_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_UART2_INTR_MAP_M ((INTERRUPT_CORE1_UART2_INTR_MAP_V) << (INTERRUPT_CORE1_UART2_INTR_MAP_S)) -#define INTERRUPT_CORE1_UART2_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_UART2_INTR_MAP_S 0 +#define INTERRUPT_CORE1_UART2_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UART2_INTR_MAP_M ((INTERRUPT_CORE1_UART2_INTR_MAP_V)<<(INTERRUPT_CORE1_UART2_INTR_MAP_S)) +#define INTERRUPT_CORE1_UART2_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UART2_INTR_MAP_S 0 -#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x878) +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x878) /* INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP 0x0000001F -#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V) << (INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S)) -#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V 0x1F -#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S 0 +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V)<<(INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S)) +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S 0 -#define INTERRUPT_CORE1_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x87C) +#define INTERRUPT_CORE1_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x87C) /* INTERRUPT_CORE1_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_PWM0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_PWM0_INTR_MAP_M ((INTERRUPT_CORE1_PWM0_INTR_MAP_V) << (INTERRUPT_CORE1_PWM0_INTR_MAP_S)) -#define INTERRUPT_CORE1_PWM0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_PWM0_INTR_MAP_S 0 +#define INTERRUPT_CORE1_PWM0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWM0_INTR_MAP_M ((INTERRUPT_CORE1_PWM0_INTR_MAP_V)<<(INTERRUPT_CORE1_PWM0_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWM0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWM0_INTR_MAP_S 0 -#define INTERRUPT_CORE1_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x880) +#define INTERRUPT_CORE1_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x880) /* INTERRUPT_CORE1_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_PWM1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_PWM1_INTR_MAP_M ((INTERRUPT_CORE1_PWM1_INTR_MAP_V) << (INTERRUPT_CORE1_PWM1_INTR_MAP_S)) -#define INTERRUPT_CORE1_PWM1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_PWM1_INTR_MAP_S 0 +#define INTERRUPT_CORE1_PWM1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWM1_INTR_MAP_M ((INTERRUPT_CORE1_PWM1_INTR_MAP_V)<<(INTERRUPT_CORE1_PWM1_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWM1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWM1_INTR_MAP_S 0 -#define INTERRUPT_CORE1_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x884) +#define INTERRUPT_CORE1_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x884) /* INTERRUPT_CORE1_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_PWM2_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_PWM2_INTR_MAP_M ((INTERRUPT_CORE1_PWM2_INTR_MAP_V) << (INTERRUPT_CORE1_PWM2_INTR_MAP_S)) -#define INTERRUPT_CORE1_PWM2_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_PWM2_INTR_MAP_S 0 +#define INTERRUPT_CORE1_PWM2_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWM2_INTR_MAP_M ((INTERRUPT_CORE1_PWM2_INTR_MAP_V)<<(INTERRUPT_CORE1_PWM2_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWM2_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWM2_INTR_MAP_S 0 -#define INTERRUPT_CORE1_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x888) +#define INTERRUPT_CORE1_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x888) /* INTERRUPT_CORE1_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_PWM3_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_PWM3_INTR_MAP_M ((INTERRUPT_CORE1_PWM3_INTR_MAP_V) << (INTERRUPT_CORE1_PWM3_INTR_MAP_S)) -#define INTERRUPT_CORE1_PWM3_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_PWM3_INTR_MAP_S 0 +#define INTERRUPT_CORE1_PWM3_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWM3_INTR_MAP_M ((INTERRUPT_CORE1_PWM3_INTR_MAP_V)<<(INTERRUPT_CORE1_PWM3_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWM3_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWM3_INTR_MAP_S 0 -#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88C) +#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88C) /* INTERRUPT_CORE1_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_LEDC_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_LEDC_INT_MAP_M ((INTERRUPT_CORE1_LEDC_INT_MAP_V) << (INTERRUPT_CORE1_LEDC_INT_MAP_S)) -#define INTERRUPT_CORE1_LEDC_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_LEDC_INT_MAP_S 0 +#define INTERRUPT_CORE1_LEDC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_LEDC_INT_MAP_M ((INTERRUPT_CORE1_LEDC_INT_MAP_V)<<(INTERRUPT_CORE1_LEDC_INT_MAP_S)) +#define INTERRUPT_CORE1_LEDC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_LEDC_INT_MAP_S 0 -#define INTERRUPT_CORE1_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x890) +#define INTERRUPT_CORE1_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x890) /* INTERRUPT_CORE1_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_EFUSE_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_EFUSE_INT_MAP_M ((INTERRUPT_CORE1_EFUSE_INT_MAP_V) << (INTERRUPT_CORE1_EFUSE_INT_MAP_S)) -#define INTERRUPT_CORE1_EFUSE_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_EFUSE_INT_MAP_S 0 +#define INTERRUPT_CORE1_EFUSE_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_EFUSE_INT_MAP_M ((INTERRUPT_CORE1_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE1_EFUSE_INT_MAP_S)) +#define INTERRUPT_CORE1_EFUSE_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_EFUSE_INT_MAP_S 0 -#define INTERRUPT_CORE1_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x894) -/* INTERRUPT_CORE1_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE1_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x894) +/* INTERRUPT_CORE1_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TWAI_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_TWAI_INT_MAP_M ((INTERRUPT_CORE1_TWAI_INT_MAP_V) << (INTERRUPT_CORE1_TWAI_INT_MAP_S)) -#define INTERRUPT_CORE1_TWAI_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_TWAI_INT_MAP_S 0 +#define INTERRUPT_CORE1_CAN_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_CAN_INT_MAP_M ((INTERRUPT_CORE1_CAN_INT_MAP_V)<<(INTERRUPT_CORE1_CAN_INT_MAP_S)) +#define INTERRUPT_CORE1_CAN_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_CAN_INT_MAP_S 0 -#define INTERRUPT_CORE1_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x898) +#define INTERRUPT_CORE1_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x898) /* INTERRUPT_CORE1_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_USB_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_USB_INTR_MAP_M ((INTERRUPT_CORE1_USB_INTR_MAP_V) << (INTERRUPT_CORE1_USB_INTR_MAP_S)) -#define INTERRUPT_CORE1_USB_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_USB_INTR_MAP_S 0 +#define INTERRUPT_CORE1_USB_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_USB_INTR_MAP_M ((INTERRUPT_CORE1_USB_INTR_MAP_V)<<(INTERRUPT_CORE1_USB_INTR_MAP_S)) +#define INTERRUPT_CORE1_USB_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_USB_INTR_MAP_S 0 -#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x89C) +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x89C) /* INTERRUPT_CORE1_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V) << (INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S)) -#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S)) +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A0) +#define INTERRUPT_CORE1_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A0) /* INTERRUPT_CORE1_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_RMT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_RMT_INTR_MAP_M ((INTERRUPT_CORE1_RMT_INTR_MAP_V) << (INTERRUPT_CORE1_RMT_INTR_MAP_S)) -#define INTERRUPT_CORE1_RMT_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_RMT_INTR_MAP_S 0 +#define INTERRUPT_CORE1_RMT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_RMT_INTR_MAP_M ((INTERRUPT_CORE1_RMT_INTR_MAP_V)<<(INTERRUPT_CORE1_RMT_INTR_MAP_S)) +#define INTERRUPT_CORE1_RMT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_RMT_INTR_MAP_S 0 -#define INTERRUPT_CORE1_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A4) +#define INTERRUPT_CORE1_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A4) /* INTERRUPT_CORE1_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_PCNT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_PCNT_INTR_MAP_M ((INTERRUPT_CORE1_PCNT_INTR_MAP_V) << (INTERRUPT_CORE1_PCNT_INTR_MAP_S)) -#define INTERRUPT_CORE1_PCNT_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_PCNT_INTR_MAP_S 0 +#define INTERRUPT_CORE1_PCNT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PCNT_INTR_MAP_M ((INTERRUPT_CORE1_PCNT_INTR_MAP_V)<<(INTERRUPT_CORE1_PCNT_INTR_MAP_S)) +#define INTERRUPT_CORE1_PCNT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PCNT_INTR_MAP_S 0 -#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A8) +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A8) /* INTERRUPT_CORE1_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V) << (INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S)) -#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S 0 +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S)) +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S 0 -#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8AC) +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8AC) /* INTERRUPT_CORE1_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V) << (INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S)) -#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S 0 +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V)<<(INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S)) +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S 0 -#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B0) +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B0) /* INTERRUPT_CORE1_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S)) -#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S 0 +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V)<<(INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S)) +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S 0 -#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B4) +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B4) /* INTERRUPT_CORE1_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S)) -#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S 0 +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V)<<(INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S)) +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S 0 -#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B8) +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B8) /* INTERRUPT_CORE1_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S)) -#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S 0 +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V)<<(INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S)) +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S 0 -#define INTERRUPT_CORE1_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8BC) +#define INTERRUPT_CORE1_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8BC) /* INTERRUPT_CORE1_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_WDG_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_WDG_INT_MAP_M ((INTERRUPT_CORE1_WDG_INT_MAP_V) << (INTERRUPT_CORE1_WDG_INT_MAP_S)) -#define INTERRUPT_CORE1_WDG_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_WDG_INT_MAP_S 0 +#define INTERRUPT_CORE1_WDG_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_WDG_INT_MAP_M ((INTERRUPT_CORE1_WDG_INT_MAP_V)<<(INTERRUPT_CORE1_WDG_INT_MAP_S)) +#define INTERRUPT_CORE1_WDG_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_WDG_INT_MAP_S 0 -#define INTERRUPT_CORE1_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C0) +#define INTERRUPT_CORE1_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C0) /* INTERRUPT_CORE1_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TIMER_INT1_MAP 0x0000001F -#define INTERRUPT_CORE1_TIMER_INT1_MAP_M ((INTERRUPT_CORE1_TIMER_INT1_MAP_V) << (INTERRUPT_CORE1_TIMER_INT1_MAP_S)) -#define INTERRUPT_CORE1_TIMER_INT1_MAP_V 0x1F -#define INTERRUPT_CORE1_TIMER_INT1_MAP_S 0 +#define INTERRUPT_CORE1_TIMER_INT1_MAP 0x0000001F +#define INTERRUPT_CORE1_TIMER_INT1_MAP_M ((INTERRUPT_CORE1_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE1_TIMER_INT1_MAP_S)) +#define INTERRUPT_CORE1_TIMER_INT1_MAP_V 0x1F +#define INTERRUPT_CORE1_TIMER_INT1_MAP_S 0 -#define INTERRUPT_CORE1_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C4) +#define INTERRUPT_CORE1_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C4) /* INTERRUPT_CORE1_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TIMER_INT2_MAP 0x0000001F -#define INTERRUPT_CORE1_TIMER_INT2_MAP_M ((INTERRUPT_CORE1_TIMER_INT2_MAP_V) << (INTERRUPT_CORE1_TIMER_INT2_MAP_S)) -#define INTERRUPT_CORE1_TIMER_INT2_MAP_V 0x1F -#define INTERRUPT_CORE1_TIMER_INT2_MAP_S 0 +#define INTERRUPT_CORE1_TIMER_INT2_MAP 0x0000001F +#define INTERRUPT_CORE1_TIMER_INT2_MAP_M ((INTERRUPT_CORE1_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE1_TIMER_INT2_MAP_S)) +#define INTERRUPT_CORE1_TIMER_INT2_MAP_V 0x1F +#define INTERRUPT_CORE1_TIMER_INT2_MAP_S 0 -#define INTERRUPT_CORE1_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C8) +#define INTERRUPT_CORE1_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C8) /* INTERRUPT_CORE1_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TG_T0_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_TG_T0_INT_MAP_M ((INTERRUPT_CORE1_TG_T0_INT_MAP_V) << (INTERRUPT_CORE1_TG_T0_INT_MAP_S)) -#define INTERRUPT_CORE1_TG_T0_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_TG_T0_INT_MAP_S 0 +#define INTERRUPT_CORE1_TG_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG_T0_INT_MAP_M ((INTERRUPT_CORE1_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TG_T0_INT_MAP_S)) +#define INTERRUPT_CORE1_TG_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG_T0_INT_MAP_S 0 -#define INTERRUPT_CORE1_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8CC) +#define INTERRUPT_CORE1_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8CC) /* INTERRUPT_CORE1_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TG_T1_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_TG_T1_INT_MAP_M ((INTERRUPT_CORE1_TG_T1_INT_MAP_V) << (INTERRUPT_CORE1_TG_T1_INT_MAP_S)) -#define INTERRUPT_CORE1_TG_T1_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_TG_T1_INT_MAP_S 0 +#define INTERRUPT_CORE1_TG_T1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG_T1_INT_MAP_M ((INTERRUPT_CORE1_TG_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TG_T1_INT_MAP_S)) +#define INTERRUPT_CORE1_TG_T1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG_T1_INT_MAP_S 0 -#define INTERRUPT_CORE1_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D0) +#define INTERRUPT_CORE1_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D0) /* INTERRUPT_CORE1_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TG_WDT_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_TG_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG_WDT_INT_MAP_V) << (INTERRUPT_CORE1_TG_WDT_INT_MAP_S)) -#define INTERRUPT_CORE1_TG_WDT_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_TG_WDT_INT_MAP_S 0 +#define INTERRUPT_CORE1_TG_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TG_WDT_INT_MAP_S)) +#define INTERRUPT_CORE1_TG_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE1_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D4) +#define INTERRUPT_CORE1_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D4) /* INTERRUPT_CORE1_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TG1_T0_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_TG1_T0_INT_MAP_M ((INTERRUPT_CORE1_TG1_T0_INT_MAP_V) << (INTERRUPT_CORE1_TG1_T0_INT_MAP_S)) -#define INTERRUPT_CORE1_TG1_T0_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_TG1_T0_INT_MAP_S 0 +#define INTERRUPT_CORE1_TG1_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG1_T0_INT_MAP_M ((INTERRUPT_CORE1_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TG1_T0_INT_MAP_S)) +#define INTERRUPT_CORE1_TG1_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG1_T0_INT_MAP_S 0 -#define INTERRUPT_CORE1_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D8) +#define INTERRUPT_CORE1_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D8) /* INTERRUPT_CORE1_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TG1_T1_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_TG1_T1_INT_MAP_M ((INTERRUPT_CORE1_TG1_T1_INT_MAP_V) << (INTERRUPT_CORE1_TG1_T1_INT_MAP_S)) -#define INTERRUPT_CORE1_TG1_T1_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_TG1_T1_INT_MAP_S 0 +#define INTERRUPT_CORE1_TG1_T1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG1_T1_INT_MAP_M ((INTERRUPT_CORE1_TG1_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TG1_T1_INT_MAP_S)) +#define INTERRUPT_CORE1_TG1_T1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG1_T1_INT_MAP_S 0 -#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8DC) +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8DC) /* INTERRUPT_CORE1_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_TG1_WDT_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG1_WDT_INT_MAP_V) << (INTERRUPT_CORE1_TG1_WDT_INT_MAP_S)) -#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_S 0 +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TG1_WDT_INT_MAP_S)) +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_S 0 -#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E0) +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E0) /* INTERRUPT_CORE1_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CACHE_IA_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE1_CACHE_IA_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_IA_INT_MAP_S)) -#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_S 0 +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE1_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_IA_INT_MAP_S)) +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_S 0 -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E4) +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E4) /* INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S)) -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0 +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S)) +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0 -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E8) +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E8) /* INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S)) -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0 +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S)) +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0 -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8EC) +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8EC) /* INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S)) -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0 +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S)) +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0 -#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F0) +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F0) /* INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V) << (INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S)) -#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S 0 +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S)) +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S 0 -#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F4) +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F4) /* INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S)) -#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S 0 +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S 0 -#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F8) +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F8) /* INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S)) -#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S 0 +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S 0 -#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8FC) +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8FC) /* INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S)) -#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S 0 +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S 0 -#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x900) +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x900) /* INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S)) -#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S 0 +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S 0 -#define INTERRUPT_CORE1_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x904) +#define INTERRUPT_CORE1_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x904) /* INTERRUPT_CORE1_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_APB_ADC_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_APB_ADC_INT_MAP_M ((INTERRUPT_CORE1_APB_ADC_INT_MAP_V) << (INTERRUPT_CORE1_APB_ADC_INT_MAP_S)) -#define INTERRUPT_CORE1_APB_ADC_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_APB_ADC_INT_MAP_S 0 +#define INTERRUPT_CORE1_APB_ADC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_APB_ADC_INT_MAP_M ((INTERRUPT_CORE1_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE1_APB_ADC_INT_MAP_S)) +#define INTERRUPT_CORE1_APB_ADC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_APB_ADC_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x908) -/* INTERRUPT_CORE1_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x908) +/* INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_DMA_CH0_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH0_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH0_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_S 0 +#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90C) -/* INTERRUPT_CORE1_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90C) +/* INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_DMA_CH1_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH1_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH1_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_S 0 +#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x910) -/* INTERRUPT_CORE1_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x910) +/* INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_DMA_CH2_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH2_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH2_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_S 0 +#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x914) -/* INTERRUPT_CORE1_DMA_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x914) +/* INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_DMA_CH3_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH3_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH3_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_S 0 +#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_S 0 -#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x918) -/* INTERRUPT_CORE1_DMA_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x918) +/* INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_DMA_CH4_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH4_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH4_INT_MAP_S)) -#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_S 0 +#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_S 0 -#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x91C) +#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x91C) +/* INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x920) +/* INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x924) +/* INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x928) +/* INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x92C) +/* INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_S 0 + +#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x930) /* INTERRUPT_CORE1_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_RSA_INT_MAP_M ((INTERRUPT_CORE1_RSA_INT_MAP_V) << (INTERRUPT_CORE1_RSA_INT_MAP_S)) -#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_RSA_INT_MAP_S 0 +#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_RSA_INT_MAP_M ((INTERRUPT_CORE1_RSA_INT_MAP_V)<<(INTERRUPT_CORE1_RSA_INT_MAP_S)) +#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_RSA_INT_MAP_S 0 -#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x920) +#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x934) /* INTERRUPT_CORE1_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_AES_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_AES_INT_MAP_M ((INTERRUPT_CORE1_AES_INT_MAP_V) << (INTERRUPT_CORE1_AES_INT_MAP_S)) -#define INTERRUPT_CORE1_AES_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_AES_INT_MAP_S 0 +#define INTERRUPT_CORE1_AES_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_AES_INT_MAP_M ((INTERRUPT_CORE1_AES_INT_MAP_V)<<(INTERRUPT_CORE1_AES_INT_MAP_S)) +#define INTERRUPT_CORE1_AES_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_AES_INT_MAP_S 0 -#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x924) +#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x938) /* INTERRUPT_CORE1_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_SHA_INT_MAP_M ((INTERRUPT_CORE1_SHA_INT_MAP_V) << (INTERRUPT_CORE1_SHA_INT_MAP_S)) -#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_SHA_INT_MAP_S 0 +#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SHA_INT_MAP_M ((INTERRUPT_CORE1_SHA_INT_MAP_V)<<(INTERRUPT_CORE1_SHA_INT_MAP_S)) +#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SHA_INT_MAP_S 0 -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x928) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x93C) /* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP 0x0000001F -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S)) -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V 0x1F -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S 0 +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S)) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S 0 -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x92C) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x940) /* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP 0x0000001F -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S)) -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V 0x1F -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S 0 +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S)) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S 0 -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x930) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x944) /* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP 0x0000001F -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S)) -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V 0x1F -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S 0 +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S)) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S 0 -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x934) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x948) /* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP 0x0000001F -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S)) -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V 0x1F -#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S 0 +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S)) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S 0 -#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x938) +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94C) /* INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V) << (INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S)) -#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S 0 +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S)) +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S 0 -#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x93C) +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x950) /* INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x940) +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x954) /* INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x944) +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x958) /* INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x948) +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x95C) /* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94C) +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x960) /* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x950) +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x964) /* INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x954) +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x968) /* INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x958) +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x96C) /* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x95C) +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x970) /* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 -#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x960) +#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x974) +/* INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x978) /* INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S)) -#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S 0 +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S)) +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S 0 -#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x964) +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x97C) /* INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP 0x0000001F -#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S)) -#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V 0x1F -#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S 0 +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S)) +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S 0 -#define INTERRUPT_CORE1_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x968) +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x980) +/* INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M ((INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S)) +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S 0 + +#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x984) +/* INTERRUPT_CORE1_PERI_BACKUP_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_M ((INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_V)<<(INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_S)) +#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x988) +/* INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_M ((INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_S 0 + +#define INTERRUPT_CORE1_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98C) /* INTERRUPT_CORE1_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_0_M ((INTERRUPT_CORE1_INTR_STATUS_0_V) << (INTERRUPT_CORE1_INTR_STATUS_0_S)) -#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_0_S 0 +#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_0_M ((INTERRUPT_CORE1_INTR_STATUS_0_V)<<(INTERRUPT_CORE1_INTR_STATUS_0_S)) +#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_0_S 0 -#define INTERRUPT_CORE1_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x96C) +#define INTERRUPT_CORE1_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x990) /* INTERRUPT_CORE1_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_1_M ((INTERRUPT_CORE1_INTR_STATUS_1_V) << (INTERRUPT_CORE1_INTR_STATUS_1_S)) -#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_1_S 0 +#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_1_M ((INTERRUPT_CORE1_INTR_STATUS_1_V)<<(INTERRUPT_CORE1_INTR_STATUS_1_S)) +#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_1_S 0 -#define INTERRUPT_CORE1_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x970) +#define INTERRUPT_CORE1_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x994) /* INTERRUPT_CORE1_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_2_M ((INTERRUPT_CORE1_INTR_STATUS_2_V) << (INTERRUPT_CORE1_INTR_STATUS_2_S)) -#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFF -#define INTERRUPT_CORE1_INTR_STATUS_2_S 0 +#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_2_M ((INTERRUPT_CORE1_INTR_STATUS_2_V)<<(INTERRUPT_CORE1_INTR_STATUS_2_S)) +#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_2_S 0 -#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x974) +#define INTERRUPT_CORE1_INTR_STATUS_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x998) +/* INTERRUPT_CORE1_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE1_INTR_STATUS_3 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_3_M ((INTERRUPT_CORE1_INTR_STATUS_3_V)<<(INTERRUPT_CORE1_INTR_STATUS_3_S)) +#define INTERRUPT_CORE1_INTR_STATUS_3_V 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_3_S 0 + +#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x99c) /* INTERRUPT_CORE1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ -#define INTERRUPT_CORE1_CLK_EN (BIT(0)) -#define INTERRUPT_CORE1_CLK_EN_M (BIT(0)) -#define INTERRUPT_CORE1_CLK_EN_V 0x1 -#define INTERRUPT_CORE1_CLK_EN_S 0 +#define INTERRUPT_CORE1_CLK_EN (BIT(0)) +#define INTERRUPT_CORE1_CLK_EN_M (BIT(0)) +#define INTERRUPT_CORE1_CLK_EN_V 0x1 +#define INTERRUPT_CORE1_CLK_EN_S 0 -#define INTERRUPT_CORE1_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xFFC) -/* INTERRUPT_CORE1_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */ +#define INTERRUPT_CORE1_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xFFC) +/* INTERRUPT_CORE1_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */ /*description: */ -#define INTERRUPT_CORE1_INTERRUPT_DATE 0x0FFFFFFF -#define INTERRUPT_CORE1_INTERRUPT_DATE_M ((INTERRUPT_CORE1_INTERRUPT_DATE_V) << (INTERRUPT_CORE1_INTERRUPT_DATE_S)) -#define INTERRUPT_CORE1_INTERRUPT_DATE_V 0xFFFFFFF -#define INTERRUPT_CORE1_INTERRUPT_DATE_S 0 +#define INTERRUPT_CORE1_INTERRUPT_DATE 0x0FFFFFFF +#define INTERRUPT_CORE1_INTERRUPT_DATE_M ((INTERRUPT_CORE1_INTERRUPT_DATE_V)<<(INTERRUPT_CORE1_INTERRUPT_DATE_S)) +#define INTERRUPT_CORE1_INTERRUPT_DATE_V 0xFFFFFFF +#define INTERRUPT_CORE1_INTERRUPT_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_INTERRUPT_CORE1_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/interrupt_core1_struct.h b/components/soc/esp32s3/include/soc/interrupt_core1_struct.h index cddcb10308..41147b428a 100644 --- a/components/soc/esp32s3/include/soc/interrupt_core1_struct.h +++ b/components/soc/esp32s3/include/soc/interrupt_core1_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,14 +11,12 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_INTERRUPT_CORE1_STRUCT_H_ +#define _SOC_INTERRUPT_CORE1_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif -#include - typedef volatile struct { uint32_t reserved_0; uint32_t reserved_4; @@ -996,39 +994,74 @@ typedef volatile struct { } core1_apb_adc_int_map; union { struct { - uint32_t core1_dma_ch0_int_map: 5; - uint32_t reserved5: 27; + uint32_t core1_dma_in_ch0_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core1_dma_ch0_int_map; + } core1_dma_in_ch0_int_map; union { struct { - uint32_t core1_dma_ch1_int_map: 5; - uint32_t reserved5: 27; + uint32_t core1_dma_in_ch1_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core1_dma_ch1_int_map; + } core1_dma_in_ch1_int_map; union { struct { - uint32_t core1_dma_ch2_int_map: 5; - uint32_t reserved5: 27; + uint32_t core1_dma_in_ch2_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core1_dma_ch2_int_map; + } core1_dma_in_ch2_int_map; union { struct { - uint32_t core1_dma_ch3_int_map: 5; - uint32_t reserved5: 27; + uint32_t core1_dma_in_ch3_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core1_dma_ch3_int_map; + } core1_dma_in_ch3_int_map; union { struct { - uint32_t core1_dma_ch4_int_map: 5; - uint32_t reserved5: 27; + uint32_t core1_dma_in_ch4_int_map: 5; + uint32_t reserved5: 27; }; uint32_t val; - } core1_dma_ch4_int_map; + } core1_dma_in_ch4_int_map; + union { + struct { + uint32_t core1_dma_out_ch0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_out_ch0_int_map; + union { + struct { + uint32_t core1_dma_out_ch1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_out_ch1_int_map; + union { + struct { + uint32_t core1_dma_out_ch2_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_out_ch2_int_map; + union { + struct { + uint32_t core1_dma_out_ch3_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_out_ch3_int_map; + union { + struct { + uint32_t core1_dma_out_ch4_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_out_ch4_int_map; union { struct { uint32_t core1_rsa_int_map: 5; @@ -1148,6 +1181,13 @@ typedef volatile struct { }; uint32_t val; } core1_core_1_pif_pms_monitor_violate_size_intr_map; + union { + struct { + uint32_t core1_backup_pms_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_backup_pms_violate_intr_map; union { struct { uint32_t core1_cache_core0_acs_int_map: 5; @@ -1162,9 +1202,31 @@ typedef volatile struct { }; uint32_t val; } core1_cache_core1_acs_int_map; + union { + struct { + uint32_t core1_usb_device_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_usb_device_int_map; + union { + struct { + uint32_t core1_peri_backup_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_peri_backup_int_map; + union { + struct { + uint32_t core1_dma_extmem_reject_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_extmem_reject_int_map; uint32_t core1_intr_status_0; /**/ uint32_t core1_intr_status_1; /**/ uint32_t core1_intr_status_2; /**/ + uint32_t core1_intr_status_3; /**/ union { struct { uint32_t core1_clk_en: 1; @@ -1172,16 +1234,6 @@ typedef volatile struct { }; uint32_t val; } core1_clock_gate; - uint32_t reserved_978; - uint32_t reserved_97c; - uint32_t reserved_980; - uint32_t reserved_984; - uint32_t reserved_988; - uint32_t reserved_98c; - uint32_t reserved_990; - uint32_t reserved_994; - uint32_t reserved_998; - uint32_t reserved_99c; uint32_t reserved_9a0; uint32_t reserved_9a4; uint32_t reserved_9a8; @@ -1591,15 +1643,15 @@ typedef volatile struct { uint32_t reserved_ff8; union { struct { - uint32_t core1_interrupt_date: 28; + uint32_t core1_interrupt_date:28; uint32_t reserved28: 4; }; uint32_t val; } core1_interrupt_date; } interrupt_core1_dev_t; - extern interrupt_core1_dev_t INTERRUPT_CORE1; - #ifdef __cplusplus } #endif + +#endif /* _SOC_INTERRUPT_CORE1_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/lcd_cam_reg.h b/components/soc/esp32s3/include/soc/lcd_cam_reg.h index f43dfd6e6f..5efb19193e 100644 --- a/components/soc/esp32s3/include/soc/lcd_cam_reg.h +++ b/components/soc/esp32s3/include/soc/lcd_cam_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,830 +11,836 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_LCD_CAM_REG_H_ +#define _SOC_LCD_CAM_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x000) +#define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x0) /* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Set this bit to enable clk gate*/ -#define LCD_CAM_CLK_EN (BIT(31)) -#define LCD_CAM_CLK_EN_M (BIT(31)) -#define LCD_CAM_CLK_EN_V 0x1 -#define LCD_CAM_CLK_EN_S 31 +/*description: Set this bit to enable clk gate.*/ +#define LCD_CAM_CLK_EN (BIT(31)) +#define LCD_CAM_CLK_EN_M (BIT(31)) +#define LCD_CAM_CLK_EN_V 0x1 +#define LCD_CAM_CLK_EN_S 31 /* LCD_CAM_LCD_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ -/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/ -#define LCD_CAM_LCD_CLK_SEL 0x00000003 -#define LCD_CAM_LCD_CLK_SEL_M ((LCD_CAM_LCD_CLK_SEL_V) << (LCD_CAM_LCD_CLK_SEL_S)) -#define LCD_CAM_LCD_CLK_SEL_V 0x3 -#define LCD_CAM_LCD_CLK_SEL_S 29 +/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/ +#define LCD_CAM_LCD_CLK_SEL 0x00000003 +#define LCD_CAM_LCD_CLK_SEL_M ((LCD_CAM_LCD_CLK_SEL_V)<<(LCD_CAM_LCD_CLK_SEL_S)) +#define LCD_CAM_LCD_CLK_SEL_V 0x3 +#define LCD_CAM_LCD_CLK_SEL_S 29 /* LCD_CAM_LCD_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */ -/*description: Fractional clock divider denominator value*/ -#define LCD_CAM_LCD_CLKM_DIV_A 0x0000003F -#define LCD_CAM_LCD_CLKM_DIV_A_M ((LCD_CAM_LCD_CLKM_DIV_A_V) << (LCD_CAM_LCD_CLKM_DIV_A_S)) -#define LCD_CAM_LCD_CLKM_DIV_A_V 0x3F -#define LCD_CAM_LCD_CLKM_DIV_A_S 23 +/*description: Fractional clock divider denominator value.*/ +#define LCD_CAM_LCD_CLKM_DIV_A 0x0000003F +#define LCD_CAM_LCD_CLKM_DIV_A_M ((LCD_CAM_LCD_CLKM_DIV_A_V)<<(LCD_CAM_LCD_CLKM_DIV_A_S)) +#define LCD_CAM_LCD_CLKM_DIV_A_V 0x3F +#define LCD_CAM_LCD_CLKM_DIV_A_S 23 /* LCD_CAM_LCD_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */ -/*description: Fractional clock divider numerator value*/ -#define LCD_CAM_LCD_CLKM_DIV_B 0x0000003F -#define LCD_CAM_LCD_CLKM_DIV_B_M ((LCD_CAM_LCD_CLKM_DIV_B_V) << (LCD_CAM_LCD_CLKM_DIV_B_S)) -#define LCD_CAM_LCD_CLKM_DIV_B_V 0x3F -#define LCD_CAM_LCD_CLKM_DIV_B_S 17 +/*description: Fractional clock divider numerator value.*/ +#define LCD_CAM_LCD_CLKM_DIV_B 0x0000003F +#define LCD_CAM_LCD_CLKM_DIV_B_M ((LCD_CAM_LCD_CLKM_DIV_B_V)<<(LCD_CAM_LCD_CLKM_DIV_B_S)) +#define LCD_CAM_LCD_CLKM_DIV_B_V 0x3F +#define LCD_CAM_LCD_CLKM_DIV_B_S 17 /* LCD_CAM_LCD_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */ -/*description: Integral LCD clock divider value*/ -#define LCD_CAM_LCD_CLKM_DIV_NUM 0x000000FF -#define LCD_CAM_LCD_CLKM_DIV_NUM_M ((LCD_CAM_LCD_CLKM_DIV_NUM_V) << (LCD_CAM_LCD_CLKM_DIV_NUM_S)) -#define LCD_CAM_LCD_CLKM_DIV_NUM_V 0xFF -#define LCD_CAM_LCD_CLKM_DIV_NUM_S 9 +/*description: Integral LCD clock divider value.*/ +#define LCD_CAM_LCD_CLKM_DIV_NUM 0x000000FF +#define LCD_CAM_LCD_CLKM_DIV_NUM_M ((LCD_CAM_LCD_CLKM_DIV_NUM_V)<<(LCD_CAM_LCD_CLKM_DIV_NUM_S)) +#define LCD_CAM_LCD_CLKM_DIV_NUM_V 0xFF +#define LCD_CAM_LCD_CLKM_DIV_NUM_S 9 /* LCD_CAM_LCD_CK_OUT_EDGE : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define LCD_CAM_LCD_CK_OUT_EDGE (BIT(8)) -#define LCD_CAM_LCD_CK_OUT_EDGE_M (BIT(8)) -#define LCD_CAM_LCD_CK_OUT_EDGE_V 0x1 -#define LCD_CAM_LCD_CK_OUT_EDGE_S 8 +/*description: .*/ +#define LCD_CAM_LCD_CK_OUT_EDGE (BIT(8)) +#define LCD_CAM_LCD_CK_OUT_EDGE_M (BIT(8)) +#define LCD_CAM_LCD_CK_OUT_EDGE_V 0x1 +#define LCD_CAM_LCD_CK_OUT_EDGE_S 8 /* LCD_CAM_LCD_CK_IDLE_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.*/ -#define LCD_CAM_LCD_CK_IDLE_EDGE (BIT(7)) -#define LCD_CAM_LCD_CK_IDLE_EDGE_M (BIT(7)) -#define LCD_CAM_LCD_CK_IDLE_EDGE_V 0x1 -#define LCD_CAM_LCD_CK_IDLE_EDGE_S 7 +/*description: 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. .*/ +#define LCD_CAM_LCD_CK_IDLE_EDGE (BIT(7)) +#define LCD_CAM_LCD_CK_IDLE_EDGE_M (BIT(7)) +#define LCD_CAM_LCD_CK_IDLE_EDGE_V 0x1 +#define LCD_CAM_LCD_CK_IDLE_EDGE_S 7 /* LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W ;bitpos:[6] ;default: 1'h1 ; */ -/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/ -#define LCD_CAM_LCD_CLK_EQU_SYSCLK (BIT(6)) -#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M (BIT(6)) -#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V 0x1 -#define LCD_CAM_LCD_CLK_EQU_SYSCLK_S 6 +/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)..*/ +#define LCD_CAM_LCD_CLK_EQU_SYSCLK (BIT(6)) +#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M (BIT(6)) +#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V 0x1 +#define LCD_CAM_LCD_CLK_EQU_SYSCLK_S 6 /* LCD_CAM_LCD_CLKCNT_N : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ -/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/ -#define LCD_CAM_LCD_CLKCNT_N 0x0000003F -#define LCD_CAM_LCD_CLKCNT_N_M ((LCD_CAM_LCD_CLKCNT_N_V) << (LCD_CAM_LCD_CLKCNT_N_S)) -#define LCD_CAM_LCD_CLKCNT_N_V 0x3F -#define LCD_CAM_LCD_CLKCNT_N_S 0 +/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0..*/ +#define LCD_CAM_LCD_CLKCNT_N 0x0000003F +#define LCD_CAM_LCD_CLKCNT_N_M ((LCD_CAM_LCD_CLKCNT_N_V)<<(LCD_CAM_LCD_CLKCNT_N_S)) +#define LCD_CAM_LCD_CLKCNT_N_V 0x3F +#define LCD_CAM_LCD_CLKCNT_N_S 0 -#define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x004) +#define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x4) /* LCD_CAM_CAM_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ -/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/ -#define LCD_CAM_CAM_CLK_SEL 0x00000003 -#define LCD_CAM_CAM_CLK_SEL_M ((LCD_CAM_CAM_CLK_SEL_V) << (LCD_CAM_CAM_CLK_SEL_S)) -#define LCD_CAM_CAM_CLK_SEL_V 0x3 -#define LCD_CAM_CAM_CLK_SEL_S 29 +/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/ +#define LCD_CAM_CAM_CLK_SEL 0x00000003 +#define LCD_CAM_CAM_CLK_SEL_M ((LCD_CAM_CAM_CLK_SEL_V)<<(LCD_CAM_CAM_CLK_SEL_S)) +#define LCD_CAM_CAM_CLK_SEL_V 0x3 +#define LCD_CAM_CAM_CLK_SEL_S 29 /* LCD_CAM_CAM_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */ -/*description: Fractional clock divider denominator value*/ -#define LCD_CAM_CAM_CLKM_DIV_A 0x0000003F -#define LCD_CAM_CAM_CLKM_DIV_A_M ((LCD_CAM_CAM_CLKM_DIV_A_V) << (LCD_CAM_CAM_CLKM_DIV_A_S)) -#define LCD_CAM_CAM_CLKM_DIV_A_V 0x3F -#define LCD_CAM_CAM_CLKM_DIV_A_S 23 +/*description: Fractional clock divider denominator value.*/ +#define LCD_CAM_CAM_CLKM_DIV_A 0x0000003F +#define LCD_CAM_CAM_CLKM_DIV_A_M ((LCD_CAM_CAM_CLKM_DIV_A_V)<<(LCD_CAM_CAM_CLKM_DIV_A_S)) +#define LCD_CAM_CAM_CLKM_DIV_A_V 0x3F +#define LCD_CAM_CAM_CLKM_DIV_A_S 23 /* LCD_CAM_CAM_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */ -/*description: Fractional clock divider numerator value*/ -#define LCD_CAM_CAM_CLKM_DIV_B 0x0000003F -#define LCD_CAM_CAM_CLKM_DIV_B_M ((LCD_CAM_CAM_CLKM_DIV_B_V) << (LCD_CAM_CAM_CLKM_DIV_B_S)) -#define LCD_CAM_CAM_CLKM_DIV_B_V 0x3F -#define LCD_CAM_CAM_CLKM_DIV_B_S 17 +/*description: Fractional clock divider numerator value.*/ +#define LCD_CAM_CAM_CLKM_DIV_B 0x0000003F +#define LCD_CAM_CAM_CLKM_DIV_B_M ((LCD_CAM_CAM_CLKM_DIV_B_V)<<(LCD_CAM_CAM_CLKM_DIV_B_S)) +#define LCD_CAM_CAM_CLKM_DIV_B_V 0x3F +#define LCD_CAM_CAM_CLKM_DIV_B_S 17 /* LCD_CAM_CAM_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */ -/*description: Integral Camera clock divider value*/ -#define LCD_CAM_CAM_CLKM_DIV_NUM 0x000000FF -#define LCD_CAM_CAM_CLKM_DIV_NUM_M ((LCD_CAM_CAM_CLKM_DIV_NUM_V) << (LCD_CAM_CAM_CLKM_DIV_NUM_S)) -#define LCD_CAM_CAM_CLKM_DIV_NUM_V 0xFF -#define LCD_CAM_CAM_CLKM_DIV_NUM_S 9 +/*description: Integral Camera clock divider value.*/ +#define LCD_CAM_CAM_CLKM_DIV_NUM 0x000000FF +#define LCD_CAM_CAM_CLKM_DIV_NUM_M ((LCD_CAM_CAM_CLKM_DIV_NUM_V)<<(LCD_CAM_CAM_CLKM_DIV_NUM_S)) +#define LCD_CAM_CAM_CLKM_DIV_NUM_V 0xFF +#define LCD_CAM_CAM_CLKM_DIV_NUM_S 9 /* LCD_CAM_CAM_VS_EOF_EN : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled - by reg_cam_rec_data_cyclelen.*/ -#define LCD_CAM_CAM_VS_EOF_EN (BIT(8)) -#define LCD_CAM_CAM_VS_EOF_EN_M (BIT(8)) -#define LCD_CAM_CAM_VS_EOF_EN_V 0x1 -#define LCD_CAM_CAM_VS_EOF_EN_S 8 +/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_ +data_cyclelen..*/ +#define LCD_CAM_CAM_VS_EOF_EN (BIT(8)) +#define LCD_CAM_CAM_VS_EOF_EN_M (BIT(8)) +#define LCD_CAM_CAM_VS_EOF_EN_V 0x1 +#define LCD_CAM_CAM_VS_EOF_EN_S 8 /* LCD_CAM_CAM_LINE_INT_EN : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: 1: Enable to generate CAM_HS_INT. 0: Disable.*/ -#define LCD_CAM_CAM_LINE_INT_EN (BIT(7)) -#define LCD_CAM_CAM_LINE_INT_EN_M (BIT(7)) -#define LCD_CAM_CAM_LINE_INT_EN_V 0x1 -#define LCD_CAM_CAM_LINE_INT_EN_S 7 +/*description: 1: Enable to generate CAM_HS_INT. 0: Disable..*/ +#define LCD_CAM_CAM_LINE_INT_EN (BIT(7)) +#define LCD_CAM_CAM_LINE_INT_EN_M (BIT(7)) +#define LCD_CAM_CAM_LINE_INT_EN_V 0x1 +#define LCD_CAM_CAM_LINE_INT_EN_S 7 /* LCD_CAM_CAM_BIT_ORDER : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: 1: invert data byte order only valid in 2 byte mode. 0: Not change.*/ -#define LCD_CAM_CAM_BIT_ORDER (BIT(6)) -#define LCD_CAM_CAM_BIT_ORDER_M (BIT(6)) -#define LCD_CAM_CAM_BIT_ORDER_V 0x1 -#define LCD_CAM_CAM_BIT_ORDER_S 6 +/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/ +#define LCD_CAM_CAM_BIT_ORDER (BIT(6)) +#define LCD_CAM_CAM_BIT_ORDER_M (BIT(6)) +#define LCD_CAM_CAM_BIT_ORDER_V 0x1 +#define LCD_CAM_CAM_BIT_ORDER_S 6 /* LCD_CAM_CAM_BYTE_ORDER : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: 1: Change data bit order change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] - in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/ -#define LCD_CAM_CAM_BYTE_ORDER (BIT(5)) -#define LCD_CAM_CAM_BYTE_ORDER_M (BIT(5)) -#define LCD_CAM_CAM_BYTE_ORDER_V 0x1 -#define LCD_CAM_CAM_BYTE_ORDER_S 5 +/*description: 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byt +e mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change..*/ +#define LCD_CAM_CAM_BYTE_ORDER (BIT(5)) +#define LCD_CAM_CAM_BYTE_ORDER_M (BIT(5)) +#define LCD_CAM_CAM_BYTE_ORDER_V 0x1 +#define LCD_CAM_CAM_BYTE_ORDER_S 5 /* LCD_CAM_CAM_UPDATE_REG : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: 1: Update Camera registers will be cleared by hardware. 0 : Not care.*/ -#define LCD_CAM_CAM_UPDATE_REG (BIT(4)) -#define LCD_CAM_CAM_UPDATE_REG_M (BIT(4)) -#define LCD_CAM_CAM_UPDATE_REG_V 0x1 -#define LCD_CAM_CAM_UPDATE_REG_S 4 +/*description: 1: Update Camera registers, will be cleared by hardware. 0 : Not care..*/ +#define LCD_CAM_CAM_UPDATE_REG (BIT(4)) +#define LCD_CAM_CAM_UPDATE_REG_M (BIT(4)) +#define LCD_CAM_CAM_UPDATE_REG_V 0x1 +#define LCD_CAM_CAM_UPDATE_REG_S 4 /* LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W ;bitpos:[3:1] ;default: 3'h0 ; */ -/*description: Filter threshold value for CAM_VSYNC signal.*/ -#define LCD_CAM_CAM_VSYNC_FILTER_THRES 0x00000007 -#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V) << (LCD_CAM_CAM_VSYNC_FILTER_THRES_S)) -#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V 0x7 -#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S 1 +/*description: Filter threshold value for CAM_VSYNC signal..*/ +#define LCD_CAM_CAM_VSYNC_FILTER_THRES 0x00000007 +#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V)<<(LCD_CAM_CAM_VSYNC_FILTER_THRES_S)) +#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V 0x7 +#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S 1 /* LCD_CAM_CAM_STOP_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Camera stop enable signal 1: camera stops when DMA Rx FIFO is - full. 0: Not stop.*/ -#define LCD_CAM_CAM_STOP_EN (BIT(0)) -#define LCD_CAM_CAM_STOP_EN_M (BIT(0)) -#define LCD_CAM_CAM_STOP_EN_V 0x1 -#define LCD_CAM_CAM_STOP_EN_S 0 +/*description: Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop +..*/ +#define LCD_CAM_CAM_STOP_EN (BIT(0)) +#define LCD_CAM_CAM_STOP_EN_M (BIT(0)) +#define LCD_CAM_CAM_STOP_EN_V 0x1 +#define LCD_CAM_CAM_STOP_EN_S 0 -#define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x008) +#define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x8) /* LCD_CAM_CAM_AFIFO_RESET : WO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Camera AFIFO reset signal.*/ -#define LCD_CAM_CAM_AFIFO_RESET (BIT(31)) -#define LCD_CAM_CAM_AFIFO_RESET_M (BIT(31)) -#define LCD_CAM_CAM_AFIFO_RESET_V 0x1 -#define LCD_CAM_CAM_AFIFO_RESET_S 31 +/*description: Camera AFIFO reset signal..*/ +#define LCD_CAM_CAM_AFIFO_RESET (BIT(31)) +#define LCD_CAM_CAM_AFIFO_RESET_M (BIT(31)) +#define LCD_CAM_CAM_AFIFO_RESET_V 0x1 +#define LCD_CAM_CAM_AFIFO_RESET_S 31 /* LCD_CAM_CAM_RESET : WO ;bitpos:[30] ;default: 1'h0 ; */ -/*description: Camera module reset signal.*/ -#define LCD_CAM_CAM_RESET (BIT(30)) -#define LCD_CAM_CAM_RESET_M (BIT(30)) -#define LCD_CAM_CAM_RESET_V 0x1 -#define LCD_CAM_CAM_RESET_S 30 +/*description: Camera module reset signal..*/ +#define LCD_CAM_CAM_RESET (BIT(30)) +#define LCD_CAM_CAM_RESET_M (BIT(30)) +#define LCD_CAM_CAM_RESET_V 0x1 +#define LCD_CAM_CAM_RESET_S 30 /* LCD_CAM_CAM_START : R/W ;bitpos:[29] ;default: 1'h0 ; */ -/*description: Camera module start signal.*/ -#define LCD_CAM_CAM_START (BIT(29)) -#define LCD_CAM_CAM_START_M (BIT(29)) -#define LCD_CAM_CAM_START_V 0x1 -#define LCD_CAM_CAM_START_S 29 +/*description: Camera module start signal..*/ +#define LCD_CAM_CAM_START (BIT(29)) +#define LCD_CAM_CAM_START_M (BIT(29)) +#define LCD_CAM_CAM_START_V 0x1 +#define LCD_CAM_CAM_START_S 29 /* LCD_CAM_CAM_VH_DE_MODE_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ -/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is - 1. 0: Input control signals are CAM_DE and CAM_VSYNC*/ -#define LCD_CAM_CAM_VH_DE_MODE_EN (BIT(28)) -#define LCD_CAM_CAM_VH_DE_MODE_EN_M (BIT(28)) -#define LCD_CAM_CAM_VH_DE_MODE_EN_V 0x1 -#define LCD_CAM_CAM_VH_DE_MODE_EN_S 28 +/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input contr +ol signals are CAM_DE and CAM_VSYNC.*/ +#define LCD_CAM_CAM_VH_DE_MODE_EN (BIT(28)) +#define LCD_CAM_CAM_VH_DE_MODE_EN_M (BIT(28)) +#define LCD_CAM_CAM_VH_DE_MODE_EN_V 0x1 +#define LCD_CAM_CAM_VH_DE_MODE_EN_S 28 /* LCD_CAM_CAM_VSYNC_INV : R/W ;bitpos:[27] ;default: 1'h0 ; */ -/*description: CAM_VSYNC invert enable signal valid in high level.*/ -#define LCD_CAM_CAM_VSYNC_INV (BIT(27)) -#define LCD_CAM_CAM_VSYNC_INV_M (BIT(27)) -#define LCD_CAM_CAM_VSYNC_INV_V 0x1 -#define LCD_CAM_CAM_VSYNC_INV_S 27 +/*description: CAM_VSYNC invert enable signal, valid in high level..*/ +#define LCD_CAM_CAM_VSYNC_INV (BIT(27)) +#define LCD_CAM_CAM_VSYNC_INV_M (BIT(27)) +#define LCD_CAM_CAM_VSYNC_INV_V 0x1 +#define LCD_CAM_CAM_VSYNC_INV_S 27 /* LCD_CAM_CAM_HSYNC_INV : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: CAM_HSYNC invert enable signal valid in high level.*/ -#define LCD_CAM_CAM_HSYNC_INV (BIT(26)) -#define LCD_CAM_CAM_HSYNC_INV_M (BIT(26)) -#define LCD_CAM_CAM_HSYNC_INV_V 0x1 -#define LCD_CAM_CAM_HSYNC_INV_S 26 +/*description: CAM_HSYNC invert enable signal, valid in high level..*/ +#define LCD_CAM_CAM_HSYNC_INV (BIT(26)) +#define LCD_CAM_CAM_HSYNC_INV_M (BIT(26)) +#define LCD_CAM_CAM_HSYNC_INV_V 0x1 +#define LCD_CAM_CAM_HSYNC_INV_S 26 /* LCD_CAM_CAM_DE_INV : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: CAM_DE invert enable signal valid in high level.*/ -#define LCD_CAM_CAM_DE_INV (BIT(25)) -#define LCD_CAM_CAM_DE_INV_M (BIT(25)) -#define LCD_CAM_CAM_DE_INV_V 0x1 -#define LCD_CAM_CAM_DE_INV_S 25 +/*description: CAM_DE invert enable signal, valid in high level..*/ +#define LCD_CAM_CAM_DE_INV (BIT(25)) +#define LCD_CAM_CAM_DE_INV_M (BIT(25)) +#define LCD_CAM_CAM_DE_INV_V 0x1 +#define LCD_CAM_CAM_DE_INV_S 25 /* LCD_CAM_CAM_2BYTE_EN : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: 1: The bit number of input data is 9~16. 0: The bit number of - input data is 0~8.*/ -#define LCD_CAM_CAM_2BYTE_EN (BIT(24)) -#define LCD_CAM_CAM_2BYTE_EN_M (BIT(24)) -#define LCD_CAM_CAM_2BYTE_EN_V 0x1 -#define LCD_CAM_CAM_2BYTE_EN_S 24 +/*description: 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8 +. .*/ +#define LCD_CAM_CAM_2BYTE_EN (BIT(24)) +#define LCD_CAM_CAM_2BYTE_EN_M (BIT(24)) +#define LCD_CAM_CAM_2BYTE_EN_V 0x1 +#define LCD_CAM_CAM_2BYTE_EN_S 24 /* LCD_CAM_CAM_VSYNC_FILTER_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: 1: Enable CAM_VSYNC filter function. 0: bypass.*/ -#define LCD_CAM_CAM_VSYNC_FILTER_EN (BIT(23)) -#define LCD_CAM_CAM_VSYNC_FILTER_EN_M (BIT(23)) -#define LCD_CAM_CAM_VSYNC_FILTER_EN_V 0x1 -#define LCD_CAM_CAM_VSYNC_FILTER_EN_S 23 -/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: 1: Invert the input signal CAM_PCLK. 0: Not invert.*/ -#define LCD_CAM_CAM_CLK_INV (BIT(21)) -#define LCD_CAM_CAM_CLK_INV_M (BIT(21)) -#define LCD_CAM_CAM_CLK_INV_V 0x1 -#define LCD_CAM_CAM_CLK_INV_S 21 -/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[20:14] ;default: 7'h0 ; */ -/*description: The line number minus 1 to generate cam_hs_int.*/ -#define LCD_CAM_CAM_LINE_INT_NUM 0x0000007F -#define LCD_CAM_CAM_LINE_INT_NUM_M ((LCD_CAM_CAM_LINE_INT_NUM_V) << (LCD_CAM_CAM_LINE_INT_NUM_S)) -#define LCD_CAM_CAM_LINE_INT_NUM_V 0x7F -#define LCD_CAM_CAM_LINE_INT_NUM_S 14 -/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/ -#define LCD_CAM_CAM_REC_DATA_BYTELEN 0x00003FFF -#define LCD_CAM_CAM_REC_DATA_BYTELEN_M ((LCD_CAM_CAM_REC_DATA_BYTELEN_V) << (LCD_CAM_CAM_REC_DATA_BYTELEN_S)) -#define LCD_CAM_CAM_REC_DATA_BYTELEN_V 0x3FFF -#define LCD_CAM_CAM_REC_DATA_BYTELEN_S 0 +/*description: 1: Enable CAM_VSYNC filter function. 0: bypass..*/ +#define LCD_CAM_CAM_VSYNC_FILTER_EN (BIT(23)) +#define LCD_CAM_CAM_VSYNC_FILTER_EN_M (BIT(23)) +#define LCD_CAM_CAM_VSYNC_FILTER_EN_V 0x1 +#define LCD_CAM_CAM_VSYNC_FILTER_EN_S 23 +/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: Invert the input signal CAM_PCLK. 0: Not invert..*/ +#define LCD_CAM_CAM_CLK_INV (BIT(22)) +#define LCD_CAM_CAM_CLK_INV_M (BIT(22)) +#define LCD_CAM_CAM_CLK_INV_V 0x1 +#define LCD_CAM_CAM_CLK_INV_S 22 +/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[21:16] ;default: 6'h0 ; */ +/*description: The line number minus 1 to generate cam_hs_int..*/ +#define LCD_CAM_CAM_LINE_INT_NUM 0x0000003F +#define LCD_CAM_CAM_LINE_INT_NUM_M ((LCD_CAM_CAM_LINE_INT_NUM_V)<<(LCD_CAM_CAM_LINE_INT_NUM_S)) +#define LCD_CAM_CAM_LINE_INT_NUM_V 0x3F +#define LCD_CAM_CAM_LINE_INT_NUM_S 16 +/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int..*/ +#define LCD_CAM_CAM_REC_DATA_BYTELEN 0x0000FFFF +#define LCD_CAM_CAM_REC_DATA_BYTELEN_M ((LCD_CAM_CAM_REC_DATA_BYTELEN_V)<<(LCD_CAM_CAM_REC_DATA_BYTELEN_S)) +#define LCD_CAM_CAM_REC_DATA_BYTELEN_V 0xFFFF +#define LCD_CAM_CAM_REC_DATA_BYTELEN_S 0 -#define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x00C) +#define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0xC) /* LCD_CAM_CAM_CONV_BYPASS : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Bypass converter. 1: Enable converter.*/ -#define LCD_CAM_CAM_CONV_BYPASS (BIT(31)) -#define LCD_CAM_CAM_CONV_BYPASS_M (BIT(31)) -#define LCD_CAM_CAM_CONV_BYPASS_V 0x1 -#define LCD_CAM_CAM_CONV_BYPASS_S 31 +/*description: 0: Bypass converter. 1: Enable converter..*/ +#define LCD_CAM_CAM_CONV_BYPASS (BIT(31)) +#define LCD_CAM_CAM_CONV_BYPASS_M (BIT(31)) +#define LCD_CAM_CAM_CONV_BYPASS_V 0x1 +#define LCD_CAM_CAM_CONV_BYPASS_S 31 /* LCD_CAM_CAM_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: YUV to RGB. 1: RGB to YUV.*/ -#define LCD_CAM_CAM_CONV_TRANS_MODE (BIT(30)) -#define LCD_CAM_CAM_CONV_TRANS_MODE_M (BIT(30)) -#define LCD_CAM_CAM_CONV_TRANS_MODE_V 0x1 -#define LCD_CAM_CAM_CONV_TRANS_MODE_S 30 +/*description: 0: YUV to RGB. 1: RGB to YUV..*/ +#define LCD_CAM_CAM_CONV_TRANS_MODE (BIT(30)) +#define LCD_CAM_CAM_CONV_TRANS_MODE_M (BIT(30)) +#define LCD_CAM_CAM_CONV_TRANS_MODE_V 0x1 +#define LCD_CAM_CAM_CONV_TRANS_MODE_S 30 /* LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 0: 16bits mode. 1: 8bits mode.*/ -#define LCD_CAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) -#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M (BIT(29)) -#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V 0x1 -#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S 29 +/*description: 0: 16bits mode. 1: 8bits mode..*/ +#define LCD_CAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) +#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M (BIT(29)) +#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V 0x1 +#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S 29 /* LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full*/ -#define LCD_CAM_CAM_CONV_DATA_IN_MODE (BIT(28)) -#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M (BIT(28)) -#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V 0x1 -#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S 28 +/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/ +#define LCD_CAM_CAM_CONV_DATA_IN_MODE (BIT(28)) +#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M (BIT(28)) +#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V 0x1 +#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S 28 /* LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full*/ -#define LCD_CAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) -#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M (BIT(27)) -#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V 0x1 -#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S 27 +/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/ +#define LCD_CAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) +#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M (BIT(27)) +#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V 0x1 +#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S 27 /* LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 0:BT601. 1:BT709.*/ -#define LCD_CAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) -#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M (BIT(26)) -#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V 0x1 -#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S 26 +/*description: 0:BT601. 1:BT709..*/ +#define LCD_CAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) +#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M (BIT(26)) +#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V 0x1 +#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S 26 /* LCD_CAM_CAM_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ -/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode - decides the yuv mode of Data_in*/ -#define LCD_CAM_CAM_CONV_YUV_MODE 0x00000003 -#define LCD_CAM_CAM_CONV_YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV_MODE_V) << (LCD_CAM_CAM_CONV_YUV_MODE_S)) -#define LCD_CAM_CAM_CONV_YUV_MODE_V 0x3 -#define LCD_CAM_CAM_CONV_YUV_MODE_S 24 +/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv +mode of Data_in.*/ +#define LCD_CAM_CAM_CONV_YUV_MODE 0x00000003 +#define LCD_CAM_CAM_CONV_YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV_MODE_S)) +#define LCD_CAM_CAM_CONV_YUV_MODE_V 0x3 +#define LCD_CAM_CAM_CONV_YUV_MODE_S 24 /* LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */ -/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable - yuv2yuv mode trans_mode must be set to 1.*/ -#define LCD_CAM_CAM_CONV_YUV2YUV_MODE 0x00000003 -#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V) << (LCD_CAM_CAM_CONV_YUV2YUV_MODE_S)) -#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V 0x3 -#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S 22 +/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, +trans_mode must be set to 1. .*/ +#define LCD_CAM_CAM_CONV_YUV2YUV_MODE 0x00000003 +#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV2YUV_MODE_S)) +#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V 0x3 +#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S 22 /* LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: 1:invert every two 8bits input data. 2. disabled.*/ -#define LCD_CAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) -#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M (BIT(21)) -#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V 0x1 -#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S 21 +/*description: 1:invert every two 8bits input data. 2. disabled..*/ +#define LCD_CAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) +#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M (BIT(21)) +#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V 0x1 +#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S 21 -#define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x010) +#define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x10) /* LCD_CAM_LCD_CONV_BYPASS : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Bypass converter. 1: Enable converter.*/ -#define LCD_CAM_LCD_CONV_BYPASS (BIT(31)) -#define LCD_CAM_LCD_CONV_BYPASS_M (BIT(31)) -#define LCD_CAM_LCD_CONV_BYPASS_V 0x1 -#define LCD_CAM_LCD_CONV_BYPASS_S 31 +/*description: 0: Bypass converter. 1: Enable converter..*/ +#define LCD_CAM_LCD_CONV_BYPASS (BIT(31)) +#define LCD_CAM_LCD_CONV_BYPASS_M (BIT(31)) +#define LCD_CAM_LCD_CONV_BYPASS_V 0x1 +#define LCD_CAM_LCD_CONV_BYPASS_S 31 /* LCD_CAM_LCD_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: YUV to RGB. 1: RGB to YUV.*/ -#define LCD_CAM_LCD_CONV_TRANS_MODE (BIT(30)) -#define LCD_CAM_LCD_CONV_TRANS_MODE_M (BIT(30)) -#define LCD_CAM_LCD_CONV_TRANS_MODE_V 0x1 -#define LCD_CAM_LCD_CONV_TRANS_MODE_S 30 +/*description: 0: YUV to RGB. 1: RGB to YUV..*/ +#define LCD_CAM_LCD_CONV_TRANS_MODE (BIT(30)) +#define LCD_CAM_LCD_CONV_TRANS_MODE_M (BIT(30)) +#define LCD_CAM_LCD_CONV_TRANS_MODE_V 0x1 +#define LCD_CAM_LCD_CONV_TRANS_MODE_S 30 /* LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 0: 16bits mode. 1: 8bits mode.*/ -#define LCD_CAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) -#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M (BIT(29)) -#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V 0x1 -#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S 29 +/*description: 0: 16bits mode. 1: 8bits mode..*/ +#define LCD_CAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) +#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M (BIT(29)) +#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V 0x1 +#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S 29 /* LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full*/ -#define LCD_CAM_LCD_CONV_DATA_IN_MODE (BIT(28)) -#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M (BIT(28)) -#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V 0x1 -#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S 28 +/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/ +#define LCD_CAM_LCD_CONV_DATA_IN_MODE (BIT(28)) +#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M (BIT(28)) +#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V 0x1 +#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S 28 /* LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full*/ -#define LCD_CAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) -#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M (BIT(27)) -#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V 0x1 -#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S 27 +/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/ +#define LCD_CAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) +#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M (BIT(27)) +#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V 0x1 +#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S 27 /* LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 0:BT601. 1:BT709.*/ -#define LCD_CAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) -#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M (BIT(26)) -#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V 0x1 -#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S 26 +/*description: 0:BT601. 1:BT709..*/ +#define LCD_CAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) +#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M (BIT(26)) +#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V 0x1 +#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S 26 /* LCD_CAM_LCD_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ -/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode - decides the yuv mode of Data_in*/ -#define LCD_CAM_LCD_CONV_YUV_MODE 0x00000003 -#define LCD_CAM_LCD_CONV_YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV_MODE_V) << (LCD_CAM_LCD_CONV_YUV_MODE_S)) -#define LCD_CAM_LCD_CONV_YUV_MODE_V 0x3 -#define LCD_CAM_LCD_CONV_YUV_MODE_S 24 +/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv +mode of Data_in.*/ +#define LCD_CAM_LCD_CONV_YUV_MODE 0x00000003 +#define LCD_CAM_LCD_CONV_YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV_MODE_S)) +#define LCD_CAM_LCD_CONV_YUV_MODE_V 0x3 +#define LCD_CAM_LCD_CONV_YUV_MODE_S 24 /* LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */ -/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable - yuv2yuv mode trans_mode must be set to 1.*/ -#define LCD_CAM_LCD_CONV_YUV2YUV_MODE 0x00000003 -#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V) << (LCD_CAM_LCD_CONV_YUV2YUV_MODE_S)) -#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V 0x3 -#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S 22 +/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, +trans_mode must be set to 1. .*/ +#define LCD_CAM_LCD_CONV_YUV2YUV_MODE 0x00000003 +#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV2YUV_MODE_S)) +#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V 0x3 +#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S 22 /* LCD_CAM_LCD_CONV_TXTORX : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: 0: txtorx mode off. 1: txtorx mode on.*/ -#define LCD_CAM_LCD_CONV_TXTORX (BIT(21)) -#define LCD_CAM_LCD_CONV_TXTORX_M (BIT(21)) -#define LCD_CAM_LCD_CONV_TXTORX_V 0x1 -#define LCD_CAM_LCD_CONV_TXTORX_S 21 +/*description: 0: txtorx mode off. 1: txtorx mode on..*/ +#define LCD_CAM_LCD_CONV_TXTORX (BIT(21)) +#define LCD_CAM_LCD_CONV_TXTORX_M (BIT(21)) +#define LCD_CAM_LCD_CONV_TXTORX_V 0x1 +#define LCD_CAM_LCD_CONV_TXTORX_S 21 /* LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: 1:invert every two 8bits input data. 2. disabled.*/ -#define LCD_CAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) -#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M (BIT(20)) -#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V 0x1 -#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S 20 +/*description: 1:invert every two 8bits input data. 2. disabled..*/ +#define LCD_CAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) +#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M (BIT(20)) +#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V 0x1 +#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S 20 -#define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x014) +#define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x14) /* LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: The cycle length of command phase*/ -#define LCD_CAM_LCD_CMD_2_CYCLE_EN (BIT(31)) -#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M (BIT(31)) -#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V 0x1 -#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S 31 +/*description: The cycle length of command phase.*/ +#define LCD_CAM_LCD_CMD_2_CYCLE_EN (BIT(31)) +#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M (BIT(31)) +#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V 0x1 +#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S 31 /* LCD_CAM_LCD_DUMMY_CYCLELEN : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ -/*description: The dummy cycle length minus 1.*/ -#define LCD_CAM_LCD_DUMMY_CYCLELEN 0x00000003 -#define LCD_CAM_LCD_DUMMY_CYCLELEN_M ((LCD_CAM_LCD_DUMMY_CYCLELEN_V) << (LCD_CAM_LCD_DUMMY_CYCLELEN_S)) -#define LCD_CAM_LCD_DUMMY_CYCLELEN_V 0x3 -#define LCD_CAM_LCD_DUMMY_CYCLELEN_S 29 +/*description: The dummy cycle length minus 1..*/ +#define LCD_CAM_LCD_DUMMY_CYCLELEN 0x00000003 +#define LCD_CAM_LCD_DUMMY_CYCLELEN_M ((LCD_CAM_LCD_DUMMY_CYCLELEN_V)<<(LCD_CAM_LCD_DUMMY_CYCLELEN_S)) +#define LCD_CAM_LCD_DUMMY_CYCLELEN_V 0x3 +#define LCD_CAM_LCD_DUMMY_CYCLELEN_S 29 /* LCD_CAM_LCD_RESET : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The value of command.*/ -#define LCD_CAM_LCD_RESET (BIT(28)) -#define LCD_CAM_LCD_RESET_M (BIT(28)) -#define LCD_CAM_LCD_RESET_V 0x1 -#define LCD_CAM_LCD_RESET_S 28 +/*description: The value of command. .*/ +#define LCD_CAM_LCD_RESET (BIT(28)) +#define LCD_CAM_LCD_RESET_M (BIT(28)) +#define LCD_CAM_LCD_RESET_V 0x1 +#define LCD_CAM_LCD_RESET_S 28 /* LCD_CAM_LCD_START : R/W ;bitpos:[27] ;default: 1'h0 ; */ -/*description: LCD start sending data enable signal valid in high level.*/ -#define LCD_CAM_LCD_START (BIT(27)) -#define LCD_CAM_LCD_START_M (BIT(27)) -#define LCD_CAM_LCD_START_V 0x1 -#define LCD_CAM_LCD_START_S 27 +/*description: LCD start sending data enable signal, valid in high level..*/ +#define LCD_CAM_LCD_START (BIT(27)) +#define LCD_CAM_LCD_START_M (BIT(27)) +#define LCD_CAM_LCD_START_V 0x1 +#define LCD_CAM_LCD_START_S 27 /* LCD_CAM_LCD_CMD : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/ -#define LCD_CAM_LCD_CMD (BIT(26)) -#define LCD_CAM_LCD_CMD_M (BIT(26)) -#define LCD_CAM_LCD_CMD_V 0x1 -#define LCD_CAM_LCD_CMD_S 26 +/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable..*/ +#define LCD_CAM_LCD_CMD (BIT(26)) +#define LCD_CAM_LCD_CMD_M (BIT(26)) +#define LCD_CAM_LCD_CMD_V 0x1 +#define LCD_CAM_LCD_CMD_S 26 /* LCD_CAM_LCD_DUMMY : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/ -#define LCD_CAM_LCD_DUMMY (BIT(25)) -#define LCD_CAM_LCD_DUMMY_M (BIT(25)) -#define LCD_CAM_LCD_DUMMY_V 0x1 -#define LCD_CAM_LCD_DUMMY_S 25 +/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable..*/ +#define LCD_CAM_LCD_DUMMY (BIT(25)) +#define LCD_CAM_LCD_DUMMY_M (BIT(25)) +#define LCD_CAM_LCD_DUMMY_V 0x1 +#define LCD_CAM_LCD_DUMMY_S 25 /* LCD_CAM_LCD_DOUT : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/ -#define LCD_CAM_LCD_DOUT (BIT(24)) -#define LCD_CAM_LCD_DOUT_M (BIT(24)) -#define LCD_CAM_LCD_DOUT_V 0x1 -#define LCD_CAM_LCD_DOUT_S 24 +/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable..*/ +#define LCD_CAM_LCD_DOUT (BIT(24)) +#define LCD_CAM_LCD_DOUT_M (BIT(24)) +#define LCD_CAM_LCD_DOUT_V 0x1 +#define LCD_CAM_LCD_DOUT_S 24 /* LCD_CAM_LCD_2BYTE_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: 1: The bit number of output LCD data is 9~16. 0: The bit number - of output LCD data is 0~8.*/ -#define LCD_CAM_LCD_2BYTE_EN (BIT(23)) -#define LCD_CAM_LCD_2BYTE_EN_M (BIT(23)) -#define LCD_CAM_LCD_2BYTE_EN_V 0x1 -#define LCD_CAM_LCD_2BYTE_EN_S 23 +/*description: 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD d +ata is 0~8. .*/ +#define LCD_CAM_LCD_2BYTE_EN (BIT(23)) +#define LCD_CAM_LCD_2BYTE_EN_M (BIT(23)) +#define LCD_CAM_LCD_2BYTE_EN_V 0x1 +#define LCD_CAM_LCD_2BYTE_EN_S 23 /* LCD_CAM_LCD_BYTE_ORDER : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: 1: invert data byte order only valid in 2 byte mode. 0: Not change.*/ -#define LCD_CAM_LCD_BYTE_ORDER (BIT(22)) -#define LCD_CAM_LCD_BYTE_ORDER_M (BIT(22)) -#define LCD_CAM_LCD_BYTE_ORDER_V 0x1 -#define LCD_CAM_LCD_BYTE_ORDER_S 22 +/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/ +#define LCD_CAM_LCD_BYTE_ORDER (BIT(22)) +#define LCD_CAM_LCD_BYTE_ORDER_M (BIT(22)) +#define LCD_CAM_LCD_BYTE_ORDER_V 0x1 +#define LCD_CAM_LCD_BYTE_ORDER_S 22 /* LCD_CAM_LCD_BIT_ORDER : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: 1: Change data bit order change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] - in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/ -#define LCD_CAM_LCD_BIT_ORDER (BIT(21)) -#define LCD_CAM_LCD_BIT_ORDER_M (BIT(21)) -#define LCD_CAM_LCD_BIT_ORDER_V 0x1 -#define LCD_CAM_LCD_BIT_ORDER_S 21 +/*description: 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one b +yte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change..*/ +#define LCD_CAM_LCD_BIT_ORDER (BIT(21)) +#define LCD_CAM_LCD_BIT_ORDER_M (BIT(21)) +#define LCD_CAM_LCD_BIT_ORDER_V 0x1 +#define LCD_CAM_LCD_BIT_ORDER_S 21 /* LCD_CAM_LCD_UPDATE_REG : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: 1: Update LCD registers will be cleared by hardware. 0 : Not care.*/ -#define LCD_CAM_LCD_UPDATE_REG (BIT(20)) -#define LCD_CAM_LCD_UPDATE_REG_M (BIT(20)) -#define LCD_CAM_LCD_UPDATE_REG_V 0x1 -#define LCD_CAM_LCD_UPDATE_REG_S 20 +/*description: 1: Update LCD registers, will be cleared by hardware. 0 : Not care..*/ +#define LCD_CAM_LCD_UPDATE_REG (BIT(20)) +#define LCD_CAM_LCD_UPDATE_REG_M (BIT(20)) +#define LCD_CAM_LCD_UPDATE_REG_V 0x1 +#define LCD_CAM_LCD_UPDATE_REG_S 20 /* LCD_CAM_LCD_8BITS_ORDER : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: 1: invert every two data byte valid in 1 byte mode. 0: Not change.*/ -#define LCD_CAM_LCD_8BITS_ORDER (BIT(19)) -#define LCD_CAM_LCD_8BITS_ORDER_M (BIT(19)) -#define LCD_CAM_LCD_8BITS_ORDER_V 0x1 -#define LCD_CAM_LCD_8BITS_ORDER_S 19 +/*description: 1: invert every two data byte, valid in 1 byte mode. 0: Not change..*/ +#define LCD_CAM_LCD_8BITS_ORDER (BIT(19)) +#define LCD_CAM_LCD_8BITS_ORDER_M (BIT(19)) +#define LCD_CAM_LCD_8BITS_ORDER_V 0x1 +#define LCD_CAM_LCD_8BITS_ORDER_S 19 /* LCD_CAM_LCD_ALWAYS_OUT_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */ -/*description: LCD always output when LCD is in LCD_DOUT state unless reg_lcd_start - is cleared or reg_lcd_reset is set.*/ -#define LCD_CAM_LCD_ALWAYS_OUT_EN (BIT(13)) -#define LCD_CAM_LCD_ALWAYS_OUT_EN_M (BIT(13)) -#define LCD_CAM_LCD_ALWAYS_OUT_EN_V 0x1 -#define LCD_CAM_LCD_ALWAYS_OUT_EN_S 13 +/*description: LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared + or reg_lcd_reset is set..*/ +#define LCD_CAM_LCD_ALWAYS_OUT_EN (BIT(13)) +#define LCD_CAM_LCD_ALWAYS_OUT_EN_M (BIT(13)) +#define LCD_CAM_LCD_ALWAYS_OUT_EN_V 0x1 +#define LCD_CAM_LCD_ALWAYS_OUT_EN_S 13 /* LCD_CAM_LCD_DOUT_CYCLELEN : R/W ;bitpos:[12:0] ;default: 13'h1 ; */ -/*description: The output data cycles minus 1 of LCD module.*/ -#define LCD_CAM_LCD_DOUT_CYCLELEN 0x00001FFF -#define LCD_CAM_LCD_DOUT_CYCLELEN_M ((LCD_CAM_LCD_DOUT_CYCLELEN_V) << (LCD_CAM_LCD_DOUT_CYCLELEN_S)) -#define LCD_CAM_LCD_DOUT_CYCLELEN_V 0x1FFF -#define LCD_CAM_LCD_DOUT_CYCLELEN_S 0 +/*description: The output data cycles minus 1 of LCD module..*/ +#define LCD_CAM_LCD_DOUT_CYCLELEN 0x00001FFF +#define LCD_CAM_LCD_DOUT_CYCLELEN_M ((LCD_CAM_LCD_DOUT_CYCLELEN_V)<<(LCD_CAM_LCD_DOUT_CYCLELEN_S)) +#define LCD_CAM_LCD_DOUT_CYCLELEN_V 0x1FFF +#define LCD_CAM_LCD_DOUT_CYCLELEN_S 0 -#define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x018) +#define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x18) /* LCD_CAM_LCD_CD_IDLE_EDGE : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: The default value of LCD_CD.*/ -#define LCD_CAM_LCD_CD_IDLE_EDGE (BIT(31)) -#define LCD_CAM_LCD_CD_IDLE_EDGE_M (BIT(31)) -#define LCD_CAM_LCD_CD_IDLE_EDGE_V 0x1 -#define LCD_CAM_LCD_CD_IDLE_EDGE_S 31 +/*description: The default value of LCD_CD. .*/ +#define LCD_CAM_LCD_CD_IDLE_EDGE (BIT(31)) +#define LCD_CAM_LCD_CD_IDLE_EDGE_M (BIT(31)) +#define LCD_CAM_LCD_CD_IDLE_EDGE_V 0x1 +#define LCD_CAM_LCD_CD_IDLE_EDGE_S 31 /* LCD_CAM_LCD_CD_CMD_SET : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD - state. 0: LCD_CD = reg_cd_idle_edge.*/ -#define LCD_CAM_LCD_CD_CMD_SET (BIT(30)) -#define LCD_CAM_LCD_CD_CMD_SET_M (BIT(30)) -#define LCD_CAM_LCD_CD_CMD_SET_V 0x1 -#define LCD_CAM_LCD_CD_CMD_SET_S 30 +/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = + reg_cd_idle_edge. .*/ +#define LCD_CAM_LCD_CD_CMD_SET (BIT(30)) +#define LCD_CAM_LCD_CD_CMD_SET_M (BIT(30)) +#define LCD_CAM_LCD_CD_CMD_SET_V 0x1 +#define LCD_CAM_LCD_CD_CMD_SET_S 30 /* LCD_CAM_LCD_CD_DUMMY_SET : R/W ;bitpos:[29] ;default: 1'h0 ; */ -/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY - state. 0: LCD_CD = reg_cd_idle_edge.*/ -#define LCD_CAM_LCD_CD_DUMMY_SET (BIT(29)) -#define LCD_CAM_LCD_CD_DUMMY_SET_M (BIT(29)) -#define LCD_CAM_LCD_CD_DUMMY_SET_V 0x1 -#define LCD_CAM_LCD_CD_DUMMY_SET_S 29 +/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD + = reg_cd_idle_edge. .*/ +#define LCD_CAM_LCD_CD_DUMMY_SET (BIT(29)) +#define LCD_CAM_LCD_CD_DUMMY_SET_M (BIT(29)) +#define LCD_CAM_LCD_CD_DUMMY_SET_V 0x1 +#define LCD_CAM_LCD_CD_DUMMY_SET_S 29 /* LCD_CAM_LCD_CD_DATA_SET : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT - state. 0: LCD_CD = reg_cd_idle_edge.*/ -#define LCD_CAM_LCD_CD_DATA_SET (BIT(28)) -#define LCD_CAM_LCD_CD_DATA_SET_M (BIT(28)) -#define LCD_CAM_LCD_CD_DATA_SET_V 0x1 -#define LCD_CAM_LCD_CD_DATA_SET_S 28 +/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD += reg_cd_idle_edge. .*/ +#define LCD_CAM_LCD_CD_DATA_SET (BIT(28)) +#define LCD_CAM_LCD_CD_DATA_SET_M (BIT(28)) +#define LCD_CAM_LCD_CD_DATA_SET_V 0x1 +#define LCD_CAM_LCD_CD_DATA_SET_S 28 /* LCD_CAM_LCD_AFIFO_RESET : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: LCD AFIFO reset signal.*/ -#define LCD_CAM_LCD_AFIFO_RESET (BIT(27)) -#define LCD_CAM_LCD_AFIFO_RESET_M (BIT(27)) -#define LCD_CAM_LCD_AFIFO_RESET_V 0x1 -#define LCD_CAM_LCD_AFIFO_RESET_S 27 +/*description: LCD AFIFO reset signal..*/ +#define LCD_CAM_LCD_AFIFO_RESET (BIT(27)) +#define LCD_CAM_LCD_AFIFO_RESET_M (BIT(27)) +#define LCD_CAM_LCD_AFIFO_RESET_V 0x1 +#define LCD_CAM_LCD_AFIFO_RESET_S 27 /* LCD_CAM_LCD_BK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: Enable blank region when LCD sends data out. 0: No blank region.*/ -#define LCD_CAM_LCD_BK_EN (BIT(26)) -#define LCD_CAM_LCD_BK_EN_M (BIT(26)) -#define LCD_CAM_LCD_BK_EN_V 0x1 -#define LCD_CAM_LCD_BK_EN_S 26 +/*description: 1: Enable blank region when LCD sends data out. 0: No blank region..*/ +#define LCD_CAM_LCD_BK_EN (BIT(26)) +#define LCD_CAM_LCD_BK_EN_M (BIT(26)) +#define LCD_CAM_LCD_BK_EN_V 0x1 +#define LCD_CAM_LCD_BK_EN_S 26 /* LCD_CAM_LCD_NEXT_FRAME_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: 1: Send the next frame data when the current frame is sent out. - 0: LCD stops when the current frame is sent out.*/ -#define LCD_CAM_LCD_NEXT_FRAME_EN (BIT(25)) -#define LCD_CAM_LCD_NEXT_FRAME_EN_M (BIT(25)) -#define LCD_CAM_LCD_NEXT_FRAME_EN_V 0x1 -#define LCD_CAM_LCD_NEXT_FRAME_EN_S 25 +/*description: 1: Send the next frame data when the current frame is sent out. 0: LCD stops whe +n the current frame is sent out..*/ +#define LCD_CAM_LCD_NEXT_FRAME_EN (BIT(25)) +#define LCD_CAM_LCD_NEXT_FRAME_EN_M (BIT(25)) +#define LCD_CAM_LCD_NEXT_FRAME_EN_V 0x1 +#define LCD_CAM_LCD_NEXT_FRAME_EN_S 25 /* LCD_CAM_LCD_VBK_CYCLELEN : R/W ;bitpos:[24:12] ;default: 13'h0 ; */ -/*description: The vertical back blank region cycle length minus 1 in LCD RGB - mode or the hold time cycle length in LCD non-RGB mode.*/ -#define LCD_CAM_LCD_VBK_CYCLELEN 0x00001FFF -#define LCD_CAM_LCD_VBK_CYCLELEN_M ((LCD_CAM_LCD_VBK_CYCLELEN_V) << (LCD_CAM_LCD_VBK_CYCLELEN_S)) -#define LCD_CAM_LCD_VBK_CYCLELEN_V 0x1FFF -#define LCD_CAM_LCD_VBK_CYCLELEN_S 12 +/*description: The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold + time cycle length in LCD non-RGB mode..*/ +#define LCD_CAM_LCD_VBK_CYCLELEN 0x00001FFF +#define LCD_CAM_LCD_VBK_CYCLELEN_M ((LCD_CAM_LCD_VBK_CYCLELEN_V)<<(LCD_CAM_LCD_VBK_CYCLELEN_S)) +#define LCD_CAM_LCD_VBK_CYCLELEN_V 0x1FFF +#define LCD_CAM_LCD_VBK_CYCLELEN_S 12 /* LCD_CAM_LCD_VFK_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'h3 ; */ -/*description: The setup cycle length minus 1 in LCD non-RGB mode.*/ -#define LCD_CAM_LCD_VFK_CYCLELEN 0x0000003F -#define LCD_CAM_LCD_VFK_CYCLELEN_M ((LCD_CAM_LCD_VFK_CYCLELEN_V) << (LCD_CAM_LCD_VFK_CYCLELEN_S)) -#define LCD_CAM_LCD_VFK_CYCLELEN_V 0x3F -#define LCD_CAM_LCD_VFK_CYCLELEN_S 6 +/*description: The setup cycle length minus 1 in LCD non-RGB mode..*/ +#define LCD_CAM_LCD_VFK_CYCLELEN 0x0000003F +#define LCD_CAM_LCD_VFK_CYCLELEN_M ((LCD_CAM_LCD_VFK_CYCLELEN_V)<<(LCD_CAM_LCD_VFK_CYCLELEN_S)) +#define LCD_CAM_LCD_VFK_CYCLELEN_V 0x3F +#define LCD_CAM_LCD_VFK_CYCLELEN_S 6 /* LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W ;bitpos:[5:1] ;default: 5'd11 ; */ -/*description: The awfull threshold number of lcd_afifo.*/ -#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM 0x0000001F -#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_M ((LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V) << (LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S)) -#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V 0x1F -#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S 1 +/*description: The awfull threshold number of lcd_afifo..*/ +#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM 0x0000001F +#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_M ((LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V)<<(LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S)) +#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V 0x1F +#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S 1 -#define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x01C) +#define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x1C) /* LCD_CAM_LCD_RGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: Enable reg mode input vsync*/ -#define LCD_CAM_LCD_RGB_MODE_EN (BIT(31)) -#define LCD_CAM_LCD_RGB_MODE_EN_M (BIT(31)) -#define LCD_CAM_LCD_RGB_MODE_EN_V 0x1 -#define LCD_CAM_LCD_RGB_MODE_EN_S 31 +/*description: 1: Enable reg mode input vsync.*/ +#define LCD_CAM_LCD_RGB_MODE_EN (BIT(31)) +#define LCD_CAM_LCD_RGB_MODE_EN_M (BIT(31)) +#define LCD_CAM_LCD_RGB_MODE_EN_V 0x1 +#define LCD_CAM_LCD_RGB_MODE_EN_S 31 /* LCD_CAM_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */ -/*description: It is the vertical total height of a frame.*/ -#define LCD_CAM_LCD_VT_HEIGHT 0x000003FF -#define LCD_CAM_LCD_VT_HEIGHT_M ((LCD_CAM_LCD_VT_HEIGHT_V) << (LCD_CAM_LCD_VT_HEIGHT_S)) -#define LCD_CAM_LCD_VT_HEIGHT_V 0x3FF -#define LCD_CAM_LCD_VT_HEIGHT_S 21 +/*description: It is the vertical total height of a frame. .*/ +#define LCD_CAM_LCD_VT_HEIGHT 0x000003FF +#define LCD_CAM_LCD_VT_HEIGHT_M ((LCD_CAM_LCD_VT_HEIGHT_V)<<(LCD_CAM_LCD_VT_HEIGHT_S)) +#define LCD_CAM_LCD_VT_HEIGHT_V 0x3FF +#define LCD_CAM_LCD_VT_HEIGHT_S 21 /* LCD_CAM_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */ -/*description: It is the vertical active height of a frame.*/ -#define LCD_CAM_LCD_VA_HEIGHT 0x000003FF -#define LCD_CAM_LCD_VA_HEIGHT_M ((LCD_CAM_LCD_VA_HEIGHT_V) << (LCD_CAM_LCD_VA_HEIGHT_S)) -#define LCD_CAM_LCD_VA_HEIGHT_V 0x3FF -#define LCD_CAM_LCD_VA_HEIGHT_S 11 +/*description: It is the vertical active height of a frame. .*/ +#define LCD_CAM_LCD_VA_HEIGHT 0x000003FF +#define LCD_CAM_LCD_VA_HEIGHT_M ((LCD_CAM_LCD_VA_HEIGHT_V)<<(LCD_CAM_LCD_VA_HEIGHT_S)) +#define LCD_CAM_LCD_VA_HEIGHT_V 0x3FF +#define LCD_CAM_LCD_VA_HEIGHT_S 11 /* LCD_CAM_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */ -/*description: It is the horizontal blank front porch of a frame.*/ -#define LCD_CAM_LCD_HB_FRONT 0x000007FF -#define LCD_CAM_LCD_HB_FRONT_M ((LCD_CAM_LCD_HB_FRONT_V) << (LCD_CAM_LCD_HB_FRONT_S)) -#define LCD_CAM_LCD_HB_FRONT_V 0x7FF -#define LCD_CAM_LCD_HB_FRONT_S 0 +/*description: It is the horizontal blank front porch of a frame. .*/ +#define LCD_CAM_LCD_HB_FRONT 0x000007FF +#define LCD_CAM_LCD_HB_FRONT_M ((LCD_CAM_LCD_HB_FRONT_V)<<(LCD_CAM_LCD_HB_FRONT_S)) +#define LCD_CAM_LCD_HB_FRONT_V 0x7FF +#define LCD_CAM_LCD_HB_FRONT_S 0 -#define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x020) +#define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x20) /* LCD_CAM_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */ -/*description: It is the horizontal total width of a frame.*/ -#define LCD_CAM_LCD_HT_WIDTH 0x00000FFF -#define LCD_CAM_LCD_HT_WIDTH_M ((LCD_CAM_LCD_HT_WIDTH_V) << (LCD_CAM_LCD_HT_WIDTH_S)) -#define LCD_CAM_LCD_HT_WIDTH_V 0xFFF -#define LCD_CAM_LCD_HT_WIDTH_S 20 +/*description: It is the horizontal total width of a frame. .*/ +#define LCD_CAM_LCD_HT_WIDTH 0x00000FFF +#define LCD_CAM_LCD_HT_WIDTH_M ((LCD_CAM_LCD_HT_WIDTH_V)<<(LCD_CAM_LCD_HT_WIDTH_S)) +#define LCD_CAM_LCD_HT_WIDTH_V 0xFFF +#define LCD_CAM_LCD_HT_WIDTH_S 20 /* LCD_CAM_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */ -/*description: It is the horizontal active width of a frame.*/ -#define LCD_CAM_LCD_HA_WIDTH 0x00000FFF -#define LCD_CAM_LCD_HA_WIDTH_M ((LCD_CAM_LCD_HA_WIDTH_V) << (LCD_CAM_LCD_HA_WIDTH_S)) -#define LCD_CAM_LCD_HA_WIDTH_V 0xFFF -#define LCD_CAM_LCD_HA_WIDTH_S 8 +/*description: It is the horizontal active width of a frame. .*/ +#define LCD_CAM_LCD_HA_WIDTH 0x00000FFF +#define LCD_CAM_LCD_HA_WIDTH_M ((LCD_CAM_LCD_HA_WIDTH_V)<<(LCD_CAM_LCD_HA_WIDTH_S)) +#define LCD_CAM_LCD_HA_WIDTH_V 0xFFF +#define LCD_CAM_LCD_HA_WIDTH_S 8 /* LCD_CAM_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ -/*description: It is the vertical blank front porch of a frame.*/ -#define LCD_CAM_LCD_VB_FRONT 0x000000FF -#define LCD_CAM_LCD_VB_FRONT_M ((LCD_CAM_LCD_VB_FRONT_V) << (LCD_CAM_LCD_VB_FRONT_S)) -#define LCD_CAM_LCD_VB_FRONT_V 0xFF -#define LCD_CAM_LCD_VB_FRONT_S 0 +/*description: It is the vertical blank front porch of a frame. .*/ +#define LCD_CAM_LCD_VB_FRONT 0x000000FF +#define LCD_CAM_LCD_VB_FRONT_M ((LCD_CAM_LCD_VB_FRONT_V)<<(LCD_CAM_LCD_VB_FRONT_S)) +#define LCD_CAM_LCD_VB_FRONT_V 0xFF +#define LCD_CAM_LCD_VB_FRONT_S 0 -#define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x024) +#define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x24) /* LCD_CAM_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ -/*description: It is the position of LCD_HSYNC active pulse in a line.*/ -#define LCD_CAM_LCD_HSYNC_POSITION 0x000000FF -#define LCD_CAM_LCD_HSYNC_POSITION_M ((LCD_CAM_LCD_HSYNC_POSITION_V) << (LCD_CAM_LCD_HSYNC_POSITION_S)) -#define LCD_CAM_LCD_HSYNC_POSITION_V 0xFF -#define LCD_CAM_LCD_HSYNC_POSITION_S 24 +/*description: It is the position of LCD_HSYNC active pulse in a line. .*/ +#define LCD_CAM_LCD_HSYNC_POSITION 0x000000FF +#define LCD_CAM_LCD_HSYNC_POSITION_M ((LCD_CAM_LCD_HSYNC_POSITION_V)<<(LCD_CAM_LCD_HSYNC_POSITION_S)) +#define LCD_CAM_LCD_HSYNC_POSITION_V 0xFF +#define LCD_CAM_LCD_HSYNC_POSITION_S 24 /* LCD_CAM_LCD_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: It is the idle value of LCD_HSYNC.*/ -#define LCD_CAM_LCD_HSYNC_IDLE_POL (BIT(23)) -#define LCD_CAM_LCD_HSYNC_IDLE_POL_M (BIT(23)) -#define LCD_CAM_LCD_HSYNC_IDLE_POL_V 0x1 -#define LCD_CAM_LCD_HSYNC_IDLE_POL_S 23 +/*description: It is the idle value of LCD_HSYNC. .*/ +#define LCD_CAM_LCD_HSYNC_IDLE_POL (BIT(23)) +#define LCD_CAM_LCD_HSYNC_IDLE_POL_M (BIT(23)) +#define LCD_CAM_LCD_HSYNC_IDLE_POL_V 0x1 +#define LCD_CAM_LCD_HSYNC_IDLE_POL_S 23 /* LCD_CAM_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */ -/*description: It is the position of LCD_HSYNC active pulse in a line.*/ -#define LCD_CAM_LCD_HSYNC_WIDTH 0x0000007F -#define LCD_CAM_LCD_HSYNC_WIDTH_M ((LCD_CAM_LCD_HSYNC_WIDTH_V) << (LCD_CAM_LCD_HSYNC_WIDTH_S)) -#define LCD_CAM_LCD_HSYNC_WIDTH_V 0x7F -#define LCD_CAM_LCD_HSYNC_WIDTH_S 16 +/*description: It is the position of LCD_HSYNC active pulse in a line. .*/ +#define LCD_CAM_LCD_HSYNC_WIDTH 0x0000007F +#define LCD_CAM_LCD_HSYNC_WIDTH_M ((LCD_CAM_LCD_HSYNC_WIDTH_V)<<(LCD_CAM_LCD_HSYNC_WIDTH_S)) +#define LCD_CAM_LCD_HSYNC_WIDTH_V 0x7F +#define LCD_CAM_LCD_HSYNC_WIDTH_S 16 /* LCD_CAM_LCD_HS_BLANK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB - mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode.*/ -#define LCD_CAM_LCD_HS_BLANK_EN (BIT(9)) -#define LCD_CAM_LCD_HS_BLANK_EN_M (BIT(9)) -#define LCD_CAM_LCD_HS_BLANK_EN_V 0x1 -#define LCD_CAM_LCD_HS_BLANK_EN_S 9 +/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSY +NC pulse is valid only in active region lines in RGB mode. .*/ +#define LCD_CAM_LCD_HS_BLANK_EN (BIT(9)) +#define LCD_CAM_LCD_HS_BLANK_EN_M (BIT(9)) +#define LCD_CAM_LCD_HS_BLANK_EN_V 0x1 +#define LCD_CAM_LCD_HS_BLANK_EN_S 9 /* LCD_CAM_LCD_DE_IDLE_POL : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: It is the idle value of LCD_DE.*/ -#define LCD_CAM_LCD_DE_IDLE_POL (BIT(8)) -#define LCD_CAM_LCD_DE_IDLE_POL_M (BIT(8)) -#define LCD_CAM_LCD_DE_IDLE_POL_V 0x1 -#define LCD_CAM_LCD_DE_IDLE_POL_S 8 +/*description: It is the idle value of LCD_DE. .*/ +#define LCD_CAM_LCD_DE_IDLE_POL (BIT(8)) +#define LCD_CAM_LCD_DE_IDLE_POL_M (BIT(8)) +#define LCD_CAM_LCD_DE_IDLE_POL_V 0x1 +#define LCD_CAM_LCD_DE_IDLE_POL_S 8 /* LCD_CAM_LCD_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: It is the idle value of LCD_VSYNC.*/ -#define LCD_CAM_LCD_VSYNC_IDLE_POL (BIT(7)) -#define LCD_CAM_LCD_VSYNC_IDLE_POL_M (BIT(7)) -#define LCD_CAM_LCD_VSYNC_IDLE_POL_V 0x1 -#define LCD_CAM_LCD_VSYNC_IDLE_POL_S 7 +/*description: It is the idle value of LCD_VSYNC. .*/ +#define LCD_CAM_LCD_VSYNC_IDLE_POL (BIT(7)) +#define LCD_CAM_LCD_VSYNC_IDLE_POL_M (BIT(7)) +#define LCD_CAM_LCD_VSYNC_IDLE_POL_V 0x1 +#define LCD_CAM_LCD_VSYNC_IDLE_POL_S 7 /* LCD_CAM_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ -/*description: It is the position of LCD_VSYNC active pulse in a line.*/ -#define LCD_CAM_LCD_VSYNC_WIDTH 0x0000007F -#define LCD_CAM_LCD_VSYNC_WIDTH_M ((LCD_CAM_LCD_VSYNC_WIDTH_V) << (LCD_CAM_LCD_VSYNC_WIDTH_S)) -#define LCD_CAM_LCD_VSYNC_WIDTH_V 0x7F -#define LCD_CAM_LCD_VSYNC_WIDTH_S 0 +/*description: It is the position of LCD_VSYNC active pulse in a line. .*/ +#define LCD_CAM_LCD_VSYNC_WIDTH 0x0000007F +#define LCD_CAM_LCD_VSYNC_WIDTH_M ((LCD_CAM_LCD_VSYNC_WIDTH_V)<<(LCD_CAM_LCD_VSYNC_WIDTH_S)) +#define LCD_CAM_LCD_VSYNC_WIDTH_V 0x7F +#define LCD_CAM_LCD_VSYNC_WIDTH_S 0 -#define LCD_CAM_LCD_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x028) +#define LCD_CAM_LCD_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x28) /* LCD_CAM_LCD_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The LCD write command value.*/ -#define LCD_CAM_LCD_CMD_VALUE 0xFFFFFFFF -#define LCD_CAM_LCD_CMD_VALUE_M ((LCD_CAM_LCD_CMD_VALUE_V) << (LCD_CAM_LCD_CMD_VALUE_S)) -#define LCD_CAM_LCD_CMD_VALUE_V 0xFFFFFFFF -#define LCD_CAM_LCD_CMD_VALUE_S 0 +/*description: The LCD write command value..*/ +#define LCD_CAM_LCD_CMD_VALUE 0xFFFFFFFF +#define LCD_CAM_LCD_CMD_VALUE_M ((LCD_CAM_LCD_CMD_VALUE_V)<<(LCD_CAM_LCD_CMD_VALUE_S)) +#define LCD_CAM_LCD_CMD_VALUE_V 0xFFFFFFFF +#define LCD_CAM_LCD_CMD_VALUE_S 0 -#define LCD_CAM_LCD_DLY_MODE_REG (DR_REG_LCD_CAM_BASE + 0x030) +#define LCD_CAM_LCD_DLY_MODE_REG (DR_REG_LCD_CAM_BASE + 0x30) /* LCD_CAM_LCD_VSYNC_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK*/ -#define LCD_CAM_LCD_VSYNC_MODE 0x00000003 -#define LCD_CAM_LCD_VSYNC_MODE_M ((LCD_CAM_LCD_VSYNC_MODE_V) << (LCD_CAM_LCD_VSYNC_MODE_S)) -#define LCD_CAM_LCD_VSYNC_MODE_V 0x3 -#define LCD_CAM_LCD_VSYNC_MODE_S 6 +/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_LCD_VSYNC_MODE 0x00000003 +#define LCD_CAM_LCD_VSYNC_MODE_M ((LCD_CAM_LCD_VSYNC_MODE_V)<<(LCD_CAM_LCD_VSYNC_MODE_S)) +#define LCD_CAM_LCD_VSYNC_MODE_V 0x3 +#define LCD_CAM_LCD_VSYNC_MODE_S 6 /* LCD_CAM_LCD_HSYNC_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK*/ -#define LCD_CAM_LCD_HSYNC_MODE 0x00000003 -#define LCD_CAM_LCD_HSYNC_MODE_M ((LCD_CAM_LCD_HSYNC_MODE_V) << (LCD_CAM_LCD_HSYNC_MODE_S)) -#define LCD_CAM_LCD_HSYNC_MODE_V 0x3 -#define LCD_CAM_LCD_HSYNC_MODE_S 4 +/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_LCD_HSYNC_MODE 0x00000003 +#define LCD_CAM_LCD_HSYNC_MODE_M ((LCD_CAM_LCD_HSYNC_MODE_V)<<(LCD_CAM_LCD_HSYNC_MODE_S)) +#define LCD_CAM_LCD_HSYNC_MODE_V 0x3 +#define LCD_CAM_LCD_HSYNC_MODE_S 4 /* LCD_CAM_LCD_DE_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: The output LCD_DE is delayed by module clock LCD_CLK*/ -#define LCD_CAM_LCD_DE_MODE 0x00000003 -#define LCD_CAM_LCD_DE_MODE_M ((LCD_CAM_LCD_DE_MODE_V) << (LCD_CAM_LCD_DE_MODE_S)) -#define LCD_CAM_LCD_DE_MODE_V 0x3 -#define LCD_CAM_LCD_DE_MODE_S 2 +/*description: The output LCD_DE is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_LCD_DE_MODE 0x00000003 +#define LCD_CAM_LCD_DE_MODE_M ((LCD_CAM_LCD_DE_MODE_V)<<(LCD_CAM_LCD_DE_MODE_S)) +#define LCD_CAM_LCD_DE_MODE_V 0x3 +#define LCD_CAM_LCD_DE_MODE_S 2 /* LCD_CAM_LCD_CD_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The output LCD_CD is delayed by module clock LCD_CLK*/ -#define LCD_CAM_LCD_CD_MODE 0x00000003 -#define LCD_CAM_LCD_CD_MODE_M ((LCD_CAM_LCD_CD_MODE_V) << (LCD_CAM_LCD_CD_MODE_S)) -#define LCD_CAM_LCD_CD_MODE_V 0x3 -#define LCD_CAM_LCD_CD_MODE_S 0 +/*description: The output LCD_CD is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_LCD_CD_MODE 0x00000003 +#define LCD_CAM_LCD_CD_MODE_M ((LCD_CAM_LCD_CD_MODE_V)<<(LCD_CAM_LCD_CD_MODE_S)) +#define LCD_CAM_LCD_CD_MODE_V 0x3 +#define LCD_CAM_LCD_CD_MODE_S 0 -#define LCD_CAM_LCD_DATA_DOUT_MODE_REG (DR_REG_LCD_CAM_BASE + 0x038) +#define LCD_CAM_LCD_DATA_DOUT_MODE_REG (DR_REG_LCD_CAM_BASE + 0x38) /* LCD_CAM_DOUT15_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT15_MODE 0x00000003 -#define LCD_CAM_DOUT15_MODE_M ((LCD_CAM_DOUT15_MODE_V) << (LCD_CAM_DOUT15_MODE_S)) -#define LCD_CAM_DOUT15_MODE_V 0x3 -#define LCD_CAM_DOUT15_MODE_S 30 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT15_MODE 0x00000003 +#define LCD_CAM_DOUT15_MODE_M ((LCD_CAM_DOUT15_MODE_V)<<(LCD_CAM_DOUT15_MODE_S)) +#define LCD_CAM_DOUT15_MODE_V 0x3 +#define LCD_CAM_DOUT15_MODE_S 30 /* LCD_CAM_DOUT14_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT14_MODE 0x00000003 -#define LCD_CAM_DOUT14_MODE_M ((LCD_CAM_DOUT14_MODE_V) << (LCD_CAM_DOUT14_MODE_S)) -#define LCD_CAM_DOUT14_MODE_V 0x3 -#define LCD_CAM_DOUT14_MODE_S 28 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT14_MODE 0x00000003 +#define LCD_CAM_DOUT14_MODE_M ((LCD_CAM_DOUT14_MODE_V)<<(LCD_CAM_DOUT14_MODE_S)) +#define LCD_CAM_DOUT14_MODE_V 0x3 +#define LCD_CAM_DOUT14_MODE_S 28 /* LCD_CAM_DOUT13_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT13_MODE 0x00000003 -#define LCD_CAM_DOUT13_MODE_M ((LCD_CAM_DOUT13_MODE_V) << (LCD_CAM_DOUT13_MODE_S)) -#define LCD_CAM_DOUT13_MODE_V 0x3 -#define LCD_CAM_DOUT13_MODE_S 26 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT13_MODE 0x00000003 +#define LCD_CAM_DOUT13_MODE_M ((LCD_CAM_DOUT13_MODE_V)<<(LCD_CAM_DOUT13_MODE_S)) +#define LCD_CAM_DOUT13_MODE_V 0x3 +#define LCD_CAM_DOUT13_MODE_S 26 /* LCD_CAM_DOUT12_MODE : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT12_MODE 0x00000003 -#define LCD_CAM_DOUT12_MODE_M ((LCD_CAM_DOUT12_MODE_V) << (LCD_CAM_DOUT12_MODE_S)) -#define LCD_CAM_DOUT12_MODE_V 0x3 -#define LCD_CAM_DOUT12_MODE_S 24 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT12_MODE 0x00000003 +#define LCD_CAM_DOUT12_MODE_M ((LCD_CAM_DOUT12_MODE_V)<<(LCD_CAM_DOUT12_MODE_S)) +#define LCD_CAM_DOUT12_MODE_V 0x3 +#define LCD_CAM_DOUT12_MODE_S 24 /* LCD_CAM_DOUT11_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT11_MODE 0x00000003 -#define LCD_CAM_DOUT11_MODE_M ((LCD_CAM_DOUT11_MODE_V) << (LCD_CAM_DOUT11_MODE_S)) -#define LCD_CAM_DOUT11_MODE_V 0x3 -#define LCD_CAM_DOUT11_MODE_S 22 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT11_MODE 0x00000003 +#define LCD_CAM_DOUT11_MODE_M ((LCD_CAM_DOUT11_MODE_V)<<(LCD_CAM_DOUT11_MODE_S)) +#define LCD_CAM_DOUT11_MODE_V 0x3 +#define LCD_CAM_DOUT11_MODE_S 22 /* LCD_CAM_DOUT10_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT10_MODE 0x00000003 -#define LCD_CAM_DOUT10_MODE_M ((LCD_CAM_DOUT10_MODE_V) << (LCD_CAM_DOUT10_MODE_S)) -#define LCD_CAM_DOUT10_MODE_V 0x3 -#define LCD_CAM_DOUT10_MODE_S 20 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT10_MODE 0x00000003 +#define LCD_CAM_DOUT10_MODE_M ((LCD_CAM_DOUT10_MODE_V)<<(LCD_CAM_DOUT10_MODE_S)) +#define LCD_CAM_DOUT10_MODE_V 0x3 +#define LCD_CAM_DOUT10_MODE_S 20 /* LCD_CAM_DOUT9_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT9_MODE 0x00000003 -#define LCD_CAM_DOUT9_MODE_M ((LCD_CAM_DOUT9_MODE_V) << (LCD_CAM_DOUT9_MODE_S)) -#define LCD_CAM_DOUT9_MODE_V 0x3 -#define LCD_CAM_DOUT9_MODE_S 18 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT9_MODE 0x00000003 +#define LCD_CAM_DOUT9_MODE_M ((LCD_CAM_DOUT9_MODE_V)<<(LCD_CAM_DOUT9_MODE_S)) +#define LCD_CAM_DOUT9_MODE_V 0x3 +#define LCD_CAM_DOUT9_MODE_S 18 /* LCD_CAM_DOUT8_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT8_MODE 0x00000003 -#define LCD_CAM_DOUT8_MODE_M ((LCD_CAM_DOUT8_MODE_V) << (LCD_CAM_DOUT8_MODE_S)) -#define LCD_CAM_DOUT8_MODE_V 0x3 -#define LCD_CAM_DOUT8_MODE_S 16 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT8_MODE 0x00000003 +#define LCD_CAM_DOUT8_MODE_M ((LCD_CAM_DOUT8_MODE_V)<<(LCD_CAM_DOUT8_MODE_S)) +#define LCD_CAM_DOUT8_MODE_V 0x3 +#define LCD_CAM_DOUT8_MODE_S 16 /* LCD_CAM_DOUT7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT7_MODE 0x00000003 -#define LCD_CAM_DOUT7_MODE_M ((LCD_CAM_DOUT7_MODE_V) << (LCD_CAM_DOUT7_MODE_S)) -#define LCD_CAM_DOUT7_MODE_V 0x3 -#define LCD_CAM_DOUT7_MODE_S 14 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT7_MODE 0x00000003 +#define LCD_CAM_DOUT7_MODE_M ((LCD_CAM_DOUT7_MODE_V)<<(LCD_CAM_DOUT7_MODE_S)) +#define LCD_CAM_DOUT7_MODE_V 0x3 +#define LCD_CAM_DOUT7_MODE_S 14 /* LCD_CAM_DOUT6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT6_MODE 0x00000003 -#define LCD_CAM_DOUT6_MODE_M ((LCD_CAM_DOUT6_MODE_V) << (LCD_CAM_DOUT6_MODE_S)) -#define LCD_CAM_DOUT6_MODE_V 0x3 -#define LCD_CAM_DOUT6_MODE_S 12 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT6_MODE 0x00000003 +#define LCD_CAM_DOUT6_MODE_M ((LCD_CAM_DOUT6_MODE_V)<<(LCD_CAM_DOUT6_MODE_S)) +#define LCD_CAM_DOUT6_MODE_V 0x3 +#define LCD_CAM_DOUT6_MODE_S 12 /* LCD_CAM_DOUT5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT5_MODE 0x00000003 -#define LCD_CAM_DOUT5_MODE_M ((LCD_CAM_DOUT5_MODE_V) << (LCD_CAM_DOUT5_MODE_S)) -#define LCD_CAM_DOUT5_MODE_V 0x3 -#define LCD_CAM_DOUT5_MODE_S 10 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT5_MODE 0x00000003 +#define LCD_CAM_DOUT5_MODE_M ((LCD_CAM_DOUT5_MODE_V)<<(LCD_CAM_DOUT5_MODE_S)) +#define LCD_CAM_DOUT5_MODE_V 0x3 +#define LCD_CAM_DOUT5_MODE_S 10 /* LCD_CAM_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT4_MODE 0x00000003 -#define LCD_CAM_DOUT4_MODE_M ((LCD_CAM_DOUT4_MODE_V) << (LCD_CAM_DOUT4_MODE_S)) -#define LCD_CAM_DOUT4_MODE_V 0x3 -#define LCD_CAM_DOUT4_MODE_S 8 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT4_MODE 0x00000003 +#define LCD_CAM_DOUT4_MODE_M ((LCD_CAM_DOUT4_MODE_V)<<(LCD_CAM_DOUT4_MODE_S)) +#define LCD_CAM_DOUT4_MODE_V 0x3 +#define LCD_CAM_DOUT4_MODE_S 8 /* LCD_CAM_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT3_MODE 0x00000003 -#define LCD_CAM_DOUT3_MODE_M ((LCD_CAM_DOUT3_MODE_V) << (LCD_CAM_DOUT3_MODE_S)) -#define LCD_CAM_DOUT3_MODE_V 0x3 -#define LCD_CAM_DOUT3_MODE_S 6 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT3_MODE 0x00000003 +#define LCD_CAM_DOUT3_MODE_M ((LCD_CAM_DOUT3_MODE_V)<<(LCD_CAM_DOUT3_MODE_S)) +#define LCD_CAM_DOUT3_MODE_V 0x3 +#define LCD_CAM_DOUT3_MODE_S 6 /* LCD_CAM_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT2_MODE 0x00000003 -#define LCD_CAM_DOUT2_MODE_M ((LCD_CAM_DOUT2_MODE_V) << (LCD_CAM_DOUT2_MODE_S)) -#define LCD_CAM_DOUT2_MODE_V 0x3 -#define LCD_CAM_DOUT2_MODE_S 4 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT2_MODE 0x00000003 +#define LCD_CAM_DOUT2_MODE_M ((LCD_CAM_DOUT2_MODE_V)<<(LCD_CAM_DOUT2_MODE_S)) +#define LCD_CAM_DOUT2_MODE_V 0x3 +#define LCD_CAM_DOUT2_MODE_S 4 /* LCD_CAM_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT1_MODE 0x00000003 -#define LCD_CAM_DOUT1_MODE_M ((LCD_CAM_DOUT1_MODE_V) << (LCD_CAM_DOUT1_MODE_S)) -#define LCD_CAM_DOUT1_MODE_V 0x3 -#define LCD_CAM_DOUT1_MODE_S 2 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT1_MODE 0x00000003 +#define LCD_CAM_DOUT1_MODE_M ((LCD_CAM_DOUT1_MODE_V)<<(LCD_CAM_DOUT1_MODE_S)) +#define LCD_CAM_DOUT1_MODE_V 0x3 +#define LCD_CAM_DOUT1_MODE_S 2 /* LCD_CAM_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The output data bit $n is delayed by module clock LCD_CLK*/ -#define LCD_CAM_DOUT0_MODE 0x00000003 -#define LCD_CAM_DOUT0_MODE_M ((LCD_CAM_DOUT0_MODE_V) << (LCD_CAM_DOUT0_MODE_S)) -#define LCD_CAM_DOUT0_MODE_V 0x3 -#define LCD_CAM_DOUT0_MODE_S 0 +/*description: The output data bit $n is delayed by module clock LCD_CLK.*/ +#define LCD_CAM_DOUT0_MODE 0x00000003 +#define LCD_CAM_DOUT0_MODE_M ((LCD_CAM_DOUT0_MODE_V)<<(LCD_CAM_DOUT0_MODE_S)) +#define LCD_CAM_DOUT0_MODE_V 0x3 +#define LCD_CAM_DOUT0_MODE_S 0 -#define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x064) +#define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x64) /* LCD_CAM_CAM_HS_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for Camera line interrupt.*/ -#define LCD_CAM_CAM_HS_INT_ENA (BIT(3)) -#define LCD_CAM_CAM_HS_INT_ENA_M (BIT(3)) -#define LCD_CAM_CAM_HS_INT_ENA_V 0x1 -#define LCD_CAM_CAM_HS_INT_ENA_S 3 +/*description: The enable bit for Camera line interrupt..*/ +#define LCD_CAM_CAM_HS_INT_ENA (BIT(3)) +#define LCD_CAM_CAM_HS_INT_ENA_M (BIT(3)) +#define LCD_CAM_CAM_HS_INT_ENA_V 0x1 +#define LCD_CAM_CAM_HS_INT_ENA_S 3 /* LCD_CAM_CAM_VSYNC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for Camera frame end interrupt.*/ -#define LCD_CAM_CAM_VSYNC_INT_ENA (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_ENA_M (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_ENA_V 0x1 -#define LCD_CAM_CAM_VSYNC_INT_ENA_S 2 +/*description: The enable bit for Camera frame end interrupt..*/ +#define LCD_CAM_CAM_VSYNC_INT_ENA (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_ENA_M (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_ENA_V 0x1 +#define LCD_CAM_CAM_VSYNC_INT_ENA_S 2 /* LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for lcd transfer end interrupt.*/ -#define LCD_CAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V 0x1 -#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S 1 +/*description: The enable bit for lcd transfer end interrupt..*/ +#define LCD_CAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V 0x1 +#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S 1 /* LCD_CAM_LCD_VSYNC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for LCD frame end interrupt.*/ -#define LCD_CAM_LCD_VSYNC_INT_ENA (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_ENA_M (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_ENA_V 0x1 -#define LCD_CAM_LCD_VSYNC_INT_ENA_S 0 +/*description: The enable bit for LCD frame end interrupt..*/ +#define LCD_CAM_LCD_VSYNC_INT_ENA (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_ENA_M (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_ENA_V 0x1 +#define LCD_CAM_LCD_VSYNC_INT_ENA_S 0 -#define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x068) +#define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x68) /* LCD_CAM_CAM_HS_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw bit for Camera line interrupt.*/ -#define LCD_CAM_CAM_HS_INT_RAW (BIT(3)) -#define LCD_CAM_CAM_HS_INT_RAW_M (BIT(3)) -#define LCD_CAM_CAM_HS_INT_RAW_V 0x1 -#define LCD_CAM_CAM_HS_INT_RAW_S 3 +/*description: The raw bit for Camera line interrupt..*/ +#define LCD_CAM_CAM_HS_INT_RAW (BIT(3)) +#define LCD_CAM_CAM_HS_INT_RAW_M (BIT(3)) +#define LCD_CAM_CAM_HS_INT_RAW_V 0x1 +#define LCD_CAM_CAM_HS_INT_RAW_S 3 /* LCD_CAM_CAM_VSYNC_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw bit for Camera frame end interrupt.*/ -#define LCD_CAM_CAM_VSYNC_INT_RAW (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_RAW_M (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_RAW_V 0x1 -#define LCD_CAM_CAM_VSYNC_INT_RAW_S 2 +/*description: The raw bit for Camera frame end interrupt..*/ +#define LCD_CAM_CAM_VSYNC_INT_RAW (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_RAW_M (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_RAW_V 0x1 +#define LCD_CAM_CAM_VSYNC_INT_RAW_S 2 /* LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit for lcd transfer end interrupt.*/ -#define LCD_CAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V 0x1 -#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S 1 +/*description: The raw bit for lcd transfer end interrupt..*/ +#define LCD_CAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V 0x1 +#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S 1 /* LCD_CAM_LCD_VSYNC_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit for LCD frame end interrupt.*/ -#define LCD_CAM_LCD_VSYNC_INT_RAW (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_RAW_M (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_RAW_V 0x1 -#define LCD_CAM_LCD_VSYNC_INT_RAW_S 0 +/*description: The raw bit for LCD frame end interrupt..*/ +#define LCD_CAM_LCD_VSYNC_INT_RAW (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_RAW_M (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_RAW_V 0x1 +#define LCD_CAM_LCD_VSYNC_INT_RAW_S 0 -#define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x06C) +#define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x6C) /* LCD_CAM_CAM_HS_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The status bit for Camera transfer end interrupt.*/ -#define LCD_CAM_CAM_HS_INT_ST (BIT(3)) -#define LCD_CAM_CAM_HS_INT_ST_M (BIT(3)) -#define LCD_CAM_CAM_HS_INT_ST_V 0x1 -#define LCD_CAM_CAM_HS_INT_ST_S 3 +/*description: The status bit for Camera transfer end interrupt..*/ +#define LCD_CAM_CAM_HS_INT_ST (BIT(3)) +#define LCD_CAM_CAM_HS_INT_ST_M (BIT(3)) +#define LCD_CAM_CAM_HS_INT_ST_V 0x1 +#define LCD_CAM_CAM_HS_INT_ST_S 3 /* LCD_CAM_CAM_VSYNC_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The status bit for Camera frame end interrupt.*/ -#define LCD_CAM_CAM_VSYNC_INT_ST (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_ST_M (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_ST_V 0x1 -#define LCD_CAM_CAM_VSYNC_INT_ST_S 2 +/*description: The status bit for Camera frame end interrupt..*/ +#define LCD_CAM_CAM_VSYNC_INT_ST (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_ST_M (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_ST_V 0x1 +#define LCD_CAM_CAM_VSYNC_INT_ST_S 2 /* LCD_CAM_LCD_TRANS_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status bit for lcd transfer end interrupt.*/ -#define LCD_CAM_LCD_TRANS_DONE_INT_ST (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V 0x1 -#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S 1 +/*description: The status bit for lcd transfer end interrupt..*/ +#define LCD_CAM_LCD_TRANS_DONE_INT_ST (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V 0x1 +#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S 1 /* LCD_CAM_LCD_VSYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status bit for LCD frame end interrupt.*/ -#define LCD_CAM_LCD_VSYNC_INT_ST (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_ST_M (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_ST_V 0x1 -#define LCD_CAM_LCD_VSYNC_INT_ST_S 0 +/*description: The status bit for LCD frame end interrupt..*/ +#define LCD_CAM_LCD_VSYNC_INT_ST (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_ST_M (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_ST_V 0x1 +#define LCD_CAM_LCD_VSYNC_INT_ST_S 0 -#define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x070) +#define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x70) /* LCD_CAM_CAM_HS_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The clear bit for Camera line interrupt.*/ -#define LCD_CAM_CAM_HS_INT_CLR (BIT(3)) -#define LCD_CAM_CAM_HS_INT_CLR_M (BIT(3)) -#define LCD_CAM_CAM_HS_INT_CLR_V 0x1 -#define LCD_CAM_CAM_HS_INT_CLR_S 3 +/*description: The clear bit for Camera line interrupt..*/ +#define LCD_CAM_CAM_HS_INT_CLR (BIT(3)) +#define LCD_CAM_CAM_HS_INT_CLR_M (BIT(3)) +#define LCD_CAM_CAM_HS_INT_CLR_V 0x1 +#define LCD_CAM_CAM_HS_INT_CLR_S 3 /* LCD_CAM_CAM_VSYNC_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The clear bit for Camera frame end interrupt.*/ -#define LCD_CAM_CAM_VSYNC_INT_CLR (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_CLR_M (BIT(2)) -#define LCD_CAM_CAM_VSYNC_INT_CLR_V 0x1 -#define LCD_CAM_CAM_VSYNC_INT_CLR_S 2 +/*description: The clear bit for Camera frame end interrupt..*/ +#define LCD_CAM_CAM_VSYNC_INT_CLR (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_CLR_M (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_CLR_V 0x1 +#define LCD_CAM_CAM_VSYNC_INT_CLR_S 2 /* LCD_CAM_LCD_TRANS_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear bit for lcd transfer end interrupt.*/ -#define LCD_CAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M (BIT(1)) -#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V 0x1 -#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S 1 +/*description: The clear bit for lcd transfer end interrupt..*/ +#define LCD_CAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V 0x1 +#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S 1 /* LCD_CAM_LCD_VSYNC_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear bit for LCD frame end interrupt.*/ -#define LCD_CAM_LCD_VSYNC_INT_CLR (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_CLR_M (BIT(0)) -#define LCD_CAM_LCD_VSYNC_INT_CLR_V 0x1 -#define LCD_CAM_LCD_VSYNC_INT_CLR_S 0 +/*description: The clear bit for LCD frame end interrupt..*/ +#define LCD_CAM_LCD_VSYNC_INT_CLR (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_CLR_M (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_CLR_V 0x1 +#define LCD_CAM_LCD_VSYNC_INT_CLR_S 0 -#define LCD_CAM_LC_DATE_REG (DR_REG_LCD_CAM_BASE + 0x0FC) +#define LCD_CAM_LC_REG_DATE_REG (DR_REG_LCD_CAM_BASE + 0xFC) /* LCD_CAM_LC_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */ -/*description: LCD_CAM version control register*/ -#define LCD_CAM_LC_DATE 0x0FFFFFFF -#define LCD_CAM_LC_DATE_M ((LCD_CAM_LC_DATE_V) << (LCD_CAM_LC_DATE_S)) -#define LCD_CAM_LC_DATE_V 0xFFFFFFF -#define LCD_CAM_LC_DATE_S 0 +/*description: LCD_CAM version control register.*/ +#define LCD_CAM_LC_DATE 0x0FFFFFFF +#define LCD_CAM_LC_DATE_M ((LCD_CAM_LC_DATE_V)<<(LCD_CAM_LC_DATE_S)) +#define LCD_CAM_LC_DATE_V 0xFFFFFFF +#define LCD_CAM_LC_DATE_S 0 + #ifdef __cplusplus } #endif + + + +#endif /*_SOC_LCD_CAM_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/mcpwm_reg.h b/components/soc/esp32s3/include/soc/mcpwm_reg.h index 1edb7c5774..0b3675d66d 100644 --- a/components/soc/esp32s3/include/soc/mcpwm_reg.h +++ b/components/soc/esp32s3/include/soc/mcpwm_reg.h @@ -16,2888 +16,2885 @@ #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000)) - -#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000) +#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0) /* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define MCPWM_CLK_PRESCALE 0x000000FF -#define MCPWM_CLK_PRESCALE_M ((MCPWM_CLK_PRESCALE_V) << (MCPWM_CLK_PRESCALE_S)) -#define MCPWM_CLK_PRESCALE_V 0xFF -#define MCPWM_CLK_PRESCALE_S 0 +/*description: .*/ +#define MCPWM_CLK_PRESCALE 0x000000FF +#define MCPWM_CLK_PRESCALE_M ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S)) +#define MCPWM_CLK_PRESCALE_V 0xFF +#define MCPWM_CLK_PRESCALE_S 0 -#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0004) +#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4) /* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: 0: immediate 1: eqz 2: sync 3: eqz | sync*/ -#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER0_PERIOD_UPMETHOD_M ((MCPWM_TIMER0_PERIOD_UPMETHOD_V) << (MCPWM_TIMER0_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 +/*description: 0: immediate, 1: eqz, 2: sync, 3: eqz | sync.*/ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 /* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: */ -#define MCPWM_TIMER0_PERIOD 0x0000FFFF -#define MCPWM_TIMER0_PERIOD_M ((MCPWM_TIMER0_PERIOD_V) << (MCPWM_TIMER0_PERIOD_S)) -#define MCPWM_TIMER0_PERIOD_V 0xFFFF -#define MCPWM_TIMER0_PERIOD_S 8 +/*description: .*/ +#define MCPWM_TIMER0_PERIOD 0x0000FFFF +#define MCPWM_TIMER0_PERIOD_M ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S)) +#define MCPWM_TIMER0_PERIOD_V 0xFFFF +#define MCPWM_TIMER0_PERIOD_S 8 /* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_PRESCALE 0x000000FF -#define MCPWM_TIMER0_PRESCALE_M ((MCPWM_TIMER0_PRESCALE_V) << (MCPWM_TIMER0_PRESCALE_S)) -#define MCPWM_TIMER0_PRESCALE_V 0xFF -#define MCPWM_TIMER0_PRESCALE_S 0 +/*description: .*/ +#define MCPWM_TIMER0_PRESCALE 0x000000FF +#define MCPWM_TIMER0_PRESCALE_M ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S)) +#define MCPWM_TIMER0_PRESCALE_V 0xFF +#define MCPWM_TIMER0_PRESCALE_S 0 -#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0008) +#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8) /* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: 0: freeze 1: inc 2: dec 3: up-down*/ -#define MCPWM_TIMER0_MOD 0x00000003 -#define MCPWM_TIMER0_MOD_M ((MCPWM_TIMER0_MOD_V) << (MCPWM_TIMER0_MOD_S)) -#define MCPWM_TIMER0_MOD_V 0x3 -#define MCPWM_TIMER0_MOD_S 3 +/*description: 0: freeze, 1: inc, 2: dec, 3: up-down.*/ +#define MCPWM_TIMER0_MOD 0x00000003 +#define MCPWM_TIMER0_MOD_M ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S)) +#define MCPWM_TIMER0_MOD_V 0x3 +#define MCPWM_TIMER0_MOD_S 3 /* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: 0: stop @ eqz 1: stop @ eqp 2: free run 3: start and stop - @ next eqz 4: start and stop @ next eqp*/ -#define MCPWM_TIMER0_START 0x00000007 -#define MCPWM_TIMER0_START_M ((MCPWM_TIMER0_START_V) << (MCPWM_TIMER0_START_S)) -#define MCPWM_TIMER0_START_V 0x7 -#define MCPWM_TIMER0_START_S 0 +/*description: 0: stop @ eqz, 1: stop @ eqp, 2: free run, 3: start and stop @ next eqz, 4: star +t and stop @ next eqp,.*/ +#define MCPWM_TIMER0_START 0x00000007 +#define MCPWM_TIMER0_START_M ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S)) +#define MCPWM_TIMER0_START_V 0x7 +#define MCPWM_TIMER0_START_S 0 -#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x000c) +#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xC) /* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: */ -#define MCPWM_TIMER0_PHASE 0x0001FFFF -#define MCPWM_TIMER0_PHASE_M ((MCPWM_TIMER0_PHASE_V) << (MCPWM_TIMER0_PHASE_S)) -#define MCPWM_TIMER0_PHASE_V 0x1FFFF -#define MCPWM_TIMER0_PHASE_S 4 +/*description: .*/ +#define MCPWM_TIMER0_PHASE 0x0001FFFF +#define MCPWM_TIMER0_PHASE_M ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S)) +#define MCPWM_TIMER0_PHASE_V 0x1FFFF +#define MCPWM_TIMER0_PHASE_S 4 /* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_TIMER0_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER0_SYNCO_SEL_M ((MCPWM_TIMER0_SYNCO_SEL_V) << (MCPWM_TIMER0_SYNCO_SEL_S)) -#define MCPWM_TIMER0_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/*description: .*/ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER0_SYNCO_SEL_M ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S)) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER0_SYNCO_SEL_S 2 /* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: write the negate value will trigger a sw sync*/ -#define MCPWM_TIMER0_SYNC_SW (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER0_SYNC_SW_V 0x1 -#define MCPWM_TIMER0_SYNC_SW_S 1 +/*description: write the negate value will trigger a sw sync.*/ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_V 0x1 +#define MCPWM_TIMER0_SYNC_SW_S 1 /* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER0_SYNCI_EN_V 0x1 -#define MCPWM_TIMER0_SYNCI_EN_S 0 +/*description: .*/ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_V 0x1 +#define MCPWM_TIMER0_SYNCI_EN_S 0 -#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0010) +#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10) /* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TIMER0_DIRECTION (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER0_DIRECTION_V 0x1 -#define MCPWM_TIMER0_DIRECTION_S 16 +/*description: .*/ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_V 0x1 +#define MCPWM_TIMER0_DIRECTION_S 16 /* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_TIMER0_VALUE 0x0000FFFF -#define MCPWM_TIMER0_VALUE_M ((MCPWM_TIMER0_VALUE_V) << (MCPWM_TIMER0_VALUE_S)) -#define MCPWM_TIMER0_VALUE_V 0xFFFF -#define MCPWM_TIMER0_VALUE_S 0 +/*description: .*/ +#define MCPWM_TIMER0_VALUE 0x0000FFFF +#define MCPWM_TIMER0_VALUE_M ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S)) +#define MCPWM_TIMER0_VALUE_V 0xFFFF +#define MCPWM_TIMER0_VALUE_S 0 -#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0014) +#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14) /* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER1_PERIOD_UPMETHOD_M ((MCPWM_TIMER1_PERIOD_UPMETHOD_V) << (MCPWM_TIMER1_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 +/*description: .*/ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 /* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: */ -#define MCPWM_TIMER1_PERIOD 0x0000FFFF -#define MCPWM_TIMER1_PERIOD_M ((MCPWM_TIMER1_PERIOD_V) << (MCPWM_TIMER1_PERIOD_S)) -#define MCPWM_TIMER1_PERIOD_V 0xFFFF -#define MCPWM_TIMER1_PERIOD_S 8 +/*description: .*/ +#define MCPWM_TIMER1_PERIOD 0x0000FFFF +#define MCPWM_TIMER1_PERIOD_M ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S)) +#define MCPWM_TIMER1_PERIOD_V 0xFFFF +#define MCPWM_TIMER1_PERIOD_S 8 /* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_PRESCALE 0x000000FF -#define MCPWM_TIMER1_PRESCALE_M ((MCPWM_TIMER1_PRESCALE_V) << (MCPWM_TIMER1_PRESCALE_S)) -#define MCPWM_TIMER1_PRESCALE_V 0xFF -#define MCPWM_TIMER1_PRESCALE_S 0 +/*description: .*/ +#define MCPWM_TIMER1_PRESCALE 0x000000FF +#define MCPWM_TIMER1_PRESCALE_M ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S)) +#define MCPWM_TIMER1_PRESCALE_V 0xFF +#define MCPWM_TIMER1_PRESCALE_S 0 -#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0018) +#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18) /* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: 0: freeze 1: inc 2: dec 3: up-down*/ -#define MCPWM_TIMER1_MOD 0x00000003 -#define MCPWM_TIMER1_MOD_M ((MCPWM_TIMER1_MOD_V) << (MCPWM_TIMER1_MOD_S)) -#define MCPWM_TIMER1_MOD_V 0x3 -#define MCPWM_TIMER1_MOD_S 3 +/*description: 0: freeze, 1: inc, 2: dec, 3: up-down.*/ +#define MCPWM_TIMER1_MOD 0x00000003 +#define MCPWM_TIMER1_MOD_M ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S)) +#define MCPWM_TIMER1_MOD_V 0x3 +#define MCPWM_TIMER1_MOD_S 3 /* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_START 0x00000007 -#define MCPWM_TIMER1_START_M ((MCPWM_TIMER1_START_V) << (MCPWM_TIMER1_START_S)) -#define MCPWM_TIMER1_START_V 0x7 -#define MCPWM_TIMER1_START_S 0 +/*description: .*/ +#define MCPWM_TIMER1_START 0x00000007 +#define MCPWM_TIMER1_START_M ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S)) +#define MCPWM_TIMER1_START_V 0x7 +#define MCPWM_TIMER1_START_S 0 -#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x001c) +#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1C) /* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: */ -#define MCPWM_TIMER1_PHASE 0x0001FFFF -#define MCPWM_TIMER1_PHASE_M ((MCPWM_TIMER1_PHASE_V) << (MCPWM_TIMER1_PHASE_S)) -#define MCPWM_TIMER1_PHASE_V 0x1FFFF -#define MCPWM_TIMER1_PHASE_S 4 +/*description: .*/ +#define MCPWM_TIMER1_PHASE 0x0001FFFF +#define MCPWM_TIMER1_PHASE_M ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S)) +#define MCPWM_TIMER1_PHASE_V 0x1FFFF +#define MCPWM_TIMER1_PHASE_S 4 /* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: 0: synci 1: tez 2: tep else 0*/ -#define MCPWM_TIMER1_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER1_SYNCO_SEL_M ((MCPWM_TIMER1_SYNCO_SEL_V) << (MCPWM_TIMER1_SYNCO_SEL_S)) -#define MCPWM_TIMER1_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/*description: 0: synci, 1: tez, 2: tep, else 0.*/ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER1_SYNCO_SEL_M ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S)) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER1_SYNCO_SEL_S 2 /* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: write the negate value will trigger a sw sync*/ -#define MCPWM_TIMER1_SYNC_SW (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER1_SYNC_SW_V 0x1 -#define MCPWM_TIMER1_SYNC_SW_S 1 +/*description: write the negate value will trigger a sw sync.*/ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_V 0x1 +#define MCPWM_TIMER1_SYNC_SW_S 1 /* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER1_SYNCI_EN_V 0x1 -#define MCPWM_TIMER1_SYNCI_EN_S 0 +/*description: .*/ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_V 0x1 +#define MCPWM_TIMER1_SYNCI_EN_S 0 -#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0020) +#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20) /* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TIMER1_DIRECTION (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER1_DIRECTION_V 0x1 -#define MCPWM_TIMER1_DIRECTION_S 16 +/*description: .*/ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_V 0x1 +#define MCPWM_TIMER1_DIRECTION_S 16 /* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_TIMER1_VALUE 0x0000FFFF -#define MCPWM_TIMER1_VALUE_M ((MCPWM_TIMER1_VALUE_V) << (MCPWM_TIMER1_VALUE_S)) -#define MCPWM_TIMER1_VALUE_V 0xFFFF -#define MCPWM_TIMER1_VALUE_S 0 +/*description: .*/ +#define MCPWM_TIMER1_VALUE 0x0000FFFF +#define MCPWM_TIMER1_VALUE_M ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S)) +#define MCPWM_TIMER1_VALUE_V 0xFFFF +#define MCPWM_TIMER1_VALUE_S 0 -#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0024) +#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24) /* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003 -#define MCPWM_TIMER2_PERIOD_UPMETHOD_M ((MCPWM_TIMER2_PERIOD_UPMETHOD_V) << (MCPWM_TIMER2_PERIOD_UPMETHOD_S)) -#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x3 -#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 +/*description: .*/ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 /* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ -/*description: */ -#define MCPWM_TIMER2_PERIOD 0x0000FFFF -#define MCPWM_TIMER2_PERIOD_M ((MCPWM_TIMER2_PERIOD_V) << (MCPWM_TIMER2_PERIOD_S)) -#define MCPWM_TIMER2_PERIOD_V 0xFFFF -#define MCPWM_TIMER2_PERIOD_S 8 +/*description: .*/ +#define MCPWM_TIMER2_PERIOD 0x0000FFFF +#define MCPWM_TIMER2_PERIOD_M ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S)) +#define MCPWM_TIMER2_PERIOD_V 0xFFFF +#define MCPWM_TIMER2_PERIOD_S 8 /* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_PRESCALE 0x000000FF -#define MCPWM_TIMER2_PRESCALE_M ((MCPWM_TIMER2_PRESCALE_V) << (MCPWM_TIMER2_PRESCALE_S)) -#define MCPWM_TIMER2_PRESCALE_V 0xFF -#define MCPWM_TIMER2_PRESCALE_S 0 +/*description: .*/ +#define MCPWM_TIMER2_PRESCALE 0x000000FF +#define MCPWM_TIMER2_PRESCALE_M ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S)) +#define MCPWM_TIMER2_PRESCALE_V 0xFF +#define MCPWM_TIMER2_PRESCALE_S 0 -#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0028) +#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28) /* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_MOD 0x00000003 -#define MCPWM_TIMER2_MOD_M ((MCPWM_TIMER2_MOD_V) << (MCPWM_TIMER2_MOD_S)) -#define MCPWM_TIMER2_MOD_V 0x3 -#define MCPWM_TIMER2_MOD_S 3 +/*description: .*/ +#define MCPWM_TIMER2_MOD 0x00000003 +#define MCPWM_TIMER2_MOD_M ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S)) +#define MCPWM_TIMER2_MOD_V 0x3 +#define MCPWM_TIMER2_MOD_S 3 /* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_START 0x00000007 -#define MCPWM_TIMER2_START_M ((MCPWM_TIMER2_START_V) << (MCPWM_TIMER2_START_S)) -#define MCPWM_TIMER2_START_V 0x7 -#define MCPWM_TIMER2_START_S 0 +/*description: .*/ +#define MCPWM_TIMER2_START 0x00000007 +#define MCPWM_TIMER2_START_M ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S)) +#define MCPWM_TIMER2_START_V 0x7 +#define MCPWM_TIMER2_START_S 0 -#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x002c) +#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2C) /* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ -/*description: */ -#define MCPWM_TIMER2_PHASE 0x0001FFFF -#define MCPWM_TIMER2_PHASE_M ((MCPWM_TIMER2_PHASE_V) << (MCPWM_TIMER2_PHASE_S)) -#define MCPWM_TIMER2_PHASE_V 0x1FFFF -#define MCPWM_TIMER2_PHASE_S 4 +/*description: .*/ +#define MCPWM_TIMER2_PHASE 0x0001FFFF +#define MCPWM_TIMER2_PHASE_M ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S)) +#define MCPWM_TIMER2_PHASE_V 0x1FFFF +#define MCPWM_TIMER2_PHASE_S 4 /* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_TIMER2_SYNCO_SEL 0x00000003 -#define MCPWM_TIMER2_SYNCO_SEL_M ((MCPWM_TIMER2_SYNCO_SEL_V) << (MCPWM_TIMER2_SYNCO_SEL_S)) -#define MCPWM_TIMER2_SYNCO_SEL_V 0x3 -#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/*description: .*/ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER2_SYNCO_SEL_M ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S)) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER2_SYNCO_SEL_S 2 /* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: write the negate value will trigger a sw sync*/ -#define MCPWM_TIMER2_SYNC_SW (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_M (BIT(1)) -#define MCPWM_TIMER2_SYNC_SW_V 0x1 -#define MCPWM_TIMER2_SYNC_SW_S 1 +/*description: write the negate value will trigger a sw sync.*/ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_V 0x1 +#define MCPWM_TIMER2_SYNC_SW_S 1 /* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_M (BIT(0)) -#define MCPWM_TIMER2_SYNCI_EN_V 0x1 -#define MCPWM_TIMER2_SYNCI_EN_S 0 +/*description: .*/ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_V 0x1 +#define MCPWM_TIMER2_SYNCI_EN_S 0 -#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0030) +#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30) /* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TIMER2_DIRECTION (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_M (BIT(16)) -#define MCPWM_TIMER2_DIRECTION_V 0x1 -#define MCPWM_TIMER2_DIRECTION_S 16 +/*description: .*/ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_V 0x1 +#define MCPWM_TIMER2_DIRECTION_S 16 /* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_TIMER2_VALUE 0x0000FFFF -#define MCPWM_TIMER2_VALUE_M ((MCPWM_TIMER2_VALUE_V) << (MCPWM_TIMER2_VALUE_S)) -#define MCPWM_TIMER2_VALUE_V 0xFFFF -#define MCPWM_TIMER2_VALUE_S 0 +/*description: .*/ +#define MCPWM_TIMER2_VALUE 0x0000FFFF +#define MCPWM_TIMER2_VALUE_M ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S)) +#define MCPWM_TIMER2_VALUE_V 0xFFFF +#define MCPWM_TIMER2_VALUE_S 0 -#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0034) +#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34) /* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (BIT(11)) -#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 +/*description: .*/ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 /* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (BIT(10)) -#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/*description: .*/ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 /* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (BIT(9)) -#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x1 -#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/*description: .*/ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 /* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */ -/*description: */ -#define MCPWM_TIMER2_SYNCISEL 0x00000007 -#define MCPWM_TIMER2_SYNCISEL_M ((MCPWM_TIMER2_SYNCISEL_V) << (MCPWM_TIMER2_SYNCISEL_S)) -#define MCPWM_TIMER2_SYNCISEL_V 0x7 -#define MCPWM_TIMER2_SYNCISEL_S 6 +/*description: .*/ +#define MCPWM_TIMER2_SYNCISEL 0x00000007 +#define MCPWM_TIMER2_SYNCISEL_M ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S)) +#define MCPWM_TIMER2_SYNCISEL_V 0x7 +#define MCPWM_TIMER2_SYNCISEL_S 6 /* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */ -/*description: */ -#define MCPWM_TIMER1_SYNCISEL 0x00000007 -#define MCPWM_TIMER1_SYNCISEL_M ((MCPWM_TIMER1_SYNCISEL_V) << (MCPWM_TIMER1_SYNCISEL_S)) -#define MCPWM_TIMER1_SYNCISEL_V 0x7 -#define MCPWM_TIMER1_SYNCISEL_S 3 +/*description: .*/ +#define MCPWM_TIMER1_SYNCISEL 0x00000007 +#define MCPWM_TIMER1_SYNCISEL_M ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S)) +#define MCPWM_TIMER1_SYNCISEL_V 0x7 +#define MCPWM_TIMER1_SYNCISEL_S 3 /* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */ -/*description: */ -#define MCPWM_TIMER0_SYNCISEL 0x00000007 -#define MCPWM_TIMER0_SYNCISEL_M ((MCPWM_TIMER0_SYNCISEL_V) << (MCPWM_TIMER0_SYNCISEL_S)) -#define MCPWM_TIMER0_SYNCISEL_V 0x7 -#define MCPWM_TIMER0_SYNCISEL_S 0 +/*description: .*/ +#define MCPWM_TIMER0_SYNCISEL 0x00000007 +#define MCPWM_TIMER0_SYNCISEL_M ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S)) +#define MCPWM_TIMER0_SYNCISEL_V 0x7 +#define MCPWM_TIMER0_SYNCISEL_S 0 -#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x0038) +#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38) /* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR2_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR2_TIMERSEL_M ((MCPWM_OPERATOR2_TIMERSEL_V) << (MCPWM_OPERATOR2_TIMERSEL_S)) -#define MCPWM_OPERATOR2_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR2_TIMERSEL_S 4 +/*description: 0: timer0, 1: timer1, 2: timer2.*/ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR2_TIMERSEL_M ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S)) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR2_TIMERSEL_S 4 /* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR1_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR1_TIMERSEL_M ((MCPWM_OPERATOR1_TIMERSEL_V) << (MCPWM_OPERATOR1_TIMERSEL_S)) -#define MCPWM_OPERATOR1_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/*description: 0: timer0, 1: timer1, 2: timer2.*/ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR1_TIMERSEL_M ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S)) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR1_TIMERSEL_S 2 /* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: 0: timer0 1: timer1 2: timer2*/ -#define MCPWM_OPERATOR0_TIMERSEL 0x00000003 -#define MCPWM_OPERATOR0_TIMERSEL_M ((MCPWM_OPERATOR0_TIMERSEL_V) << (MCPWM_OPERATOR0_TIMERSEL_S)) -#define MCPWM_OPERATOR0_TIMERSEL_V 0x3 -#define MCPWM_OPERATOR0_TIMERSEL_S 0 +/*description: 0: timer0, 1: timer1, 2: timer2.*/ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR0_TIMERSEL_M ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S)) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR0_TIMERSEL_S 0 -#define MCPWM_CMPR0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x003c) +#define MCPWM_CMPR0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3C) /* MCPWM_CMPR0_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR0_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_CMPR0_B_SHDW_FULL_V 0x1 -#define MCPWM_CMPR0_B_SHDW_FULL_S 9 +/*description: .*/ +#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR0_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_CMPR0_B_SHDW_FULL_V 0x1 +#define MCPWM_CMPR0_B_SHDW_FULL_S 9 /* MCPWM_CMPR0_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR0_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_CMPR0_A_SHDW_FULL_V 0x1 -#define MCPWM_CMPR0_A_SHDW_FULL_S 8 +/*description: .*/ +#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR0_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_CMPR0_A_SHDW_FULL_V 0x1 +#define MCPWM_CMPR0_A_SHDW_FULL_S 8 /* MCPWM_CMPR0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ -#define MCPWM_CMPR0_B_UPMETHOD 0x0000000F -#define MCPWM_CMPR0_B_UPMETHOD_M ((MCPWM_CMPR0_B_UPMETHOD_V) << (MCPWM_CMPR0_B_UPMETHOD_S)) -#define MCPWM_CMPR0_B_UPMETHOD_V 0xF -#define MCPWM_CMPR0_B_UPMETHOD_S 4 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ +#define MCPWM_CMPR0_B_UPMETHOD 0x0000000F +#define MCPWM_CMPR0_B_UPMETHOD_M ((MCPWM_CMPR0_B_UPMETHOD_V)<<(MCPWM_CMPR0_B_UPMETHOD_S)) +#define MCPWM_CMPR0_B_UPMETHOD_V 0xF +#define MCPWM_CMPR0_B_UPMETHOD_S 4 /* MCPWM_CMPR0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ -#define MCPWM_CMPR0_A_UPMETHOD 0x0000000F -#define MCPWM_CMPR0_A_UPMETHOD_M ((MCPWM_CMPR0_A_UPMETHOD_V) << (MCPWM_CMPR0_A_UPMETHOD_S)) -#define MCPWM_CMPR0_A_UPMETHOD_V 0xF -#define MCPWM_CMPR0_A_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ +#define MCPWM_CMPR0_A_UPMETHOD 0x0000000F +#define MCPWM_CMPR0_A_UPMETHOD_M ((MCPWM_CMPR0_A_UPMETHOD_V)<<(MCPWM_CMPR0_A_UPMETHOD_S)) +#define MCPWM_CMPR0_A_UPMETHOD_V 0xF +#define MCPWM_CMPR0_A_UPMETHOD_S 0 -#define MCPWM_CMPR0_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x0040) +#define MCPWM_CMPR0_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x40) /* MCPWM_CMPR0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_A 0x0000FFFF -#define MCPWM_CMPR0_A_M ((MCPWM_CMPR0_A_V) << (MCPWM_CMPR0_A_S)) -#define MCPWM_CMPR0_A_V 0xFFFF -#define MCPWM_CMPR0_A_S 0 +/*description: .*/ +#define MCPWM_CMPR0_A 0x0000FFFF +#define MCPWM_CMPR0_A_M ((MCPWM_CMPR0_A_V)<<(MCPWM_CMPR0_A_S)) +#define MCPWM_CMPR0_A_V 0xFFFF +#define MCPWM_CMPR0_A_S 0 -#define MCPWM_CMPR0_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x0044) +#define MCPWM_CMPR0_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x44) /* MCPWM_CMPR0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_B 0x0000FFFF -#define MCPWM_CMPR0_B_M ((MCPWM_CMPR0_B_V) << (MCPWM_CMPR0_B_S)) -#define MCPWM_CMPR0_B_V 0xFFFF -#define MCPWM_CMPR0_B_S 0 +/*description: .*/ +#define MCPWM_CMPR0_B 0x0000FFFF +#define MCPWM_CMPR0_B_M ((MCPWM_CMPR0_B_V)<<(MCPWM_CMPR0_B_S)) +#define MCPWM_CMPR0_B_V 0xFFFF +#define MCPWM_CMPR0_B_S 0 -#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0048) +#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48) /* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ -#define MCPWM_GEN0_T1_SEL 0x00000007 -#define MCPWM_GEN0_T1_SEL_M ((MCPWM_GEN0_T1_SEL_V) << (MCPWM_GEN0_T1_SEL_S)) -#define MCPWM_GEN0_T1_SEL_V 0x7 -#define MCPWM_GEN0_T1_SEL_S 7 +/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ +#define MCPWM_GEN0_T1_SEL 0x00000007 +#define MCPWM_GEN0_T1_SEL_M ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S)) +#define MCPWM_GEN0_T1_SEL_V 0x7 +#define MCPWM_GEN0_T1_SEL_S 7 /* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ -#define MCPWM_GEN0_T0_SEL 0x00000007 -#define MCPWM_GEN0_T0_SEL_M ((MCPWM_GEN0_T0_SEL_V) << (MCPWM_GEN0_T0_SEL_S)) -#define MCPWM_GEN0_T0_SEL_V 0x7 -#define MCPWM_GEN0_T0_SEL_S 4 +/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ +#define MCPWM_GEN0_T0_SEL 0x00000007 +#define MCPWM_GEN0_T0_SEL_M ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S)) +#define MCPWM_GEN0_T0_SEL_V 0x7 +#define MCPWM_GEN0_T0_SEL_S 4 /* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/ -#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN0_CFG_UPMETHOD_M ((MCPWM_GEN0_CFG_UPMETHOD_V) << (MCPWM_GEN0_CFG_UPMETHOD_S)) -#define MCPWM_GEN0_CFG_UPMETHOD_V 0xF -#define MCPWM_GEN0_CFG_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze.*/ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN0_CFG_UPMETHOD_M ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S)) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 -#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x004c) +#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4C) /* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN0_B_NCIFORCE_MODE_M ((MCPWM_GEN0_B_NCIFORCE_MODE_V) << (MCPWM_GEN0_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN0_B_NCIFORCE_MODE_M ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 /* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force a toggle will trigger a force event*/ -#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN0_B_NCIFORCE_V 0x1 -#define MCPWM_GEN0_B_NCIFORCE_S 13 +/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_V 0x1 +#define MCPWM_GEN0_B_NCIFORCE_S 13 /* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN0_A_NCIFORCE_MODE_M ((MCPWM_GEN0_A_NCIFORCE_MODE_V) << (MCPWM_GEN0_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN0_A_NCIFORCE_MODE_M ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 /* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force a toggle will trigger a force event*/ -#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN0_A_NCIFORCE_V 0x1 -#define MCPWM_GEN0_A_NCIFORCE_S 10 +/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_V 0x1 +#define MCPWM_GEN0_A_NCIFORCE_S 10 /* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN0_B_CNTUFORCE_MODE_M ((MCPWM_GEN0_B_CNTUFORCE_MODE_V) << (MCPWM_GEN0_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 /* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN0_A_CNTUFORCE_MODE_M ((MCPWM_GEN0_A_CNTUFORCE_MODE_V) << (MCPWM_GEN0_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 /* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: - sync bit5: freeze*/ -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V) << (MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: free +ze.*/ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 -#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x0050) +#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50) /* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN0_A_DT1 0x00000003 -#define MCPWM_GEN0_A_DT1_M ((MCPWM_GEN0_A_DT1_V) << (MCPWM_GEN0_A_DT1_S)) -#define MCPWM_GEN0_A_DT1_V 0x3 -#define MCPWM_GEN0_A_DT1_S 22 +/*description: 0: no change, 1: low, 2: high, 3: toggle.*/ +#define MCPWM_GEN0_A_DT1 0x00000003 +#define MCPWM_GEN0_A_DT1_M ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S)) +#define MCPWM_GEN0_A_DT1_V 0x3 +#define MCPWM_GEN0_A_DT1_S 22 /* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_DT0 0x00000003 -#define MCPWM_GEN0_A_DT0_M ((MCPWM_GEN0_A_DT0_V) << (MCPWM_GEN0_A_DT0_S)) -#define MCPWM_GEN0_A_DT0_V 0x3 -#define MCPWM_GEN0_A_DT0_S 20 +/*description: .*/ +#define MCPWM_GEN0_A_DT0 0x00000003 +#define MCPWM_GEN0_A_DT0_M ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S)) +#define MCPWM_GEN0_A_DT0_V 0x3 +#define MCPWM_GEN0_A_DT0_S 20 /* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_DTEB 0x00000003 -#define MCPWM_GEN0_A_DTEB_M ((MCPWM_GEN0_A_DTEB_V) << (MCPWM_GEN0_A_DTEB_S)) -#define MCPWM_GEN0_A_DTEB_V 0x3 -#define MCPWM_GEN0_A_DTEB_S 18 +/*description: .*/ +#define MCPWM_GEN0_A_DTEB 0x00000003 +#define MCPWM_GEN0_A_DTEB_M ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S)) +#define MCPWM_GEN0_A_DTEB_V 0x3 +#define MCPWM_GEN0_A_DTEB_S 18 /* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_DTEA 0x00000003 -#define MCPWM_GEN0_A_DTEA_M ((MCPWM_GEN0_A_DTEA_V) << (MCPWM_GEN0_A_DTEA_S)) -#define MCPWM_GEN0_A_DTEA_V 0x3 -#define MCPWM_GEN0_A_DTEA_S 16 +/*description: .*/ +#define MCPWM_GEN0_A_DTEA 0x00000003 +#define MCPWM_GEN0_A_DTEA_M ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S)) +#define MCPWM_GEN0_A_DTEA_V 0x3 +#define MCPWM_GEN0_A_DTEA_S 16 /* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_DTEP 0x00000003 -#define MCPWM_GEN0_A_DTEP_M ((MCPWM_GEN0_A_DTEP_V) << (MCPWM_GEN0_A_DTEP_S)) -#define MCPWM_GEN0_A_DTEP_V 0x3 -#define MCPWM_GEN0_A_DTEP_S 14 +/*description: .*/ +#define MCPWM_GEN0_A_DTEP 0x00000003 +#define MCPWM_GEN0_A_DTEP_M ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S)) +#define MCPWM_GEN0_A_DTEP_V 0x3 +#define MCPWM_GEN0_A_DTEP_S 14 /* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_DTEZ 0x00000003 -#define MCPWM_GEN0_A_DTEZ_M ((MCPWM_GEN0_A_DTEZ_V) << (MCPWM_GEN0_A_DTEZ_S)) -#define MCPWM_GEN0_A_DTEZ_V 0x3 -#define MCPWM_GEN0_A_DTEZ_S 12 +/*description: .*/ +#define MCPWM_GEN0_A_DTEZ 0x00000003 +#define MCPWM_GEN0_A_DTEZ_M ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S)) +#define MCPWM_GEN0_A_DTEZ_V 0x3 +#define MCPWM_GEN0_A_DTEZ_S 12 /* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_UT1 0x00000003 -#define MCPWM_GEN0_A_UT1_M ((MCPWM_GEN0_A_UT1_V) << (MCPWM_GEN0_A_UT1_S)) -#define MCPWM_GEN0_A_UT1_V 0x3 -#define MCPWM_GEN0_A_UT1_S 10 +/*description: .*/ +#define MCPWM_GEN0_A_UT1 0x00000003 +#define MCPWM_GEN0_A_UT1_M ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S)) +#define MCPWM_GEN0_A_UT1_V 0x3 +#define MCPWM_GEN0_A_UT1_S 10 /* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_UT0 0x00000003 -#define MCPWM_GEN0_A_UT0_M ((MCPWM_GEN0_A_UT0_V) << (MCPWM_GEN0_A_UT0_S)) -#define MCPWM_GEN0_A_UT0_V 0x3 -#define MCPWM_GEN0_A_UT0_S 8 +/*description: .*/ +#define MCPWM_GEN0_A_UT0 0x00000003 +#define MCPWM_GEN0_A_UT0_M ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S)) +#define MCPWM_GEN0_A_UT0_V 0x3 +#define MCPWM_GEN0_A_UT0_S 8 /* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_UTEB 0x00000003 -#define MCPWM_GEN0_A_UTEB_M ((MCPWM_GEN0_A_UTEB_V) << (MCPWM_GEN0_A_UTEB_S)) -#define MCPWM_GEN0_A_UTEB_V 0x3 -#define MCPWM_GEN0_A_UTEB_S 6 +/*description: .*/ +#define MCPWM_GEN0_A_UTEB 0x00000003 +#define MCPWM_GEN0_A_UTEB_M ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S)) +#define MCPWM_GEN0_A_UTEB_V 0x3 +#define MCPWM_GEN0_A_UTEB_S 6 /* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_UTEA 0x00000003 -#define MCPWM_GEN0_A_UTEA_M ((MCPWM_GEN0_A_UTEA_V) << (MCPWM_GEN0_A_UTEA_S)) -#define MCPWM_GEN0_A_UTEA_V 0x3 -#define MCPWM_GEN0_A_UTEA_S 4 +/*description: .*/ +#define MCPWM_GEN0_A_UTEA 0x00000003 +#define MCPWM_GEN0_A_UTEA_M ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S)) +#define MCPWM_GEN0_A_UTEA_V 0x3 +#define MCPWM_GEN0_A_UTEA_S 4 /* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_UTEP 0x00000003 -#define MCPWM_GEN0_A_UTEP_M ((MCPWM_GEN0_A_UTEP_V) << (MCPWM_GEN0_A_UTEP_S)) -#define MCPWM_GEN0_A_UTEP_V 0x3 -#define MCPWM_GEN0_A_UTEP_S 2 +/*description: .*/ +#define MCPWM_GEN0_A_UTEP 0x00000003 +#define MCPWM_GEN0_A_UTEP_M ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S)) +#define MCPWM_GEN0_A_UTEP_V 0x3 +#define MCPWM_GEN0_A_UTEP_S 2 /* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_A_UTEZ 0x00000003 -#define MCPWM_GEN0_A_UTEZ_M ((MCPWM_GEN0_A_UTEZ_V) << (MCPWM_GEN0_A_UTEZ_S)) -#define MCPWM_GEN0_A_UTEZ_V 0x3 -#define MCPWM_GEN0_A_UTEZ_S 0 +/*description: .*/ +#define MCPWM_GEN0_A_UTEZ 0x00000003 +#define MCPWM_GEN0_A_UTEZ_M ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S)) +#define MCPWM_GEN0_A_UTEZ_V 0x3 +#define MCPWM_GEN0_A_UTEZ_S 0 -#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x0054) +#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54) /* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_DT1 0x00000003 -#define MCPWM_GEN0_B_DT1_M ((MCPWM_GEN0_B_DT1_V) << (MCPWM_GEN0_B_DT1_S)) -#define MCPWM_GEN0_B_DT1_V 0x3 -#define MCPWM_GEN0_B_DT1_S 22 +/*description: .*/ +#define MCPWM_GEN0_B_DT1 0x00000003 +#define MCPWM_GEN0_B_DT1_M ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S)) +#define MCPWM_GEN0_B_DT1_V 0x3 +#define MCPWM_GEN0_B_DT1_S 22 /* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_DT0 0x00000003 -#define MCPWM_GEN0_B_DT0_M ((MCPWM_GEN0_B_DT0_V) << (MCPWM_GEN0_B_DT0_S)) -#define MCPWM_GEN0_B_DT0_V 0x3 -#define MCPWM_GEN0_B_DT0_S 20 +/*description: .*/ +#define MCPWM_GEN0_B_DT0 0x00000003 +#define MCPWM_GEN0_B_DT0_M ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S)) +#define MCPWM_GEN0_B_DT0_V 0x3 +#define MCPWM_GEN0_B_DT0_S 20 /* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_DTEB 0x00000003 -#define MCPWM_GEN0_B_DTEB_M ((MCPWM_GEN0_B_DTEB_V) << (MCPWM_GEN0_B_DTEB_S)) -#define MCPWM_GEN0_B_DTEB_V 0x3 -#define MCPWM_GEN0_B_DTEB_S 18 +/*description: .*/ +#define MCPWM_GEN0_B_DTEB 0x00000003 +#define MCPWM_GEN0_B_DTEB_M ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S)) +#define MCPWM_GEN0_B_DTEB_V 0x3 +#define MCPWM_GEN0_B_DTEB_S 18 /* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_DTEA 0x00000003 -#define MCPWM_GEN0_B_DTEA_M ((MCPWM_GEN0_B_DTEA_V) << (MCPWM_GEN0_B_DTEA_S)) -#define MCPWM_GEN0_B_DTEA_V 0x3 -#define MCPWM_GEN0_B_DTEA_S 16 +/*description: .*/ +#define MCPWM_GEN0_B_DTEA 0x00000003 +#define MCPWM_GEN0_B_DTEA_M ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S)) +#define MCPWM_GEN0_B_DTEA_V 0x3 +#define MCPWM_GEN0_B_DTEA_S 16 /* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_DTEP 0x00000003 -#define MCPWM_GEN0_B_DTEP_M ((MCPWM_GEN0_B_DTEP_V) << (MCPWM_GEN0_B_DTEP_S)) -#define MCPWM_GEN0_B_DTEP_V 0x3 -#define MCPWM_GEN0_B_DTEP_S 14 +/*description: .*/ +#define MCPWM_GEN0_B_DTEP 0x00000003 +#define MCPWM_GEN0_B_DTEP_M ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S)) +#define MCPWM_GEN0_B_DTEP_V 0x3 +#define MCPWM_GEN0_B_DTEP_S 14 /* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_DTEZ 0x00000003 -#define MCPWM_GEN0_B_DTEZ_M ((MCPWM_GEN0_B_DTEZ_V) << (MCPWM_GEN0_B_DTEZ_S)) -#define MCPWM_GEN0_B_DTEZ_V 0x3 -#define MCPWM_GEN0_B_DTEZ_S 12 +/*description: .*/ +#define MCPWM_GEN0_B_DTEZ 0x00000003 +#define MCPWM_GEN0_B_DTEZ_M ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S)) +#define MCPWM_GEN0_B_DTEZ_V 0x3 +#define MCPWM_GEN0_B_DTEZ_S 12 /* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_UT1 0x00000003 -#define MCPWM_GEN0_B_UT1_M ((MCPWM_GEN0_B_UT1_V) << (MCPWM_GEN0_B_UT1_S)) -#define MCPWM_GEN0_B_UT1_V 0x3 -#define MCPWM_GEN0_B_UT1_S 10 +/*description: .*/ +#define MCPWM_GEN0_B_UT1 0x00000003 +#define MCPWM_GEN0_B_UT1_M ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S)) +#define MCPWM_GEN0_B_UT1_V 0x3 +#define MCPWM_GEN0_B_UT1_S 10 /* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_UT0 0x00000003 -#define MCPWM_GEN0_B_UT0_M ((MCPWM_GEN0_B_UT0_V) << (MCPWM_GEN0_B_UT0_S)) -#define MCPWM_GEN0_B_UT0_V 0x3 -#define MCPWM_GEN0_B_UT0_S 8 +/*description: .*/ +#define MCPWM_GEN0_B_UT0 0x00000003 +#define MCPWM_GEN0_B_UT0_M ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S)) +#define MCPWM_GEN0_B_UT0_V 0x3 +#define MCPWM_GEN0_B_UT0_S 8 /* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_UTEB 0x00000003 -#define MCPWM_GEN0_B_UTEB_M ((MCPWM_GEN0_B_UTEB_V) << (MCPWM_GEN0_B_UTEB_S)) -#define MCPWM_GEN0_B_UTEB_V 0x3 -#define MCPWM_GEN0_B_UTEB_S 6 +/*description: .*/ +#define MCPWM_GEN0_B_UTEB 0x00000003 +#define MCPWM_GEN0_B_UTEB_M ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S)) +#define MCPWM_GEN0_B_UTEB_V 0x3 +#define MCPWM_GEN0_B_UTEB_S 6 /* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_UTEA 0x00000003 -#define MCPWM_GEN0_B_UTEA_M ((MCPWM_GEN0_B_UTEA_V) << (MCPWM_GEN0_B_UTEA_S)) -#define MCPWM_GEN0_B_UTEA_V 0x3 -#define MCPWM_GEN0_B_UTEA_S 4 +/*description: .*/ +#define MCPWM_GEN0_B_UTEA 0x00000003 +#define MCPWM_GEN0_B_UTEA_M ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S)) +#define MCPWM_GEN0_B_UTEA_V 0x3 +#define MCPWM_GEN0_B_UTEA_S 4 /* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_UTEP 0x00000003 -#define MCPWM_GEN0_B_UTEP_M ((MCPWM_GEN0_B_UTEP_V) << (MCPWM_GEN0_B_UTEP_S)) -#define MCPWM_GEN0_B_UTEP_V 0x3 -#define MCPWM_GEN0_B_UTEP_S 2 +/*description: .*/ +#define MCPWM_GEN0_B_UTEP 0x00000003 +#define MCPWM_GEN0_B_UTEP_M ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S)) +#define MCPWM_GEN0_B_UTEP_V 0x3 +#define MCPWM_GEN0_B_UTEP_S 2 /* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN0_B_UTEZ 0x00000003 -#define MCPWM_GEN0_B_UTEZ_M ((MCPWM_GEN0_B_UTEZ_V) << (MCPWM_GEN0_B_UTEZ_S)) -#define MCPWM_GEN0_B_UTEZ_V 0x3 -#define MCPWM_GEN0_B_UTEZ_S 0 +/*description: .*/ +#define MCPWM_GEN0_B_UTEZ 0x00000003 +#define MCPWM_GEN0_B_UTEZ_M ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S)) +#define MCPWM_GEN0_B_UTEZ_V 0x3 +#define MCPWM_GEN0_B_UTEZ_S 0 -#define MCPWM_DB0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0058) +#define MCPWM_DB0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58) /* MCPWM_DB0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB0_CLK_SEL (BIT(17)) -#define MCPWM_DB0_CLK_SEL_M (BIT(17)) -#define MCPWM_DB0_CLK_SEL_V 0x1 -#define MCPWM_DB0_CLK_SEL_S 17 +/*description: .*/ +#define MCPWM_DB0_CLK_SEL (BIT(17)) +#define MCPWM_DB0_CLK_SEL_M (BIT(17)) +#define MCPWM_DB0_CLK_SEL_V 0x1 +#define MCPWM_DB0_CLK_SEL_S 17 /* MCPWM_DB0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_DB0_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB0_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DB0_B_OUTBYPASS_V 0x1 -#define MCPWM_DB0_B_OUTBYPASS_S 16 +/*description: .*/ +#define MCPWM_DB0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB0_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DB0_B_OUTBYPASS_V 0x1 +#define MCPWM_DB0_B_OUTBYPASS_S 16 /* MCPWM_DB0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_DB0_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB0_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DB0_A_OUTBYPASS_V 0x1 -#define MCPWM_DB0_A_OUTBYPASS_S 15 +/*description: .*/ +#define MCPWM_DB0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB0_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DB0_A_OUTBYPASS_V 0x1 +#define MCPWM_DB0_A_OUTBYPASS_S 15 /* MCPWM_DB0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB0_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB0_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DB0_FED_OUTINVERT_V 0x1 -#define MCPWM_DB0_FED_OUTINVERT_S 14 +/*description: .*/ +#define MCPWM_DB0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB0_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DB0_FED_OUTINVERT_V 0x1 +#define MCPWM_DB0_FED_OUTINVERT_S 14 /* MCPWM_DB0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB0_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB0_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DB0_RED_OUTINVERT_V 0x1 -#define MCPWM_DB0_RED_OUTINVERT_S 13 +/*description: .*/ +#define MCPWM_DB0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB0_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DB0_RED_OUTINVERT_V 0x1 +#define MCPWM_DB0_RED_OUTINVERT_S 13 /* MCPWM_DB0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB0_FED_INSEL (BIT(12)) -#define MCPWM_DB0_FED_INSEL_M (BIT(12)) -#define MCPWM_DB0_FED_INSEL_V 0x1 -#define MCPWM_DB0_FED_INSEL_S 12 +/*description: .*/ +#define MCPWM_DB0_FED_INSEL (BIT(12)) +#define MCPWM_DB0_FED_INSEL_M (BIT(12)) +#define MCPWM_DB0_FED_INSEL_V 0x1 +#define MCPWM_DB0_FED_INSEL_S 12 /* MCPWM_DB0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB0_RED_INSEL (BIT(11)) -#define MCPWM_DB0_RED_INSEL_M (BIT(11)) -#define MCPWM_DB0_RED_INSEL_V 0x1 -#define MCPWM_DB0_RED_INSEL_S 11 +/*description: .*/ +#define MCPWM_DB0_RED_INSEL (BIT(11)) +#define MCPWM_DB0_RED_INSEL_M (BIT(11)) +#define MCPWM_DB0_RED_INSEL_V 0x1 +#define MCPWM_DB0_RED_INSEL_S 11 /* MCPWM_DB0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB0_B_OUTSWAP (BIT(10)) -#define MCPWM_DB0_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DB0_B_OUTSWAP_V 0x1 -#define MCPWM_DB0_B_OUTSWAP_S 10 +/*description: .*/ +#define MCPWM_DB0_B_OUTSWAP (BIT(10)) +#define MCPWM_DB0_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DB0_B_OUTSWAP_V 0x1 +#define MCPWM_DB0_B_OUTSWAP_S 10 /* MCPWM_DB0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB0_A_OUTSWAP (BIT(9)) -#define MCPWM_DB0_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DB0_A_OUTSWAP_V 0x1 -#define MCPWM_DB0_A_OUTSWAP_S 9 +/*description: .*/ +#define MCPWM_DB0_A_OUTSWAP (BIT(9)) +#define MCPWM_DB0_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DB0_A_OUTSWAP_V 0x1 +#define MCPWM_DB0_A_OUTSWAP_S 9 /* MCPWM_DB0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: immediate dual-edge B mode 0: fed/red take effect on different - path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ -#define MCPWM_DB0_DEB_MODE (BIT(8)) -#define MCPWM_DB0_DEB_MODE_M (BIT(8)) -#define MCPWM_DB0_DEB_MODE_V 0x1 -#define MCPWM_DB0_DEB_MODE_S 8 +/*description: immediate, dual-edge B mode, 0: fed/red take effect on different path separately +, 1: fed/red take effect on B path, A out is in bypass or dulpB mode.*/ +#define MCPWM_DB0_DEB_MODE (BIT(8)) +#define MCPWM_DB0_DEB_MODE_M (BIT(8)) +#define MCPWM_DB0_DEB_MODE_V 0x1 +#define MCPWM_DB0_DEB_MODE_S 8 /* MCPWM_DB0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ -#define MCPWM_DB0_RED_UPMETHOD 0x0000000F -#define MCPWM_DB0_RED_UPMETHOD_M ((MCPWM_DB0_RED_UPMETHOD_V) << (MCPWM_DB0_RED_UPMETHOD_S)) -#define MCPWM_DB0_RED_UPMETHOD_V 0xF -#define MCPWM_DB0_RED_UPMETHOD_S 4 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ +#define MCPWM_DB0_RED_UPMETHOD 0x0000000F +#define MCPWM_DB0_RED_UPMETHOD_M ((MCPWM_DB0_RED_UPMETHOD_V)<<(MCPWM_DB0_RED_UPMETHOD_S)) +#define MCPWM_DB0_RED_UPMETHOD_V 0xF +#define MCPWM_DB0_RED_UPMETHOD_S 4 /* MCPWM_DB0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ -#define MCPWM_DB0_FED_UPMETHOD 0x0000000F -#define MCPWM_DB0_FED_UPMETHOD_M ((MCPWM_DB0_FED_UPMETHOD_V) << (MCPWM_DB0_FED_UPMETHOD_S)) -#define MCPWM_DB0_FED_UPMETHOD_V 0xF -#define MCPWM_DB0_FED_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ +#define MCPWM_DB0_FED_UPMETHOD 0x0000000F +#define MCPWM_DB0_FED_UPMETHOD_M ((MCPWM_DB0_FED_UPMETHOD_V)<<(MCPWM_DB0_FED_UPMETHOD_S)) +#define MCPWM_DB0_FED_UPMETHOD_V 0xF +#define MCPWM_DB0_FED_UPMETHOD_S 0 -#define MCPWM_DB0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x005c) +#define MCPWM_DB0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5C) /* MCPWM_DB0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_DB0_FED 0x0000FFFF -#define MCPWM_DB0_FED_M ((MCPWM_DB0_FED_V) << (MCPWM_DB0_FED_S)) -#define MCPWM_DB0_FED_V 0xFFFF -#define MCPWM_DB0_FED_S 0 +/*description: .*/ +#define MCPWM_DB0_FED 0x0000FFFF +#define MCPWM_DB0_FED_M ((MCPWM_DB0_FED_V)<<(MCPWM_DB0_FED_S)) +#define MCPWM_DB0_FED_V 0xFFFF +#define MCPWM_DB0_FED_S 0 -#define MCPWM_DB0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0060) +#define MCPWM_DB0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60) /* MCPWM_DB0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_DB0_RED 0x0000FFFF -#define MCPWM_DB0_RED_M ((MCPWM_DB0_RED_V) << (MCPWM_DB0_RED_S)) -#define MCPWM_DB0_RED_V 0xFFFF -#define MCPWM_DB0_RED_S 0 +/*description: .*/ +#define MCPWM_DB0_RED 0x0000FFFF +#define MCPWM_DB0_RED_M ((MCPWM_DB0_RED_V)<<(MCPWM_DB0_RED_S)) +#define MCPWM_DB0_RED_V 0xFFFF +#define MCPWM_DB0_RED_S 0 -#define MCPWM_CHOPPER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0064) +#define MCPWM_CHOPPER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64) /* MCPWM_CHOPPER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER0_IN_INVERT_M (BIT(13)) -#define MCPWM_CHOPPER0_IN_INVERT_V 0x1 -#define MCPWM_CHOPPER0_IN_INVERT_S 13 +/*description: .*/ +#define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER0_IN_INVERT_M (BIT(13)) +#define MCPWM_CHOPPER0_IN_INVERT_V 0x1 +#define MCPWM_CHOPPER0_IN_INVERT_S 13 /* MCPWM_CHOPPER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER0_OUT_INVERT_M (BIT(12)) -#define MCPWM_CHOPPER0_OUT_INVERT_V 0x1 -#define MCPWM_CHOPPER0_OUT_INVERT_S 12 +/*description: .*/ +#define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER0_OUT_INVERT_M (BIT(12)) +#define MCPWM_CHOPPER0_OUT_INVERT_V 0x1 +#define MCPWM_CHOPPER0_OUT_INVERT_S 12 /* MCPWM_CHOPPER0_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER0_OSHTWTH 0x0000000F -#define MCPWM_CHOPPER0_OSHTWTH_M ((MCPWM_CHOPPER0_OSHTWTH_V) << (MCPWM_CHOPPER0_OSHTWTH_S)) -#define MCPWM_CHOPPER0_OSHTWTH_V 0xF -#define MCPWM_CHOPPER0_OSHTWTH_S 8 +/*description: .*/ +#define MCPWM_CHOPPER0_OSHTWTH 0x0000000F +#define MCPWM_CHOPPER0_OSHTWTH_M ((MCPWM_CHOPPER0_OSHTWTH_V)<<(MCPWM_CHOPPER0_OSHTWTH_S)) +#define MCPWM_CHOPPER0_OSHTWTH_V 0xF +#define MCPWM_CHOPPER0_OSHTWTH_S 8 /* MCPWM_CHOPPER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER0_DUTY 0x00000007 -#define MCPWM_CHOPPER0_DUTY_M ((MCPWM_CHOPPER0_DUTY_V) << (MCPWM_CHOPPER0_DUTY_S)) -#define MCPWM_CHOPPER0_DUTY_V 0x7 -#define MCPWM_CHOPPER0_DUTY_S 5 +/*description: .*/ +#define MCPWM_CHOPPER0_DUTY 0x00000007 +#define MCPWM_CHOPPER0_DUTY_M ((MCPWM_CHOPPER0_DUTY_V)<<(MCPWM_CHOPPER0_DUTY_S)) +#define MCPWM_CHOPPER0_DUTY_V 0x7 +#define MCPWM_CHOPPER0_DUTY_S 5 /* MCPWM_CHOPPER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER0_PRESCALE 0x0000000F -#define MCPWM_CHOPPER0_PRESCALE_M ((MCPWM_CHOPPER0_PRESCALE_V) << (MCPWM_CHOPPER0_PRESCALE_S)) -#define MCPWM_CHOPPER0_PRESCALE_V 0xF -#define MCPWM_CHOPPER0_PRESCALE_S 1 +/*description: .*/ +#define MCPWM_CHOPPER0_PRESCALE 0x0000000F +#define MCPWM_CHOPPER0_PRESCALE_M ((MCPWM_CHOPPER0_PRESCALE_V)<<(MCPWM_CHOPPER0_PRESCALE_S)) +#define MCPWM_CHOPPER0_PRESCALE_V 0xF +#define MCPWM_CHOPPER0_PRESCALE_S 1 /* MCPWM_CHOPPER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER0_EN (BIT(0)) -#define MCPWM_CHOPPER0_EN_M (BIT(0)) -#define MCPWM_CHOPPER0_EN_V 0x1 -#define MCPWM_CHOPPER0_EN_S 0 +/*description: .*/ +#define MCPWM_CHOPPER0_EN (BIT(0)) +#define MCPWM_CHOPPER0_EN_M (BIT(0)) +#define MCPWM_CHOPPER0_EN_V 0x1 +#define MCPWM_CHOPPER0_EN_S 0 -#define MCPWM_TZ0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0068) +#define MCPWM_TZ0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68) /* MCPWM_TZ0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ0_B_OST_U 0x00000003 -#define MCPWM_TZ0_B_OST_U_M ((MCPWM_TZ0_B_OST_U_V) << (MCPWM_TZ0_B_OST_U_S)) -#define MCPWM_TZ0_B_OST_U_V 0x3 -#define MCPWM_TZ0_B_OST_U_S 22 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ0_B_OST_U 0x00000003 +#define MCPWM_TZ0_B_OST_U_M ((MCPWM_TZ0_B_OST_U_V)<<(MCPWM_TZ0_B_OST_U_S)) +#define MCPWM_TZ0_B_OST_U_V 0x3 +#define MCPWM_TZ0_B_OST_U_S 22 /* MCPWM_TZ0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ0_B_OST_D 0x00000003 -#define MCPWM_TZ0_B_OST_D_M ((MCPWM_TZ0_B_OST_D_V) << (MCPWM_TZ0_B_OST_D_S)) -#define MCPWM_TZ0_B_OST_D_V 0x3 -#define MCPWM_TZ0_B_OST_D_S 20 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ0_B_OST_D 0x00000003 +#define MCPWM_TZ0_B_OST_D_M ((MCPWM_TZ0_B_OST_D_V)<<(MCPWM_TZ0_B_OST_D_S)) +#define MCPWM_TZ0_B_OST_D_V 0x3 +#define MCPWM_TZ0_B_OST_D_S 20 /* MCPWM_TZ0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ0_B_CBC_U 0x00000003 -#define MCPWM_TZ0_B_CBC_U_M ((MCPWM_TZ0_B_CBC_U_V) << (MCPWM_TZ0_B_CBC_U_S)) -#define MCPWM_TZ0_B_CBC_U_V 0x3 -#define MCPWM_TZ0_B_CBC_U_S 18 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ0_B_CBC_U 0x00000003 +#define MCPWM_TZ0_B_CBC_U_M ((MCPWM_TZ0_B_CBC_U_V)<<(MCPWM_TZ0_B_CBC_U_S)) +#define MCPWM_TZ0_B_CBC_U_V 0x3 +#define MCPWM_TZ0_B_CBC_U_S 18 /* MCPWM_TZ0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ0_B_CBC_D 0x00000003 -#define MCPWM_TZ0_B_CBC_D_M ((MCPWM_TZ0_B_CBC_D_V) << (MCPWM_TZ0_B_CBC_D_S)) -#define MCPWM_TZ0_B_CBC_D_V 0x3 -#define MCPWM_TZ0_B_CBC_D_S 16 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ0_B_CBC_D 0x00000003 +#define MCPWM_TZ0_B_CBC_D_M ((MCPWM_TZ0_B_CBC_D_V)<<(MCPWM_TZ0_B_CBC_D_S)) +#define MCPWM_TZ0_B_CBC_D_V 0x3 +#define MCPWM_TZ0_B_CBC_D_S 16 /* MCPWM_TZ0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ0_A_OST_U 0x00000003 -#define MCPWM_TZ0_A_OST_U_M ((MCPWM_TZ0_A_OST_U_V) << (MCPWM_TZ0_A_OST_U_S)) -#define MCPWM_TZ0_A_OST_U_V 0x3 -#define MCPWM_TZ0_A_OST_U_S 14 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ0_A_OST_U 0x00000003 +#define MCPWM_TZ0_A_OST_U_M ((MCPWM_TZ0_A_OST_U_V)<<(MCPWM_TZ0_A_OST_U_S)) +#define MCPWM_TZ0_A_OST_U_V 0x3 +#define MCPWM_TZ0_A_OST_U_S 14 /* MCPWM_TZ0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ0_A_OST_D 0x00000003 -#define MCPWM_TZ0_A_OST_D_M ((MCPWM_TZ0_A_OST_D_V) << (MCPWM_TZ0_A_OST_D_S)) -#define MCPWM_TZ0_A_OST_D_V 0x3 -#define MCPWM_TZ0_A_OST_D_S 12 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ0_A_OST_D 0x00000003 +#define MCPWM_TZ0_A_OST_D_M ((MCPWM_TZ0_A_OST_D_V)<<(MCPWM_TZ0_A_OST_D_S)) +#define MCPWM_TZ0_A_OST_D_V 0x3 +#define MCPWM_TZ0_A_OST_D_S 12 /* MCPWM_TZ0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ0_A_CBC_U 0x00000003 -#define MCPWM_TZ0_A_CBC_U_M ((MCPWM_TZ0_A_CBC_U_V) << (MCPWM_TZ0_A_CBC_U_S)) -#define MCPWM_TZ0_A_CBC_U_V 0x3 -#define MCPWM_TZ0_A_CBC_U_S 10 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ0_A_CBC_U 0x00000003 +#define MCPWM_TZ0_A_CBC_U_M ((MCPWM_TZ0_A_CBC_U_V)<<(MCPWM_TZ0_A_CBC_U_S)) +#define MCPWM_TZ0_A_CBC_U_V 0x3 +#define MCPWM_TZ0_A_CBC_U_S 10 /* MCPWM_TZ0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ0_A_CBC_D 0x00000003 -#define MCPWM_TZ0_A_CBC_D_M ((MCPWM_TZ0_A_CBC_D_V) << (MCPWM_TZ0_A_CBC_D_S)) -#define MCPWM_TZ0_A_CBC_D_V 0x3 -#define MCPWM_TZ0_A_CBC_D_S 8 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ0_A_CBC_D 0x00000003 +#define MCPWM_TZ0_A_CBC_D_M ((MCPWM_TZ0_A_CBC_D_V)<<(MCPWM_TZ0_A_CBC_D_S)) +#define MCPWM_TZ0_A_CBC_D_V 0x3 +#define MCPWM_TZ0_A_CBC_D_S 8 /* MCPWM_TZ0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ0_F0_OST (BIT(7)) -#define MCPWM_TZ0_F0_OST_M (BIT(7)) -#define MCPWM_TZ0_F0_OST_V 0x1 -#define MCPWM_TZ0_F0_OST_S 7 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ0_F0_OST (BIT(7)) +#define MCPWM_TZ0_F0_OST_M (BIT(7)) +#define MCPWM_TZ0_F0_OST_V 0x1 +#define MCPWM_TZ0_F0_OST_S 7 /* MCPWM_TZ0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ0_F1_OST (BIT(6)) -#define MCPWM_TZ0_F1_OST_M (BIT(6)) -#define MCPWM_TZ0_F1_OST_V 0x1 -#define MCPWM_TZ0_F1_OST_S 6 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ0_F1_OST (BIT(6)) +#define MCPWM_TZ0_F1_OST_M (BIT(6)) +#define MCPWM_TZ0_F1_OST_V 0x1 +#define MCPWM_TZ0_F1_OST_S 6 /* MCPWM_TZ0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ0_F2_OST (BIT(5)) -#define MCPWM_TZ0_F2_OST_M (BIT(5)) -#define MCPWM_TZ0_F2_OST_V 0x1 -#define MCPWM_TZ0_F2_OST_S 5 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ0_F2_OST (BIT(5)) +#define MCPWM_TZ0_F2_OST_M (BIT(5)) +#define MCPWM_TZ0_F2_OST_V 0x1 +#define MCPWM_TZ0_F2_OST_S 5 /* MCPWM_TZ0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ0_SW_OST (BIT(4)) -#define MCPWM_TZ0_SW_OST_M (BIT(4)) -#define MCPWM_TZ0_SW_OST_V 0x1 -#define MCPWM_TZ0_SW_OST_S 4 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ0_SW_OST (BIT(4)) +#define MCPWM_TZ0_SW_OST_M (BIT(4)) +#define MCPWM_TZ0_SW_OST_V 0x1 +#define MCPWM_TZ0_SW_OST_S 4 /* MCPWM_TZ0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ0_F0_CBC (BIT(3)) -#define MCPWM_TZ0_F0_CBC_M (BIT(3)) -#define MCPWM_TZ0_F0_CBC_V 0x1 -#define MCPWM_TZ0_F0_CBC_S 3 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ0_F0_CBC (BIT(3)) +#define MCPWM_TZ0_F0_CBC_M (BIT(3)) +#define MCPWM_TZ0_F0_CBC_V 0x1 +#define MCPWM_TZ0_F0_CBC_S 3 /* MCPWM_TZ0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ0_F1_CBC (BIT(2)) -#define MCPWM_TZ0_F1_CBC_M (BIT(2)) -#define MCPWM_TZ0_F1_CBC_V 0x1 -#define MCPWM_TZ0_F1_CBC_S 2 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ0_F1_CBC (BIT(2)) +#define MCPWM_TZ0_F1_CBC_M (BIT(2)) +#define MCPWM_TZ0_F1_CBC_V 0x1 +#define MCPWM_TZ0_F1_CBC_S 2 /* MCPWM_TZ0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ0_F2_CBC (BIT(1)) -#define MCPWM_TZ0_F2_CBC_M (BIT(1)) -#define MCPWM_TZ0_F2_CBC_V 0x1 -#define MCPWM_TZ0_F2_CBC_S 1 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ0_F2_CBC (BIT(1)) +#define MCPWM_TZ0_F2_CBC_M (BIT(1)) +#define MCPWM_TZ0_F2_CBC_V 0x1 +#define MCPWM_TZ0_F2_CBC_S 1 /* MCPWM_TZ0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ0_SW_CBC (BIT(0)) -#define MCPWM_TZ0_SW_CBC_M (BIT(0)) -#define MCPWM_TZ0_SW_CBC_V 0x1 -#define MCPWM_TZ0_SW_CBC_S 0 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ0_SW_CBC (BIT(0)) +#define MCPWM_TZ0_SW_CBC_M (BIT(0)) +#define MCPWM_TZ0_SW_CBC_V 0x1 +#define MCPWM_TZ0_SW_CBC_S 0 -#define MCPWM_TZ0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x006c) +#define MCPWM_TZ0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6C) /* MCPWM_TZ0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: a toggle trigger a oneshot tripping*/ -#define MCPWM_TZ0_FORCE_OST (BIT(4)) -#define MCPWM_TZ0_FORCE_OST_M (BIT(4)) -#define MCPWM_TZ0_FORCE_OST_V 0x1 -#define MCPWM_TZ0_FORCE_OST_S 4 +/*description: a toggle trigger a oneshot tripping.*/ +#define MCPWM_TZ0_FORCE_OST (BIT(4)) +#define MCPWM_TZ0_FORCE_OST_M (BIT(4)) +#define MCPWM_TZ0_FORCE_OST_V 0x1 +#define MCPWM_TZ0_FORCE_OST_S 4 /* MCPWM_TZ0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: a toggle trigger a cycle-by-cycle tripping*/ -#define MCPWM_TZ0_FORCE_CBC (BIT(3)) -#define MCPWM_TZ0_FORCE_CBC_M (BIT(3)) -#define MCPWM_TZ0_FORCE_CBC_V 0x1 -#define MCPWM_TZ0_FORCE_CBC_S 3 +/*description: a toggle trigger a cycle-by-cycle tripping.*/ +#define MCPWM_TZ0_FORCE_CBC (BIT(3)) +#define MCPWM_TZ0_FORCE_CBC_M (BIT(3)) +#define MCPWM_TZ0_FORCE_CBC_V 0x1 +#define MCPWM_TZ0_FORCE_CBC_S 3 /* MCPWM_TZ0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: bit0: tez bit1: tep*/ -#define MCPWM_TZ0_CBCPULSE 0x00000003 -#define MCPWM_TZ0_CBCPULSE_M ((MCPWM_TZ0_CBCPULSE_V) << (MCPWM_TZ0_CBCPULSE_S)) -#define MCPWM_TZ0_CBCPULSE_V 0x3 -#define MCPWM_TZ0_CBCPULSE_S 1 +/*description: bit0: tez, bit1: tep.*/ +#define MCPWM_TZ0_CBCPULSE 0x00000003 +#define MCPWM_TZ0_CBCPULSE_M ((MCPWM_TZ0_CBCPULSE_V)<<(MCPWM_TZ0_CBCPULSE_S)) +#define MCPWM_TZ0_CBCPULSE_V 0x3 +#define MCPWM_TZ0_CBCPULSE_S 1 /* MCPWM_TZ0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: a toggle will clear oneshot tripping*/ -#define MCPWM_TZ0_CLR_OST (BIT(0)) -#define MCPWM_TZ0_CLR_OST_M (BIT(0)) -#define MCPWM_TZ0_CLR_OST_V 0x1 -#define MCPWM_TZ0_CLR_OST_S 0 +/*description: a toggle will clear oneshot tripping.*/ +#define MCPWM_TZ0_CLR_OST (BIT(0)) +#define MCPWM_TZ0_CLR_OST_M (BIT(0)) +#define MCPWM_TZ0_CLR_OST_V 0x1 +#define MCPWM_TZ0_CLR_OST_S 0 -#define MCPWM_TZ0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0070) +#define MCPWM_TZ0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70) /* MCPWM_TZ0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_OST_ON (BIT(1)) -#define MCPWM_TZ0_OST_ON_M (BIT(1)) -#define MCPWM_TZ0_OST_ON_V 0x1 -#define MCPWM_TZ0_OST_ON_S 1 +/*description: .*/ +#define MCPWM_TZ0_OST_ON (BIT(1)) +#define MCPWM_TZ0_OST_ON_M (BIT(1)) +#define MCPWM_TZ0_OST_ON_V 0x1 +#define MCPWM_TZ0_OST_ON_S 1 /* MCPWM_TZ0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_CBC_ON (BIT(0)) -#define MCPWM_TZ0_CBC_ON_M (BIT(0)) -#define MCPWM_TZ0_CBC_ON_V 0x1 -#define MCPWM_TZ0_CBC_ON_S 0 +/*description: .*/ +#define MCPWM_TZ0_CBC_ON (BIT(0)) +#define MCPWM_TZ0_CBC_ON_M (BIT(0)) +#define MCPWM_TZ0_CBC_ON_V 0x1 +#define MCPWM_TZ0_CBC_ON_S 0 -#define MCPWM_CMPR1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0074) +#define MCPWM_CMPR1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74) /* MCPWM_CMPR1_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR1_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_CMPR1_B_SHDW_FULL_V 0x1 -#define MCPWM_CMPR1_B_SHDW_FULL_S 9 +/*description: .*/ +#define MCPWM_CMPR1_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR1_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_CMPR1_B_SHDW_FULL_V 0x1 +#define MCPWM_CMPR1_B_SHDW_FULL_S 9 /* MCPWM_CMPR1_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR1_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_CMPR1_A_SHDW_FULL_V 0x1 -#define MCPWM_CMPR1_A_SHDW_FULL_S 8 +/*description: .*/ +#define MCPWM_CMPR1_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR1_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_CMPR1_A_SHDW_FULL_V 0x1 +#define MCPWM_CMPR1_A_SHDW_FULL_S 8 /* MCPWM_CMPR1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ -#define MCPWM_CMPR1_B_UPMETHOD 0x0000000F -#define MCPWM_CMPR1_B_UPMETHOD_M ((MCPWM_CMPR1_B_UPMETHOD_V) << (MCPWM_CMPR1_B_UPMETHOD_S)) -#define MCPWM_CMPR1_B_UPMETHOD_V 0xF -#define MCPWM_CMPR1_B_UPMETHOD_S 4 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ +#define MCPWM_CMPR1_B_UPMETHOD 0x0000000F +#define MCPWM_CMPR1_B_UPMETHOD_M ((MCPWM_CMPR1_B_UPMETHOD_V)<<(MCPWM_CMPR1_B_UPMETHOD_S)) +#define MCPWM_CMPR1_B_UPMETHOD_V 0xF +#define MCPWM_CMPR1_B_UPMETHOD_S 4 /* MCPWM_CMPR1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ -#define MCPWM_CMPR1_A_UPMETHOD 0x0000000F -#define MCPWM_CMPR1_A_UPMETHOD_M ((MCPWM_CMPR1_A_UPMETHOD_V) << (MCPWM_CMPR1_A_UPMETHOD_S)) -#define MCPWM_CMPR1_A_UPMETHOD_V 0xF -#define MCPWM_CMPR1_A_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ +#define MCPWM_CMPR1_A_UPMETHOD 0x0000000F +#define MCPWM_CMPR1_A_UPMETHOD_M ((MCPWM_CMPR1_A_UPMETHOD_V)<<(MCPWM_CMPR1_A_UPMETHOD_S)) +#define MCPWM_CMPR1_A_UPMETHOD_V 0xF +#define MCPWM_CMPR1_A_UPMETHOD_S 0 -#define MCPWM_CMPR1_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x0078) +#define MCPWM_CMPR1_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x78) /* MCPWM_CMPR1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_A 0x0000FFFF -#define MCPWM_CMPR1_A_M ((MCPWM_CMPR1_A_V) << (MCPWM_CMPR1_A_S)) -#define MCPWM_CMPR1_A_V 0xFFFF -#define MCPWM_CMPR1_A_S 0 +/*description: .*/ +#define MCPWM_CMPR1_A 0x0000FFFF +#define MCPWM_CMPR1_A_M ((MCPWM_CMPR1_A_V)<<(MCPWM_CMPR1_A_S)) +#define MCPWM_CMPR1_A_V 0xFFFF +#define MCPWM_CMPR1_A_S 0 -#define MCPWM_CMPR1_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x007c) +#define MCPWM_CMPR1_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x7C) /* MCPWM_CMPR1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_B 0x0000FFFF -#define MCPWM_CMPR1_B_M ((MCPWM_CMPR1_B_V) << (MCPWM_CMPR1_B_S)) -#define MCPWM_CMPR1_B_V 0xFFFF -#define MCPWM_CMPR1_B_S 0 +/*description: .*/ +#define MCPWM_CMPR1_B 0x0000FFFF +#define MCPWM_CMPR1_B_M ((MCPWM_CMPR1_B_V)<<(MCPWM_CMPR1_B_S)) +#define MCPWM_CMPR1_B_V 0xFFFF +#define MCPWM_CMPR1_B_S 0 -#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0080) +#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80) /* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ -#define MCPWM_GEN1_T1_SEL 0x00000007 -#define MCPWM_GEN1_T1_SEL_M ((MCPWM_GEN1_T1_SEL_V) << (MCPWM_GEN1_T1_SEL_S)) -#define MCPWM_GEN1_T1_SEL_V 0x7 -#define MCPWM_GEN1_T1_SEL_S 7 +/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ +#define MCPWM_GEN1_T1_SEL 0x00000007 +#define MCPWM_GEN1_T1_SEL_M ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S)) +#define MCPWM_GEN1_T1_SEL_V 0x7 +#define MCPWM_GEN1_T1_SEL_S 7 /* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ -#define MCPWM_GEN1_T0_SEL 0x00000007 -#define MCPWM_GEN1_T0_SEL_M ((MCPWM_GEN1_T0_SEL_V) << (MCPWM_GEN1_T0_SEL_S)) -#define MCPWM_GEN1_T0_SEL_V 0x7 -#define MCPWM_GEN1_T0_SEL_S 4 +/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ +#define MCPWM_GEN1_T0_SEL 0x00000007 +#define MCPWM_GEN1_T0_SEL_M ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S)) +#define MCPWM_GEN1_T0_SEL_V 0x7 +#define MCPWM_GEN1_T0_SEL_S 4 /* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/ -#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN1_CFG_UPMETHOD_M ((MCPWM_GEN1_CFG_UPMETHOD_V) << (MCPWM_GEN1_CFG_UPMETHOD_S)) -#define MCPWM_GEN1_CFG_UPMETHOD_V 0xF -#define MCPWM_GEN1_CFG_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze.*/ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN1_CFG_UPMETHOD_M ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S)) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 -#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x0084) +#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84) /* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN1_B_NCIFORCE_MODE_M ((MCPWM_GEN1_B_NCIFORCE_MODE_V) << (MCPWM_GEN1_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN1_B_NCIFORCE_MODE_M ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 /* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force a toggle will trigger a force event*/ -#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN1_B_NCIFORCE_V 0x1 -#define MCPWM_GEN1_B_NCIFORCE_S 13 +/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_V 0x1 +#define MCPWM_GEN1_B_NCIFORCE_S 13 /* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN1_A_NCIFORCE_MODE_M ((MCPWM_GEN1_A_NCIFORCE_MODE_V) << (MCPWM_GEN1_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN1_A_NCIFORCE_MODE_M ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 /* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force a toggle will trigger a force event*/ -#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN1_A_NCIFORCE_V 0x1 -#define MCPWM_GEN1_A_NCIFORCE_S 10 +/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_V 0x1 +#define MCPWM_GEN1_A_NCIFORCE_S 10 /* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN1_B_CNTUFORCE_MODE_M ((MCPWM_GEN1_B_CNTUFORCE_MODE_V) << (MCPWM_GEN1_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 /* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN1_A_CNTUFORCE_MODE_M ((MCPWM_GEN1_A_CNTUFORCE_MODE_V) << (MCPWM_GEN1_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 /* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: - sync bit5: freeze*/ -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V) << (MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: free +ze.*/ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 -#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x0088) +#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88) /* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN1_A_DT1 0x00000003 -#define MCPWM_GEN1_A_DT1_M ((MCPWM_GEN1_A_DT1_V) << (MCPWM_GEN1_A_DT1_S)) -#define MCPWM_GEN1_A_DT1_V 0x3 -#define MCPWM_GEN1_A_DT1_S 22 +/*description: 0: no change, 1: low, 2: high, 3: toggle.*/ +#define MCPWM_GEN1_A_DT1 0x00000003 +#define MCPWM_GEN1_A_DT1_M ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S)) +#define MCPWM_GEN1_A_DT1_V 0x3 +#define MCPWM_GEN1_A_DT1_S 22 /* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_DT0 0x00000003 -#define MCPWM_GEN1_A_DT0_M ((MCPWM_GEN1_A_DT0_V) << (MCPWM_GEN1_A_DT0_S)) -#define MCPWM_GEN1_A_DT0_V 0x3 -#define MCPWM_GEN1_A_DT0_S 20 +/*description: .*/ +#define MCPWM_GEN1_A_DT0 0x00000003 +#define MCPWM_GEN1_A_DT0_M ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S)) +#define MCPWM_GEN1_A_DT0_V 0x3 +#define MCPWM_GEN1_A_DT0_S 20 /* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_DTEB 0x00000003 -#define MCPWM_GEN1_A_DTEB_M ((MCPWM_GEN1_A_DTEB_V) << (MCPWM_GEN1_A_DTEB_S)) -#define MCPWM_GEN1_A_DTEB_V 0x3 -#define MCPWM_GEN1_A_DTEB_S 18 +/*description: .*/ +#define MCPWM_GEN1_A_DTEB 0x00000003 +#define MCPWM_GEN1_A_DTEB_M ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S)) +#define MCPWM_GEN1_A_DTEB_V 0x3 +#define MCPWM_GEN1_A_DTEB_S 18 /* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_DTEA 0x00000003 -#define MCPWM_GEN1_A_DTEA_M ((MCPWM_GEN1_A_DTEA_V) << (MCPWM_GEN1_A_DTEA_S)) -#define MCPWM_GEN1_A_DTEA_V 0x3 -#define MCPWM_GEN1_A_DTEA_S 16 +/*description: .*/ +#define MCPWM_GEN1_A_DTEA 0x00000003 +#define MCPWM_GEN1_A_DTEA_M ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S)) +#define MCPWM_GEN1_A_DTEA_V 0x3 +#define MCPWM_GEN1_A_DTEA_S 16 /* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_DTEP 0x00000003 -#define MCPWM_GEN1_A_DTEP_M ((MCPWM_GEN1_A_DTEP_V) << (MCPWM_GEN1_A_DTEP_S)) -#define MCPWM_GEN1_A_DTEP_V 0x3 -#define MCPWM_GEN1_A_DTEP_S 14 +/*description: .*/ +#define MCPWM_GEN1_A_DTEP 0x00000003 +#define MCPWM_GEN1_A_DTEP_M ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S)) +#define MCPWM_GEN1_A_DTEP_V 0x3 +#define MCPWM_GEN1_A_DTEP_S 14 /* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_DTEZ 0x00000003 -#define MCPWM_GEN1_A_DTEZ_M ((MCPWM_GEN1_A_DTEZ_V) << (MCPWM_GEN1_A_DTEZ_S)) -#define MCPWM_GEN1_A_DTEZ_V 0x3 -#define MCPWM_GEN1_A_DTEZ_S 12 +/*description: .*/ +#define MCPWM_GEN1_A_DTEZ 0x00000003 +#define MCPWM_GEN1_A_DTEZ_M ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S)) +#define MCPWM_GEN1_A_DTEZ_V 0x3 +#define MCPWM_GEN1_A_DTEZ_S 12 /* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_UT1 0x00000003 -#define MCPWM_GEN1_A_UT1_M ((MCPWM_GEN1_A_UT1_V) << (MCPWM_GEN1_A_UT1_S)) -#define MCPWM_GEN1_A_UT1_V 0x3 -#define MCPWM_GEN1_A_UT1_S 10 +/*description: .*/ +#define MCPWM_GEN1_A_UT1 0x00000003 +#define MCPWM_GEN1_A_UT1_M ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S)) +#define MCPWM_GEN1_A_UT1_V 0x3 +#define MCPWM_GEN1_A_UT1_S 10 /* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_UT0 0x00000003 -#define MCPWM_GEN1_A_UT0_M ((MCPWM_GEN1_A_UT0_V) << (MCPWM_GEN1_A_UT0_S)) -#define MCPWM_GEN1_A_UT0_V 0x3 -#define MCPWM_GEN1_A_UT0_S 8 +/*description: .*/ +#define MCPWM_GEN1_A_UT0 0x00000003 +#define MCPWM_GEN1_A_UT0_M ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S)) +#define MCPWM_GEN1_A_UT0_V 0x3 +#define MCPWM_GEN1_A_UT0_S 8 /* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_UTEB 0x00000003 -#define MCPWM_GEN1_A_UTEB_M ((MCPWM_GEN1_A_UTEB_V) << (MCPWM_GEN1_A_UTEB_S)) -#define MCPWM_GEN1_A_UTEB_V 0x3 -#define MCPWM_GEN1_A_UTEB_S 6 +/*description: .*/ +#define MCPWM_GEN1_A_UTEB 0x00000003 +#define MCPWM_GEN1_A_UTEB_M ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S)) +#define MCPWM_GEN1_A_UTEB_V 0x3 +#define MCPWM_GEN1_A_UTEB_S 6 /* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_UTEA 0x00000003 -#define MCPWM_GEN1_A_UTEA_M ((MCPWM_GEN1_A_UTEA_V) << (MCPWM_GEN1_A_UTEA_S)) -#define MCPWM_GEN1_A_UTEA_V 0x3 -#define MCPWM_GEN1_A_UTEA_S 4 +/*description: .*/ +#define MCPWM_GEN1_A_UTEA 0x00000003 +#define MCPWM_GEN1_A_UTEA_M ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S)) +#define MCPWM_GEN1_A_UTEA_V 0x3 +#define MCPWM_GEN1_A_UTEA_S 4 /* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_UTEP 0x00000003 -#define MCPWM_GEN1_A_UTEP_M ((MCPWM_GEN1_A_UTEP_V) << (MCPWM_GEN1_A_UTEP_S)) -#define MCPWM_GEN1_A_UTEP_V 0x3 -#define MCPWM_GEN1_A_UTEP_S 2 +/*description: .*/ +#define MCPWM_GEN1_A_UTEP 0x00000003 +#define MCPWM_GEN1_A_UTEP_M ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S)) +#define MCPWM_GEN1_A_UTEP_V 0x3 +#define MCPWM_GEN1_A_UTEP_S 2 /* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_A_UTEZ 0x00000003 -#define MCPWM_GEN1_A_UTEZ_M ((MCPWM_GEN1_A_UTEZ_V) << (MCPWM_GEN1_A_UTEZ_S)) -#define MCPWM_GEN1_A_UTEZ_V 0x3 -#define MCPWM_GEN1_A_UTEZ_S 0 +/*description: .*/ +#define MCPWM_GEN1_A_UTEZ 0x00000003 +#define MCPWM_GEN1_A_UTEZ_M ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S)) +#define MCPWM_GEN1_A_UTEZ_V 0x3 +#define MCPWM_GEN1_A_UTEZ_S 0 -#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x008c) +#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8C) /* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_DT1 0x00000003 -#define MCPWM_GEN1_B_DT1_M ((MCPWM_GEN1_B_DT1_V) << (MCPWM_GEN1_B_DT1_S)) -#define MCPWM_GEN1_B_DT1_V 0x3 -#define MCPWM_GEN1_B_DT1_S 22 +/*description: .*/ +#define MCPWM_GEN1_B_DT1 0x00000003 +#define MCPWM_GEN1_B_DT1_M ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S)) +#define MCPWM_GEN1_B_DT1_V 0x3 +#define MCPWM_GEN1_B_DT1_S 22 /* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_DT0 0x00000003 -#define MCPWM_GEN1_B_DT0_M ((MCPWM_GEN1_B_DT0_V) << (MCPWM_GEN1_B_DT0_S)) -#define MCPWM_GEN1_B_DT0_V 0x3 -#define MCPWM_GEN1_B_DT0_S 20 +/*description: .*/ +#define MCPWM_GEN1_B_DT0 0x00000003 +#define MCPWM_GEN1_B_DT0_M ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S)) +#define MCPWM_GEN1_B_DT0_V 0x3 +#define MCPWM_GEN1_B_DT0_S 20 /* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_DTEB 0x00000003 -#define MCPWM_GEN1_B_DTEB_M ((MCPWM_GEN1_B_DTEB_V) << (MCPWM_GEN1_B_DTEB_S)) -#define MCPWM_GEN1_B_DTEB_V 0x3 -#define MCPWM_GEN1_B_DTEB_S 18 +/*description: .*/ +#define MCPWM_GEN1_B_DTEB 0x00000003 +#define MCPWM_GEN1_B_DTEB_M ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S)) +#define MCPWM_GEN1_B_DTEB_V 0x3 +#define MCPWM_GEN1_B_DTEB_S 18 /* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_DTEA 0x00000003 -#define MCPWM_GEN1_B_DTEA_M ((MCPWM_GEN1_B_DTEA_V) << (MCPWM_GEN1_B_DTEA_S)) -#define MCPWM_GEN1_B_DTEA_V 0x3 -#define MCPWM_GEN1_B_DTEA_S 16 +/*description: .*/ +#define MCPWM_GEN1_B_DTEA 0x00000003 +#define MCPWM_GEN1_B_DTEA_M ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S)) +#define MCPWM_GEN1_B_DTEA_V 0x3 +#define MCPWM_GEN1_B_DTEA_S 16 /* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_DTEP 0x00000003 -#define MCPWM_GEN1_B_DTEP_M ((MCPWM_GEN1_B_DTEP_V) << (MCPWM_GEN1_B_DTEP_S)) -#define MCPWM_GEN1_B_DTEP_V 0x3 -#define MCPWM_GEN1_B_DTEP_S 14 +/*description: .*/ +#define MCPWM_GEN1_B_DTEP 0x00000003 +#define MCPWM_GEN1_B_DTEP_M ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S)) +#define MCPWM_GEN1_B_DTEP_V 0x3 +#define MCPWM_GEN1_B_DTEP_S 14 /* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_DTEZ 0x00000003 -#define MCPWM_GEN1_B_DTEZ_M ((MCPWM_GEN1_B_DTEZ_V) << (MCPWM_GEN1_B_DTEZ_S)) -#define MCPWM_GEN1_B_DTEZ_V 0x3 -#define MCPWM_GEN1_B_DTEZ_S 12 +/*description: .*/ +#define MCPWM_GEN1_B_DTEZ 0x00000003 +#define MCPWM_GEN1_B_DTEZ_M ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S)) +#define MCPWM_GEN1_B_DTEZ_V 0x3 +#define MCPWM_GEN1_B_DTEZ_S 12 /* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_UT1 0x00000003 -#define MCPWM_GEN1_B_UT1_M ((MCPWM_GEN1_B_UT1_V) << (MCPWM_GEN1_B_UT1_S)) -#define MCPWM_GEN1_B_UT1_V 0x3 -#define MCPWM_GEN1_B_UT1_S 10 +/*description: .*/ +#define MCPWM_GEN1_B_UT1 0x00000003 +#define MCPWM_GEN1_B_UT1_M ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S)) +#define MCPWM_GEN1_B_UT1_V 0x3 +#define MCPWM_GEN1_B_UT1_S 10 /* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_UT0 0x00000003 -#define MCPWM_GEN1_B_UT0_M ((MCPWM_GEN1_B_UT0_V) << (MCPWM_GEN1_B_UT0_S)) -#define MCPWM_GEN1_B_UT0_V 0x3 -#define MCPWM_GEN1_B_UT0_S 8 +/*description: .*/ +#define MCPWM_GEN1_B_UT0 0x00000003 +#define MCPWM_GEN1_B_UT0_M ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S)) +#define MCPWM_GEN1_B_UT0_V 0x3 +#define MCPWM_GEN1_B_UT0_S 8 /* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_UTEB 0x00000003 -#define MCPWM_GEN1_B_UTEB_M ((MCPWM_GEN1_B_UTEB_V) << (MCPWM_GEN1_B_UTEB_S)) -#define MCPWM_GEN1_B_UTEB_V 0x3 -#define MCPWM_GEN1_B_UTEB_S 6 +/*description: .*/ +#define MCPWM_GEN1_B_UTEB 0x00000003 +#define MCPWM_GEN1_B_UTEB_M ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S)) +#define MCPWM_GEN1_B_UTEB_V 0x3 +#define MCPWM_GEN1_B_UTEB_S 6 /* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_UTEA 0x00000003 -#define MCPWM_GEN1_B_UTEA_M ((MCPWM_GEN1_B_UTEA_V) << (MCPWM_GEN1_B_UTEA_S)) -#define MCPWM_GEN1_B_UTEA_V 0x3 -#define MCPWM_GEN1_B_UTEA_S 4 +/*description: .*/ +#define MCPWM_GEN1_B_UTEA 0x00000003 +#define MCPWM_GEN1_B_UTEA_M ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S)) +#define MCPWM_GEN1_B_UTEA_V 0x3 +#define MCPWM_GEN1_B_UTEA_S 4 /* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_UTEP 0x00000003 -#define MCPWM_GEN1_B_UTEP_M ((MCPWM_GEN1_B_UTEP_V) << (MCPWM_GEN1_B_UTEP_S)) -#define MCPWM_GEN1_B_UTEP_V 0x3 -#define MCPWM_GEN1_B_UTEP_S 2 +/*description: .*/ +#define MCPWM_GEN1_B_UTEP 0x00000003 +#define MCPWM_GEN1_B_UTEP_M ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S)) +#define MCPWM_GEN1_B_UTEP_V 0x3 +#define MCPWM_GEN1_B_UTEP_S 2 /* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN1_B_UTEZ 0x00000003 -#define MCPWM_GEN1_B_UTEZ_M ((MCPWM_GEN1_B_UTEZ_V) << (MCPWM_GEN1_B_UTEZ_S)) -#define MCPWM_GEN1_B_UTEZ_V 0x3 -#define MCPWM_GEN1_B_UTEZ_S 0 +/*description: .*/ +#define MCPWM_GEN1_B_UTEZ 0x00000003 +#define MCPWM_GEN1_B_UTEZ_M ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S)) +#define MCPWM_GEN1_B_UTEZ_V 0x3 +#define MCPWM_GEN1_B_UTEZ_S 0 -#define MCPWM_DB1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0090) +#define MCPWM_DB1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90) /* MCPWM_DB1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB1_CLK_SEL (BIT(17)) -#define MCPWM_DB1_CLK_SEL_M (BIT(17)) -#define MCPWM_DB1_CLK_SEL_V 0x1 -#define MCPWM_DB1_CLK_SEL_S 17 +/*description: .*/ +#define MCPWM_DB1_CLK_SEL (BIT(17)) +#define MCPWM_DB1_CLK_SEL_M (BIT(17)) +#define MCPWM_DB1_CLK_SEL_V 0x1 +#define MCPWM_DB1_CLK_SEL_S 17 /* MCPWM_DB1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_DB1_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB1_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DB1_B_OUTBYPASS_V 0x1 -#define MCPWM_DB1_B_OUTBYPASS_S 16 +/*description: .*/ +#define MCPWM_DB1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB1_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DB1_B_OUTBYPASS_V 0x1 +#define MCPWM_DB1_B_OUTBYPASS_S 16 /* MCPWM_DB1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_DB1_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB1_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DB1_A_OUTBYPASS_V 0x1 -#define MCPWM_DB1_A_OUTBYPASS_S 15 +/*description: .*/ +#define MCPWM_DB1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB1_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DB1_A_OUTBYPASS_V 0x1 +#define MCPWM_DB1_A_OUTBYPASS_S 15 /* MCPWM_DB1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB1_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB1_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DB1_FED_OUTINVERT_V 0x1 -#define MCPWM_DB1_FED_OUTINVERT_S 14 +/*description: .*/ +#define MCPWM_DB1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB1_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DB1_FED_OUTINVERT_V 0x1 +#define MCPWM_DB1_FED_OUTINVERT_S 14 /* MCPWM_DB1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB1_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB1_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DB1_RED_OUTINVERT_V 0x1 -#define MCPWM_DB1_RED_OUTINVERT_S 13 +/*description: .*/ +#define MCPWM_DB1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB1_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DB1_RED_OUTINVERT_V 0x1 +#define MCPWM_DB1_RED_OUTINVERT_S 13 /* MCPWM_DB1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB1_FED_INSEL (BIT(12)) -#define MCPWM_DB1_FED_INSEL_M (BIT(12)) -#define MCPWM_DB1_FED_INSEL_V 0x1 -#define MCPWM_DB1_FED_INSEL_S 12 +/*description: .*/ +#define MCPWM_DB1_FED_INSEL (BIT(12)) +#define MCPWM_DB1_FED_INSEL_M (BIT(12)) +#define MCPWM_DB1_FED_INSEL_V 0x1 +#define MCPWM_DB1_FED_INSEL_S 12 /* MCPWM_DB1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB1_RED_INSEL (BIT(11)) -#define MCPWM_DB1_RED_INSEL_M (BIT(11)) -#define MCPWM_DB1_RED_INSEL_V 0x1 -#define MCPWM_DB1_RED_INSEL_S 11 +/*description: .*/ +#define MCPWM_DB1_RED_INSEL (BIT(11)) +#define MCPWM_DB1_RED_INSEL_M (BIT(11)) +#define MCPWM_DB1_RED_INSEL_V 0x1 +#define MCPWM_DB1_RED_INSEL_S 11 /* MCPWM_DB1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB1_B_OUTSWAP (BIT(10)) -#define MCPWM_DB1_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DB1_B_OUTSWAP_V 0x1 -#define MCPWM_DB1_B_OUTSWAP_S 10 +/*description: .*/ +#define MCPWM_DB1_B_OUTSWAP (BIT(10)) +#define MCPWM_DB1_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DB1_B_OUTSWAP_V 0x1 +#define MCPWM_DB1_B_OUTSWAP_S 10 /* MCPWM_DB1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB1_A_OUTSWAP (BIT(9)) -#define MCPWM_DB1_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DB1_A_OUTSWAP_V 0x1 -#define MCPWM_DB1_A_OUTSWAP_S 9 +/*description: .*/ +#define MCPWM_DB1_A_OUTSWAP (BIT(9)) +#define MCPWM_DB1_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DB1_A_OUTSWAP_V 0x1 +#define MCPWM_DB1_A_OUTSWAP_S 9 /* MCPWM_DB1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB1_DEB_MODE (BIT(8)) -#define MCPWM_DB1_DEB_MODE_M (BIT(8)) -#define MCPWM_DB1_DEB_MODE_V 0x1 -#define MCPWM_DB1_DEB_MODE_S 8 +/*description: .*/ +#define MCPWM_DB1_DEB_MODE (BIT(8)) +#define MCPWM_DB1_DEB_MODE_M (BIT(8)) +#define MCPWM_DB1_DEB_MODE_V 0x1 +#define MCPWM_DB1_DEB_MODE_S 8 /* MCPWM_DB1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_DB1_RED_UPMETHOD 0x0000000F -#define MCPWM_DB1_RED_UPMETHOD_M ((MCPWM_DB1_RED_UPMETHOD_V) << (MCPWM_DB1_RED_UPMETHOD_S)) -#define MCPWM_DB1_RED_UPMETHOD_V 0xF -#define MCPWM_DB1_RED_UPMETHOD_S 4 +/*description: .*/ +#define MCPWM_DB1_RED_UPMETHOD 0x0000000F +#define MCPWM_DB1_RED_UPMETHOD_M ((MCPWM_DB1_RED_UPMETHOD_V)<<(MCPWM_DB1_RED_UPMETHOD_S)) +#define MCPWM_DB1_RED_UPMETHOD_V 0xF +#define MCPWM_DB1_RED_UPMETHOD_S 4 /* MCPWM_DB1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_DB1_FED_UPMETHOD 0x0000000F -#define MCPWM_DB1_FED_UPMETHOD_M ((MCPWM_DB1_FED_UPMETHOD_V) << (MCPWM_DB1_FED_UPMETHOD_S)) -#define MCPWM_DB1_FED_UPMETHOD_V 0xF -#define MCPWM_DB1_FED_UPMETHOD_S 0 +/*description: .*/ +#define MCPWM_DB1_FED_UPMETHOD 0x0000000F +#define MCPWM_DB1_FED_UPMETHOD_M ((MCPWM_DB1_FED_UPMETHOD_V)<<(MCPWM_DB1_FED_UPMETHOD_S)) +#define MCPWM_DB1_FED_UPMETHOD_V 0xF +#define MCPWM_DB1_FED_UPMETHOD_S 0 -#define MCPWM_DB1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0094) +#define MCPWM_DB1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94) /* MCPWM_DB1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_DB1_FED 0x0000FFFF -#define MCPWM_DB1_FED_M ((MCPWM_DB1_FED_V) << (MCPWM_DB1_FED_S)) -#define MCPWM_DB1_FED_V 0xFFFF -#define MCPWM_DB1_FED_S 0 +/*description: .*/ +#define MCPWM_DB1_FED 0x0000FFFF +#define MCPWM_DB1_FED_M ((MCPWM_DB1_FED_V)<<(MCPWM_DB1_FED_S)) +#define MCPWM_DB1_FED_V 0xFFFF +#define MCPWM_DB1_FED_S 0 -#define MCPWM_DB1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0098) +#define MCPWM_DB1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98) /* MCPWM_DB1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_DB1_RED 0x0000FFFF -#define MCPWM_DB1_RED_M ((MCPWM_DB1_RED_V) << (MCPWM_DB1_RED_S)) -#define MCPWM_DB1_RED_V 0xFFFF -#define MCPWM_DB1_RED_S 0 +/*description: .*/ +#define MCPWM_DB1_RED 0x0000FFFF +#define MCPWM_DB1_RED_M ((MCPWM_DB1_RED_V)<<(MCPWM_DB1_RED_S)) +#define MCPWM_DB1_RED_V 0xFFFF +#define MCPWM_DB1_RED_S 0 -#define MCPWM_CHOPPER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x009c) +#define MCPWM_CHOPPER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9C) /* MCPWM_CHOPPER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER1_IN_INVERT_M (BIT(13)) -#define MCPWM_CHOPPER1_IN_INVERT_V 0x1 -#define MCPWM_CHOPPER1_IN_INVERT_S 13 +/*description: .*/ +#define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER1_IN_INVERT_M (BIT(13)) +#define MCPWM_CHOPPER1_IN_INVERT_V 0x1 +#define MCPWM_CHOPPER1_IN_INVERT_S 13 /* MCPWM_CHOPPER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER1_OUT_INVERT_M (BIT(12)) -#define MCPWM_CHOPPER1_OUT_INVERT_V 0x1 -#define MCPWM_CHOPPER1_OUT_INVERT_S 12 +/*description: .*/ +#define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER1_OUT_INVERT_M (BIT(12)) +#define MCPWM_CHOPPER1_OUT_INVERT_V 0x1 +#define MCPWM_CHOPPER1_OUT_INVERT_S 12 /* MCPWM_CHOPPER1_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER1_OSHTWTH 0x0000000F -#define MCPWM_CHOPPER1_OSHTWTH_M ((MCPWM_CHOPPER1_OSHTWTH_V) << (MCPWM_CHOPPER1_OSHTWTH_S)) -#define MCPWM_CHOPPER1_OSHTWTH_V 0xF -#define MCPWM_CHOPPER1_OSHTWTH_S 8 +/*description: .*/ +#define MCPWM_CHOPPER1_OSHTWTH 0x0000000F +#define MCPWM_CHOPPER1_OSHTWTH_M ((MCPWM_CHOPPER1_OSHTWTH_V)<<(MCPWM_CHOPPER1_OSHTWTH_S)) +#define MCPWM_CHOPPER1_OSHTWTH_V 0xF +#define MCPWM_CHOPPER1_OSHTWTH_S 8 /* MCPWM_CHOPPER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER1_DUTY 0x00000007 -#define MCPWM_CHOPPER1_DUTY_M ((MCPWM_CHOPPER1_DUTY_V) << (MCPWM_CHOPPER1_DUTY_S)) -#define MCPWM_CHOPPER1_DUTY_V 0x7 -#define MCPWM_CHOPPER1_DUTY_S 5 +/*description: .*/ +#define MCPWM_CHOPPER1_DUTY 0x00000007 +#define MCPWM_CHOPPER1_DUTY_M ((MCPWM_CHOPPER1_DUTY_V)<<(MCPWM_CHOPPER1_DUTY_S)) +#define MCPWM_CHOPPER1_DUTY_V 0x7 +#define MCPWM_CHOPPER1_DUTY_S 5 /* MCPWM_CHOPPER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER1_PRESCALE 0x0000000F -#define MCPWM_CHOPPER1_PRESCALE_M ((MCPWM_CHOPPER1_PRESCALE_V) << (MCPWM_CHOPPER1_PRESCALE_S)) -#define MCPWM_CHOPPER1_PRESCALE_V 0xF -#define MCPWM_CHOPPER1_PRESCALE_S 1 +/*description: .*/ +#define MCPWM_CHOPPER1_PRESCALE 0x0000000F +#define MCPWM_CHOPPER1_PRESCALE_M ((MCPWM_CHOPPER1_PRESCALE_V)<<(MCPWM_CHOPPER1_PRESCALE_S)) +#define MCPWM_CHOPPER1_PRESCALE_V 0xF +#define MCPWM_CHOPPER1_PRESCALE_S 1 /* MCPWM_CHOPPER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER1_EN (BIT(0)) -#define MCPWM_CHOPPER1_EN_M (BIT(0)) -#define MCPWM_CHOPPER1_EN_V 0x1 -#define MCPWM_CHOPPER1_EN_S 0 +/*description: .*/ +#define MCPWM_CHOPPER1_EN (BIT(0)) +#define MCPWM_CHOPPER1_EN_M (BIT(0)) +#define MCPWM_CHOPPER1_EN_V 0x1 +#define MCPWM_CHOPPER1_EN_S 0 -#define MCPWM_TZ1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00a0) +#define MCPWM_TZ1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xA0) /* MCPWM_TZ1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ1_B_OST_U 0x00000003 -#define MCPWM_TZ1_B_OST_U_M ((MCPWM_TZ1_B_OST_U_V) << (MCPWM_TZ1_B_OST_U_S)) -#define MCPWM_TZ1_B_OST_U_V 0x3 -#define MCPWM_TZ1_B_OST_U_S 22 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ1_B_OST_U 0x00000003 +#define MCPWM_TZ1_B_OST_U_M ((MCPWM_TZ1_B_OST_U_V)<<(MCPWM_TZ1_B_OST_U_S)) +#define MCPWM_TZ1_B_OST_U_V 0x3 +#define MCPWM_TZ1_B_OST_U_S 22 /* MCPWM_TZ1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ1_B_OST_D 0x00000003 -#define MCPWM_TZ1_B_OST_D_M ((MCPWM_TZ1_B_OST_D_V) << (MCPWM_TZ1_B_OST_D_S)) -#define MCPWM_TZ1_B_OST_D_V 0x3 -#define MCPWM_TZ1_B_OST_D_S 20 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ1_B_OST_D 0x00000003 +#define MCPWM_TZ1_B_OST_D_M ((MCPWM_TZ1_B_OST_D_V)<<(MCPWM_TZ1_B_OST_D_S)) +#define MCPWM_TZ1_B_OST_D_V 0x3 +#define MCPWM_TZ1_B_OST_D_S 20 /* MCPWM_TZ1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ1_B_CBC_U 0x00000003 -#define MCPWM_TZ1_B_CBC_U_M ((MCPWM_TZ1_B_CBC_U_V) << (MCPWM_TZ1_B_CBC_U_S)) -#define MCPWM_TZ1_B_CBC_U_V 0x3 -#define MCPWM_TZ1_B_CBC_U_S 18 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ1_B_CBC_U 0x00000003 +#define MCPWM_TZ1_B_CBC_U_M ((MCPWM_TZ1_B_CBC_U_V)<<(MCPWM_TZ1_B_CBC_U_S)) +#define MCPWM_TZ1_B_CBC_U_V 0x3 +#define MCPWM_TZ1_B_CBC_U_S 18 /* MCPWM_TZ1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ1_B_CBC_D 0x00000003 -#define MCPWM_TZ1_B_CBC_D_M ((MCPWM_TZ1_B_CBC_D_V) << (MCPWM_TZ1_B_CBC_D_S)) -#define MCPWM_TZ1_B_CBC_D_V 0x3 -#define MCPWM_TZ1_B_CBC_D_S 16 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ1_B_CBC_D 0x00000003 +#define MCPWM_TZ1_B_CBC_D_M ((MCPWM_TZ1_B_CBC_D_V)<<(MCPWM_TZ1_B_CBC_D_S)) +#define MCPWM_TZ1_B_CBC_D_V 0x3 +#define MCPWM_TZ1_B_CBC_D_S 16 /* MCPWM_TZ1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ1_A_OST_U 0x00000003 -#define MCPWM_TZ1_A_OST_U_M ((MCPWM_TZ1_A_OST_U_V) << (MCPWM_TZ1_A_OST_U_S)) -#define MCPWM_TZ1_A_OST_U_V 0x3 -#define MCPWM_TZ1_A_OST_U_S 14 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ1_A_OST_U 0x00000003 +#define MCPWM_TZ1_A_OST_U_M ((MCPWM_TZ1_A_OST_U_V)<<(MCPWM_TZ1_A_OST_U_S)) +#define MCPWM_TZ1_A_OST_U_V 0x3 +#define MCPWM_TZ1_A_OST_U_S 14 /* MCPWM_TZ1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ1_A_OST_D 0x00000003 -#define MCPWM_TZ1_A_OST_D_M ((MCPWM_TZ1_A_OST_D_V) << (MCPWM_TZ1_A_OST_D_S)) -#define MCPWM_TZ1_A_OST_D_V 0x3 -#define MCPWM_TZ1_A_OST_D_S 12 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ1_A_OST_D 0x00000003 +#define MCPWM_TZ1_A_OST_D_M ((MCPWM_TZ1_A_OST_D_V)<<(MCPWM_TZ1_A_OST_D_S)) +#define MCPWM_TZ1_A_OST_D_V 0x3 +#define MCPWM_TZ1_A_OST_D_S 12 /* MCPWM_TZ1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ1_A_CBC_U 0x00000003 -#define MCPWM_TZ1_A_CBC_U_M ((MCPWM_TZ1_A_CBC_U_V) << (MCPWM_TZ1_A_CBC_U_S)) -#define MCPWM_TZ1_A_CBC_U_V 0x3 -#define MCPWM_TZ1_A_CBC_U_S 10 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ1_A_CBC_U 0x00000003 +#define MCPWM_TZ1_A_CBC_U_M ((MCPWM_TZ1_A_CBC_U_V)<<(MCPWM_TZ1_A_CBC_U_S)) +#define MCPWM_TZ1_A_CBC_U_V 0x3 +#define MCPWM_TZ1_A_CBC_U_S 10 /* MCPWM_TZ1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ1_A_CBC_D 0x00000003 -#define MCPWM_TZ1_A_CBC_D_M ((MCPWM_TZ1_A_CBC_D_V) << (MCPWM_TZ1_A_CBC_D_S)) -#define MCPWM_TZ1_A_CBC_D_V 0x3 -#define MCPWM_TZ1_A_CBC_D_S 8 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ1_A_CBC_D 0x00000003 +#define MCPWM_TZ1_A_CBC_D_M ((MCPWM_TZ1_A_CBC_D_V)<<(MCPWM_TZ1_A_CBC_D_S)) +#define MCPWM_TZ1_A_CBC_D_V 0x3 +#define MCPWM_TZ1_A_CBC_D_S 8 /* MCPWM_TZ1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ1_F0_OST (BIT(7)) -#define MCPWM_TZ1_F0_OST_M (BIT(7)) -#define MCPWM_TZ1_F0_OST_V 0x1 -#define MCPWM_TZ1_F0_OST_S 7 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ1_F0_OST (BIT(7)) +#define MCPWM_TZ1_F0_OST_M (BIT(7)) +#define MCPWM_TZ1_F0_OST_V 0x1 +#define MCPWM_TZ1_F0_OST_S 7 /* MCPWM_TZ1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ1_F1_OST (BIT(6)) -#define MCPWM_TZ1_F1_OST_M (BIT(6)) -#define MCPWM_TZ1_F1_OST_V 0x1 -#define MCPWM_TZ1_F1_OST_S 6 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ1_F1_OST (BIT(6)) +#define MCPWM_TZ1_F1_OST_M (BIT(6)) +#define MCPWM_TZ1_F1_OST_V 0x1 +#define MCPWM_TZ1_F1_OST_S 6 /* MCPWM_TZ1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ1_F2_OST (BIT(5)) -#define MCPWM_TZ1_F2_OST_M (BIT(5)) -#define MCPWM_TZ1_F2_OST_V 0x1 -#define MCPWM_TZ1_F2_OST_S 5 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ1_F2_OST (BIT(5)) +#define MCPWM_TZ1_F2_OST_M (BIT(5)) +#define MCPWM_TZ1_F2_OST_V 0x1 +#define MCPWM_TZ1_F2_OST_S 5 /* MCPWM_TZ1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ1_SW_OST (BIT(4)) -#define MCPWM_TZ1_SW_OST_M (BIT(4)) -#define MCPWM_TZ1_SW_OST_V 0x1 -#define MCPWM_TZ1_SW_OST_S 4 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ1_SW_OST (BIT(4)) +#define MCPWM_TZ1_SW_OST_M (BIT(4)) +#define MCPWM_TZ1_SW_OST_V 0x1 +#define MCPWM_TZ1_SW_OST_S 4 /* MCPWM_TZ1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ1_F0_CBC (BIT(3)) -#define MCPWM_TZ1_F0_CBC_M (BIT(3)) -#define MCPWM_TZ1_F0_CBC_V 0x1 -#define MCPWM_TZ1_F0_CBC_S 3 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ1_F0_CBC (BIT(3)) +#define MCPWM_TZ1_F0_CBC_M (BIT(3)) +#define MCPWM_TZ1_F0_CBC_V 0x1 +#define MCPWM_TZ1_F0_CBC_S 3 /* MCPWM_TZ1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ1_F1_CBC (BIT(2)) -#define MCPWM_TZ1_F1_CBC_M (BIT(2)) -#define MCPWM_TZ1_F1_CBC_V 0x1 -#define MCPWM_TZ1_F1_CBC_S 2 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ1_F1_CBC (BIT(2)) +#define MCPWM_TZ1_F1_CBC_M (BIT(2)) +#define MCPWM_TZ1_F1_CBC_V 0x1 +#define MCPWM_TZ1_F1_CBC_S 2 /* MCPWM_TZ1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ1_F2_CBC (BIT(1)) -#define MCPWM_TZ1_F2_CBC_M (BIT(1)) -#define MCPWM_TZ1_F2_CBC_V 0x1 -#define MCPWM_TZ1_F2_CBC_S 1 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ1_F2_CBC (BIT(1)) +#define MCPWM_TZ1_F2_CBC_M (BIT(1)) +#define MCPWM_TZ1_F2_CBC_V 0x1 +#define MCPWM_TZ1_F2_CBC_S 1 /* MCPWM_TZ1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ1_SW_CBC (BIT(0)) -#define MCPWM_TZ1_SW_CBC_M (BIT(0)) -#define MCPWM_TZ1_SW_CBC_V 0x1 -#define MCPWM_TZ1_SW_CBC_S 0 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ1_SW_CBC (BIT(0)) +#define MCPWM_TZ1_SW_CBC_M (BIT(0)) +#define MCPWM_TZ1_SW_CBC_V 0x1 +#define MCPWM_TZ1_SW_CBC_S 0 -#define MCPWM_TZ1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00a4) +#define MCPWM_TZ1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xA4) /* MCPWM_TZ1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: a toggle trigger a oneshot tripping*/ -#define MCPWM_TZ1_FORCE_OST (BIT(4)) -#define MCPWM_TZ1_FORCE_OST_M (BIT(4)) -#define MCPWM_TZ1_FORCE_OST_V 0x1 -#define MCPWM_TZ1_FORCE_OST_S 4 +/*description: a toggle trigger a oneshot tripping.*/ +#define MCPWM_TZ1_FORCE_OST (BIT(4)) +#define MCPWM_TZ1_FORCE_OST_M (BIT(4)) +#define MCPWM_TZ1_FORCE_OST_V 0x1 +#define MCPWM_TZ1_FORCE_OST_S 4 /* MCPWM_TZ1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: a toggle trigger a cycle-by-cycle tripping*/ -#define MCPWM_TZ1_FORCE_CBC (BIT(3)) -#define MCPWM_TZ1_FORCE_CBC_M (BIT(3)) -#define MCPWM_TZ1_FORCE_CBC_V 0x1 -#define MCPWM_TZ1_FORCE_CBC_S 3 +/*description: a toggle trigger a cycle-by-cycle tripping.*/ +#define MCPWM_TZ1_FORCE_CBC (BIT(3)) +#define MCPWM_TZ1_FORCE_CBC_M (BIT(3)) +#define MCPWM_TZ1_FORCE_CBC_V 0x1 +#define MCPWM_TZ1_FORCE_CBC_S 3 /* MCPWM_TZ1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: bit0: tez bit1: tep*/ -#define MCPWM_TZ1_CBCPULSE 0x00000003 -#define MCPWM_TZ1_CBCPULSE_M ((MCPWM_TZ1_CBCPULSE_V) << (MCPWM_TZ1_CBCPULSE_S)) -#define MCPWM_TZ1_CBCPULSE_V 0x3 -#define MCPWM_TZ1_CBCPULSE_S 1 +/*description: bit0: tez, bit1: tep.*/ +#define MCPWM_TZ1_CBCPULSE 0x00000003 +#define MCPWM_TZ1_CBCPULSE_M ((MCPWM_TZ1_CBCPULSE_V)<<(MCPWM_TZ1_CBCPULSE_S)) +#define MCPWM_TZ1_CBCPULSE_V 0x3 +#define MCPWM_TZ1_CBCPULSE_S 1 /* MCPWM_TZ1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: a toggle will clear oneshot tripping*/ -#define MCPWM_TZ1_CLR_OST (BIT(0)) -#define MCPWM_TZ1_CLR_OST_M (BIT(0)) -#define MCPWM_TZ1_CLR_OST_V 0x1 -#define MCPWM_TZ1_CLR_OST_S 0 +/*description: a toggle will clear oneshot tripping.*/ +#define MCPWM_TZ1_CLR_OST (BIT(0)) +#define MCPWM_TZ1_CLR_OST_M (BIT(0)) +#define MCPWM_TZ1_CLR_OST_V 0x1 +#define MCPWM_TZ1_CLR_OST_S 0 -#define MCPWM_TZ1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00a8) +#define MCPWM_TZ1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xA8) /* MCPWM_TZ1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_OST_ON (BIT(1)) -#define MCPWM_TZ1_OST_ON_M (BIT(1)) -#define MCPWM_TZ1_OST_ON_V 0x1 -#define MCPWM_TZ1_OST_ON_S 1 +/*description: .*/ +#define MCPWM_TZ1_OST_ON (BIT(1)) +#define MCPWM_TZ1_OST_ON_M (BIT(1)) +#define MCPWM_TZ1_OST_ON_V 0x1 +#define MCPWM_TZ1_OST_ON_S 1 /* MCPWM_TZ1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_CBC_ON (BIT(0)) -#define MCPWM_TZ1_CBC_ON_M (BIT(0)) -#define MCPWM_TZ1_CBC_ON_V 0x1 -#define MCPWM_TZ1_CBC_ON_S 0 +/*description: .*/ +#define MCPWM_TZ1_CBC_ON (BIT(0)) +#define MCPWM_TZ1_CBC_ON_M (BIT(0)) +#define MCPWM_TZ1_CBC_ON_V 0x1 +#define MCPWM_TZ1_CBC_ON_S 0 -#define MCPWM_CMPR2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00ac) +#define MCPWM_CMPR2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xAC) /* MCPWM_CMPR2_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_B_SHDW_FULL (BIT(9)) -#define MCPWM_CMPR2_B_SHDW_FULL_M (BIT(9)) -#define MCPWM_CMPR2_B_SHDW_FULL_V 0x1 -#define MCPWM_CMPR2_B_SHDW_FULL_S 9 +/*description: .*/ +#define MCPWM_CMPR2_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR2_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_CMPR2_B_SHDW_FULL_V 0x1 +#define MCPWM_CMPR2_B_SHDW_FULL_S 9 /* MCPWM_CMPR2_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_A_SHDW_FULL (BIT(8)) -#define MCPWM_CMPR2_A_SHDW_FULL_M (BIT(8)) -#define MCPWM_CMPR2_A_SHDW_FULL_V 0x1 -#define MCPWM_CMPR2_A_SHDW_FULL_S 8 +/*description: .*/ +#define MCPWM_CMPR2_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR2_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_CMPR2_A_SHDW_FULL_V 0x1 +#define MCPWM_CMPR2_A_SHDW_FULL_S 8 /* MCPWM_CMPR2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ -#define MCPWM_CMPR2_B_UPMETHOD 0x0000000F -#define MCPWM_CMPR2_B_UPMETHOD_M ((MCPWM_CMPR2_B_UPMETHOD_V) << (MCPWM_CMPR2_B_UPMETHOD_S)) -#define MCPWM_CMPR2_B_UPMETHOD_V 0xF -#define MCPWM_CMPR2_B_UPMETHOD_S 4 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ +#define MCPWM_CMPR2_B_UPMETHOD 0x0000000F +#define MCPWM_CMPR2_B_UPMETHOD_M ((MCPWM_CMPR2_B_UPMETHOD_V)<<(MCPWM_CMPR2_B_UPMETHOD_S)) +#define MCPWM_CMPR2_B_UPMETHOD_V 0xF +#define MCPWM_CMPR2_B_UPMETHOD_S 4 /* MCPWM_CMPR2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ -#define MCPWM_CMPR2_A_UPMETHOD 0x0000000F -#define MCPWM_CMPR2_A_UPMETHOD_M ((MCPWM_CMPR2_A_UPMETHOD_V) << (MCPWM_CMPR2_A_UPMETHOD_S)) -#define MCPWM_CMPR2_A_UPMETHOD_V 0xF -#define MCPWM_CMPR2_A_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze.*/ +#define MCPWM_CMPR2_A_UPMETHOD 0x0000000F +#define MCPWM_CMPR2_A_UPMETHOD_M ((MCPWM_CMPR2_A_UPMETHOD_V)<<(MCPWM_CMPR2_A_UPMETHOD_S)) +#define MCPWM_CMPR2_A_UPMETHOD_V 0xF +#define MCPWM_CMPR2_A_UPMETHOD_S 0 -#define MCPWM_CMPR2_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x00b0) +#define MCPWM_CMPR2_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0xB0) /* MCPWM_CMPR2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_A 0x0000FFFF -#define MCPWM_CMPR2_A_M ((MCPWM_CMPR2_A_V) << (MCPWM_CMPR2_A_S)) -#define MCPWM_CMPR2_A_V 0xFFFF -#define MCPWM_CMPR2_A_S 0 +/*description: .*/ +#define MCPWM_CMPR2_A 0x0000FFFF +#define MCPWM_CMPR2_A_M ((MCPWM_CMPR2_A_V)<<(MCPWM_CMPR2_A_S)) +#define MCPWM_CMPR2_A_V 0xFFFF +#define MCPWM_CMPR2_A_S 0 -#define MCPWM_CMPR2_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x00b4) +#define MCPWM_CMPR2_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0xB4) /* MCPWM_CMPR2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_B 0x0000FFFF -#define MCPWM_CMPR2_B_M ((MCPWM_CMPR2_B_V) << (MCPWM_CMPR2_B_S)) -#define MCPWM_CMPR2_B_V 0xFFFF -#define MCPWM_CMPR2_B_S 0 +/*description: .*/ +#define MCPWM_CMPR2_B 0x0000FFFF +#define MCPWM_CMPR2_B_M ((MCPWM_CMPR2_B_V)<<(MCPWM_CMPR2_B_S)) +#define MCPWM_CMPR2_B_V 0xFFFF +#define MCPWM_CMPR2_B_S 0 -#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00b8) +#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xB8) /* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ -/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ -#define MCPWM_GEN2_T1_SEL 0x00000007 -#define MCPWM_GEN2_T1_SEL_M ((MCPWM_GEN2_T1_SEL_V) << (MCPWM_GEN2_T1_SEL_S)) -#define MCPWM_GEN2_T1_SEL_V 0x7 -#define MCPWM_GEN2_T1_SEL_S 7 +/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ +#define MCPWM_GEN2_T1_SEL 0x00000007 +#define MCPWM_GEN2_T1_SEL_M ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S)) +#define MCPWM_GEN2_T1_SEL_V 0x7 +#define MCPWM_GEN2_T1_SEL_S 7 /* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ -/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ -#define MCPWM_GEN2_T0_SEL 0x00000007 -#define MCPWM_GEN2_T0_SEL_M ((MCPWM_GEN2_T0_SEL_V) << (MCPWM_GEN2_T0_SEL_S)) -#define MCPWM_GEN2_T0_SEL_V 0x7 -#define MCPWM_GEN2_T0_SEL_S 4 +/*description: take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none.*/ +#define MCPWM_GEN2_T0_SEL 0x00000007 +#define MCPWM_GEN2_T0_SEL_M ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S)) +#define MCPWM_GEN2_T0_SEL_V 0x7 +#define MCPWM_GEN2_T0_SEL_S 4 /* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/ -#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000F -#define MCPWM_GEN2_CFG_UPMETHOD_M ((MCPWM_GEN2_CFG_UPMETHOD_V) << (MCPWM_GEN2_CFG_UPMETHOD_S)) -#define MCPWM_GEN2_CFG_UPMETHOD_V 0xF -#define MCPWM_GEN2_CFG_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze.*/ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN2_CFG_UPMETHOD_M ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S)) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 -#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x00bc) +#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xBC) /* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN2_B_NCIFORCE_MODE_M ((MCPWM_GEN2_B_NCIFORCE_MODE_V) << (MCPWM_GEN2_B_NCIFORCE_MODE_S)) -#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN2_B_NCIFORCE_MODE_M ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 /* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force a toggle will trigger a force event*/ -#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_M (BIT(13)) -#define MCPWM_GEN2_B_NCIFORCE_V 0x1 -#define MCPWM_GEN2_B_NCIFORCE_S 13 +/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_V 0x1 +#define MCPWM_GEN2_B_NCIFORCE_S 13 /* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003 -#define MCPWM_GEN2_A_NCIFORCE_MODE_M ((MCPWM_GEN2_A_NCIFORCE_MODE_V) << (MCPWM_GEN2_A_NCIFORCE_MODE_S)) -#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x3 -#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN2_A_NCIFORCE_MODE_M ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 /* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: non-continuous immediate sw force a toggle will trigger a force event*/ -#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_M (BIT(10)) -#define MCPWM_GEN2_A_NCIFORCE_V 0x1 -#define MCPWM_GEN2_A_NCIFORCE_S 10 +/*description: non-continuous immediate sw force, a toggle will trigger a force event.*/ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_V 0x1 +#define MCPWM_GEN2_A_NCIFORCE_S 10 /* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN2_B_CNTUFORCE_MODE_M ((MCPWM_GEN2_B_CNTUFORCE_MODE_V) << (MCPWM_GEN2_B_CNTUFORCE_MODE_S)) -#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 /* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: 0: disabled 1: low 2: high 3: disabled*/ -#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003 -#define MCPWM_GEN2_A_CNTUFORCE_MODE_M ((MCPWM_GEN2_A_CNTUFORCE_MODE_V) << (MCPWM_GEN2_A_CNTUFORCE_MODE_S)) -#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x3 -#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/*description: 0: disabled, 1: low, 2: high, 3: disabled.*/ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 /* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: 0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: - sync bit5: freeze*/ -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003F -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V) << (MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)) -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x3F -#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/*description: 0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: free +ze.*/ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 -#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0x00c0) +#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xC0) /* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: no change 1: low 2: high 3: toggle*/ -#define MCPWM_GEN2_A_DT1 0x00000003 -#define MCPWM_GEN2_A_DT1_M ((MCPWM_GEN2_A_DT1_V) << (MCPWM_GEN2_A_DT1_S)) -#define MCPWM_GEN2_A_DT1_V 0x3 -#define MCPWM_GEN2_A_DT1_S 22 +/*description: 0: no change, 1: low, 2: high, 3: toggle.*/ +#define MCPWM_GEN2_A_DT1 0x00000003 +#define MCPWM_GEN2_A_DT1_M ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S)) +#define MCPWM_GEN2_A_DT1_V 0x3 +#define MCPWM_GEN2_A_DT1_S 22 /* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_DT0 0x00000003 -#define MCPWM_GEN2_A_DT0_M ((MCPWM_GEN2_A_DT0_V) << (MCPWM_GEN2_A_DT0_S)) -#define MCPWM_GEN2_A_DT0_V 0x3 -#define MCPWM_GEN2_A_DT0_S 20 +/*description: .*/ +#define MCPWM_GEN2_A_DT0 0x00000003 +#define MCPWM_GEN2_A_DT0_M ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S)) +#define MCPWM_GEN2_A_DT0_V 0x3 +#define MCPWM_GEN2_A_DT0_S 20 /* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_DTEB 0x00000003 -#define MCPWM_GEN2_A_DTEB_M ((MCPWM_GEN2_A_DTEB_V) << (MCPWM_GEN2_A_DTEB_S)) -#define MCPWM_GEN2_A_DTEB_V 0x3 -#define MCPWM_GEN2_A_DTEB_S 18 +/*description: .*/ +#define MCPWM_GEN2_A_DTEB 0x00000003 +#define MCPWM_GEN2_A_DTEB_M ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S)) +#define MCPWM_GEN2_A_DTEB_V 0x3 +#define MCPWM_GEN2_A_DTEB_S 18 /* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_DTEA 0x00000003 -#define MCPWM_GEN2_A_DTEA_M ((MCPWM_GEN2_A_DTEA_V) << (MCPWM_GEN2_A_DTEA_S)) -#define MCPWM_GEN2_A_DTEA_V 0x3 -#define MCPWM_GEN2_A_DTEA_S 16 +/*description: .*/ +#define MCPWM_GEN2_A_DTEA 0x00000003 +#define MCPWM_GEN2_A_DTEA_M ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S)) +#define MCPWM_GEN2_A_DTEA_V 0x3 +#define MCPWM_GEN2_A_DTEA_S 16 /* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_DTEP 0x00000003 -#define MCPWM_GEN2_A_DTEP_M ((MCPWM_GEN2_A_DTEP_V) << (MCPWM_GEN2_A_DTEP_S)) -#define MCPWM_GEN2_A_DTEP_V 0x3 -#define MCPWM_GEN2_A_DTEP_S 14 +/*description: .*/ +#define MCPWM_GEN2_A_DTEP 0x00000003 +#define MCPWM_GEN2_A_DTEP_M ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S)) +#define MCPWM_GEN2_A_DTEP_V 0x3 +#define MCPWM_GEN2_A_DTEP_S 14 /* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_DTEZ 0x00000003 -#define MCPWM_GEN2_A_DTEZ_M ((MCPWM_GEN2_A_DTEZ_V) << (MCPWM_GEN2_A_DTEZ_S)) -#define MCPWM_GEN2_A_DTEZ_V 0x3 -#define MCPWM_GEN2_A_DTEZ_S 12 +/*description: .*/ +#define MCPWM_GEN2_A_DTEZ 0x00000003 +#define MCPWM_GEN2_A_DTEZ_M ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S)) +#define MCPWM_GEN2_A_DTEZ_V 0x3 +#define MCPWM_GEN2_A_DTEZ_S 12 /* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_UT1 0x00000003 -#define MCPWM_GEN2_A_UT1_M ((MCPWM_GEN2_A_UT1_V) << (MCPWM_GEN2_A_UT1_S)) -#define MCPWM_GEN2_A_UT1_V 0x3 -#define MCPWM_GEN2_A_UT1_S 10 +/*description: .*/ +#define MCPWM_GEN2_A_UT1 0x00000003 +#define MCPWM_GEN2_A_UT1_M ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S)) +#define MCPWM_GEN2_A_UT1_V 0x3 +#define MCPWM_GEN2_A_UT1_S 10 /* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_UT0 0x00000003 -#define MCPWM_GEN2_A_UT0_M ((MCPWM_GEN2_A_UT0_V) << (MCPWM_GEN2_A_UT0_S)) -#define MCPWM_GEN2_A_UT0_V 0x3 -#define MCPWM_GEN2_A_UT0_S 8 +/*description: .*/ +#define MCPWM_GEN2_A_UT0 0x00000003 +#define MCPWM_GEN2_A_UT0_M ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S)) +#define MCPWM_GEN2_A_UT0_V 0x3 +#define MCPWM_GEN2_A_UT0_S 8 /* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_UTEB 0x00000003 -#define MCPWM_GEN2_A_UTEB_M ((MCPWM_GEN2_A_UTEB_V) << (MCPWM_GEN2_A_UTEB_S)) -#define MCPWM_GEN2_A_UTEB_V 0x3 -#define MCPWM_GEN2_A_UTEB_S 6 +/*description: .*/ +#define MCPWM_GEN2_A_UTEB 0x00000003 +#define MCPWM_GEN2_A_UTEB_M ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S)) +#define MCPWM_GEN2_A_UTEB_V 0x3 +#define MCPWM_GEN2_A_UTEB_S 6 /* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_UTEA 0x00000003 -#define MCPWM_GEN2_A_UTEA_M ((MCPWM_GEN2_A_UTEA_V) << (MCPWM_GEN2_A_UTEA_S)) -#define MCPWM_GEN2_A_UTEA_V 0x3 -#define MCPWM_GEN2_A_UTEA_S 4 +/*description: .*/ +#define MCPWM_GEN2_A_UTEA 0x00000003 +#define MCPWM_GEN2_A_UTEA_M ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S)) +#define MCPWM_GEN2_A_UTEA_V 0x3 +#define MCPWM_GEN2_A_UTEA_S 4 /* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_UTEP 0x00000003 -#define MCPWM_GEN2_A_UTEP_M ((MCPWM_GEN2_A_UTEP_V) << (MCPWM_GEN2_A_UTEP_S)) -#define MCPWM_GEN2_A_UTEP_V 0x3 -#define MCPWM_GEN2_A_UTEP_S 2 +/*description: .*/ +#define MCPWM_GEN2_A_UTEP 0x00000003 +#define MCPWM_GEN2_A_UTEP_M ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S)) +#define MCPWM_GEN2_A_UTEP_V 0x3 +#define MCPWM_GEN2_A_UTEP_S 2 /* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_A_UTEZ 0x00000003 -#define MCPWM_GEN2_A_UTEZ_M ((MCPWM_GEN2_A_UTEZ_V) << (MCPWM_GEN2_A_UTEZ_S)) -#define MCPWM_GEN2_A_UTEZ_V 0x3 -#define MCPWM_GEN2_A_UTEZ_S 0 +/*description: .*/ +#define MCPWM_GEN2_A_UTEZ 0x00000003 +#define MCPWM_GEN2_A_UTEZ_M ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S)) +#define MCPWM_GEN2_A_UTEZ_V 0x3 +#define MCPWM_GEN2_A_UTEZ_S 0 -#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0x00c4) +#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xC4) /* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_DT1 0x00000003 -#define MCPWM_GEN2_B_DT1_M ((MCPWM_GEN2_B_DT1_V) << (MCPWM_GEN2_B_DT1_S)) -#define MCPWM_GEN2_B_DT1_V 0x3 -#define MCPWM_GEN2_B_DT1_S 22 +/*description: .*/ +#define MCPWM_GEN2_B_DT1 0x00000003 +#define MCPWM_GEN2_B_DT1_M ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S)) +#define MCPWM_GEN2_B_DT1_V 0x3 +#define MCPWM_GEN2_B_DT1_S 22 /* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_DT0 0x00000003 -#define MCPWM_GEN2_B_DT0_M ((MCPWM_GEN2_B_DT0_V) << (MCPWM_GEN2_B_DT0_S)) -#define MCPWM_GEN2_B_DT0_V 0x3 -#define MCPWM_GEN2_B_DT0_S 20 +/*description: .*/ +#define MCPWM_GEN2_B_DT0 0x00000003 +#define MCPWM_GEN2_B_DT0_M ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S)) +#define MCPWM_GEN2_B_DT0_V 0x3 +#define MCPWM_GEN2_B_DT0_S 20 /* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_DTEB 0x00000003 -#define MCPWM_GEN2_B_DTEB_M ((MCPWM_GEN2_B_DTEB_V) << (MCPWM_GEN2_B_DTEB_S)) -#define MCPWM_GEN2_B_DTEB_V 0x3 -#define MCPWM_GEN2_B_DTEB_S 18 +/*description: .*/ +#define MCPWM_GEN2_B_DTEB 0x00000003 +#define MCPWM_GEN2_B_DTEB_M ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S)) +#define MCPWM_GEN2_B_DTEB_V 0x3 +#define MCPWM_GEN2_B_DTEB_S 18 /* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_DTEA 0x00000003 -#define MCPWM_GEN2_B_DTEA_M ((MCPWM_GEN2_B_DTEA_V) << (MCPWM_GEN2_B_DTEA_S)) -#define MCPWM_GEN2_B_DTEA_V 0x3 -#define MCPWM_GEN2_B_DTEA_S 16 +/*description: .*/ +#define MCPWM_GEN2_B_DTEA 0x00000003 +#define MCPWM_GEN2_B_DTEA_M ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S)) +#define MCPWM_GEN2_B_DTEA_V 0x3 +#define MCPWM_GEN2_B_DTEA_S 16 /* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_DTEP 0x00000003 -#define MCPWM_GEN2_B_DTEP_M ((MCPWM_GEN2_B_DTEP_V) << (MCPWM_GEN2_B_DTEP_S)) -#define MCPWM_GEN2_B_DTEP_V 0x3 -#define MCPWM_GEN2_B_DTEP_S 14 +/*description: .*/ +#define MCPWM_GEN2_B_DTEP 0x00000003 +#define MCPWM_GEN2_B_DTEP_M ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S)) +#define MCPWM_GEN2_B_DTEP_V 0x3 +#define MCPWM_GEN2_B_DTEP_S 14 /* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_DTEZ 0x00000003 -#define MCPWM_GEN2_B_DTEZ_M ((MCPWM_GEN2_B_DTEZ_V) << (MCPWM_GEN2_B_DTEZ_S)) -#define MCPWM_GEN2_B_DTEZ_V 0x3 -#define MCPWM_GEN2_B_DTEZ_S 12 +/*description: .*/ +#define MCPWM_GEN2_B_DTEZ 0x00000003 +#define MCPWM_GEN2_B_DTEZ_M ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S)) +#define MCPWM_GEN2_B_DTEZ_V 0x3 +#define MCPWM_GEN2_B_DTEZ_S 12 /* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_UT1 0x00000003 -#define MCPWM_GEN2_B_UT1_M ((MCPWM_GEN2_B_UT1_V) << (MCPWM_GEN2_B_UT1_S)) -#define MCPWM_GEN2_B_UT1_V 0x3 -#define MCPWM_GEN2_B_UT1_S 10 +/*description: .*/ +#define MCPWM_GEN2_B_UT1 0x00000003 +#define MCPWM_GEN2_B_UT1_M ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S)) +#define MCPWM_GEN2_B_UT1_V 0x3 +#define MCPWM_GEN2_B_UT1_S 10 /* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_UT0 0x00000003 -#define MCPWM_GEN2_B_UT0_M ((MCPWM_GEN2_B_UT0_V) << (MCPWM_GEN2_B_UT0_S)) -#define MCPWM_GEN2_B_UT0_V 0x3 -#define MCPWM_GEN2_B_UT0_S 8 +/*description: .*/ +#define MCPWM_GEN2_B_UT0 0x00000003 +#define MCPWM_GEN2_B_UT0_M ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S)) +#define MCPWM_GEN2_B_UT0_V 0x3 +#define MCPWM_GEN2_B_UT0_S 8 /* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_UTEB 0x00000003 -#define MCPWM_GEN2_B_UTEB_M ((MCPWM_GEN2_B_UTEB_V) << (MCPWM_GEN2_B_UTEB_S)) -#define MCPWM_GEN2_B_UTEB_V 0x3 -#define MCPWM_GEN2_B_UTEB_S 6 +/*description: .*/ +#define MCPWM_GEN2_B_UTEB 0x00000003 +#define MCPWM_GEN2_B_UTEB_M ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S)) +#define MCPWM_GEN2_B_UTEB_V 0x3 +#define MCPWM_GEN2_B_UTEB_S 6 /* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_UTEA 0x00000003 -#define MCPWM_GEN2_B_UTEA_M ((MCPWM_GEN2_B_UTEA_V) << (MCPWM_GEN2_B_UTEA_S)) -#define MCPWM_GEN2_B_UTEA_V 0x3 -#define MCPWM_GEN2_B_UTEA_S 4 +/*description: .*/ +#define MCPWM_GEN2_B_UTEA 0x00000003 +#define MCPWM_GEN2_B_UTEA_M ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S)) +#define MCPWM_GEN2_B_UTEA_V 0x3 +#define MCPWM_GEN2_B_UTEA_S 4 /* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_UTEP 0x00000003 -#define MCPWM_GEN2_B_UTEP_M ((MCPWM_GEN2_B_UTEP_V) << (MCPWM_GEN2_B_UTEP_S)) -#define MCPWM_GEN2_B_UTEP_V 0x3 -#define MCPWM_GEN2_B_UTEP_S 2 +/*description: .*/ +#define MCPWM_GEN2_B_UTEP 0x00000003 +#define MCPWM_GEN2_B_UTEP_M ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S)) +#define MCPWM_GEN2_B_UTEP_V 0x3 +#define MCPWM_GEN2_B_UTEP_S 2 /* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_GEN2_B_UTEZ 0x00000003 -#define MCPWM_GEN2_B_UTEZ_M ((MCPWM_GEN2_B_UTEZ_V) << (MCPWM_GEN2_B_UTEZ_S)) -#define MCPWM_GEN2_B_UTEZ_V 0x3 -#define MCPWM_GEN2_B_UTEZ_S 0 +/*description: .*/ +#define MCPWM_GEN2_B_UTEZ 0x00000003 +#define MCPWM_GEN2_B_UTEZ_M ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S)) +#define MCPWM_GEN2_B_UTEZ_V 0x3 +#define MCPWM_GEN2_B_UTEZ_S 0 -#define MCPWM_DB2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00c8) +#define MCPWM_DB2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xC8) /* MCPWM_DB2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB2_CLK_SEL (BIT(17)) -#define MCPWM_DB2_CLK_SEL_M (BIT(17)) -#define MCPWM_DB2_CLK_SEL_V 0x1 -#define MCPWM_DB2_CLK_SEL_S 17 +/*description: .*/ +#define MCPWM_DB2_CLK_SEL (BIT(17)) +#define MCPWM_DB2_CLK_SEL_M (BIT(17)) +#define MCPWM_DB2_CLK_SEL_V 0x1 +#define MCPWM_DB2_CLK_SEL_S 17 /* MCPWM_DB2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_DB2_B_OUTBYPASS (BIT(16)) -#define MCPWM_DB2_B_OUTBYPASS_M (BIT(16)) -#define MCPWM_DB2_B_OUTBYPASS_V 0x1 -#define MCPWM_DB2_B_OUTBYPASS_S 16 +/*description: .*/ +#define MCPWM_DB2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB2_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DB2_B_OUTBYPASS_V 0x1 +#define MCPWM_DB2_B_OUTBYPASS_S 16 /* MCPWM_DB2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_DB2_A_OUTBYPASS (BIT(15)) -#define MCPWM_DB2_A_OUTBYPASS_M (BIT(15)) -#define MCPWM_DB2_A_OUTBYPASS_V 0x1 -#define MCPWM_DB2_A_OUTBYPASS_S 15 +/*description: .*/ +#define MCPWM_DB2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB2_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DB2_A_OUTBYPASS_V 0x1 +#define MCPWM_DB2_A_OUTBYPASS_S 15 /* MCPWM_DB2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB2_FED_OUTINVERT (BIT(14)) -#define MCPWM_DB2_FED_OUTINVERT_M (BIT(14)) -#define MCPWM_DB2_FED_OUTINVERT_V 0x1 -#define MCPWM_DB2_FED_OUTINVERT_S 14 +/*description: .*/ +#define MCPWM_DB2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB2_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DB2_FED_OUTINVERT_V 0x1 +#define MCPWM_DB2_FED_OUTINVERT_S 14 /* MCPWM_DB2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB2_RED_OUTINVERT (BIT(13)) -#define MCPWM_DB2_RED_OUTINVERT_M (BIT(13)) -#define MCPWM_DB2_RED_OUTINVERT_V 0x1 -#define MCPWM_DB2_RED_OUTINVERT_S 13 +/*description: .*/ +#define MCPWM_DB2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB2_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DB2_RED_OUTINVERT_V 0x1 +#define MCPWM_DB2_RED_OUTINVERT_S 13 /* MCPWM_DB2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB2_FED_INSEL (BIT(12)) -#define MCPWM_DB2_FED_INSEL_M (BIT(12)) -#define MCPWM_DB2_FED_INSEL_V 0x1 -#define MCPWM_DB2_FED_INSEL_S 12 +/*description: .*/ +#define MCPWM_DB2_FED_INSEL (BIT(12)) +#define MCPWM_DB2_FED_INSEL_M (BIT(12)) +#define MCPWM_DB2_FED_INSEL_V 0x1 +#define MCPWM_DB2_FED_INSEL_S 12 /* MCPWM_DB2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB2_RED_INSEL (BIT(11)) -#define MCPWM_DB2_RED_INSEL_M (BIT(11)) -#define MCPWM_DB2_RED_INSEL_V 0x1 -#define MCPWM_DB2_RED_INSEL_S 11 +/*description: .*/ +#define MCPWM_DB2_RED_INSEL (BIT(11)) +#define MCPWM_DB2_RED_INSEL_M (BIT(11)) +#define MCPWM_DB2_RED_INSEL_V 0x1 +#define MCPWM_DB2_RED_INSEL_S 11 /* MCPWM_DB2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB2_B_OUTSWAP (BIT(10)) -#define MCPWM_DB2_B_OUTSWAP_M (BIT(10)) -#define MCPWM_DB2_B_OUTSWAP_V 0x1 -#define MCPWM_DB2_B_OUTSWAP_S 10 +/*description: .*/ +#define MCPWM_DB2_B_OUTSWAP (BIT(10)) +#define MCPWM_DB2_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DB2_B_OUTSWAP_V 0x1 +#define MCPWM_DB2_B_OUTSWAP_S 10 /* MCPWM_DB2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB2_A_OUTSWAP (BIT(9)) -#define MCPWM_DB2_A_OUTSWAP_M (BIT(9)) -#define MCPWM_DB2_A_OUTSWAP_V 0x1 -#define MCPWM_DB2_A_OUTSWAP_S 9 +/*description: .*/ +#define MCPWM_DB2_A_OUTSWAP (BIT(9)) +#define MCPWM_DB2_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DB2_A_OUTSWAP_V 0x1 +#define MCPWM_DB2_A_OUTSWAP_S 9 /* MCPWM_DB2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_DB2_DEB_MODE (BIT(8)) -#define MCPWM_DB2_DEB_MODE_M (BIT(8)) -#define MCPWM_DB2_DEB_MODE_V 0x1 -#define MCPWM_DB2_DEB_MODE_S 8 +/*description: .*/ +#define MCPWM_DB2_DEB_MODE (BIT(8)) +#define MCPWM_DB2_DEB_MODE_M (BIT(8)) +#define MCPWM_DB2_DEB_MODE_V 0x1 +#define MCPWM_DB2_DEB_MODE_S 8 /* MCPWM_DB2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_DB2_RED_UPMETHOD 0x0000000F -#define MCPWM_DB2_RED_UPMETHOD_M ((MCPWM_DB2_RED_UPMETHOD_V) << (MCPWM_DB2_RED_UPMETHOD_S)) -#define MCPWM_DB2_RED_UPMETHOD_V 0xF -#define MCPWM_DB2_RED_UPMETHOD_S 4 +/*description: .*/ +#define MCPWM_DB2_RED_UPMETHOD 0x0000000F +#define MCPWM_DB2_RED_UPMETHOD_M ((MCPWM_DB2_RED_UPMETHOD_V)<<(MCPWM_DB2_RED_UPMETHOD_S)) +#define MCPWM_DB2_RED_UPMETHOD_V 0xF +#define MCPWM_DB2_RED_UPMETHOD_S 4 /* MCPWM_DB2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_DB2_FED_UPMETHOD 0x0000000F -#define MCPWM_DB2_FED_UPMETHOD_M ((MCPWM_DB2_FED_UPMETHOD_V) << (MCPWM_DB2_FED_UPMETHOD_S)) -#define MCPWM_DB2_FED_UPMETHOD_V 0xF -#define MCPWM_DB2_FED_UPMETHOD_S 0 +/*description: .*/ +#define MCPWM_DB2_FED_UPMETHOD 0x0000000F +#define MCPWM_DB2_FED_UPMETHOD_M ((MCPWM_DB2_FED_UPMETHOD_V)<<(MCPWM_DB2_FED_UPMETHOD_S)) +#define MCPWM_DB2_FED_UPMETHOD_V 0xF +#define MCPWM_DB2_FED_UPMETHOD_S 0 -#define MCPWM_DB2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00cc) +#define MCPWM_DB2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xCC) /* MCPWM_DB2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_DB2_FED 0x0000FFFF -#define MCPWM_DB2_FED_M ((MCPWM_DB2_FED_V) << (MCPWM_DB2_FED_S)) -#define MCPWM_DB2_FED_V 0xFFFF -#define MCPWM_DB2_FED_S 0 +/*description: .*/ +#define MCPWM_DB2_FED 0x0000FFFF +#define MCPWM_DB2_FED_M ((MCPWM_DB2_FED_V)<<(MCPWM_DB2_FED_S)) +#define MCPWM_DB2_FED_V 0xFFFF +#define MCPWM_DB2_FED_S 0 -#define MCPWM_DB2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d0) +#define MCPWM_DB2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xD0) /* MCPWM_DB2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ -/*description: */ -#define MCPWM_DB2_RED 0x0000FFFF -#define MCPWM_DB2_RED_M ((MCPWM_DB2_RED_V) << (MCPWM_DB2_RED_S)) -#define MCPWM_DB2_RED_V 0xFFFF -#define MCPWM_DB2_RED_S 0 +/*description: .*/ +#define MCPWM_DB2_RED 0x0000FFFF +#define MCPWM_DB2_RED_M ((MCPWM_DB2_RED_V)<<(MCPWM_DB2_RED_S)) +#define MCPWM_DB2_RED_V 0xFFFF +#define MCPWM_DB2_RED_S 0 -#define MCPWM_CHOPPER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d4) +#define MCPWM_CHOPPER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xD4) /* MCPWM_CHOPPER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) -#define MCPWM_CHOPPER2_IN_INVERT_M (BIT(13)) -#define MCPWM_CHOPPER2_IN_INVERT_V 0x1 -#define MCPWM_CHOPPER2_IN_INVERT_S 13 +/*description: .*/ +#define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER2_IN_INVERT_M (BIT(13)) +#define MCPWM_CHOPPER2_IN_INVERT_V 0x1 +#define MCPWM_CHOPPER2_IN_INVERT_S 13 /* MCPWM_CHOPPER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) -#define MCPWM_CHOPPER2_OUT_INVERT_M (BIT(12)) -#define MCPWM_CHOPPER2_OUT_INVERT_V 0x1 -#define MCPWM_CHOPPER2_OUT_INVERT_S 12 +/*description: .*/ +#define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER2_OUT_INVERT_M (BIT(12)) +#define MCPWM_CHOPPER2_OUT_INVERT_V 0x1 +#define MCPWM_CHOPPER2_OUT_INVERT_S 12 /* MCPWM_CHOPPER2_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER2_OSHTWTH 0x0000000F -#define MCPWM_CHOPPER2_OSHTWTH_M ((MCPWM_CHOPPER2_OSHTWTH_V) << (MCPWM_CHOPPER2_OSHTWTH_S)) -#define MCPWM_CHOPPER2_OSHTWTH_V 0xF -#define MCPWM_CHOPPER2_OSHTWTH_S 8 +/*description: .*/ +#define MCPWM_CHOPPER2_OSHTWTH 0x0000000F +#define MCPWM_CHOPPER2_OSHTWTH_M ((MCPWM_CHOPPER2_OSHTWTH_V)<<(MCPWM_CHOPPER2_OSHTWTH_S)) +#define MCPWM_CHOPPER2_OSHTWTH_V 0xF +#define MCPWM_CHOPPER2_OSHTWTH_S 8 /* MCPWM_CHOPPER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER2_DUTY 0x00000007 -#define MCPWM_CHOPPER2_DUTY_M ((MCPWM_CHOPPER2_DUTY_V) << (MCPWM_CHOPPER2_DUTY_S)) -#define MCPWM_CHOPPER2_DUTY_V 0x7 -#define MCPWM_CHOPPER2_DUTY_S 5 +/*description: .*/ +#define MCPWM_CHOPPER2_DUTY 0x00000007 +#define MCPWM_CHOPPER2_DUTY_M ((MCPWM_CHOPPER2_DUTY_V)<<(MCPWM_CHOPPER2_DUTY_S)) +#define MCPWM_CHOPPER2_DUTY_V 0x7 +#define MCPWM_CHOPPER2_DUTY_S 5 /* MCPWM_CHOPPER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER2_PRESCALE 0x0000000F -#define MCPWM_CHOPPER2_PRESCALE_M ((MCPWM_CHOPPER2_PRESCALE_V) << (MCPWM_CHOPPER2_PRESCALE_S)) -#define MCPWM_CHOPPER2_PRESCALE_V 0xF -#define MCPWM_CHOPPER2_PRESCALE_S 1 +/*description: .*/ +#define MCPWM_CHOPPER2_PRESCALE 0x0000000F +#define MCPWM_CHOPPER2_PRESCALE_M ((MCPWM_CHOPPER2_PRESCALE_V)<<(MCPWM_CHOPPER2_PRESCALE_S)) +#define MCPWM_CHOPPER2_PRESCALE_V 0xF +#define MCPWM_CHOPPER2_PRESCALE_S 1 /* MCPWM_CHOPPER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CHOPPER2_EN (BIT(0)) -#define MCPWM_CHOPPER2_EN_M (BIT(0)) -#define MCPWM_CHOPPER2_EN_V 0x1 -#define MCPWM_CHOPPER2_EN_S 0 +/*description: .*/ +#define MCPWM_CHOPPER2_EN (BIT(0)) +#define MCPWM_CHOPPER2_EN_M (BIT(0)) +#define MCPWM_CHOPPER2_EN_V 0x1 +#define MCPWM_CHOPPER2_EN_S 0 -#define MCPWM_TZ2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00d8) +#define MCPWM_TZ2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xD8) /* MCPWM_TZ2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ2_B_OST_U 0x00000003 -#define MCPWM_TZ2_B_OST_U_M ((MCPWM_TZ2_B_OST_U_V) << (MCPWM_TZ2_B_OST_U_S)) -#define MCPWM_TZ2_B_OST_U_V 0x3 -#define MCPWM_TZ2_B_OST_U_S 22 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ2_B_OST_U 0x00000003 +#define MCPWM_TZ2_B_OST_U_M ((MCPWM_TZ2_B_OST_U_V)<<(MCPWM_TZ2_B_OST_U_S)) +#define MCPWM_TZ2_B_OST_U_V 0x3 +#define MCPWM_TZ2_B_OST_U_S 22 /* MCPWM_TZ2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ2_B_OST_D 0x00000003 -#define MCPWM_TZ2_B_OST_D_M ((MCPWM_TZ2_B_OST_D_V) << (MCPWM_TZ2_B_OST_D_S)) -#define MCPWM_TZ2_B_OST_D_V 0x3 -#define MCPWM_TZ2_B_OST_D_S 20 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ2_B_OST_D 0x00000003 +#define MCPWM_TZ2_B_OST_D_M ((MCPWM_TZ2_B_OST_D_V)<<(MCPWM_TZ2_B_OST_D_S)) +#define MCPWM_TZ2_B_OST_D_V 0x3 +#define MCPWM_TZ2_B_OST_D_S 20 /* MCPWM_TZ2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ2_B_CBC_U 0x00000003 -#define MCPWM_TZ2_B_CBC_U_M ((MCPWM_TZ2_B_CBC_U_V) << (MCPWM_TZ2_B_CBC_U_S)) -#define MCPWM_TZ2_B_CBC_U_V 0x3 -#define MCPWM_TZ2_B_CBC_U_S 18 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ2_B_CBC_U 0x00000003 +#define MCPWM_TZ2_B_CBC_U_M ((MCPWM_TZ2_B_CBC_U_V)<<(MCPWM_TZ2_B_CBC_U_S)) +#define MCPWM_TZ2_B_CBC_U_V 0x3 +#define MCPWM_TZ2_B_CBC_U_S 18 /* MCPWM_TZ2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ2_B_CBC_D 0x00000003 -#define MCPWM_TZ2_B_CBC_D_M ((MCPWM_TZ2_B_CBC_D_V) << (MCPWM_TZ2_B_CBC_D_S)) -#define MCPWM_TZ2_B_CBC_D_V 0x3 -#define MCPWM_TZ2_B_CBC_D_S 16 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ2_B_CBC_D 0x00000003 +#define MCPWM_TZ2_B_CBC_D_M ((MCPWM_TZ2_B_CBC_D_V)<<(MCPWM_TZ2_B_CBC_D_S)) +#define MCPWM_TZ2_B_CBC_D_V 0x3 +#define MCPWM_TZ2_B_CBC_D_S 16 /* MCPWM_TZ2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ2_A_OST_U 0x00000003 -#define MCPWM_TZ2_A_OST_U_M ((MCPWM_TZ2_A_OST_U_V) << (MCPWM_TZ2_A_OST_U_S)) -#define MCPWM_TZ2_A_OST_U_V 0x3 -#define MCPWM_TZ2_A_OST_U_S 14 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ2_A_OST_U 0x00000003 +#define MCPWM_TZ2_A_OST_U_M ((MCPWM_TZ2_A_OST_U_V)<<(MCPWM_TZ2_A_OST_U_S)) +#define MCPWM_TZ2_A_OST_U_V 0x3 +#define MCPWM_TZ2_A_OST_U_S 14 /* MCPWM_TZ2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ2_A_OST_D 0x00000003 -#define MCPWM_TZ2_A_OST_D_M ((MCPWM_TZ2_A_OST_D_V) << (MCPWM_TZ2_A_OST_D_S)) -#define MCPWM_TZ2_A_OST_D_V 0x3 -#define MCPWM_TZ2_A_OST_D_S 12 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ2_A_OST_D 0x00000003 +#define MCPWM_TZ2_A_OST_D_M ((MCPWM_TZ2_A_OST_D_V)<<(MCPWM_TZ2_A_OST_D_S)) +#define MCPWM_TZ2_A_OST_D_V 0x3 +#define MCPWM_TZ2_A_OST_D_S 12 /* MCPWM_TZ2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ2_A_CBC_U 0x00000003 -#define MCPWM_TZ2_A_CBC_U_M ((MCPWM_TZ2_A_CBC_U_V) << (MCPWM_TZ2_A_CBC_U_S)) -#define MCPWM_TZ2_A_CBC_U_V 0x3 -#define MCPWM_TZ2_A_CBC_U_S 10 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ2_A_CBC_U 0x00000003 +#define MCPWM_TZ2_A_CBC_U_M ((MCPWM_TZ2_A_CBC_U_V)<<(MCPWM_TZ2_A_CBC_U_S)) +#define MCPWM_TZ2_A_CBC_U_V 0x3 +#define MCPWM_TZ2_A_CBC_U_S 10 /* MCPWM_TZ2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ -/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ -#define MCPWM_TZ2_A_CBC_D 0x00000003 -#define MCPWM_TZ2_A_CBC_D_M ((MCPWM_TZ2_A_CBC_D_V) << (MCPWM_TZ2_A_CBC_D_S)) -#define MCPWM_TZ2_A_CBC_D_V 0x3 -#define MCPWM_TZ2_A_CBC_D_S 8 +/*description: 0: do nothing, 1: force lo, 2: force hi, 3: toggle.*/ +#define MCPWM_TZ2_A_CBC_D 0x00000003 +#define MCPWM_TZ2_A_CBC_D_M ((MCPWM_TZ2_A_CBC_D_V)<<(MCPWM_TZ2_A_CBC_D_S)) +#define MCPWM_TZ2_A_CBC_D_V 0x3 +#define MCPWM_TZ2_A_CBC_D_S 8 /* MCPWM_TZ2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ2_F0_OST (BIT(7)) -#define MCPWM_TZ2_F0_OST_M (BIT(7)) -#define MCPWM_TZ2_F0_OST_V 0x1 -#define MCPWM_TZ2_F0_OST_S 7 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ2_F0_OST (BIT(7)) +#define MCPWM_TZ2_F0_OST_M (BIT(7)) +#define MCPWM_TZ2_F0_OST_V 0x1 +#define MCPWM_TZ2_F0_OST_S 7 /* MCPWM_TZ2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ2_F1_OST (BIT(6)) -#define MCPWM_TZ2_F1_OST_M (BIT(6)) -#define MCPWM_TZ2_F1_OST_V 0x1 -#define MCPWM_TZ2_F1_OST_S 6 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ2_F1_OST (BIT(6)) +#define MCPWM_TZ2_F1_OST_M (BIT(6)) +#define MCPWM_TZ2_F1_OST_V 0x1 +#define MCPWM_TZ2_F1_OST_S 6 /* MCPWM_TZ2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ2_F2_OST (BIT(5)) -#define MCPWM_TZ2_F2_OST_M (BIT(5)) -#define MCPWM_TZ2_F2_OST_V 0x1 -#define MCPWM_TZ2_F2_OST_S 5 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ2_F2_OST (BIT(5)) +#define MCPWM_TZ2_F2_OST_M (BIT(5)) +#define MCPWM_TZ2_F2_OST_V 0x1 +#define MCPWM_TZ2_F2_OST_S 5 /* MCPWM_TZ2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ2_SW_OST (BIT(4)) -#define MCPWM_TZ2_SW_OST_M (BIT(4)) -#define MCPWM_TZ2_SW_OST_V 0x1 -#define MCPWM_TZ2_SW_OST_S 4 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ2_SW_OST (BIT(4)) +#define MCPWM_TZ2_SW_OST_M (BIT(4)) +#define MCPWM_TZ2_SW_OST_V 0x1 +#define MCPWM_TZ2_SW_OST_S 4 /* MCPWM_TZ2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ2_F0_CBC (BIT(3)) -#define MCPWM_TZ2_F0_CBC_M (BIT(3)) -#define MCPWM_TZ2_F0_CBC_V 0x1 -#define MCPWM_TZ2_F0_CBC_S 3 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ2_F0_CBC (BIT(3)) +#define MCPWM_TZ2_F0_CBC_M (BIT(3)) +#define MCPWM_TZ2_F0_CBC_V 0x1 +#define MCPWM_TZ2_F0_CBC_S 3 /* MCPWM_TZ2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ2_F1_CBC (BIT(2)) -#define MCPWM_TZ2_F1_CBC_M (BIT(2)) -#define MCPWM_TZ2_F1_CBC_V 0x1 -#define MCPWM_TZ2_F1_CBC_S 2 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ2_F1_CBC (BIT(2)) +#define MCPWM_TZ2_F1_CBC_M (BIT(2)) +#define MCPWM_TZ2_F1_CBC_V 0x1 +#define MCPWM_TZ2_F1_CBC_S 2 /* MCPWM_TZ2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ2_F2_CBC (BIT(1)) -#define MCPWM_TZ2_F2_CBC_M (BIT(1)) -#define MCPWM_TZ2_F2_CBC_V 0x1 -#define MCPWM_TZ2_F2_CBC_S 1 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ2_F2_CBC (BIT(1)) +#define MCPWM_TZ2_F2_CBC_M (BIT(1)) +#define MCPWM_TZ2_F2_CBC_V 0x1 +#define MCPWM_TZ2_F2_CBC_S 1 /* MCPWM_TZ2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: 0: disable 1: enable*/ -#define MCPWM_TZ2_SW_CBC (BIT(0)) -#define MCPWM_TZ2_SW_CBC_M (BIT(0)) -#define MCPWM_TZ2_SW_CBC_V 0x1 -#define MCPWM_TZ2_SW_CBC_S 0 +/*description: 0: disable, 1: enable.*/ +#define MCPWM_TZ2_SW_CBC (BIT(0)) +#define MCPWM_TZ2_SW_CBC_M (BIT(0)) +#define MCPWM_TZ2_SW_CBC_V 0x1 +#define MCPWM_TZ2_SW_CBC_S 0 -#define MCPWM_TZ2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00dc) +#define MCPWM_TZ2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xDC) /* MCPWM_TZ2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: a toggle trigger a oneshot tripping*/ -#define MCPWM_TZ2_FORCE_OST (BIT(4)) -#define MCPWM_TZ2_FORCE_OST_M (BIT(4)) -#define MCPWM_TZ2_FORCE_OST_V 0x1 -#define MCPWM_TZ2_FORCE_OST_S 4 +/*description: a toggle trigger a oneshot tripping.*/ +#define MCPWM_TZ2_FORCE_OST (BIT(4)) +#define MCPWM_TZ2_FORCE_OST_M (BIT(4)) +#define MCPWM_TZ2_FORCE_OST_V 0x1 +#define MCPWM_TZ2_FORCE_OST_S 4 /* MCPWM_TZ2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: a toggle trigger a cycle-by-cycle tripping*/ -#define MCPWM_TZ2_FORCE_CBC (BIT(3)) -#define MCPWM_TZ2_FORCE_CBC_M (BIT(3)) -#define MCPWM_TZ2_FORCE_CBC_V 0x1 -#define MCPWM_TZ2_FORCE_CBC_S 3 +/*description: a toggle trigger a cycle-by-cycle tripping.*/ +#define MCPWM_TZ2_FORCE_CBC (BIT(3)) +#define MCPWM_TZ2_FORCE_CBC_M (BIT(3)) +#define MCPWM_TZ2_FORCE_CBC_V 0x1 +#define MCPWM_TZ2_FORCE_CBC_S 3 /* MCPWM_TZ2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: bit0: tez bit1: tep*/ -#define MCPWM_TZ2_CBCPULSE 0x00000003 -#define MCPWM_TZ2_CBCPULSE_M ((MCPWM_TZ2_CBCPULSE_V) << (MCPWM_TZ2_CBCPULSE_S)) -#define MCPWM_TZ2_CBCPULSE_V 0x3 -#define MCPWM_TZ2_CBCPULSE_S 1 +/*description: bit0: tez, bit1: tep.*/ +#define MCPWM_TZ2_CBCPULSE 0x00000003 +#define MCPWM_TZ2_CBCPULSE_M ((MCPWM_TZ2_CBCPULSE_V)<<(MCPWM_TZ2_CBCPULSE_S)) +#define MCPWM_TZ2_CBCPULSE_V 0x3 +#define MCPWM_TZ2_CBCPULSE_S 1 /* MCPWM_TZ2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: a toggle will clear oneshot tripping*/ -#define MCPWM_TZ2_CLR_OST (BIT(0)) -#define MCPWM_TZ2_CLR_OST_M (BIT(0)) -#define MCPWM_TZ2_CLR_OST_V 0x1 -#define MCPWM_TZ2_CLR_OST_S 0 +/*description: a toggle will clear oneshot tripping.*/ +#define MCPWM_TZ2_CLR_OST (BIT(0)) +#define MCPWM_TZ2_CLR_OST_M (BIT(0)) +#define MCPWM_TZ2_CLR_OST_V 0x1 +#define MCPWM_TZ2_CLR_OST_S 0 -#define MCPWM_TZ2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00e0) +#define MCPWM_TZ2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xE0) /* MCPWM_TZ2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_OST_ON (BIT(1)) -#define MCPWM_TZ2_OST_ON_M (BIT(1)) -#define MCPWM_TZ2_OST_ON_V 0x1 -#define MCPWM_TZ2_OST_ON_S 1 +/*description: .*/ +#define MCPWM_TZ2_OST_ON (BIT(1)) +#define MCPWM_TZ2_OST_ON_M (BIT(1)) +#define MCPWM_TZ2_OST_ON_V 0x1 +#define MCPWM_TZ2_OST_ON_S 1 /* MCPWM_TZ2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_CBC_ON (BIT(0)) -#define MCPWM_TZ2_CBC_ON_M (BIT(0)) -#define MCPWM_TZ2_CBC_ON_V 0x1 -#define MCPWM_TZ2_CBC_ON_S 0 +/*description: .*/ +#define MCPWM_TZ2_CBC_ON (BIT(0)) +#define MCPWM_TZ2_CBC_ON_M (BIT(0)) +#define MCPWM_TZ2_CBC_ON_V 0x1 +#define MCPWM_TZ2_CBC_ON_S 0 -#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0x00e4) +#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xE4) /* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_EVENT_F2 (BIT(8)) -#define MCPWM_EVENT_F2_M (BIT(8)) -#define MCPWM_EVENT_F2_V 0x1 -#define MCPWM_EVENT_F2_S 8 +/*description: .*/ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (BIT(8)) +#define MCPWM_EVENT_F2_V 0x1 +#define MCPWM_EVENT_F2_S 8 /* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_EVENT_F1 (BIT(7)) -#define MCPWM_EVENT_F1_M (BIT(7)) -#define MCPWM_EVENT_F1_V 0x1 -#define MCPWM_EVENT_F1_S 7 +/*description: .*/ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (BIT(7)) +#define MCPWM_EVENT_F1_V 0x1 +#define MCPWM_EVENT_F1_S 7 /* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_EVENT_F0 (BIT(6)) -#define MCPWM_EVENT_F0_M (BIT(6)) -#define MCPWM_EVENT_F0_V 0x1 -#define MCPWM_EVENT_F0_S 6 +/*description: .*/ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (BIT(6)) +#define MCPWM_EVENT_F0_V 0x1 +#define MCPWM_EVENT_F0_S 6 /* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_F2_POLE (BIT(5)) -#define MCPWM_F2_POLE_M (BIT(5)) -#define MCPWM_F2_POLE_V 0x1 -#define MCPWM_F2_POLE_S 5 +/*description: .*/ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (BIT(5)) +#define MCPWM_F2_POLE_V 0x1 +#define MCPWM_F2_POLE_S 5 /* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_F1_POLE (BIT(4)) -#define MCPWM_F1_POLE_M (BIT(4)) -#define MCPWM_F1_POLE_V 0x1 -#define MCPWM_F1_POLE_S 4 +/*description: .*/ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (BIT(4)) +#define MCPWM_F1_POLE_V 0x1 +#define MCPWM_F1_POLE_S 4 /* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_F0_POLE (BIT(3)) -#define MCPWM_F0_POLE_M (BIT(3)) -#define MCPWM_F0_POLE_V 0x1 -#define MCPWM_F0_POLE_S 3 +/*description: .*/ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (BIT(3)) +#define MCPWM_F0_POLE_V 0x1 +#define MCPWM_F0_POLE_S 3 /* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_F2_EN (BIT(2)) -#define MCPWM_F2_EN_M (BIT(2)) -#define MCPWM_F2_EN_V 0x1 -#define MCPWM_F2_EN_S 2 +/*description: .*/ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (BIT(2)) +#define MCPWM_F2_EN_V 0x1 +#define MCPWM_F2_EN_S 2 /* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_F1_EN (BIT(1)) -#define MCPWM_F1_EN_M (BIT(1)) -#define MCPWM_F1_EN_V 0x1 -#define MCPWM_F1_EN_S 1 +/*description: .*/ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (BIT(1)) +#define MCPWM_F1_EN_V 0x1 +#define MCPWM_F1_EN_S 1 /* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_F0_EN (BIT(0)) -#define MCPWM_F0_EN_M (BIT(0)) -#define MCPWM_F0_EN_V 0x1 -#define MCPWM_F0_EN_S 0 +/*description: .*/ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (BIT(0)) +#define MCPWM_F0_EN_V 0x1 +#define MCPWM_F0_EN_S 0 -#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00e8) +#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xE8) /* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */ -/*description: Write 1 will force a timer sync*/ -#define MCPWM_CAP_SYNC_SW (BIT(5)) -#define MCPWM_CAP_SYNC_SW_M (BIT(5)) -#define MCPWM_CAP_SYNC_SW_V 0x1 -#define MCPWM_CAP_SYNC_SW_S 5 +/*description: Write 1 will force a timer sync.*/ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (BIT(5)) +#define MCPWM_CAP_SYNC_SW_V 0x1 +#define MCPWM_CAP_SYNC_SW_S 5 /* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ -/*description: */ -#define MCPWM_CAP_SYNCI_SEL 0x00000007 -#define MCPWM_CAP_SYNCI_SEL_M ((MCPWM_CAP_SYNCI_SEL_V) << (MCPWM_CAP_SYNCI_SEL_S)) -#define MCPWM_CAP_SYNCI_SEL_V 0x7 -#define MCPWM_CAP_SYNCI_SEL_S 2 +/*description: .*/ +#define MCPWM_CAP_SYNCI_SEL 0x00000007 +#define MCPWM_CAP_SYNCI_SEL_M ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S)) +#define MCPWM_CAP_SYNCI_SEL_V 0x7 +#define MCPWM_CAP_SYNCI_SEL_S 2 /* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP_SYNCI_EN (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_M (BIT(1)) -#define MCPWM_CAP_SYNCI_EN_V 0x1 -#define MCPWM_CAP_SYNCI_EN_S 1 +/*description: .*/ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_V 0x1 +#define MCPWM_CAP_SYNCI_EN_S 1 /* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP_TIMER_EN (BIT(0)) -#define MCPWM_CAP_TIMER_EN_M (BIT(0)) -#define MCPWM_CAP_TIMER_EN_V 0x1 -#define MCPWM_CAP_TIMER_EN_S 0 +/*description: .*/ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (BIT(0)) +#define MCPWM_CAP_TIMER_EN_V 0x1 +#define MCPWM_CAP_TIMER_EN_S 0 -#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0x00ec) +#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xEC) /* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define MCPWM_CAP_PHASE 0xFFFFFFFF -#define MCPWM_CAP_PHASE_M ((MCPWM_CAP_PHASE_V) << (MCPWM_CAP_PHASE_S)) -#define MCPWM_CAP_PHASE_V 0xFFFFFFFF -#define MCPWM_CAP_PHASE_S 0 +/*description: .*/ +#define MCPWM_CAP_PHASE 0xFFFFFFFF +#define MCPWM_CAP_PHASE_M ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S)) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFF +#define MCPWM_CAP_PHASE_S 0 -#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f0) +#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xF0) /* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a sw capture*/ -#define MCPWM_CAP0_SW (BIT(12)) -#define MCPWM_CAP0_SW_M (BIT(12)) -#define MCPWM_CAP0_SW_V 0x1 -#define MCPWM_CAP0_SW_S 12 +/*description: Write 1 will trigger a sw capture.*/ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (BIT(12)) +#define MCPWM_CAP0_SW_V 0x1 +#define MCPWM_CAP0_SW_S 12 /* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP0_IN_INVERT (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP0_IN_INVERT_V 0x1 -#define MCPWM_CAP0_IN_INVERT_S 11 +/*description: .*/ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_V 0x1 +#define MCPWM_CAP0_IN_INVERT_S 11 /* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: */ -#define MCPWM_CAP0_PRESCALE 0x000000FF -#define MCPWM_CAP0_PRESCALE_M ((MCPWM_CAP0_PRESCALE_V) << (MCPWM_CAP0_PRESCALE_S)) -#define MCPWM_CAP0_PRESCALE_V 0xFF -#define MCPWM_CAP0_PRESCALE_S 3 +/*description: .*/ +#define MCPWM_CAP0_PRESCALE 0x000000FF +#define MCPWM_CAP0_PRESCALE_M ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S)) +#define MCPWM_CAP0_PRESCALE_V 0xFF +#define MCPWM_CAP0_PRESCALE_S 3 /* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: bit0: negedge cap en bit1: posedge cap en*/ -#define MCPWM_CAP0_MODE 0x00000003 -#define MCPWM_CAP0_MODE_M ((MCPWM_CAP0_MODE_V) << (MCPWM_CAP0_MODE_S)) -#define MCPWM_CAP0_MODE_V 0x3 -#define MCPWM_CAP0_MODE_S 1 +/*description: bit0: negedge cap en, bit1: posedge cap en.*/ +#define MCPWM_CAP0_MODE 0x00000003 +#define MCPWM_CAP0_MODE_M ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S)) +#define MCPWM_CAP0_MODE_V 0x3 +#define MCPWM_CAP0_MODE_S 1 /* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP0_EN (BIT(0)) -#define MCPWM_CAP0_EN_M (BIT(0)) -#define MCPWM_CAP0_EN_V 0x1 -#define MCPWM_CAP0_EN_S 0 +/*description: .*/ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (BIT(0)) +#define MCPWM_CAP0_EN_V 0x1 +#define MCPWM_CAP0_EN_S 0 -#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f4) +#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xF4) /* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a sw capture*/ -#define MCPWM_CAP1_SW (BIT(12)) -#define MCPWM_CAP1_SW_M (BIT(12)) -#define MCPWM_CAP1_SW_V 0x1 -#define MCPWM_CAP1_SW_S 12 +/*description: Write 1 will trigger a sw capture.*/ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (BIT(12)) +#define MCPWM_CAP1_SW_V 0x1 +#define MCPWM_CAP1_SW_S 12 /* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP1_IN_INVERT (BIT(11)) -#define MCPWM_CAP1_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP1_IN_INVERT_V 0x1 -#define MCPWM_CAP1_IN_INVERT_S 11 +/*description: .*/ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_V 0x1 +#define MCPWM_CAP1_IN_INVERT_S 11 /* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: */ -#define MCPWM_CAP1_PRESCALE 0x000000FF -#define MCPWM_CAP1_PRESCALE_M ((MCPWM_CAP1_PRESCALE_V) << (MCPWM_CAP1_PRESCALE_S)) -#define MCPWM_CAP1_PRESCALE_V 0xFF -#define MCPWM_CAP1_PRESCALE_S 3 +/*description: .*/ +#define MCPWM_CAP1_PRESCALE 0x000000FF +#define MCPWM_CAP1_PRESCALE_M ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S)) +#define MCPWM_CAP1_PRESCALE_V 0xFF +#define MCPWM_CAP1_PRESCALE_S 3 /* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_CAP1_MODE 0x00000003 -#define MCPWM_CAP1_MODE_M ((MCPWM_CAP1_MODE_V) << (MCPWM_CAP1_MODE_S)) -#define MCPWM_CAP1_MODE_V 0x3 -#define MCPWM_CAP1_MODE_S 1 +/*description: .*/ +#define MCPWM_CAP1_MODE 0x00000003 +#define MCPWM_CAP1_MODE_M ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S)) +#define MCPWM_CAP1_MODE_V 0x3 +#define MCPWM_CAP1_MODE_S 1 /* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP1_EN (BIT(0)) -#define MCPWM_CAP1_EN_M (BIT(0)) -#define MCPWM_CAP1_EN_V 0x1 -#define MCPWM_CAP1_EN_S 0 +/*description: .*/ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (BIT(0)) +#define MCPWM_CAP1_EN_V 0x1 +#define MCPWM_CAP1_EN_S 0 -#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f8) +#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xF8) /* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: Write 1 will trigger a sw capture*/ -#define MCPWM_CAP2_SW (BIT(12)) -#define MCPWM_CAP2_SW_M (BIT(12)) -#define MCPWM_CAP2_SW_V 0x1 -#define MCPWM_CAP2_SW_S 12 +/*description: Write 1 will trigger a sw capture.*/ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (BIT(12)) +#define MCPWM_CAP2_SW_V 0x1 +#define MCPWM_CAP2_SW_S 12 /* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP2_IN_INVERT (BIT(11)) -#define MCPWM_CAP2_IN_INVERT_M (BIT(11)) -#define MCPWM_CAP2_IN_INVERT_V 0x1 -#define MCPWM_CAP2_IN_INVERT_S 11 +/*description: .*/ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_V 0x1 +#define MCPWM_CAP2_IN_INVERT_S 11 /* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: */ -#define MCPWM_CAP2_PRESCALE 0x000000FF -#define MCPWM_CAP2_PRESCALE_M ((MCPWM_CAP2_PRESCALE_V) << (MCPWM_CAP2_PRESCALE_S)) -#define MCPWM_CAP2_PRESCALE_V 0xFF -#define MCPWM_CAP2_PRESCALE_S 3 +/*description: .*/ +#define MCPWM_CAP2_PRESCALE 0x000000FF +#define MCPWM_CAP2_PRESCALE_M ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S)) +#define MCPWM_CAP2_PRESCALE_V 0xFF +#define MCPWM_CAP2_PRESCALE_S 3 /* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ -/*description: */ -#define MCPWM_CAP2_MODE 0x00000003 -#define MCPWM_CAP2_MODE_M ((MCPWM_CAP2_MODE_V) << (MCPWM_CAP2_MODE_S)) -#define MCPWM_CAP2_MODE_V 0x3 -#define MCPWM_CAP2_MODE_S 1 +/*description: .*/ +#define MCPWM_CAP2_MODE 0x00000003 +#define MCPWM_CAP2_MODE_M ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S)) +#define MCPWM_CAP2_MODE_V 0x3 +#define MCPWM_CAP2_MODE_S 1 /* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP2_EN (BIT(0)) -#define MCPWM_CAP2_EN_M (BIT(0)) -#define MCPWM_CAP2_EN_V 0x1 -#define MCPWM_CAP2_EN_S 0 +/*description: .*/ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (BIT(0)) +#define MCPWM_CAP2_EN_V 0x1 +#define MCPWM_CAP2_EN_S 0 -#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0x00fc) +#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xFC) /* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define MCPWM_CAP0_VALUE 0xFFFFFFFF -#define MCPWM_CAP0_VALUE_M ((MCPWM_CAP0_VALUE_V) << (MCPWM_CAP0_VALUE_S)) -#define MCPWM_CAP0_VALUE_V 0xFFFFFFFF -#define MCPWM_CAP0_VALUE_S 0 +/*description: .*/ +#define MCPWM_CAP0_VALUE 0xFFFFFFFF +#define MCPWM_CAP0_VALUE_M ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S)) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP0_VALUE_S 0 -#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x0100) +#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100) /* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define MCPWM_CAP1_VALUE 0xFFFFFFFF -#define MCPWM_CAP1_VALUE_M ((MCPWM_CAP1_VALUE_V) << (MCPWM_CAP1_VALUE_S)) -#define MCPWM_CAP1_VALUE_V 0xFFFFFFFF -#define MCPWM_CAP1_VALUE_S 0 +/*description: .*/ +#define MCPWM_CAP1_VALUE 0xFFFFFFFF +#define MCPWM_CAP1_VALUE_M ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S)) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP1_VALUE_S 0 -#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x0104) +#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104) /* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define MCPWM_CAP2_VALUE 0xFFFFFFFF -#define MCPWM_CAP2_VALUE_M ((MCPWM_CAP2_VALUE_V) << (MCPWM_CAP2_VALUE_S)) -#define MCPWM_CAP2_VALUE_V 0xFFFFFFFF -#define MCPWM_CAP2_VALUE_S 0 +/*description: .*/ +#define MCPWM_CAP2_VALUE 0xFFFFFFFF +#define MCPWM_CAP2_VALUE_M ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S)) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP2_VALUE_S 0 -#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0108) +#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108) /* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */ -/*description: cap trigger's edge 0: posedge 1: negedge*/ -#define MCPWM_CAP2_EDGE (BIT(2)) -#define MCPWM_CAP2_EDGE_M (BIT(2)) -#define MCPWM_CAP2_EDGE_V 0x1 -#define MCPWM_CAP2_EDGE_S 2 +/*description: cap trigger's edge, 0: posedge, 1: negedge.*/ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (BIT(2)) +#define MCPWM_CAP2_EDGE_V 0x1 +#define MCPWM_CAP2_EDGE_S 2 /* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP1_EDGE (BIT(1)) -#define MCPWM_CAP1_EDGE_M (BIT(1)) -#define MCPWM_CAP1_EDGE_V 0x1 -#define MCPWM_CAP1_EDGE_S 1 +/*description: .*/ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (BIT(1)) +#define MCPWM_CAP1_EDGE_V 0x1 +#define MCPWM_CAP1_EDGE_S 1 /* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP0_EDGE (BIT(0)) -#define MCPWM_CAP0_EDGE_M (BIT(0)) -#define MCPWM_CAP0_EDGE_V 0x1 -#define MCPWM_CAP0_EDGE_S 0 +/*description: .*/ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (BIT(0)) +#define MCPWM_CAP0_EDGE_V 0x1 +#define MCPWM_CAP0_EDGE_S 0 -#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x010c) +#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10C) /* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: a toggle will trigger a force update*/ -#define MCPWM_OP2_FORCE_UP (BIT(7)) -#define MCPWM_OP2_FORCE_UP_M (BIT(7)) -#define MCPWM_OP2_FORCE_UP_V 0x1 -#define MCPWM_OP2_FORCE_UP_S 7 +/*description: a toggle will trigger a force update.*/ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (BIT(7)) +#define MCPWM_OP2_FORCE_UP_V 0x1 +#define MCPWM_OP2_FORCE_UP_S 7 /* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */ -/*description: reg update local enable*/ -#define MCPWM_OP2_UP_EN (BIT(6)) -#define MCPWM_OP2_UP_EN_M (BIT(6)) -#define MCPWM_OP2_UP_EN_V 0x1 -#define MCPWM_OP2_UP_EN_S 6 +/*description: reg update local enable.*/ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (BIT(6)) +#define MCPWM_OP2_UP_EN_V 0x1 +#define MCPWM_OP2_UP_EN_S 6 /* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: a toggle will trigger a force update*/ -#define MCPWM_OP1_FORCE_UP (BIT(5)) -#define MCPWM_OP1_FORCE_UP_M (BIT(5)) -#define MCPWM_OP1_FORCE_UP_V 0x1 -#define MCPWM_OP1_FORCE_UP_S 5 +/*description: a toggle will trigger a force update.*/ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (BIT(5)) +#define MCPWM_OP1_FORCE_UP_V 0x1 +#define MCPWM_OP1_FORCE_UP_S 5 /* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_OP1_UP_EN (BIT(4)) -#define MCPWM_OP1_UP_EN_M (BIT(4)) -#define MCPWM_OP1_UP_EN_V 0x1 -#define MCPWM_OP1_UP_EN_S 4 +/*description: .*/ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (BIT(4)) +#define MCPWM_OP1_UP_EN_V 0x1 +#define MCPWM_OP1_UP_EN_S 4 /* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: a toggle will trigger a force update*/ -#define MCPWM_OP0_FORCE_UP (BIT(3)) -#define MCPWM_OP0_FORCE_UP_M (BIT(3)) -#define MCPWM_OP0_FORCE_UP_V 0x1 -#define MCPWM_OP0_FORCE_UP_S 3 +/*description: a toggle will trigger a force update.*/ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (BIT(3)) +#define MCPWM_OP0_FORCE_UP_V 0x1 +#define MCPWM_OP0_FORCE_UP_S 3 /* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_OP0_UP_EN (BIT(2)) -#define MCPWM_OP0_UP_EN_M (BIT(2)) -#define MCPWM_OP0_UP_EN_V 0x1 -#define MCPWM_OP0_UP_EN_S 2 +/*description: .*/ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (BIT(2)) +#define MCPWM_OP0_UP_EN_V 0x1 +#define MCPWM_OP0_UP_EN_S 2 /* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: a toggle will trigger a force update all timers and operators - will update their active regs*/ -#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_M (BIT(1)) -#define MCPWM_GLOBAL_FORCE_UP_V 0x1 -#define MCPWM_GLOBAL_FORCE_UP_S 1 +/*description: a toggle will trigger a force update, all timers and operators will update their + active regs.*/ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_V 0x1 +#define MCPWM_GLOBAL_FORCE_UP_S 1 /* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ -/*description: */ -#define MCPWM_GLOBAL_UP_EN (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_M (BIT(0)) -#define MCPWM_GLOBAL_UP_EN_V 0x1 -#define MCPWM_GLOBAL_UP_EN_S 0 +/*description: .*/ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_V 0x1 +#define MCPWM_GLOBAL_UP_EN_S 0 -#define MCMCPWM_INT_ENA_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0110) +#define MCPWM_INT_ENA_PWM_REG(i) (REG_MCPWM_BASE(i) + 0x110) /* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP2_INT_ENA (BIT(29)) -#define MCPWM_CAP2_INT_ENA_M (BIT(29)) -#define MCPWM_CAP2_INT_ENA_V 0x1 -#define MCPWM_CAP2_INT_ENA_S 29 +/*description: .*/ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (BIT(29)) +#define MCPWM_CAP2_INT_ENA_V 0x1 +#define MCPWM_CAP2_INT_ENA_S 29 /* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP1_INT_ENA (BIT(28)) -#define MCPWM_CAP1_INT_ENA_M (BIT(28)) -#define MCPWM_CAP1_INT_ENA_V 0x1 -#define MCPWM_CAP1_INT_ENA_S 28 +/*description: .*/ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (BIT(28)) +#define MCPWM_CAP1_INT_ENA_V 0x1 +#define MCPWM_CAP1_INT_ENA_S 28 /* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP0_INT_ENA (BIT(27)) -#define MCPWM_CAP0_INT_ENA_M (BIT(27)) -#define MCPWM_CAP0_INT_ENA_V 0x1 -#define MCPWM_CAP0_INT_ENA_S 27 +/*description: .*/ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (BIT(27)) +#define MCPWM_CAP0_INT_ENA_V 0x1 +#define MCPWM_CAP0_INT_ENA_S 27 /* MCPWM_TZ2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) -#define MCPWM_TZ2_OST_INT_ENA_M (BIT(26)) -#define MCPWM_TZ2_OST_INT_ENA_V 0x1 -#define MCPWM_TZ2_OST_INT_ENA_S 26 +/*description: .*/ +#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_M (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_V 0x1 +#define MCPWM_TZ2_OST_INT_ENA_S 26 /* MCPWM_TZ1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) -#define MCPWM_TZ1_OST_INT_ENA_M (BIT(25)) -#define MCPWM_TZ1_OST_INT_ENA_V 0x1 -#define MCPWM_TZ1_OST_INT_ENA_S 25 +/*description: .*/ +#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_M (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_V 0x1 +#define MCPWM_TZ1_OST_INT_ENA_S 25 /* MCPWM_TZ0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) -#define MCPWM_TZ0_OST_INT_ENA_M (BIT(24)) -#define MCPWM_TZ0_OST_INT_ENA_V 0x1 -#define MCPWM_TZ0_OST_INT_ENA_S 24 +/*description: .*/ +#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_M (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_V 0x1 +#define MCPWM_TZ0_OST_INT_ENA_S 24 /* MCPWM_TZ2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ENA_M (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ENA_V 0x1 -#define MCPWM_TZ2_CBC_INT_ENA_S 23 +/*description: .*/ +#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_M (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_V 0x1 +#define MCPWM_TZ2_CBC_INT_ENA_S 23 /* MCPWM_TZ1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ENA_M (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ENA_V 0x1 -#define MCPWM_TZ1_CBC_INT_ENA_S 22 +/*description: .*/ +#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_M (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_V 0x1 +#define MCPWM_TZ1_CBC_INT_ENA_S 22 /* MCPWM_TZ0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ENA_M (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ENA_V 0x1 -#define MCPWM_TZ0_CBC_INT_ENA_S 21 +/*description: .*/ +#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_M (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_V 0x1 +#define MCPWM_TZ0_CBC_INT_ENA_S 21 /* MCPWM_CMPR2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ENA_M (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ENA_V 0x1 -#define MCPWM_CMPR2_TEB_INT_ENA_S 20 +/*description: .*/ +#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_M (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_V 0x1 +#define MCPWM_CMPR2_TEB_INT_ENA_S 20 /* MCPWM_CMPR1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ENA_M (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ENA_V 0x1 -#define MCPWM_CMPR1_TEB_INT_ENA_S 19 +/*description: .*/ +#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_M (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_V 0x1 +#define MCPWM_CMPR1_TEB_INT_ENA_S 19 /* MCPWM_CMPR0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ENA_M (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ENA_V 0x1 -#define MCPWM_CMPR0_TEB_INT_ENA_S 18 +/*description: .*/ +#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_M (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_V 0x1 +#define MCPWM_CMPR0_TEB_INT_ENA_S 18 /* MCPWM_CMPR2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ENA_M (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ENA_V 0x1 -#define MCPWM_CMPR2_TEA_INT_ENA_S 17 +/*description: .*/ +#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_M (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_V 0x1 +#define MCPWM_CMPR2_TEA_INT_ENA_S 17 /* MCPWM_CMPR1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ENA_M (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ENA_V 0x1 -#define MCPWM_CMPR1_TEA_INT_ENA_S 16 +/*description: .*/ +#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_M (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_V 0x1 +#define MCPWM_CMPR1_TEA_INT_ENA_S 16 /* MCPWM_CMPR0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ENA_M (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ENA_V 0x1 -#define MCPWM_CMPR0_TEA_INT_ENA_S 15 +/*description: .*/ +#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_M (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_V 0x1 +#define MCPWM_CMPR0_TEA_INT_ENA_S 15 /* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/*description: .*/ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 /* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/*description: .*/ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 /* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ENA_V 0x1 -#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/*description: .*/ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 /* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT2_INT_ENA (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_M (BIT(11)) -#define MCPWM_FAULT2_INT_ENA_V 0x1 -#define MCPWM_FAULT2_INT_ENA_S 11 +/*description: .*/ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_V 0x1 +#define MCPWM_FAULT2_INT_ENA_S 11 /* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT1_INT_ENA (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_M (BIT(10)) -#define MCPWM_FAULT1_INT_ENA_V 0x1 -#define MCPWM_FAULT1_INT_ENA_S 10 +/*description: .*/ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_V 0x1 +#define MCPWM_FAULT1_INT_ENA_S 10 /* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT0_INT_ENA (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_M (BIT(9)) -#define MCPWM_FAULT0_INT_ENA_V 0x1 -#define MCPWM_FAULT0_INT_ENA_S 9 +/*description: .*/ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_V 0x1 +#define MCPWM_FAULT0_INT_ENA_S 9 /* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/*description: .*/ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 /* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/*description: .*/ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 /* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ENA_V 0x1 -#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/*description: .*/ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 /* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/*description: .*/ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 /* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/*description: .*/ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 /* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/*description: .*/ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 /* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/*description: .*/ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 /* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/*description: .*/ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 /* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ENA_V 0x1 -#define MCPWM_TIMER0_STOP_INT_ENA_S 0 +/*description: .*/ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 -#define MCMCPWM_INT_RAW_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0114) +#define MCPWM_INT_RAW_PWM_REG(i) (REG_MCPWM_BASE(i) + 0x114) /* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP2_INT_RAW (BIT(29)) -#define MCPWM_CAP2_INT_RAW_M (BIT(29)) -#define MCPWM_CAP2_INT_RAW_V 0x1 -#define MCPWM_CAP2_INT_RAW_S 29 +/*description: .*/ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (BIT(29)) +#define MCPWM_CAP2_INT_RAW_V 0x1 +#define MCPWM_CAP2_INT_RAW_S 29 /* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP1_INT_RAW (BIT(28)) -#define MCPWM_CAP1_INT_RAW_M (BIT(28)) -#define MCPWM_CAP1_INT_RAW_V 0x1 -#define MCPWM_CAP1_INT_RAW_S 28 +/*description: .*/ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (BIT(28)) +#define MCPWM_CAP1_INT_RAW_V 0x1 +#define MCPWM_CAP1_INT_RAW_S 28 /* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP0_INT_RAW (BIT(27)) -#define MCPWM_CAP0_INT_RAW_M (BIT(27)) -#define MCPWM_CAP0_INT_RAW_V 0x1 -#define MCPWM_CAP0_INT_RAW_S 27 +/*description: .*/ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (BIT(27)) +#define MCPWM_CAP0_INT_RAW_V 0x1 +#define MCPWM_CAP0_INT_RAW_S 27 /* MCPWM_TZ2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) -#define MCPWM_TZ2_OST_INT_RAW_M (BIT(26)) -#define MCPWM_TZ2_OST_INT_RAW_V 0x1 -#define MCPWM_TZ2_OST_INT_RAW_S 26 +/*description: .*/ +#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_M (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_V 0x1 +#define MCPWM_TZ2_OST_INT_RAW_S 26 /* MCPWM_TZ1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) -#define MCPWM_TZ1_OST_INT_RAW_M (BIT(25)) -#define MCPWM_TZ1_OST_INT_RAW_V 0x1 -#define MCPWM_TZ1_OST_INT_RAW_S 25 +/*description: .*/ +#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_M (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_V 0x1 +#define MCPWM_TZ1_OST_INT_RAW_S 25 /* MCPWM_TZ0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) -#define MCPWM_TZ0_OST_INT_RAW_M (BIT(24)) -#define MCPWM_TZ0_OST_INT_RAW_V 0x1 -#define MCPWM_TZ0_OST_INT_RAW_S 24 +/*description: .*/ +#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_M (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_V 0x1 +#define MCPWM_TZ0_OST_INT_RAW_S 24 /* MCPWM_TZ2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) -#define MCPWM_TZ2_CBC_INT_RAW_M (BIT(23)) -#define MCPWM_TZ2_CBC_INT_RAW_V 0x1 -#define MCPWM_TZ2_CBC_INT_RAW_S 23 +/*description: .*/ +#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_M (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_V 0x1 +#define MCPWM_TZ2_CBC_INT_RAW_S 23 /* MCPWM_TZ1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) -#define MCPWM_TZ1_CBC_INT_RAW_M (BIT(22)) -#define MCPWM_TZ1_CBC_INT_RAW_V 0x1 -#define MCPWM_TZ1_CBC_INT_RAW_S 22 +/*description: .*/ +#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_M (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_V 0x1 +#define MCPWM_TZ1_CBC_INT_RAW_S 22 /* MCPWM_TZ0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) -#define MCPWM_TZ0_CBC_INT_RAW_M (BIT(21)) -#define MCPWM_TZ0_CBC_INT_RAW_V 0x1 -#define MCPWM_TZ0_CBC_INT_RAW_S 21 +/*description: .*/ +#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_M (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_V 0x1 +#define MCPWM_TZ0_CBC_INT_RAW_S 21 /* MCPWM_CMPR2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_RAW_M (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_RAW_V 0x1 -#define MCPWM_CMPR2_TEB_INT_RAW_S 20 +/*description: .*/ +#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_M (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_V 0x1 +#define MCPWM_CMPR2_TEB_INT_RAW_S 20 /* MCPWM_CMPR1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_RAW_M (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_RAW_V 0x1 -#define MCPWM_CMPR1_TEB_INT_RAW_S 19 +/*description: .*/ +#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_M (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_V 0x1 +#define MCPWM_CMPR1_TEB_INT_RAW_S 19 /* MCPWM_CMPR0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_RAW_M (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_RAW_V 0x1 -#define MCPWM_CMPR0_TEB_INT_RAW_S 18 +/*description: .*/ +#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_M (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_V 0x1 +#define MCPWM_CMPR0_TEB_INT_RAW_S 18 /* MCPWM_CMPR2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_RAW_M (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_RAW_V 0x1 -#define MCPWM_CMPR2_TEA_INT_RAW_S 17 +/*description: .*/ +#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_M (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_V 0x1 +#define MCPWM_CMPR2_TEA_INT_RAW_S 17 /* MCPWM_CMPR1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_RAW_M (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_RAW_V 0x1 -#define MCPWM_CMPR1_TEA_INT_RAW_S 16 +/*description: .*/ +#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_M (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_V 0x1 +#define MCPWM_CMPR1_TEA_INT_RAW_S 16 /* MCPWM_CMPR0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_RAW_M (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_RAW_V 0x1 -#define MCPWM_CMPR0_TEA_INT_RAW_S 15 +/*description: .*/ +#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_M (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_V 0x1 +#define MCPWM_CMPR0_TEA_INT_RAW_S 15 /* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/*description: .*/ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 /* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/*description: .*/ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 /* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_RAW_V 0x1 -#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/*description: .*/ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 /* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT2_INT_RAW (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_M (BIT(11)) -#define MCPWM_FAULT2_INT_RAW_V 0x1 -#define MCPWM_FAULT2_INT_RAW_S 11 +/*description: .*/ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_V 0x1 +#define MCPWM_FAULT2_INT_RAW_S 11 /* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT1_INT_RAW (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_M (BIT(10)) -#define MCPWM_FAULT1_INT_RAW_V 0x1 -#define MCPWM_FAULT1_INT_RAW_S 10 +/*description: .*/ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_V 0x1 +#define MCPWM_FAULT1_INT_RAW_S 10 /* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT0_INT_RAW (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_M (BIT(9)) -#define MCPWM_FAULT0_INT_RAW_V 0x1 -#define MCPWM_FAULT0_INT_RAW_S 9 +/*description: .*/ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_V 0x1 +#define MCPWM_FAULT0_INT_RAW_S 9 /* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/*description: .*/ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 /* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/*description: .*/ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 /* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_RAW_V 0x1 -#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/*description: .*/ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 /* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/*description: .*/ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 /* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/*description: .*/ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 /* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/*description: .*/ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 /* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/*description: .*/ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 /* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/*description: .*/ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 /* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_RAW_V 0x1 -#define MCPWM_TIMER0_STOP_INT_RAW_S 0 +/*description: .*/ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 -#define MCMCPWM_INT_ST_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0118) +#define MCPWM_INT_ST_PWM_REG(i) (REG_MCPWM_BASE(i) + 0x118) /* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP2_INT_ST (BIT(29)) -#define MCPWM_CAP2_INT_ST_M (BIT(29)) -#define MCPWM_CAP2_INT_ST_V 0x1 -#define MCPWM_CAP2_INT_ST_S 29 +/*description: .*/ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (BIT(29)) +#define MCPWM_CAP2_INT_ST_V 0x1 +#define MCPWM_CAP2_INT_ST_S 29 /* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP1_INT_ST (BIT(28)) -#define MCPWM_CAP1_INT_ST_M (BIT(28)) -#define MCPWM_CAP1_INT_ST_V 0x1 -#define MCPWM_CAP1_INT_ST_S 28 +/*description: .*/ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (BIT(28)) +#define MCPWM_CAP1_INT_ST_V 0x1 +#define MCPWM_CAP1_INT_ST_S 28 /* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP0_INT_ST (BIT(27)) -#define MCPWM_CAP0_INT_ST_M (BIT(27)) -#define MCPWM_CAP0_INT_ST_V 0x1 -#define MCPWM_CAP0_INT_ST_S 27 +/*description: .*/ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (BIT(27)) +#define MCPWM_CAP0_INT_ST_V 0x1 +#define MCPWM_CAP0_INT_ST_S 27 /* MCPWM_TZ2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_OST_INT_ST (BIT(26)) -#define MCPWM_TZ2_OST_INT_ST_M (BIT(26)) -#define MCPWM_TZ2_OST_INT_ST_V 0x1 -#define MCPWM_TZ2_OST_INT_ST_S 26 +/*description: .*/ +#define MCPWM_TZ2_OST_INT_ST (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_M (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_V 0x1 +#define MCPWM_TZ2_OST_INT_ST_S 26 /* MCPWM_TZ1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_OST_INT_ST (BIT(25)) -#define MCPWM_TZ1_OST_INT_ST_M (BIT(25)) -#define MCPWM_TZ1_OST_INT_ST_V 0x1 -#define MCPWM_TZ1_OST_INT_ST_S 25 +/*description: .*/ +#define MCPWM_TZ1_OST_INT_ST (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_M (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_V 0x1 +#define MCPWM_TZ1_OST_INT_ST_S 25 /* MCPWM_TZ0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_OST_INT_ST (BIT(24)) -#define MCPWM_TZ0_OST_INT_ST_M (BIT(24)) -#define MCPWM_TZ0_OST_INT_ST_V 0x1 -#define MCPWM_TZ0_OST_INT_ST_S 24 +/*description: .*/ +#define MCPWM_TZ0_OST_INT_ST (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_M (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_V 0x1 +#define MCPWM_TZ0_OST_INT_ST_S 24 /* MCPWM_TZ2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ST_M (BIT(23)) -#define MCPWM_TZ2_CBC_INT_ST_V 0x1 -#define MCPWM_TZ2_CBC_INT_ST_S 23 +/*description: .*/ +#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_M (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_V 0x1 +#define MCPWM_TZ2_CBC_INT_ST_S 23 /* MCPWM_TZ1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ST_M (BIT(22)) -#define MCPWM_TZ1_CBC_INT_ST_V 0x1 -#define MCPWM_TZ1_CBC_INT_ST_S 22 +/*description: .*/ +#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_M (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_V 0x1 +#define MCPWM_TZ1_CBC_INT_ST_S 22 /* MCPWM_TZ0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ST_M (BIT(21)) -#define MCPWM_TZ0_CBC_INT_ST_V 0x1 -#define MCPWM_TZ0_CBC_INT_ST_S 21 +/*description: .*/ +#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_M (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_V 0x1 +#define MCPWM_TZ0_CBC_INT_ST_S 21 /* MCPWM_CMPR2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ST_M (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_ST_V 0x1 -#define MCPWM_CMPR2_TEB_INT_ST_S 20 +/*description: .*/ +#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_M (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_V 0x1 +#define MCPWM_CMPR2_TEB_INT_ST_S 20 /* MCPWM_CMPR1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ST_M (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_ST_V 0x1 -#define MCPWM_CMPR1_TEB_INT_ST_S 19 +/*description: .*/ +#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_M (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_V 0x1 +#define MCPWM_CMPR1_TEB_INT_ST_S 19 /* MCPWM_CMPR0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ST_M (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_ST_V 0x1 -#define MCPWM_CMPR0_TEB_INT_ST_S 18 +/*description: .*/ +#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_M (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_V 0x1 +#define MCPWM_CMPR0_TEB_INT_ST_S 18 /* MCPWM_CMPR2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ST_M (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_ST_V 0x1 -#define MCPWM_CMPR2_TEA_INT_ST_S 17 +/*description: .*/ +#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_M (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_V 0x1 +#define MCPWM_CMPR2_TEA_INT_ST_S 17 /* MCPWM_CMPR1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ST_M (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_ST_V 0x1 -#define MCPWM_CMPR1_TEA_INT_ST_S 16 +/*description: .*/ +#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_M (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_V 0x1 +#define MCPWM_CMPR1_TEA_INT_ST_S 16 /* MCPWM_CMPR0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ST_M (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_ST_V 0x1 -#define MCPWM_CMPR0_TEA_INT_ST_S 15 +/*description: .*/ +#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_M (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_V 0x1 +#define MCPWM_CMPR0_TEA_INT_ST_S 15 /* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/*description: .*/ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT2_CLR_INT_ST_S 14 /* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/*description: .*/ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT1_CLR_INT_ST_S 13 /* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_ST_V 0x1 -#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/*description: .*/ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT0_CLR_INT_ST_S 12 /* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT2_INT_ST (BIT(11)) -#define MCPWM_FAULT2_INT_ST_M (BIT(11)) -#define MCPWM_FAULT2_INT_ST_V 0x1 -#define MCPWM_FAULT2_INT_ST_S 11 +/*description: .*/ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (BIT(11)) +#define MCPWM_FAULT2_INT_ST_V 0x1 +#define MCPWM_FAULT2_INT_ST_S 11 /* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT1_INT_ST (BIT(10)) -#define MCPWM_FAULT1_INT_ST_M (BIT(10)) -#define MCPWM_FAULT1_INT_ST_V 0x1 -#define MCPWM_FAULT1_INT_ST_S 10 +/*description: .*/ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (BIT(10)) +#define MCPWM_FAULT1_INT_ST_V 0x1 +#define MCPWM_FAULT1_INT_ST_S 10 /* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT0_INT_ST (BIT(9)) -#define MCPWM_FAULT0_INT_ST_M (BIT(9)) -#define MCPWM_FAULT0_INT_ST_V 0x1 -#define MCPWM_FAULT0_INT_ST_S 9 +/*description: .*/ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (BIT(9)) +#define MCPWM_FAULT0_INT_ST_V 0x1 +#define MCPWM_FAULT0_INT_ST_S 9 /* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/*description: .*/ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER2_TEP_INT_ST_S 8 /* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/*description: .*/ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER1_TEP_INT_ST_S 7 /* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_ST_V 0x1 -#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/*description: .*/ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER0_TEP_INT_ST_S 6 /* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/*description: .*/ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 /* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/*description: .*/ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 /* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_ST_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/*description: .*/ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 /* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/*description: .*/ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER2_STOP_INT_ST_S 2 /* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/*description: .*/ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER1_STOP_INT_ST_S 1 /* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_ST_V 0x1 -#define MCPWM_TIMER0_STOP_INT_ST_S 0 +/*description: .*/ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ST_S 0 -#define MCMCPWM_INT_CLR_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x011c) +#define MCPWM_INT_CLR_PWM_REG(i) (REG_MCPWM_BASE(i) + 0x11C) /* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP2_INT_CLR (BIT(29)) -#define MCPWM_CAP2_INT_CLR_M (BIT(29)) -#define MCPWM_CAP2_INT_CLR_V 0x1 -#define MCPWM_CAP2_INT_CLR_S 29 +/*description: .*/ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (BIT(29)) +#define MCPWM_CAP2_INT_CLR_V 0x1 +#define MCPWM_CAP2_INT_CLR_S 29 /* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP1_INT_CLR (BIT(28)) -#define MCPWM_CAP1_INT_CLR_M (BIT(28)) -#define MCPWM_CAP1_INT_CLR_V 0x1 -#define MCPWM_CAP1_INT_CLR_S 28 +/*description: .*/ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (BIT(28)) +#define MCPWM_CAP1_INT_CLR_V 0x1 +#define MCPWM_CAP1_INT_CLR_S 28 /* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CAP0_INT_CLR (BIT(27)) -#define MCPWM_CAP0_INT_CLR_M (BIT(27)) -#define MCPWM_CAP0_INT_CLR_V 0x1 -#define MCPWM_CAP0_INT_CLR_S 27 +/*description: .*/ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (BIT(27)) +#define MCPWM_CAP0_INT_CLR_V 0x1 +#define MCPWM_CAP0_INT_CLR_S 27 /* MCPWM_TZ2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) -#define MCPWM_TZ2_OST_INT_CLR_M (BIT(26)) -#define MCPWM_TZ2_OST_INT_CLR_V 0x1 -#define MCPWM_TZ2_OST_INT_CLR_S 26 +/*description: .*/ +#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_M (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_V 0x1 +#define MCPWM_TZ2_OST_INT_CLR_S 26 /* MCPWM_TZ1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) -#define MCPWM_TZ1_OST_INT_CLR_M (BIT(25)) -#define MCPWM_TZ1_OST_INT_CLR_V 0x1 -#define MCPWM_TZ1_OST_INT_CLR_S 25 +/*description: .*/ +#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_M (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_V 0x1 +#define MCPWM_TZ1_OST_INT_CLR_S 25 /* MCPWM_TZ0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) -#define MCPWM_TZ0_OST_INT_CLR_M (BIT(24)) -#define MCPWM_TZ0_OST_INT_CLR_V 0x1 -#define MCPWM_TZ0_OST_INT_CLR_S 24 +/*description: .*/ +#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_M (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_V 0x1 +#define MCPWM_TZ0_OST_INT_CLR_S 24 /* MCPWM_TZ2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) -#define MCPWM_TZ2_CBC_INT_CLR_M (BIT(23)) -#define MCPWM_TZ2_CBC_INT_CLR_V 0x1 -#define MCPWM_TZ2_CBC_INT_CLR_S 23 +/*description: .*/ +#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_M (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_V 0x1 +#define MCPWM_TZ2_CBC_INT_CLR_S 23 /* MCPWM_TZ1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) -#define MCPWM_TZ1_CBC_INT_CLR_M (BIT(22)) -#define MCPWM_TZ1_CBC_INT_CLR_V 0x1 -#define MCPWM_TZ1_CBC_INT_CLR_S 22 +/*description: .*/ +#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_M (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_V 0x1 +#define MCPWM_TZ1_CBC_INT_CLR_S 22 /* MCPWM_TZ0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) -#define MCPWM_TZ0_CBC_INT_CLR_M (BIT(21)) -#define MCPWM_TZ0_CBC_INT_CLR_V 0x1 -#define MCPWM_TZ0_CBC_INT_CLR_S 21 +/*description: .*/ +#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_M (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_V 0x1 +#define MCPWM_TZ0_CBC_INT_CLR_S 21 /* MCPWM_CMPR2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_CLR_M (BIT(20)) -#define MCPWM_CMPR2_TEB_INT_CLR_V 0x1 -#define MCPWM_CMPR2_TEB_INT_CLR_S 20 +/*description: .*/ +#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_M (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_V 0x1 +#define MCPWM_CMPR2_TEB_INT_CLR_S 20 /* MCPWM_CMPR1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_CLR_M (BIT(19)) -#define MCPWM_CMPR1_TEB_INT_CLR_V 0x1 -#define MCPWM_CMPR1_TEB_INT_CLR_S 19 +/*description: .*/ +#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_M (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_V 0x1 +#define MCPWM_CMPR1_TEB_INT_CLR_S 19 /* MCPWM_CMPR0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_CLR_M (BIT(18)) -#define MCPWM_CMPR0_TEB_INT_CLR_V 0x1 -#define MCPWM_CMPR0_TEB_INT_CLR_S 18 +/*description: .*/ +#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_M (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_V 0x1 +#define MCPWM_CMPR0_TEB_INT_CLR_S 18 /* MCPWM_CMPR2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_CLR_M (BIT(17)) -#define MCPWM_CMPR2_TEA_INT_CLR_V 0x1 -#define MCPWM_CMPR2_TEA_INT_CLR_S 17 +/*description: .*/ +#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_M (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_V 0x1 +#define MCPWM_CMPR2_TEA_INT_CLR_S 17 /* MCPWM_CMPR1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_CLR_M (BIT(16)) -#define MCPWM_CMPR1_TEA_INT_CLR_V 0x1 -#define MCPWM_CMPR1_TEA_INT_CLR_S 16 +/*description: .*/ +#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_M (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_V 0x1 +#define MCPWM_CMPR1_TEA_INT_CLR_S 16 /* MCPWM_CMPR0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_CLR_M (BIT(15)) -#define MCPWM_CMPR0_TEA_INT_CLR_V 0x1 -#define MCPWM_CMPR0_TEA_INT_CLR_S 15 +/*description: .*/ +#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_M (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_V 0x1 +#define MCPWM_CMPR0_TEA_INT_CLR_S 15 /* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_M (BIT(14)) -#define MCPWM_FAULT2_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/*description: .*/ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 /* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_M (BIT(13)) -#define MCPWM_FAULT1_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/*description: .*/ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 /* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_M (BIT(12)) -#define MCPWM_FAULT0_CLR_INT_CLR_V 0x1 -#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/*description: .*/ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 /* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT2_INT_CLR (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_M (BIT(11)) -#define MCPWM_FAULT2_INT_CLR_V 0x1 -#define MCPWM_FAULT2_INT_CLR_S 11 +/*description: .*/ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_V 0x1 +#define MCPWM_FAULT2_INT_CLR_S 11 /* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT1_INT_CLR (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_M (BIT(10)) -#define MCPWM_FAULT1_INT_CLR_V 0x1 -#define MCPWM_FAULT1_INT_CLR_S 10 +/*description: .*/ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_V 0x1 +#define MCPWM_FAULT1_INT_CLR_S 10 /* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_FAULT0_INT_CLR (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_M (BIT(9)) -#define MCPWM_FAULT0_INT_CLR_V 0x1 -#define MCPWM_FAULT0_INT_CLR_S 9 +/*description: .*/ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_V 0x1 +#define MCPWM_FAULT0_INT_CLR_S 9 /* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_M (BIT(8)) -#define MCPWM_TIMER2_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/*description: .*/ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 /* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_M (BIT(7)) -#define MCPWM_TIMER1_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/*description: .*/ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 /* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_M (BIT(6)) -#define MCPWM_TIMER0_TEP_INT_CLR_V 0x1 -#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/*description: .*/ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 /* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_M (BIT(5)) -#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/*description: .*/ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 /* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_M (BIT(4)) -#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/*description: .*/ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 /* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_M (BIT(3)) -#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x1 -#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/*description: .*/ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 /* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_M (BIT(2)) -#define MCPWM_TIMER2_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/*description: .*/ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 /* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_M (BIT(1)) -#define MCPWM_TIMER1_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/*description: .*/ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 /* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_M (BIT(0)) -#define MCPWM_TIMER0_STOP_INT_CLR_V 0x1 -#define MCPWM_TIMER0_STOP_INT_CLR_S 0 +/*description: .*/ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 -#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x0120) +#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x120) /* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define MCPWM_CLK_EN (BIT(0)) -#define MCPWM_CLK_EN_M (BIT(0)) -#define MCPWM_CLK_EN_V 0x1 -#define MCPWM_CLK_EN_S 0 +/*description: .*/ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (BIT(0)) +#define MCPWM_CLK_EN_V 0x1 +#define MCPWM_CLK_EN_S 0 -#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x0124) +#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x124) /* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */ -/*description: */ -#define MCPWM_DATE 0x0FFFFFFF -#define MCPWM_DATE_M ((MCPWM_DATE_V) << (MCPWM_DATE_S)) -#define MCPWM_DATE_V 0xFFFFFFF -#define MCPWM_DATE_S 0 +/*description: .*/ +#define MCPWM_DATE 0x0FFFFFFF +#define MCPWM_DATE_M ((MCPWM_DATE_V)<<(MCPWM_DATE_S)) +#define MCPWM_DATE_V 0xFFFFFFF +#define MCPWM_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32s3/include/soc/mcpwm_struct.h b/components/soc/esp32s3/include/soc/mcpwm_struct.h index b5b194d065..a12b68d887 100644 --- a/components/soc/esp32s3/include/soc/mcpwm_struct.h +++ b/components/soc/esp32s3/include/soc/mcpwm_struct.h @@ -13,446 +13,443 @@ // limitations under the License. #pragma once -#include - #ifdef __cplusplus extern "C" { #endif -typedef volatile struct mcpwm_dev_s { +#include + +typedef volatile struct { union { struct { - uint32_t prescale: 8; - uint32_t reserved8: 24; + uint32_t prescale : 8; + uint32_t reserved8 : 24; }; uint32_t val; } clk_cfg; struct { union { struct { - uint32_t prescale: 8; - uint32_t period: 16; - uint32_t upmethod: 2; /*0: immediate 1: eqz 2: sync 3: eqz | sync*/ - uint32_t reserved26: 6; + uint32_t prescale : 8; + uint32_t period : 16; + uint32_t upmethod : 2; /*0: immediate, 1: eqz, 2: sync, 3: eqz | sync*/ + uint32_t reserved26 : 6; }; uint32_t val; } period; union { struct { - uint32_t start: 3; /*0: stop @ eqz 1: stop @ eqp 2: free run 3: start and stop @ next eqz 4: start and stop @ next eqp*/ - uint32_t mode: 2; /*0: freeze 1: inc 2: dec 3: up-down*/ - uint32_t reserved5: 27; + uint32_t start : 3; /*0: stop @ eqz, 1: stop @ eqp, 2: free run, 3: start and stop @ next eqz, 4: start and stop @ next eqp,*/ + uint32_t mod : 2; /* 0: freeze, 1: inc, 2: dec, 3: up-down*/ + uint32_t reserved5 : 27; }; uint32_t val; } mode; union { struct { - uint32_t in_en: 1; - uint32_t sync_sw: 1; /*write the negate value will trigger a sw sync*/ - uint32_t out_sel: 2; - uint32_t timer_phase: 16; - uint32_t phase_direct : 1; - uint32_t reserved21: 11; + uint32_t in_en : 1; + uint32_t sync_sw : 1; /*write the negate value will trigger a sw sync*/ + uint32_t out_sel : 2; + uint32_t phase : 17; + uint32_t reserved21 : 11; }; uint32_t val; } sync; union { struct { - uint32_t value: 16; - uint32_t direction: 1; - uint32_t reserved17: 15; + uint32_t value : 16; + uint32_t direction : 1; + uint32_t reserved17 : 15; }; uint32_t val; } status; } timer[3]; union { struct { - uint32_t t0_in_sel: 3; - uint32_t t1_in_sel: 3; - uint32_t t2_in_sel: 3; - uint32_t ext_in0_inv: 1; - uint32_t ext_in1_inv: 1; - uint32_t ext_in2_inv: 1; - uint32_t reserved12: 20; + uint32_t t0_in_sel : 3; + uint32_t t1_in_sel : 3; + uint32_t t2_in_sel : 3; + uint32_t ext_in0_inv : 1; + uint32_t ext_in1_inv : 1; + uint32_t ext_in2_inv : 1; + uint32_t reserved12 : 20; }; uint32_t val; } timer_synci_cfg; union { struct { - uint32_t operator0_sel: 2; /*0: timer0 1: timer1 2: timer2*/ - uint32_t operator1_sel: 2; /*0: timer0 1: timer1 2: timer2*/ - uint32_t operator2_sel: 2; /*0: timer0 1: timer1 2: timer2*/ - uint32_t reserved6: 26; + uint32_t operator0_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/ + uint32_t operator1_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/ + uint32_t operator2_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/ + uint32_t reserved6 : 26; }; uint32_t val; } timer_sel; struct { union { struct { - uint32_t a_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ - uint32_t b_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ - uint32_t a_shdw_full: 1; - uint32_t b_shdw_full: 1; - uint32_t reserved10: 22; + uint32_t a_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/ + uint32_t b_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/ + uint32_t a_shdw_full : 1; + uint32_t b_shdw_full : 1; + uint32_t reserved10 : 22; }; uint32_t val; } cmpr_cfg; union { struct { - uint32_t cmpr_val: 16; - uint32_t reserved16: 16; + uint32_t cmpr_val : 16; + uint32_t reserved16 : 16; }; uint32_t val; } cmpr_value[2]; union { struct { - uint32_t upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/ - uint32_t t0_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ - uint32_t t1_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ - uint32_t reserved10: 22; + uint32_t upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze*/ + uint32_t t0_sel : 3; /*take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none*/ + uint32_t t1_sel : 3; /*take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none*/ + uint32_t reserved10 : 22; }; uint32_t val; } gen_cfg0; union { struct { - uint32_t cntu_force_upmethod: 6; /*0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: sync bit5: freeze*/ - uint32_t a_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/ - uint32_t b_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/ - uint32_t a_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/ - uint32_t a_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/ - uint32_t b_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/ - uint32_t b_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/ - uint32_t reserved16: 16; + uint32_t cntu_force_upmethod : 6; /*0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: freeze*/ + uint32_t a_cntuforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/ + uint32_t b_cntuforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/ + uint32_t a_nciforce : 1; /*non-continuous immediate sw force, a toggle will trigger a force event*/ + uint32_t a_nciforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/ + uint32_t b_nciforce : 1; /*non-continuous immediate sw force, a toggle will trigger a force event*/ + uint32_t b_nciforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/ + uint32_t reserved16 : 16; }; uint32_t val; } gen_force; union { struct { - uint32_t utez: 2; - uint32_t utep: 2; - uint32_t utea: 2; - uint32_t uteb: 2; - uint32_t ut0: 2; - uint32_t ut1: 2; - uint32_t dtez: 2; - uint32_t dtep: 2; - uint32_t dtea: 2; - uint32_t dteb: 2; - uint32_t dt0: 2; - uint32_t dt1: 2; /*0: no change 1: low 2: high 3: toggle*/ - uint32_t reserved24: 8; + uint32_t utez : 2; + uint32_t utep : 2; + uint32_t utea : 2; + uint32_t uteb : 2; + uint32_t ut0 : 2; + uint32_t ut1 : 2; + uint32_t dtez : 2; + uint32_t dtep : 2; + uint32_t dtea : 2; + uint32_t dteb : 2; + uint32_t dt0 : 2; + uint32_t dt1 : 2; /*0: no change, 1: low, 2: high, 3: toggle*/ + uint32_t reserved24 : 8; }; uint32_t val; } generator[2]; union { struct { - uint32_t fed_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ - uint32_t red_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ - uint32_t deb_mode: 1; /*immediate dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ - uint32_t a_outswap: 1; - uint32_t b_outswap: 1; - uint32_t red_insel: 1; - uint32_t fed_insel: 1; - uint32_t red_outinvert: 1; - uint32_t fed_outinvert: 1; - uint32_t a_outbypass: 1; - uint32_t b_outbypass: 1; - uint32_t clk_sel: 1; - uint32_t reserved18: 14; + uint32_t fed_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/ + uint32_t red_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/ + uint32_t deb_mode : 1; /*immediate, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode*/ + uint32_t a_outswap : 1; + uint32_t b_outswap : 1; + uint32_t red_insel : 1; + uint32_t fed_insel : 1; + uint32_t red_outinvert : 1; + uint32_t fed_outinvert : 1; + uint32_t a_outbypass : 1; + uint32_t b_outbypass : 1; + uint32_t clk_sel : 1; + uint32_t reserved18 : 14; }; uint32_t val; } db_cfg; union { struct { - uint32_t fed: 16; - uint32_t reserved16: 16; + uint32_t fed : 16; + uint32_t reserved16 : 16; }; uint32_t val; } db_fed_cfg; union { struct { - uint32_t red: 16; - uint32_t reserved16: 16; + uint32_t red : 16; + uint32_t reserved16 : 16; }; uint32_t val; } db_red_cfg; union { struct { - uint32_t en: 1; - uint32_t prescale: 4; - uint32_t duty: 3; - uint32_t oshtwth: 4; - uint32_t out_invert: 1; - uint32_t in_invert: 1; - uint32_t reserved14: 18; + uint32_t en : 1; + uint32_t prescale : 4; + uint32_t duty : 3; + uint32_t oshtwth : 4; + uint32_t out_invert : 1; + uint32_t in_invert : 1; + uint32_t reserved14 : 18; }; uint32_t val; } carrier_cfg; union { struct { - uint32_t sw_cbc: 1; /*0: disable 1: enable*/ - uint32_t f2_cbc: 1; /*0: disable 1: enable*/ - uint32_t f1_cbc: 1; /*0: disable 1: enable*/ - uint32_t f0_cbc: 1; /*0: disable 1: enable*/ - uint32_t sw_ost: 1; /*0: disable 1: enable*/ - uint32_t f2_ost: 1; /*0: disable 1: enable*/ - uint32_t f1_ost: 1; /*0: disable 1: enable*/ - uint32_t f0_ost: 1; /*0: disable 1: enable*/ - uint32_t a_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t a_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t b_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ - uint32_t reserved24: 8; + uint32_t sw_cbc : 1; /*0: disable, 1: enable*/ + uint32_t f2_cbc : 1; /*0: disable, 1: enable*/ + uint32_t f1_cbc : 1; /*0: disable, 1: enable*/ + uint32_t f0_cbc : 1; /*0: disable, 1: enable*/ + uint32_t sw_ost : 1; /*0: disable, 1: enable*/ + uint32_t f2_ost : 1; /*0: disable, 1: enable*/ + uint32_t f1_ost : 1; /*0: disable, 1: enable*/ + uint32_t f0_ost : 1; /*0: disable, 1: enable*/ + uint32_t a_cbc_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ + uint32_t a_cbc_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ + uint32_t a_ost_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ + uint32_t a_ost_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ + uint32_t b_cbc_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ + uint32_t b_cbc_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ + uint32_t b_ost_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ + uint32_t b_ost_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/ + uint32_t reserved24 : 8; }; uint32_t val; } tz_cfg0; union { struct { - uint32_t clr_ost: 1; /*a toggle will clear oneshot tripping*/ - uint32_t cbcpulse: 2; /*bit0: tez bit1: tep*/ - uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping*/ - uint32_t force_ost: 1; /*a toggle trigger a oneshot tripping*/ - uint32_t reserved5: 27; + uint32_t clr_ost : 1; /*a toggle will clear oneshot tripping*/ + uint32_t cbcpulse : 2; /*bit0: tez, bit1: tep*/ + uint32_t force_cbc : 1; /*a toggle trigger a cycle-by-cycle tripping*/ + uint32_t force_ost : 1; /*a toggle trigger a oneshot tripping*/ + uint32_t reserved5 : 27; }; uint32_t val; } tz_cfg1; union { struct { - uint32_t cbc_on: 1; - uint32_t ost_on: 1; - uint32_t reserved2: 30; + uint32_t cbc_on : 1; + uint32_t ost_on : 1; + uint32_t reserved2 : 30; }; uint32_t val; } tz_status; } channel[3]; union { struct { - uint32_t f0_en: 1; - uint32_t f1_en: 1; - uint32_t f2_en: 1; - uint32_t f0_pole: 1; - uint32_t f1_pole: 1; - uint32_t f2_pole: 1; - uint32_t event_f0: 1; - uint32_t event_f1: 1; - uint32_t event_f2: 1; - uint32_t reserved9: 23; + uint32_t f0_en : 1; + uint32_t f1_en : 1; + uint32_t f2_en : 1; + uint32_t f0_pole : 1; + uint32_t f1_pole : 1; + uint32_t f2_pole : 1; + uint32_t event_f0 : 1; + uint32_t event_f1 : 1; + uint32_t event_f2 : 1; + uint32_t reserved9 : 23; }; uint32_t val; } fault_detect; union { struct { - uint32_t timer_en: 1; - uint32_t synci_en: 1; - uint32_t synci_sel: 3; - uint32_t sync_sw: 1; /*Write 1 will force a timer sync*/ - uint32_t reserved6: 26; + uint32_t timer_en : 1; + uint32_t synci_en : 1; + uint32_t synci_sel : 3; + uint32_t sync_sw : 1; /*Write 1 will force a timer sync*/ + uint32_t reserved6 : 26; }; uint32_t val; } cap_timer_cfg; - uint32_t cap_timer_phase; /**/ + uint32_t cap_timer_phase; union { struct { - uint32_t en: 1; - uint32_t mode: 2; /*bit0: negedge cap en bit1: posedge cap en*/ - uint32_t prescale: 8; - uint32_t in_invert: 1; - uint32_t sw: 1; /*Write 1 will trigger a sw capture*/ - uint32_t reserved13: 19; + uint32_t en : 1; + uint32_t mode : 2; /*bit0: negedge cap en, bit1: posedge cap en*/ + uint32_t prescale : 8; + uint32_t in_invert : 1; + uint32_t sw : 1; /*Write 1 will trigger a sw capture*/ + uint32_t reserved13 : 19; }; uint32_t val; } cap_cfg_ch[3]; - uint32_t cap_val_ch[3]; /**/ + uint32_t cap_val_ch[3]; union { struct { - uint32_t cap0_edge: 1; - uint32_t cap1_edge: 1; - uint32_t cap2_edge: 1; /*cap trigger's edge 0: posedge 1: negedge*/ - uint32_t reserved3: 29; + uint32_t cap0_edge : 1; + uint32_t cap1_edge : 1; + uint32_t cap2_edge : 1; /*cap trigger's edge, 0: posedge, 1: negedge*/ + uint32_t reserved3 : 29; }; uint32_t val; } cap_status; union { struct { - uint32_t global_up_en: 1; - uint32_t global_force_up: 1; /*a toggle will trigger a force update all timers and operators will update their active regs*/ - uint32_t op0_up_en: 1; - uint32_t op0_force_up: 1; /*a toggle will trigger a force update*/ - uint32_t op1_up_en: 1; - uint32_t op1_force_up: 1; /*a toggle will trigger a force update*/ - uint32_t op2_up_en: 1; /*reg update local enable*/ - uint32_t op2_force_up: 1; /*a toggle will trigger a force update*/ - uint32_t reserved8: 24; + uint32_t global_up_en : 1; + uint32_t global_force_up : 1; /*a toggle will trigger a force update, all timers and operators will update their active regs*/ + uint32_t op0_up_en : 1; + uint32_t op0_force_up : 1; /*a toggle will trigger a force update*/ + uint32_t op1_up_en : 1; + uint32_t op1_force_up : 1; /*a toggle will trigger a force update*/ + uint32_t op2_up_en : 1; /*reg update local enable*/ + uint32_t op2_force_up : 1; /*a toggle will trigger a force update*/ + uint32_t reserved8 : 24; }; uint32_t val; } update_cfg; union { struct { - uint32_t timer0_stop: 1; - uint32_t timer1_stop: 1; - uint32_t timer2_stop: 1; - uint32_t timer0_tez: 1; - uint32_t timer1_tez: 1; - uint32_t timer2_tez: 1; - uint32_t timer0_tep: 1; - uint32_t timer1_tep: 1; - uint32_t timer2_tep: 1; - uint32_t fault0: 1; - uint32_t fault1: 1; - uint32_t fault2: 1; - uint32_t fault0_clr: 1; - uint32_t fault1_clr: 1; - uint32_t fault2_clr: 1; - uint32_t cmpr0_tea: 1; - uint32_t cmpr1_tea: 1; - uint32_t cmpr2_tea: 1; - uint32_t cmpr0_teb: 1; - uint32_t cmpr1_teb: 1; - uint32_t cmpr2_teb: 1; - uint32_t tz0_cbc: 1; - uint32_t tz1_cbc: 1; - uint32_t tz2_cbc: 1; - uint32_t tz0_ost: 1; - uint32_t tz1_ost: 1; - uint32_t tz2_ost: 1; - uint32_t cap0: 1; - uint32_t cap1: 1; - uint32_t cap2: 1; - uint32_t reserved30: 2; + uint32_t timer0_stop : 1; + uint32_t timer1_stop : 1; + uint32_t timer2_stop : 1; + uint32_t timer0_tez : 1; + uint32_t timer1_tez : 1; + uint32_t timer2_tez : 1; + uint32_t timer0_tep : 1; + uint32_t timer1_tep : 1; + uint32_t timer2_tep : 1; + uint32_t fault0 : 1; + uint32_t fault1 : 1; + uint32_t fault2 : 1; + uint32_t fault0_clr : 1; + uint32_t fault1_clr : 1; + uint32_t fault2_clr : 1; + uint32_t cmpr0_tea : 1; + uint32_t cmpr1_tea : 1; + uint32_t cmpr2_tea : 1; + uint32_t cmpr0_teb : 1; + uint32_t cmpr1_teb : 1; + uint32_t cmpr2_teb : 1; + uint32_t tz0_cbc : 1; + uint32_t tz1_cbc : 1; + uint32_t tz2_cbc : 1; + uint32_t tz0_ost : 1; + uint32_t tz1_ost : 1; + uint32_t tz2_ost : 1; + uint32_t cap0 : 1; + uint32_t cap1 : 1; + uint32_t cap2 : 1; + uint32_t reserved30 : 2; }; uint32_t val; } int_ena; union { struct { - uint32_t timer0_stop: 1; - uint32_t timer1_stop: 1; - uint32_t timer2_stop: 1; - uint32_t timer0_tez: 1; - uint32_t timer1_tez: 1; - uint32_t timer2_tez: 1; - uint32_t timer0_tep: 1; - uint32_t timer1_tep: 1; - uint32_t timer2_tep: 1; - uint32_t fault0: 1; - uint32_t fault1: 1; - uint32_t fault2: 1; - uint32_t fault0_clr: 1; - uint32_t fault1_clr: 1; - uint32_t fault2_clr: 1; - uint32_t cmpr0_tea: 1; - uint32_t cmpr1_tea: 1; - uint32_t cmpr2_tea: 1; - uint32_t cmpr0_teb: 1; - uint32_t cmpr1_teb: 1; - uint32_t cmpr2_teb: 1; - uint32_t tz0_cbc: 1; - uint32_t tz1_cbc: 1; - uint32_t tz2_cbc: 1; - uint32_t tz0_ost: 1; - uint32_t tz1_ost: 1; - uint32_t tz2_ost: 1; - uint32_t cap0: 1; - uint32_t cap1: 1; - uint32_t cap2: 1; - uint32_t reserved30: 2; + uint32_t timer0_stop : 1; + uint32_t timer1_stop : 1; + uint32_t timer2_stop : 1; + uint32_t timer0_tez : 1; + uint32_t timer1_tez : 1; + uint32_t timer2_tez : 1; + uint32_t timer0_tep : 1; + uint32_t timer1_tep : 1; + uint32_t timer2_tep : 1; + uint32_t fault0 : 1; + uint32_t fault1 : 1; + uint32_t fault2 : 1; + uint32_t fault0_clr : 1; + uint32_t fault1_clr : 1; + uint32_t fault2_clr : 1; + uint32_t cmpr0_tea : 1; + uint32_t cmpr1_tea : 1; + uint32_t cmpr2_tea : 1; + uint32_t cmpr0_teb : 1; + uint32_t cmpr1_teb : 1; + uint32_t cmpr2_teb : 1; + uint32_t tz0_cbc : 1; + uint32_t tz1_cbc : 1; + uint32_t tz2_cbc : 1; + uint32_t tz0_ost : 1; + uint32_t tz1_ost : 1; + uint32_t tz2_ost : 1; + uint32_t cap0 : 1; + uint32_t cap1 : 1; + uint32_t cap2 : 1; + uint32_t reserved30 : 2; }; uint32_t val; } int_raw; union { struct { - uint32_t timer0_stop: 1; - uint32_t timer1_stop: 1; - uint32_t timer2_stop: 1; - uint32_t timer0_tez: 1; - uint32_t timer1_tez: 1; - uint32_t timer2_tez: 1; - uint32_t timer0_tep: 1; - uint32_t timer1_tep: 1; - uint32_t timer2_tep: 1; - uint32_t fault0: 1; - uint32_t fault1: 1; - uint32_t fault2: 1; - uint32_t fault0_clr: 1; - uint32_t fault1_clr: 1; - uint32_t fault2_clr: 1; - uint32_t cmpr0_tea: 1; - uint32_t cmpr1_tea: 1; - uint32_t cmpr2_tea: 1; - uint32_t cmpr0_teb: 1; - uint32_t cmpr1_teb: 1; - uint32_t cmpr2_teb: 1; - uint32_t tz0_cbc: 1; - uint32_t tz1_cbc: 1; - uint32_t tz2_cbc: 1; - uint32_t tz0_ost: 1; - uint32_t tz1_ost: 1; - uint32_t tz2_ost: 1; - uint32_t cap0: 1; - uint32_t cap1: 1; - uint32_t cap2: 1; - uint32_t reserved30: 2; + uint32_t timer0_stop : 1; + uint32_t timer1_stop : 1; + uint32_t timer2_stop : 1; + uint32_t timer0_tez : 1; + uint32_t timer1_tez : 1; + uint32_t timer2_tez : 1; + uint32_t timer0_tep : 1; + uint32_t timer1_tep : 1; + uint32_t timer2_tep : 1; + uint32_t fault0 : 1; + uint32_t fault1 : 1; + uint32_t fault2 : 1; + uint32_t fault0_clr : 1; + uint32_t fault1_clr : 1; + uint32_t fault2_clr : 1; + uint32_t cmpr0_tea : 1; + uint32_t cmpr1_tea : 1; + uint32_t cmpr2_tea : 1; + uint32_t cmpr0_teb : 1; + uint32_t cmpr1_teb : 1; + uint32_t cmpr2_teb : 1; + uint32_t tz0_cbc : 1; + uint32_t tz1_cbc : 1; + uint32_t tz2_cbc : 1; + uint32_t tz0_ost : 1; + uint32_t tz1_ost : 1; + uint32_t tz2_ost : 1; + uint32_t cap0 : 1; + uint32_t cap1 : 1; + uint32_t cap2 : 1; + uint32_t reserved30 : 2; }; uint32_t val; } int_st; union { struct { - uint32_t timer0_stop: 1; - uint32_t timer1_stop: 1; - uint32_t timer2_stop: 1; - uint32_t timer0_tez: 1; - uint32_t timer1_tez: 1; - uint32_t timer2_tez: 1; - uint32_t timer0_tep: 1; - uint32_t timer1_tep: 1; - uint32_t timer2_tep: 1; - uint32_t fault0: 1; - uint32_t fault1: 1; - uint32_t fault2: 1; - uint32_t fault0_clr: 1; - uint32_t fault1_clr: 1; - uint32_t fault2_clr: 1; - uint32_t cmpr0_tea: 1; - uint32_t cmpr1_tea: 1; - uint32_t cmpr2_tea: 1; - uint32_t cmpr0_teb: 1; - uint32_t cmpr1_teb: 1; - uint32_t cmpr2_teb: 1; - uint32_t tz0_cbc: 1; - uint32_t tz1_cbc: 1; - uint32_t tz2_cbc: 1; - uint32_t tz0_ost: 1; - uint32_t tz1_ost: 1; - uint32_t tz2_ost: 1; - uint32_t cap0: 1; - uint32_t cap1: 1; - uint32_t cap2: 1; - uint32_t reserved30: 2; + uint32_t timer0_stop : 1; + uint32_t timer1_stop : 1; + uint32_t timer2_stop : 1; + uint32_t timer0_tez : 1; + uint32_t timer1_tez : 1; + uint32_t timer2_tez : 1; + uint32_t timer0_tep : 1; + uint32_t timer1_tep : 1; + uint32_t timer2_tep : 1; + uint32_t fault0 : 1; + uint32_t fault1 : 1; + uint32_t fault2 : 1; + uint32_t fault0_clr : 1; + uint32_t fault1_clr : 1; + uint32_t fault2_clr : 1; + uint32_t cmpr0_tea : 1; + uint32_t cmpr1_tea : 1; + uint32_t cmpr2_tea : 1; + uint32_t cmpr0_teb : 1; + uint32_t cmpr1_teb : 1; + uint32_t cmpr2_teb : 1; + uint32_t tz0_cbc : 1; + uint32_t tz1_cbc : 1; + uint32_t tz2_cbc : 1; + uint32_t tz0_ost : 1; + uint32_t tz1_ost : 1; + uint32_t tz2_ost : 1; + uint32_t cap0 : 1; + uint32_t cap1 : 1; + uint32_t cap2 : 1; + uint32_t reserved30 : 2; }; uint32_t val; } int_clr; union { struct { - uint32_t clk_en: 1; - uint32_t reserved1: 31; + uint32_t en : 1; + uint32_t reserved1 : 31; }; uint32_t val; } reg_clk; union { struct { - uint32_t date: 28; - uint32_t reserved28: 4; + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } version; } mcpwm_dev_t; - extern mcpwm_dev_t MCPWM0; extern mcpwm_dev_t MCPWM1; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/pcnt_caps.h b/components/soc/esp32s3/include/soc/pcnt_caps.h new file mode 100644 index 0000000000..b72d302c2e --- /dev/null +++ b/components/soc/esp32s3/include/soc/pcnt_caps.h @@ -0,0 +1,26 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_PCNT_PORT_NUM (1) +#define SOC_PCNT_UNIT_NUM (4) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/pcnt_reg.h b/components/soc/esp32s3/include/soc/pcnt_reg.h index 0cd636f7f7..930c3b4720 100644 --- a/components/soc/esp32s3/include/soc/pcnt_reg.h +++ b/components/soc/esp32s3/include/soc/pcnt_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,846 +11,852 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_PCNT_REG_H_ +#define _SOC_PCNT_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0) /* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V) << (PCNT_CH1_LCTRL_MODE_U0_S)) -#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U0_S 30 +/*description: .*/ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S)) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U0_S 30 /* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V) << (PCNT_CH1_HCTRL_MODE_U0_S)) -#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/*description: .*/ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S)) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U0_S 28 /* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_POS_MODE_U0 0x00000003 -#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V) << (PCNT_CH1_POS_MODE_U0_S)) -#define PCNT_CH1_POS_MODE_U0_V 0x3 -#define PCNT_CH1_POS_MODE_U0_S 26 +/*description: .*/ +#define PCNT_CH1_POS_MODE_U0 0x00000003 +#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S)) +#define PCNT_CH1_POS_MODE_U0_V 0x3 +#define PCNT_CH1_POS_MODE_U0_S 26 /* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_NEG_MODE_U0 0x00000003 -#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V) << (PCNT_CH1_NEG_MODE_U0_S)) -#define PCNT_CH1_NEG_MODE_U0_V 0x3 -#define PCNT_CH1_NEG_MODE_U0_S 24 +/*description: .*/ +#define PCNT_CH1_NEG_MODE_U0 0x00000003 +#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S)) +#define PCNT_CH1_NEG_MODE_U0_V 0x3 +#define PCNT_CH1_NEG_MODE_U0_S 24 /* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V) << (PCNT_CH0_LCTRL_MODE_U0_S)) -#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/*description: .*/ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S)) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U0_S 22 /* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V) << (PCNT_CH0_HCTRL_MODE_U0_S)) -#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/*description: .*/ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S)) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U0_S 20 /* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_POS_MODE_U0 0x00000003 -#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V) << (PCNT_CH0_POS_MODE_U0_S)) -#define PCNT_CH0_POS_MODE_U0_V 0x3 -#define PCNT_CH0_POS_MODE_U0_S 18 +/*description: .*/ +#define PCNT_CH0_POS_MODE_U0 0x00000003 +#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S)) +#define PCNT_CH0_POS_MODE_U0_V 0x3 +#define PCNT_CH0_POS_MODE_U0_S 18 /* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_NEG_MODE_U0 0x00000003 -#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V) << (PCNT_CH0_NEG_MODE_U0_S)) -#define PCNT_CH0_NEG_MODE_U0_V 0x3 -#define PCNT_CH0_NEG_MODE_U0_S 16 +/*description: .*/ +#define PCNT_CH0_NEG_MODE_U0 0x00000003 +#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S)) +#define PCNT_CH0_NEG_MODE_U0_V 0x3 +#define PCNT_CH0_NEG_MODE_U0_S 16 /* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_THR_THRES1_EN_U0 (BIT(15)) -#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U0_V 0x1 -#define PCNT_THR_THRES1_EN_U0_S 15 +/*description: .*/ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_V 0x1 +#define PCNT_THR_THRES1_EN_U0_S 15 /* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_THR_THRES0_EN_U0 (BIT(14)) -#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U0_V 0x1 -#define PCNT_THR_THRES0_EN_U0_S 14 +/*description: .*/ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_V 0x1 +#define PCNT_THR_THRES0_EN_U0_S 14 /* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U0_V 0x1 -#define PCNT_THR_L_LIM_EN_U0_S 13 +/*description: .*/ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_V 0x1 +#define PCNT_THR_L_LIM_EN_U0_S 13 /* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U0_V 0x1 -#define PCNT_THR_H_LIM_EN_U0_S 12 +/*description: .*/ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_V 0x1 +#define PCNT_THR_H_LIM_EN_U0_S 12 /* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_ZERO_EN_U0 (BIT(11)) -#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U0_V 0x1 -#define PCNT_THR_ZERO_EN_U0_S 11 +/*description: .*/ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_V 0x1 +#define PCNT_THR_ZERO_EN_U0_S 11 /* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_FILTER_EN_U0 (BIT(10)) -#define PCNT_FILTER_EN_U0_M (BIT(10)) -#define PCNT_FILTER_EN_U0_V 0x1 -#define PCNT_FILTER_EN_U0_S 10 +/*description: .*/ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (BIT(10)) +#define PCNT_FILTER_EN_U0_V 0x1 +#define PCNT_FILTER_EN_U0_S 10 /* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: */ -#define PCNT_FILTER_THRES_U0 0x000003FF -#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V) << (PCNT_FILTER_THRES_U0_S)) -#define PCNT_FILTER_THRES_U0_V 0x3FF -#define PCNT_FILTER_THRES_U0_S 0 +/*description: .*/ +#define PCNT_FILTER_THRES_U0 0x000003FF +#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S)) +#define PCNT_FILTER_THRES_U0_V 0x3FF +#define PCNT_FILTER_THRES_U0_S 0 -#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4) /* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_THRES1_U0 0x0000FFFF -#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V) << (PCNT_CNT_THRES1_U0_S)) -#define PCNT_CNT_THRES1_U0_V 0xFFFF -#define PCNT_CNT_THRES1_U0_S 16 +/*description: .*/ +#define PCNT_CNT_THRES1_U0 0x0000FFFF +#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S)) +#define PCNT_CNT_THRES1_U0_V 0xFFFF +#define PCNT_CNT_THRES1_U0_S 16 /* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_THRES0_U0 0x0000FFFF -#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V) << (PCNT_CNT_THRES0_U0_S)) -#define PCNT_CNT_THRES0_U0_V 0xFFFF -#define PCNT_CNT_THRES0_U0_S 0 +/*description: .*/ +#define PCNT_CNT_THRES0_U0 0x0000FFFF +#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S)) +#define PCNT_CNT_THRES0_U0_V 0xFFFF +#define PCNT_CNT_THRES0_U0_S 0 -#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8) /* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_L_LIM_U0 0x0000FFFF -#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V) << (PCNT_CNT_L_LIM_U0_S)) -#define PCNT_CNT_L_LIM_U0_V 0xFFFF -#define PCNT_CNT_L_LIM_U0_S 16 +/*description: .*/ +#define PCNT_CNT_L_LIM_U0 0x0000FFFF +#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S)) +#define PCNT_CNT_L_LIM_U0_V 0xFFFF +#define PCNT_CNT_L_LIM_U0_S 16 /* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_H_LIM_U0 0x0000FFFF -#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V) << (PCNT_CNT_H_LIM_U0_S)) -#define PCNT_CNT_H_LIM_U0_V 0xFFFF -#define PCNT_CNT_H_LIM_U0_S 0 +/*description: .*/ +#define PCNT_CNT_H_LIM_U0 0x0000FFFF +#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S)) +#define PCNT_CNT_H_LIM_U0_V 0xFFFF +#define PCNT_CNT_H_LIM_U0_S 0 -#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xC) /* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V) << (PCNT_CH1_LCTRL_MODE_U1_S)) -#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U1_S 30 +/*description: .*/ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S)) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U1_S 30 /* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V) << (PCNT_CH1_HCTRL_MODE_U1_S)) -#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/*description: .*/ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S)) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U1_S 28 /* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_POS_MODE_U1 0x00000003 -#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V) << (PCNT_CH1_POS_MODE_U1_S)) -#define PCNT_CH1_POS_MODE_U1_V 0x3 -#define PCNT_CH1_POS_MODE_U1_S 26 +/*description: .*/ +#define PCNT_CH1_POS_MODE_U1 0x00000003 +#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S)) +#define PCNT_CH1_POS_MODE_U1_V 0x3 +#define PCNT_CH1_POS_MODE_U1_S 26 /* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_NEG_MODE_U1 0x00000003 -#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V) << (PCNT_CH1_NEG_MODE_U1_S)) -#define PCNT_CH1_NEG_MODE_U1_V 0x3 -#define PCNT_CH1_NEG_MODE_U1_S 24 +/*description: .*/ +#define PCNT_CH1_NEG_MODE_U1 0x00000003 +#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S)) +#define PCNT_CH1_NEG_MODE_U1_V 0x3 +#define PCNT_CH1_NEG_MODE_U1_S 24 /* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V) << (PCNT_CH0_LCTRL_MODE_U1_S)) -#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/*description: .*/ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S)) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U1_S 22 /* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V) << (PCNT_CH0_HCTRL_MODE_U1_S)) -#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/*description: .*/ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S)) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U1_S 20 /* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_POS_MODE_U1 0x00000003 -#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V) << (PCNT_CH0_POS_MODE_U1_S)) -#define PCNT_CH0_POS_MODE_U1_V 0x3 -#define PCNT_CH0_POS_MODE_U1_S 18 +/*description: .*/ +#define PCNT_CH0_POS_MODE_U1 0x00000003 +#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S)) +#define PCNT_CH0_POS_MODE_U1_V 0x3 +#define PCNT_CH0_POS_MODE_U1_S 18 /* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_NEG_MODE_U1 0x00000003 -#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V) << (PCNT_CH0_NEG_MODE_U1_S)) -#define PCNT_CH0_NEG_MODE_U1_V 0x3 -#define PCNT_CH0_NEG_MODE_U1_S 16 +/*description: .*/ +#define PCNT_CH0_NEG_MODE_U1 0x00000003 +#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S)) +#define PCNT_CH0_NEG_MODE_U1_V 0x3 +#define PCNT_CH0_NEG_MODE_U1_S 16 /* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_THR_THRES1_EN_U1 (BIT(15)) -#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U1_V 0x1 -#define PCNT_THR_THRES1_EN_U1_S 15 +/*description: .*/ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_V 0x1 +#define PCNT_THR_THRES1_EN_U1_S 15 /* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_THR_THRES0_EN_U1 (BIT(14)) -#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U1_V 0x1 -#define PCNT_THR_THRES0_EN_U1_S 14 +/*description: .*/ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_V 0x1 +#define PCNT_THR_THRES0_EN_U1_S 14 /* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U1_V 0x1 -#define PCNT_THR_L_LIM_EN_U1_S 13 +/*description: .*/ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_V 0x1 +#define PCNT_THR_L_LIM_EN_U1_S 13 /* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U1_V 0x1 -#define PCNT_THR_H_LIM_EN_U1_S 12 +/*description: .*/ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_V 0x1 +#define PCNT_THR_H_LIM_EN_U1_S 12 /* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_ZERO_EN_U1 (BIT(11)) -#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U1_V 0x1 -#define PCNT_THR_ZERO_EN_U1_S 11 +/*description: .*/ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_V 0x1 +#define PCNT_THR_ZERO_EN_U1_S 11 /* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_FILTER_EN_U1 (BIT(10)) -#define PCNT_FILTER_EN_U1_M (BIT(10)) -#define PCNT_FILTER_EN_U1_V 0x1 -#define PCNT_FILTER_EN_U1_S 10 +/*description: .*/ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (BIT(10)) +#define PCNT_FILTER_EN_U1_V 0x1 +#define PCNT_FILTER_EN_U1_S 10 /* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: */ -#define PCNT_FILTER_THRES_U1 0x000003FF -#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V) << (PCNT_FILTER_THRES_U1_S)) -#define PCNT_FILTER_THRES_U1_V 0x3FF -#define PCNT_FILTER_THRES_U1_S 0 +/*description: .*/ +#define PCNT_FILTER_THRES_U1 0x000003FF +#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S)) +#define PCNT_FILTER_THRES_U1_V 0x3FF +#define PCNT_FILTER_THRES_U1_S 0 -#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10) /* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_THRES1_U1 0x0000FFFF -#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V) << (PCNT_CNT_THRES1_U1_S)) -#define PCNT_CNT_THRES1_U1_V 0xFFFF -#define PCNT_CNT_THRES1_U1_S 16 +/*description: .*/ +#define PCNT_CNT_THRES1_U1 0x0000FFFF +#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S)) +#define PCNT_CNT_THRES1_U1_V 0xFFFF +#define PCNT_CNT_THRES1_U1_S 16 /* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_THRES0_U1 0x0000FFFF -#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V) << (PCNT_CNT_THRES0_U1_S)) -#define PCNT_CNT_THRES0_U1_V 0xFFFF -#define PCNT_CNT_THRES0_U1_S 0 +/*description: .*/ +#define PCNT_CNT_THRES0_U1 0x0000FFFF +#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S)) +#define PCNT_CNT_THRES0_U1_V 0xFFFF +#define PCNT_CNT_THRES0_U1_S 0 -#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14) /* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_L_LIM_U1 0x0000FFFF -#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V) << (PCNT_CNT_L_LIM_U1_S)) -#define PCNT_CNT_L_LIM_U1_V 0xFFFF -#define PCNT_CNT_L_LIM_U1_S 16 +/*description: .*/ +#define PCNT_CNT_L_LIM_U1 0x0000FFFF +#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S)) +#define PCNT_CNT_L_LIM_U1_V 0xFFFF +#define PCNT_CNT_L_LIM_U1_S 16 /* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_H_LIM_U1 0x0000FFFF -#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V) << (PCNT_CNT_H_LIM_U1_S)) -#define PCNT_CNT_H_LIM_U1_V 0xFFFF -#define PCNT_CNT_H_LIM_U1_S 0 +/*description: .*/ +#define PCNT_CNT_H_LIM_U1 0x0000FFFF +#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S)) +#define PCNT_CNT_H_LIM_U1_V 0xFFFF +#define PCNT_CNT_H_LIM_U1_S 0 -#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18) /* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V) << (PCNT_CH1_LCTRL_MODE_U2_S)) -#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U2_S 30 +/*description: .*/ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S)) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U2_S 30 /* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V) << (PCNT_CH1_HCTRL_MODE_U2_S)) -#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/*description: .*/ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S)) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U2_S 28 /* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_POS_MODE_U2 0x00000003 -#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V) << (PCNT_CH1_POS_MODE_U2_S)) -#define PCNT_CH1_POS_MODE_U2_V 0x3 -#define PCNT_CH1_POS_MODE_U2_S 26 +/*description: .*/ +#define PCNT_CH1_POS_MODE_U2 0x00000003 +#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S)) +#define PCNT_CH1_POS_MODE_U2_V 0x3 +#define PCNT_CH1_POS_MODE_U2_S 26 /* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_NEG_MODE_U2 0x00000003 -#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V) << (PCNT_CH1_NEG_MODE_U2_S)) -#define PCNT_CH1_NEG_MODE_U2_V 0x3 -#define PCNT_CH1_NEG_MODE_U2_S 24 +/*description: .*/ +#define PCNT_CH1_NEG_MODE_U2 0x00000003 +#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S)) +#define PCNT_CH1_NEG_MODE_U2_V 0x3 +#define PCNT_CH1_NEG_MODE_U2_S 24 /* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V) << (PCNT_CH0_LCTRL_MODE_U2_S)) -#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/*description: .*/ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S)) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U2_S 22 /* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V) << (PCNT_CH0_HCTRL_MODE_U2_S)) -#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/*description: .*/ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S)) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U2_S 20 /* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_POS_MODE_U2 0x00000003 -#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V) << (PCNT_CH0_POS_MODE_U2_S)) -#define PCNT_CH0_POS_MODE_U2_V 0x3 -#define PCNT_CH0_POS_MODE_U2_S 18 +/*description: .*/ +#define PCNT_CH0_POS_MODE_U2 0x00000003 +#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S)) +#define PCNT_CH0_POS_MODE_U2_V 0x3 +#define PCNT_CH0_POS_MODE_U2_S 18 /* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_NEG_MODE_U2 0x00000003 -#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V) << (PCNT_CH0_NEG_MODE_U2_S)) -#define PCNT_CH0_NEG_MODE_U2_V 0x3 -#define PCNT_CH0_NEG_MODE_U2_S 16 +/*description: .*/ +#define PCNT_CH0_NEG_MODE_U2 0x00000003 +#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S)) +#define PCNT_CH0_NEG_MODE_U2_V 0x3 +#define PCNT_CH0_NEG_MODE_U2_S 16 /* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_THR_THRES1_EN_U2 (BIT(15)) -#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U2_V 0x1 -#define PCNT_THR_THRES1_EN_U2_S 15 +/*description: .*/ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_V 0x1 +#define PCNT_THR_THRES1_EN_U2_S 15 /* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_THR_THRES0_EN_U2 (BIT(14)) -#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U2_V 0x1 -#define PCNT_THR_THRES0_EN_U2_S 14 +/*description: .*/ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_V 0x1 +#define PCNT_THR_THRES0_EN_U2_S 14 /* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U2_V 0x1 -#define PCNT_THR_L_LIM_EN_U2_S 13 +/*description: .*/ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_V 0x1 +#define PCNT_THR_L_LIM_EN_U2_S 13 /* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U2_V 0x1 -#define PCNT_THR_H_LIM_EN_U2_S 12 +/*description: .*/ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_V 0x1 +#define PCNT_THR_H_LIM_EN_U2_S 12 /* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_ZERO_EN_U2 (BIT(11)) -#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U2_V 0x1 -#define PCNT_THR_ZERO_EN_U2_S 11 +/*description: .*/ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_V 0x1 +#define PCNT_THR_ZERO_EN_U2_S 11 /* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_FILTER_EN_U2 (BIT(10)) -#define PCNT_FILTER_EN_U2_M (BIT(10)) -#define PCNT_FILTER_EN_U2_V 0x1 -#define PCNT_FILTER_EN_U2_S 10 +/*description: .*/ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (BIT(10)) +#define PCNT_FILTER_EN_U2_V 0x1 +#define PCNT_FILTER_EN_U2_S 10 /* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: */ -#define PCNT_FILTER_THRES_U2 0x000003FF -#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V) << (PCNT_FILTER_THRES_U2_S)) -#define PCNT_FILTER_THRES_U2_V 0x3FF -#define PCNT_FILTER_THRES_U2_S 0 +/*description: .*/ +#define PCNT_FILTER_THRES_U2 0x000003FF +#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S)) +#define PCNT_FILTER_THRES_U2_V 0x3FF +#define PCNT_FILTER_THRES_U2_S 0 -#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1C) /* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_THRES1_U2 0x0000FFFF -#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V) << (PCNT_CNT_THRES1_U2_S)) -#define PCNT_CNT_THRES1_U2_V 0xFFFF -#define PCNT_CNT_THRES1_U2_S 16 +/*description: .*/ +#define PCNT_CNT_THRES1_U2 0x0000FFFF +#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S)) +#define PCNT_CNT_THRES1_U2_V 0xFFFF +#define PCNT_CNT_THRES1_U2_S 16 /* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_THRES0_U2 0x0000FFFF -#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V) << (PCNT_CNT_THRES0_U2_S)) -#define PCNT_CNT_THRES0_U2_V 0xFFFF -#define PCNT_CNT_THRES0_U2_S 0 +/*description: .*/ +#define PCNT_CNT_THRES0_U2 0x0000FFFF +#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S)) +#define PCNT_CNT_THRES0_U2_V 0xFFFF +#define PCNT_CNT_THRES0_U2_S 0 -#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20) /* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_L_LIM_U2 0x0000FFFF -#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V) << (PCNT_CNT_L_LIM_U2_S)) -#define PCNT_CNT_L_LIM_U2_V 0xFFFF -#define PCNT_CNT_L_LIM_U2_S 16 +/*description: .*/ +#define PCNT_CNT_L_LIM_U2 0x0000FFFF +#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S)) +#define PCNT_CNT_L_LIM_U2_V 0xFFFF +#define PCNT_CNT_L_LIM_U2_S 16 /* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_H_LIM_U2 0x0000FFFF -#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V) << (PCNT_CNT_H_LIM_U2_S)) -#define PCNT_CNT_H_LIM_U2_V 0xFFFF -#define PCNT_CNT_H_LIM_U2_S 0 +/*description: .*/ +#define PCNT_CNT_H_LIM_U2 0x0000FFFF +#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S)) +#define PCNT_CNT_H_LIM_U2_V 0xFFFF +#define PCNT_CNT_H_LIM_U2_S 0 -#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24) /* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V) << (PCNT_CH1_LCTRL_MODE_U3_S)) -#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U3_S 30 +/*description: .*/ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S)) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U3_S 30 /* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V) << (PCNT_CH1_HCTRL_MODE_U3_S)) -#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/*description: .*/ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S)) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U3_S 28 /* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_POS_MODE_U3 0x00000003 -#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V) << (PCNT_CH1_POS_MODE_U3_S)) -#define PCNT_CH1_POS_MODE_U3_V 0x3 -#define PCNT_CH1_POS_MODE_U3_S 26 +/*description: .*/ +#define PCNT_CH1_POS_MODE_U3 0x00000003 +#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S)) +#define PCNT_CH1_POS_MODE_U3_V 0x3 +#define PCNT_CH1_POS_MODE_U3_S 26 /* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH1_NEG_MODE_U3 0x00000003 -#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V) << (PCNT_CH1_NEG_MODE_U3_S)) -#define PCNT_CH1_NEG_MODE_U3_V 0x3 -#define PCNT_CH1_NEG_MODE_U3_S 24 +/*description: .*/ +#define PCNT_CH1_NEG_MODE_U3 0x00000003 +#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S)) +#define PCNT_CH1_NEG_MODE_U3_V 0x3 +#define PCNT_CH1_NEG_MODE_U3_S 24 /* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V) << (PCNT_CH0_LCTRL_MODE_U3_S)) -#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/*description: .*/ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S)) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U3_S 22 /* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V) << (PCNT_CH0_HCTRL_MODE_U3_S)) -#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/*description: .*/ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S)) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U3_S 20 /* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_POS_MODE_U3 0x00000003 -#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V) << (PCNT_CH0_POS_MODE_U3_S)) -#define PCNT_CH0_POS_MODE_U3_V 0x3 -#define PCNT_CH0_POS_MODE_U3_S 18 +/*description: .*/ +#define PCNT_CH0_POS_MODE_U3 0x00000003 +#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S)) +#define PCNT_CH0_POS_MODE_U3_V 0x3 +#define PCNT_CH0_POS_MODE_U3_S 18 /* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: */ -#define PCNT_CH0_NEG_MODE_U3 0x00000003 -#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V) << (PCNT_CH0_NEG_MODE_U3_S)) -#define PCNT_CH0_NEG_MODE_U3_V 0x3 -#define PCNT_CH0_NEG_MODE_U3_S 16 +/*description: .*/ +#define PCNT_CH0_NEG_MODE_U3 0x00000003 +#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S)) +#define PCNT_CH0_NEG_MODE_U3_V 0x3 +#define PCNT_CH0_NEG_MODE_U3_S 16 /* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_THR_THRES1_EN_U3 (BIT(15)) -#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U3_V 0x1 -#define PCNT_THR_THRES1_EN_U3_S 15 +/*description: .*/ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_V 0x1 +#define PCNT_THR_THRES1_EN_U3_S 15 /* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_THR_THRES0_EN_U3 (BIT(14)) -#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U3_V 0x1 -#define PCNT_THR_THRES0_EN_U3_S 14 +/*description: .*/ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_V 0x1 +#define PCNT_THR_THRES0_EN_U3_S 14 /* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U3_V 0x1 -#define PCNT_THR_L_LIM_EN_U3_S 13 +/*description: .*/ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_V 0x1 +#define PCNT_THR_L_LIM_EN_U3_S 13 /* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U3_V 0x1 -#define PCNT_THR_H_LIM_EN_U3_S 12 +/*description: .*/ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_V 0x1 +#define PCNT_THR_H_LIM_EN_U3_S 12 /* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_THR_ZERO_EN_U3 (BIT(11)) -#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U3_V 0x1 -#define PCNT_THR_ZERO_EN_U3_S 11 +/*description: .*/ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_V 0x1 +#define PCNT_THR_ZERO_EN_U3_S 11 /* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_FILTER_EN_U3 (BIT(10)) -#define PCNT_FILTER_EN_U3_M (BIT(10)) -#define PCNT_FILTER_EN_U3_V 0x1 -#define PCNT_FILTER_EN_U3_S 10 +/*description: .*/ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (BIT(10)) +#define PCNT_FILTER_EN_U3_V 0x1 +#define PCNT_FILTER_EN_U3_S 10 /* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: */ -#define PCNT_FILTER_THRES_U3 0x000003FF -#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V) << (PCNT_FILTER_THRES_U3_S)) -#define PCNT_FILTER_THRES_U3_V 0x3FF -#define PCNT_FILTER_THRES_U3_S 0 +/*description: .*/ +#define PCNT_FILTER_THRES_U3 0x000003FF +#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S)) +#define PCNT_FILTER_THRES_U3_V 0x3FF +#define PCNT_FILTER_THRES_U3_S 0 -#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28) /* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_THRES1_U3 0x0000FFFF -#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V) << (PCNT_CNT_THRES1_U3_S)) -#define PCNT_CNT_THRES1_U3_V 0xFFFF -#define PCNT_CNT_THRES1_U3_S 16 +/*description: .*/ +#define PCNT_CNT_THRES1_U3 0x0000FFFF +#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S)) +#define PCNT_CNT_THRES1_U3_V 0xFFFF +#define PCNT_CNT_THRES1_U3_S 16 /* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_THRES0_U3 0x0000FFFF -#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V) << (PCNT_CNT_THRES0_U3_S)) -#define PCNT_CNT_THRES0_U3_V 0xFFFF -#define PCNT_CNT_THRES0_U3_S 0 +/*description: .*/ +#define PCNT_CNT_THRES0_U3 0x0000FFFF +#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S)) +#define PCNT_CNT_THRES0_U3_V 0xFFFF +#define PCNT_CNT_THRES0_U3_S 0 -#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2C) /* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_L_LIM_U3 0x0000FFFF -#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V) << (PCNT_CNT_L_LIM_U3_S)) -#define PCNT_CNT_L_LIM_U3_V 0xFFFF -#define PCNT_CNT_L_LIM_U3_S 16 +/*description: .*/ +#define PCNT_CNT_L_LIM_U3 0x0000FFFF +#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S)) +#define PCNT_CNT_L_LIM_U3_V 0xFFFF +#define PCNT_CNT_L_LIM_U3_S 16 /* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: */ -#define PCNT_CNT_H_LIM_U3 0x0000FFFF -#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V) << (PCNT_CNT_H_LIM_U3_S)) -#define PCNT_CNT_H_LIM_U3_V 0xFFFF -#define PCNT_CNT_H_LIM_U3_S 0 +/*description: .*/ +#define PCNT_CNT_H_LIM_U3 0x0000FFFF +#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S)) +#define PCNT_CNT_H_LIM_U3_V 0xFFFF +#define PCNT_CNT_H_LIM_U3_S 0 -#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0030) +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30) /* PCNT_PULSE_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define PCNT_PULSE_CNT_U0 0x0000FFFF -#define PCNT_PULSE_CNT_U0_M ((PCNT_PULSE_CNT_U0_V) << (PCNT_PULSE_CNT_U0_S)) -#define PCNT_PULSE_CNT_U0_V 0xFFFF -#define PCNT_PULSE_CNT_U0_S 0 +/*description: .*/ +#define PCNT_PULSE_CNT_U0 0x0000FFFF +#define PCNT_PULSE_CNT_U0_M ((PCNT_PULSE_CNT_U0_V)<<(PCNT_PULSE_CNT_U0_S)) +#define PCNT_PULSE_CNT_U0_V 0xFFFF +#define PCNT_PULSE_CNT_U0_S 0 -#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0034) +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34) /* PCNT_PULSE_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define PCNT_PULSE_CNT_U1 0x0000FFFF -#define PCNT_PULSE_CNT_U1_M ((PCNT_PULSE_CNT_U1_V) << (PCNT_PULSE_CNT_U1_S)) -#define PCNT_PULSE_CNT_U1_V 0xFFFF -#define PCNT_PULSE_CNT_U1_S 0 +/*description: .*/ +#define PCNT_PULSE_CNT_U1 0x0000FFFF +#define PCNT_PULSE_CNT_U1_M ((PCNT_PULSE_CNT_U1_V)<<(PCNT_PULSE_CNT_U1_S)) +#define PCNT_PULSE_CNT_U1_V 0xFFFF +#define PCNT_PULSE_CNT_U1_S 0 -#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0038) +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38) /* PCNT_PULSE_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define PCNT_PULSE_CNT_U2 0x0000FFFF -#define PCNT_PULSE_CNT_U2_M ((PCNT_PULSE_CNT_U2_V) << (PCNT_PULSE_CNT_U2_S)) -#define PCNT_PULSE_CNT_U2_V 0xFFFF -#define PCNT_PULSE_CNT_U2_S 0 +/*description: .*/ +#define PCNT_PULSE_CNT_U2 0x0000FFFF +#define PCNT_PULSE_CNT_U2_M ((PCNT_PULSE_CNT_U2_V)<<(PCNT_PULSE_CNT_U2_S)) +#define PCNT_PULSE_CNT_U2_V 0xFFFF +#define PCNT_PULSE_CNT_U2_S 0 -#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x003c) +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3C) /* PCNT_PULSE_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define PCNT_PULSE_CNT_U3 0x0000FFFF -#define PCNT_PULSE_CNT_U3_M ((PCNT_PULSE_CNT_U3_V) << (PCNT_PULSE_CNT_U3_S)) -#define PCNT_PULSE_CNT_U3_V 0xFFFF -#define PCNT_PULSE_CNT_U3_S 0 +/*description: .*/ +#define PCNT_PULSE_CNT_U3 0x0000FFFF +#define PCNT_PULSE_CNT_U3_M ((PCNT_PULSE_CNT_U3_V)<<(PCNT_PULSE_CNT_U3_S)) +#define PCNT_PULSE_CNT_U3_V 0xFFFF +#define PCNT_PULSE_CNT_U3_S 0 -#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0040) +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40) /* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 /* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 /* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 /* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 -#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0044) +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44) /* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 /* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 /* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 /* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 -#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0048) +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48) /* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 /* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 /* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 /* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 -#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x004c) +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4C) /* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 /* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 /* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 /* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 +/*description: .*/ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 -#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0050) +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50) /* PCNT_CNT_THR_ZERO_LAT_U0 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U0_M (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x1 -#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 +/*description: .*/ +#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_M (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x1 +#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 /* PCNT_CNT_THR_H_LIM_LAT_U0 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U0_M (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x1 -#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 +/*description: .*/ +#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_M (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x1 +#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 /* PCNT_CNT_THR_L_LIM_LAT_U0 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U0_M (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x1 -#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 +/*description: .*/ +#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_M (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x1 +#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 /* PCNT_CNT_THR_THRES0_LAT_U0 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U0_M (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x1 -#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 +/*description: .*/ +#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_M (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x1 +#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 /* PCNT_CNT_THR_THRES1_LAT_U0 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U0_M (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x1 -#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 +/*description: .*/ +#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_M (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x1 +#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 /* PCNT_CNT_THR_ZERO_MODE_U0 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003 -#define PCNT_CNT_THR_ZERO_MODE_U0_M ((PCNT_CNT_THR_ZERO_MODE_U0_V) << (PCNT_CNT_THR_ZERO_MODE_U0_S)) -#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x3 -#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 +/*description: .*/ +#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003 +#define PCNT_CNT_THR_ZERO_MODE_U0_M ((PCNT_CNT_THR_ZERO_MODE_U0_V)<<(PCNT_CNT_THR_ZERO_MODE_U0_S)) +#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x3 +#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 -#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0054) +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54) /* PCNT_CNT_THR_ZERO_LAT_U1 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U1_M (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x1 -#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 +/*description: .*/ +#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_M (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x1 +#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 /* PCNT_CNT_THR_H_LIM_LAT_U1 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U1_M (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x1 -#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 +/*description: .*/ +#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_M (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x1 +#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 /* PCNT_CNT_THR_L_LIM_LAT_U1 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U1_M (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x1 -#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 +/*description: .*/ +#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_M (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x1 +#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 /* PCNT_CNT_THR_THRES0_LAT_U1 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U1_M (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x1 -#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 +/*description: .*/ +#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_M (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x1 +#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 /* PCNT_CNT_THR_THRES1_LAT_U1 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U1_M (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x1 -#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 +/*description: .*/ +#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_M (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x1 +#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 /* PCNT_CNT_THR_ZERO_MODE_U1 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003 -#define PCNT_CNT_THR_ZERO_MODE_U1_M ((PCNT_CNT_THR_ZERO_MODE_U1_V) << (PCNT_CNT_THR_ZERO_MODE_U1_S)) -#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x3 -#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 +/*description: .*/ +#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003 +#define PCNT_CNT_THR_ZERO_MODE_U1_M ((PCNT_CNT_THR_ZERO_MODE_U1_V)<<(PCNT_CNT_THR_ZERO_MODE_U1_S)) +#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x3 +#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 -#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0058) +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58) /* PCNT_CNT_THR_ZERO_LAT_U2 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U2_M (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x1 -#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 +/*description: .*/ +#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_M (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x1 +#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 /* PCNT_CNT_THR_H_LIM_LAT_U2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U2_M (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x1 -#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 +/*description: .*/ +#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_M (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x1 +#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 /* PCNT_CNT_THR_L_LIM_LAT_U2 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U2_M (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x1 -#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 +/*description: .*/ +#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_M (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x1 +#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 /* PCNT_CNT_THR_THRES0_LAT_U2 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U2_M (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x1 -#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 +/*description: .*/ +#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_M (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x1 +#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 /* PCNT_CNT_THR_THRES1_LAT_U2 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U2_M (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x1 -#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 +/*description: .*/ +#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_M (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x1 +#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 /* PCNT_CNT_THR_ZERO_MODE_U2 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003 -#define PCNT_CNT_THR_ZERO_MODE_U2_M ((PCNT_CNT_THR_ZERO_MODE_U2_V) << (PCNT_CNT_THR_ZERO_MODE_U2_S)) -#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x3 -#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 +/*description: .*/ +#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003 +#define PCNT_CNT_THR_ZERO_MODE_U2_M ((PCNT_CNT_THR_ZERO_MODE_U2_V)<<(PCNT_CNT_THR_ZERO_MODE_U2_S)) +#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x3 +#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 -#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x005c) +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5C) /* PCNT_CNT_THR_ZERO_LAT_U3 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U3_M (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x1 -#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 +/*description: .*/ +#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_M (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x1 +#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 /* PCNT_CNT_THR_H_LIM_LAT_U3 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U3_M (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x1 -#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 +/*description: .*/ +#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_M (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x1 +#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 /* PCNT_CNT_THR_L_LIM_LAT_U3 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U3_M (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x1 -#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 +/*description: .*/ +#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_M (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x1 +#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 /* PCNT_CNT_THR_THRES0_LAT_U3 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U3_M (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x1 -#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 +/*description: .*/ +#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_M (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x1 +#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 /* PCNT_CNT_THR_THRES1_LAT_U3 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U3_M (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x1 -#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 +/*description: .*/ +#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_M (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x1 +#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 /* PCNT_CNT_THR_ZERO_MODE_U3 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003 -#define PCNT_CNT_THR_ZERO_MODE_U3_M ((PCNT_CNT_THR_ZERO_MODE_U3_V) << (PCNT_CNT_THR_ZERO_MODE_U3_S)) -#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x3 -#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 +/*description: .*/ +#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003 +#define PCNT_CNT_THR_ZERO_MODE_U3_M ((PCNT_CNT_THR_ZERO_MODE_U3_V)<<(PCNT_CNT_THR_ZERO_MODE_U3_S)) +#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x3 +#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 -#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x0060) +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60) /* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CLK_EN (BIT(16)) -#define PCNT_CLK_EN_M (BIT(16)) -#define PCNT_CLK_EN_V 0x1 -#define PCNT_CLK_EN_S 16 +/*description: .*/ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (BIT(16)) +#define PCNT_CLK_EN_V 0x1 +#define PCNT_CLK_EN_S 16 /* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_PAUSE_U3 (BIT(7)) -#define PCNT_CNT_PAUSE_U3_M (BIT(7)) -#define PCNT_CNT_PAUSE_U3_V 0x1 -#define PCNT_CNT_PAUSE_U3_S 7 +/*description: .*/ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (BIT(7)) +#define PCNT_CNT_PAUSE_U3_V 0x1 +#define PCNT_CNT_PAUSE_U3_S 7 /* PCNT_PULSE_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) -#define PCNT_PULSE_CNT_RST_U3_M (BIT(6)) -#define PCNT_PULSE_CNT_RST_U3_V 0x1 -#define PCNT_PULSE_CNT_RST_U3_S 6 +/*description: .*/ +#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_M (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_V 0x1 +#define PCNT_PULSE_CNT_RST_U3_S 6 /* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_PAUSE_U2 (BIT(5)) -#define PCNT_CNT_PAUSE_U2_M (BIT(5)) -#define PCNT_CNT_PAUSE_U2_V 0x1 -#define PCNT_CNT_PAUSE_U2_S 5 +/*description: .*/ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (BIT(5)) +#define PCNT_CNT_PAUSE_U2_V 0x1 +#define PCNT_CNT_PAUSE_U2_S 5 /* PCNT_PULSE_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) -#define PCNT_PULSE_CNT_RST_U2_M (BIT(4)) -#define PCNT_PULSE_CNT_RST_U2_V 0x1 -#define PCNT_PULSE_CNT_RST_U2_S 4 +/*description: .*/ +#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_M (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_V 0x1 +#define PCNT_PULSE_CNT_RST_U2_S 4 /* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_PAUSE_U1 (BIT(3)) -#define PCNT_CNT_PAUSE_U1_M (BIT(3)) -#define PCNT_CNT_PAUSE_U1_V 0x1 -#define PCNT_CNT_PAUSE_U1_S 3 +/*description: .*/ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (BIT(3)) +#define PCNT_CNT_PAUSE_U1_V 0x1 +#define PCNT_CNT_PAUSE_U1_S 3 /* PCNT_PULSE_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) -#define PCNT_PULSE_CNT_RST_U1_M (BIT(2)) -#define PCNT_PULSE_CNT_RST_U1_V 0x1 -#define PCNT_PULSE_CNT_RST_U1_S 2 +/*description: .*/ +#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_M (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_V 0x1 +#define PCNT_PULSE_CNT_RST_U1_S 2 /* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_PAUSE_U0 (BIT(1)) -#define PCNT_CNT_PAUSE_U0_M (BIT(1)) -#define PCNT_CNT_PAUSE_U0_V 0x1 -#define PCNT_CNT_PAUSE_U0_S 1 +/*description: .*/ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (BIT(1)) +#define PCNT_CNT_PAUSE_U0_V 0x1 +#define PCNT_CNT_PAUSE_U0_S 1 /* PCNT_PULSE_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) -#define PCNT_PULSE_CNT_RST_U0_M (BIT(0)) -#define PCNT_PULSE_CNT_RST_U0_V 0x1 -#define PCNT_PULSE_CNT_RST_U0_S 0 +/*description: .*/ +#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_M (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_V 0x1 +#define PCNT_PULSE_CNT_RST_U0_S 0 -#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xFC) /* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072600 ; */ -/*description: */ -#define PCNT_DATE 0xFFFFFFFF -#define PCNT_DATE_M ((PCNT_DATE_V) << (PCNT_DATE_S)) -#define PCNT_DATE_V 0xFFFFFFFF -#define PCNT_DATE_S 0 +/*description: .*/ +#define PCNT_DATE 0xFFFFFFFF +#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S)) +#define PCNT_DATE_V 0xFFFFFFFF +#define PCNT_DATE_S 0 + #ifdef __cplusplus } #endif + + + +#endif /*_SOC_PCNT_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/pcnt_struct.h b/components/soc/esp32s3/include/soc/pcnt_struct.h index d01aa09ffd..1d022363d9 100644 --- a/components/soc/esp32s3/include/soc/pcnt_struct.h +++ b/components/soc/esp32s3/include/soc/pcnt_struct.h @@ -23,111 +23,111 @@ typedef volatile struct { struct { union { struct { - uint32_t filter_thres: 10; - uint32_t filter_en: 1; - uint32_t thr_zero_en: 1; - uint32_t thr_h_lim_en: 1; - uint32_t thr_l_lim_en: 1; - uint32_t thr_thres0_en: 1; - uint32_t thr_thres1_en: 1; - uint32_t ch0_neg_mode: 2; - uint32_t ch0_pos_mode: 2; - uint32_t ch0_hctrl_mode: 2; - uint32_t ch0_lctrl_mode: 2; - uint32_t ch1_neg_mode: 2; - uint32_t ch1_pos_mode: 2; - uint32_t ch1_hctrl_mode: 2; - uint32_t ch1_lctrl_mode: 2; + uint32_t filter_thres : 10; + uint32_t filter_en : 1; + uint32_t thr_zero_en : 1; + uint32_t thr_h_lim_en : 1; + uint32_t thr_l_lim_en : 1; + uint32_t thr_thres0_en : 1; + uint32_t thr_thres1_en : 1; + uint32_t ch0_neg_mode : 2; + uint32_t ch0_pos_mode : 2; + uint32_t ch0_hctrl_mode : 2; + uint32_t ch0_lctrl_mode : 2; + uint32_t ch1_neg_mode : 2; + uint32_t ch1_pos_mode : 2; + uint32_t ch1_hctrl_mode : 2; + uint32_t ch1_lctrl_mode : 2; }; uint32_t val; } conf0; union { struct { - uint32_t cnt_thres0: 16; - uint32_t cnt_thres1: 16; + uint32_t cnt_thres0 : 16; + uint32_t cnt_thres1 : 16; }; uint32_t val; } conf1; union { struct { - uint32_t cnt_h_lim: 16; - uint32_t cnt_l_lim: 16; + uint32_t cnt_h_lim : 16; + uint32_t cnt_l_lim : 16; }; uint32_t val; } conf2; } conf_unit[4]; union { struct { - uint32_t cnt_val: 16; - uint32_t reserved16: 16; + uint32_t cnt_val : 16; + uint32_t reserved16 : 16; }; uint32_t val; } cnt_unit[4]; union { struct { - uint32_t cnt_thr_event_u0: 1; - uint32_t cnt_thr_event_u1: 1; - uint32_t cnt_thr_event_u2: 1; - uint32_t cnt_thr_event_u3: 1; - uint32_t reserved4: 28; + uint32_t cnt_thr_event_u0 : 1; + uint32_t cnt_thr_event_u1 : 1; + uint32_t cnt_thr_event_u2 : 1; + uint32_t cnt_thr_event_u3 : 1; + uint32_t reserved4 : 28; }; uint32_t val; } int_raw; union { struct { - uint32_t cnt_thr_event_u0: 1; - uint32_t cnt_thr_event_u1: 1; - uint32_t cnt_thr_event_u2: 1; - uint32_t cnt_thr_event_u3: 1; - uint32_t reserved4: 28; + uint32_t cnt_thr_event_u0 : 1; + uint32_t cnt_thr_event_u1 : 1; + uint32_t cnt_thr_event_u2 : 1; + uint32_t cnt_thr_event_u3 : 1; + uint32_t reserved4 : 28; }; uint32_t val; } int_st; union { struct { - uint32_t cnt_thr_event_u0: 1; - uint32_t cnt_thr_event_u1: 1; - uint32_t cnt_thr_event_u2: 1; - uint32_t cnt_thr_event_u3: 1; - uint32_t reserved4: 28; + uint32_t cnt_thr_event_u0 : 1; + uint32_t cnt_thr_event_u1 : 1; + uint32_t cnt_thr_event_u2 : 1; + uint32_t cnt_thr_event_u3 : 1; + uint32_t reserved4 : 28; }; uint32_t val; } int_ena; union { struct { - uint32_t cnt_thr_event_u0: 1; - uint32_t cnt_thr_event_u1: 1; - uint32_t cnt_thr_event_u2: 1; - uint32_t cnt_thr_event_u3: 1; - uint32_t reserved4: 28; + uint32_t cnt_thr_event_u0 : 1; + uint32_t cnt_thr_event_u1 : 1; + uint32_t cnt_thr_event_u2 : 1; + uint32_t cnt_thr_event_u3 : 1; + uint32_t reserved4 : 28; }; uint32_t val; } int_clr; union { struct { - uint32_t cnt_mode: 2; - uint32_t thres1_lat: 1; - uint32_t thres0_lat: 1; - uint32_t l_lim_lat: 1; - uint32_t h_lim_lat: 1; - uint32_t zero_lat: 1; - uint32_t reserved7: 25; + uint32_t zero_mode : 2; + uint32_t thres1_lat : 1; + uint32_t thres0_lat : 1; + uint32_t l_lim_lat : 1; + uint32_t h_lim_lat : 1; + uint32_t zero_lat : 1; + uint32_t reserved7 : 25; }; uint32_t val; } status_unit[4]; union { struct { - uint32_t cnt_rst_u0: 1; - uint32_t cnt_pause_u0: 1; - uint32_t cnt_rst_u1: 1; - uint32_t cnt_pause_u1: 1; - uint32_t cnt_rst_u2: 1; - uint32_t cnt_pause_u2: 1; - uint32_t cnt_rst_u3: 1; - uint32_t cnt_pause_u3: 1; - uint32_t reserved8: 8; - uint32_t clk_en: 1; - uint32_t reserved17: 15; + uint32_t cnt_rst_u0 : 1; + uint32_t cnt_pause_u0 : 1; + uint32_t cnt_rst_u1 : 1; + uint32_t cnt_pause_u1 : 1; + uint32_t cnt_rst_u2 : 1; + uint32_t cnt_pause_u2 : 1; + uint32_t cnt_rst_u3 : 1; + uint32_t cnt_pause_u3 : 1; + uint32_t reserved8 : 8; + uint32_t clk_en : 1; + uint32_t reserved17 : 15; }; uint32_t val; } ctrl; @@ -169,11 +169,9 @@ typedef volatile struct { uint32_t reserved_f0; uint32_t reserved_f4; uint32_t reserved_f8; - uint32_t date; /**/ + uint32_t date; } pcnt_dev_t; - extern pcnt_dev_t PCNT; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/peri_backup_reg.h b/components/soc/esp32s3/include/soc/peri_backup_reg.h new file mode 100644 index 0000000000..ce050c51b3 --- /dev/null +++ b/components/soc/esp32s3/include/soc/peri_backup_reg.h @@ -0,0 +1,198 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PERI_BACKUP_REG_H_ +#define _SOC_PERI_BACKUP_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define PERI_BACKUP_CONFIG_REG (DR_REG_PERI_BACKUP_BASE + 0x0) +/* PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define PERI_BACKUP_ENA (BIT(31)) +#define PERI_BACKUP_ENA_M (BIT(31)) +#define PERI_BACKUP_ENA_V 0x1 +#define PERI_BACKUP_ENA_S 31 +/* PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define PERI_BACKUP_TO_MEM (BIT(30)) +#define PERI_BACKUP_TO_MEM_M (BIT(30)) +#define PERI_BACKUP_TO_MEM_V 0x1 +#define PERI_BACKUP_TO_MEM_S 30 +/* PERI_BACKUP_START : WT ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define PERI_BACKUP_START (BIT(29)) +#define PERI_BACKUP_START_M (BIT(29)) +#define PERI_BACKUP_START_V 0x1 +#define PERI_BACKUP_START_S 29 +/* PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_SIZE 0x000003FF +#define PERI_BACKUP_SIZE_M ((PERI_BACKUP_SIZE_V)<<(PERI_BACKUP_SIZE_S)) +#define PERI_BACKUP_SIZE_V 0x3FF +#define PERI_BACKUP_SIZE_S 19 +/* PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */ +/*description: .*/ +#define PERI_BACKUP_TOUT_THRES 0x000003FF +#define PERI_BACKUP_TOUT_THRES_M ((PERI_BACKUP_TOUT_THRES_V)<<(PERI_BACKUP_TOUT_THRES_S)) +#define PERI_BACKUP_TOUT_THRES_V 0x3FF +#define PERI_BACKUP_TOUT_THRES_S 9 +/* PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */ +/*description: .*/ +#define PERI_BACKUP_BURST_LIMIT 0x0000001F +#define PERI_BACKUP_BURST_LIMIT_M ((PERI_BACKUP_BURST_LIMIT_V)<<(PERI_BACKUP_BURST_LIMIT_S)) +#define PERI_BACKUP_BURST_LIMIT_V 0x1F +#define PERI_BACKUP_BURST_LIMIT_S 4 +/* PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define PERI_BACKUP_ADDR_MAP_MODE (BIT(3)) +#define PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3)) +#define PERI_BACKUP_ADDR_MAP_MODE_V 0x1 +#define PERI_BACKUP_ADDR_MAP_MODE_S 3 +/* PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_FLOW_ERR 0x00000007 +#define PERI_BACKUP_FLOW_ERR_M ((PERI_BACKUP_FLOW_ERR_V)<<(PERI_BACKUP_FLOW_ERR_S)) +#define PERI_BACKUP_FLOW_ERR_V 0x7 +#define PERI_BACKUP_FLOW_ERR_S 0 + +#define PERI_BACKUP_APB_ADDR_REG (DR_REG_PERI_BACKUP_BASE + 0x4) +/* PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF +#define PERI_BACKUP_APB_START_ADDR_M ((PERI_BACKUP_APB_START_ADDR_V)<<(PERI_BACKUP_APB_START_ADDR_S)) +#define PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF +#define PERI_BACKUP_APB_START_ADDR_S 0 + +#define PERI_BACKUP_MEM_ADDR_REG (DR_REG_PERI_BACKUP_BASE + 0x8) +/* PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF +#define PERI_BACKUP_MEM_START_ADDR_M ((PERI_BACKUP_MEM_START_ADDR_V)<<(PERI_BACKUP_MEM_START_ADDR_S)) +#define PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF +#define PERI_BACKUP_MEM_START_ADDR_S 0 + +#define PERI_BACKUP_REG_MAP0_REG (DR_REG_PERI_BACKUP_BASE + 0xC) +/* PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_MAP0 0xFFFFFFFF +#define PERI_BACKUP_MAP0_M ((PERI_BACKUP_MAP0_V)<<(PERI_BACKUP_MAP0_S)) +#define PERI_BACKUP_MAP0_V 0xFFFFFFFF +#define PERI_BACKUP_MAP0_S 0 + +#define PERI_BACKUP_REG_MAP1_REG (DR_REG_PERI_BACKUP_BASE + 0x10) +/* PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_MAP1 0xFFFFFFFF +#define PERI_BACKUP_MAP1_M ((PERI_BACKUP_MAP1_V)<<(PERI_BACKUP_MAP1_S)) +#define PERI_BACKUP_MAP1_V 0xFFFFFFFF +#define PERI_BACKUP_MAP1_S 0 + +#define PERI_BACKUP_REG_MAP2_REG (DR_REG_PERI_BACKUP_BASE + 0x14) +/* PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_MAP2 0xFFFFFFFF +#define PERI_BACKUP_MAP2_M ((PERI_BACKUP_MAP2_V)<<(PERI_BACKUP_MAP2_S)) +#define PERI_BACKUP_MAP2_V 0xFFFFFFFF +#define PERI_BACKUP_MAP2_S 0 + +#define PERI_BACKUP_REG_MAP3_REG (DR_REG_PERI_BACKUP_BASE + 0x18) +/* PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_MAP3 0xFFFFFFFF +#define PERI_BACKUP_MAP3_M ((PERI_BACKUP_MAP3_V)<<(PERI_BACKUP_MAP3_S)) +#define PERI_BACKUP_MAP3_V 0xFFFFFFFF +#define PERI_BACKUP_MAP3_S 0 + +#define PERI_BACKUP_INT_RAW_REG (DR_REG_PERI_BACKUP_BASE + 0x1C) +/* PERI_BACKUP_ERR_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_ERR_INT_RAW (BIT(1)) +#define PERI_BACKUP_ERR_INT_RAW_M (BIT(1)) +#define PERI_BACKUP_ERR_INT_RAW_V 0x1 +#define PERI_BACKUP_ERR_INT_RAW_S 1 +/* PERI_BACKUP_DONE_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_DONE_INT_RAW (BIT(0)) +#define PERI_BACKUP_DONE_INT_RAW_M (BIT(0)) +#define PERI_BACKUP_DONE_INT_RAW_V 0x1 +#define PERI_BACKUP_DONE_INT_RAW_S 0 + +#define PERI_BACKUP_INT_ST_REG (DR_REG_PERI_BACKUP_BASE + 0x20) +/* PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_ERR_INT_ST (BIT(1)) +#define PERI_BACKUP_ERR_INT_ST_M (BIT(1)) +#define PERI_BACKUP_ERR_INT_ST_V 0x1 +#define PERI_BACKUP_ERR_INT_ST_S 1 +/* PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_DONE_INT_ST (BIT(0)) +#define PERI_BACKUP_DONE_INT_ST_M (BIT(0)) +#define PERI_BACKUP_DONE_INT_ST_V 0x1 +#define PERI_BACKUP_DONE_INT_ST_S 0 + +#define PERI_BACKUP_INT_ENA_REG (DR_REG_PERI_BACKUP_BASE + 0x24) +/* PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_ERR_INT_ENA (BIT(1)) +#define PERI_BACKUP_ERR_INT_ENA_M (BIT(1)) +#define PERI_BACKUP_ERR_INT_ENA_V 0x1 +#define PERI_BACKUP_ERR_INT_ENA_S 1 +/* PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_DONE_INT_ENA (BIT(0)) +#define PERI_BACKUP_DONE_INT_ENA_M (BIT(0)) +#define PERI_BACKUP_DONE_INT_ENA_V 0x1 +#define PERI_BACKUP_DONE_INT_ENA_S 0 + +#define PERI_BACKUP_INT_CLR_REG (DR_REG_PERI_BACKUP_BASE + 0x28) +/* PERI_BACKUP_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_ERR_INT_CLR (BIT(1)) +#define PERI_BACKUP_ERR_INT_CLR_M (BIT(1)) +#define PERI_BACKUP_ERR_INT_CLR_V 0x1 +#define PERI_BACKUP_ERR_INT_CLR_S 1 +/* PERI_BACKUP_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'd0 ; */ +/*description: .*/ +#define PERI_BACKUP_DONE_INT_CLR (BIT(0)) +#define PERI_BACKUP_DONE_INT_CLR_M (BIT(0)) +#define PERI_BACKUP_DONE_INT_CLR_V 0x1 +#define PERI_BACKUP_DONE_INT_CLR_S 0 + +#define PERI_BACKUP_DATE_REG (DR_REG_PERI_BACKUP_BASE + 0xFC) +/* PERI_BACKUP_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: register file clk gating.*/ +#define PERI_BACKUP_CLK_EN (BIT(31)) +#define PERI_BACKUP_CLK_EN_M (BIT(31)) +#define PERI_BACKUP_CLK_EN_V 0x1 +#define PERI_BACKUP_CLK_EN_S 31 +/* PERI_BACKUP_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */ +/*description: .*/ +#define PERI_BACKUP_DATE 0x0FFFFFFF +#define PERI_BACKUP_DATE_M ((PERI_BACKUP_DATE_V)<<(PERI_BACKUP_DATE_S)) +#define PERI_BACKUP_DATE_V 0xFFFFFFF +#define PERI_BACKUP_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_PERI_BACKUP_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/periph_defs.h b/components/soc/esp32s3/include/soc/periph_defs.h index ad53c5e2e8..d4acd777c7 100644 --- a/components/soc/esp32s3/include/soc/periph_defs.h +++ b/components/soc/esp32s3/include/soc/periph_defs.h @@ -33,6 +33,8 @@ typedef enum { PERIPH_TIMG1_MODULE, PERIPH_PWM0_MODULE, PERIPH_PWM1_MODULE, + PERIPH_PWM2_MODULE, + PERIPH_PWM3_MODULE, PERIPH_UHCI0_MODULE, PERIPH_UHCI1_MODULE, PERIPH_RMT_MODULE, @@ -130,6 +132,11 @@ typedef enum { ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/ ETS_DMA_CH3_INTR_SOURCE, /**< interrupt of general DMA channel 3, LEVEL*/ ETS_DMA_CH4_INTR_SOURCE, /**< interrupt of general DMA channel 4, LEVEL*/ + ETS_DMA_OUT_CH0_INTR_SOURCE, + ETS_DMA_OUT_CH1_INTR_SOURCE, + ETS_DMA_OUT_CH2_INTR_SOURCE, + ETS_DMA_OUT_CH3_INTR_SOURCE, + ETS_DMA_OUT_CH4_INTR_SOURCE, ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ @@ -147,8 +154,12 @@ typedef enum { ETS_CORE1_DRAM0_PMS_INTR_SOURCE, ETS_CORE1_PIF_PMS_INTR_SOURCE, ETS_CORE1_PIF_PMS_SIZE_INTR_SOURCE, + ETS_BACKUP_PMS_VIOLATE_INTR_SOURCE, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHE_CORE1_ACS_INTR_SOURCE, + ETS_USB_DEVICE_INTR_SOURCE, + ETS_PREI_BACKUP_INTR_SOURCE, + ETS_DMA_EXTMEM_REJECT_SOURCE, ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ } periph_interrput_t; diff --git a/components/soc/esp32s3/include/soc/rmt_caps.h b/components/soc/esp32s3/include/soc/rmt_caps.h new file mode 100644 index 0000000000..43c45b9e1b --- /dev/null +++ b/components/soc/esp32s3/include/soc/rmt_caps.h @@ -0,0 +1,30 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */ +#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */ +#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ +#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ +#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ +#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */ + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/rmt_reg.h b/components/soc/esp32s3/include/soc/rmt_reg.h index bddf00227c..0c4362183f 100644 --- a/components/soc/esp32s3/include/soc/rmt_reg.h +++ b/components/soc/esp32s3/include/soc/rmt_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,2110 +11,2212 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_RMT_REG_H_ +#define _SOC_RMT_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) -#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) -#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) -#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xC) -#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x10) -#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x14) -#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x18) -#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x1C) -#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x20) /* RMT_CONF_UPDATE_CH0 : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH0 (BIT(24)) -#define RMT_CONF_UPDATE_CH0_M (BIT(24)) -#define RMT_CONF_UPDATE_CH0_V 0x1 -#define RMT_CONF_UPDATE_CH0_S 24 +/*description: .*/ +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (BIT(24)) +#define RMT_CONF_UPDATE_CH0_V 0x1 +#define RMT_CONF_UPDATE_CH0_S 24 /* RMT_AFIFO_RST_CH0 : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH0 (BIT(23)) -#define RMT_AFIFO_RST_CH0_M (BIT(23)) -#define RMT_AFIFO_RST_CH0_V 0x1 -#define RMT_AFIFO_RST_CH0_S 23 +/*description: .*/ +#define RMT_AFIFO_RST_CH0 (BIT(23)) +#define RMT_AFIFO_RST_CH0_M (BIT(23)) +#define RMT_AFIFO_RST_CH0_V 0x1 +#define RMT_AFIFO_RST_CH0_S 23 /* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH0_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH0_V 0x1 -#define RMT_CARRIER_OUT_LV_CH0_S 22 +/*description: .*/ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_V 0x1 +#define RMT_CARRIER_OUT_LV_CH0_S 22 /* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH0 (BIT(21)) -#define RMT_CARRIER_EN_CH0_M (BIT(21)) -#define RMT_CARRIER_EN_CH0_V 0x1 -#define RMT_CARRIER_EN_CH0_S 21 +/*description: .*/ +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (BIT(21)) +#define RMT_CARRIER_EN_CH0_V 0x1 +#define RMT_CARRIER_EN_CH0_S 21 /* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH0_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH0_V 0x1 -#define RMT_CARRIER_EFF_EN_CH0_S 20 +/*description: .*/ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_V 0x1 +#define RMT_CARRIER_EFF_EN_CH0_S 20 /* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH0 0x0000000F -#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V) << (RMT_MEM_SIZE_CH0_S)) -#define RMT_MEM_SIZE_CH0_V 0xF -#define RMT_MEM_SIZE_CH0_S 16 +/*description: .*/ +#define RMT_MEM_SIZE_CH0 0x0000000F +#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) +#define RMT_MEM_SIZE_CH0_V 0xF +#define RMT_MEM_SIZE_CH0_S 16 /* RMT_DIV_CNT_CH0 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH0 0x000000FF -#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V) << (RMT_DIV_CNT_CH0_S)) -#define RMT_DIV_CNT_CH0_V 0xFF -#define RMT_DIV_CNT_CH0_S 8 +/*description: .*/ +#define RMT_DIV_CNT_CH0 0x000000FF +#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) +#define RMT_DIV_CNT_CH0_V 0xFF +#define RMT_DIV_CNT_CH0_S 8 /* RMT_TX_STOP_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH0 (BIT(7)) -#define RMT_TX_STOP_CH0_M (BIT(7)) -#define RMT_TX_STOP_CH0_V 0x1 -#define RMT_TX_STOP_CH0_S 7 +/*description: .*/ +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (BIT(7)) +#define RMT_TX_STOP_CH0_V 0x1 +#define RMT_TX_STOP_CH0_S 7 /* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH0_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH0_V 0x1 -#define RMT_IDLE_OUT_EN_CH0_S 6 +/*description: .*/ +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_V 0x1 +#define RMT_IDLE_OUT_EN_CH0_S 6 /* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH0_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH0_V 0x1 -#define RMT_IDLE_OUT_LV_CH0_S 5 +/*description: .*/ +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_V 0x1 +#define RMT_IDLE_OUT_LV_CH0_S 5 /* RMT_MEM_TX_WRAP_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH0_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH0_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/*description: .*/ +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 /* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH0_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH0_V 0x1 -#define RMT_TX_CONTI_MODE_CH0_S 3 +/*description: .*/ +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_V 0x1 +#define RMT_TX_CONTI_MODE_CH0_S 3 /* RMT_APB_MEM_RST_CH0 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH0 (BIT(2)) -#define RMT_APB_MEM_RST_CH0_M (BIT(2)) -#define RMT_APB_MEM_RST_CH0_V 0x1 -#define RMT_APB_MEM_RST_CH0_S 2 +/*description: .*/ +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (BIT(2)) +#define RMT_APB_MEM_RST_CH0_V 0x1 +#define RMT_APB_MEM_RST_CH0_S 2 /* RMT_MEM_RD_RST_CH0 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH0 (BIT(1)) -#define RMT_MEM_RD_RST_CH0_M (BIT(1)) -#define RMT_MEM_RD_RST_CH0_V 0x1 -#define RMT_MEM_RD_RST_CH0_S 1 +/*description: .*/ +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (BIT(1)) +#define RMT_MEM_RD_RST_CH0_V 0x1 +#define RMT_MEM_RD_RST_CH0_S 1 /* RMT_TX_START_CH0 : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (BIT(0)) -#define RMT_TX_START_CH0_V 0x1 -#define RMT_TX_START_CH0_S 0 +/*description: .*/ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (BIT(0)) +#define RMT_TX_START_CH0_V 0x1 +#define RMT_TX_START_CH0_S 0 -#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0024) +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x24) /* RMT_CONF_UPDATE_CH1 : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH1 (BIT(24)) -#define RMT_CONF_UPDATE_CH1_M (BIT(24)) -#define RMT_CONF_UPDATE_CH1_V 0x1 -#define RMT_CONF_UPDATE_CH1_S 24 +/*description: .*/ +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (BIT(24)) +#define RMT_CONF_UPDATE_CH1_V 0x1 +#define RMT_CONF_UPDATE_CH1_S 24 /* RMT_AFIFO_RST_CH1 : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH1 (BIT(23)) -#define RMT_AFIFO_RST_CH1_M (BIT(23)) -#define RMT_AFIFO_RST_CH1_V 0x1 -#define RMT_AFIFO_RST_CH1_S 23 +/*description: .*/ +#define RMT_AFIFO_RST_CH1 (BIT(23)) +#define RMT_AFIFO_RST_CH1_M (BIT(23)) +#define RMT_AFIFO_RST_CH1_V 0x1 +#define RMT_AFIFO_RST_CH1_S 23 /* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH1_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH1_V 0x1 -#define RMT_CARRIER_OUT_LV_CH1_S 22 +/*description: .*/ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_V 0x1 +#define RMT_CARRIER_OUT_LV_CH1_S 22 /* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH1 (BIT(21)) -#define RMT_CARRIER_EN_CH1_M (BIT(21)) -#define RMT_CARRIER_EN_CH1_V 0x1 -#define RMT_CARRIER_EN_CH1_S 21 +/*description: .*/ +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (BIT(21)) +#define RMT_CARRIER_EN_CH1_V 0x1 +#define RMT_CARRIER_EN_CH1_S 21 /* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH1_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH1_V 0x1 -#define RMT_CARRIER_EFF_EN_CH1_S 20 +/*description: .*/ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_V 0x1 +#define RMT_CARRIER_EFF_EN_CH1_S 20 /* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH1 0x0000000F -#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V) << (RMT_MEM_SIZE_CH1_S)) -#define RMT_MEM_SIZE_CH1_V 0xF -#define RMT_MEM_SIZE_CH1_S 16 +/*description: .*/ +#define RMT_MEM_SIZE_CH1 0x0000000F +#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) +#define RMT_MEM_SIZE_CH1_V 0xF +#define RMT_MEM_SIZE_CH1_S 16 /* RMT_DIV_CNT_CH1 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH1 0x000000FF -#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V) << (RMT_DIV_CNT_CH1_S)) -#define RMT_DIV_CNT_CH1_V 0xFF -#define RMT_DIV_CNT_CH1_S 8 +/*description: .*/ +#define RMT_DIV_CNT_CH1 0x000000FF +#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) +#define RMT_DIV_CNT_CH1_V 0xFF +#define RMT_DIV_CNT_CH1_S 8 /* RMT_TX_STOP_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH1 (BIT(7)) -#define RMT_TX_STOP_CH1_M (BIT(7)) -#define RMT_TX_STOP_CH1_V 0x1 -#define RMT_TX_STOP_CH1_S 7 +/*description: .*/ +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (BIT(7)) +#define RMT_TX_STOP_CH1_V 0x1 +#define RMT_TX_STOP_CH1_S 7 /* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH1_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH1_V 0x1 -#define RMT_IDLE_OUT_EN_CH1_S 6 +/*description: .*/ +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_V 0x1 +#define RMT_IDLE_OUT_EN_CH1_S 6 /* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH1_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH1_V 0x1 -#define RMT_IDLE_OUT_LV_CH1_S 5 +/*description: .*/ +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_V 0x1 +#define RMT_IDLE_OUT_LV_CH1_S 5 /* RMT_MEM_TX_WRAP_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH1_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH1_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/*description: .*/ +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 /* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH1_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH1_V 0x1 -#define RMT_TX_CONTI_MODE_CH1_S 3 +/*description: .*/ +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_V 0x1 +#define RMT_TX_CONTI_MODE_CH1_S 3 /* RMT_APB_MEM_RST_CH1 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH1 (BIT(2)) -#define RMT_APB_MEM_RST_CH1_M (BIT(2)) -#define RMT_APB_MEM_RST_CH1_V 0x1 -#define RMT_APB_MEM_RST_CH1_S 2 +/*description: .*/ +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (BIT(2)) +#define RMT_APB_MEM_RST_CH1_V 0x1 +#define RMT_APB_MEM_RST_CH1_S 2 /* RMT_MEM_RD_RST_CH1 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH1 (BIT(1)) -#define RMT_MEM_RD_RST_CH1_M (BIT(1)) -#define RMT_MEM_RD_RST_CH1_V 0x1 -#define RMT_MEM_RD_RST_CH1_S 1 +/*description: .*/ +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (BIT(1)) +#define RMT_MEM_RD_RST_CH1_V 0x1 +#define RMT_MEM_RD_RST_CH1_S 1 /* RMT_TX_START_CH1 : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH1 (BIT(0)) -#define RMT_TX_START_CH1_M (BIT(0)) -#define RMT_TX_START_CH1_V 0x1 -#define RMT_TX_START_CH1_S 0 +/*description: .*/ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (BIT(0)) +#define RMT_TX_START_CH1_V 0x1 +#define RMT_TX_START_CH1_S 0 -#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0028) +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x28) /* RMT_CONF_UPDATE_CH2 : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH2 (BIT(24)) -#define RMT_CONF_UPDATE_CH2_M (BIT(24)) -#define RMT_CONF_UPDATE_CH2_V 0x1 -#define RMT_CONF_UPDATE_CH2_S 24 +/*description: .*/ +#define RMT_CONF_UPDATE_CH2 (BIT(24)) +#define RMT_CONF_UPDATE_CH2_M (BIT(24)) +#define RMT_CONF_UPDATE_CH2_V 0x1 +#define RMT_CONF_UPDATE_CH2_S 24 /* RMT_AFIFO_RST_CH2 : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH2 (BIT(23)) -#define RMT_AFIFO_RST_CH2_M (BIT(23)) -#define RMT_AFIFO_RST_CH2_V 0x1 -#define RMT_AFIFO_RST_CH2_S 23 +/*description: .*/ +#define RMT_AFIFO_RST_CH2 (BIT(23)) +#define RMT_AFIFO_RST_CH2_M (BIT(23)) +#define RMT_AFIFO_RST_CH2_V 0x1 +#define RMT_AFIFO_RST_CH2_S 23 /* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH2 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH2_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH2_V 0x1 -#define RMT_CARRIER_OUT_LV_CH2_S 22 +/*description: .*/ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH2_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH2_V 0x1 +#define RMT_CARRIER_OUT_LV_CH2_S 22 /* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH2 (BIT(21)) -#define RMT_CARRIER_EN_CH2_M (BIT(21)) -#define RMT_CARRIER_EN_CH2_V 0x1 -#define RMT_CARRIER_EN_CH2_S 21 +/*description: .*/ +#define RMT_CARRIER_EN_CH2 (BIT(21)) +#define RMT_CARRIER_EN_CH2_M (BIT(21)) +#define RMT_CARRIER_EN_CH2_V 0x1 +#define RMT_CARRIER_EN_CH2_S 21 /* RMT_CARRIER_EFF_EN_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH2 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH2_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH2_V 0x1 -#define RMT_CARRIER_EFF_EN_CH2_S 20 +/*description: .*/ +#define RMT_CARRIER_EFF_EN_CH2 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH2_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH2_V 0x1 +#define RMT_CARRIER_EFF_EN_CH2_S 20 /* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH2 0x0000000F -#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V) << (RMT_MEM_SIZE_CH2_S)) -#define RMT_MEM_SIZE_CH2_V 0xF -#define RMT_MEM_SIZE_CH2_S 16 +/*description: .*/ +#define RMT_MEM_SIZE_CH2 0x0000000F +#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) +#define RMT_MEM_SIZE_CH2_V 0xF +#define RMT_MEM_SIZE_CH2_S 16 /* RMT_DIV_CNT_CH2 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH2 0x000000FF -#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V) << (RMT_DIV_CNT_CH2_S)) -#define RMT_DIV_CNT_CH2_V 0xFF -#define RMT_DIV_CNT_CH2_S 8 +/*description: .*/ +#define RMT_DIV_CNT_CH2 0x000000FF +#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) +#define RMT_DIV_CNT_CH2_V 0xFF +#define RMT_DIV_CNT_CH2_S 8 /* RMT_TX_STOP_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH2 (BIT(7)) -#define RMT_TX_STOP_CH2_M (BIT(7)) -#define RMT_TX_STOP_CH2_V 0x1 -#define RMT_TX_STOP_CH2_S 7 +/*description: .*/ +#define RMT_TX_STOP_CH2 (BIT(7)) +#define RMT_TX_STOP_CH2_M (BIT(7)) +#define RMT_TX_STOP_CH2_V 0x1 +#define RMT_TX_STOP_CH2_S 7 /* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH2 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH2_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH2_V 0x1 -#define RMT_IDLE_OUT_EN_CH2_S 6 +/*description: .*/ +#define RMT_IDLE_OUT_EN_CH2 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH2_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH2_V 0x1 +#define RMT_IDLE_OUT_EN_CH2_S 6 /* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH2 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH2_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH2_V 0x1 -#define RMT_IDLE_OUT_LV_CH2_S 5 +/*description: .*/ +#define RMT_IDLE_OUT_LV_CH2 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH2_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH2_V 0x1 +#define RMT_IDLE_OUT_LV_CH2_S 5 /* RMT_MEM_TX_WRAP_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH2 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH2_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH2_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH2_S 4 +/*description: .*/ +#define RMT_MEM_TX_WRAP_EN_CH2 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH2_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH2_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH2_S 4 /* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH2 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH2_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH2_V 0x1 -#define RMT_TX_CONTI_MODE_CH2_S 3 +/*description: .*/ +#define RMT_TX_CONTI_MODE_CH2 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH2_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH2_V 0x1 +#define RMT_TX_CONTI_MODE_CH2_S 3 /* RMT_APB_MEM_RST_CH2 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH2 (BIT(2)) -#define RMT_APB_MEM_RST_CH2_M (BIT(2)) -#define RMT_APB_MEM_RST_CH2_V 0x1 -#define RMT_APB_MEM_RST_CH2_S 2 +/*description: .*/ +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (BIT(2)) +#define RMT_APB_MEM_RST_CH2_V 0x1 +#define RMT_APB_MEM_RST_CH2_S 2 /* RMT_MEM_RD_RST_CH2 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH2 (BIT(1)) -#define RMT_MEM_RD_RST_CH2_M (BIT(1)) -#define RMT_MEM_RD_RST_CH2_V 0x1 -#define RMT_MEM_RD_RST_CH2_S 1 +/*description: .*/ +#define RMT_MEM_RD_RST_CH2 (BIT(1)) +#define RMT_MEM_RD_RST_CH2_M (BIT(1)) +#define RMT_MEM_RD_RST_CH2_V 0x1 +#define RMT_MEM_RD_RST_CH2_S 1 /* RMT_TX_START_CH2 : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH2 (BIT(0)) -#define RMT_TX_START_CH2_M (BIT(0)) -#define RMT_TX_START_CH2_V 0x1 -#define RMT_TX_START_CH2_S 0 +/*description: .*/ +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (BIT(0)) +#define RMT_TX_START_CH2_V 0x1 +#define RMT_TX_START_CH2_S 0 -#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x002c) +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x2C) +/* RMT_DMA_ACCESS_EN_CH3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_DMA_ACCESS_EN_CH3 (BIT(25)) +#define RMT_DMA_ACCESS_EN_CH3_M (BIT(25)) +#define RMT_DMA_ACCESS_EN_CH3_V 0x1 +#define RMT_DMA_ACCESS_EN_CH3_S 25 /* RMT_CONF_UPDATE_CH3 : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH3 (BIT(24)) -#define RMT_CONF_UPDATE_CH3_M (BIT(24)) -#define RMT_CONF_UPDATE_CH3_V 0x1 -#define RMT_CONF_UPDATE_CH3_S 24 +/*description: .*/ +#define RMT_CONF_UPDATE_CH3 (BIT(24)) +#define RMT_CONF_UPDATE_CH3_M (BIT(24)) +#define RMT_CONF_UPDATE_CH3_V 0x1 +#define RMT_CONF_UPDATE_CH3_S 24 /* RMT_AFIFO_RST_CH3 : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH3 (BIT(23)) -#define RMT_AFIFO_RST_CH3_M (BIT(23)) -#define RMT_AFIFO_RST_CH3_V 0x1 -#define RMT_AFIFO_RST_CH3_S 23 +/*description: .*/ +#define RMT_AFIFO_RST_CH3 (BIT(23)) +#define RMT_AFIFO_RST_CH3_M (BIT(23)) +#define RMT_AFIFO_RST_CH3_V 0x1 +#define RMT_AFIFO_RST_CH3_S 23 /* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH3 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH3_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH3_V 0x1 -#define RMT_CARRIER_OUT_LV_CH3_S 22 +/*description: .*/ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH3_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH3_V 0x1 +#define RMT_CARRIER_OUT_LV_CH3_S 22 /* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH3 (BIT(21)) -#define RMT_CARRIER_EN_CH3_M (BIT(21)) -#define RMT_CARRIER_EN_CH3_V 0x1 -#define RMT_CARRIER_EN_CH3_S 21 +/*description: .*/ +#define RMT_CARRIER_EN_CH3 (BIT(21)) +#define RMT_CARRIER_EN_CH3_M (BIT(21)) +#define RMT_CARRIER_EN_CH3_V 0x1 +#define RMT_CARRIER_EN_CH3_S 21 /* RMT_CARRIER_EFF_EN_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH3 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH3_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH3_V 0x1 -#define RMT_CARRIER_EFF_EN_CH3_S 20 +/*description: .*/ +#define RMT_CARRIER_EFF_EN_CH3 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH3_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH3_V 0x1 +#define RMT_CARRIER_EFF_EN_CH3_S 20 /* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH3 0x0000000F -#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V) << (RMT_MEM_SIZE_CH3_S)) -#define RMT_MEM_SIZE_CH3_V 0xF -#define RMT_MEM_SIZE_CH3_S 16 +/*description: .*/ +#define RMT_MEM_SIZE_CH3 0x0000000F +#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) +#define RMT_MEM_SIZE_CH3_V 0xF +#define RMT_MEM_SIZE_CH3_S 16 /* RMT_DIV_CNT_CH3 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH3 0x000000FF -#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V) << (RMT_DIV_CNT_CH3_S)) -#define RMT_DIV_CNT_CH3_V 0xFF -#define RMT_DIV_CNT_CH3_S 8 +/*description: .*/ +#define RMT_DIV_CNT_CH3 0x000000FF +#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) +#define RMT_DIV_CNT_CH3_V 0xFF +#define RMT_DIV_CNT_CH3_S 8 /* RMT_TX_STOP_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH3 (BIT(7)) -#define RMT_TX_STOP_CH3_M (BIT(7)) -#define RMT_TX_STOP_CH3_V 0x1 -#define RMT_TX_STOP_CH3_S 7 +/*description: .*/ +#define RMT_TX_STOP_CH3 (BIT(7)) +#define RMT_TX_STOP_CH3_M (BIT(7)) +#define RMT_TX_STOP_CH3_V 0x1 +#define RMT_TX_STOP_CH3_S 7 /* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH3 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH3_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH3_V 0x1 -#define RMT_IDLE_OUT_EN_CH3_S 6 +/*description: .*/ +#define RMT_IDLE_OUT_EN_CH3 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH3_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH3_V 0x1 +#define RMT_IDLE_OUT_EN_CH3_S 6 /* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH3 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH3_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH3_V 0x1 -#define RMT_IDLE_OUT_LV_CH3_S 5 +/*description: .*/ +#define RMT_IDLE_OUT_LV_CH3 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH3_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH3_V 0x1 +#define RMT_IDLE_OUT_LV_CH3_S 5 /* RMT_MEM_TX_WRAP_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH3 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH3_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH3_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH3_S 4 +/*description: .*/ +#define RMT_MEM_TX_WRAP_EN_CH3 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH3_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH3_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH3_S 4 /* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH3 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH3_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH3_V 0x1 -#define RMT_TX_CONTI_MODE_CH3_S 3 +/*description: .*/ +#define RMT_TX_CONTI_MODE_CH3 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH3_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH3_V 0x1 +#define RMT_TX_CONTI_MODE_CH3_S 3 /* RMT_APB_MEM_RST_CH3 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH3 (BIT(2)) -#define RMT_APB_MEM_RST_CH3_M (BIT(2)) -#define RMT_APB_MEM_RST_CH3_V 0x1 -#define RMT_APB_MEM_RST_CH3_S 2 +/*description: .*/ +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (BIT(2)) +#define RMT_APB_MEM_RST_CH3_V 0x1 +#define RMT_APB_MEM_RST_CH3_S 2 /* RMT_MEM_RD_RST_CH3 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH3 (BIT(1)) -#define RMT_MEM_RD_RST_CH3_M (BIT(1)) -#define RMT_MEM_RD_RST_CH3_V 0x1 -#define RMT_MEM_RD_RST_CH3_S 1 +/*description: .*/ +#define RMT_MEM_RD_RST_CH3 (BIT(1)) +#define RMT_MEM_RD_RST_CH3_M (BIT(1)) +#define RMT_MEM_RD_RST_CH3_V 0x1 +#define RMT_MEM_RD_RST_CH3_S 1 /* RMT_TX_START_CH3 : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH3 (BIT(0)) -#define RMT_TX_START_CH3_M (BIT(0)) -#define RMT_TX_START_CH3_V 0x1 -#define RMT_TX_START_CH3_S 0 +/*description: .*/ +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (BIT(0)) +#define RMT_TX_START_CH3_V 0x1 +#define RMT_TX_START_CH3_S 0 -#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0030) +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x30) /* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_V 0x1 -#define RMT_CARRIER_OUT_LV_CH4_S 29 +/*description: .*/ +#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_V 0x1 +#define RMT_CARRIER_OUT_LV_CH4_S 29 /* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH4 (BIT(28)) -#define RMT_CARRIER_EN_CH4_M (BIT(28)) -#define RMT_CARRIER_EN_CH4_V 0x1 -#define RMT_CARRIER_EN_CH4_S 28 +/*description: .*/ +#define RMT_CARRIER_EN_CH4 (BIT(28)) +#define RMT_CARRIER_EN_CH4_M (BIT(28)) +#define RMT_CARRIER_EN_CH4_V 0x1 +#define RMT_CARRIER_EN_CH4_S 28 /* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH4 0x0000000F -#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V) << (RMT_MEM_SIZE_CH4_S)) -#define RMT_MEM_SIZE_CH4_V 0xF -#define RMT_MEM_SIZE_CH4_S 24 +/*description: .*/ +#define RMT_MEM_SIZE_CH4 0x0000000F +#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) +#define RMT_MEM_SIZE_CH4_V 0xF +#define RMT_MEM_SIZE_CH4_S 24 /* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH4 0x00007FFF -#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V) << (RMT_IDLE_THRES_CH4_S)) -#define RMT_IDLE_THRES_CH4_V 0x7FFF -#define RMT_IDLE_THRES_CH4_S 8 +/*description: .*/ +#define RMT_IDLE_THRES_CH4 0x00007FFF +#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) +#define RMT_IDLE_THRES_CH4_V 0x7FFF +#define RMT_IDLE_THRES_CH4_S 8 /* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH4 0x000000FF -#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V) << (RMT_DIV_CNT_CH4_S)) -#define RMT_DIV_CNT_CH4_V 0xFF -#define RMT_DIV_CNT_CH4_S 0 +/*description: .*/ +#define RMT_DIV_CNT_CH4 0x000000FF +#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) +#define RMT_DIV_CNT_CH4_V 0xFF +#define RMT_DIV_CNT_CH4_S 0 -#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0034) +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x34) /* RMT_CONF_UPDATE_CH4 : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH4 (BIT(15)) -#define RMT_CONF_UPDATE_CH4_M (BIT(15)) -#define RMT_CONF_UPDATE_CH4_V 0x1 -#define RMT_CONF_UPDATE_CH4_S 15 +/*description: .*/ +#define RMT_CONF_UPDATE_CH4 (BIT(15)) +#define RMT_CONF_UPDATE_CH4_M (BIT(15)) +#define RMT_CONF_UPDATE_CH4_V 0x1 +#define RMT_CONF_UPDATE_CH4_S 15 /* RMT_AFIFO_RST_CH4 : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH4 (BIT(14)) -#define RMT_AFIFO_RST_CH4_M (BIT(14)) -#define RMT_AFIFO_RST_CH4_V 0x1 -#define RMT_AFIFO_RST_CH4_S 14 +/*description: .*/ +#define RMT_AFIFO_RST_CH4 (BIT(14)) +#define RMT_AFIFO_RST_CH4_M (BIT(14)) +#define RMT_AFIFO_RST_CH4_V 0x1 +#define RMT_AFIFO_RST_CH4_S 14 /* RMT_MEM_RX_WRAP_EN_CH4 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH4 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH4_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH4_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH4_S 13 +/*description: .*/ +#define RMT_MEM_RX_WRAP_EN_CH4 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH4_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH4_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH4_S 13 /* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH4 0x000000FF -#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V) << (RMT_RX_FILTER_THRES_CH4_S)) -#define RMT_RX_FILTER_THRES_CH4_V 0xFF -#define RMT_RX_FILTER_THRES_CH4_S 5 +/*description: .*/ +#define RMT_RX_FILTER_THRES_CH4 0x000000FF +#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) +#define RMT_RX_FILTER_THRES_CH4_V 0xFF +#define RMT_RX_FILTER_THRES_CH4_S 5 /* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH4 (BIT(4)) -#define RMT_RX_FILTER_EN_CH4_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH4_V 0x1 -#define RMT_RX_FILTER_EN_CH4_S 4 +/*description: .*/ +#define RMT_RX_FILTER_EN_CH4 (BIT(4)) +#define RMT_RX_FILTER_EN_CH4_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH4_V 0x1 +#define RMT_RX_FILTER_EN_CH4_S 4 /* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH4 (BIT(3)) -#define RMT_MEM_OWNER_CH4_M (BIT(3)) -#define RMT_MEM_OWNER_CH4_V 0x1 -#define RMT_MEM_OWNER_CH4_S 3 +/*description: .*/ +#define RMT_MEM_OWNER_CH4 (BIT(3)) +#define RMT_MEM_OWNER_CH4_M (BIT(3)) +#define RMT_MEM_OWNER_CH4_V 0x1 +#define RMT_MEM_OWNER_CH4_S 3 /* RMT_APB_MEM_RST_CH4 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH4 (BIT(2)) -#define RMT_APB_MEM_RST_CH4_M (BIT(2)) -#define RMT_APB_MEM_RST_CH4_V 0x1 -#define RMT_APB_MEM_RST_CH4_S 2 +/*description: .*/ +#define RMT_APB_MEM_RST_CH4 (BIT(2)) +#define RMT_APB_MEM_RST_CH4_M (BIT(2)) +#define RMT_APB_MEM_RST_CH4_V 0x1 +#define RMT_APB_MEM_RST_CH4_S 2 /* RMT_MEM_WR_RST_CH4 : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH4 (BIT(1)) -#define RMT_MEM_WR_RST_CH4_M (BIT(1)) -#define RMT_MEM_WR_RST_CH4_V 0x1 -#define RMT_MEM_WR_RST_CH4_S 1 +/*description: .*/ +#define RMT_MEM_WR_RST_CH4 (BIT(1)) +#define RMT_MEM_WR_RST_CH4_M (BIT(1)) +#define RMT_MEM_WR_RST_CH4_V 0x1 +#define RMT_MEM_WR_RST_CH4_S 1 /* RMT_RX_EN_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH4 (BIT(0)) -#define RMT_RX_EN_CH4_M (BIT(0)) -#define RMT_RX_EN_CH4_V 0x1 -#define RMT_RX_EN_CH4_S 0 +/*description: .*/ +#define RMT_RX_EN_CH4 (BIT(0)) +#define RMT_RX_EN_CH4_M (BIT(0)) +#define RMT_RX_EN_CH4_V 0x1 +#define RMT_RX_EN_CH4_S 0 -#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0038) +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x38) /* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_V 0x1 -#define RMT_CARRIER_OUT_LV_CH5_S 29 +/*description: .*/ +#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_V 0x1 +#define RMT_CARRIER_OUT_LV_CH5_S 29 /* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH5 (BIT(28)) -#define RMT_CARRIER_EN_CH5_M (BIT(28)) -#define RMT_CARRIER_EN_CH5_V 0x1 -#define RMT_CARRIER_EN_CH5_S 28 +/*description: .*/ +#define RMT_CARRIER_EN_CH5 (BIT(28)) +#define RMT_CARRIER_EN_CH5_M (BIT(28)) +#define RMT_CARRIER_EN_CH5_V 0x1 +#define RMT_CARRIER_EN_CH5_S 28 /* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH5 0x0000000F -#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V) << (RMT_MEM_SIZE_CH5_S)) -#define RMT_MEM_SIZE_CH5_V 0xF -#define RMT_MEM_SIZE_CH5_S 24 +/*description: .*/ +#define RMT_MEM_SIZE_CH5 0x0000000F +#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) +#define RMT_MEM_SIZE_CH5_V 0xF +#define RMT_MEM_SIZE_CH5_S 24 /* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH5 0x00007FFF -#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V) << (RMT_IDLE_THRES_CH5_S)) -#define RMT_IDLE_THRES_CH5_V 0x7FFF -#define RMT_IDLE_THRES_CH5_S 8 +/*description: .*/ +#define RMT_IDLE_THRES_CH5 0x00007FFF +#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) +#define RMT_IDLE_THRES_CH5_V 0x7FFF +#define RMT_IDLE_THRES_CH5_S 8 /* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH5 0x000000FF -#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V) << (RMT_DIV_CNT_CH5_S)) -#define RMT_DIV_CNT_CH5_V 0xFF -#define RMT_DIV_CNT_CH5_S 0 +/*description: .*/ +#define RMT_DIV_CNT_CH5 0x000000FF +#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) +#define RMT_DIV_CNT_CH5_V 0xFF +#define RMT_DIV_CNT_CH5_S 0 -#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x003c) +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x3C) /* RMT_CONF_UPDATE_CH5 : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH5 (BIT(15)) -#define RMT_CONF_UPDATE_CH5_M (BIT(15)) -#define RMT_CONF_UPDATE_CH5_V 0x1 -#define RMT_CONF_UPDATE_CH5_S 15 +/*description: .*/ +#define RMT_CONF_UPDATE_CH5 (BIT(15)) +#define RMT_CONF_UPDATE_CH5_M (BIT(15)) +#define RMT_CONF_UPDATE_CH5_V 0x1 +#define RMT_CONF_UPDATE_CH5_S 15 /* RMT_AFIFO_RST_CH5 : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH5 (BIT(14)) -#define RMT_AFIFO_RST_CH5_M (BIT(14)) -#define RMT_AFIFO_RST_CH5_V 0x1 -#define RMT_AFIFO_RST_CH5_S 14 +/*description: .*/ +#define RMT_AFIFO_RST_CH5 (BIT(14)) +#define RMT_AFIFO_RST_CH5_M (BIT(14)) +#define RMT_AFIFO_RST_CH5_V 0x1 +#define RMT_AFIFO_RST_CH5_S 14 /* RMT_MEM_RX_WRAP_EN_CH5 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH5 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH5_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH5_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH5_S 13 +/*description: .*/ +#define RMT_MEM_RX_WRAP_EN_CH5 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH5_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH5_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH5_S 13 /* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH5 0x000000FF -#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V) << (RMT_RX_FILTER_THRES_CH5_S)) -#define RMT_RX_FILTER_THRES_CH5_V 0xFF -#define RMT_RX_FILTER_THRES_CH5_S 5 +/*description: .*/ +#define RMT_RX_FILTER_THRES_CH5 0x000000FF +#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) +#define RMT_RX_FILTER_THRES_CH5_V 0xFF +#define RMT_RX_FILTER_THRES_CH5_S 5 /* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH5 (BIT(4)) -#define RMT_RX_FILTER_EN_CH5_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH5_V 0x1 -#define RMT_RX_FILTER_EN_CH5_S 4 +/*description: .*/ +#define RMT_RX_FILTER_EN_CH5 (BIT(4)) +#define RMT_RX_FILTER_EN_CH5_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH5_V 0x1 +#define RMT_RX_FILTER_EN_CH5_S 4 /* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH5 (BIT(3)) -#define RMT_MEM_OWNER_CH5_M (BIT(3)) -#define RMT_MEM_OWNER_CH5_V 0x1 -#define RMT_MEM_OWNER_CH5_S 3 +/*description: .*/ +#define RMT_MEM_OWNER_CH5 (BIT(3)) +#define RMT_MEM_OWNER_CH5_M (BIT(3)) +#define RMT_MEM_OWNER_CH5_V 0x1 +#define RMT_MEM_OWNER_CH5_S 3 /* RMT_APB_MEM_RST_CH5 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH5 (BIT(2)) -#define RMT_APB_MEM_RST_CH5_M (BIT(2)) -#define RMT_APB_MEM_RST_CH5_V 0x1 -#define RMT_APB_MEM_RST_CH5_S 2 +/*description: .*/ +#define RMT_APB_MEM_RST_CH5 (BIT(2)) +#define RMT_APB_MEM_RST_CH5_M (BIT(2)) +#define RMT_APB_MEM_RST_CH5_V 0x1 +#define RMT_APB_MEM_RST_CH5_S 2 /* RMT_MEM_WR_RST_CH5 : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH5 (BIT(1)) -#define RMT_MEM_WR_RST_CH5_M (BIT(1)) -#define RMT_MEM_WR_RST_CH5_V 0x1 -#define RMT_MEM_WR_RST_CH5_S 1 +/*description: .*/ +#define RMT_MEM_WR_RST_CH5 (BIT(1)) +#define RMT_MEM_WR_RST_CH5_M (BIT(1)) +#define RMT_MEM_WR_RST_CH5_V 0x1 +#define RMT_MEM_WR_RST_CH5_S 1 /* RMT_RX_EN_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH5 (BIT(0)) -#define RMT_RX_EN_CH5_M (BIT(0)) -#define RMT_RX_EN_CH5_V 0x1 -#define RMT_RX_EN_CH5_S 0 +/*description: .*/ +#define RMT_RX_EN_CH5 (BIT(0)) +#define RMT_RX_EN_CH5_M (BIT(0)) +#define RMT_RX_EN_CH5_V 0x1 +#define RMT_RX_EN_CH5_S 0 -#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0040) +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x40) /* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_V 0x1 -#define RMT_CARRIER_OUT_LV_CH6_S 29 +/*description: .*/ +#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_V 0x1 +#define RMT_CARRIER_OUT_LV_CH6_S 29 /* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH6 (BIT(28)) -#define RMT_CARRIER_EN_CH6_M (BIT(28)) -#define RMT_CARRIER_EN_CH6_V 0x1 -#define RMT_CARRIER_EN_CH6_S 28 +/*description: .*/ +#define RMT_CARRIER_EN_CH6 (BIT(28)) +#define RMT_CARRIER_EN_CH6_M (BIT(28)) +#define RMT_CARRIER_EN_CH6_V 0x1 +#define RMT_CARRIER_EN_CH6_S 28 /* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH6 0x0000000F -#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V) << (RMT_MEM_SIZE_CH6_S)) -#define RMT_MEM_SIZE_CH6_V 0xF -#define RMT_MEM_SIZE_CH6_S 24 +/*description: .*/ +#define RMT_MEM_SIZE_CH6 0x0000000F +#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) +#define RMT_MEM_SIZE_CH6_V 0xF +#define RMT_MEM_SIZE_CH6_S 24 /* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH6 0x00007FFF -#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V) << (RMT_IDLE_THRES_CH6_S)) -#define RMT_IDLE_THRES_CH6_V 0x7FFF -#define RMT_IDLE_THRES_CH6_S 8 +/*description: .*/ +#define RMT_IDLE_THRES_CH6 0x00007FFF +#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) +#define RMT_IDLE_THRES_CH6_V 0x7FFF +#define RMT_IDLE_THRES_CH6_S 8 /* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH6 0x000000FF -#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V) << (RMT_DIV_CNT_CH6_S)) -#define RMT_DIV_CNT_CH6_V 0xFF -#define RMT_DIV_CNT_CH6_S 0 +/*description: .*/ +#define RMT_DIV_CNT_CH6 0x000000FF +#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) +#define RMT_DIV_CNT_CH6_V 0xFF +#define RMT_DIV_CNT_CH6_S 0 -#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0044) +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x44) /* RMT_CONF_UPDATE_CH6 : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH6 (BIT(15)) -#define RMT_CONF_UPDATE_CH6_M (BIT(15)) -#define RMT_CONF_UPDATE_CH6_V 0x1 -#define RMT_CONF_UPDATE_CH6_S 15 +/*description: .*/ +#define RMT_CONF_UPDATE_CH6 (BIT(15)) +#define RMT_CONF_UPDATE_CH6_M (BIT(15)) +#define RMT_CONF_UPDATE_CH6_V 0x1 +#define RMT_CONF_UPDATE_CH6_S 15 /* RMT_AFIFO_RST_CH6 : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH6 (BIT(14)) -#define RMT_AFIFO_RST_CH6_M (BIT(14)) -#define RMT_AFIFO_RST_CH6_V 0x1 -#define RMT_AFIFO_RST_CH6_S 14 +/*description: .*/ +#define RMT_AFIFO_RST_CH6 (BIT(14)) +#define RMT_AFIFO_RST_CH6_M (BIT(14)) +#define RMT_AFIFO_RST_CH6_V 0x1 +#define RMT_AFIFO_RST_CH6_S 14 /* RMT_MEM_RX_WRAP_EN_CH6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH6 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH6_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH6_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH6_S 13 +/*description: .*/ +#define RMT_MEM_RX_WRAP_EN_CH6 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH6_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH6_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH6_S 13 /* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH6 0x000000FF -#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V) << (RMT_RX_FILTER_THRES_CH6_S)) -#define RMT_RX_FILTER_THRES_CH6_V 0xFF -#define RMT_RX_FILTER_THRES_CH6_S 5 +/*description: .*/ +#define RMT_RX_FILTER_THRES_CH6 0x000000FF +#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) +#define RMT_RX_FILTER_THRES_CH6_V 0xFF +#define RMT_RX_FILTER_THRES_CH6_S 5 /* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH6 (BIT(4)) -#define RMT_RX_FILTER_EN_CH6_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH6_V 0x1 -#define RMT_RX_FILTER_EN_CH6_S 4 +/*description: .*/ +#define RMT_RX_FILTER_EN_CH6 (BIT(4)) +#define RMT_RX_FILTER_EN_CH6_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH6_V 0x1 +#define RMT_RX_FILTER_EN_CH6_S 4 /* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH6 (BIT(3)) -#define RMT_MEM_OWNER_CH6_M (BIT(3)) -#define RMT_MEM_OWNER_CH6_V 0x1 -#define RMT_MEM_OWNER_CH6_S 3 +/*description: .*/ +#define RMT_MEM_OWNER_CH6 (BIT(3)) +#define RMT_MEM_OWNER_CH6_M (BIT(3)) +#define RMT_MEM_OWNER_CH6_V 0x1 +#define RMT_MEM_OWNER_CH6_S 3 /* RMT_APB_MEM_RST_CH6 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH6 (BIT(2)) -#define RMT_APB_MEM_RST_CH6_M (BIT(2)) -#define RMT_APB_MEM_RST_CH6_V 0x1 -#define RMT_APB_MEM_RST_CH6_S 2 +/*description: .*/ +#define RMT_APB_MEM_RST_CH6 (BIT(2)) +#define RMT_APB_MEM_RST_CH6_M (BIT(2)) +#define RMT_APB_MEM_RST_CH6_V 0x1 +#define RMT_APB_MEM_RST_CH6_S 2 /* RMT_MEM_WR_RST_CH6 : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH6 (BIT(1)) -#define RMT_MEM_WR_RST_CH6_M (BIT(1)) -#define RMT_MEM_WR_RST_CH6_V 0x1 -#define RMT_MEM_WR_RST_CH6_S 1 +/*description: .*/ +#define RMT_MEM_WR_RST_CH6 (BIT(1)) +#define RMT_MEM_WR_RST_CH6_M (BIT(1)) +#define RMT_MEM_WR_RST_CH6_V 0x1 +#define RMT_MEM_WR_RST_CH6_S 1 /* RMT_RX_EN_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH6 (BIT(0)) -#define RMT_RX_EN_CH6_M (BIT(0)) -#define RMT_RX_EN_CH6_V 0x1 -#define RMT_RX_EN_CH6_S 0 +/*description: .*/ +#define RMT_RX_EN_CH6 (BIT(0)) +#define RMT_RX_EN_CH6_M (BIT(0)) +#define RMT_RX_EN_CH6_V 0x1 +#define RMT_RX_EN_CH6_S 0 -#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0048) +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x48) /* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_V 0x1 -#define RMT_CARRIER_OUT_LV_CH7_S 29 +/*description: .*/ +#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_V 0x1 +#define RMT_CARRIER_OUT_LV_CH7_S 29 /* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH7 (BIT(28)) -#define RMT_CARRIER_EN_CH7_M (BIT(28)) -#define RMT_CARRIER_EN_CH7_V 0x1 -#define RMT_CARRIER_EN_CH7_S 28 +/*description: .*/ +#define RMT_CARRIER_EN_CH7 (BIT(28)) +#define RMT_CARRIER_EN_CH7_M (BIT(28)) +#define RMT_CARRIER_EN_CH7_V 0x1 +#define RMT_CARRIER_EN_CH7_S 28 /* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH7 0x0000000F -#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V) << (RMT_MEM_SIZE_CH7_S)) -#define RMT_MEM_SIZE_CH7_V 0xF -#define RMT_MEM_SIZE_CH7_S 24 +/*description: .*/ +#define RMT_MEM_SIZE_CH7 0x0000000F +#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) +#define RMT_MEM_SIZE_CH7_V 0xF +#define RMT_MEM_SIZE_CH7_S 24 +/* RMT_DMA_ACCESS_EN_CH7 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_DMA_ACCESS_EN_CH7 (BIT(23)) +#define RMT_DMA_ACCESS_EN_CH7_M (BIT(23)) +#define RMT_DMA_ACCESS_EN_CH7_V 0x1 +#define RMT_DMA_ACCESS_EN_CH7_S 23 /* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH7 0x00007FFF -#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V) << (RMT_IDLE_THRES_CH7_S)) -#define RMT_IDLE_THRES_CH7_V 0x7FFF -#define RMT_IDLE_THRES_CH7_S 8 +/*description: .*/ +#define RMT_IDLE_THRES_CH7 0x00007FFF +#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) +#define RMT_IDLE_THRES_CH7_V 0x7FFF +#define RMT_IDLE_THRES_CH7_S 8 /* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH7 0x000000FF -#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V) << (RMT_DIV_CNT_CH7_S)) -#define RMT_DIV_CNT_CH7_V 0xFF -#define RMT_DIV_CNT_CH7_S 0 +/*description: .*/ +#define RMT_DIV_CNT_CH7 0x000000FF +#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) +#define RMT_DIV_CNT_CH7_V 0xFF +#define RMT_DIV_CNT_CH7_S 0 -#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x004c) +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x4C) /* RMT_CONF_UPDATE_CH7 : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH7 (BIT(15)) -#define RMT_CONF_UPDATE_CH7_M (BIT(15)) -#define RMT_CONF_UPDATE_CH7_V 0x1 -#define RMT_CONF_UPDATE_CH7_S 15 +/*description: .*/ +#define RMT_CONF_UPDATE_CH7 (BIT(15)) +#define RMT_CONF_UPDATE_CH7_M (BIT(15)) +#define RMT_CONF_UPDATE_CH7_V 0x1 +#define RMT_CONF_UPDATE_CH7_S 15 /* RMT_AFIFO_RST_CH7 : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH7 (BIT(14)) -#define RMT_AFIFO_RST_CH7_M (BIT(14)) -#define RMT_AFIFO_RST_CH7_V 0x1 -#define RMT_AFIFO_RST_CH7_S 14 +/*description: .*/ +#define RMT_AFIFO_RST_CH7 (BIT(14)) +#define RMT_AFIFO_RST_CH7_M (BIT(14)) +#define RMT_AFIFO_RST_CH7_V 0x1 +#define RMT_AFIFO_RST_CH7_S 14 /* RMT_MEM_RX_WRAP_EN_CH7 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH7 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH7_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH7_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH7_S 13 +/*description: .*/ +#define RMT_MEM_RX_WRAP_EN_CH7 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH7_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH7_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH7_S 13 /* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH7 0x000000FF -#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V) << (RMT_RX_FILTER_THRES_CH7_S)) -#define RMT_RX_FILTER_THRES_CH7_V 0xFF -#define RMT_RX_FILTER_THRES_CH7_S 5 +/*description: .*/ +#define RMT_RX_FILTER_THRES_CH7 0x000000FF +#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) +#define RMT_RX_FILTER_THRES_CH7_V 0xFF +#define RMT_RX_FILTER_THRES_CH7_S 5 /* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH7 (BIT(4)) -#define RMT_RX_FILTER_EN_CH7_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH7_V 0x1 -#define RMT_RX_FILTER_EN_CH7_S 4 +/*description: .*/ +#define RMT_RX_FILTER_EN_CH7 (BIT(4)) +#define RMT_RX_FILTER_EN_CH7_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH7_V 0x1 +#define RMT_RX_FILTER_EN_CH7_S 4 /* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH7 (BIT(3)) -#define RMT_MEM_OWNER_CH7_M (BIT(3)) -#define RMT_MEM_OWNER_CH7_V 0x1 -#define RMT_MEM_OWNER_CH7_S 3 +/*description: .*/ +#define RMT_MEM_OWNER_CH7 (BIT(3)) +#define RMT_MEM_OWNER_CH7_M (BIT(3)) +#define RMT_MEM_OWNER_CH7_V 0x1 +#define RMT_MEM_OWNER_CH7_S 3 /* RMT_APB_MEM_RST_CH7 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH7 (BIT(2)) -#define RMT_APB_MEM_RST_CH7_M (BIT(2)) -#define RMT_APB_MEM_RST_CH7_V 0x1 -#define RMT_APB_MEM_RST_CH7_S 2 +/*description: .*/ +#define RMT_APB_MEM_RST_CH7 (BIT(2)) +#define RMT_APB_MEM_RST_CH7_M (BIT(2)) +#define RMT_APB_MEM_RST_CH7_V 0x1 +#define RMT_APB_MEM_RST_CH7_S 2 /* RMT_MEM_WR_RST_CH7 : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH7 (BIT(1)) -#define RMT_MEM_WR_RST_CH7_M (BIT(1)) -#define RMT_MEM_WR_RST_CH7_V 0x1 -#define RMT_MEM_WR_RST_CH7_S 1 +/*description: .*/ +#define RMT_MEM_WR_RST_CH7 (BIT(1)) +#define RMT_MEM_WR_RST_CH7_M (BIT(1)) +#define RMT_MEM_WR_RST_CH7_V 0x1 +#define RMT_MEM_WR_RST_CH7_S 1 /* RMT_RX_EN_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH7 (BIT(0)) -#define RMT_RX_EN_CH7_M (BIT(0)) -#define RMT_RX_EN_CH7_V 0x1 -#define RMT_RX_EN_CH7_S 0 +/*description: .*/ +#define RMT_RX_EN_CH7 (BIT(0)) +#define RMT_RX_EN_CH7_M (BIT(0)) +#define RMT_RX_EN_CH7_V 0x1 +#define RMT_RX_EN_CH7_S 0 -#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0050) +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x50) /* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH0_S 26 +/*description: .*/ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH0_M (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH0_S 26 /* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH0 (BIT(25)) -#define RMT_MEM_EMPTY_CH0_M (BIT(25)) -#define RMT_MEM_EMPTY_CH0_V 0x1 -#define RMT_MEM_EMPTY_CH0_S 25 +/*description: .*/ +#define RMT_MEM_EMPTY_CH0 (BIT(25)) +#define RMT_MEM_EMPTY_CH0_M (BIT(25)) +#define RMT_MEM_EMPTY_CH0_V 0x1 +#define RMT_MEM_EMPTY_CH0_S 25 /* RMT_STATE_CH0 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH0 0x00000007 -#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V) << (RMT_STATE_CH0_S)) -#define RMT_STATE_CH0_V 0x7 -#define RMT_STATE_CH0_S 22 +/*description: .*/ +#define RMT_STATE_CH0 0x00000007 +#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S)) +#define RMT_STATE_CH0_V 0x7 +#define RMT_STATE_CH0_S 22 /* RMT_APB_MEM_WADDR_CH0 : RO ;bitpos:[20:11] ;default: 10'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH0 0x000003FF -#define RMT_APB_MEM_WADDR_CH0_M ((RMT_APB_MEM_WADDR_CH0_V) << (RMT_APB_MEM_WADDR_CH0_S)) -#define RMT_APB_MEM_WADDR_CH0_V 0x3FF -#define RMT_APB_MEM_WADDR_CH0_S 11 +/*description: .*/ +#define RMT_APB_MEM_WADDR_CH0 0x000003FF +#define RMT_APB_MEM_WADDR_CH0_M ((RMT_APB_MEM_WADDR_CH0_V)<<(RMT_APB_MEM_WADDR_CH0_S)) +#define RMT_APB_MEM_WADDR_CH0_V 0x3FF +#define RMT_APB_MEM_WADDR_CH0_S 11 /* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH0 0x000003FF -#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V) << (RMT_MEM_RADDR_EX_CH0_S)) -#define RMT_MEM_RADDR_EX_CH0_V 0x3FF -#define RMT_MEM_RADDR_EX_CH0_S 0 +/*description: .*/ +#define RMT_MEM_RADDR_EX_CH0 0x000003FF +#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S)) +#define RMT_MEM_RADDR_EX_CH0_V 0x3FF +#define RMT_MEM_RADDR_EX_CH0_S 0 -#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0054) +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x54) /* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH1 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH1_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH1_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH1_S 26 +/*description: .*/ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH1_M (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH1_S 26 /* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH1 (BIT(25)) -#define RMT_MEM_EMPTY_CH1_M (BIT(25)) -#define RMT_MEM_EMPTY_CH1_V 0x1 -#define RMT_MEM_EMPTY_CH1_S 25 +/*description: .*/ +#define RMT_MEM_EMPTY_CH1 (BIT(25)) +#define RMT_MEM_EMPTY_CH1_M (BIT(25)) +#define RMT_MEM_EMPTY_CH1_V 0x1 +#define RMT_MEM_EMPTY_CH1_S 25 /* RMT_STATE_CH1 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH1 0x00000007 -#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V) << (RMT_STATE_CH1_S)) -#define RMT_STATE_CH1_V 0x7 -#define RMT_STATE_CH1_S 22 +/*description: .*/ +#define RMT_STATE_CH1 0x00000007 +#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S)) +#define RMT_STATE_CH1_V 0x7 +#define RMT_STATE_CH1_S 22 /* RMT_APB_MEM_WADDR_CH1 : RO ;bitpos:[20:11] ;default: 10'h30 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH1 0x000003FF -#define RMT_APB_MEM_WADDR_CH1_M ((RMT_APB_MEM_WADDR_CH1_V) << (RMT_APB_MEM_WADDR_CH1_S)) -#define RMT_APB_MEM_WADDR_CH1_V 0x3FF -#define RMT_APB_MEM_WADDR_CH1_S 11 +/*description: .*/ +#define RMT_APB_MEM_WADDR_CH1 0x000003FF +#define RMT_APB_MEM_WADDR_CH1_M ((RMT_APB_MEM_WADDR_CH1_V)<<(RMT_APB_MEM_WADDR_CH1_S)) +#define RMT_APB_MEM_WADDR_CH1_V 0x3FF +#define RMT_APB_MEM_WADDR_CH1_S 11 /* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h30 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH1 0x000003FF -#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V) << (RMT_MEM_RADDR_EX_CH1_S)) -#define RMT_MEM_RADDR_EX_CH1_V 0x3FF -#define RMT_MEM_RADDR_EX_CH1_S 0 +/*description: .*/ +#define RMT_MEM_RADDR_EX_CH1 0x000003FF +#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S)) +#define RMT_MEM_RADDR_EX_CH1_V 0x3FF +#define RMT_MEM_RADDR_EX_CH1_S 0 -#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0058) +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x58) /* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH2 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH2_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH2_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH2_S 26 +/*description: .*/ +#define RMT_APB_MEM_WR_ERR_CH2 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH2_M (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH2_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH2_S 26 /* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH2 (BIT(25)) -#define RMT_MEM_EMPTY_CH2_M (BIT(25)) -#define RMT_MEM_EMPTY_CH2_V 0x1 -#define RMT_MEM_EMPTY_CH2_S 25 +/*description: .*/ +#define RMT_MEM_EMPTY_CH2 (BIT(25)) +#define RMT_MEM_EMPTY_CH2_M (BIT(25)) +#define RMT_MEM_EMPTY_CH2_V 0x1 +#define RMT_MEM_EMPTY_CH2_S 25 /* RMT_STATE_CH2 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH2 0x00000007 -#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V) << (RMT_STATE_CH2_S)) -#define RMT_STATE_CH2_V 0x7 -#define RMT_STATE_CH2_S 22 +/*description: .*/ +#define RMT_STATE_CH2 0x00000007 +#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S)) +#define RMT_STATE_CH2_V 0x7 +#define RMT_STATE_CH2_S 22 /* RMT_APB_MEM_WADDR_CH2 : RO ;bitpos:[20:11] ;default: 10'h60 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH2 0x000003FF -#define RMT_APB_MEM_WADDR_CH2_M ((RMT_APB_MEM_WADDR_CH2_V) << (RMT_APB_MEM_WADDR_CH2_S)) -#define RMT_APB_MEM_WADDR_CH2_V 0x3FF -#define RMT_APB_MEM_WADDR_CH2_S 11 +/*description: .*/ +#define RMT_APB_MEM_WADDR_CH2 0x000003FF +#define RMT_APB_MEM_WADDR_CH2_M ((RMT_APB_MEM_WADDR_CH2_V)<<(RMT_APB_MEM_WADDR_CH2_S)) +#define RMT_APB_MEM_WADDR_CH2_V 0x3FF +#define RMT_APB_MEM_WADDR_CH2_S 11 /* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h60 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH2 0x000003FF -#define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V) << (RMT_MEM_RADDR_EX_CH2_S)) -#define RMT_MEM_RADDR_EX_CH2_V 0x3FF -#define RMT_MEM_RADDR_EX_CH2_S 0 +/*description: .*/ +#define RMT_MEM_RADDR_EX_CH2 0x000003FF +#define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S)) +#define RMT_MEM_RADDR_EX_CH2_V 0x3FF +#define RMT_MEM_RADDR_EX_CH2_S 0 -#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x005c) +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x5C) /* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH3 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH3_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH3_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH3_S 26 +/*description: .*/ +#define RMT_APB_MEM_WR_ERR_CH3 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH3_M (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH3_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH3_S 26 /* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH3 (BIT(25)) -#define RMT_MEM_EMPTY_CH3_M (BIT(25)) -#define RMT_MEM_EMPTY_CH3_V 0x1 -#define RMT_MEM_EMPTY_CH3_S 25 +/*description: .*/ +#define RMT_MEM_EMPTY_CH3 (BIT(25)) +#define RMT_MEM_EMPTY_CH3_M (BIT(25)) +#define RMT_MEM_EMPTY_CH3_V 0x1 +#define RMT_MEM_EMPTY_CH3_S 25 /* RMT_STATE_CH3 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH3 0x00000007 -#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V) << (RMT_STATE_CH3_S)) -#define RMT_STATE_CH3_V 0x7 -#define RMT_STATE_CH3_S 22 +/*description: .*/ +#define RMT_STATE_CH3 0x00000007 +#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S)) +#define RMT_STATE_CH3_V 0x7 +#define RMT_STATE_CH3_S 22 +/* RMT_FIFO_FULL_CH3 : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_FIFO_FULL_CH3 (BIT(21)) +#define RMT_FIFO_FULL_CH3_M (BIT(21)) +#define RMT_FIFO_FULL_CH3_V 0x1 +#define RMT_FIFO_FULL_CH3_S 21 /* RMT_APB_MEM_WADDR_CH3 : RO ;bitpos:[20:11] ;default: 10'h90 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH3 0x000003FF -#define RMT_APB_MEM_WADDR_CH3_M ((RMT_APB_MEM_WADDR_CH3_V) << (RMT_APB_MEM_WADDR_CH3_S)) -#define RMT_APB_MEM_WADDR_CH3_V 0x3FF -#define RMT_APB_MEM_WADDR_CH3_S 11 +/*description: .*/ +#define RMT_APB_MEM_WADDR_CH3 0x000003FF +#define RMT_APB_MEM_WADDR_CH3_M ((RMT_APB_MEM_WADDR_CH3_V)<<(RMT_APB_MEM_WADDR_CH3_S)) +#define RMT_APB_MEM_WADDR_CH3_V 0x3FF +#define RMT_APB_MEM_WADDR_CH3_S 11 /* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h90 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH3 0x000003FF -#define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V) << (RMT_MEM_RADDR_EX_CH3_S)) -#define RMT_MEM_RADDR_EX_CH3_V 0x3FF -#define RMT_MEM_RADDR_EX_CH3_S 0 +/*description: .*/ +#define RMT_MEM_RADDR_EX_CH3 0x000003FF +#define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S)) +#define RMT_MEM_RADDR_EX_CH3_V 0x3FF +#define RMT_MEM_RADDR_EX_CH3_S 0 -#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0060) +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x60) /* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH4 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH4_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH4_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH4_S 27 +/*description: .*/ +#define RMT_APB_MEM_RD_ERR_CH4 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH4_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH4_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH4_S 27 /* RMT_MEM_FULL_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH4 (BIT(26)) -#define RMT_MEM_FULL_CH4_M (BIT(26)) -#define RMT_MEM_FULL_CH4_V 0x1 -#define RMT_MEM_FULL_CH4_S 26 +/*description: .*/ +#define RMT_MEM_FULL_CH4 (BIT(26)) +#define RMT_MEM_FULL_CH4_M (BIT(26)) +#define RMT_MEM_FULL_CH4_V 0x1 +#define RMT_MEM_FULL_CH4_S 26 /* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH4 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH4_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH4_V 0x1 -#define RMT_MEM_OWNER_ERR_CH4_S 25 +/*description: .*/ +#define RMT_MEM_OWNER_ERR_CH4 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH4_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH4_V 0x1 +#define RMT_MEM_OWNER_ERR_CH4_S 25 /* RMT_STATE_CH4 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH4 0x00000007 -#define RMT_STATE_CH4_M ((RMT_STATE_CH4_V) << (RMT_STATE_CH4_S)) -#define RMT_STATE_CH4_V 0x7 -#define RMT_STATE_CH4_S 22 +/*description: .*/ +#define RMT_STATE_CH4 0x00000007 +#define RMT_STATE_CH4_M ((RMT_STATE_CH4_V)<<(RMT_STATE_CH4_S)) +#define RMT_STATE_CH4_V 0x7 +#define RMT_STATE_CH4_S 22 /* RMT_APB_MEM_RADDR_CH4 : RO ;bitpos:[20:11] ;default: 10'hc0 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH4 0x000003FF -#define RMT_APB_MEM_RADDR_CH4_M ((RMT_APB_MEM_RADDR_CH4_V) << (RMT_APB_MEM_RADDR_CH4_S)) -#define RMT_APB_MEM_RADDR_CH4_V 0x3FF -#define RMT_APB_MEM_RADDR_CH4_S 11 +/*description: .*/ +#define RMT_APB_MEM_RADDR_CH4 0x000003FF +#define RMT_APB_MEM_RADDR_CH4_M ((RMT_APB_MEM_RADDR_CH4_V)<<(RMT_APB_MEM_RADDR_CH4_S)) +#define RMT_APB_MEM_RADDR_CH4_V 0x3FF +#define RMT_APB_MEM_RADDR_CH4_S 11 /* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'hc0 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH4 0x000003FF -#define RMT_MEM_WADDR_EX_CH4_M ((RMT_MEM_WADDR_EX_CH4_V) << (RMT_MEM_WADDR_EX_CH4_S)) -#define RMT_MEM_WADDR_EX_CH4_V 0x3FF -#define RMT_MEM_WADDR_EX_CH4_S 0 +/*description: .*/ +#define RMT_MEM_WADDR_EX_CH4 0x000003FF +#define RMT_MEM_WADDR_EX_CH4_M ((RMT_MEM_WADDR_EX_CH4_V)<<(RMT_MEM_WADDR_EX_CH4_S)) +#define RMT_MEM_WADDR_EX_CH4_V 0x3FF +#define RMT_MEM_WADDR_EX_CH4_S 0 -#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0064) +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x64) /* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH5 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH5_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH5_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH5_S 27 +/*description: .*/ +#define RMT_APB_MEM_RD_ERR_CH5 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH5_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH5_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH5_S 27 /* RMT_MEM_FULL_CH5 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH5 (BIT(26)) -#define RMT_MEM_FULL_CH5_M (BIT(26)) -#define RMT_MEM_FULL_CH5_V 0x1 -#define RMT_MEM_FULL_CH5_S 26 +/*description: .*/ +#define RMT_MEM_FULL_CH5 (BIT(26)) +#define RMT_MEM_FULL_CH5_M (BIT(26)) +#define RMT_MEM_FULL_CH5_V 0x1 +#define RMT_MEM_FULL_CH5_S 26 /* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH5 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH5_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH5_V 0x1 -#define RMT_MEM_OWNER_ERR_CH5_S 25 +/*description: .*/ +#define RMT_MEM_OWNER_ERR_CH5 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH5_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH5_V 0x1 +#define RMT_MEM_OWNER_ERR_CH5_S 25 /* RMT_STATE_CH5 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH5 0x00000007 -#define RMT_STATE_CH5_M ((RMT_STATE_CH5_V) << (RMT_STATE_CH5_S)) -#define RMT_STATE_CH5_V 0x7 -#define RMT_STATE_CH5_S 22 +/*description: .*/ +#define RMT_STATE_CH5 0x00000007 +#define RMT_STATE_CH5_M ((RMT_STATE_CH5_V)<<(RMT_STATE_CH5_S)) +#define RMT_STATE_CH5_V 0x7 +#define RMT_STATE_CH5_S 22 /* RMT_APB_MEM_RADDR_CH5 : RO ;bitpos:[20:11] ;default: 10'hf0 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH5 0x000003FF -#define RMT_APB_MEM_RADDR_CH5_M ((RMT_APB_MEM_RADDR_CH5_V) << (RMT_APB_MEM_RADDR_CH5_S)) -#define RMT_APB_MEM_RADDR_CH5_V 0x3FF -#define RMT_APB_MEM_RADDR_CH5_S 11 +/*description: .*/ +#define RMT_APB_MEM_RADDR_CH5 0x000003FF +#define RMT_APB_MEM_RADDR_CH5_M ((RMT_APB_MEM_RADDR_CH5_V)<<(RMT_APB_MEM_RADDR_CH5_S)) +#define RMT_APB_MEM_RADDR_CH5_V 0x3FF +#define RMT_APB_MEM_RADDR_CH5_S 11 /* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'hf0 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH5 0x000003FF -#define RMT_MEM_WADDR_EX_CH5_M ((RMT_MEM_WADDR_EX_CH5_V) << (RMT_MEM_WADDR_EX_CH5_S)) -#define RMT_MEM_WADDR_EX_CH5_V 0x3FF -#define RMT_MEM_WADDR_EX_CH5_S 0 +/*description: .*/ +#define RMT_MEM_WADDR_EX_CH5 0x000003FF +#define RMT_MEM_WADDR_EX_CH5_M ((RMT_MEM_WADDR_EX_CH5_V)<<(RMT_MEM_WADDR_EX_CH5_S)) +#define RMT_MEM_WADDR_EX_CH5_V 0x3FF +#define RMT_MEM_WADDR_EX_CH5_S 0 -#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0068) +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x68) /* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH6 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH6_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH6_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH6_S 27 +/*description: .*/ +#define RMT_APB_MEM_RD_ERR_CH6 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH6_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH6_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH6_S 27 /* RMT_MEM_FULL_CH6 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH6 (BIT(26)) -#define RMT_MEM_FULL_CH6_M (BIT(26)) -#define RMT_MEM_FULL_CH6_V 0x1 -#define RMT_MEM_FULL_CH6_S 26 +/*description: .*/ +#define RMT_MEM_FULL_CH6 (BIT(26)) +#define RMT_MEM_FULL_CH6_M (BIT(26)) +#define RMT_MEM_FULL_CH6_V 0x1 +#define RMT_MEM_FULL_CH6_S 26 /* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH6 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH6_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH6_V 0x1 -#define RMT_MEM_OWNER_ERR_CH6_S 25 +/*description: .*/ +#define RMT_MEM_OWNER_ERR_CH6 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH6_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH6_V 0x1 +#define RMT_MEM_OWNER_ERR_CH6_S 25 /* RMT_STATE_CH6 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH6 0x00000007 -#define RMT_STATE_CH6_M ((RMT_STATE_CH6_V) << (RMT_STATE_CH6_S)) -#define RMT_STATE_CH6_V 0x7 -#define RMT_STATE_CH6_S 22 +/*description: .*/ +#define RMT_STATE_CH6 0x00000007 +#define RMT_STATE_CH6_M ((RMT_STATE_CH6_V)<<(RMT_STATE_CH6_S)) +#define RMT_STATE_CH6_V 0x7 +#define RMT_STATE_CH6_S 22 /* RMT_APB_MEM_RADDR_CH6 : RO ;bitpos:[20:11] ;default: 10'h120 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH6 0x000003FF -#define RMT_APB_MEM_RADDR_CH6_M ((RMT_APB_MEM_RADDR_CH6_V) << (RMT_APB_MEM_RADDR_CH6_S)) -#define RMT_APB_MEM_RADDR_CH6_V 0x3FF -#define RMT_APB_MEM_RADDR_CH6_S 11 +/*description: .*/ +#define RMT_APB_MEM_RADDR_CH6 0x000003FF +#define RMT_APB_MEM_RADDR_CH6_M ((RMT_APB_MEM_RADDR_CH6_V)<<(RMT_APB_MEM_RADDR_CH6_S)) +#define RMT_APB_MEM_RADDR_CH6_V 0x3FF +#define RMT_APB_MEM_RADDR_CH6_S 11 /* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h120 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH6 0x000003FF -#define RMT_MEM_WADDR_EX_CH6_M ((RMT_MEM_WADDR_EX_CH6_V) << (RMT_MEM_WADDR_EX_CH6_S)) -#define RMT_MEM_WADDR_EX_CH6_V 0x3FF -#define RMT_MEM_WADDR_EX_CH6_S 0 +/*description: .*/ +#define RMT_MEM_WADDR_EX_CH6 0x000003FF +#define RMT_MEM_WADDR_EX_CH6_M ((RMT_MEM_WADDR_EX_CH6_V)<<(RMT_MEM_WADDR_EX_CH6_S)) +#define RMT_MEM_WADDR_EX_CH6_V 0x3FF +#define RMT_MEM_WADDR_EX_CH6_S 0 -#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x006c) +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x6C) /* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH7 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH7_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH7_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH7_S 27 +/*description: .*/ +#define RMT_APB_MEM_RD_ERR_CH7 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH7_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH7_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH7_S 27 /* RMT_MEM_FULL_CH7 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH7 (BIT(26)) -#define RMT_MEM_FULL_CH7_M (BIT(26)) -#define RMT_MEM_FULL_CH7_V 0x1 -#define RMT_MEM_FULL_CH7_S 26 +/*description: .*/ +#define RMT_MEM_FULL_CH7 (BIT(26)) +#define RMT_MEM_FULL_CH7_M (BIT(26)) +#define RMT_MEM_FULL_CH7_V 0x1 +#define RMT_MEM_FULL_CH7_S 26 /* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH7 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH7_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH7_V 0x1 -#define RMT_MEM_OWNER_ERR_CH7_S 25 +/*description: .*/ +#define RMT_MEM_OWNER_ERR_CH7 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH7_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH7_V 0x1 +#define RMT_MEM_OWNER_ERR_CH7_S 25 /* RMT_STATE_CH7 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH7 0x00000007 -#define RMT_STATE_CH7_M ((RMT_STATE_CH7_V) << (RMT_STATE_CH7_S)) -#define RMT_STATE_CH7_V 0x7 -#define RMT_STATE_CH7_S 22 +/*description: .*/ +#define RMT_STATE_CH7 0x00000007 +#define RMT_STATE_CH7_M ((RMT_STATE_CH7_V)<<(RMT_STATE_CH7_S)) +#define RMT_STATE_CH7_V 0x7 +#define RMT_STATE_CH7_S 22 +/* RMT_FIFO_EMPTY_CH7 : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_FIFO_EMPTY_CH7 (BIT(21)) +#define RMT_FIFO_EMPTY_CH7_M (BIT(21)) +#define RMT_FIFO_EMPTY_CH7_V 0x1 +#define RMT_FIFO_EMPTY_CH7_S 21 /* RMT_APB_MEM_RADDR_CH7 : RO ;bitpos:[20:11] ;default: 10'h150 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH7 0x000003FF -#define RMT_APB_MEM_RADDR_CH7_M ((RMT_APB_MEM_RADDR_CH7_V) << (RMT_APB_MEM_RADDR_CH7_S)) -#define RMT_APB_MEM_RADDR_CH7_V 0x3FF -#define RMT_APB_MEM_RADDR_CH7_S 11 +/*description: .*/ +#define RMT_APB_MEM_RADDR_CH7 0x000003FF +#define RMT_APB_MEM_RADDR_CH7_M ((RMT_APB_MEM_RADDR_CH7_V)<<(RMT_APB_MEM_RADDR_CH7_S)) +#define RMT_APB_MEM_RADDR_CH7_V 0x3FF +#define RMT_APB_MEM_RADDR_CH7_S 11 /* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h150 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH7 0x000003FF -#define RMT_MEM_WADDR_EX_CH7_M ((RMT_MEM_WADDR_EX_CH7_V) << (RMT_MEM_WADDR_EX_CH7_S)) -#define RMT_MEM_WADDR_EX_CH7_V 0x3FF -#define RMT_MEM_WADDR_EX_CH7_S 0 +/*description: .*/ +#define RMT_MEM_WADDR_EX_CH7 0x000003FF +#define RMT_MEM_WADDR_EX_CH7_M ((RMT_MEM_WADDR_EX_CH7_V)<<(RMT_MEM_WADDR_EX_CH7_S)) +#define RMT_MEM_WADDR_EX_CH7_V 0x3FF +#define RMT_MEM_WADDR_EX_CH7_S 0 -#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x0070) +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x70) +/* RMT_CH7_DMA_ACCESS_FAIL_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_M (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_V 0x1 +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S 29 +/* RMT_CH3_DMA_ACCESS_FAIL_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_M (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_V 0x1 +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S 28 /* RMT_CH7_RX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_THR_EVENT_INT_RAW (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_RAW_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_RAW_S 27 +/*description: .*/ +#define RMT_CH7_RX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_M (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH7_RX_THR_EVENT_INT_RAW_S 27 /* RMT_CH6_RX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_THR_EVENT_INT_RAW (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_RAW_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_RAW_S 26 +/*description: .*/ +#define RMT_CH6_RX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_M (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH6_RX_THR_EVENT_INT_RAW_S 26 /* RMT_CH5_RX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_THR_EVENT_INT_RAW (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_RAW_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_RAW_S 25 +/*description: .*/ +#define RMT_CH5_RX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_M (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH5_RX_THR_EVENT_INT_RAW_S 25 /* RMT_CH4_RX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_THR_EVENT_INT_RAW (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_RAW_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_RAW_S 24 +/*description: .*/ +#define RMT_CH4_RX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_M (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH4_RX_THR_EVENT_INT_RAW_S 24 /* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_ERR_INT_RAW (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_V 0x1 -#define RMT_CH7_ERR_INT_RAW_S 23 +/*description: .*/ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_V 0x1 +#define RMT_CH7_ERR_INT_RAW_S 23 /* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_ERR_INT_RAW (BIT(22)) -#define RMT_CH6_ERR_INT_RAW_M (BIT(22)) -#define RMT_CH6_ERR_INT_RAW_V 0x1 -#define RMT_CH6_ERR_INT_RAW_S 22 +/*description: .*/ +#define RMT_CH6_ERR_INT_RAW (BIT(22)) +#define RMT_CH6_ERR_INT_RAW_M (BIT(22)) +#define RMT_CH6_ERR_INT_RAW_V 0x1 +#define RMT_CH6_ERR_INT_RAW_S 22 /* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_ERR_INT_RAW (BIT(21)) -#define RMT_CH5_ERR_INT_RAW_M (BIT(21)) -#define RMT_CH5_ERR_INT_RAW_V 0x1 -#define RMT_CH5_ERR_INT_RAW_S 21 +/*description: .*/ +#define RMT_CH5_ERR_INT_RAW (BIT(21)) +#define RMT_CH5_ERR_INT_RAW_M (BIT(21)) +#define RMT_CH5_ERR_INT_RAW_V 0x1 +#define RMT_CH5_ERR_INT_RAW_S 21 /* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_ERR_INT_RAW (BIT(20)) -#define RMT_CH4_ERR_INT_RAW_M (BIT(20)) -#define RMT_CH4_ERR_INT_RAW_V 0x1 -#define RMT_CH4_ERR_INT_RAW_S 20 +/*description: .*/ +#define RMT_CH4_ERR_INT_RAW (BIT(20)) +#define RMT_CH4_ERR_INT_RAW_M (BIT(20)) +#define RMT_CH4_ERR_INT_RAW_V 0x1 +#define RMT_CH4_ERR_INT_RAW_S 20 /* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_END_INT_RAW (BIT(19)) -#define RMT_CH7_RX_END_INT_RAW_M (BIT(19)) -#define RMT_CH7_RX_END_INT_RAW_V 0x1 -#define RMT_CH7_RX_END_INT_RAW_S 19 +/*description: .*/ +#define RMT_CH7_RX_END_INT_RAW (BIT(19)) +#define RMT_CH7_RX_END_INT_RAW_M (BIT(19)) +#define RMT_CH7_RX_END_INT_RAW_V 0x1 +#define RMT_CH7_RX_END_INT_RAW_S 19 /* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_END_INT_RAW (BIT(18)) -#define RMT_CH6_RX_END_INT_RAW_M (BIT(18)) -#define RMT_CH6_RX_END_INT_RAW_V 0x1 -#define RMT_CH6_RX_END_INT_RAW_S 18 +/*description: .*/ +#define RMT_CH6_RX_END_INT_RAW (BIT(18)) +#define RMT_CH6_RX_END_INT_RAW_M (BIT(18)) +#define RMT_CH6_RX_END_INT_RAW_V 0x1 +#define RMT_CH6_RX_END_INT_RAW_S 18 /* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_END_INT_RAW (BIT(17)) -#define RMT_CH5_RX_END_INT_RAW_M (BIT(17)) -#define RMT_CH5_RX_END_INT_RAW_V 0x1 -#define RMT_CH5_RX_END_INT_RAW_S 17 +/*description: .*/ +#define RMT_CH5_RX_END_INT_RAW (BIT(17)) +#define RMT_CH5_RX_END_INT_RAW_M (BIT(17)) +#define RMT_CH5_RX_END_INT_RAW_V 0x1 +#define RMT_CH5_RX_END_INT_RAW_S 17 /* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_END_INT_RAW (BIT(16)) -#define RMT_CH4_RX_END_INT_RAW_M (BIT(16)) -#define RMT_CH4_RX_END_INT_RAW_V 0x1 -#define RMT_CH4_RX_END_INT_RAW_S 16 +/*description: .*/ +#define RMT_CH4_RX_END_INT_RAW (BIT(16)) +#define RMT_CH4_RX_END_INT_RAW_M (BIT(16)) +#define RMT_CH4_RX_END_INT_RAW_V 0x1 +#define RMT_CH4_RX_END_INT_RAW_S 16 /* RMT_CH3_TX_LOOP_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_LOOP_INT_RAW (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_RAW_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH3_TX_LOOP_INT_RAW_S 15 +/*description: .*/ +#define RMT_CH3_TX_LOOP_INT_RAW (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_RAW_M (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH3_TX_LOOP_INT_RAW_S 15 /* RMT_CH2_TX_LOOP_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_LOOP_INT_RAW (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_RAW_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH2_TX_LOOP_INT_RAW_S 14 +/*description: .*/ +#define RMT_CH2_TX_LOOP_INT_RAW (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_RAW_M (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH2_TX_LOOP_INT_RAW_S 14 /* RMT_CH1_TX_LOOP_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_RAW_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH1_TX_LOOP_INT_RAW_S 13 +/*description: .*/ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 /* RMT_CH0_TX_LOOP_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_RAW_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/*description: .*/ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 /* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 11 +/*description: .*/ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 11 /* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 10 +/*description: .*/ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 10 /* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/*description: .*/ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 /* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/*description: .*/ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 /* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_RAW (BIT(7)) -#define RMT_CH3_ERR_INT_RAW_M (BIT(7)) -#define RMT_CH3_ERR_INT_RAW_V 0x1 -#define RMT_CH3_ERR_INT_RAW_S 7 +/*description: .*/ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_V 0x1 +#define RMT_CH3_ERR_INT_RAW_S 7 /* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_RAW (BIT(6)) -#define RMT_CH2_ERR_INT_RAW_M (BIT(6)) -#define RMT_CH2_ERR_INT_RAW_V 0x1 -#define RMT_CH2_ERR_INT_RAW_S 6 +/*description: .*/ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_V 0x1 +#define RMT_CH2_ERR_INT_RAW_S 6 /* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_RAW (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_V 0x1 -#define RMT_CH1_ERR_INT_RAW_S 5 +/*description: .*/ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_V 0x1 +#define RMT_CH1_ERR_INT_RAW_S 5 /* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_RAW (BIT(4)) -#define RMT_CH0_ERR_INT_RAW_M (BIT(4)) -#define RMT_CH0_ERR_INT_RAW_V 0x1 -#define RMT_CH0_ERR_INT_RAW_S 4 +/*description: .*/ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_V 0x1 +#define RMT_CH0_ERR_INT_RAW_S 4 /* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_END_INT_RAW (BIT(3)) -#define RMT_CH3_TX_END_INT_RAW_M (BIT(3)) -#define RMT_CH3_TX_END_INT_RAW_V 0x1 -#define RMT_CH3_TX_END_INT_RAW_S 3 +/*description: .*/ +#define RMT_CH3_TX_END_INT_RAW (BIT(3)) +#define RMT_CH3_TX_END_INT_RAW_M (BIT(3)) +#define RMT_CH3_TX_END_INT_RAW_V 0x1 +#define RMT_CH3_TX_END_INT_RAW_S 3 /* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_END_INT_RAW (BIT(2)) -#define RMT_CH2_TX_END_INT_RAW_M (BIT(2)) -#define RMT_CH2_TX_END_INT_RAW_V 0x1 -#define RMT_CH2_TX_END_INT_RAW_S 2 +/*description: .*/ +#define RMT_CH2_TX_END_INT_RAW (BIT(2)) +#define RMT_CH2_TX_END_INT_RAW_M (BIT(2)) +#define RMT_CH2_TX_END_INT_RAW_V 0x1 +#define RMT_CH2_TX_END_INT_RAW_S 2 /* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_RAW (BIT(1)) -#define RMT_CH1_TX_END_INT_RAW_M (BIT(1)) -#define RMT_CH1_TX_END_INT_RAW_V 0x1 -#define RMT_CH1_TX_END_INT_RAW_S 1 +/*description: .*/ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_V 0x1 +#define RMT_CH1_TX_END_INT_RAW_S 1 /* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_RAW (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_V 0x1 -#define RMT_CH0_TX_END_INT_RAW_S 0 +/*description: .*/ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_V 0x1 +#define RMT_CH0_TX_END_INT_RAW_S 0 -#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x0074) +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x74) +/* RMT_CH7_DMA_ACCESS_FAIL_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_M (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_V 0x1 +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S 29 +/* RMT_CH3_DMA_ACCESS_FAIL_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_M (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_V 0x1 +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S 28 /* RMT_CH7_RX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_THR_EVENT_INT_ST (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ST_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_ST_S 27 +/*description: .*/ +#define RMT_CH7_RX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ST_M (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH7_RX_THR_EVENT_INT_ST_S 27 /* RMT_CH6_RX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_THR_EVENT_INT_ST (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ST_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_ST_S 26 +/*description: .*/ +#define RMT_CH6_RX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ST_M (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH6_RX_THR_EVENT_INT_ST_S 26 /* RMT_CH5_RX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_THR_EVENT_INT_ST (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ST_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_ST_S 25 +/*description: .*/ +#define RMT_CH5_RX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ST_M (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH5_RX_THR_EVENT_INT_ST_S 25 /* RMT_CH4_RX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_THR_EVENT_INT_ST (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ST_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_ST_S 24 +/*description: .*/ +#define RMT_CH4_RX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ST_M (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH4_RX_THR_EVENT_INT_ST_S 24 /* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_ERR_INT_ST (BIT(23)) -#define RMT_CH7_ERR_INT_ST_M (BIT(23)) -#define RMT_CH7_ERR_INT_ST_V 0x1 -#define RMT_CH7_ERR_INT_ST_S 23 +/*description: .*/ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (BIT(23)) +#define RMT_CH7_ERR_INT_ST_V 0x1 +#define RMT_CH7_ERR_INT_ST_S 23 /* RMT_CH6_ERR_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_ERR_INT_ST (BIT(22)) -#define RMT_CH6_ERR_INT_ST_M (BIT(22)) -#define RMT_CH6_ERR_INT_ST_V 0x1 -#define RMT_CH6_ERR_INT_ST_S 22 +/*description: .*/ +#define RMT_CH6_ERR_INT_ST (BIT(22)) +#define RMT_CH6_ERR_INT_ST_M (BIT(22)) +#define RMT_CH6_ERR_INT_ST_V 0x1 +#define RMT_CH6_ERR_INT_ST_S 22 /* RMT_CH5_ERR_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_ERR_INT_ST (BIT(21)) -#define RMT_CH5_ERR_INT_ST_M (BIT(21)) -#define RMT_CH5_ERR_INT_ST_V 0x1 -#define RMT_CH5_ERR_INT_ST_S 21 +/*description: .*/ +#define RMT_CH5_ERR_INT_ST (BIT(21)) +#define RMT_CH5_ERR_INT_ST_M (BIT(21)) +#define RMT_CH5_ERR_INT_ST_V 0x1 +#define RMT_CH5_ERR_INT_ST_S 21 /* RMT_CH4_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_ERR_INT_ST (BIT(20)) -#define RMT_CH4_ERR_INT_ST_M (BIT(20)) -#define RMT_CH4_ERR_INT_ST_V 0x1 -#define RMT_CH4_ERR_INT_ST_S 20 +/*description: .*/ +#define RMT_CH4_ERR_INT_ST (BIT(20)) +#define RMT_CH4_ERR_INT_ST_M (BIT(20)) +#define RMT_CH4_ERR_INT_ST_V 0x1 +#define RMT_CH4_ERR_INT_ST_S 20 /* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_END_INT_ST (BIT(19)) -#define RMT_CH7_RX_END_INT_ST_M (BIT(19)) -#define RMT_CH7_RX_END_INT_ST_V 0x1 -#define RMT_CH7_RX_END_INT_ST_S 19 +/*description: .*/ +#define RMT_CH7_RX_END_INT_ST (BIT(19)) +#define RMT_CH7_RX_END_INT_ST_M (BIT(19)) +#define RMT_CH7_RX_END_INT_ST_V 0x1 +#define RMT_CH7_RX_END_INT_ST_S 19 /* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_END_INT_ST (BIT(18)) -#define RMT_CH6_RX_END_INT_ST_M (BIT(18)) -#define RMT_CH6_RX_END_INT_ST_V 0x1 -#define RMT_CH6_RX_END_INT_ST_S 18 +/*description: .*/ +#define RMT_CH6_RX_END_INT_ST (BIT(18)) +#define RMT_CH6_RX_END_INT_ST_M (BIT(18)) +#define RMT_CH6_RX_END_INT_ST_V 0x1 +#define RMT_CH6_RX_END_INT_ST_S 18 /* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_END_INT_ST (BIT(17)) -#define RMT_CH5_RX_END_INT_ST_M (BIT(17)) -#define RMT_CH5_RX_END_INT_ST_V 0x1 -#define RMT_CH5_RX_END_INT_ST_S 17 +/*description: .*/ +#define RMT_CH5_RX_END_INT_ST (BIT(17)) +#define RMT_CH5_RX_END_INT_ST_M (BIT(17)) +#define RMT_CH5_RX_END_INT_ST_V 0x1 +#define RMT_CH5_RX_END_INT_ST_S 17 /* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_END_INT_ST (BIT(16)) -#define RMT_CH4_RX_END_INT_ST_M (BIT(16)) -#define RMT_CH4_RX_END_INT_ST_V 0x1 -#define RMT_CH4_RX_END_INT_ST_S 16 +/*description: .*/ +#define RMT_CH4_RX_END_INT_ST (BIT(16)) +#define RMT_CH4_RX_END_INT_ST_M (BIT(16)) +#define RMT_CH4_RX_END_INT_ST_V 0x1 +#define RMT_CH4_RX_END_INT_ST_S 16 /* RMT_CH3_TX_LOOP_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_LOOP_INT_ST (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ST_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH3_TX_LOOP_INT_ST_S 15 +/*description: .*/ +#define RMT_CH3_TX_LOOP_INT_ST (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ST_M (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH3_TX_LOOP_INT_ST_S 15 /* RMT_CH2_TX_LOOP_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_LOOP_INT_ST (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ST_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH2_TX_LOOP_INT_ST_S 14 +/*description: .*/ +#define RMT_CH2_TX_LOOP_INT_ST (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ST_M (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH2_TX_LOOP_INT_ST_S 14 /* RMT_CH1_TX_LOOP_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ST_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH1_TX_LOOP_INT_ST_S 13 +/*description: .*/ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH1_TX_LOOP_INT_ST_S 13 /* RMT_CH0_TX_LOOP_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ST_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/*description: .*/ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH0_TX_LOOP_INT_ST_S 12 /* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ST_S 11 +/*description: .*/ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 11 /* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ST_S 10 +/*description: .*/ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 10 /* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/*description: .*/ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 /* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/*description: .*/ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 /* RMT_CH3_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_ST (BIT(7)) -#define RMT_CH3_ERR_INT_ST_M (BIT(7)) -#define RMT_CH3_ERR_INT_ST_V 0x1 -#define RMT_CH3_ERR_INT_ST_S 7 +/*description: .*/ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (BIT(7)) +#define RMT_CH3_ERR_INT_ST_V 0x1 +#define RMT_CH3_ERR_INT_ST_S 7 /* RMT_CH2_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_ST (BIT(6)) -#define RMT_CH2_ERR_INT_ST_M (BIT(6)) -#define RMT_CH2_ERR_INT_ST_V 0x1 -#define RMT_CH2_ERR_INT_ST_S 6 +/*description: .*/ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (BIT(6)) +#define RMT_CH2_ERR_INT_ST_V 0x1 +#define RMT_CH2_ERR_INT_ST_S 6 /* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_ST (BIT(5)) -#define RMT_CH1_ERR_INT_ST_M (BIT(5)) -#define RMT_CH1_ERR_INT_ST_V 0x1 -#define RMT_CH1_ERR_INT_ST_S 5 +/*description: .*/ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (BIT(5)) +#define RMT_CH1_ERR_INT_ST_V 0x1 +#define RMT_CH1_ERR_INT_ST_S 5 /* RMT_CH0_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_ST (BIT(4)) -#define RMT_CH0_ERR_INT_ST_M (BIT(4)) -#define RMT_CH0_ERR_INT_ST_V 0x1 -#define RMT_CH0_ERR_INT_ST_S 4 +/*description: .*/ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (BIT(4)) +#define RMT_CH0_ERR_INT_ST_V 0x1 +#define RMT_CH0_ERR_INT_ST_S 4 /* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_END_INT_ST (BIT(3)) -#define RMT_CH3_TX_END_INT_ST_M (BIT(3)) -#define RMT_CH3_TX_END_INT_ST_V 0x1 -#define RMT_CH3_TX_END_INT_ST_S 3 +/*description: .*/ +#define RMT_CH3_TX_END_INT_ST (BIT(3)) +#define RMT_CH3_TX_END_INT_ST_M (BIT(3)) +#define RMT_CH3_TX_END_INT_ST_V 0x1 +#define RMT_CH3_TX_END_INT_ST_S 3 /* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_END_INT_ST (BIT(2)) -#define RMT_CH2_TX_END_INT_ST_M (BIT(2)) -#define RMT_CH2_TX_END_INT_ST_V 0x1 -#define RMT_CH2_TX_END_INT_ST_S 2 +/*description: .*/ +#define RMT_CH2_TX_END_INT_ST (BIT(2)) +#define RMT_CH2_TX_END_INT_ST_M (BIT(2)) +#define RMT_CH2_TX_END_INT_ST_V 0x1 +#define RMT_CH2_TX_END_INT_ST_S 2 /* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_ST (BIT(1)) -#define RMT_CH1_TX_END_INT_ST_M (BIT(1)) -#define RMT_CH1_TX_END_INT_ST_V 0x1 -#define RMT_CH1_TX_END_INT_ST_S 1 +/*description: .*/ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_V 0x1 +#define RMT_CH1_TX_END_INT_ST_S 1 /* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_ST (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_V 0x1 -#define RMT_CH0_TX_END_INT_ST_S 0 +/*description: .*/ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_V 0x1 +#define RMT_CH0_TX_END_INT_ST_S 0 -#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x0078) +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x78) +/* RMT_CH7_DMA_ACCESS_FAIL_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_M (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_V 0x1 +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S 29 +/* RMT_CH3_DMA_ACCESS_FAIL_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_M (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_V 0x1 +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S 28 /* RMT_CH7_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_THR_EVENT_INT_ENA (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ENA_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_ENA_S 27 +/*description: .*/ +#define RMT_CH7_RX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_M (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH7_RX_THR_EVENT_INT_ENA_S 27 /* RMT_CH6_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_THR_EVENT_INT_ENA (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ENA_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_ENA_S 26 +/*description: .*/ +#define RMT_CH6_RX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_M (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH6_RX_THR_EVENT_INT_ENA_S 26 /* RMT_CH5_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_THR_EVENT_INT_ENA (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ENA_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_ENA_S 25 +/*description: .*/ +#define RMT_CH5_RX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_M (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH5_RX_THR_EVENT_INT_ENA_S 25 /* RMT_CH4_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_THR_EVENT_INT_ENA (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ENA_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_ENA_S 24 +/*description: .*/ +#define RMT_CH4_RX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_M (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH4_RX_THR_EVENT_INT_ENA_S 24 /* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_ERR_INT_ENA (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_V 0x1 -#define RMT_CH7_ERR_INT_ENA_S 23 +/*description: .*/ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_V 0x1 +#define RMT_CH7_ERR_INT_ENA_S 23 /* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_ERR_INT_ENA (BIT(22)) -#define RMT_CH6_ERR_INT_ENA_M (BIT(22)) -#define RMT_CH6_ERR_INT_ENA_V 0x1 -#define RMT_CH6_ERR_INT_ENA_S 22 +/*description: .*/ +#define RMT_CH6_ERR_INT_ENA (BIT(22)) +#define RMT_CH6_ERR_INT_ENA_M (BIT(22)) +#define RMT_CH6_ERR_INT_ENA_V 0x1 +#define RMT_CH6_ERR_INT_ENA_S 22 /* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_ERR_INT_ENA (BIT(21)) -#define RMT_CH5_ERR_INT_ENA_M (BIT(21)) -#define RMT_CH5_ERR_INT_ENA_V 0x1 -#define RMT_CH5_ERR_INT_ENA_S 21 +/*description: .*/ +#define RMT_CH5_ERR_INT_ENA (BIT(21)) +#define RMT_CH5_ERR_INT_ENA_M (BIT(21)) +#define RMT_CH5_ERR_INT_ENA_V 0x1 +#define RMT_CH5_ERR_INT_ENA_S 21 /* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_ERR_INT_ENA (BIT(20)) -#define RMT_CH4_ERR_INT_ENA_M (BIT(20)) -#define RMT_CH4_ERR_INT_ENA_V 0x1 -#define RMT_CH4_ERR_INT_ENA_S 20 +/*description: .*/ +#define RMT_CH4_ERR_INT_ENA (BIT(20)) +#define RMT_CH4_ERR_INT_ENA_M (BIT(20)) +#define RMT_CH4_ERR_INT_ENA_V 0x1 +#define RMT_CH4_ERR_INT_ENA_S 20 /* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_END_INT_ENA (BIT(19)) -#define RMT_CH7_RX_END_INT_ENA_M (BIT(19)) -#define RMT_CH7_RX_END_INT_ENA_V 0x1 -#define RMT_CH7_RX_END_INT_ENA_S 19 +/*description: .*/ +#define RMT_CH7_RX_END_INT_ENA (BIT(19)) +#define RMT_CH7_RX_END_INT_ENA_M (BIT(19)) +#define RMT_CH7_RX_END_INT_ENA_V 0x1 +#define RMT_CH7_RX_END_INT_ENA_S 19 /* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_END_INT_ENA (BIT(18)) -#define RMT_CH6_RX_END_INT_ENA_M (BIT(18)) -#define RMT_CH6_RX_END_INT_ENA_V 0x1 -#define RMT_CH6_RX_END_INT_ENA_S 18 +/*description: .*/ +#define RMT_CH6_RX_END_INT_ENA (BIT(18)) +#define RMT_CH6_RX_END_INT_ENA_M (BIT(18)) +#define RMT_CH6_RX_END_INT_ENA_V 0x1 +#define RMT_CH6_RX_END_INT_ENA_S 18 /* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_END_INT_ENA (BIT(17)) -#define RMT_CH5_RX_END_INT_ENA_M (BIT(17)) -#define RMT_CH5_RX_END_INT_ENA_V 0x1 -#define RMT_CH5_RX_END_INT_ENA_S 17 +/*description: .*/ +#define RMT_CH5_RX_END_INT_ENA (BIT(17)) +#define RMT_CH5_RX_END_INT_ENA_M (BIT(17)) +#define RMT_CH5_RX_END_INT_ENA_V 0x1 +#define RMT_CH5_RX_END_INT_ENA_S 17 /* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_END_INT_ENA (BIT(16)) -#define RMT_CH4_RX_END_INT_ENA_M (BIT(16)) -#define RMT_CH4_RX_END_INT_ENA_V 0x1 -#define RMT_CH4_RX_END_INT_ENA_S 16 +/*description: .*/ +#define RMT_CH4_RX_END_INT_ENA (BIT(16)) +#define RMT_CH4_RX_END_INT_ENA_M (BIT(16)) +#define RMT_CH4_RX_END_INT_ENA_V 0x1 +#define RMT_CH4_RX_END_INT_ENA_S 16 /* RMT_CH3_TX_LOOP_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_LOOP_INT_ENA (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ENA_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH3_TX_LOOP_INT_ENA_S 15 +/*description: .*/ +#define RMT_CH3_TX_LOOP_INT_ENA (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ENA_M (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH3_TX_LOOP_INT_ENA_S 15 /* RMT_CH2_TX_LOOP_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_LOOP_INT_ENA (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ENA_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH2_TX_LOOP_INT_ENA_S 14 +/*description: .*/ +#define RMT_CH2_TX_LOOP_INT_ENA (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ENA_M (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH2_TX_LOOP_INT_ENA_S 14 /* RMT_CH1_TX_LOOP_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ENA_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH1_TX_LOOP_INT_ENA_S 13 +/*description: .*/ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 /* RMT_CH0_TX_LOOP_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ENA_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/*description: .*/ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 /* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 11 +/*description: .*/ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 11 /* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 10 +/*description: .*/ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 10 /* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/*description: .*/ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 /* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/*description: .*/ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 /* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_ENA (BIT(7)) -#define RMT_CH3_ERR_INT_ENA_M (BIT(7)) -#define RMT_CH3_ERR_INT_ENA_V 0x1 -#define RMT_CH3_ERR_INT_ENA_S 7 +/*description: .*/ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_V 0x1 +#define RMT_CH3_ERR_INT_ENA_S 7 /* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_ENA (BIT(6)) -#define RMT_CH2_ERR_INT_ENA_M (BIT(6)) -#define RMT_CH2_ERR_INT_ENA_V 0x1 -#define RMT_CH2_ERR_INT_ENA_S 6 +/*description: .*/ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_V 0x1 +#define RMT_CH2_ERR_INT_ENA_S 6 /* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_ENA (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_V 0x1 -#define RMT_CH1_ERR_INT_ENA_S 5 +/*description: .*/ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_V 0x1 +#define RMT_CH1_ERR_INT_ENA_S 5 /* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_ENA (BIT(4)) -#define RMT_CH0_ERR_INT_ENA_M (BIT(4)) -#define RMT_CH0_ERR_INT_ENA_V 0x1 -#define RMT_CH0_ERR_INT_ENA_S 4 +/*description: .*/ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_V 0x1 +#define RMT_CH0_ERR_INT_ENA_S 4 /* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_END_INT_ENA (BIT(3)) -#define RMT_CH3_TX_END_INT_ENA_M (BIT(3)) -#define RMT_CH3_TX_END_INT_ENA_V 0x1 -#define RMT_CH3_TX_END_INT_ENA_S 3 +/*description: .*/ +#define RMT_CH3_TX_END_INT_ENA (BIT(3)) +#define RMT_CH3_TX_END_INT_ENA_M (BIT(3)) +#define RMT_CH3_TX_END_INT_ENA_V 0x1 +#define RMT_CH3_TX_END_INT_ENA_S 3 /* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_END_INT_ENA (BIT(2)) -#define RMT_CH2_TX_END_INT_ENA_M (BIT(2)) -#define RMT_CH2_TX_END_INT_ENA_V 0x1 -#define RMT_CH2_TX_END_INT_ENA_S 2 +/*description: .*/ +#define RMT_CH2_TX_END_INT_ENA (BIT(2)) +#define RMT_CH2_TX_END_INT_ENA_M (BIT(2)) +#define RMT_CH2_TX_END_INT_ENA_V 0x1 +#define RMT_CH2_TX_END_INT_ENA_S 2 /* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_ENA (BIT(1)) -#define RMT_CH1_TX_END_INT_ENA_M (BIT(1)) -#define RMT_CH1_TX_END_INT_ENA_V 0x1 -#define RMT_CH1_TX_END_INT_ENA_S 1 +/*description: .*/ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_V 0x1 +#define RMT_CH1_TX_END_INT_ENA_S 1 /* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_ENA (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_V 0x1 -#define RMT_CH0_TX_END_INT_ENA_S 0 +/*description: .*/ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_V 0x1 +#define RMT_CH0_TX_END_INT_ENA_S 0 -#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x007c) +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x7C) +/* RMT_CH7_DMA_ACCESS_FAIL_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_M (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_V 0x1 +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S 29 +/* RMT_CH3_DMA_ACCESS_FAIL_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_M (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_V 0x1 +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S 28 /* RMT_CH7_RX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_THR_EVENT_INT_CLR (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_CLR_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_CLR_S 27 +/*description: .*/ +#define RMT_CH7_RX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_M (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH7_RX_THR_EVENT_INT_CLR_S 27 /* RMT_CH6_RX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_THR_EVENT_INT_CLR (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_CLR_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_CLR_S 26 +/*description: .*/ +#define RMT_CH6_RX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_M (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH6_RX_THR_EVENT_INT_CLR_S 26 /* RMT_CH5_RX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_THR_EVENT_INT_CLR (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_CLR_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_CLR_S 25 +/*description: .*/ +#define RMT_CH5_RX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_M (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH5_RX_THR_EVENT_INT_CLR_S 25 /* RMT_CH4_RX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_THR_EVENT_INT_CLR (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_CLR_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_CLR_S 24 +/*description: .*/ +#define RMT_CH4_RX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_M (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH4_RX_THR_EVENT_INT_CLR_S 24 /* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_ERR_INT_CLR (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_V 0x1 -#define RMT_CH7_ERR_INT_CLR_S 23 +/*description: .*/ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_V 0x1 +#define RMT_CH7_ERR_INT_CLR_S 23 /* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_ERR_INT_CLR (BIT(22)) -#define RMT_CH6_ERR_INT_CLR_M (BIT(22)) -#define RMT_CH6_ERR_INT_CLR_V 0x1 -#define RMT_CH6_ERR_INT_CLR_S 22 +/*description: .*/ +#define RMT_CH6_ERR_INT_CLR (BIT(22)) +#define RMT_CH6_ERR_INT_CLR_M (BIT(22)) +#define RMT_CH6_ERR_INT_CLR_V 0x1 +#define RMT_CH6_ERR_INT_CLR_S 22 /* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_ERR_INT_CLR (BIT(21)) -#define RMT_CH5_ERR_INT_CLR_M (BIT(21)) -#define RMT_CH5_ERR_INT_CLR_V 0x1 -#define RMT_CH5_ERR_INT_CLR_S 21 +/*description: .*/ +#define RMT_CH5_ERR_INT_CLR (BIT(21)) +#define RMT_CH5_ERR_INT_CLR_M (BIT(21)) +#define RMT_CH5_ERR_INT_CLR_V 0x1 +#define RMT_CH5_ERR_INT_CLR_S 21 /* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_ERR_INT_CLR (BIT(20)) -#define RMT_CH4_ERR_INT_CLR_M (BIT(20)) -#define RMT_CH4_ERR_INT_CLR_V 0x1 -#define RMT_CH4_ERR_INT_CLR_S 20 +/*description: .*/ +#define RMT_CH4_ERR_INT_CLR (BIT(20)) +#define RMT_CH4_ERR_INT_CLR_M (BIT(20)) +#define RMT_CH4_ERR_INT_CLR_V 0x1 +#define RMT_CH4_ERR_INT_CLR_S 20 /* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH7_RX_END_INT_CLR (BIT(19)) -#define RMT_CH7_RX_END_INT_CLR_M (BIT(19)) -#define RMT_CH7_RX_END_INT_CLR_V 0x1 -#define RMT_CH7_RX_END_INT_CLR_S 19 +/*description: .*/ +#define RMT_CH7_RX_END_INT_CLR (BIT(19)) +#define RMT_CH7_RX_END_INT_CLR_M (BIT(19)) +#define RMT_CH7_RX_END_INT_CLR_V 0x1 +#define RMT_CH7_RX_END_INT_CLR_S 19 /* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH6_RX_END_INT_CLR (BIT(18)) -#define RMT_CH6_RX_END_INT_CLR_M (BIT(18)) -#define RMT_CH6_RX_END_INT_CLR_V 0x1 -#define RMT_CH6_RX_END_INT_CLR_S 18 +/*description: .*/ +#define RMT_CH6_RX_END_INT_CLR (BIT(18)) +#define RMT_CH6_RX_END_INT_CLR_M (BIT(18)) +#define RMT_CH6_RX_END_INT_CLR_V 0x1 +#define RMT_CH6_RX_END_INT_CLR_S 18 /* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH5_RX_END_INT_CLR (BIT(17)) -#define RMT_CH5_RX_END_INT_CLR_M (BIT(17)) -#define RMT_CH5_RX_END_INT_CLR_V 0x1 -#define RMT_CH5_RX_END_INT_CLR_S 17 +/*description: .*/ +#define RMT_CH5_RX_END_INT_CLR (BIT(17)) +#define RMT_CH5_RX_END_INT_CLR_M (BIT(17)) +#define RMT_CH5_RX_END_INT_CLR_V 0x1 +#define RMT_CH5_RX_END_INT_CLR_S 17 /* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH4_RX_END_INT_CLR (BIT(16)) -#define RMT_CH4_RX_END_INT_CLR_M (BIT(16)) -#define RMT_CH4_RX_END_INT_CLR_V 0x1 -#define RMT_CH4_RX_END_INT_CLR_S 16 +/*description: .*/ +#define RMT_CH4_RX_END_INT_CLR (BIT(16)) +#define RMT_CH4_RX_END_INT_CLR_M (BIT(16)) +#define RMT_CH4_RX_END_INT_CLR_V 0x1 +#define RMT_CH4_RX_END_INT_CLR_S 16 /* RMT_CH3_TX_LOOP_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_LOOP_INT_CLR (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_CLR_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH3_TX_LOOP_INT_CLR_S 15 +/*description: .*/ +#define RMT_CH3_TX_LOOP_INT_CLR (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_CLR_M (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH3_TX_LOOP_INT_CLR_S 15 /* RMT_CH2_TX_LOOP_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_LOOP_INT_CLR (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_CLR_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH2_TX_LOOP_INT_CLR_S 14 +/*description: .*/ +#define RMT_CH2_TX_LOOP_INT_CLR (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_CLR_M (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH2_TX_LOOP_INT_CLR_S 14 /* RMT_CH1_TX_LOOP_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_CLR_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH1_TX_LOOP_INT_CLR_S 13 +/*description: .*/ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 /* RMT_CH0_TX_LOOP_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_CLR_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/*description: .*/ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 /* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 11 +/*description: .*/ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 11 /* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 10 +/*description: .*/ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 10 /* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/*description: .*/ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 /* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/*description: .*/ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 /* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_CLR (BIT(7)) -#define RMT_CH3_ERR_INT_CLR_M (BIT(7)) -#define RMT_CH3_ERR_INT_CLR_V 0x1 -#define RMT_CH3_ERR_INT_CLR_S 7 +/*description: .*/ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_V 0x1 +#define RMT_CH3_ERR_INT_CLR_S 7 /* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_CLR (BIT(6)) -#define RMT_CH2_ERR_INT_CLR_M (BIT(6)) -#define RMT_CH2_ERR_INT_CLR_V 0x1 -#define RMT_CH2_ERR_INT_CLR_S 6 +/*description: .*/ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_V 0x1 +#define RMT_CH2_ERR_INT_CLR_S 6 /* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_CLR (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_V 0x1 -#define RMT_CH1_ERR_INT_CLR_S 5 +/*description: .*/ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_V 0x1 +#define RMT_CH1_ERR_INT_CLR_S 5 /* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_CLR (BIT(4)) -#define RMT_CH0_ERR_INT_CLR_M (BIT(4)) -#define RMT_CH0_ERR_INT_CLR_V 0x1 -#define RMT_CH0_ERR_INT_CLR_S 4 +/*description: .*/ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_V 0x1 +#define RMT_CH0_ERR_INT_CLR_S 4 /* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_TX_END_INT_CLR (BIT(3)) -#define RMT_CH3_TX_END_INT_CLR_M (BIT(3)) -#define RMT_CH3_TX_END_INT_CLR_V 0x1 -#define RMT_CH3_TX_END_INT_CLR_S 3 +/*description: .*/ +#define RMT_CH3_TX_END_INT_CLR (BIT(3)) +#define RMT_CH3_TX_END_INT_CLR_M (BIT(3)) +#define RMT_CH3_TX_END_INT_CLR_V 0x1 +#define RMT_CH3_TX_END_INT_CLR_S 3 /* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_TX_END_INT_CLR (BIT(2)) -#define RMT_CH2_TX_END_INT_CLR_M (BIT(2)) -#define RMT_CH2_TX_END_INT_CLR_V 0x1 -#define RMT_CH2_TX_END_INT_CLR_S 2 +/*description: .*/ +#define RMT_CH2_TX_END_INT_CLR (BIT(2)) +#define RMT_CH2_TX_END_INT_CLR_M (BIT(2)) +#define RMT_CH2_TX_END_INT_CLR_V 0x1 +#define RMT_CH2_TX_END_INT_CLR_S 2 /* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_CLR (BIT(1)) -#define RMT_CH1_TX_END_INT_CLR_M (BIT(1)) -#define RMT_CH1_TX_END_INT_CLR_V 0x1 -#define RMT_CH1_TX_END_INT_CLR_S 1 +/*description: .*/ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_V 0x1 +#define RMT_CH1_TX_END_INT_CLR_S 1 /* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_CLR (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_V 0x1 -#define RMT_CH0_TX_END_INT_CLR_S 0 +/*description: .*/ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_V 0x1 +#define RMT_CH0_TX_END_INT_CLR_S 0 -#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0080) +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x80) /* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFF -#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V) << (RMT_CARRIER_HIGH_CH0_S)) -#define RMT_CARRIER_HIGH_CH0_V 0xFFFF -#define RMT_CARRIER_HIGH_CH0_S 16 +/*description: .*/ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) +#define RMT_CARRIER_HIGH_CH0_V 0xFFFF +#define RMT_CARRIER_HIGH_CH0_S 16 /* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH0 0x0000FFFF -#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V) << (RMT_CARRIER_LOW_CH0_S)) -#define RMT_CARRIER_LOW_CH0_V 0xFFFF -#define RMT_CARRIER_LOW_CH0_S 0 +/*description: .*/ +#define RMT_CARRIER_LOW_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) +#define RMT_CARRIER_LOW_CH0_V 0xFFFF +#define RMT_CARRIER_LOW_CH0_S 0 -#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0084) +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x84) /* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH1 0x0000FFFF -#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V) << (RMT_CARRIER_HIGH_CH1_S)) -#define RMT_CARRIER_HIGH_CH1_V 0xFFFF -#define RMT_CARRIER_HIGH_CH1_S 16 +/*description: .*/ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) +#define RMT_CARRIER_HIGH_CH1_V 0xFFFF +#define RMT_CARRIER_HIGH_CH1_S 16 /* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH1 0x0000FFFF -#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V) << (RMT_CARRIER_LOW_CH1_S)) -#define RMT_CARRIER_LOW_CH1_V 0xFFFF -#define RMT_CARRIER_LOW_CH1_S 0 +/*description: .*/ +#define RMT_CARRIER_LOW_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) +#define RMT_CARRIER_LOW_CH1_V 0xFFFF +#define RMT_CARRIER_LOW_CH1_S 0 -#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0088) +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x88) /* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH2 0x0000FFFF -#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V) << (RMT_CARRIER_HIGH_CH2_S)) -#define RMT_CARRIER_HIGH_CH2_V 0xFFFF -#define RMT_CARRIER_HIGH_CH2_S 16 +/*description: .*/ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) +#define RMT_CARRIER_HIGH_CH2_V 0xFFFF +#define RMT_CARRIER_HIGH_CH2_S 16 /* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH2 0x0000FFFF -#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V) << (RMT_CARRIER_LOW_CH2_S)) -#define RMT_CARRIER_LOW_CH2_V 0xFFFF -#define RMT_CARRIER_LOW_CH2_S 0 +/*description: .*/ +#define RMT_CARRIER_LOW_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) +#define RMT_CARRIER_LOW_CH2_V 0xFFFF +#define RMT_CARRIER_LOW_CH2_S 0 -#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x008c) +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x8C) /* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH3 0x0000FFFF -#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V) << (RMT_CARRIER_HIGH_CH3_S)) -#define RMT_CARRIER_HIGH_CH3_V 0xFFFF -#define RMT_CARRIER_HIGH_CH3_S 16 +/*description: .*/ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) +#define RMT_CARRIER_HIGH_CH3_V 0xFFFF +#define RMT_CARRIER_HIGH_CH3_S 16 /* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH3 0x0000FFFF -#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V) << (RMT_CARRIER_LOW_CH3_S)) -#define RMT_CARRIER_LOW_CH3_V 0xFFFF -#define RMT_CARRIER_LOW_CH3_S 0 +/*description: .*/ +#define RMT_CARRIER_LOW_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) +#define RMT_CARRIER_LOW_CH3_V 0xFFFF +#define RMT_CARRIER_LOW_CH3_S 0 -#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0090) +#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x90) /* RMT_CARRIER_HIGH_THRES_CH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH4 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH4_M ((RMT_CARRIER_HIGH_THRES_CH4_V) << (RMT_CARRIER_HIGH_THRES_CH4_S)) -#define RMT_CARRIER_HIGH_THRES_CH4_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH4_S 16 +/*description: .*/ +#define RMT_CARRIER_HIGH_THRES_CH4 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH4_M ((RMT_CARRIER_HIGH_THRES_CH4_V)<<(RMT_CARRIER_HIGH_THRES_CH4_S)) +#define RMT_CARRIER_HIGH_THRES_CH4_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH4_S 16 /* RMT_CARRIER_LOW_THRES_CH4 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH4 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH4_M ((RMT_CARRIER_LOW_THRES_CH4_V) << (RMT_CARRIER_LOW_THRES_CH4_S)) -#define RMT_CARRIER_LOW_THRES_CH4_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH4_S 0 +/*description: .*/ +#define RMT_CARRIER_LOW_THRES_CH4 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH4_M ((RMT_CARRIER_LOW_THRES_CH4_V)<<(RMT_CARRIER_LOW_THRES_CH4_S)) +#define RMT_CARRIER_LOW_THRES_CH4_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH4_S 0 -#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0094) +#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x94) /* RMT_CARRIER_HIGH_THRES_CH5 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH5 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH5_M ((RMT_CARRIER_HIGH_THRES_CH5_V) << (RMT_CARRIER_HIGH_THRES_CH5_S)) -#define RMT_CARRIER_HIGH_THRES_CH5_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH5_S 16 +/*description: .*/ +#define RMT_CARRIER_HIGH_THRES_CH5 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH5_M ((RMT_CARRIER_HIGH_THRES_CH5_V)<<(RMT_CARRIER_HIGH_THRES_CH5_S)) +#define RMT_CARRIER_HIGH_THRES_CH5_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH5_S 16 /* RMT_CARRIER_LOW_THRES_CH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH5 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH5_M ((RMT_CARRIER_LOW_THRES_CH5_V) << (RMT_CARRIER_LOW_THRES_CH5_S)) -#define RMT_CARRIER_LOW_THRES_CH5_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH5_S 0 +/*description: .*/ +#define RMT_CARRIER_LOW_THRES_CH5 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH5_M ((RMT_CARRIER_LOW_THRES_CH5_V)<<(RMT_CARRIER_LOW_THRES_CH5_S)) +#define RMT_CARRIER_LOW_THRES_CH5_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH5_S 0 -#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0098) +#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x98) /* RMT_CARRIER_HIGH_THRES_CH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH6 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH6_M ((RMT_CARRIER_HIGH_THRES_CH6_V) << (RMT_CARRIER_HIGH_THRES_CH6_S)) -#define RMT_CARRIER_HIGH_THRES_CH6_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH6_S 16 +/*description: .*/ +#define RMT_CARRIER_HIGH_THRES_CH6 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH6_M ((RMT_CARRIER_HIGH_THRES_CH6_V)<<(RMT_CARRIER_HIGH_THRES_CH6_S)) +#define RMT_CARRIER_HIGH_THRES_CH6_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH6_S 16 /* RMT_CARRIER_LOW_THRES_CH6 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH6 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH6_M ((RMT_CARRIER_LOW_THRES_CH6_V) << (RMT_CARRIER_LOW_THRES_CH6_S)) -#define RMT_CARRIER_LOW_THRES_CH6_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH6_S 0 +/*description: .*/ +#define RMT_CARRIER_LOW_THRES_CH6 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH6_M ((RMT_CARRIER_LOW_THRES_CH6_V)<<(RMT_CARRIER_LOW_THRES_CH6_S)) +#define RMT_CARRIER_LOW_THRES_CH6_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH6_S 0 -#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x009c) +#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x9C) /* RMT_CARRIER_HIGH_THRES_CH7 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH7 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH7_M ((RMT_CARRIER_HIGH_THRES_CH7_V) << (RMT_CARRIER_HIGH_THRES_CH7_S)) -#define RMT_CARRIER_HIGH_THRES_CH7_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH7_S 16 +/*description: .*/ +#define RMT_CARRIER_HIGH_THRES_CH7 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH7_M ((RMT_CARRIER_HIGH_THRES_CH7_V)<<(RMT_CARRIER_HIGH_THRES_CH7_S)) +#define RMT_CARRIER_HIGH_THRES_CH7_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH7_S 16 /* RMT_CARRIER_LOW_THRES_CH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH7 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH7_M ((RMT_CARRIER_LOW_THRES_CH7_V) << (RMT_CARRIER_LOW_THRES_CH7_S)) -#define RMT_CARRIER_LOW_THRES_CH7_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH7_S 0 +/*description: .*/ +#define RMT_CARRIER_LOW_THRES_CH7 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH7_M ((RMT_CARRIER_LOW_THRES_CH7_V)<<(RMT_CARRIER_LOW_THRES_CH7_S)) +#define RMT_CARRIER_LOW_THRES_CH7_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH7_S 0 -#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a0) +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0xA0) +/* RMT_LOOP_STOP_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_LOOP_STOP_EN_CH0 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH0_M (BIT(21)) +#define RMT_LOOP_STOP_EN_CH0_V 0x1 +#define RMT_LOOP_STOP_EN_CH0_S 21 /* RMT_LOOP_COUNT_RESET_CH0 : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/*description: .*/ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH0_S 20 /* RMT_TX_LOOP_CNT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/*description: .*/ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 /* RMT_TX_LOOP_NUM_CH0 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH0 0x000003FF -#define RMT_TX_LOOP_NUM_CH0_M ((RMT_TX_LOOP_NUM_CH0_V) << (RMT_TX_LOOP_NUM_CH0_S)) -#define RMT_TX_LOOP_NUM_CH0_V 0x3FF -#define RMT_TX_LOOP_NUM_CH0_S 9 +/*description: .*/ +#define RMT_TX_LOOP_NUM_CH0 0x000003FF +#define RMT_TX_LOOP_NUM_CH0_M ((RMT_TX_LOOP_NUM_CH0_V)<<(RMT_TX_LOOP_NUM_CH0_S)) +#define RMT_TX_LOOP_NUM_CH0_V 0x3FF +#define RMT_TX_LOOP_NUM_CH0_S 9 /* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH0 0x000001FF -#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V) << (RMT_TX_LIM_CH0_S)) -#define RMT_TX_LIM_CH0_V 0x1FF -#define RMT_TX_LIM_CH0_S 0 +/*description: .*/ +#define RMT_TX_LIM_CH0 0x000001FF +#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) +#define RMT_TX_LIM_CH0_V 0x1FF +#define RMT_TX_LIM_CH0_S 0 -#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a4) +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0xA4) +/* RMT_LOOP_STOP_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_LOOP_STOP_EN_CH1 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH1_M (BIT(21)) +#define RMT_LOOP_STOP_EN_CH1_V 0x1 +#define RMT_LOOP_STOP_EN_CH1_S 21 /* RMT_LOOP_COUNT_RESET_CH1 : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH1_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH1_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/*description: .*/ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH1_S 20 /* RMT_TX_LOOP_CNT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH1_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH1_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/*description: .*/ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 /* RMT_TX_LOOP_NUM_CH1 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH1 0x000003FF -#define RMT_TX_LOOP_NUM_CH1_M ((RMT_TX_LOOP_NUM_CH1_V) << (RMT_TX_LOOP_NUM_CH1_S)) -#define RMT_TX_LOOP_NUM_CH1_V 0x3FF -#define RMT_TX_LOOP_NUM_CH1_S 9 +/*description: .*/ +#define RMT_TX_LOOP_NUM_CH1 0x000003FF +#define RMT_TX_LOOP_NUM_CH1_M ((RMT_TX_LOOP_NUM_CH1_V)<<(RMT_TX_LOOP_NUM_CH1_S)) +#define RMT_TX_LOOP_NUM_CH1_V 0x3FF +#define RMT_TX_LOOP_NUM_CH1_S 9 /* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH1 0x000001FF -#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V) << (RMT_TX_LIM_CH1_S)) -#define RMT_TX_LIM_CH1_V 0x1FF -#define RMT_TX_LIM_CH1_S 0 +/*description: .*/ +#define RMT_TX_LIM_CH1 0x000001FF +#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) +#define RMT_TX_LIM_CH1_V 0x1FF +#define RMT_TX_LIM_CH1_S 0 -#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a8) +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0xA8) +/* RMT_LOOP_STOP_EN_CH2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_LOOP_STOP_EN_CH2 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH2_M (BIT(21)) +#define RMT_LOOP_STOP_EN_CH2_V 0x1 +#define RMT_LOOP_STOP_EN_CH2_S 21 /* RMT_LOOP_COUNT_RESET_CH2 : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH2_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH2_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH2_S 20 +/*description: .*/ +#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH2_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH2_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH2_S 20 /* RMT_TX_LOOP_CNT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH2_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH2_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH2_S 19 +/*description: .*/ +#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH2_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH2_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH2_S 19 /* RMT_TX_LOOP_NUM_CH2 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH2 0x000003FF -#define RMT_TX_LOOP_NUM_CH2_M ((RMT_TX_LOOP_NUM_CH2_V) << (RMT_TX_LOOP_NUM_CH2_S)) -#define RMT_TX_LOOP_NUM_CH2_V 0x3FF -#define RMT_TX_LOOP_NUM_CH2_S 9 +/*description: .*/ +#define RMT_TX_LOOP_NUM_CH2 0x000003FF +#define RMT_TX_LOOP_NUM_CH2_M ((RMT_TX_LOOP_NUM_CH2_V)<<(RMT_TX_LOOP_NUM_CH2_S)) +#define RMT_TX_LOOP_NUM_CH2_V 0x3FF +#define RMT_TX_LOOP_NUM_CH2_S 9 /* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH2 0x000001FF -#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V) << (RMT_TX_LIM_CH2_S)) -#define RMT_TX_LIM_CH2_V 0x1FF -#define RMT_TX_LIM_CH2_S 0 +/*description: .*/ +#define RMT_TX_LIM_CH2 0x000001FF +#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) +#define RMT_TX_LIM_CH2_V 0x1FF +#define RMT_TX_LIM_CH2_S 0 -#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ac) +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0xAC) +/* RMT_LOOP_STOP_EN_CH3 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define RMT_LOOP_STOP_EN_CH3 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH3_M (BIT(21)) +#define RMT_LOOP_STOP_EN_CH3_V 0x1 +#define RMT_LOOP_STOP_EN_CH3_S 21 /* RMT_LOOP_COUNT_RESET_CH3 : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH3_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH3_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH3_S 20 +/*description: .*/ +#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH3_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH3_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH3_S 20 /* RMT_TX_LOOP_CNT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH3_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH3_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH3_S 19 +/*description: .*/ +#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH3_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH3_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH3_S 19 /* RMT_TX_LOOP_NUM_CH3 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH3 0x000003FF -#define RMT_TX_LOOP_NUM_CH3_M ((RMT_TX_LOOP_NUM_CH3_V) << (RMT_TX_LOOP_NUM_CH3_S)) -#define RMT_TX_LOOP_NUM_CH3_V 0x3FF -#define RMT_TX_LOOP_NUM_CH3_S 9 +/*description: .*/ +#define RMT_TX_LOOP_NUM_CH3 0x000003FF +#define RMT_TX_LOOP_NUM_CH3_M ((RMT_TX_LOOP_NUM_CH3_V)<<(RMT_TX_LOOP_NUM_CH3_S)) +#define RMT_TX_LOOP_NUM_CH3_V 0x3FF +#define RMT_TX_LOOP_NUM_CH3_S 9 /* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH3 0x000001FF -#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V) << (RMT_TX_LIM_CH3_S)) -#define RMT_TX_LIM_CH3_V 0x1FF -#define RMT_TX_LIM_CH3_S 0 +/*description: .*/ +#define RMT_TX_LIM_CH3 0x000001FF +#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) +#define RMT_TX_LIM_CH3_V 0x1FF +#define RMT_TX_LIM_CH3_S 0 -#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b0) +#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0xB0) /* RMT_RX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH4 0x000001FF -#define RMT_RX_LIM_CH4_M ((RMT_RX_LIM_CH4_V) << (RMT_RX_LIM_CH4_S)) -#define RMT_RX_LIM_CH4_V 0x1FF -#define RMT_RX_LIM_CH4_S 0 +/*description: .*/ +#define RMT_RX_LIM_CH4 0x000001FF +#define RMT_RX_LIM_CH4_M ((RMT_RX_LIM_CH4_V)<<(RMT_RX_LIM_CH4_S)) +#define RMT_RX_LIM_CH4_V 0x1FF +#define RMT_RX_LIM_CH4_S 0 -#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b4) +#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0xB4) /* RMT_RX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH5 0x000001FF -#define RMT_RX_LIM_CH5_M ((RMT_RX_LIM_CH5_V) << (RMT_RX_LIM_CH5_S)) -#define RMT_RX_LIM_CH5_V 0x1FF -#define RMT_RX_LIM_CH5_S 0 +/*description: .*/ +#define RMT_RX_LIM_CH5 0x000001FF +#define RMT_RX_LIM_CH5_M ((RMT_RX_LIM_CH5_V)<<(RMT_RX_LIM_CH5_S)) +#define RMT_RX_LIM_CH5_V 0x1FF +#define RMT_RX_LIM_CH5_S 0 -#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b8) +#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0xB8) /* RMT_RX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH6 0x000001FF -#define RMT_RX_LIM_CH6_M ((RMT_RX_LIM_CH6_V) << (RMT_RX_LIM_CH6_S)) -#define RMT_RX_LIM_CH6_V 0x1FF -#define RMT_RX_LIM_CH6_S 0 +/*description: .*/ +#define RMT_RX_LIM_CH6 0x000001FF +#define RMT_RX_LIM_CH6_M ((RMT_RX_LIM_CH6_V)<<(RMT_RX_LIM_CH6_S)) +#define RMT_RX_LIM_CH6_V 0x1FF +#define RMT_RX_LIM_CH6_S 0 -#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0x00bc) +#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0xBC) /* RMT_RX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH7 0x000001FF -#define RMT_RX_LIM_CH7_M ((RMT_RX_LIM_CH7_V) << (RMT_RX_LIM_CH7_S)) -#define RMT_RX_LIM_CH7_V 0x1FF -#define RMT_RX_LIM_CH7_S 0 +/*description: .*/ +#define RMT_RX_LIM_CH7 0x000001FF +#define RMT_RX_LIM_CH7_M ((RMT_RX_LIM_CH7_V)<<(RMT_RX_LIM_CH7_S)) +#define RMT_RX_LIM_CH7_V 0x1FF +#define RMT_RX_LIM_CH7_S 0 -#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x00c0) +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0xC0) /* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define RMT_CLK_EN (BIT(31)) -#define RMT_CLK_EN_M (BIT(31)) -#define RMT_CLK_EN_V 0x1 -#define RMT_CLK_EN_S 31 +/*description: .*/ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (BIT(31)) +#define RMT_CLK_EN_V 0x1 +#define RMT_CLK_EN_S 31 /* RMT_SCLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'h1 ; */ -/*description: */ -#define RMT_SCLK_ACTIVE (BIT(26)) -#define RMT_SCLK_ACTIVE_M (BIT(26)) -#define RMT_SCLK_ACTIVE_V 0x1 -#define RMT_SCLK_ACTIVE_S 26 +/*description: .*/ +#define RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_SCLK_ACTIVE_M (BIT(26)) +#define RMT_SCLK_ACTIVE_V 0x1 +#define RMT_SCLK_ACTIVE_S 26 /* RMT_SCLK_SEL : R/W ;bitpos:[25:24] ;default: 2'h1 ; */ -/*description: */ -#define RMT_SCLK_SEL 0x00000003 -#define RMT_SCLK_SEL_M ((RMT_SCLK_SEL_V) << (RMT_SCLK_SEL_S)) -#define RMT_SCLK_SEL_V 0x3 -#define RMT_SCLK_SEL_S 24 +/*description: .*/ +#define RMT_SCLK_SEL 0x00000003 +#define RMT_SCLK_SEL_M ((RMT_SCLK_SEL_V)<<(RMT_SCLK_SEL_S)) +#define RMT_SCLK_SEL_V 0x3 +#define RMT_SCLK_SEL_S 24 /* RMT_SCLK_DIV_B : R/W ;bitpos:[23:18] ;default: 6'h0 ; */ -/*description: */ -#define RMT_SCLK_DIV_B 0x0000003F -#define RMT_SCLK_DIV_B_M ((RMT_SCLK_DIV_B_V) << (RMT_SCLK_DIV_B_S)) -#define RMT_SCLK_DIV_B_V 0x3F -#define RMT_SCLK_DIV_B_S 18 +/*description: .*/ +#define RMT_SCLK_DIV_B 0x0000003F +#define RMT_SCLK_DIV_B_M ((RMT_SCLK_DIV_B_V)<<(RMT_SCLK_DIV_B_S)) +#define RMT_SCLK_DIV_B_V 0x3F +#define RMT_SCLK_DIV_B_S 18 /* RMT_SCLK_DIV_A : R/W ;bitpos:[17:12] ;default: 6'h0 ; */ -/*description: */ -#define RMT_SCLK_DIV_A 0x0000003F -#define RMT_SCLK_DIV_A_M ((RMT_SCLK_DIV_A_V) << (RMT_SCLK_DIV_A_S)) -#define RMT_SCLK_DIV_A_V 0x3F -#define RMT_SCLK_DIV_A_S 12 +/*description: .*/ +#define RMT_SCLK_DIV_A 0x0000003F +#define RMT_SCLK_DIV_A_M ((RMT_SCLK_DIV_A_V)<<(RMT_SCLK_DIV_A_S)) +#define RMT_SCLK_DIV_A_V 0x3F +#define RMT_SCLK_DIV_A_S 12 /* RMT_SCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h1 ; */ -/*description: */ -#define RMT_SCLK_DIV_NUM 0x000000FF -#define RMT_SCLK_DIV_NUM_M ((RMT_SCLK_DIV_NUM_V) << (RMT_SCLK_DIV_NUM_S)) -#define RMT_SCLK_DIV_NUM_V 0xFF -#define RMT_SCLK_DIV_NUM_S 4 +/*description: .*/ +#define RMT_SCLK_DIV_NUM 0x000000FF +#define RMT_SCLK_DIV_NUM_M ((RMT_SCLK_DIV_NUM_V)<<(RMT_SCLK_DIV_NUM_S)) +#define RMT_SCLK_DIV_NUM_V 0xFF +#define RMT_SCLK_DIV_NUM_S 4 /* RMT_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FORCE_PU (BIT(3)) -#define RMT_MEM_FORCE_PU_M (BIT(3)) -#define RMT_MEM_FORCE_PU_V 0x1 -#define RMT_MEM_FORCE_PU_S 3 +/*description: .*/ +#define RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_MEM_FORCE_PU_M (BIT(3)) +#define RMT_MEM_FORCE_PU_V 0x1 +#define RMT_MEM_FORCE_PU_S 3 /* RMT_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FORCE_PD (BIT(2)) -#define RMT_MEM_FORCE_PD_M (BIT(2)) -#define RMT_MEM_FORCE_PD_V 0x1 -#define RMT_MEM_FORCE_PD_S 2 +/*description: .*/ +#define RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_MEM_FORCE_PD_M (BIT(2)) +#define RMT_MEM_FORCE_PD_V 0x1 +#define RMT_MEM_FORCE_PD_S 2 /* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_CLK_FORCE_ON (BIT(1)) -#define RMT_MEM_CLK_FORCE_ON_M (BIT(1)) -#define RMT_MEM_CLK_FORCE_ON_V 0x1 -#define RMT_MEM_CLK_FORCE_ON_S 1 +/*description: .*/ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_V 0x1 +#define RMT_MEM_CLK_FORCE_ON_S 1 /* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_APB_FIFO_MASK (BIT(0)) -#define RMT_APB_FIFO_MASK_M (BIT(0)) -#define RMT_APB_FIFO_MASK_V 0x1 -#define RMT_APB_FIFO_MASK_S 0 +/*description: .*/ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (BIT(0)) +#define RMT_APB_FIFO_MASK_V 0x1 +#define RMT_APB_FIFO_MASK_S 0 -#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x00c4) +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0xC4) /* RMT_TX_SIM_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_EN (BIT(4)) -#define RMT_TX_SIM_EN_M (BIT(4)) -#define RMT_TX_SIM_EN_V 0x1 -#define RMT_TX_SIM_EN_S 4 +/*description: .*/ +#define RMT_TX_SIM_EN (BIT(4)) +#define RMT_TX_SIM_EN_M (BIT(4)) +#define RMT_TX_SIM_EN_V 0x1 +#define RMT_TX_SIM_EN_S 4 /* RMT_TX_SIM_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH3 (BIT(3)) -#define RMT_TX_SIM_CH3_M (BIT(3)) -#define RMT_TX_SIM_CH3_V 0x1 -#define RMT_TX_SIM_CH3_S 3 +/*description: .*/ +#define RMT_TX_SIM_CH3 (BIT(3)) +#define RMT_TX_SIM_CH3_M (BIT(3)) +#define RMT_TX_SIM_CH3_V 0x1 +#define RMT_TX_SIM_CH3_S 3 /* RMT_TX_SIM_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH2 (BIT(2)) -#define RMT_TX_SIM_CH2_M (BIT(2)) -#define RMT_TX_SIM_CH2_V 0x1 -#define RMT_TX_SIM_CH2_S 2 +/*description: .*/ +#define RMT_TX_SIM_CH2 (BIT(2)) +#define RMT_TX_SIM_CH2_M (BIT(2)) +#define RMT_TX_SIM_CH2_V 0x1 +#define RMT_TX_SIM_CH2_S 2 /* RMT_TX_SIM_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH1 (BIT(1)) -#define RMT_TX_SIM_CH1_M (BIT(1)) -#define RMT_TX_SIM_CH1_V 0x1 -#define RMT_TX_SIM_CH1_S 1 +/*description: .*/ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (BIT(1)) +#define RMT_TX_SIM_CH1_V 0x1 +#define RMT_TX_SIM_CH1_S 1 /* RMT_TX_SIM_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH0 (BIT(0)) -#define RMT_TX_SIM_CH0_M (BIT(0)) -#define RMT_TX_SIM_CH0_V 0x1 -#define RMT_TX_SIM_CH0_S 0 +/*description: .*/ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (BIT(0)) +#define RMT_TX_SIM_CH0_V 0x1 +#define RMT_TX_SIM_CH0_S 0 -#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x00c8) +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0xC8) /* RMT_REF_CNT_RST_CH7 : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH7 (BIT(7)) -#define RMT_REF_CNT_RST_CH7_M (BIT(7)) -#define RMT_REF_CNT_RST_CH7_V 0x1 -#define RMT_REF_CNT_RST_CH7_S 7 +/*description: .*/ +#define RMT_REF_CNT_RST_CH7 (BIT(7)) +#define RMT_REF_CNT_RST_CH7_M (BIT(7)) +#define RMT_REF_CNT_RST_CH7_V 0x1 +#define RMT_REF_CNT_RST_CH7_S 7 /* RMT_REF_CNT_RST_CH6 : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH6 (BIT(6)) -#define RMT_REF_CNT_RST_CH6_M (BIT(6)) -#define RMT_REF_CNT_RST_CH6_V 0x1 -#define RMT_REF_CNT_RST_CH6_S 6 +/*description: .*/ +#define RMT_REF_CNT_RST_CH6 (BIT(6)) +#define RMT_REF_CNT_RST_CH6_M (BIT(6)) +#define RMT_REF_CNT_RST_CH6_V 0x1 +#define RMT_REF_CNT_RST_CH6_S 6 /* RMT_REF_CNT_RST_CH5 : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH5 (BIT(5)) -#define RMT_REF_CNT_RST_CH5_M (BIT(5)) -#define RMT_REF_CNT_RST_CH5_V 0x1 -#define RMT_REF_CNT_RST_CH5_S 5 +/*description: .*/ +#define RMT_REF_CNT_RST_CH5 (BIT(5)) +#define RMT_REF_CNT_RST_CH5_M (BIT(5)) +#define RMT_REF_CNT_RST_CH5_V 0x1 +#define RMT_REF_CNT_RST_CH5_S 5 /* RMT_REF_CNT_RST_CH4 : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH4 (BIT(4)) -#define RMT_REF_CNT_RST_CH4_M (BIT(4)) -#define RMT_REF_CNT_RST_CH4_V 0x1 -#define RMT_REF_CNT_RST_CH4_S 4 +/*description: .*/ +#define RMT_REF_CNT_RST_CH4 (BIT(4)) +#define RMT_REF_CNT_RST_CH4_M (BIT(4)) +#define RMT_REF_CNT_RST_CH4_V 0x1 +#define RMT_REF_CNT_RST_CH4_S 4 /* RMT_REF_CNT_RST_CH3 : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH3 (BIT(3)) -#define RMT_REF_CNT_RST_CH3_M (BIT(3)) -#define RMT_REF_CNT_RST_CH3_V 0x1 -#define RMT_REF_CNT_RST_CH3_S 3 +/*description: .*/ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (BIT(3)) +#define RMT_REF_CNT_RST_CH3_V 0x1 +#define RMT_REF_CNT_RST_CH3_S 3 /* RMT_REF_CNT_RST_CH2 : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH2 (BIT(2)) -#define RMT_REF_CNT_RST_CH2_M (BIT(2)) -#define RMT_REF_CNT_RST_CH2_V 0x1 -#define RMT_REF_CNT_RST_CH2_S 2 +/*description: .*/ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (BIT(2)) +#define RMT_REF_CNT_RST_CH2_V 0x1 +#define RMT_REF_CNT_RST_CH2_S 2 /* RMT_REF_CNT_RST_CH1 : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH1 (BIT(1)) -#define RMT_REF_CNT_RST_CH1_M (BIT(1)) -#define RMT_REF_CNT_RST_CH1_V 0x1 -#define RMT_REF_CNT_RST_CH1_S 1 +/*description: .*/ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (BIT(1)) +#define RMT_REF_CNT_RST_CH1_V 0x1 +#define RMT_REF_CNT_RST_CH1_S 1 /* RMT_REF_CNT_RST_CH0 : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH0 (BIT(0)) -#define RMT_REF_CNT_RST_CH0_M (BIT(0)) -#define RMT_REF_CNT_RST_CH0_V 0x1 -#define RMT_REF_CNT_RST_CH0_S 0 +/*description: .*/ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (BIT(0)) +#define RMT_REF_CNT_RST_CH0_V 0x1 +#define RMT_REF_CNT_RST_CH0_S 0 + +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xCC) +/* RMT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101181 ; */ +/*description: .*/ +#define RMT_DATE 0x0FFFFFFF +#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) +#define RMT_DATE_V 0xFFFFFFF +#define RMT_DATE_S 0 -#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00cc) -/* RMT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003041 ; */ -/*description: */ -#define RMT_DATE 0x0FFFFFFF -#define RMT_DATE_M ((RMT_DATE_V) << (RMT_DATE_S)) -#define RMT_DATE_V 0xFFFFFFF -#define RMT_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_RMT_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/rmt_struct.h b/components/soc/esp32s3/include/soc/rmt_struct.h index 044a5d14bd..682408c0f4 100644 --- a/components/soc/esp32s3/include/soc/rmt_struct.h +++ b/components/soc/esp32s3/include/soc/rmt_struct.h @@ -11,305 +11,315 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_RMT_STRUCT_H_ +#define _SOC_RMT_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { uint32_t data_ch[8]; union { struct { - uint32_t tx_start : 1; - uint32_t mem_rd_rst : 1; - uint32_t apb_mem_rst : 1; - uint32_t tx_conti_mode : 1; - uint32_t mem_tx_wrap_en : 1; - uint32_t idle_out_lv : 1; - uint32_t idle_out_en : 1; - uint32_t tx_stop : 1; - uint32_t div_cnt : 8; - uint32_t mem_size : 4; - uint32_t carrier_eff_en : 1; - uint32_t carrier_en : 1; - uint32_t carrier_out_lv : 1; - uint32_t afifo_rst : 1; - uint32_t conf_update : 1; - uint32_t reserved25 : 7; + uint32_t tx_start : 1; + uint32_t mem_rd_rst : 1; + uint32_t mem_rst : 1; + uint32_t tx_conti_mode : 1; + uint32_t mem_tx_wrap_en : 1; + uint32_t idle_out_lv : 1; + uint32_t idle_out_en : 1; + uint32_t tx_stop : 1; + uint32_t div_cnt : 8; + uint32_t mem_size : 4; + uint32_t carrier_eff_en : 1; + uint32_t carrier_en : 1; + uint32_t carrier_out_lv : 1; + uint32_t afifo_rst : 1; + uint32_t conf_update : 1; + uint32_t reserved25 : 7; }; uint32_t val; } tx_conf[4]; struct { union { struct { - uint32_t div_cnt : 8; - uint32_t idle_thres : 15; - uint32_t reserved23 : 1; - uint32_t mem_size : 4; - uint32_t carrier_en : 1; - uint32_t carrier_out_lv : 1; - uint32_t reserved30 : 2; + uint32_t div_cnt : 8; + uint32_t idle_thres : 15; + uint32_t reserved23 : 1; + uint32_t mem_size : 4; + uint32_t carrier_en : 1; + uint32_t carrier_out_lv : 1; + uint32_t reserved30 : 2; }; uint32_t val; } conf0; union { struct { - uint32_t rx_en : 1; - uint32_t mem_wr_rst : 1; - uint32_t apb_mem_rst : 1; - uint32_t mem_owner : 1; - uint32_t rx_filter_en : 1; - uint32_t rx_filter_thres : 8; - uint32_t mem_rx_wrap_en : 1; - uint32_t afifo_rst : 1; - uint32_t conf_update : 1; - uint32_t reserved16 : 16; + uint32_t rx_en : 1; + uint32_t mem_wr_rst : 1; + uint32_t mem_rst : 1; + uint32_t mem_owner : 1; + uint32_t rx_filter_en : 1; + uint32_t rx_filter_thres : 8; + uint32_t mem_rx_wrap_en : 1; + uint32_t afifo_rst : 1; + uint32_t conf_update : 1; + uint32_t reserved16 : 16; }; uint32_t val; } conf1; } rx_conf[4]; union { struct { - uint32_t mem_raddr_ex : 10; - uint32_t reserved10 : 1; - uint32_t apb_mem_waddr : 10; - uint32_t reserved21 : 1; - uint32_t state : 3; - uint32_t mem_empty : 1; - uint32_t apb_mem_wr_err : 1; - uint32_t reserved27 : 5; + uint32_t mem_raddr_ex : 10; + uint32_t reserved10 : 1; + uint32_t mem_waddr : 10; + uint32_t reserved21 : 1; + uint32_t state : 3; + uint32_t mem_empty : 1; + uint32_t mem_wr_err : 1; + uint32_t reserved27 : 5; }; uint32_t val; } tx_status[4]; union { struct { - uint32_t mem_waddr_ex : 10; - uint32_t reserved10 : 1; - uint32_t apb_mem_raddr : 10; - uint32_t reserved21 : 1; - uint32_t state : 3; - uint32_t mem_owner_err : 1; - uint32_t mem_full : 1; - uint32_t apb_mem_rd_err : 1; - uint32_t reserved27 : 4; + uint32_t mem_waddr_ex : 10; + uint32_t reserved10 : 1; + uint32_t mem_raddr : 10; + uint32_t reserved21 : 1; + uint32_t state : 3; + uint32_t mem_owner_err : 1; + uint32_t mem_full : 1; + uint32_t mem_rd_err : 1; + uint32_t reserved28 : 4; }; uint32_t val; } rx_status[4]; union { struct { - uint32_t ch0_tx_end : 1; - uint32_t ch1_tx_end : 1; - uint32_t ch2_tx_end : 1; - uint32_t ch3_tx_end : 1; - uint32_t ch0_err : 1; - uint32_t ch1_err : 1; - uint32_t ch2_err : 1; - uint32_t ch3_err : 1; - uint32_t ch0_tx_thr_event : 1; - uint32_t ch1_tx_thr_event : 1; - uint32_t ch2_tx_thr_event : 1; - uint32_t ch3_tx_thr_event : 1; - uint32_t ch0_tx_loop : 1; - uint32_t ch1_tx_loop : 1; - uint32_t ch2_tx_loop : 1; - uint32_t ch3_tx_loop : 1; - uint32_t ch4_rx_end : 1; - uint32_t ch5_rx_end : 1; - uint32_t ch6_rx_end : 1; - uint32_t ch7_rx_end : 1; - uint32_t ch4_err : 1; - uint32_t ch5_err : 1; - uint32_t ch6_err : 1; - uint32_t ch7_err : 1; - uint32_t ch4_rx_thr_event : 1; - uint32_t ch5_rx_thr_event : 1; - uint32_t ch6_rx_thr_event : 1; - uint32_t ch7_rx_thr_event : 1; - uint32_t reserved28 : 4; + uint32_t ch0_tx_end : 1; + uint32_t ch1_tx_end : 1; + uint32_t ch2_tx_end : 1; + uint32_t ch3_tx_end : 1; + uint32_t ch0_err : 1; + uint32_t ch1_err : 1; + uint32_t ch2_err : 1; + uint32_t ch3_err : 1; + uint32_t ch0_tx_thr_event : 1; + uint32_t ch1_tx_thr_event : 1; + uint32_t ch2_tx_thr_event : 1; + uint32_t ch3_tx_thr_event : 1; + uint32_t ch0_tx_loop : 1; + uint32_t ch1_tx_loop : 1; + uint32_t ch2_tx_loop : 1; + uint32_t ch3_tx_loop : 1; + uint32_t ch4_rx_end : 1; + uint32_t ch5_rx_end : 1; + uint32_t ch6_rx_end : 1; + uint32_t ch7_rx_end : 1; + uint32_t ch4_err : 1; + uint32_t ch5_err : 1; + uint32_t ch6_err : 1; + uint32_t ch7_err : 1; + uint32_t ch4_rx_thr_event : 1; + uint32_t ch5_rx_thr_event : 1; + uint32_t ch6_rx_thr_event : 1; + uint32_t ch7_rx_thr_event : 1; + uint32_t ch3_dma_access_fail : 1; + uint32_t ch7_dma_access_fail : 1; + uint32_t reserved30 : 2; }; uint32_t val; } int_raw; union { struct { - uint32_t ch0_tx_end : 1; - uint32_t ch1_tx_end : 1; - uint32_t ch2_tx_end : 1; - uint32_t ch3_tx_end : 1; - uint32_t ch0_err : 1; - uint32_t ch1_err : 1; - uint32_t ch2_err : 1; - uint32_t ch3_err : 1; - uint32_t ch0_tx_thr_event : 1; - uint32_t ch1_tx_thr_event : 1; - uint32_t ch2_tx_thr_event : 1; - uint32_t ch3_tx_thr_event : 1; - uint32_t ch0_tx_loop : 1; - uint32_t ch1_tx_loop : 1; - uint32_t ch2_tx_loop : 1; - uint32_t ch3_tx_loop : 1; - uint32_t ch4_rx_end : 1; - uint32_t ch5_rx_end : 1; - uint32_t ch6_rx_end : 1; - uint32_t ch7_rx_end : 1; - uint32_t ch4_err : 1; - uint32_t ch5_err : 1; - uint32_t ch6_err : 1; - uint32_t ch7_err : 1; - uint32_t ch4_rx_thr_event : 1; - uint32_t ch5_rx_thr_event : 1; - uint32_t ch6_rx_thr_event : 1; - uint32_t ch7_rx_thr_event : 1; - uint32_t reserved28 : 4; + uint32_t ch0_tx_end : 1; + uint32_t ch1_tx_end : 1; + uint32_t ch2_tx_end : 1; + uint32_t ch3_tx_end : 1; + uint32_t ch0_err : 1; + uint32_t ch1_err : 1; + uint32_t ch2_err : 1; + uint32_t ch3_err : 1; + uint32_t ch0_tx_thr_event : 1; + uint32_t ch1_tx_thr_event : 1; + uint32_t ch2_tx_thr_event : 1; + uint32_t ch3_tx_thr_event : 1; + uint32_t ch0_tx_loop : 1; + uint32_t ch1_tx_loop : 1; + uint32_t ch2_tx_loop : 1; + uint32_t ch3_tx_loop : 1; + uint32_t ch4_rx_end : 1; + uint32_t ch5_rx_end : 1; + uint32_t ch6_rx_end : 1; + uint32_t ch7_rx_end : 1; + uint32_t ch4_err : 1; + uint32_t ch5_err : 1; + uint32_t ch6_err : 1; + uint32_t ch7_err : 1; + uint32_t ch4_rx_thr_event : 1; + uint32_t ch5_rx_thr_event : 1; + uint32_t ch6_rx_thr_event : 1; + uint32_t ch7_rx_thr_event : 1; + uint32_t ch3_dma_access_fail : 1; + uint32_t ch7_dma_access_fail : 1; + uint32_t reserved30 : 2; }; uint32_t val; } int_st; union { struct { - uint32_t ch0_tx_end : 1; - uint32_t ch1_tx_end : 1; - uint32_t ch2_tx_end : 1; - uint32_t ch3_tx_end : 1; - uint32_t ch0_err : 1; - uint32_t ch1_err : 1; - uint32_t ch2_err : 1; - uint32_t ch3_err : 1; - uint32_t ch0_tx_thr_event : 1; - uint32_t ch1_tx_thr_event : 1; - uint32_t ch2_tx_thr_event : 1; - uint32_t ch3_tx_thr_event : 1; - uint32_t ch0_tx_loop : 1; - uint32_t ch1_tx_loop : 1; - uint32_t ch2_tx_loop : 1; - uint32_t ch3_tx_loop : 1; - uint32_t ch4_rx_end : 1; - uint32_t ch5_rx_end : 1; - uint32_t ch6_rx_end : 1; - uint32_t ch7_rx_end : 1; - uint32_t ch4_err : 1; - uint32_t ch5_err : 1; - uint32_t ch6_err : 1; - uint32_t ch7_err : 1; - uint32_t ch4_rx_thr_event : 1; - uint32_t ch5_rx_thr_event : 1; - uint32_t ch6_rx_thr_event : 1; - uint32_t ch7_rx_thr_event : 1; - uint32_t reserved28 : 4; + uint32_t ch0_tx_end : 1; + uint32_t ch1_tx_end : 1; + uint32_t ch2_tx_end : 1; + uint32_t ch3_tx_end : 1; + uint32_t ch0_err : 1; + uint32_t ch1_err : 1; + uint32_t ch2_err : 1; + uint32_t ch3_err : 1; + uint32_t ch0_tx_thr_event : 1; + uint32_t ch1_tx_thr_event : 1; + uint32_t ch2_tx_thr_event : 1; + uint32_t ch3_tx_thr_event : 1; + uint32_t ch0_tx_loop : 1; + uint32_t ch1_tx_loop : 1; + uint32_t ch2_tx_loop : 1; + uint32_t ch3_tx_loop : 1; + uint32_t ch4_rx_end : 1; + uint32_t ch5_rx_end : 1; + uint32_t ch6_rx_end : 1; + uint32_t ch7_rx_end : 1; + uint32_t ch4_err : 1; + uint32_t ch5_err : 1; + uint32_t ch6_err : 1; + uint32_t ch7_err : 1; + uint32_t ch4_rx_thr_event : 1; + uint32_t ch5_rx_thr_event : 1; + uint32_t ch6_rx_thr_event : 1; + uint32_t ch7_rx_thr_event : 1; + uint32_t ch3_dma_access_fail : 1; + uint32_t ch7_dma_access_fail : 1; + uint32_t reserved30 : 2; }; uint32_t val; } int_ena; union { struct { - uint32_t ch0_tx_end : 1; - uint32_t ch1_tx_end : 1; - uint32_t ch2_tx_end : 1; - uint32_t ch3_tx_end : 1; - uint32_t ch0_err : 1; - uint32_t ch1_err : 1; - uint32_t ch2_err : 1; - uint32_t ch3_err : 1; - uint32_t ch0_tx_thr_event : 1; - uint32_t ch1_tx_thr_event : 1; - uint32_t ch2_tx_thr_event : 1; - uint32_t ch3_tx_thr_event : 1; - uint32_t ch0_tx_loop : 1; - uint32_t ch1_tx_loop : 1; - uint32_t ch2_tx_loop : 1; - uint32_t ch3_tx_loop : 1; - uint32_t ch4_rx_end : 1; - uint32_t ch5_rx_end : 1; - uint32_t ch6_rx_end : 1; - uint32_t ch7_rx_end : 1; - uint32_t ch4_err : 1; - uint32_t ch5_err : 1; - uint32_t ch6_err : 1; - uint32_t ch7_err : 1; - uint32_t ch4_rx_thr_event : 1; - uint32_t ch5_rx_thr_event : 1; - uint32_t ch6_rx_thr_event : 1; - uint32_t ch7_rx_thr_event : 1; - uint32_t reserved28 : 4; + uint32_t ch0_tx_end : 1; + uint32_t ch1_tx_end : 1; + uint32_t ch2_tx_end : 1; + uint32_t ch3_tx_end : 1; + uint32_t ch0_err : 1; + uint32_t ch1_err : 1; + uint32_t ch2_err : 1; + uint32_t ch3_err : 1; + uint32_t ch0_tx_thr_event : 1; + uint32_t ch1_tx_thr_event : 1; + uint32_t ch2_tx_thr_event : 1; + uint32_t ch3_tx_thr_event : 1; + uint32_t ch0_tx_loop : 1; + uint32_t ch1_tx_loop : 1; + uint32_t ch2_tx_loop : 1; + uint32_t ch3_tx_loop : 1; + uint32_t ch4_rx_end : 1; + uint32_t ch5_rx_end : 1; + uint32_t ch6_rx_end : 1; + uint32_t ch7_rx_end : 1; + uint32_t ch4_err : 1; + uint32_t ch5_err : 1; + uint32_t ch6_err : 1; + uint32_t ch7_err : 1; + uint32_t ch4_rx_thr_event : 1; + uint32_t ch5_rx_thr_event : 1; + uint32_t ch6_rx_thr_event : 1; + uint32_t ch7_rx_thr_event : 1; + uint32_t ch3_dma_access_fail : 1; + uint32_t ch7_dma_access_fail : 1; + uint32_t reserved30 : 2; }; uint32_t val; } int_clr; union { struct { - uint32_t low : 16; - uint32_t high : 16; + uint32_t low : 16; + uint32_t high : 16; }; uint32_t val; } tx_carrier[4]; union { struct { - uint32_t low_thres : 16; - uint32_t high_thres : 16; + uint32_t low_thres : 16; + uint32_t high_thres : 16; }; uint32_t val; } rx_carrier[4]; union { struct { - uint32_t limit : 9; - uint32_t tx_loop_num : 10; - uint32_t tx_loop_cnt_en : 1; - uint32_t loop_count_reset : 1; - uint32_t reserved21 : 11; + uint32_t limit : 9; + uint32_t tx_loop_num : 10; + uint32_t tx_loop_cnt_en : 1; + uint32_t loop_count_reset : 1; + uint32_t loop_stop_en : 1; + uint32_t reserved22 : 10; }; uint32_t val; } tx_lim[4]; union { struct { - uint32_t rx_lim : 9; - uint32_t reserved9 : 23; + uint32_t rx_lim : 9; + uint32_t reserved9 : 23; }; uint32_t val; } rx_lim[4]; union { struct { - uint32_t fifo_mask : 1; - uint32_t mem_clk_force_on : 1; - uint32_t mem_force_pd : 1; - uint32_t mem_force_pu : 1; - uint32_t sclk_div_num : 8; - uint32_t sclk_div_a : 6; - uint32_t sclk_div_b : 6; - uint32_t sclk_sel : 2; - uint32_t sclk_active : 1; - uint32_t reserved27 : 4; - uint32_t clk_en : 1; + uint32_t fifo_mask : 1; + uint32_t mem_clk_force_on : 1; + uint32_t mem_force_pd : 1; + uint32_t mem_force_pu : 1; + uint32_t sclk_div_num : 8; + uint32_t sclk_div_a : 6; + uint32_t sclk_div_b : 6; + uint32_t sclk_sel : 2; + uint32_t sclk_active : 1; + uint32_t reserved27 : 4; + uint32_t clk_en : 1; }; uint32_t val; } sys_conf; union { struct { - uint32_t ch0 : 1; - uint32_t ch1 : 1; - uint32_t ch2 : 1; - uint32_t ch3 : 1; - uint32_t en : 1; - uint32_t reserved5 : 27; + uint32_t ch0 : 1; + uint32_t ch1 : 1; + uint32_t ch2 : 1; + uint32_t ch3 : 1; + uint32_t en : 1; + uint32_t reserved5 : 27; }; uint32_t val; } tx_sim; union { struct { - uint32_t ref_cnt_rst_ch0 : 1; - uint32_t ref_cnt_rst_ch1 : 1; - uint32_t ref_cnt_rst_ch2 : 1; - uint32_t ref_cnt_rst_ch3 : 1; - uint32_t ref_cnt_rst_ch4 : 1; - uint32_t ref_cnt_rst_ch5 : 1; - uint32_t ref_cnt_rst_ch6 : 1; - uint32_t ref_cnt_rst_ch7 : 1; - uint32_t reserved8 : 24; + uint32_t ch0 : 1; + uint32_t ch1 : 1; + uint32_t ch2 : 1; + uint32_t ch3 : 1; + uint32_t ch4 : 1; + uint32_t ch5 : 1; + uint32_t ch6 : 1; + uint32_t ch7 : 1; + uint32_t reserved8 : 24; }; uint32_t val; } ref_cnt_rst; union { struct { - uint32_t date : 28; - uint32_t reserved28 : 4; + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } date; @@ -342,3 +352,7 @@ extern rmt_mem_t RMTMEM; #ifdef __cplusplus } #endif + + + +#endif /*_SOC_RMT_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index 7cf5d63445..4d2bae6b25 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -14,6 +14,7 @@ #ifndef _SOC_RTC_CNTL_REG_H_ #define _SOC_RTC_CNTL_REG_H_ + #ifdef __cplusplus extern "C" { #endif @@ -33,2107 +34,2088 @@ extern "C" { #define RTC_WDT_RESET_LENGTH_800_NS 5 #define RTC_WDT_RESET_LENGTH_1600_NS 6 #define RTC_WDT_RESET_LENGTH_3200_NS 7 +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG -#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG -#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG - -#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ -/*description: SW system reset*/ -#define RTC_CNTL_SW_SYS_RST (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_V 0x1 -#define RTC_CNTL_SW_SYS_RST_S 31 +/*description: SW system reset.*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: digital core force no reset in deep sleep*/ -#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/*description: digital core force no reset in deep sleep.*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: digital wrap force reset in deep sleep*/ -#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/*description: digital wrap force reset in deep sleep.*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 -#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/*description: .*/ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 -#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/*description: .*/ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 -#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/*description: .*/ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 -#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/*description: .*/ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 -#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/*description: .*/ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 -#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/*description: .*/ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 /* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ -/*description: wait bias_sleep and current source wakeup*/ -#define RTC_CNTL_XTL_EN_WAIT 0x0000000F -#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V) << (RTC_CNTL_XTL_EN_WAIT_S)) -#define RTC_CNTL_XTL_EN_WAIT_V 0xF -#define RTC_CNTL_XTL_EN_WAIT_S 14 +/*description: wait bias_sleep and current source wakeup.*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ -/*description: crystall force power up*/ -#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_V 0x1 -#define RTC_CNTL_XTL_FORCE_PU_S 13 +/*description: crystall force power up.*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: crystall force power down*/ -#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_V 0x1 -#define RTC_CNTL_XTL_FORCE_PD_S 12 +/*description: crystall force power down.*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: BB_PLL force power up*/ -#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 -#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/*description: BB_PLL force power up.*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: BB_PLL force power down*/ -#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 -#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/*description: BB_PLL force power down.*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: BB_PLL_I2C force power up*/ -#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/*description: BB_PLL_I2C force power up.*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: BB_PLL _I2C force power down*/ -#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/*description: BB_PLL _I2C force power down.*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: BB_I2C force power up*/ -#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 -#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/*description: BB_I2C force power up.*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: BB_I2C force power down*/ -#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 -#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/*description: BB_I2C force power down.*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: PRO CPU SW reset*/ -#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_V 0x1 -#define RTC_CNTL_SW_PROCPU_RST_S 5 +/*description: PRO CPU SW reset.*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: APP CPU SW reset*/ -#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_V 0x1 -#define RTC_CNTL_SW_APPCPU_RST_S 4 +/*description: APP CPU SW reset.*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == - 0x86 will stall PRO CPU*/ -#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V) << (RTC_CNTL_SW_STALL_PROCPU_C0_S)) -#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 -#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/*description: {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P +RO CPU.*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == - 0x86 will stall APP CPU*/ -#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V) << (RTC_CNTL_SW_STALL_APPCPU_C0_S)) -#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 -#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 +/*description: {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A +PP CPU.*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 -#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF -#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V) << (RTC_CNTL_SLP_VAL_LO_S)) -#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF -#define RTC_CNTL_SLP_VAL_LO_S 0 +/*description: .*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 -#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) /* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ -/*description: timer alarm enable bit*/ -#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/*description: timer alarm enable bit.*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC sleep timer high 16 bits*/ -#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF -#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V) << (RTC_CNTL_SLP_VAL_HI_S)) -#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF -#define RTC_CNTL_SLP_VAL_HI_S 0 +/*description: RTC sleep timer high 16 bits.*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 -#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC) /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Set 1: to update register with RTC timer*/ -#define RTC_CNTL_TIME_UPDATE (BIT(31)) -#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) -#define RTC_CNTL_TIME_UPDATE_V 0x1 -#define RTC_CNTL_TIME_UPDATE_S 31 +/*description: Set 1: to update register with RTC timer.*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 /* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: enable to record system reset time*/ -#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) -#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) -#define RTC_CNTL_TIMER_SYS_RST_V 0x1 -#define RTC_CNTL_TIMER_SYS_RST_S 29 +/*description: enable to record system reset time.*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_V 0x1 +#define RTC_CNTL_TIMER_SYS_RST_S 29 /* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Enable to record 40M XTAL OFF time*/ -#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) -#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) -#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 -#define RTC_CNTL_TIMER_XTL_OFF_S 28 +/*description: Enable to record 40M XTAL OFF time.*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 /* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Enable to record system stall time*/ -#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) -#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) -#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 -#define RTC_CNTL_TIMER_SYS_STALL_S 27 +/*description: Enable to record system stall time.*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 -#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) /* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: RTC timer low 32 bits*/ -#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V) << (RTC_CNTL_TIMER_VALUE0_LOW_S)) -#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 +/*description: RTC timer low 32 bits.*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 -#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) /* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC timer high 16 bits*/ -#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF -#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V) << (RTC_CNTL_TIMER_VALUE0_HIGH_S)) -#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF -#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 +/*description: RTC timer high 16 bits.*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 -#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: sleep enable bit*/ -#define RTC_CNTL_SLEEP_EN (BIT(31)) -#define RTC_CNTL_SLEEP_EN_M (BIT(31)) -#define RTC_CNTL_SLEEP_EN_V 0x1 -#define RTC_CNTL_SLEEP_EN_S 31 +/*description: sleep enable bit.*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: leep reject bit*/ -#define RTC_CNTL_SLP_REJECT (BIT(30)) -#define RTC_CNTL_SLP_REJECT_M (BIT(30)) -#define RTC_CNTL_SLP_REJECT_V 0x1 -#define RTC_CNTL_SLP_REJECT_S 30 +/*description: leep reject bit.*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: leep wakeup bit*/ -#define RTC_CNTL_SLP_WAKEUP (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_S 29 +/*description: leep wakeup bit.*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: SDIO active indication*/ -#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 -#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/*description: SDIO active indication.*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: 1: APB to RTC using bridge*/ -#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/*description: 1: APB to RTC using bridge.*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 /* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: clear rtc sleep reject cause*/ -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 +/*description: clear rtc sleep reject cause.*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 /* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: rtc software interrupt to main cpu*/ -#define RTC_CNTL_SW_CPU_INT (BIT(0)) -#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) -#define RTC_CNTL_SW_CPU_INT_V 0x1 -#define RTC_CNTL_SW_CPU_INT_S 0 +/*description: rtc software interrupt to main cpu.*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_V 0x1 +#define RTC_CNTL_SW_CPU_INT_S 0 -#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ -/*description: PLL wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF -#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V) << (RTC_CNTL_PLL_BUF_WAIT_S)) -#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF -#define RTC_CNTL_PLL_BUF_WAIT_S 24 +/*description: PLL wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ -/*description: XTAL wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF -#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V) << (RTC_CNTL_XTL_BUF_WAIT_S)) -#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF -#define RTC_CNTL_XTL_BUF_WAIT_S 14 +/*description: XTAL wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ -/*description: CK8M wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_CK8M_WAIT 0x000000FF -#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V) << (RTC_CNTL_CK8M_WAIT_S)) -#define RTC_CNTL_CK8M_WAIT_V 0xFF -#define RTC_CNTL_CK8M_WAIT_S 6 +/*description: CK8M wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ -/*description: CPU stall wait cycles in fast_clk_rtc*/ -#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F -#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V) << (RTC_CNTL_CPU_STALL_WAIT_S)) -#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F -#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/*description: CPU stall wait cycles in fast_clk_rtc.*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ -/*description: CPU stall enable bit*/ -#define RTC_CNTL_CPU_STALL_EN (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_V 0x1 -#define RTC_CNTL_CPU_STALL_EN_S 0 +/*description: CPU stall enable bit.*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 -#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ -/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ -#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF -#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V) << (RTC_CNTL_MIN_TIME_CK8M_OFF_S)) -#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF -#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 /* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ -/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller - start to work*/ -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V) << (RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to w +ork.*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 -#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) /* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ -/*description: */ -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V) << (RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 +/*description: .*/ +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 /* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ -/*description: */ -#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V) << (RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +/*description: .*/ +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V) << (RTC_CNTL_WIFI_POWERUP_TIMER_S)) -#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/*description: .*/ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF -#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V) << (RTC_CNTL_WIFI_WAIT_TIMER_S)) -#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 +/*description: .*/ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 -#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V) << (RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/*description: .*/ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V) << (RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/*description: .*/ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 /* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V) << (RTC_CNTL_POWERUP_TIMER_S)) -#define RTC_CNTL_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_POWERUP_TIMER_S 9 +/*description: .*/ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 /* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_WAIT_TIMER 0x000001FF -#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V) << (RTC_CNTL_WAIT_TIMER_S)) -#define RTC_CNTL_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_WAIT_TIMER_S 0 +/*description: .*/ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 -#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) -/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ -/*description: */ -#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V) << (RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 -/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ -/*description: */ -#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF -#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V) << (RTC_CNTL_RTCMEM_WAIT_TIMER_S)) -#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2C) +/* RTC_CNTLMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ +/*description: .*/ +#define RTC_CNTLMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTLMEM_POWERUP_TIMER_M ((RTC_CNTLMEM_POWERUP_TIMER_V)<<(RTC_CNTLMEM_POWERUP_TIMER_S)) +#define RTC_CNTLMEM_POWERUP_TIMER_V 0x7F +#define RTC_CNTLMEM_POWERUP_TIMER_S 25 +/* RTC_CNTLMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ +/*description: .*/ +#define RTC_CNTLMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTLMEM_WAIT_TIMER_M ((RTC_CNTLMEM_WAIT_TIMER_V)<<(RTC_CNTLMEM_WAIT_TIMER_S)) +#define RTC_CNTLMEM_WAIT_TIMER_V 0x1FF +#define RTC_CNTLMEM_WAIT_TIMER_S 16 /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ -/*description: minimal sleep cycles in slow_clk_rtc*/ -#define RTC_CNTL_MIN_SLP_VAL 0x000000FF -#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V) << (RTC_CNTL_MIN_SLP_VAL_S)) -#define RTC_CNTL_MIN_SLP_VAL_V 0xFF -#define RTC_CNTL_MIN_SLP_VAL_S 8 +/*description: minimal sleep cycles in slow_clk_rtc.*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 #define RTC_CNTL_MIN_SLP_VAL_MIN 2 -#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) /* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ -/*description: */ -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M ((RTC_CNTL_DG_DCDC_POWERUP_TIMER_V) << (RTC_CNTL_DG_DCDC_POWERUP_TIMER_S)) -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 +/*description: .*/ +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M ((RTC_CNTL_DG_DCDC_POWERUP_TIMER_V)<<(RTC_CNTL_DG_DCDC_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 /* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ -/*description: */ -#define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M ((RTC_CNTL_DG_DCDC_WAIT_TIMER_V) << (RTC_CNTL_DG_DCDC_WAIT_TIMER_S)) -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 +/*description: .*/ +#define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M ((RTC_CNTL_DG_DCDC_WAIT_TIMER_V)<<(RTC_CNTL_DG_DCDC_WAIT_TIMER_S)) +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 -#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_PLL_I2C_PU (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_V 0x1 -#define RTC_CNTL_PLL_I2C_PU_S 31 +/*description: .*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: 1: CKGEN_I2C power up*/ -#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 -#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/*description: 1: CKGEN_I2C power up.*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: 1: RFRX_PBUS power up*/ -#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 -#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/*description: 1: RFRX_PBUS power up.*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: 1: TXRF_I2C power up*/ -#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_V 0x1 -#define RTC_CNTL_TXRF_I2C_PU_S 27 +/*description: 1: TXRF_I2C power up.*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: PVTMON power up*/ -#define RTC_CNTL_PVTMON_PU (BIT(26)) -#define RTC_CNTL_PVTMON_PU_M (BIT(26)) -#define RTC_CNTL_PVTMON_PU_V 0x1 -#define RTC_CNTL_PVTMON_PU_S 26 +/*description: 1: PVTMON power up.*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: start BBPLL calibration during sleep*/ -#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 -#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/*description: start BBPLL calibration during sleep.*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 /* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: PLLA force power up*/ -#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 -#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/*description: PLLA force power up.*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 /* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: PLLA force power down*/ -#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 -#define RTC_CNTL_PLLA_FORCE_PD_S 23 +/*description: PLLA force power down.*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 /* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: PLLA force power up*/ -#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +/*description: PLLA force power up.*/ +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) #define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) #define RTC_CNTL_SAR_I2C_PU_V 0x1 #define RTC_CNTL_SAR_I2C_PU_S 22 /* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) -#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) -#define RTC_CNTL_GLITCH_RST_EN_V 0x1 -#define RTC_CNTL_GLITCH_RST_EN_S 20 +/*description: .*/ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 /* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 +/*description: .*/ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 /* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 +/*description: .*/ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 -#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) /* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) +/*description: .*/ +#define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) #define RTC_CNTL_PRO_DRESET_MASK_M (BIT(25)) #define RTC_CNTL_PRO_DRESET_MASK_V 0x1 #define RTC_CNTL_PRO_DRESET_MASK_S 25 /* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_APP_DRESET_MASK (BIT(24)) +/*description: .*/ +#define RTC_CNTL_APP_DRESET_MASK (BIT(24)) #define RTC_CNTL_APP_DRESET_MASK_M (BIT(24)) #define RTC_CNTL_APP_DRESET_MASK_V 0x1 #define RTC_CNTL_APP_DRESET_MASK_S 24 /* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (BIT(23)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23 /* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (BIT(22)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22 /* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (BIT(21)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21 /* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (BIT(20)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20 /* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: PROCPU OcdHaltOnReset*/ -#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) +/*description: PROCPU OcdHaltOnReset.*/ +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (BIT(19)) #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x1 #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19 /* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: APPCPU OcdHaltOnReset*/ -#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) +/*description: APPCPU OcdHaltOnReset.*/ +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (BIT(18)) #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x1 #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18 /* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: clear APP CPU reset flag*/ -#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) +/*description: clear APP CPU reset flag.*/ +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (BIT(17)) #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17 /* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: clear PRO CPU reset_flag*/ -#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) +/*description: clear PRO CPU reset_flag.*/ +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (BIT(16)) #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16 /* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: APP CPU reset flag*/ -#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) +/*description: APP CPU reset flag.*/ +#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) #define RTC_CNTL_RESET_FLAG_APPCPU_M (BIT(15)) #define RTC_CNTL_RESET_FLAG_APPCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_APPCPU_S 15 /* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: PRO CPU reset_flag*/ -#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) +/*description: PRO CPU reset_flag.*/ +#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) #define RTC_CNTL_RESET_FLAG_PROCPU_M (BIT(14)) #define RTC_CNTL_RESET_FLAG_PROCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_PROCPU_S 14 /* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: PRO CPU state vector sel*/ -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/*description: PRO CPU state vector sel.*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 /* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: APP CPU state vector sel*/ -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/*description: APP CPU state vector sel.*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ -/*description: reset cause of APP CPU*/ -#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F -#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V) << (RTC_CNTL_RESET_CAUSE_APPCPU_S)) -#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F -#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/*description: reset cause of APP CPU.*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ -/*description: reset cause of PRO CPU*/ -#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F -#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V) << (RTC_CNTL_RESET_CAUSE_PROCPU_S)) -#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F -#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 +/*description: reset cause of PRO CPU.*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 -#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3C) /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ -/*description: wakeup enable bitmap*/ -#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF -#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V) << (RTC_CNTL_WAKEUP_ENA_S)) -#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF -#define RTC_CNTL_WAKEUP_ENA_S 15 +/*description: wakeup enable bitmap.*/ +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 -#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x40) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 -#define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 /* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_V 0x1 -#define RTC_CNTL_SWD_INT_ENA_S 15 +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_S 15 /* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt*/ -#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ENA_V 0x1 -#define RTC_CNTL_SARADC2_INT_ENA_S 14 +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_S 14 /* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt*/ -#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) -#define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) -#define RTC_CNTL_COCPU_INT_ENA_V 0x1 -#define RTC_CNTL_COCPU_INT_ENA_S 13 +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_S 13 /* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt*/ -#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) -#define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) -#define RTC_CNTL_TSENS_INT_ENA_V 0x1 -#define RTC_CNTL_TSENS_INT_ENA_S 12 +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_S 12 /* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt*/ -#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ENA_V 0x1 -#define RTC_CNTL_SARADC1_INT_ENA_S 11 +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 -#define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 /* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt*/ -#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 -#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_V 0x1 -#define RTC_CNTL_WDT_INT_ENA_S 3 +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 -#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x44) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20 +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20 /* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: glitch_det_interrupt_raw*/ -#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 +/*description: glitch_det_interrupt_raw.*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: touch timeout interrupt raw*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 +/*description: touch timeout interrupt raw.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 /* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: cocpu trap interrupt raw*/ -#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 -#define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 +/*description: cocpu trap interrupt raw.*/ +#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: xtal32k dead detection interrupt raw*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 +/*description: xtal32k dead detection interrupt raw.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 /* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: super watch dog interrupt raw*/ -#define RTC_CNTL_SWD_INT_RAW (BIT(15)) -#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) -#define RTC_CNTL_SWD_INT_RAW_V 0x1 -#define RTC_CNTL_SWD_INT_RAW_S 15 +/*description: super watch dog interrupt raw.*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_V 0x1 +#define RTC_CNTL_SWD_INT_RAW_S 15 /* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: saradc2 interrupt raw*/ -#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) -#define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) -#define RTC_CNTL_SARADC2_INT_RAW_V 0x1 -#define RTC_CNTL_SARADC2_INT_RAW_S 14 +/*description: saradc2 interrupt raw.*/ +#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_V 0x1 +#define RTC_CNTL_SARADC2_INT_RAW_S 14 /* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: riscV cocpu interrupt raw*/ -#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) -#define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) -#define RTC_CNTL_COCPU_INT_RAW_V 0x1 -#define RTC_CNTL_COCPU_INT_RAW_S 13 +/*description: riscV cocpu interrupt raw.*/ +#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_V 0x1 +#define RTC_CNTL_COCPU_INT_RAW_S 13 /* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: tsens interrupt raw*/ -#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) -#define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) -#define RTC_CNTL_TSENS_INT_RAW_V 0x1 -#define RTC_CNTL_TSENS_INT_RAW_S 12 +/*description: tsens interrupt raw.*/ +#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_V 0x1 +#define RTC_CNTL_TSENS_INT_RAW_S 12 /* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: saradc1 interrupt raw*/ -#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) -#define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) -#define RTC_CNTL_SARADC1_INT_RAW_V 0x1 -#define RTC_CNTL_SARADC1_INT_RAW_S 11 +/*description: saradc1 interrupt raw.*/ +#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_V 0x1 +#define RTC_CNTL_SARADC1_INT_RAW_S 11 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC main timer interrupt raw*/ -#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 +/*description: RTC main timer interrupt raw.*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: brown out interrupt raw*/ -#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 +/*description: brown out interrupt raw.*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: touch inactive interrupt raw*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 +/*description: touch inactive interrupt raw.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: touch active interrupt raw*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 +/*description: touch active interrupt raw.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 /* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: touch interrupt raw*/ -#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 -#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 +/*description: touch interrupt raw.*/ +#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 /* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ULP-coprocessor interrupt raw*/ -#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 -#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/*description: ULP-coprocessor interrupt raw.*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC WDT interrupt raw*/ -#define RTC_CNTL_WDT_INT_RAW (BIT(3)) -#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) -#define RTC_CNTL_WDT_INT_RAW_V 0x1 -#define RTC_CNTL_WDT_INT_RAW_S 3 +/*description: RTC WDT interrupt raw.*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 /* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SDIO idle interrupt raw*/ -#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/*description: SDIO idle interrupt raw.*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: sleep reject interrupt raw*/ -#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/*description: sleep reject interrupt raw.*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: sleep wakeup interrupt raw*/ -#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 +/*description: sleep wakeup interrupt raw.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 -#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x48) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20 +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20 /* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: glitch_det_interrupt state*/ -#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 +/*description: glitch_det_interrupt state.*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Touch timeout interrupt state*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 +/*description: Touch timeout interrupt state.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: cocpu trap interrupt state*/ -#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 -#define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 +/*description: cocpu trap interrupt state.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: xtal32k dead detection interrupt state*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 +/*description: xtal32k dead detection interrupt state.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 /* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: super watch dog interrupt state*/ -#define RTC_CNTL_SWD_INT_ST (BIT(15)) -#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) -#define RTC_CNTL_SWD_INT_ST_V 0x1 -#define RTC_CNTL_SWD_INT_ST_S 15 +/*description: super watch dog interrupt state.*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_V 0x1 +#define RTC_CNTL_SWD_INT_ST_S 15 /* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: saradc2 interrupt state*/ -#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ST_V 0x1 -#define RTC_CNTL_SARADC2_INT_ST_S 14 +/*description: saradc2 interrupt state.*/ +#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_V 0x1 +#define RTC_CNTL_SARADC2_INT_ST_S 14 /* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: riscV cocpu interrupt state*/ -#define RTC_CNTL_COCPU_INT_ST (BIT(13)) -#define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) -#define RTC_CNTL_COCPU_INT_ST_V 0x1 -#define RTC_CNTL_COCPU_INT_ST_S 13 +/*description: riscV cocpu interrupt state.*/ +#define RTC_CNTL_COCPU_INT_ST (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_V 0x1 +#define RTC_CNTL_COCPU_INT_ST_S 13 /* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: tsens interrupt state*/ -#define RTC_CNTL_TSENS_INT_ST (BIT(12)) -#define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) -#define RTC_CNTL_TSENS_INT_ST_V 0x1 -#define RTC_CNTL_TSENS_INT_ST_S 12 +/*description: tsens interrupt state.*/ +#define RTC_CNTL_TSENS_INT_ST (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_V 0x1 +#define RTC_CNTL_TSENS_INT_ST_S 12 /* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: saradc1 interrupt state*/ -#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ST_V 0x1 -#define RTC_CNTL_SARADC1_INT_ST_S 11 +/*description: saradc1 interrupt state.*/ +#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_V 0x1 +#define RTC_CNTL_SARADC1_INT_ST_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC main timer interrupt state*/ -#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 +/*description: RTC main timer interrupt state.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: brown out interrupt state*/ -#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 +/*description: brown out interrupt state.*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: touch inactive interrupt state*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 +/*description: touch inactive interrupt state.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: touch active interrupt state*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 +/*description: touch active interrupt state.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: touch done interrupt state*/ -#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 -#define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 +/*description: touch done interrupt state.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 /* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ULP-coprocessor interrupt state*/ -#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ST_V 0x1 -#define RTC_CNTL_ULP_CP_INT_ST_S 5 +/*description: ULP-coprocessor interrupt state.*/ +#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ST_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC WDT interrupt state*/ -#define RTC_CNTL_WDT_INT_ST (BIT(3)) -#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ST_V 0x1 -#define RTC_CNTL_WDT_INT_ST_S 3 +/*description: RTC WDT interrupt state.*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SDIO idle interrupt state*/ -#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/*description: SDIO idle interrupt state.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: sleep reject interrupt state*/ -#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/*description: sleep reject interrupt state.*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: sleep wakeup interrupt state*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 +/*description: sleep wakeup interrupt state.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 -#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x4C) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20 +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20 /* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Clear glitch det interrupt state*/ -#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 +/*description: Clear glitch det interrupt state.*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Clear touch timeout interrupt state*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 +/*description: Clear touch timeout interrupt state.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 /* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Clear cocpu trap interrupt state*/ -#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 -#define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 +/*description: Clear cocpu trap interrupt state.*/ +#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Clear RTC WDT interrupt state*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 +/*description: Clear RTC WDT interrupt state.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 /* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Clear super watch dog interrupt state*/ -#define RTC_CNTL_SWD_INT_CLR (BIT(15)) -#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) -#define RTC_CNTL_SWD_INT_CLR_V 0x1 -#define RTC_CNTL_SWD_INT_CLR_S 15 +/*description: Clear super watch dog interrupt state.*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_V 0x1 +#define RTC_CNTL_SWD_INT_CLR_S 15 /* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Clear saradc2 interrupt state*/ -#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) -#define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) -#define RTC_CNTL_SARADC2_INT_CLR_V 0x1 -#define RTC_CNTL_SARADC2_INT_CLR_S 14 +/*description: Clear saradc2 interrupt state.*/ +#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_V 0x1 +#define RTC_CNTL_SARADC2_INT_CLR_S 14 /* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Clear riscV cocpu interrupt state*/ -#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) -#define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) -#define RTC_CNTL_COCPU_INT_CLR_V 0x1 -#define RTC_CNTL_COCPU_INT_CLR_S 13 +/*description: Clear riscV cocpu interrupt state.*/ +#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_V 0x1 +#define RTC_CNTL_COCPU_INT_CLR_S 13 /* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Clear tsens interrupt state*/ -#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) -#define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) -#define RTC_CNTL_TSENS_INT_CLR_V 0x1 -#define RTC_CNTL_TSENS_INT_CLR_S 12 +/*description: Clear tsens interrupt state.*/ +#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_V 0x1 +#define RTC_CNTL_TSENS_INT_CLR_S 12 /* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Clear saradc1 interrupt state*/ -#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) -#define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) -#define RTC_CNTL_SARADC1_INT_CLR_V 0x1 -#define RTC_CNTL_SARADC1_INT_CLR_S 11 +/*description: Clear saradc1 interrupt state.*/ +#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_V 0x1 +#define RTC_CNTL_SARADC1_INT_CLR_S 11 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Clear RTC main timer interrupt state*/ -#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 +/*description: Clear RTC main timer interrupt state.*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Clear brown out interrupt state*/ -#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 +/*description: Clear brown out interrupt state.*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Clear touch inactive interrupt state*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 +/*description: Clear touch inactive interrupt state.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Clear touch active interrupt state*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 +/*description: Clear touch active interrupt state.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 /* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Clear touch done interrupt state*/ -#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 -#define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 +/*description: Clear touch done interrupt state.*/ +#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 /* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Clear ULP-coprocessor interrupt state*/ -#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 -#define RTC_CNTL_ULP_CP_INT_CLR_S 5 +/*description: Clear ULP-coprocessor interrupt state.*/ +#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_INT_CLR_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Clear RTC WDT interrupt state*/ -#define RTC_CNTL_WDT_INT_CLR (BIT(3)) -#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) -#define RTC_CNTL_WDT_INT_CLR_V 0x1 -#define RTC_CNTL_WDT_INT_CLR_S 3 +/*description: Clear RTC WDT interrupt state.*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 /* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Clear SDIO idle interrupt state*/ -#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/*description: Clear SDIO idle interrupt state.*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Clear sleep reject interrupt state*/ -#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/*description: Clear sleep reject interrupt state.*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Clear sleep wakeup interrupt state*/ -#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 +/*description: Clear sleep wakeup interrupt state.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 -#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH0 0xFFFFFFFF -#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V) << (RTC_CNTL_SCRATCH0_S)) -#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH0_S 0 +/*description: .*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 -#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH1 0xFFFFFFFF -#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V) << (RTC_CNTL_SCRATCH1_S)) -#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH1_S 0 +/*description: .*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 -#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH2 0xFFFFFFFF -#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V) << (RTC_CNTL_SCRATCH2_S)) -#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH2_S 0 +/*description: .*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 -#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5C) /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH3 0xFFFFFFFF -#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V) << (RTC_CNTL_SCRATCH3_S)) -#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH3_S 0 +/*description: .*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 -#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 -#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/*description: .*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: power down XTAL at high level*/ -#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 -#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 +/*description: 0: power down XTAL at high level.*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 /* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: XTAL_32K sel. 0: external XTAL_32K*/ -#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) -#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) -#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 -#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 +/*description: XTAL_32K sel. 0: external XTAL_32K.*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 /* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: state of 32k_wdt*/ -#define RTC_CNTL_WDT_STATE 0x00000007 -#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V) << (RTC_CNTL_WDT_STATE_S)) -#define RTC_CNTL_WDT_STATE_V 0x7 -#define RTC_CNTL_WDT_STATE_S 20 +/*description: state of 32k_wdt.*/ +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 /* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ -/*description: DAC_XTAL_32K*/ -#define RTC_CNTL_DAC_XTAL_32K 0x00000007 -#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V) << (RTC_CNTL_DAC_XTAL_32K_S)) -#define RTC_CNTL_DAC_XTAL_32K_V 0x7 -#define RTC_CNTL_DAC_XTAL_32K_S 17 +/*description: DAC_XTAL_32K.*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 +#define RTC_CNTL_DAC_XTAL_32K_S 17 /* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: XPD_XTAL_32K*/ -#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) -#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) -#define RTC_CNTL_XPD_XTAL_32K_V 0x1 -#define RTC_CNTL_XPD_XTAL_32K_S 16 +/*description: XPD_XTAL_32K.*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_V 0x1 +#define RTC_CNTL_XPD_XTAL_32K_S 16 /* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ -/*description: DRES_XTAL_32K*/ -#define RTC_CNTL_DRES_XTAL_32K 0x00000007 -#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V) << (RTC_CNTL_DRES_XTAL_32K_S)) -#define RTC_CNTL_DRES_XTAL_32K_V 0x7 -#define RTC_CNTL_DRES_XTAL_32K_S 13 +/*description: DRES_XTAL_32K.*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) +#define RTC_CNTL_DRES_XTAL_32K_V 0x7 +#define RTC_CNTL_DRES_XTAL_32K_S 13 /* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ -/*description: xtal_32k gm control*/ -#define RTC_CNTL_DGM_XTAL_32K 0x00000007 -#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V) << (RTC_CNTL_DGM_XTAL_32K_S)) -#define RTC_CNTL_DGM_XTAL_32K_V 0x7 -#define RTC_CNTL_DGM_XTAL_32K_S 10 +/*description: xtal_32k gm control.*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) +#define RTC_CNTL_DGM_XTAL_32K_V 0x7 +#define RTC_CNTL_DGM_XTAL_32K_S 10 /* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 0: single-end buffer 1: differential buffer*/ -#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) -#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) -#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 -#define RTC_CNTL_DBUF_XTAL_32K_S 9 +/*description: 0: single-end buffer 1: differential buffer.*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 /* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: apply an internal clock to help xtal 32k to start*/ -#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) -#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) -#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 -#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 +/*description: apply an internal clock to help xtal 32k to start.*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 /* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: Xtal 32k xpd control by sw or fsm*/ -#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) -#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) -#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 -#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 +/*description: Xtal 32k xpd control by sw or fsm.*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 /* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: xtal 32k switch back xtal when xtal is restarted*/ -#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 -#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 +/*description: xtal 32k switch back xtal when xtal is restarted.*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 /* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: xtal 32k restart xtal when xtal is dead*/ -#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 -#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 +/*description: xtal 32k restart xtal when xtal is dead.*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 /* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: xtal 32k switch to back up clock when xtal is dead*/ -#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 +/*description: xtal 32k switch to back up clock when xtal is dead.*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 /* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: xtal 32k external xtal clock force on*/ -#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 +/*description: xtal 32k external xtal clock force on.*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 /* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog sw reset*/ -#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) -#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) -#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 -#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 +/*description: xtal 32k watch dog sw reset.*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 /* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog clock force on*/ -#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 +/*description: xtal 32k watch dog clock force on.*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 /* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog enable*/ -#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) -#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) -#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 -#define RTC_CNTL_XTAL32K_WDT_EN_S 0 +/*description: xtal 32k watch dog enable.*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 -#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) -#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) -#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 -#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/*description: .*/ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: external wakeup at low level*/ -#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) -#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) -#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 -#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 +/*description: 0: external wakeup at low level.*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: enable filter for gpio wakeup event*/ -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 -#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 +/*description: enable filter for gpio wakeup event.*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 -#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: enable reject for deep sleep*/ -#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 -#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 +/*description: enable reject for deep sleep.*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: enable reject for light sleep*/ -#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 +/*description: enable reject for light sleep.*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 /* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ -/*description: sleep reject enable*/ -#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF -#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V) << (RTC_CNTL_SLEEP_REJECT_ENA_S)) -#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF -#define RTC_CNTL_SLEEP_REJECT_ENA_S 12 +/*description: sleep reject enable.*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 12 -#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C) /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ -/*description: */ -#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 -#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V) << (RTC_CNTL_CPUPERIOD_SEL_S)) -#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 -#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/*description: .*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: CPU sel option*/ -#define RTC_CNTL_CPUSEL_CONF (BIT(29)) -#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) -#define RTC_CNTL_CPUSEL_CONF_V 0x1 -#define RTC_CNTL_CPUSEL_CONF_S 29 +/*description: CPU sel option.*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 -#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) /* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ -/*description: */ -#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF -#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V) << (RTC_CNTL_SDIO_ACT_DNUM_S)) -#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF -#define RTC_CNTL_SDIO_ACT_DNUM_S 22 +/*description: .*/ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 -#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 -#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V) << (RTC_CNTL_ANA_CLK_RTC_SEL_S)) -#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 -#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/*description: .*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: fast_clk_rtc sel. 0: XTAL div 4*/ -#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 -#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/*description: fast_clk_rtc sel. 0: XTAL div 4.*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: CK8M force power up*/ -#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 -#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/*description: CK8M force power up.*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: CK8M force power down*/ -#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 -#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/*description: CK8M force power down.*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ -/*description: CK8M_DFREQ*/ -#define RTC_CNTL_CK8M_DFREQ 0x000000FF -#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V) << (RTC_CNTL_CK8M_DFREQ_S)) -#define RTC_CNTL_CK8M_DFREQ_V 0xFF -#define RTC_CNTL_CK8M_DFREQ_S 17 +/*description: CK8M_DFREQ.*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: CK8M force no gating during sleep*/ -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/*description: CK8M force no gating during sleep.*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: XTAL force no gating during sleep*/ -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/*description: XTAL force no gating during sleep.*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ -/*description: divider = reg_ck8m_div_sel + 1*/ -#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 -#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V) << (RTC_CNTL_CK8M_DIV_SEL_S)) -#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 -#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/*description: divider = reg_ck8m_div_sel + 1.*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: enable CK8M for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) -#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) -#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 -#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/*description: enable CK8M for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ -/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) -#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) -#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 -#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) -#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) -#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 -#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 1: CK8M_D256_OUT is actually CK8M*/ -#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) -#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) -#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 -#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/*description: 1: CK8M_D256_OUT is actually CK8M.*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: disable CK8M and CK8M_D256_OUT*/ -#define RTC_CNTL_ENB_CK8M (BIT(6)) -#define RTC_CNTL_ENB_CK8M_M (BIT(6)) -#define RTC_CNTL_ENB_CK8M_V 0x1 -#define RTC_CNTL_ENB_CK8M_S 6 +/*description: disable CK8M and CK8M_D256_OUT.*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ -/*description: CK8M_D256_OUT divider. 00: div128*/ -#define RTC_CNTL_CK8M_DIV 0x00000003 -#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V) << (RTC_CNTL_CK8M_DIV_S)) -#define RTC_CNTL_CK8M_DIV_V 0x3 -#define RTC_CNTL_CK8M_DIV_S 4 +/*description: CK8M_D256_OUT divider. 00: div128.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 /* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ -#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 -#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 -#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) /* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 +/*description: .*/ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 /* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_DIV 0x000000FF -#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V) << (RTC_CNTL_ANA_CLK_DIV_S)) -#define RTC_CNTL_ANA_CLK_DIV_V 0xFF -#define RTC_CNTL_ANA_CLK_DIV_S 23 +/*description: .*/ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) +#define RTC_CNTL_ANA_CLK_DIV_V 0xFF +#define RTC_CNTL_ANA_CLK_DIV_S 23 /* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ -#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) -#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) -#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 -#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 -#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7C) /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_V 0x1 -#define RTC_CNTL_XPD_SDIO_REG_S 31 +/*description: .*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ -/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFH_SDIO 0x00000003 -#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V) << (RTC_CNTL_DREFH_SDIO_S)) -#define RTC_CNTL_DREFH_SDIO_V 0x3 -#define RTC_CNTL_DREFH_SDIO_S 29 +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ -/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFM_SDIO 0x00000003 -#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V) << (RTC_CNTL_DREFM_SDIO_S)) -#define RTC_CNTL_DREFM_SDIO_V 0x3 -#define RTC_CNTL_DREFM_SDIO_S 27 +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ -/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFL_SDIO 0x00000003 -#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V) << (RTC_CNTL_DREFL_SDIO_S)) -#define RTC_CNTL_DREFL_SDIO_V 0x3 -#define RTC_CNTL_DREFL_SDIO_S 25 +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: read only register for REG1P8_READY*/ -#define RTC_CNTL_REG1P8_READY (BIT(24)) -#define RTC_CNTL_REG1P8_READY_M (BIT(24)) -#define RTC_CNTL_REG1P8_READY_V 0x1 -#define RTC_CNTL_REG1P8_READY_S 24 +/*description: read only register for REG1P8_READY.*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ -/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_SDIO_TIEH (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_V 0x1 -#define RTC_CNTL_SDIO_TIEH_S 23 +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: 1: use SW option to control SDIO_REG*/ -#define RTC_CNTL_SDIO_FORCE (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_V 0x1 -#define RTC_CNTL_SDIO_FORCE_S 22 +/*description: 1: use SW option to control SDIO_REG.*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ -/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ -#define RTC_CNTL_SDIO_PD_EN (BIT(21)) -#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) -#define RTC_CNTL_SDIO_PD_EN_V 0x1 -#define RTC_CNTL_SDIO_PD_EN_S 21 +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0.*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 /* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ -/*description: enable current limit*/ -#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) -#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) -#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 -#define RTC_CNTL_SDIO_ENCURLIM_S 20 +/*description: enable current limit.*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 /* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: select current limit mode*/ -#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) -#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) -#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 -#define RTC_CNTL_SDIO_MODECURLIM_S 19 +/*description: select current limit mode.*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 /* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ -/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ -#define RTC_CNTL_SDIO_DCURLIM 0x00000007 -#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V) << (RTC_CNTL_SDIO_DCURLIM_S)) -#define RTC_CNTL_SDIO_DCURLIM_V 0x7 -#define RTC_CNTL_SDIO_DCURLIM_S 16 +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d).*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) +#define RTC_CNTL_SDIO_DCURLIM_V 0x7 +#define RTC_CNTL_SDIO_DCURLIM_S 16 /* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: 0 to set init[1:0]=0*/ -#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) -#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) -#define RTC_CNTL_SDIO_EN_INITI_V 0x1 -#define RTC_CNTL_SDIO_EN_INITI_S 15 +/*description: 0 to set init[1:0]=0.*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_V 0x1 +#define RTC_CNTL_SDIO_EN_INITI_S 15 /* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ -/*description: add resistor from ldo output to ground. 0: no res*/ -#define RTC_CNTL_SDIO_INITI 0x00000003 -#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V) << (RTC_CNTL_SDIO_INITI_S)) -#define RTC_CNTL_SDIO_INITI_V 0x3 -#define RTC_CNTL_SDIO_INITI_S 13 +/*description: add resistor from ldo output to ground. 0: no res.*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) +#define RTC_CNTL_SDIO_INITI_V 0x3 +#define RTC_CNTL_SDIO_INITI_S 13 /* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ -/*description: ability to prevent LDO from overshoot*/ -#define RTC_CNTL_SDIO_DCAP 0x00000003 -#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V) << (RTC_CNTL_SDIO_DCAP_S)) -#define RTC_CNTL_SDIO_DCAP_V 0x3 -#define RTC_CNTL_SDIO_DCAP_S 11 +/*description: ability to prevent LDO from overshoot.*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) +#define RTC_CNTL_SDIO_DCAP_V 0x3 +#define RTC_CNTL_SDIO_DCAP_S 11 /* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ -/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ -#define RTC_CNTL_SDIO_DTHDRV 0x00000003 -#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V) << (RTC_CNTL_SDIO_DTHDRV_S)) -#define RTC_CNTL_SDIO_DTHDRV_V 0x3 -#define RTC_CNTL_SDIO_DTHDRV_S 9 +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current.*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) +#define RTC_CNTL_SDIO_DTHDRV_V 0x3 +#define RTC_CNTL_SDIO_DTHDRV_S 9 /* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ -/*description: timer count to apply reg_sdio_dcap after sdio power on*/ -#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF -#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V) << (RTC_CNTL_SDIO_TIMER_TARGET_S)) -#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF -#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 +/*description: timer count to apply reg_sdio_dcap after sdio power on.*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 -#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0080) +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) /* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ -/*description: DBG_ATTEN when rtc in monitor state*/ -#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F -#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V) << (RTC_CNTL_DBG_ATTEN_MONITOR_S)) -#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF -#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 +/*description: DBG_ATTEN when rtc in monitor state.*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 /* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ -/*description: DBG_ATTEN when rtc in sleep state*/ -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V) << (RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 +/*description: DBG_ATTEN when rtc in sleep state.*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 /* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: bias_sleep when rtc in monitor state*/ -#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 -#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 +/*description: bias_sleep when rtc in monitor state.*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 /* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: bias_sleep when rtc in sleep_state*/ -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 +/*description: bias_sleep when rtc in sleep_state.*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 /* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: xpd cur when rtc in monitor state*/ -#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) -#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) -#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 -#define RTC_CNTL_PD_CUR_MONITOR_S 15 +/*description: xpd cur when rtc in monitor state.*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 /* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: xpd cur when rtc in sleep_state*/ -#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) -#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) -#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 -#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 +/*description: xpd cur when rtc in sleep_state.*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 /* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) -#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) -#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 -#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 /* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 /* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) -#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) -#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 -#define RTC_CNTL_BIAS_BUF_WAKE_S 11 +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 /* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) -#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) -#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 -#define RTC_CNTL_BIAS_BUF_IDLE_S 10 +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 -#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084) +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84) /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) -#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) -#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 -#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 +/*description: .*/ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 /* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: RTC_REG force power down (for RTC_REG power down means decrease - the voltage to 0.8v or lower )*/ -#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) -#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) -#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 -#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 +/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0 +.8v or lower ).*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ -/*description: RTC_DBOOST force power up*/ -#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) -#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) -#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 -#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/*description: RTC_DBOOST force power up.*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RTC_DBOOST force power down*/ -#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) -#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) -#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 -#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/*description: RTC_DBOOST force power down.*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ -/*description: SCK_DCAP*/ -#define RTC_CNTL_SCK_DCAP 0x000000FF -#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V) << (RTC_CNTL_SCK_DCAP_S)) -#define RTC_CNTL_SCK_DCAP_V 0xFF -#define RTC_CNTL_SCK_DCAP_S 14 -#define RTC_CNTL_SCK_DCAP_DEFAULT 255 +/*description: SCK_DCAP.*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 /* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DIG_CAL_EN (BIT(7)) +/*description: .*/ +#define RTC_CNTL_DIG_CAL_EN (BIT(7)) #define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) #define RTC_CNTL_DIG_CAL_EN_V 0x1 #define RTC_CNTL_DIG_CAL_EN_S 7 -#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) /* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: rtc pad force hold*/ -#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) -#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) -#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 -#define RTC_CNTL_PAD_FORCE_HOLD_S 21 +/*description: rtc pad force hold.*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: enable power down rtc_peri in sleep*/ -#define RTC_CNTL_PD_EN (BIT(20)) -#define RTC_CNTL_PD_EN_M (BIT(20)) -#define RTC_CNTL_PD_EN_V 0x1 -#define RTC_CNTL_PD_EN_S 20 +/*description: enable power down rtc_peri in sleep .*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: rtc_peri force power up*/ -#define RTC_CNTL_FORCE_PU (BIT(19)) -#define RTC_CNTL_FORCE_PU_M (BIT(19)) -#define RTC_CNTL_FORCE_PU_V 0x1 -#define RTC_CNTL_FORCE_PU_S 19 +/*description: rtc_peri force power up.*/ +#define RTC_CNTL_FORCE_PU (BIT(19)) +#define RTC_CNTL_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 19 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: rtc_peri force power down*/ -#define RTC_CNTL_FORCE_PD (BIT(18)) -#define RTC_CNTL_FORCE_PD_M (BIT(18)) -#define RTC_CNTL_FORCE_PD_V 0x1 -#define RTC_CNTL_FORCE_PD_S 18 +/*description: rtc_peri force power down.*/ +#define RTC_CNTL_FORCE_PD (BIT(18)) +#define RTC_CNTL_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 18 /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable power down RTC memory in sleep*/ -#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) -#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) -#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 -#define RTC_CNTL_SLOWMEM_PD_EN_S 17 +/*description: enable power down RTC memory in sleep.*/ +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: RTC memory force power up*/ -#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) -#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) -#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 +/*description: RTC memory force power up.*/ +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 /* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: RTC memory force power down*/ -#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) -#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) -#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 +/*description: RTC memory force power down.*/ +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 /* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable power down fast RTC memory in sleep*/ -#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) -#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) -#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 -#define RTC_CNTL_FASTMEM_PD_EN_S 14 +/*description: enable power down fast RTC memory in sleep.*/ +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: Fast RTC memory force power up*/ -#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) -#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) -#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 +/*description: Fast RTC memory force power up.*/ +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 /* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Fast RTC memory force power down*/ -#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) -#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) -#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 +/*description: Fast RTC memory force power down.*/ +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: RTC memory force no PD*/ -#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) -#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) -#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/*description: RTC memory force no PD.*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC memory force PD*/ -#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) -#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) -#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/*description: RTC memory force PD.*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: RTC memory PD following CPU*/ -#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) -#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) -#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 -#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/*description: 1: RTC memory PD following CPU.*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: Fast RTC memory force no PD*/ -#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) -#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) -#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/*description: Fast RTC memory force no PD.*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Fast RTC memory force PD*/ -#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) -#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) -#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/*description: Fast RTC memory force PD.*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: Fast RTC memory PD following CPU*/ -#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) -#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) -#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 -#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/*description: 1: Fast RTC memory PD following CPU.*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ -/*description: rtc_peri force no ISO*/ -#define RTC_CNTL_FORCE_NOISO (BIT(5)) -#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) -#define RTC_CNTL_FORCE_NOISO_V 0x1 -#define RTC_CNTL_FORCE_NOISO_S 5 +/*description: rtc_peri force no ISO.*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: rtc_peri force ISO*/ -#define RTC_CNTL_FORCE_ISO (BIT(4)) -#define RTC_CNTL_FORCE_ISO_M (BIT(4)) -#define RTC_CNTL_FORCE_ISO_V 0x1 -#define RTC_CNTL_FORCE_ISO_S 4 +/*description: rtc_peri force ISO.*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC memory force ISO*/ -#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) -#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) -#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/*description: RTC memory force ISO.*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: RTC memory force no ISO*/ -#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/*description: RTC memory force no ISO.*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Fast RTC memory force ISO*/ -#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) -#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) -#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/*description: Fast RTC memory force ISO.*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Fast RTC memory force no ISO*/ -#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) -#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) -#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 -/* Useful groups of RTC_CNTL_PWC_REG bits */ -#define RTC_CNTL_MEM_FORCE_ISO \ - (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) -#define RTC_CNTL_MEM_FORCE_NOISO \ - (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) -#define RTC_CNTL_MEM_PD_EN \ - (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) -#define RTC_CNTL_MEM_FORCE_PU \ - (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) -#define RTC_CNTL_MEM_FORCE_PD \ - (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) -#define RTC_CNTL_MEM_FOLW_CPU \ - (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) -#define RTC_CNTL_MEM_FORCE_LPU \ - (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) -#define RTC_CNTL_MEM_FORCE_LPD \ - (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) +/*description: Fast RTC memory force no ISO.*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008C) +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x8C) /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 -#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/*description: .*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ -/*description: enable power down wifi in sleep*/ -#define RTC_CNTL_WIFI_PD_EN (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_V 0x1 -#define RTC_CNTL_WIFI_PD_EN_S 30 +/*description: enable power down wifi in sleep.*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 /* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ -/*description: enable power down internal SRAM 4 in sleep*/ -#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) -#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) -#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 +/*description: enable power down internal SRAM 4 in sleep.*/ +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 /* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ -/*description: enable power down internal SRAM 3 in sleep*/ -#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) -#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) -#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 +/*description: enable power down internal SRAM 3 in sleep.*/ +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 /* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ -/*description: enable power down internal SRAM 2 in sleep*/ -#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) -#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) -#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 +/*description: enable power down internal SRAM 2 in sleep.*/ +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 /* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ -/*description: enable power down internal SRAM 1 in sleep*/ -#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) -#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) -#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 +/*description: enable power down internal SRAM 1 in sleep.*/ +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 /* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ -/*description: enable power down internal SRAM 0 in sleep*/ -#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) -#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) -#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 +/*description: enable power down internal SRAM 0 in sleep.*/ +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 /* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ -/*description: enable power down ROM in sleep*/ -#define RTC_CNTL_ROM0_PD_EN (BIT(24)) -#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) -#define RTC_CNTL_ROM0_PD_EN_V 0x1 -#define RTC_CNTL_ROM0_PD_EN_S 24 +/*description: enable power down ROM in sleep.*/ +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_V 0x1 +#define RTC_CNTL_ROM0_PD_EN_S 24 /* RTC_CNTL_DG_DCDC_PD_EN : R/W ;bitpos:[23] ;default: 0 ; */ -/*description: enable power down digital dcdc in sleep*/ -#define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) -#define RTC_CNTL_DG_DCDC_PD_EN_M (BIT(23)) -#define RTC_CNTL_DG_DCDC_PD_EN_V 0x1 -#define RTC_CNTL_DG_DCDC_PD_EN_S 23 +/*description: enable power down digital dcdc in sleep.*/ +#define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) +#define RTC_CNTL_DG_DCDC_PD_EN_M (BIT(23)) +#define RTC_CNTL_DG_DCDC_PD_EN_V 0x1 +#define RTC_CNTL_DG_DCDC_PD_EN_S 23 /* RTC_CNTL_DG_DCDC_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ -/*description: digital dcdc force power up*/ -#define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) -#define RTC_CNTL_DG_DCDC_FORCE_PU_M (BIT(22)) -#define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 +/*description: digital dcdc force power up.*/ +#define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) +#define RTC_CNTL_DG_DCDC_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 /* RTC_CNTL_DG_DCDC_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: digital dcdc force power down*/ -#define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) -#define RTC_CNTL_DG_DCDC_FORCE_PD_M (BIT(21)) -#define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 +/*description: digital dcdc force power down.*/ +#define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) +#define RTC_CNTL_DG_DCDC_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ -/*description: digital core force power up*/ -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/*description: digital core force power up.*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: digital core force power down*/ -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/*description: digital core force power down.*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ -/*description: wifi force power up*/ -#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 -#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/*description: wifi force power up.*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: wifi force power down*/ -#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 -#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/*description: wifi force power down.*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 /* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: internal SRAM 4 force power up*/ -#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) -#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) -#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 +/*description: internal SRAM 4 force power up.*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 /* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: internal SRAM 4 force power down*/ -#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) -#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) -#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 +/*description: internal SRAM 4 force power down.*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 /* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ -/*description: internal SRAM 3 force power up*/ -#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) -#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) -#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 +/*description: internal SRAM 3 force power up.*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 /* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: internal SRAM 3 force power down*/ -#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) -#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) -#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 +/*description: internal SRAM 3 force power down.*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 /* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: internal SRAM 2 force power up*/ -#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) -#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) -#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 +/*description: internal SRAM 2 force power up.*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 /* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: internal SRAM 2 force power down*/ -#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) -#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) -#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 +/*description: internal SRAM 2 force power down.*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 /* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ -/*description: internal SRAM 1 force power up*/ -#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) -#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) -#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 +/*description: internal SRAM 1 force power up.*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 /* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: internal SRAM 1 force power down*/ -#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) -#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) -#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 +/*description: internal SRAM 1 force power down.*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 /* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ -/*description: internal SRAM 0 force power up*/ -#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) -#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) -#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 +/*description: internal SRAM 0 force power up.*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 /* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: internal SRAM 0 force power down*/ -#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) -#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) -#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 +/*description: internal SRAM 0 force power down.*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 /* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ -/*description: ROM force power up*/ -#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) -#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) -#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 -#define RTC_CNTL_ROM0_FORCE_PU_S 6 +/*description: ROM force power up.*/ +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 /* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ROM force power down*/ -#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) -#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) -#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 -#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/*description: ROM force power down.*/ +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: memories in digital core force no PD in sleep*/ -#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 -#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/*description: memories in digital core force no PD in sleep.*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: memories in digital core force PD in sleep*/ -#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 -#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 +/*description: memories in digital core force PD in sleep.*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x0090) +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x90) /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/*description: .*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: digital core force ISO*/ -#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/*description: digital core force ISO.*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ -/*description: wifi force no ISO*/ -#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 -#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/*description: wifi force no ISO.*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: wifi force ISO*/ -#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 -#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/*description: wifi force ISO.*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 /* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: internal SRAM 4 force no ISO*/ -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 +/*description: internal SRAM 4 force no ISO.*/ +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 /* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: internal SRAM 4 force ISO*/ -#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 +/*description: internal SRAM 4 force ISO.*/ +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 /* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ -/*description: internal SRAM 3 force no ISO*/ -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 +/*description: internal SRAM 3 force no ISO.*/ +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 /* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: internal SRAM 3 force ISO*/ -#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 +/*description: internal SRAM 3 force ISO.*/ +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 /* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ -/*description: internal SRAM 2 force no ISO*/ -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 +/*description: internal SRAM 2 force no ISO.*/ +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 /* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: internal SRAM 2 force ISO*/ -#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 +/*description: internal SRAM 2 force ISO.*/ +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 /* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ -/*description: internal SRAM 1 force no ISO*/ -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 +/*description: internal SRAM 1 force no ISO.*/ +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 /* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: internal SRAM 1 force ISO*/ -#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 +/*description: internal SRAM 1 force ISO.*/ +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 /* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ -/*description: internal SRAM 0 force no ISO*/ -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 +/*description: internal SRAM 0 force no ISO.*/ +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 /* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: internal SRAM 0 force ISO*/ -#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 +/*description: internal SRAM 0 force ISO.*/ +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 /* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ -/*description: ROM force no ISO*/ -#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) -#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) -#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 -#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 +/*description: ROM force no ISO.*/ +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 /* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: ROM force ISO*/ -#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) -#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) -#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 -#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/*description: ROM force ISO.*/ +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: digital pad force hold*/ -#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/*description: digital pad force hold.*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ -/*description: digital pad force un-hold*/ -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/*description: digital pad force un-hold.*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: digital pad force ISO*/ -#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/*description: digital pad force ISO.*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: digital pad force no ISO*/ -#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/*description: digital pad force no ISO.*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: digital pad enable auto-hold*/ -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/*description: digital pad enable auto-hold.*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: wtite only register to clear digital pad auto-hold*/ -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/*description: wtite only register to clear digital pad auto-hold.*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: read only register to indicate digital pad auto-hold status*/ -#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 -#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/*description: read only register to indicate digital pad auto-hold status.*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 -#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/*description: .*/ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 -#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 +/*description: .*/ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 -#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0094) +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x94) /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define RTC_CNTL_WDT_EN (BIT(31)) -#define RTC_CNTL_WDT_EN_M (BIT(31)) -#define RTC_CNTL_WDT_EN_V 0x1 -#define RTC_CNTL_WDT_EN_S 31 +/*description: .*/ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG0 0x00000007 -#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V) << (RTC_CNTL_WDT_STG0_S)) -#define RTC_CNTL_WDT_STG0_V 0x7 -#define RTC_CNTL_WDT_STG0_S 28 +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG1 0x00000007 -#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V) << (RTC_CNTL_WDT_STG1_S)) -#define RTC_CNTL_WDT_STG1_V 0x7 -#define RTC_CNTL_WDT_STG1_S 25 +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG2 0x00000007 -#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V) << (RTC_CNTL_WDT_STG2_S)) -#define RTC_CNTL_WDT_STG2_V 0x7 -#define RTC_CNTL_WDT_STG2_S 22 +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG3 0x00000007 -#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V) << (RTC_CNTL_WDT_STG3_S)) -#define RTC_CNTL_WDT_STG3_V 0x7 -#define RTC_CNTL_WDT_STG3_S 19 -/* RTC_CNTL_WDT_STGX : */ +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 + /*description: stage action selection values */ #define RTC_WDT_STG_SEL_OFF 0 #define RTC_WDT_STG_SEL_INT 1 @@ -2142,1494 +2124,1497 @@ extern "C" { #define RTC_WDT_STG_SEL_RESET_RTC 4 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ -/*description: CPU reset counter length*/ -#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V) << (RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 +/*description: CPU reset counter length.*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ -/*description: system reset counter length*/ -#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V) << (RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 +/*description: system reset counter length.*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: enable WDT in flash boot*/ -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 +/*description: enable WDT in flash boot.*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: enable WDT reset PRO CPU*/ -#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 -#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 +/*description: enable WDT reset PRO CPU.*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: enable WDT reset APP CPU*/ -#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 -#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 +/*description: enable WDT reset APP CPU.*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ -/*description: pause WDT in sleep*/ -#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 -#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 +/*description: pause WDT in sleep.*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 /* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: wdt reset whole chip enable*/ -#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) -#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) -#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 -#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 +/*description: wdt reset whole chip enable.*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 /* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ -/*description: chip reset siginal pulse width*/ -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V) << (RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 +/*description: chip reset siginal pulse width.*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 -#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0098) +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x98) /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ -/*description: */ -#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V) << (RTC_CNTL_WDT_STG0_HOLD_S)) -#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG0_HOLD_S 0 +/*description: .*/ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x009C) +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x9C) /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ -/*description: */ -#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V) << (RTC_CNTL_WDT_STG1_HOLD_S)) -#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG1_HOLD_S 0 +/*description: .*/ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00A0) +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xA0) /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ -/*description: */ -#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V) << (RTC_CNTL_WDT_STG2_HOLD_S)) -#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG2_HOLD_S 0 +/*description: .*/ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A4) +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xA4) /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ -/*description: */ -#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V) << (RTC_CNTL_WDT_STG3_HOLD_S)) -#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG3_HOLD_S 0 +/*description: .*/ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A8) +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xA8) /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_WDT_FEED (BIT(31)) -#define RTC_CNTL_WDT_FEED_M (BIT(31)) -#define RTC_CNTL_WDT_FEED_V 0x1 -#define RTC_CNTL_WDT_FEED_S 31 +/*description: .*/ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00AC) +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xAC) /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ -/*description: */ -#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF -#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V) << (RTC_CNTL_WDT_WKEY_S)) -#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF -#define RTC_CNTL_WDT_WKEY_S 0 +/*description: .*/ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 -#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00B0) +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xB0) /* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: automatically feed swd when int comes*/ -#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) -#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) -#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 -#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 +/*description: automatically feed swd when int comes.*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: disabel SWD*/ -#define RTC_CNTL_SWD_DISABLE (BIT(30)) -#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) -#define RTC_CNTL_SWD_DISABLE_V 0x1 -#define RTC_CNTL_SWD_DISABLE_S 30 +/*description: disabel SWD.*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_V 0x1 +#define RTC_CNTL_SWD_DISABLE_S 30 /* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Sw feed swd*/ -#define RTC_CNTL_SWD_FEED (BIT(29)) -#define RTC_CNTL_SWD_FEED_M (BIT(29)) -#define RTC_CNTL_SWD_FEED_V 0x1 -#define RTC_CNTL_SWD_FEED_S 29 +/*description: Sw feed swd.*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (BIT(29)) +#define RTC_CNTL_SWD_FEED_V 0x1 +#define RTC_CNTL_SWD_FEED_S 29 /* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: reset swd reset flag*/ -#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) -#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) -#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 -#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 +/*description: reset swd reset flag.*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 /* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ -/*description: adjust signal width send to swd*/ -#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF -#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V) << (RTC_CNTL_SWD_SIGNAL_WIDTH_S)) -#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF -#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 +/*description: adjust signal width send to swd.*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 /* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +/*description: .*/ +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) #define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) #define RTC_CNTL_SWD_BYPASS_RST_V 0x1 #define RTC_CNTL_SWD_BYPASS_RST_S 17 /* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: swd interrupt for feeding*/ -#define RTC_CNTL_SWD_FEED_INT (BIT(1)) -#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) -#define RTC_CNTL_SWD_FEED_INT_V 0x1 -#define RTC_CNTL_SWD_FEED_INT_S 1 +/*description: swd interrupt for feeding.*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_V 0x1 +#define RTC_CNTL_SWD_FEED_INT_S 1 /* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: swd reset flag*/ -#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) -#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) -#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 -#define RTC_CNTL_SWD_RESET_FLAG_S 0 +/*description: swd reset flag.*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 -#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B4) +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB4) /* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ -/*description: */ -#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF -#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V) << (RTC_CNTL_SWD_WKEY_S)) -#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF -#define RTC_CNTL_SWD_WKEY_S 0 +/*description: .*/ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B8) +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xB8) /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ -/*description: */ -#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F -#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V) << (RTC_CNTL_SW_STALL_PROCPU_C1_S)) -#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F -#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/*description: .*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ -/*description: {reg_sw_stall_appcpu_c1[5:0]*/ -#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F -#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V) << (RTC_CNTL_SW_STALL_APPCPU_C1_S)) -#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F -#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 +/*description: {reg_sw_stall_appcpu_c1[5:0].*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00BC) +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xBC) /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH4 0xFFFFFFFF -#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V) << (RTC_CNTL_SCRATCH4_S)) -#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH4_S 0 +/*description: .*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00C0) +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xC0) /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH5 0xFFFFFFFF -#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V) << (RTC_CNTL_SCRATCH5_S)) -#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH5_S 0 +/*description: .*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C4) +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xC4) /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH6 0xFFFFFFFF -#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V) << (RTC_CNTL_SCRATCH6_S)) -#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH6_S 0 +/*description: .*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C8) +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xC8) /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH7 0xFFFFFFFF -#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V) << (RTC_CNTL_SCRATCH7_S)) -#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH7_S 0 +/*description: .*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 -#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00CC) +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xCC) /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ -/*description: rtc main state machine status*/ -#define RTC_CNTL_MAIN_STATE 0x0000000F -#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V) << (RTC_CNTL_MAIN_STATE_S)) -#define RTC_CNTL_MAIN_STATE_V 0xF -#define RTC_CNTL_MAIN_STATE_S 28 +/*description: rtc main state machine status.*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) +#define RTC_CNTL_MAIN_STATE_V 0xF +#define RTC_CNTL_MAIN_STATE_S 28 /* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: rtc main state machine is in idle state*/ -#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) -#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) -#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 +/*description: rtc main state machine is in idle state.*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 /* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: rtc main state machine is in sleep state*/ -#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) -#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) -#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 +/*description: rtc main state machine is in sleep state.*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 /* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait xtal state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 +/*description: rtc main state machine is in wait xtal state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 /* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait pll state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 +/*description: rtc main state machine is in wait pll state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 /* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait 8m state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 +/*description: rtc main state machine is in wait 8m state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 /* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: rtc main state machine is in the states of low power*/ -#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) -#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) -#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 -#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 +/*description: rtc main state machine is in the states of low power.*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 /* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: rtc main state machine is in the states of wakeup process*/ -#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) -#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) -#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 -#define RTC_CNTL_IN_WAKEUP_STATE_S 21 +/*description: rtc main state machine is in the states of wakeup process.*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 /* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: rtc main state machine has been waited for some cycles*/ -#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) -#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) -#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 -#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 +/*description: rtc main state machine has been waited for some cycles.*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 /* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: rtc is ready to receive wake up trigger from wake up source*/ -#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) -#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) -#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 -#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 +/*description: rtc is ready to receive wake up trigger from wake up source.*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 /* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: rtc main state machine is in states that pll should be running*/ -#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) -#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) -#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 -#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 +/*description: rtc main state machine is in states that pll should be running.*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 /* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: no use any more*/ -#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 +/*description: no use any more.*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 /* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: ulp/cocpu is done*/ -#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) -#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) -#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 -#define RTC_CNTL_COCPU_STATE_DONE_S 16 +/*description: ulp/cocpu is done.*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 /* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: ulp/cocpu is in sleep state*/ -#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) -#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) -#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 -#define RTC_CNTL_COCPU_STATE_SLP_S 15 +/*description: ulp/cocpu is in sleep state.*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 /* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: ulp/cocpu is about to working. Switch rtc main state*/ -#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) -#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) -#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 -#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 +/*description: ulp/cocpu is about to working. Switch rtc main state.*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 /* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: ulp/cocpu should start to work*/ -#define RTC_CNTL_COCPU_STATE_START (BIT(13)) -#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) -#define RTC_CNTL_COCPU_STATE_START_V 0x1 -#define RTC_CNTL_COCPU_STATE_START_S 13 +/*description: ulp/cocpu should start to work.*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_V 0x1 +#define RTC_CNTL_COCPU_STATE_START_S 13 /* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: touch is done*/ -#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) -#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) -#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 -#define RTC_CNTL_TOUCH_STATE_DONE_S 12 +/*description: touch is done.*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 /* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: touch is in sleep state*/ -#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) -#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) -#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 -#define RTC_CNTL_TOUCH_STATE_SLP_S 11 +/*description: touch is in sleep state.*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 /* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: touch is about to working. Switch rtc main state*/ -#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) -#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) -#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 -#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 +/*description: touch is about to working. Switch rtc main state.*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 /* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: touch should start to work*/ -#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) -#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) -#define RTC_CNTL_TOUCH_STATE_START_V 0x1 -#define RTC_CNTL_TOUCH_STATE_START_S 9 +/*description: touch should start to work.*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_V 0x1 +#define RTC_CNTL_TOUCH_STATE_START_S 9 /* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: digital wrap power down*/ -#define RTC_CNTL_XPD_DIG (BIT(8)) -#define RTC_CNTL_XPD_DIG_M (BIT(8)) -#define RTC_CNTL_XPD_DIG_V 0x1 -#define RTC_CNTL_XPD_DIG_S 8 +/*description: digital wrap power down.*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (BIT(8)) +#define RTC_CNTL_XPD_DIG_V 0x1 +#define RTC_CNTL_XPD_DIG_S 8 /* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: digital wrap iso*/ -#define RTC_CNTL_DIG_ISO (BIT(7)) -#define RTC_CNTL_DIG_ISO_M (BIT(7)) -#define RTC_CNTL_DIG_ISO_V 0x1 -#define RTC_CNTL_DIG_ISO_S 7 +/*description: digital wrap iso.*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_V 0x1 +#define RTC_CNTL_DIG_ISO_S 7 /* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: wifi wrap power down*/ -#define RTC_CNTL_XPD_WIFI (BIT(6)) -#define RTC_CNTL_XPD_WIFI_M (BIT(6)) -#define RTC_CNTL_XPD_WIFI_V 0x1 -#define RTC_CNTL_XPD_WIFI_S 6 +/*description: wifi wrap power down.*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (BIT(6)) +#define RTC_CNTL_XPD_WIFI_V 0x1 +#define RTC_CNTL_XPD_WIFI_S 6 /* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: wifi iso*/ -#define RTC_CNTL_WIFI_ISO (BIT(5)) -#define RTC_CNTL_WIFI_ISO_M (BIT(5)) -#define RTC_CNTL_WIFI_ISO_V 0x1 -#define RTC_CNTL_WIFI_ISO_S 5 +/*description: wifi iso.*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (BIT(5)) +#define RTC_CNTL_WIFI_ISO_V 0x1 +#define RTC_CNTL_WIFI_ISO_S 5 /* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: rtc peripheral power down*/ -#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) -#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) -#define RTC_CNTL_XPD_RTC_PERI_V 0x1 -#define RTC_CNTL_XPD_RTC_PERI_S 4 +/*description: rtc peripheral power down .*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_V 0x1 +#define RTC_CNTL_XPD_RTC_PERI_S 4 /* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: rtc peripheral iso*/ -#define RTC_CNTL_PERI_ISO (BIT(3)) -#define RTC_CNTL_PERI_ISO_M (BIT(3)) -#define RTC_CNTL_PERI_ISO_V 0x1 -#define RTC_CNTL_PERI_ISO_S 3 +/*description: rtc peripheral iso.*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (BIT(3)) +#define RTC_CNTL_PERI_ISO_V 0x1 +#define RTC_CNTL_PERI_ISO_S 3 /* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: External DCDC power down*/ -#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) -#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) -#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 -#define RTC_CNTL_XPD_DIG_DCDC_S 2 +/*description: External DCDC power down.*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 /* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: rom0 power down*/ -#define RTC_CNTL_XPD_ROM0 (BIT(0)) -#define RTC_CNTL_XPD_ROM0_M (BIT(0)) -#define RTC_CNTL_XPD_ROM0_V 0x1 -#define RTC_CNTL_XPD_ROM0_S 0 +/*description: rom0 power down.*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (BIT(0)) +#define RTC_CNTL_XPD_ROM0_V 0x1 +#define RTC_CNTL_XPD_ROM0_S 0 -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00D0) +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xD0) /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V) << (RTC_CNTL_LOW_POWER_DIAG1_S)) -#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG1_S 0 +/*description: .*/ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 -#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xD4) /* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PAD21_HOLD (BIT(21)) -#define RTC_CNTL_PAD21_HOLD_M (BIT(21)) -#define RTC_CNTL_PAD21_HOLD_V 0x1 -#define RTC_CNTL_PAD21_HOLD_S 21 +/*description: .*/ +#define RTC_CNTL_PAD21_HOLD (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_V 0x1 +#define RTC_CNTL_PAD21_HOLD_S 21 /* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PAD20_HOLD (BIT(20)) -#define RTC_CNTL_PAD20_HOLD_M (BIT(20)) -#define RTC_CNTL_PAD20_HOLD_V 0x1 -#define RTC_CNTL_PAD20_HOLD_S 20 +/*description: .*/ +#define RTC_CNTL_PAD20_HOLD (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_M (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_V 0x1 +#define RTC_CNTL_PAD20_HOLD_S 20 /* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PAD19_HOLD (BIT(19)) -#define RTC_CNTL_PAD19_HOLD_M (BIT(19)) -#define RTC_CNTL_PAD19_HOLD_V 0x1 -#define RTC_CNTL_PAD19_HOLD_S 19 +/*description: .*/ +#define RTC_CNTL_PAD19_HOLD (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_M (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_V 0x1 +#define RTC_CNTL_PAD19_HOLD_S 19 /* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PDAC2_HOLD (BIT(18)) -#define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) -#define RTC_CNTL_PDAC2_HOLD_V 0x1 -#define RTC_CNTL_PDAC2_HOLD_S 18 +/*description: .*/ +#define RTC_CNTL_PDAC2_HOLD (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_S 18 /* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PDAC1_HOLD (BIT(17)) -#define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) -#define RTC_CNTL_PDAC1_HOLD_V 0x1 -#define RTC_CNTL_PDAC1_HOLD_S 17 +/*description: .*/ +#define RTC_CNTL_PDAC1_HOLD (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_S 17 /* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_X32N_HOLD (BIT(16)) -#define RTC_CNTL_X32N_HOLD_M (BIT(16)) -#define RTC_CNTL_X32N_HOLD_V 0x1 -#define RTC_CNTL_X32N_HOLD_S 16 +/*description: .*/ +#define RTC_CNTL_X32N_HOLD (BIT(16)) +#define RTC_CNTL_X32N_HOLD_M (BIT(16)) +#define RTC_CNTL_X32N_HOLD_V 0x1 +#define RTC_CNTL_X32N_HOLD_S 16 /* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_X32P_HOLD (BIT(15)) -#define RTC_CNTL_X32P_HOLD_M (BIT(15)) -#define RTC_CNTL_X32P_HOLD_V 0x1 -#define RTC_CNTL_X32P_HOLD_S 15 +/*description: .*/ +#define RTC_CNTL_X32P_HOLD (BIT(15)) +#define RTC_CNTL_X32P_HOLD_M (BIT(15)) +#define RTC_CNTL_X32P_HOLD_V 0x1 +#define RTC_CNTL_X32P_HOLD_S 15 /* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) -#define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) -#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 /* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) -#define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) -#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 /* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) -#define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) -#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 /* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) -#define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) -#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 /* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) -#define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) -#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 /* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) -#define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) -#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 /* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) -#define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) -#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 /* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) -#define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) -#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 /* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) -#define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) -#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 /* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) -#define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) -#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 /* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) -#define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) -#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 /* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) -#define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) -#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 /* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) -#define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) -#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 /* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) -#define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) -#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 /* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) -#define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) -#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 -#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D8) +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xD8) /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF -#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V) << (RTC_CNTL_DIG_PAD_HOLD_S)) -#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_DIG_PAD_HOLD_S 0 +/*description: .*/ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 -#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xDC) /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: clear ext wakeup1 status*/ -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 +/*description: clear ext wakeup1 status.*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */ -/*description: Bitmap to select RTC pads for ext wakeup1*/ -#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF -#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V) << (RTC_CNTL_EXT_WAKEUP1_SEL_S)) -#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF -#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 +/*description: Bitmap to select RTC pads for ext wakeup1.*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 -#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0x00E0) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xE0) /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ -/*description: ext wakeup1 status*/ -#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF -#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V) << (RTC_CNTL_EXT_WAKEUP1_STATUS_S)) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF -#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 +/*description: ext wakeup1 status.*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00E4) +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xE4) /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) -#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) -#define RTC_CNTL_BROWN_OUT_DET_V 0x1 -#define RTC_CNTL_BROWN_OUT_DET_S 31 +/*description: .*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: enable brown out*/ -#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/*description: enable brown out.*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 /* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: clear brown out counter*/ -#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 -#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 +/*description: clear brown out counter.*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 /* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +/*description: .*/ +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 /* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 1: 4-pos reset*/ -#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) -#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) -#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 -#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 +/*description: 1: 4-pos reset.*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: enable brown out reset*/ -#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/*description: enable brown out reset.*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ -/*description: brown out reset wait cycles*/ -#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF -#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V) << (RTC_CNTL_BROWN_OUT_RST_WAIT_S)) -#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF -#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/*description: brown out reset wait cycles.*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable power down RF when brown out happens*/ -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/*description: enable power down RF when brown out happens.*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable close flash when brown out happens*/ -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 +/*description: enable close flash when brown out happens.*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 /* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ -/*description: brown out interrupt wait cycles*/ -#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF -#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V) << (RTC_CNTL_BROWN_OUT_INT_WAIT_S)) -#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF -#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 +/*description: brown out interrupt wait cycles.*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 -#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00E8) +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xE8) /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: RTC timer low 32 bits*/ -#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V) << (RTC_CNTL_TIMER_VALUE1_LOW_S)) -#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 +/*description: RTC timer low 32 bits.*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 -#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00EC) +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xEC) /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC timer high 16 bits*/ -#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF -#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V) << (RTC_CNTL_TIMER_VALUE1_HIGH_S)) -#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF -#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 +/*description: RTC timer high 16 bits.*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 -#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00F0) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xF0) /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: xtal 32k watch dog backup clock factor*/ -#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF -#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V) << (RTC_CNTL_XTAL32K_CLK_FACTOR_S)) -#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF -#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 +/*description: xtal 32k watch dog backup clock factor.*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 -#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00F4) +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xF4) /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: if restarted xtal32k period is smaller than this*/ -#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F -#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V) << (RTC_CNTL_XTAL32K_STABLE_THRES_S)) -#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF -#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 +/*description: if restarted xtal32k period is smaller than this.*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 /* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ -/*description: If no clock detected for this amount of time*/ -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V) << (RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 +/*description: If no clock detected for this amount of time.*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 /* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ -/*description: cycles to wait to repower on xtal 32k*/ -#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF -#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V) << (RTC_CNTL_XTAL32K_RESTART_WAIT_S)) -#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF -#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 +/*description: cycles to wait to repower on xtal 32k.*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: cycles to wait to return noral xtal 32k*/ -#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F -#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V) << (RTC_CNTL_XTAL32K_RETURN_WAIT_S)) -#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF -#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 +/*description: cycles to wait to return noral xtal 32k.*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 -#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0x00F8) +#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xF8) /* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: ULP-coprocessor timer enable bit*/ -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 +/*description: ULP-coprocessor timer enable bit.*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */ -/*description: ULP-coprocessor wakeup by GPIO state clear*/ -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 +/*description: ULP-coprocessor wakeup by GPIO state clear.*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: ULP-coprocessor wakeup by GPIO enable*/ -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 +/*description: ULP-coprocessor wakeup by GPIO enable.*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 /* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ -/*description: ULP-coprocessor PC initial address*/ -#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF -#define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V) << (RTC_CNTL_ULP_CP_PC_INIT_S)) -#define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF -#define RTC_CNTL_ULP_CP_PC_INIT_S 0 +/*description: ULP-coprocessor PC initial address.*/ +#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF +#define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S)) +#define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF +#define RTC_CNTL_ULP_CP_PC_INIT_S 0 -#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x00FC) +#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0xFC) /* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: Write 1 to start ULP-coprocessor*/ -#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) -#define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) -#define RTC_CNTL_ULP_CP_START_TOP_V 0x1 -#define RTC_CNTL_ULP_CP_START_TOP_S 31 +/*description: Write 1 to start ULP-coprocessor.*/ +#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_V 0x1 +#define RTC_CNTL_ULP_CP_START_TOP_S 31 /* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: 1: ULP-coprocessor is started by SW*/ -#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 +/*description: 1: ULP-coprocessor is started by SW.*/ +#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 /* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: ulp coprocessor clk software reset*/ -#define RTC_CNTL_ULP_CP_RESET (BIT(29)) -#define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) -#define RTC_CNTL_ULP_CP_RESET_V 0x1 -#define RTC_CNTL_ULP_CP_RESET_S 29 +/*description: ulp coprocessor clk software reset.*/ +#define RTC_CNTL_ULP_CP_RESET (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_V 0x1 +#define RTC_CNTL_ULP_CP_RESET_S 29 /* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: ulp coprocessor clk force on*/ -#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) -#define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) -#define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 -#define RTC_CNTL_ULP_CP_CLK_FO_S 28 +/*description: ulp coprocessor clk force on.*/ +#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 +#define RTC_CNTL_ULP_CP_CLK_FO_S 28 /* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 /* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ -/*description: */ -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V) << (RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 /* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ -/*description: */ -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V) << (RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 -#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0100) +#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100) /* RTC_CNTL_COCPU_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) -#define RTC_CNTL_COCPU_CLKGATE_EN_M (BIT(27)) -#define RTC_CNTL_COCPU_CLKGATE_EN_V 0x1 -#define RTC_CNTL_COCPU_CLKGATE_EN_S 27 +/*description: .*/ +#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) +#define RTC_CNTL_COCPU_CLKGATE_EN_M (BIT(27)) +#define RTC_CNTL_COCPU_CLKGATE_EN_V 0x1 +#define RTC_CNTL_COCPU_CLKGATE_EN_S 27 /* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: trigger cocpu register interrupt*/ -#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 +/*description: trigger cocpu register interrupt.*/ +#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 /* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: done signal used by riscv to control timer.*/ -#define RTC_CNTL_COCPU_DONE (BIT(25)) -#define RTC_CNTL_COCPU_DONE_M (BIT(25)) -#define RTC_CNTL_COCPU_DONE_V 0x1 -#define RTC_CNTL_COCPU_DONE_S 25 +/*description: done signal used by riscv to control timer. .*/ +#define RTC_CNTL_COCPU_DONE (BIT(25)) +#define RTC_CNTL_COCPU_DONE_M (BIT(25)) +#define RTC_CNTL_COCPU_DONE_V 0x1 +#define RTC_CNTL_COCPU_DONE_S 25 /* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: 1: select riscv done 0: select ulp done*/ -#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) -#define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) -#define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 -#define RTC_CNTL_COCPU_DONE_FORCE_S 24 +/*description: 1: select riscv done 0: select ulp done.*/ +#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 +#define RTC_CNTL_COCPU_DONE_FORCE_S 24 /* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: 1: old ULP 0: new riscV*/ -#define RTC_CNTL_COCPU_SEL (BIT(23)) -#define RTC_CNTL_COCPU_SEL_M (BIT(23)) -#define RTC_CNTL_COCPU_SEL_V 0x1 -#define RTC_CNTL_COCPU_SEL_S 23 +/*description: 1: old ULP 0: new riscV.*/ +#define RTC_CNTL_COCPU_SEL (BIT(23)) +#define RTC_CNTL_COCPU_SEL_M (BIT(23)) +#define RTC_CNTL_COCPU_SEL_V 0x1 +#define RTC_CNTL_COCPU_SEL_S 23 /* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: to reset cocpu*/ -#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) -#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) -#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 -#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 +/*description: to reset cocpu.*/ +#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 +#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 /* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ -/*description: time from shut cocpu to disable clk*/ -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V) << (RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 +/*description: time from shut cocpu to disable clk.*/ +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 /* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: to shut cocpu*/ -#define RTC_CNTL_COCPU_SHUT (BIT(13)) -#define RTC_CNTL_COCPU_SHUT_M (BIT(13)) -#define RTC_CNTL_COCPU_SHUT_V 0x1 -#define RTC_CNTL_COCPU_SHUT_S 13 +/*description: to shut cocpu.*/ +#define RTC_CNTL_COCPU_SHUT (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_M (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_V 0x1 +#define RTC_CNTL_COCPU_SHUT_S 13 /* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ -/*description: time from start cocpu to give start interrupt*/ -#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F -#define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V) << (RTC_CNTL_COCPU_START_2_INTR_EN_S)) -#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F -#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 +/*description: time from start cocpu to give start interrupt.*/ +#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F +#define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S)) +#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F +#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 /* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ -/*description: time from start cocpu to pull down reset*/ -#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F -#define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V) << (RTC_CNTL_COCPU_START_2_RESET_DIS_S)) -#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F -#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 +/*description: time from start cocpu to pull down reset.*/ +#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F +#define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S)) +#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F +#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 /* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: cocpu clk force on*/ -#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) -#define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) -#define RTC_CNTL_COCPU_CLK_FO_V 0x1 -#define RTC_CNTL_COCPU_CLK_FO_S 0 +/*description: cocpu clk force on.*/ +#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_V 0x1 +#define RTC_CNTL_COCPU_CLK_FO_S 0 -#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0104) +#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x104) /* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ -/*description: the meas length (in 8MHz)*/ -#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF -#define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V) << (RTC_CNTL_TOUCH_MEAS_NUM_S)) -#define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF -#define RTC_CNTL_TOUCH_MEAS_NUM_S 16 +/*description: the meas length (in 8MHz).*/ +#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF +#define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S)) +#define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF +#define RTC_CNTL_TOUCH_MEAS_NUM_S 16 /* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */ -/*description: sleep cycles for timer*/ -#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V) << (RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 +/*description: sleep cycles for timer.*/ +#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 -#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0108) +#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x108) /* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: touch clock enable*/ -#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) -#define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) -#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 -#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 +/*description: touch clock enable.*/ +#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 +#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 /* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: touch clock force on*/ -#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) -#define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) -#define RTC_CNTL_TOUCH_CLK_FO_V 0x1 -#define RTC_CNTL_TOUCH_CLK_FO_S 30 +/*description: touch clock force on.*/ +#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_V 0x1 +#define RTC_CNTL_TOUCH_CLK_FO_S 30 /* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: reset upgrade touch*/ -#define RTC_CNTL_TOUCH_RESET (BIT(29)) -#define RTC_CNTL_TOUCH_RESET_M (BIT(29)) -#define RTC_CNTL_TOUCH_RESET_V 0x1 -#define RTC_CNTL_TOUCH_RESET_S 29 +/*description: reset upgrade touch.*/ +#define RTC_CNTL_TOUCH_RESET (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_M (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_V 0x1 +#define RTC_CNTL_TOUCH_RESET_S 29 /* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: force touch timer done*/ -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V) << (RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 +/*description: force touch timer done.*/ +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 /* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ -/*description: when a touch pad is active*/ -#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V) << (RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 +/*description: when a touch pad is active.*/ +#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 /* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */ -/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ -#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF -#define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V) << (RTC_CNTL_TOUCH_XPD_WAIT_S)) -#define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF -#define RTC_CNTL_TOUCH_XPD_WAIT_S 17 +/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD.*/ +#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF +#define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S)) +#define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF +#define RTC_CNTL_TOUCH_XPD_WAIT_S 17 /* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: 1: to start touch fsm by SW*/ -#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) -#define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) -#define RTC_CNTL_TOUCH_START_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_START_FORCE_S 16 +/*description: 1: to start touch fsm by SW.*/ +#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_START_FORCE_S 16 /* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 1: start touch fsm*/ -#define RTC_CNTL_TOUCH_START_EN (BIT(15)) -#define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) -#define RTC_CNTL_TOUCH_START_EN_V 0x1 -#define RTC_CNTL_TOUCH_START_EN_S 15 +/*description: 1: start touch fsm.*/ +#define RTC_CNTL_TOUCH_START_EN (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_V 0x1 +#define RTC_CNTL_TOUCH_START_EN_S 15 /* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ -#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) -#define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) -#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 -#define RTC_CNTL_TOUCH_START_FSM_EN_S 14 +/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm.*/ +#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 +#define RTC_CNTL_TOUCH_START_FSM_EN_S 14 /* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: touch timer enable bit*/ -#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 +/*description: touch timer enable bit.*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 /* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: 1:use self bias 0:use bandgap bias*/ -#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) -#define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) -#define RTC_CNTL_TOUCH_DBIAS_V 0x1 -#define RTC_CNTL_TOUCH_DBIAS_S 12 +/*description: 1:use self bias 0:use bandgap bias.*/ +#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_V 0x1 +#define RTC_CNTL_TOUCH_DBIAS_S 12 /* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: TOUCH pad0 reference cap*/ -#define RTC_CNTL_TOUCH_REFC 0x00000007 -#define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V) << (RTC_CNTL_TOUCH_REFC_S)) -#define RTC_CNTL_TOUCH_REFC_V 0x7 -#define RTC_CNTL_TOUCH_REFC_S 9 +/*description: TOUCH pad0 reference cap.*/ +#define RTC_CNTL_TOUCH_REFC 0x00000007 +#define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S)) +#define RTC_CNTL_TOUCH_REFC_V 0x7 +#define RTC_CNTL_TOUCH_REFC_S 9 /* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: TOUCH_XPD_BIAS*/ -#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) -#define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) -#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 -#define RTC_CNTL_TOUCH_XPD_BIAS_S 8 +/*description: TOUCH_XPD_BIAS.*/ +#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 +#define RTC_CNTL_TOUCH_XPD_BIAS_S 8 /* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ -/*description: TOUCH_DREFH*/ -#define RTC_CNTL_TOUCH_DREFH 0x00000003 -#define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V) << (RTC_CNTL_TOUCH_DREFH_S)) -#define RTC_CNTL_TOUCH_DREFH_V 0x3 -#define RTC_CNTL_TOUCH_DREFH_S 6 +/*description: TOUCH_DREFH.*/ +#define RTC_CNTL_TOUCH_DREFH 0x00000003 +#define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S)) +#define RTC_CNTL_TOUCH_DREFH_V 0x3 +#define RTC_CNTL_TOUCH_DREFH_S 6 /* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ -/*description: TOUCH_DREFL*/ -#define RTC_CNTL_TOUCH_DREFL 0x00000003 -#define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V) << (RTC_CNTL_TOUCH_DREFL_S)) -#define RTC_CNTL_TOUCH_DREFL_V 0x3 -#define RTC_CNTL_TOUCH_DREFL_S 4 +/*description: TOUCH_DREFL.*/ +#define RTC_CNTL_TOUCH_DREFL 0x00000003 +#define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S)) +#define RTC_CNTL_TOUCH_DREFL_V 0x3 +#define RTC_CNTL_TOUCH_DREFL_S 4 /* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ -/*description: TOUCH_DRANGE*/ -#define RTC_CNTL_TOUCH_DRANGE 0x00000003 -#define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V) << (RTC_CNTL_TOUCH_DRANGE_S)) -#define RTC_CNTL_TOUCH_DRANGE_V 0x3 -#define RTC_CNTL_TOUCH_DRANGE_S 2 +/*description: TOUCH_DRANGE.*/ +#define RTC_CNTL_TOUCH_DRANGE 0x00000003 +#define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S)) +#define RTC_CNTL_TOUCH_DRANGE_V 0x3 +#define RTC_CNTL_TOUCH_DRANGE_S 2 -#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x010C) +#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x10C) /* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ -/*description: select out ring pad*/ -#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F -#define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V) << (RTC_CNTL_TOUCH_OUT_RING_S)) -#define RTC_CNTL_TOUCH_OUT_RING_V 0xF -#define RTC_CNTL_TOUCH_OUT_RING_S 28 +/*description: select out ring pad.*/ +#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F +#define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S)) +#define RTC_CNTL_TOUCH_OUT_RING_V 0xF +#define RTC_CNTL_TOUCH_OUT_RING_S 28 /* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: touch7 buffer driver strength*/ -#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 -#define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V) << (RTC_CNTL_TOUCH_BUFDRV_S)) -#define RTC_CNTL_TOUCH_BUFDRV_V 0x7 -#define RTC_CNTL_TOUCH_BUFDRV_S 25 +/*description: touch7 buffer driver strength.*/ +#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 +#define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S)) +#define RTC_CNTL_TOUCH_BUFDRV_V 0x7 +#define RTC_CNTL_TOUCH_BUFDRV_S 25 /* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */ -/*description: touch scan mode pad enable map*/ -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V) << (RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 +/*description: touch scan mode pad enable map.*/ +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 /* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: touch pad14 will be used as shield*/ -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 +/*description: touch pad14 will be used as shield.*/ +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 /* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: inactive touch pads connect to 1: gnd 0: HighZ*/ -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 +/*description: inactive touch pads connect to 1: gnd 0: HighZ.*/ +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 /* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: touch pad0 will be used to de-noise*/ -#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) -#define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) -#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 -#define RTC_CNTL_TOUCH_DENOISE_EN_S 2 +/*description: touch pad0 will be used to de-noise.*/ +#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 +#define RTC_CNTL_TOUCH_DENOISE_EN_S 2 /* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */ -/*description: De-noise resolution: 12/10/8/4 bit*/ -#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 -#define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V) << (RTC_CNTL_TOUCH_DENOISE_RES_S)) -#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 -#define RTC_CNTL_TOUCH_DENOISE_RES_S 0 +/*description: De-noise resolution: 12/10/8/4 bit.*/ +#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 +#define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S)) +#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 +#define RTC_CNTL_TOUCH_DENOISE_RES_S 0 -#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x0110) -/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hF ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F -#define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V) << (RTC_CNTL_TOUCH_SLP_PAD_S)) -#define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F -#define RTC_CNTL_TOUCH_SLP_PAD_S 27 +#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x110) +/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hf ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F +#define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S)) +#define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F +#define RTC_CNTL_TOUCH_SLP_PAD_S 27 /* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: sleep pad approach function enable*/ -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 +/*description: sleep pad approach function enable.*/ +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 /* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: the threshold for sleep touch pad*/ -#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF -#define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V) << (RTC_CNTL_TOUCH_SLP_TH_S)) -#define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF -#define RTC_CNTL_TOUCH_SLP_TH_S 0 +/*description: the threshold for sleep touch pad.*/ +#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF +#define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S)) +#define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF +#define RTC_CNTL_TOUCH_SLP_TH_S 0 -#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x0114) +#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x114) /* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ -/*description: approach pads total meas times*/ -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V) << (RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 +/*description: approach pads total meas times.*/ +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 /* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: clear touch slp channel*/ -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 +/*description: clear touch slp channel.*/ +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 -#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0118) +#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x118) /* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: touch filter enable*/ -#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) -#define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) -#define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 -#define RTC_CNTL_TOUCH_FILTER_EN_S 31 +/*description: touch filter enable.*/ +#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 +#define RTC_CNTL_TOUCH_FILTER_EN_S 31 /* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ -/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ -#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 -#define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V) << (RTC_CNTL_TOUCH_FILTER_MODE_S)) -#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 -#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 +/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter.*/ +#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 +#define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S)) +#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 +#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 /* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ -/*description: debounce counter*/ -#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 -#define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V) << (RTC_CNTL_TOUCH_DEBOUNCE_S)) -#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 -#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 -/* RTC_CNTL_TOUCH_CONFIG3 : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_CONFIG3 0x00000003 -#define RTC_CNTL_TOUCH_CONFIG3_M ((RTC_CNTL_TOUCH_CONFIG3_V) << (RTC_CNTL_TOUCH_CONFIG3_S)) -#define RTC_CNTL_TOUCH_CONFIG3_V 0x3 -#define RTC_CNTL_TOUCH_CONFIG3_S 23 +/*description: debounce counter.*/ +#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 +#define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) +#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 +#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 +/* RTC_CNTL_TOUCH_HYSTERESIS : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 +#define RTC_CNTL_TOUCH_HYSTERESIS_M ((RTC_CNTL_TOUCH_HYSTERESIS_V)<<(RTC_CNTL_TOUCH_HYSTERESIS_S)) +#define RTC_CNTL_TOUCH_HYSTERESIS_V 0x3 +#define RTC_CNTL_TOUCH_HYSTERESIS_S 23 /* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 -#define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V) << (RTC_CNTL_TOUCH_NOISE_THRES_S)) -#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 -#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 -/* RTC_CNTL_TOUCH_CONFIG2 : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_CONFIG2 0x00000003 -#define RTC_CNTL_TOUCH_CONFIG2_M ((RTC_CNTL_TOUCH_CONFIG2_V) << (RTC_CNTL_TOUCH_CONFIG2_S)) -#define RTC_CNTL_TOUCH_CONFIG2_V 0x3 -#define RTC_CNTL_TOUCH_CONFIG2_S 19 -/* RTC_CNTL_TOUCH_CONFIG1 : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_CONFIG1 0x0000000F -#define RTC_CNTL_TOUCH_CONFIG1_M ((RTC_CNTL_TOUCH_CONFIG1_V) << (RTC_CNTL_TOUCH_CONFIG1_S)) -#define RTC_CNTL_TOUCH_CONFIG1_V 0xF -#define RTC_CNTL_TOUCH_CONFIG1_S 15 +/*description: .*/ +#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 +#define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) +#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 +#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 +/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M ((RTC_CNTL_TOUCH_NEG_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_THRES_S)) +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x3 +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 +/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ +/*description: negative threshold counter limit.*/ +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000F +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M ((RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S)) +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0xF +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 /* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ -/*description: touch jitter step*/ -#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F -#define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V) << (RTC_CNTL_TOUCH_JITTER_STEP_S)) -#define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF -#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 +/*description: touch jitter step.*/ +#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F +#define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S)) +#define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF +#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 /* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 -#define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V) << (RTC_CNTL_TOUCH_SMOOTH_LVL_S)) -#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 -#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 +/*description: .*/ +#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S)) +#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 /* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (BIT(8)) -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x1 -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8 -/* RTC_CNTL_TOUCH_BYPASS_NEG_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_BYPASS_NEG_THRES (BIT(7)) -#define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_M (BIT(7)) -#define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_V 0x1 -#define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_S 7 +/*description: .*/ +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (BIT(8)) +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x1 +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8 +/* RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(7)) +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_M (BIT(7)) +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_V 0x1 +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_S 7 -#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x011C) +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x11C) /* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 -#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 +/*description: .*/ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 /* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) -#define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) -#define RTC_CNTL_USB_RESET_DISABLE_V 0x1 -#define RTC_CNTL_USB_RESET_DISABLE_S 17 +/*description: .*/ +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_V 0x1 +#define RTC_CNTL_USB_RESET_DISABLE_S 17 /* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) -#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) -#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 -#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 +/*description: .*/ +#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 /* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_TX_EN (BIT(15)) -#define RTC_CNTL_USB_TX_EN_M (BIT(15)) -#define RTC_CNTL_USB_TX_EN_V 0x1 -#define RTC_CNTL_USB_TX_EN_S 15 +/*description: .*/ +#define RTC_CNTL_USB_TX_EN (BIT(15)) +#define RTC_CNTL_USB_TX_EN_M (BIT(15)) +#define RTC_CNTL_USB_TX_EN_V 0x1 +#define RTC_CNTL_USB_TX_EN_S 15 /* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_TXP (BIT(14)) -#define RTC_CNTL_USB_TXP_M (BIT(14)) -#define RTC_CNTL_USB_TXP_V 0x1 -#define RTC_CNTL_USB_TXP_S 14 +/*description: .*/ +#define RTC_CNTL_USB_TXP (BIT(14)) +#define RTC_CNTL_USB_TXP_M (BIT(14)) +#define RTC_CNTL_USB_TXP_V 0x1 +#define RTC_CNTL_USB_TXP_S 14 /* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_TXM (BIT(13)) -#define RTC_CNTL_USB_TXM_M (BIT(13)) -#define RTC_CNTL_USB_TXM_V 0x1 -#define RTC_CNTL_USB_TXM_S 13 +/*description: .*/ +#define RTC_CNTL_USB_TXM (BIT(13)) +#define RTC_CNTL_USB_TXM_M (BIT(13)) +#define RTC_CNTL_USB_TXM_V 0x1 +#define RTC_CNTL_USB_TXM_S 13 /* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) -#define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) -#define RTC_CNTL_USB_PAD_ENABLE_V 0x1 -#define RTC_CNTL_USB_PAD_ENABLE_S 12 +/*description: .*/ +#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_V 0x1 +#define RTC_CNTL_USB_PAD_ENABLE_S 12 /* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 +/*description: .*/ +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 /* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) -#define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) -#define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 -#define RTC_CNTL_USB_PULLUP_VALUE_S 10 +/*description: .*/ +#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 +#define RTC_CNTL_USB_PULLUP_VALUE_S 10 /* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) -#define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) -#define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 -#define RTC_CNTL_USB_DM_PULLDOWN_S 9 +/*description: .*/ +#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 +#define RTC_CNTL_USB_DM_PULLDOWN_S 9 /* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) -#define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) -#define RTC_CNTL_USB_DM_PULLUP_V 0x1 -#define RTC_CNTL_USB_DM_PULLUP_S 8 +/*description: .*/ +#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_V 0x1 +#define RTC_CNTL_USB_DM_PULLUP_S 8 /* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) -#define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) -#define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 -#define RTC_CNTL_USB_DP_PULLDOWN_S 7 +/*description: .*/ +#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 +#define RTC_CNTL_USB_DP_PULLDOWN_S 7 /* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) -#define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) -#define RTC_CNTL_USB_DP_PULLUP_V 0x1 -#define RTC_CNTL_USB_DP_PULLUP_S 6 +/*description: .*/ +#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_V 0x1 +#define RTC_CNTL_USB_DP_PULLUP_S 6 /* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 +/*description: .*/ +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 /* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) -#define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) -#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 -#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 +/*description: .*/ +#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 /* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_VREFL 0x00000003 -#define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V) << (RTC_CNTL_USB_VREFL_S)) -#define RTC_CNTL_USB_VREFL_V 0x3 -#define RTC_CNTL_USB_VREFL_S 2 +/*description: .*/ +#define RTC_CNTL_USB_VREFL 0x00000003 +#define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S)) +#define RTC_CNTL_USB_VREFL_V 0x3 +#define RTC_CNTL_USB_VREFL_S 2 /* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_VREFH 0x00000003 -#define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V) << (RTC_CNTL_USB_VREFH_S)) -#define RTC_CNTL_USB_VREFH_V 0x3 -#define RTC_CNTL_USB_VREFH_S 0 +/*description: .*/ +#define RTC_CNTL_USB_VREFH 0x00000003 +#define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S)) +#define RTC_CNTL_USB_VREFH_V 0x3 +#define RTC_CNTL_USB_VREFH_S 0 -#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0120) +#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x120) /* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) -#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) -#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 -#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 +/*description: .*/ +#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 /* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ -/*description: */ -#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V) << (RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 +/*description: .*/ +#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 -#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0124) +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x124) /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ -/*description: sleep reject cause*/ -#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF -#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V) << (RTC_CNTL_REJECT_CAUSE_S)) -#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF -#define RTC_CNTL_REJECT_CAUSE_S 0 +/*description: sleep reject cause.*/ +#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 -#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x0128) +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x128) /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 +/*description: .*/ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 -#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x012C) +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x12C) /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: sleep wakeup cause*/ -#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF -#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V) << (RTC_CNTL_WAKEUP_CAUSE_S)) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF -#define RTC_CNTL_WAKEUP_CAUSE_S 0 +/*description: sleep wakeup cause.*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 -#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0130) +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x130) /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ -/*description: sleep cycles for ULP-coprocessor timer*/ -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V) << (RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 +/*description: sleep cycles for ULP-coprocessor timer.*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 -#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0134) +#define RTC_CNTL_INT_ENA_RTC_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x134) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18 +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S 17 +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 /* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 /* RTC_CNTL_SARADC2_INT_ENA_W1TS : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt*/ -#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ENA_W1TS_M (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SARADC2_INT_ENA_W1TS_S 14 +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_S 14 /* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt*/ -#define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) -#define RTC_CNTL_COCPU_INT_ENA_W1TS_M (BIT(13)) -#define RTC_CNTL_COCPU_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_COCPU_INT_ENA_W1TS_S 13 +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TS_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_W1TS_S 13 /* RTC_CNTL_TSENS_INT_ENA_W1TS : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt*/ -#define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) -#define RTC_CNTL_TSENS_INT_ENA_W1TS_M (BIT(12)) -#define RTC_CNTL_TSENS_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_TSENS_INT_ENA_W1TS_S 12 +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TS_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_W1TS_S 12 /* RTC_CNTL_SARADC1_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt*/ -#define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ENA_W1TS_M (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SARADC1_INT_ENA_W1TS_S 11 +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S 8 +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S 7 +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S 6 +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S 6 /* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt*/ -#define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S 5 +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4 +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4 /* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2 +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 -#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0138) +#define RTC_CNTL_INT_ENA_RTC_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x138) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(20)) -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18 +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S 17 +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 /* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 /* RTC_CNTL_SARADC2_INT_ENA_W1TC : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt*/ -#define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ENA_W1TC_M (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SARADC2_INT_ENA_W1TC_S 14 +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_S 14 /* RTC_CNTL_COCPU_INT_ENA_W1TC : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt*/ -#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) -#define RTC_CNTL_COCPU_INT_ENA_W1TC_M (BIT(13)) -#define RTC_CNTL_COCPU_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_COCPU_INT_ENA_W1TC_S 13 +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TC_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_W1TC_S 13 /* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt*/ -#define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) -#define RTC_CNTL_TSENS_INT_ENA_W1TC_M (BIT(12)) -#define RTC_CNTL_TSENS_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_TSENS_INT_ENA_W1TC_S 12 +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TC_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_W1TC_S 12 /* RTC_CNTL_SARADC1_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt*/ -#define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ENA_W1TC_M (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SARADC1_INT_ENA_W1TC_S 11 +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S 8 +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S 7 +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S 6 +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S 6 /* RTC_CNTL_ULP_CP_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt*/ -#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S 5 +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4 +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4 /* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2 +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 -#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x013c) +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x13C) /* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ -/*description: wait cycles for rention operation*/ -#define RTC_CNTL_RETENTION_WAIT 0x0000001F +/*description: wait cycles for rention operation.*/ +#define RTC_CNTL_RETENTION_WAIT 0x0000001F #define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) #define RTC_CNTL_RETENTION_WAIT_V 0x1F #define RTC_CNTL_RETENTION_WAIT_S 27 /* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_EN (BIT(26)) +/*description: .*/ +#define RTC_CNTL_RETENTION_EN (BIT(26)) #define RTC_CNTL_RETENTION_EN_M (BIT(26)) #define RTC_CNTL_RETENTION_EN_V 0x1 #define RTC_CNTL_RETENTION_EN_S 26 -#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0140) +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x140) /* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: select use analog fib signal*/ -#define RTC_CNTL_FIB_SEL 0x00000007 +/*description: select use analog fib signal.*/ +#define RTC_CNTL_FIB_SEL 0x00000007 #define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) #define RTC_CNTL_FIB_SEL_V 0x7 #define RTC_CNTL_FIB_SEL_S 0 -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0144) -/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003251 ; */ -/*description: */ -#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF -#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V) << (RTC_CNTL_CNTL_DATE_S)) -#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF -#define RTC_CNTL_CNTL_DATE_S 0 +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x144) +/* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003251 ; */ +/*description: .*/ +#define RTC_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S)) +#define RTC_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_DATE_S 0 + #ifdef __cplusplus } #endif + + #endif /*_SOC_RTC_CNTL_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h index cc0a235363..a9408be766 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,957 +11,960 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_RTC_CNTL_STRUCT_H_ +#define _SOC_RTC_CNTL_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { union { struct { - uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ - uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ - uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ - uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ - uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ - uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ - uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ - uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ - uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ - uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ - uint32_t xtl_force_pd: 1; /*crystall force power down*/ - uint32_t xtl_force_pu: 1; /*crystall force power up*/ - uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/ - uint32_t reserved18: 5; - uint32_t xtl_force_iso: 1; - uint32_t pll_force_iso: 1; - uint32_t analog_force_iso: 1; - uint32_t xtl_force_noiso: 1; - uint32_t pll_force_noiso: 1; - uint32_t analog_force_noiso: 1; - uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ - uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ - uint32_t sw_sys_rst: 1; /*SW system reset*/ + uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0 : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst : 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst : 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd : 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu : 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd : 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu : 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd : 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu : 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd : 1; /*crystall force power down*/ + uint32_t xtl_force_pu : 1; /*crystall force power up*/ + uint32_t xtl_en_wait : 4; /*wait bias_sleep and current source wakeup*/ + uint32_t reserved18 : 5; + uint32_t xtl_force_iso : 1; + uint32_t pll_force_iso : 1; + uint32_t analog_force_iso : 1; + uint32_t xtl_force_noiso : 1; + uint32_t pll_force_noiso : 1; + uint32_t analog_force_noiso : 1; + uint32_t dg_wrap_force_rst : 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst : 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst : 1; /*SW system reset*/ }; uint32_t val; } options0; - uint32_t slp_timer0; /**/ + uint32_t slp_timer0; union { struct { - uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ - uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ - uint32_t reserved17: 15; + uint32_t slp_val_hi : 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en : 1; /*timer alarm enable bit*/ + uint32_t reserved17 : 15; }; uint32_t val; } slp_timer1; union { struct { - uint32_t reserved0: 27; - uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ - uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ - uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ - uint32_t reserved30: 1; - uint32_t update: 1; /*Set 1: to update register with RTC timer*/ + uint32_t reserved0 : 27; + uint32_t timer_sys_stall : 1; /*Enable to record system stall time*/ + uint32_t timer_xtl_off : 1; /*Enable to record 40M XTAL OFF time*/ + uint32_t timer_sys_rst : 1; /*enable to record system reset time*/ + uint32_t reserved30 : 1; + uint32_t update : 1; /*Set 1: to update register with RTC timer*/ }; uint32_t val; } time_update; - uint32_t time_low0; /*RTC timer low 32 bits*/ + uint32_t time_low0; union { struct { - uint32_t rtc_timer_value0_high: 16; /*RTC timer high 16 bits*/ - uint32_t reserved16: 16; + uint32_t rtc_timer_value0_high : 16; /*RTC timer high 16 bits*/ + uint32_t reserved16 : 16; }; uint32_t val; } time_high0; union { struct { - uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/ - uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/ - uint32_t reserved2: 20; - uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/ - uint32_t reserved23: 5; - uint32_t sdio_active_ind: 1; /*SDIO active indication*/ - uint32_t slp_wakeup: 1; /*leep wakeup bit*/ - uint32_t slp_reject: 1; /*leep reject bit*/ - uint32_t sleep_en: 1; /*sleep enable bit*/ + uint32_t rtc_sw_cpu_int : 1; /*rtc software interrupt to main cpu*/ + uint32_t rtc_slp_reject_cause_clr : 1; /*clear rtc sleep reject cause*/ + uint32_t reserved2 : 20; + uint32_t apb2rtc_bridge_sel : 1; /*1: APB to RTC using bridge*/ + uint32_t reserved23 : 5; + uint32_t sdio_active_ind : 1; /*SDIO active indication*/ + uint32_t slp_wakeup : 1; /*leep wakeup bit*/ + uint32_t slp_reject : 1; /*leep reject bit*/ + uint32_t sleep_en : 1; /*sleep enable bit*/ }; uint32_t val; } state0; union { struct { - uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ - uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ - uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ - uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ - uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ + uint32_t cpu_stall_en : 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait : 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait : 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait : 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait : 8; /*PLL wait cycles in slow_clk_rtc*/ }; uint32_t val; } timer1; union { struct { - uint32_t reserved0: 15; - uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ - uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + uint32_t reserved0 : 15; + uint32_t ulpcp_touch_start_wait : 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ + uint32_t min_time_ck8m_off : 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ }; uint32_t val; } timer2; union { struct { - uint32_t wifi_wait_timer: 9; - uint32_t wifi_powerup_timer: 7; - uint32_t rom_ram_wait_timer: 9; - uint32_t rom_ram_powerup_timer: 7; + uint32_t wifi_wait_timer : 9; + uint32_t wifi_powerup_timer : 7; + uint32_t rom_ram_wait_timer : 9; + uint32_t rom_ram_powerup_timer : 7; }; uint32_t val; } timer3; union { struct { - uint32_t rtc_wait_timer: 9; - uint32_t rtc_powerup_timer: 7; - uint32_t dg_wrap_wait_timer: 9; - uint32_t dg_wrap_powerup_timer: 7; + uint32_t rtc_wait_timer : 9; + uint32_t rtc_powerup_timer : 7; + uint32_t dg_wrap_wait_timer : 9; + uint32_t dg_wrap_powerup_timer : 7; }; uint32_t val; } timer4; union { struct { - uint32_t reserved0: 8; - uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ - uint32_t rtcmem_wait_timer: 9; - uint32_t rtcmem_powerup_timer: 7; + uint32_t reserved0 : 8; + uint32_t min_slp_val : 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t rtcmem_wait_timer : 9; + uint32_t rtcmem_powerup_timer : 7; }; uint32_t val; } timer5; union { struct { - uint32_t reserved0: 16; - uint32_t dg_dcdc_wait_timer: 9; - uint32_t dg_dcdc_powerup_timer: 7; + uint32_t reserved0 : 16; + uint32_t dg_dcdc_wait_timer : 9; + uint32_t dg_dcdc_powerup_timer : 7; }; uint32_t val; } timer6; union { struct { - uint32_t reserved0: 18; - uint32_t i2c_reset_por_force_pd: 1; - uint32_t i2c_reset_por_force_pu: 1; - uint32_t glitch_rst_en: 1; - uint32_t reserved21: 1; /*PLLA force power down*/ - uint32_t sar_i2c_pu: 1; /*PLLA force power up*/ - uint32_t plla_force_pd: 1; /*PLLA force power down*/ - uint32_t plla_force_pu: 1; /*PLLA force power up*/ - uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ - uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/ - uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/ - uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/ - uint32_t reserved29: 1; - uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/ - uint32_t pll_i2c_pu: 1; + uint32_t reserved0 : 18; + uint32_t i2c_reset_por_force_pd : 1; + uint32_t i2c_reset_por_force_pu : 1; + uint32_t glitch_rst_en : 1; + uint32_t reserved21 : 1; /*PLLA force power down*/ + uint32_t sar_i2c_pu : 1; /*PLLA force power up*/ + uint32_t plla_force_pd : 1; /*PLLA force power down*/ + uint32_t plla_force_pu : 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start : 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu : 1; /*1: PVTMON power up*/ + uint32_t txrf_i2c_pu : 1; /*1: TXRF_I2C power up*/ + uint32_t rfrx_pbus_pu : 1; /*1: RFRX_PBUS power up*/ + uint32_t reserved29 : 1; + uint32_t ckgen_i2c_pu : 1; /*1: CKGEN_I2C power up*/ + uint32_t pll_i2c_pu : 1; }; uint32_t val; } ana_conf; union { struct { - uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ - uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ - uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/ - uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/ - uint32_t reset_flag_procpu: 1; /*PRO CPU reset_flag*/ - uint32_t reset_flag_appcpu: 1; /*APP CPU reset flag*/ - uint32_t reset_flag_procpu_clr: 1; /*clear PRO CPU reset_flag*/ - uint32_t reset_flag_appcpu_clr: 1; /*clear APP CPU reset flag*/ - uint32_t appcpu_ocd_halt_on_reset: 1; /*APPCPU OcdHaltOnReset*/ - uint32_t procpu_ocd_halt_on_reset: 1; /*PROCPU OcdHaltOnReset*/ - uint32_t reset_flag_jtag_procpu: 1; - uint32_t reset_flag_jtag_appcpu: 1; - uint32_t reset_flag_jtag_procpu_clr: 1; - uint32_t reset_flag_jtag_appcpu_clr: 1; - uint32_t rtc_app_dreset_mask: 1; - uint32_t rtc_pro_dreset_mask: 1; - uint32_t reserved26: 6; + uint32_t reset_cause_procpu : 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu : 6; /*reset cause of APP CPU*/ + uint32_t appcpu_stat_vector_sel : 1; /*APP CPU state vector sel*/ + uint32_t procpu_stat_vector_sel : 1; /*PRO CPU state vector sel*/ + uint32_t reset_flag_procpu : 1; /*PRO CPU reset_flag*/ + uint32_t reset_flag_appcpu : 1; /*APP CPU reset flag*/ + uint32_t reset_flag_procpu_clr : 1; /*clear PRO CPU reset_flag*/ + uint32_t reset_flag_appcpu_clr : 1; /*clear APP CPU reset flag*/ + uint32_t appcpu_ocd_halt_on_reset : 1; /*APPCPU OcdHaltOnReset*/ + uint32_t procpu_ocd_halt_on_reset : 1; /*PROCPU OcdHaltOnReset*/ + uint32_t reset_flag_jtag_procpu : 1; + uint32_t reset_flag_jtag_appcpu : 1; + uint32_t reset_flag_jtag_procpu_clr : 1; + uint32_t reset_flag_jtag_appcpu_clr : 1; + uint32_t rtc_app_dreset_mask : 1; + uint32_t rtc_pro_dreset_mask : 1; + uint32_t reserved26 : 6; }; uint32_t val; } reset_state; union { struct { - uint32_t reserved0: 15; - uint32_t rtc_wakeup_ena: 17; /*wakeup enable bitmap*/ + uint32_t reserved0 : 15; + uint32_t rtc_wakeup_ena : 17; /*wakeup enable bitmap*/ }; uint32_t val; } wakeup_state; union { struct { - uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ - uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ - uint32_t rtc_touch_scan_done: 1; /*enable touch scan done interrupt*/ - uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ - uint32_t rtc_touch_done: 1; /*enable touch done interrupt*/ - uint32_t rtc_touch_active: 1; /*enable touch active interrupt*/ - uint32_t rtc_touch_inactive: 1; /*enable touch inactive interrupt*/ - uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ - uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/ - uint32_t rtc_tsens: 1; /*enable tsens interrupt*/ - uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/ - uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/ - uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ - uint32_t rtc_cocpu_trap: 1; /*enable cocpu trap interrupt*/ - uint32_t rtc_touch_timeout: 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_touch_approach_loop_done: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup : 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject : 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle : 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt : 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done : 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp : 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done : 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active : 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive : 1; /*enable touch inactive interrupt*/ + uint32_t rtc_brown_out : 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer : 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1 : 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens : 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu : 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2 : 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd : 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead : 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap : 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout : 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done : 1; + uint32_t reserved21 : 11; }; uint32_t val; } int_ena; union { struct { - uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ - uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ - uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ - uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ - uint32_t rtc_touch_scan_done: 1; - uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ - uint32_t rtc_touch_done: 1; /*touch interrupt raw*/ - uint32_t rtc_touch_active: 1; /*touch active interrupt raw*/ - uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt raw*/ - uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ - uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ - uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/ - uint32_t rtc_tsens: 1; /*tsens interrupt raw*/ - uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/ - uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/ - uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/ - uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/ - uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt raw*/ - uint32_t rtc_touch_timeout: 1; /*touch timeout interrupt raw*/ - uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/ - uint32_t rtc_touch_approach_loop_done: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup : 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject : 1; /*sleep reject interrupt raw*/ + uint32_t sdio_idle : 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt : 1; /*RTC WDT interrupt raw*/ + uint32_t rtc_touch_scan_done : 1; + uint32_t rtc_ulp_cp : 1; /*ULP-coprocessor interrupt raw*/ + uint32_t rtc_touch_done : 1; /*touch interrupt raw*/ + uint32_t rtc_touch_active : 1; /*touch active interrupt raw*/ + uint32_t rtc_touch_inactive : 1; /*touch inactive interrupt raw*/ + uint32_t rtc_brown_out : 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer : 1; /*RTC main timer interrupt raw*/ + uint32_t rtc_saradc1 : 1; /*saradc1 interrupt raw*/ + uint32_t rtc_tsens : 1; /*tsens interrupt raw*/ + uint32_t rtc_cocpu : 1; /*riscV cocpu interrupt raw*/ + uint32_t rtc_saradc2 : 1; /*saradc2 interrupt raw*/ + uint32_t rtc_swd : 1; /*super watch dog interrupt raw*/ + uint32_t rtc_xtal32k_dead : 1; /*xtal32k dead detection interrupt raw*/ + uint32_t rtc_cocpu_trap : 1; /*cocpu trap interrupt raw*/ + uint32_t rtc_touch_timeout : 1; /*touch timeout interrupt raw*/ + uint32_t rtc_glitch_det : 1; /*glitch_det_interrupt_raw*/ + uint32_t rtc_touch_approach_loop_done : 1; + uint32_t reserved21 : 11; }; uint32_t val; } int_raw; union { struct { - uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ - uint32_t slp_reject: 1; /*sleep reject interrupt state*/ - uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ - uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ - uint32_t rtc_touch_scan_done: 1; - uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/ - uint32_t rtc_touch_done: 1; /*touch done interrupt state*/ - uint32_t rtc_touch_active: 1; /*touch active interrupt state*/ - uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt state*/ - uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ - uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ - uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/ - uint32_t rtc_tsens: 1; /*tsens interrupt state*/ - uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/ - uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/ - uint32_t rtc_swd: 1; /*super watch dog interrupt state*/ - uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/ - uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt state*/ - uint32_t rtc_touch_timeout: 1; /*Touch timeout interrupt state*/ - uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/ - uint32_t rtc_touch_approach_loop_done: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup : 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject : 1; /*sleep reject interrupt state*/ + uint32_t sdio_idle : 1; /*SDIO idle interrupt state*/ + uint32_t rtc_wdt : 1; /*RTC WDT interrupt state*/ + uint32_t rtc_touch_scan_done : 1; + uint32_t rtc_ulp_cp : 1; /*ULP-coprocessor interrupt state*/ + uint32_t rtc_touch_done : 1; /*touch done interrupt state*/ + uint32_t rtc_touch_active : 1; /*touch active interrupt state*/ + uint32_t rtc_touch_inactive : 1; /*touch inactive interrupt state*/ + uint32_t rtc_brown_out : 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer : 1; /*RTC main timer interrupt state*/ + uint32_t rtc_saradc1 : 1; /*saradc1 interrupt state*/ + uint32_t rtc_tsens : 1; /*tsens interrupt state*/ + uint32_t rtc_cocpu : 1; /*riscV cocpu interrupt state*/ + uint32_t rtc_saradc2 : 1; /*saradc2 interrupt state*/ + uint32_t rtc_swd : 1; /*super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead : 1; /*xtal32k dead detection interrupt state*/ + uint32_t rtc_cocpu_trap : 1; /*cocpu trap interrupt state*/ + uint32_t rtc_touch_timeout : 1; /*Touch timeout interrupt state*/ + uint32_t rtc_glitch_det : 1; /*glitch_det_interrupt state*/ + uint32_t rtc_touch_approach_loop_done : 1; + uint32_t reserved21 : 11; }; uint32_t val; } int_st; union { struct { - uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ - uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ - uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ - uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ - uint32_t rtc_touch_scan_done: 1; - uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/ - uint32_t rtc_touch_done: 1; /*Clear touch done interrupt state*/ - uint32_t rtc_touch_active: 1; /*Clear touch active interrupt state*/ - uint32_t rtc_touch_inactive: 1; /*Clear touch inactive interrupt state*/ - uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ - uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ - uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/ - uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/ - uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/ - uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/ - uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/ - uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/ - uint32_t rtc_cocpu_trap: 1; /*Clear cocpu trap interrupt state*/ - uint32_t rtc_touch_timeout: 1; /*Clear touch timeout interrupt state*/ - uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/ - uint32_t rtc_touch_approach_loop_done: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup : 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject : 1; /*Clear sleep reject interrupt state*/ + uint32_t sdio_idle : 1; /*Clear SDIO idle interrupt state*/ + uint32_t rtc_wdt : 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_touch_scan_done : 1; + uint32_t rtc_ulp_cp : 1; /*Clear ULP-coprocessor interrupt state*/ + uint32_t rtc_touch_done : 1; /*Clear touch done interrupt state*/ + uint32_t rtc_touch_active : 1; /*Clear touch active interrupt state*/ + uint32_t rtc_touch_inactive : 1; /*Clear touch inactive interrupt state*/ + uint32_t rtc_brown_out : 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer : 1; /*Clear RTC main timer interrupt state*/ + uint32_t rtc_saradc1 : 1; /*Clear saradc1 interrupt state*/ + uint32_t rtc_tsens : 1; /*Clear tsens interrupt state*/ + uint32_t rtc_cocpu : 1; /*Clear riscV cocpu interrupt state*/ + uint32_t rtc_saradc2 : 1; /*Clear saradc2 interrupt state*/ + uint32_t rtc_swd : 1; /*Clear super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead : 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_cocpu_trap : 1; /*Clear cocpu trap interrupt state*/ + uint32_t rtc_touch_timeout : 1; /*Clear touch timeout interrupt state*/ + uint32_t rtc_glitch_det : 1; /*Clear glitch det interrupt state*/ + uint32_t rtc_touch_approach_loop_done : 1; + uint32_t reserved21 : 11; }; uint32_t val; } int_clr; - uint32_t store[4]; /**/ + uint32_t store[4]; union { struct { - uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/ - uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/ - uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/ - uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/ - uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/ - uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/ - uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/ - uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/ - uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/ - uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/ - uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/ - uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/ - uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ - uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/ - uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/ - uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/ - uint32_t reserved24: 6; - uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/ - uint32_t ctr_en: 1; + uint32_t xtal32k_en : 1; /*xtal 32k watch dog enable*/ + uint32_t xtal32k_wdt_clk_fo : 1; /*xtal 32k watch dog clock force on*/ + uint32_t xtal32k_wdt_reset : 1; /*xtal 32k watch dog sw reset*/ + uint32_t xtal32k_ext_clk_fo : 1; /*xtal 32k external xtal clock force on*/ + uint32_t xtal32k_auto_backup : 1; /*xtal 32k switch to back up clock when xtal is dead*/ + uint32_t xtal32k_auto_restart : 1; /*xtal 32k restart xtal when xtal is dead*/ + uint32_t xtal32k_auto_return : 1; /*xtal 32k switch back xtal when xtal is restarted*/ + uint32_t xtal32k_xpd_force : 1; /*Xtal 32k xpd control by sw or fsm*/ + uint32_t enckinit_xtal_32k : 1; /*apply an internal clock to help xtal 32k to start*/ + uint32_t dbuf_xtal_32k : 1; /*0: single-end buffer 1: differential buffer*/ + uint32_t dgm_xtal_32k : 3; /*xtal_32k gm control*/ + uint32_t dres_xtal_32k : 3; /*DRES_XTAL_32K*/ + uint32_t xpd_xtal_32k : 1; /*XPD_XTAL_32K*/ + uint32_t dac_xtal_32k : 3; /*DAC_XTAL_32K*/ + uint32_t rtc_wdt_state : 3; /*state of 32k_wdt*/ + uint32_t rtc_xtal32k_gpio_sel : 1; /*XTAL_32K sel. 0: external XTAL_32K*/ + uint32_t reserved24 : 6; + uint32_t ctr_lv : 1; /*0: power down XTAL at high level*/ + uint32_t ctr_en : 1; }; uint32_t val; } ext_xtl_conf; union { struct { - uint32_t reserved0: 29; - uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ - uint32_t wakeup0_lv: 1; /*0: external wakeup at low level*/ - uint32_t wakeup1_lv: 1; + uint32_t reserved0 : 29; + uint32_t gpio_wakeup_filter : 1; /*enable filter for gpio wakeup event*/ + uint32_t ext_wakeup0_lv : 1; /*0: external wakeup at low level*/ + uint32_t ext_wakeup1_lv : 1; }; uint32_t val; } ext_wakeup_conf; union { struct { - uint32_t reserved0: 12; - uint32_t rtc_sleep_reject_ena: 18; /*sleep reject enable*/ - uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ - uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ + uint32_t reserved0 : 12; + uint32_t rtc_sleep_reject_ena : 18; /*sleep reject enable*/ + uint32_t light_slp_reject_en : 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en : 1; /*enable reject for deep sleep*/ }; uint32_t val; } slp_reject_conf; union { struct { - uint32_t reserved0: 29; - uint32_t cpusel_conf: 1; /*CPU sel option*/ - uint32_t cpuperiod_sel: 2; + uint32_t reserved0 : 29; + uint32_t cpusel_conf : 1; /*CPU sel option*/ + uint32_t cpuperiod_sel : 2; }; uint32_t val; } cpu_period_conf; union { struct { - uint32_t reserved0: 22; - uint32_t sdio_act_dnum: 10; + uint32_t reserved0 : 22; + uint32_t sdio_act_dnum : 10; }; uint32_t val; } sdio_act_conf; union { struct { - uint32_t reserved0: 3; - uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ - uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/ - uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ - uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/ - uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ - uint32_t reserved11: 1; - uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ - uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ - uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ - uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ - uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ - uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ - uint32_t reserved27: 2; - uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ - uint32_t ana_clk_rtc_sel: 2; + uint32_t reserved0 : 3; + uint32_t ck8m_div_sel_vld : 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ + uint32_t ck8m_div : 2; /*CK8M_D256_OUT divider. 00: div128*/ + uint32_t enb_ck8m : 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div : 1; /*1: CK8M_D256_OUT is actually CK8M*/ + uint32_t dig_xtal32k_en : 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en : 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en : 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t reserved11 : 1; + uint32_t ck8m_div_sel : 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating : 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating : 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq : 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd : 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu : 1; /*CK8M force power up*/ + uint32_t reserved27 : 2; + uint32_t fast_clk_rtc_sel : 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ + uint32_t ana_clk_rtc_sel : 2; }; uint32_t val; } clk_conf; union { struct { - uint32_t reserved0: 22; - uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ - uint32_t rtc_ana_clk_div: 8; - uint32_t slow_clk_next_edge: 1; + uint32_t reserved0 : 22; + uint32_t rtc_ana_clk_div_vld : 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ + uint32_t rtc_ana_clk_div : 8; + uint32_t slow_clk_next_edge : 1; }; uint32_t val; } slow_clk_conf; union { struct { - uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ - uint32_t reserved8: 1; - uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ - uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/ - uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/ - uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/ - uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ - uint32_t sdio_modecurlim: 1; /*select current limit mode*/ - uint32_t sdio_encurlim: 1; /*enable current limit*/ - uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ - uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/ - uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ - uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ - uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t xpd_sdio: 1; + uint32_t sdio_timer_target : 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ + uint32_t reserved8 : 1; + uint32_t sdio_dthdrv : 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ + uint32_t sdio_dcap : 2; /*ability to prevent LDO from overshoot*/ + uint32_t sdio_initi : 2; /*add resistor from ldo output to ground. 0: no res*/ + uint32_t sdio_en_initi : 1; /*0 to set init[1:0]=0*/ + uint32_t sdio_dcurlim : 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ + uint32_t sdio_modecurlim : 1; /*select current limit mode*/ + uint32_t sdio_encurlim : 1; /*enable current limit*/ + uint32_t sdio_pd_en : 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force : 1; /*1: use SW option to control SDIO_REG*/ + uint32_t sdio_tieh : 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready : 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio : 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio : 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio : 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio : 1; }; uint32_t val; } sdio_conf; union { struct { - uint32_t reserved0: 10; - uint32_t bias_buf_idle: 1; - uint32_t bias_buf_wake: 1; - uint32_t bias_buf_deep_slp: 1; - uint32_t bias_buf_monitor: 1; - uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/ - uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/ - uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/ - uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/ - uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/ - uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/ - uint32_t reserved26: 6; + uint32_t reserved0 : 10; + uint32_t bias_buf_idle : 1; + uint32_t bias_buf_wake : 1; + uint32_t bias_buf_deep_slp : 1; + uint32_t bias_buf_monitor : 1; + uint32_t pd_cur_deep_slp : 1; /*xpd cur when rtc in sleep_state*/ + uint32_t pd_cur_monitor : 1; /*xpd cur when rtc in monitor state*/ + uint32_t bias_sleep_deep_slp : 1; /*bias_sleep when rtc in sleep_state*/ + uint32_t bias_sleep_monitor : 1; /*bias_sleep when rtc in monitor state*/ + uint32_t dbg_atten_deep_slp : 4; /*DBG_ATTEN when rtc in sleep state*/ + uint32_t dbg_atten_monitor : 4; /*DBG_ATTEN when rtc in monitor state*/ + uint32_t reserved26 : 6; }; uint32_t val; } bias_conf; union { struct { - uint32_t reserved0: 7; - uint32_t dig_cal_en: 1; - uint32_t reserved8: 6; - uint32_t sck_dcap: 8; /*SCK_DCAP*/ - uint32_t reserved22: 6; - uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ - uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ - uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ - uint32_t rtculator_force_pu: 1; + uint32_t reserved0 : 7; + uint32_t dig_cal_en : 1; + uint32_t reserved8 : 6; + uint32_t sck_dcap : 8; /*SCK_DCAP*/ + uint32_t reserved22 : 6; + uint32_t rtc_dboost_force_pd : 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu : 1; /*RTC_DBOOST force power up*/ + uint32_t rtculator_force_pd : 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtculator_force_pu : 1; }; uint32_t val; } rtc; union { struct { - uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/ - uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/ - uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/ - uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/ - uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/ - uint32_t rtc_force_noiso: 1; /*rtc_peri force no ISO*/ - uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU*/ - uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/ - uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/ - uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU*/ - uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/ - uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/ - uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/ - uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/ - uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/ - uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/ - uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/ - uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/ - uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/ - uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/ - uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/ - uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/ - uint32_t reserved22: 10; + uint32_t rtc_fastmem_force_noiso : 1; /*Fast RTC memory force no ISO*/ + uint32_t rtc_fastmem_force_iso : 1; /*Fast RTC memory force ISO*/ + uint32_t rtc_slowmem_force_noiso : 1; /*RTC memory force no ISO*/ + uint32_t rtc_slowmem_force_iso : 1; /*RTC memory force ISO*/ + uint32_t rtc_force_iso : 1; /*rtc_peri force ISO*/ + uint32_t rtc_force_noiso : 1; /*rtc_peri force no ISO*/ + uint32_t rtc_fastmem_folw_cpu : 1; /*1: Fast RTC memory PD following CPU*/ + uint32_t fastmem_force_lpd : 1; /*Fast RTC memory force PD*/ + uint32_t fastmem_force_lpu : 1; /*Fast RTC memory force no PD*/ + uint32_t rtc_slowmem_folw_cpu : 1; /*1: RTC memory PD following CPU*/ + uint32_t rtc_slowmem_force_lpd : 1; /*RTC memory force PD*/ + uint32_t rtc_slowmem_force_lpu : 1; /*RTC memory force no PD*/ + uint32_t rtc_fastmem_force_pd : 1; /*Fast RTC memory force power down*/ + uint32_t rtc_fastmem_force_pu : 1; /*Fast RTC memory force power up*/ + uint32_t rtc_fastmem_pd_en : 1; /*enable power down fast RTC memory in sleep*/ + uint32_t rtc_slowmem_force_pd : 1; /*RTC memory force power down*/ + uint32_t rtc_slowmem_force_pu : 1; /*RTC memory force power up*/ + uint32_t rtc_slowmem_pd_en : 1; /*enable power down RTC memory in sleep*/ + uint32_t rtc_force_pd : 1; /*rtc_peri force power down*/ + uint32_t rtc_force_pu : 1; /*rtc_peri force power up*/ + uint32_t rtc_pd_en : 1; /*enable power down rtc_peri in sleep */ + uint32_t rtc_pad_force_hold : 1; /*rtc pad force hold*/ + uint32_t reserved22 : 10; }; uint32_t val; - } rtc_pwc; + } pwc; union { struct { - uint32_t reserved0: 3; - uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ - uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ - uint32_t rom0_force_pd: 1; /*ROM force power down*/ - uint32_t rom0_force_pu: 1; /*ROM force power up*/ - uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/ - uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/ - uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/ - uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/ - uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/ - uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/ - uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/ - uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/ - uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/ - uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/ - uint32_t wifi_force_pd: 1; /*wifi force power down*/ - uint32_t wifi_force_pu: 1; /*wifi force power up*/ - uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ - uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ - uint32_t dg_dcdc_force_pd: 1; /*digital dcdc force power down*/ - uint32_t dg_dcdc_force_pu: 1; /*digital dcdc force power up*/ - uint32_t dg_dcdc_pd_en: 1; /*enable power down digital dcdc in sleep*/ - uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/ - uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/ - uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/ - uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/ - uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/ - uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/ - uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ - uint32_t dg_wrap_pd_en: 1; + uint32_t reserved0 : 3; + uint32_t lslp_mem_force_pd : 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu : 1; /*memories in digital core force no PD in sleep*/ + uint32_t rom0_force_pd : 1; /*ROM force power down*/ + uint32_t rom0_force_pu : 1; /*ROM force power up*/ + uint32_t inter_ram0_force_pd : 1; /*internal SRAM 0 force power down*/ + uint32_t inter_ram0_force_pu : 1; /*internal SRAM 0 force power up*/ + uint32_t inter_ram1_force_pd : 1; /*internal SRAM 1 force power down*/ + uint32_t inter_ram1_force_pu : 1; /*internal SRAM 1 force power up*/ + uint32_t inter_ram2_force_pd : 1; /*internal SRAM 2 force power down*/ + uint32_t inter_ram2_force_pu : 1; /*internal SRAM 2 force power up*/ + uint32_t inter_ram3_force_pd : 1; /*internal SRAM 3 force power down*/ + uint32_t inter_ram3_force_pu : 1; /*internal SRAM 3 force power up*/ + uint32_t inter_ram4_force_pd : 1; /*internal SRAM 4 force power down*/ + uint32_t inter_ram4_force_pu : 1; /*internal SRAM 4 force power up*/ + uint32_t wifi_force_pd : 1; /*wifi force power down*/ + uint32_t wifi_force_pu : 1; /*wifi force power up*/ + uint32_t dg_wrap_force_pd : 1; /*digital core force power down*/ + uint32_t dg_wrap_force_pu : 1; /*digital core force power up*/ + uint32_t dg_dcdc_force_pd : 1; /*digital dcdc force power down*/ + uint32_t dg_dcdc_force_pu : 1; /*digital dcdc force power up*/ + uint32_t dg_dcdc_pd_en : 1; /*enable power down digital dcdc in sleep*/ + uint32_t rom0_pd_en : 1; /*enable power down ROM in sleep*/ + uint32_t inter_ram0_pd_en : 1; /*enable power down internal SRAM 0 in sleep*/ + uint32_t inter_ram1_pd_en : 1; /*enable power down internal SRAM 1 in sleep*/ + uint32_t inter_ram2_pd_en : 1; /*enable power down internal SRAM 2 in sleep*/ + uint32_t inter_ram3_pd_en : 1; /*enable power down internal SRAM 3 in sleep*/ + uint32_t inter_ram4_pd_en : 1; /*enable power down internal SRAM 4 in sleep*/ + uint32_t wifi_pd_en : 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en : 1; }; uint32_t val; } dig_pwc; union { struct { - uint32_t reserved0: 7; - uint32_t dig_iso_force_off: 1; - uint32_t dig_iso_force_on: 1; - uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ - uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ - uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ - uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ - uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ - uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ - uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ - uint32_t rom0_force_iso: 1; /*ROM force ISO*/ - uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/ - uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/ - uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/ - uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/ - uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/ - uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/ - uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/ - uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/ - uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/ - uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/ - uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/ - uint32_t wifi_force_iso: 1; /*wifi force ISO*/ - uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ - uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ - uint32_t dg_wrap_force_noiso: 1; + uint32_t reserved0 : 7; + uint32_t dig_iso_force_off : 1; + uint32_t dig_iso_force_on : 1; + uint32_t dg_pad_autohold : 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold : 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en : 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso : 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso : 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold : 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold : 1; /*digital pad force hold*/ + uint32_t rom0_force_iso : 1; /*ROM force ISO*/ + uint32_t rom0_force_noiso : 1; /*ROM force no ISO*/ + uint32_t inter_ram0_force_iso : 1; /*internal SRAM 0 force ISO*/ + uint32_t inter_ram0_force_noiso : 1; /*internal SRAM 0 force no ISO*/ + uint32_t inter_ram1_force_iso : 1; /*internal SRAM 1 force ISO*/ + uint32_t inter_ram1_force_noiso : 1; /*internal SRAM 1 force no ISO*/ + uint32_t inter_ram2_force_iso : 1; /*internal SRAM 2 force ISO*/ + uint32_t inter_ram2_force_noiso : 1; /*internal SRAM 2 force no ISO*/ + uint32_t inter_ram3_force_iso : 1; /*internal SRAM 3 force ISO*/ + uint32_t inter_ram3_force_noiso : 1; /*internal SRAM 3 force no ISO*/ + uint32_t inter_ram4_force_iso : 1; /*internal SRAM 4 force ISO*/ + uint32_t inter_ram4_force_noiso : 1; /*internal SRAM 4 force no ISO*/ + uint32_t wifi_force_iso : 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso : 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso : 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso : 1; }; uint32_t val; } dig_iso; union { struct { - uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/ - uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/ - uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ - uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ - uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ - uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ - uint32_t sys_reset_length: 3; /*system reset counter length*/ - uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ - uint32_t stg3: 3; /*1: interrupt stage en*/ - uint32_t stg2: 3; /*1: interrupt stage en*/ - uint32_t stg1: 3; /*1: interrupt stage en*/ - uint32_t stg0: 3; /*1: interrupt stage en*/ - uint32_t en: 1; + uint32_t chip_reset_width : 8; /*chip reset siginal pulse width*/ + uint32_t chip_reset_en : 1; /*wdt reset whole chip enable*/ + uint32_t pause_in_slp : 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en : 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en : 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en : 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length : 3; /*system reset counter length*/ + uint32_t cpu_reset_length : 3; /*CPU reset counter length*/ + uint32_t stg3 : 3; /*1: interrupt stage en*/ + uint32_t stg2 : 3; /*1: interrupt stage en*/ + uint32_t stg1 : 3; /*1: interrupt stage en*/ + uint32_t stg0 : 3; /*1: interrupt stage en*/ + uint32_t en : 1; }; uint32_t val; } wdt_config0; - uint32_t wdt_config1; /**/ - uint32_t wdt_config2; /**/ - uint32_t wdt_config3; /**/ - uint32_t wdt_config4; /**/ + uint32_t wdt_config1; + uint32_t wdt_config2; + uint32_t wdt_config3; + uint32_t wdt_config4; union { struct { - uint32_t reserved0: 31; - uint32_t feed: 1; + uint32_t reserved0 : 31; + uint32_t feed : 1; }; uint32_t val; } wdt_feed; - uint32_t wdt_wprotect; /**/ + uint32_t wdt_wprotect; union { struct { - uint32_t swd_reset_flag: 1; /*swd reset flag*/ - uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/ - uint32_t reserved2: 15; - uint32_t swd_bypass_rst: 1; - uint32_t swd_signal_width: 10; /*adjust signal width send to swd*/ - uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ - uint32_t swd_feed: 1; /*Sw feed swd*/ - uint32_t swd_disable: 1; /*disabel SWD*/ - uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ + uint32_t swd_reset_flag : 1; /*swd reset flag*/ + uint32_t swd_feed_int : 1; /*swd interrupt for feeding*/ + uint32_t reserved2 : 15; + uint32_t swd_bypass_rst : 1; + uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/ + uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/ + uint32_t swd_feed : 1; /*Sw feed swd*/ + uint32_t swd_disable : 1; /*disabel SWD*/ + uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/ }; uint32_t val; } swd_conf; - uint32_t swd_wprotect; /**/ + uint32_t swd_wprotect; union { struct { - uint32_t reserved0: 20; - uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ - uint32_t procpu_c1: 6; + uint32_t reserved0 : 20; + uint32_t appcpu_c1 : 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ + uint32_t procpu_c1 : 6; }; uint32_t val; } sw_cpu_stall; - uint32_t store4; /**/ - uint32_t store5; /**/ - uint32_t store6; /**/ - uint32_t store7; /**/ + uint32_t store4; + uint32_t store5; + uint32_t store6; + uint32_t store7; union { struct { - uint32_t xpd_rom0: 1; /*rom0 power down*/ - uint32_t reserved1: 1; - uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/ - uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/ - uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/ - uint32_t wifi_iso: 1; /*wifi iso*/ - uint32_t xpd_wifi: 1; /*wifi wrap power down*/ - uint32_t dig_iso: 1; /*digital wrap iso*/ - uint32_t xpd_dig: 1; /*digital wrap power down*/ - uint32_t rtc_touch_state_start: 1; /*touch should start to work*/ - uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/ - uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/ - uint32_t rtc_touch_state_done: 1; /*touch is done*/ - uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/ - uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/ - uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/ - uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/ - uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/ - uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/ - uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/ - uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/ - uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/ - uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/ - uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/ - uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/ - uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/ - uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/ - uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/ - uint32_t rtc_main_state: 4; /*rtc main state machine status*/ + uint32_t xpd_rom0 : 1; /*rom0 power down*/ + uint32_t reserved1 : 1; + uint32_t xpd_dig_dcdc : 1; /*External DCDC power down*/ + uint32_t rtc_peri_iso : 1; /*rtc peripheral iso*/ + uint32_t xpd_rtc_peri : 1; /*rtc peripheral power down */ + uint32_t wifi_iso : 1; /*wifi iso*/ + uint32_t xpd_wifi : 1; /*wifi wrap power down*/ + uint32_t dig_iso : 1; /*digital wrap iso*/ + uint32_t xpd_dig : 1; /*digital wrap power down*/ + uint32_t rtc_touch_state_start : 1; /*touch should start to work*/ + uint32_t rtc_touch_state_switch : 1; /*touch is about to working. Switch rtc main state*/ + uint32_t rtc_touch_state_slp : 1; /*touch is in sleep state*/ + uint32_t rtc_touch_state_done : 1; /*touch is done*/ + uint32_t rtc_cocpu_state_start : 1; /*ulp/cocpu should start to work*/ + uint32_t rtc_cocpu_state_switch : 1; /*ulp/cocpu is about to working. Switch rtc main state*/ + uint32_t rtc_cocpu_state_slp : 1; /*ulp/cocpu is in sleep state*/ + uint32_t rtc_cocpu_state_done : 1; /*ulp/cocpu is done*/ + uint32_t rtc_main_state_xtal_iso : 1; /*no use any more*/ + uint32_t rtc_main_state_pll_on : 1; /*rtc main state machine is in states that pll should be running*/ + uint32_t rtc_rdy_for_wakeup : 1; /*rtc is ready to receive wake up trigger from wake up source*/ + uint32_t rtc_main_state_wait_end : 1; /*rtc main state machine has been waited for some cycles*/ + uint32_t rtc_in_wakeup_state : 1; /*rtc main state machine is in the states of wakeup process*/ + uint32_t rtc_in_low_power_state : 1; /*rtc main state machine is in the states of low power*/ + uint32_t rtc_main_state_in_wait_8m : 1; /*rtc main state machine is in wait 8m state*/ + uint32_t rtc_main_state_in_wait_pll : 1; /*rtc main state machine is in wait pll state*/ + uint32_t rtc_main_state_in_wait_xtl : 1; /*rtc main state machine is in wait xtal state*/ + uint32_t rtc_main_state_in_slp : 1; /*rtc main state machine is in sleep state*/ + uint32_t rtc_main_state_in_idle : 1; /*rtc main state machine is in idle state*/ + uint32_t rtc_main_state : 4; /*rtc main state machine status*/ }; uint32_t val; } low_power_st; - uint32_t diag0; /**/ + uint32_t diag0; union { struct { - uint32_t touch_pad0_hold: 1; - uint32_t touch_pad1_hold: 1; - uint32_t touch_pad2_hold: 1; - uint32_t touch_pad3_hold: 1; - uint32_t touch_pad4_hold: 1; - uint32_t touch_pad5_hold: 1; - uint32_t touch_pad6_hold: 1; - uint32_t touch_pad7_hold: 1; - uint32_t touch_pad8_hold: 1; - uint32_t touch_pad9_hold: 1; - uint32_t touch_pad10_hold: 1; - uint32_t touch_pad11_hold: 1; - uint32_t touch_pad12_hold: 1; - uint32_t touch_pad13_hold: 1; - uint32_t touch_pad14_hold: 1; - uint32_t x32p_hold: 1; - uint32_t x32n_hold: 1; - uint32_t pdac1_hold: 1; - uint32_t pdac2_hold: 1; - uint32_t rtc_pad19_hold: 1; - uint32_t rtc_pad20_hold: 1; - uint32_t rtc_pad21_hold: 1; - uint32_t reserved22: 10; + uint32_t touch_pad0_hold : 1; + uint32_t touch_pad1_hold : 1; + uint32_t touch_pad2_hold : 1; + uint32_t touch_pad3_hold : 1; + uint32_t touch_pad4_hold : 1; + uint32_t touch_pad5_hold : 1; + uint32_t touch_pad6_hold : 1; + uint32_t touch_pad7_hold : 1; + uint32_t touch_pad8_hold : 1; + uint32_t touch_pad9_hold : 1; + uint32_t touch_pad10_hold : 1; + uint32_t touch_pad11_hold : 1; + uint32_t touch_pad12_hold : 1; + uint32_t touch_pad13_hold : 1; + uint32_t touch_pad14_hold : 1; + uint32_t x32p_hold : 1; + uint32_t x32n_hold : 1; + uint32_t pdac1_hold : 1; + uint32_t pdac2_hold : 1; + uint32_t rtc_pad19_hold : 1; + uint32_t rtc_pad20_hold : 1; + uint32_t rtc_pad21_hold : 1; + uint32_t reserved22 : 10; }; uint32_t val; } pad_hold; - uint32_t dig_pad_hold; /**/ + uint32_t dig_pad_hold; union { struct { - uint32_t sel: 22; /*Bitmap to select RTC pads for ext wakeup1*/ - uint32_t status_clr: 1; /*clear ext wakeup1 status*/ - uint32_t reserved23: 9; + uint32_t ext_wakeup1_sel : 22; /*Bitmap to select RTC pads for ext wakeup1*/ + uint32_t ext_wakeup1_status_clr : 1; /*clear ext wakeup1 status*/ + uint32_t reserved23 : 9; }; uint32_t val; } ext_wakeup1; union { struct { - uint32_t status: 22; /*ext wakeup1 status*/ - uint32_t reserved22: 10; + uint32_t ext_wakeup1_status : 22; /*ext wakeup1 status*/ + uint32_t reserved22 : 10; }; uint32_t val; } ext_wakeup1_status; union { struct { - uint32_t reserved0: 4; - uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ - uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ - uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ - uint32_t rst_wait: 10; /*brown out reset wait cycles*/ - uint32_t rst_ena: 1; /*enable brown out reset*/ - uint32_t rst_sel: 1; /*1: 4-pos reset*/ - uint32_t ana_rst_en: 1; - uint32_t cnt_clr: 1; /*clear brown out counter*/ - uint32_t ena: 1; /*enable brown out*/ - uint32_t det: 1; + uint32_t reserved0 : 4; + uint32_t int_wait : 10; /*brown out interrupt wait cycles*/ + uint32_t close_flash_ena : 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena : 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait : 10; /*brown out reset wait cycles*/ + uint32_t rst_ena : 1; /*enable brown out reset*/ + uint32_t rst_sel : 1; /*1: 4-pos reset*/ + uint32_t ana_rst_en : 1; + uint32_t cnt_clr : 1; /*clear brown out counter*/ + uint32_t ena : 1; /*enable brown out*/ + uint32_t det : 1; }; uint32_t val; } brown_out; - uint32_t time_low1; /*RTC timer low 32 bits*/ + uint32_t time_low1; union { struct { - uint32_t rtc_timer_value1_high: 16; /*RTC timer high 16 bits*/ - uint32_t reserved16: 16; + uint32_t rtc_timer_value1_high : 16; /*RTC timer high 16 bits*/ + uint32_t reserved16 : 16; }; uint32_t val; } time_high1; - uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ + uint32_t xtal32k_clk_factor; union { struct { - uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ - uint32_t xtal32k_restart_wait: 16; /*cycles to wait to repower on xtal 32k*/ - uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ - uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ + uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_restart_wait : 16; /*cycles to wait to repower on xtal 32k*/ + uint32_t xtal32k_wdt_timeout : 8; /*If no clock detected for this amount of time*/ + uint32_t xtal32k_stable_thres : 4; /*if restarted xtal32k period is smaller than this*/ }; uint32_t val; } xtal32k_conf; union { struct { - uint32_t ulp_cp_pc_init: 11; /*ULP-coprocessor PC initial address*/ - uint32_t reserved11: 18; - uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/ - uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/ - uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ + uint32_t ulp_cp_pc_init : 11; /*ULP-coprocessor PC initial address*/ + uint32_t reserved11 : 18; + uint32_t ulp_cp_gpio_wakeup_ena : 1; /*ULP-coprocessor wakeup by GPIO enable*/ + uint32_t ulp_cp_gpio_wakeup_clr : 1; /*ULP-coprocessor wakeup by GPIO state clear*/ + uint32_t ulp_cp_slp_timer_en : 1; /*ULP-coprocessor timer enable bit*/ }; uint32_t val; } ulp_cp_timer; union { struct { - uint32_t ulp_cp_mem_addr_init: 11; - uint32_t ulp_cp_mem_addr_size: 11; - uint32_t ulp_cp_mem_offst_clr: 1; - uint32_t reserved23: 5; - uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/ - uint32_t ulp_cp_reset: 1; /*ulp coprocessor clk software reset*/ - uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW*/ - uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor*/ + uint32_t ulp_cp_mem_addr_init : 11; + uint32_t ulp_cp_mem_addr_size : 11; + uint32_t ulp_cp_mem_offst_clr : 1; + uint32_t reserved23 : 5; + uint32_t ulp_cp_clk_fo : 1; /*ulp coprocessor clk force on*/ + uint32_t ulp_cp_reset : 1; /*ulp coprocessor clk software reset*/ + uint32_t ulp_cp_force_start_top : 1; /*1: ULP-coprocessor is started by SW*/ + uint32_t ulp_cp_start_top : 1; /*Write 1 to start ULP-coprocessor*/ }; uint32_t val; } ulp_cp_ctrl; union { struct { - uint32_t cocpu_clk_fo: 1; /*cocpu clk force on*/ - uint32_t cocpu_start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/ - uint32_t cocpu_start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/ - uint32_t cocpu_shut: 1; /*to shut cocpu*/ - uint32_t cocpu_shut_2_clk_dis: 8; /*time from shut cocpu to disable clk*/ - uint32_t cocpu_shut_reset_en: 1; /*to reset cocpu*/ - uint32_t cocpu_sel: 1; /*1: old ULP 0: new riscV*/ - uint32_t cocpu_done_force: 1; /*1: select riscv done 0: select ulp done*/ - uint32_t cocpu_done: 1; /*done signal used by riscv to control timer.*/ - uint32_t cocpu_sw_int_trigger: 1; /*trigger cocpu register interrupt*/ - uint32_t cocpu_clkgate_en: 1; - uint32_t reserved28: 4; + uint32_t cocpu_clk_fo : 1; /*cocpu clk force on*/ + uint32_t cocpu_start_2_reset_dis : 6; /*time from start cocpu to pull down reset*/ + uint32_t cocpu_start_2_intr_en : 6; /*time from start cocpu to give start interrupt*/ + uint32_t cocpu_shut : 1; /*to shut cocpu*/ + uint32_t cocpu_shut_2_clk_dis : 8; /*time from shut cocpu to disable clk*/ + uint32_t cocpu_shut_reset_en : 1; /*to reset cocpu*/ + uint32_t cocpu_sel : 1; /*1: old ULP 0: new riscV*/ + uint32_t cocpu_done_force : 1; /*1: select riscv done 0: select ulp done*/ + uint32_t cocpu_done : 1; /*done signal used by riscv to control timer. */ + uint32_t cocpu_sw_int_trigger : 1; /*trigger cocpu register interrupt*/ + uint32_t cocpu_clkgate_en : 1; + uint32_t reserved28 : 4; }; uint32_t val; } cocpu_ctrl; union { struct { - uint32_t touch_sleep_cycles: 16; /*sleep cycles for timer*/ - uint32_t touch_meas_num: 16; /*the meas length (in 8MHz)*/ + uint32_t touch_sleep_cycles : 16; /*sleep cycles for timer*/ + uint32_t touch_meas_num : 16; /*the meas length (in 8MHz)*/ }; uint32_t val; } touch_ctrl1; union { struct { - uint32_t reserved0: 2; - uint32_t touch_drange: 2; /*TOUCH_DRANGE*/ - uint32_t touch_drefl: 2; /*TOUCH_DREFL*/ - uint32_t touch_drefh: 2; /*TOUCH_DREFH*/ - uint32_t touch_xpd_bias: 1; /*TOUCH_XPD_BIAS*/ - uint32_t touch_refc: 3; /*TOUCH pad0 reference cap*/ - uint32_t touch_dbias: 1; /*1:use self bias 0:use bandgap bias*/ - uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ - uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ - uint32_t touch_start_en: 1; /*1: start touch fsm*/ - uint32_t touch_start_force: 1; /*1: to start touch fsm by SW*/ - uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ - uint32_t touch_slp_cyc_div: 2; /*when a touch pad is active*/ - uint32_t touch_timer_force_done: 2; /*force touch timer done*/ - uint32_t touch_reset: 1; /*reset upgrade touch*/ - uint32_t touch_clk_fo: 1; /*touch clock force on*/ - uint32_t touch_clkgate_en: 1; /*touch clock enable*/ + uint32_t reserved0 : 2; + uint32_t touch_drange : 2; /*TOUCH_DRANGE*/ + uint32_t touch_drefl : 2; /*TOUCH_DREFL*/ + uint32_t touch_drefh : 2; /*TOUCH_DREFH*/ + uint32_t touch_xpd_bias : 1; /*TOUCH_XPD_BIAS*/ + uint32_t touch_refc : 3; /*TOUCH pad0 reference cap*/ + uint32_t touch_dbias : 1; /*1:use self bias 0:use bandgap bias*/ + uint32_t touch_slp_timer_en : 1; /*touch timer enable bit*/ + uint32_t touch_start_fsm_en : 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ + uint32_t touch_start_en : 1; /*1: start touch fsm*/ + uint32_t touch_start_force : 1; /*1: to start touch fsm by SW*/ + uint32_t touch_xpd_wait : 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ + uint32_t touch_slp_cyc_div : 2; /*when a touch pad is active*/ + uint32_t touch_timer_force_done : 2; /*force touch timer done*/ + uint32_t touch_reset : 1; /*reset upgrade touch*/ + uint32_t touch_clk_fo : 1; /*touch clock force on*/ + uint32_t touch_clkgate_en : 1; /*touch clock enable*/ }; uint32_t val; } touch_ctrl2; union { struct { - uint32_t touch_denoise_res: 2; /*De-noise resolution: 12/10/8/4 bit*/ - uint32_t touch_denoise_en: 1; /*touch pad0 will be used to de-noise*/ - uint32_t reserved3: 5; - uint32_t touch_inactive_connection: 1; /*inactive touch pads connect to 1: gnd 0: HighZ*/ - uint32_t touch_shield_pad_en: 1; /*touch pad14 will be used as shield*/ - uint32_t touch_scan_pad_map: 15; /*touch scan mode pad enable map*/ - uint32_t touch_bufdrv: 3; /*touch7 buffer driver strength*/ - uint32_t touch_out_ring: 4; /*select out ring pad*/ + uint32_t touch_denoise_res : 2; /*De-noise resolution: 12/10/8/4 bit*/ + uint32_t touch_denoise_en : 1; /*touch pad0 will be used to de-noise*/ + uint32_t reserved3 : 5; + uint32_t touch_inactive_connection : 1; /*inactive touch pads connect to 1: gnd 0: HighZ*/ + uint32_t touch_shield_pad_en : 1; /*touch pad14 will be used as shield*/ + uint32_t touch_scan_pad_map : 15; /*touch scan mode pad enable map*/ + uint32_t touch_bufdrv : 3; /*touch7 buffer driver strength*/ + uint32_t touch_out_ring : 4; /*select out ring pad*/ }; uint32_t val; } touch_scan_ctrl; union { struct { - uint32_t touch_slp_th: 22; /*the threshold for sleep touch pad*/ - uint32_t reserved22: 4; - uint32_t touch_slp_approach_en: 1; /*sleep pad approach function enable*/ - uint32_t touch_slp_pad: 5; + uint32_t touch_slp_th : 22; /*the threshold for sleep touch pad*/ + uint32_t reserved22 : 4; + uint32_t touch_slp_approach_en : 1; /*sleep pad approach function enable*/ + uint32_t touch_slp_pad : 5; /* */ }; uint32_t val; } touch_slp_thres; union { struct { - uint32_t reserved0: 23; - uint32_t touch_slp_channel_clr: 1; /*clear touch slp channel*/ - uint32_t touch_approach_meas_time: 8; /*approach pads total meas times*/ + uint32_t reserved0 : 23; + uint32_t touch_slp_channel_clr : 1; /*clear touch slp channel*/ + uint32_t touch_approach_meas_time : 8; /*approach pads total meas times*/ }; uint32_t val; } touch_approach; union { struct { - uint32_t reserved0: 7; - uint32_t touch_bypass_neg_thres: 1; - uint32_t touch_bypass_noise_thres: 1; - uint32_t touch_smooth_lvl: 2; - uint32_t touch_jitter_step: 4; /*touch jitter step*/ - uint32_t config1: 4; - uint32_t config2: 2; - uint32_t touch_noise_thres: 2; - uint32_t config3: 2; - uint32_t touch_debounce: 3; /*debounce counter*/ - uint32_t touch_filter_mode: 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ - uint32_t touch_filter_en: 1; /*touch filter enable*/ + uint32_t reserved0 : 7; + uint32_t touch_bypass_neg_noise_thres : 1; + uint32_t touch_bypass_noise_thres : 1; + uint32_t touch_smooth_lvl : 2; + uint32_t touch_jitter_step : 4; /*touch jitter step*/ + uint32_t touch_neg_noise_limit : 4; /*negative threshold counter limit*/ + uint32_t touch_neg_noise_thres : 2; + uint32_t touch_noise_thres : 2; + uint32_t touch_hysteresis : 2; + uint32_t touch_debounce : 3; /*debounce counter*/ + uint32_t touch_filter_mode : 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ + uint32_t touch_filter_en : 1; /*touch filter enable*/ }; uint32_t val; } touch_filter_ctrl; union { struct { - uint32_t usb_vrefh: 2; - uint32_t usb_vrefl: 2; - uint32_t usb_vref_override: 1; - uint32_t usb_pad_pull_override: 1; - uint32_t usb_dp_pullup: 1; - uint32_t usb_dp_pulldown: 1; - uint32_t usb_dm_pullup: 1; - uint32_t usb_dm_pulldown: 1; - uint32_t usb_pullup_value: 1; - uint32_t usb_pad_enable_override: 1; - uint32_t usb_pad_enable: 1; - uint32_t usb_txm: 1; - uint32_t usb_txp: 1; - uint32_t usb_tx_en: 1; - uint32_t usb_tx_en_override: 1; - uint32_t usb_reset_disable: 1; - uint32_t io_mux_reset_disable: 1; - uint32_t reserved19: 13; + uint32_t usb_vrefh : 2; + uint32_t usb_vrefl : 2; + uint32_t usb_vref_override : 1; + uint32_t usb_pad_pull_override : 1; + uint32_t usb_dp_pullup : 1; + uint32_t usb_dp_pulldown : 1; + uint32_t usb_dm_pullup : 1; + uint32_t usb_dm_pulldown : 1; + uint32_t usb_pullup_value : 1; + uint32_t usb_pad_enable_override : 1; + uint32_t usb_pad_enable : 1; + uint32_t usb_txm : 1; + uint32_t usb_txp : 1; + uint32_t usb_tx_en : 1; + uint32_t usb_tx_en_override : 1; + uint32_t usb_reset_disable : 1; + uint32_t io_mux_reset_disable : 1; + uint32_t reserved19 : 13; }; uint32_t val; } usb_conf; union { struct { - uint32_t touch_timeout_num: 22; - uint32_t touch_timeout_en: 1; - uint32_t reserved23: 9; + uint32_t touch_timeout_num : 22; + uint32_t touch_timeout_en : 1; + uint32_t reserved23 : 9; }; uint32_t val; } touch_timeout_ctrl; union { struct { - uint32_t reject_cause: 18; /*sleep reject cause*/ - uint32_t reserved18: 14; + uint32_t reject_cause : 18; /*sleep reject cause*/ + uint32_t reserved18 : 14; }; uint32_t val; } slp_reject_cause; union { struct { - uint32_t force_download_boot: 1; - uint32_t reserved1: 31; + uint32_t force_download_boot : 1; + uint32_t reserved1 : 31; }; uint32_t val; } option1; union { struct { - uint32_t wakeup_cause: 17; /*sleep wakeup cause*/ - uint32_t reserved17: 15; + uint32_t wakeup_cause : 17; /*sleep wakeup cause*/ + uint32_t reserved17 : 15; }; uint32_t val; } slp_wakeup_cause; union { struct { - uint32_t reserved0: 8; - uint32_t ulp_cp_timer_slp_cycle: 24; /*sleep cycles for ULP-coprocessor timer*/ + uint32_t reserved0 : 8; + uint32_t ulp_cp_timer_slp_cycle : 24; /*sleep cycles for ULP-coprocessor timer*/ }; uint32_t val; } ulp_cp_timer_1; union { struct { - uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/ - uint32_t sdio_idle_w1ts: 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/ - uint32_t rtc_touch_scan_done_w1ts: 1; /*enable touch scan done interrupt*/ - uint32_t rtc_ulp_cp_w1ts: 1; /*enable ULP-coprocessor interrupt*/ - uint32_t rtc_touch_done_w1ts: 1; /*enable touch done interrupt*/ - uint32_t rtc_touch_active_w1ts: 1; /*enable touch active interrupt*/ - uint32_t rtc_touch_inactive_w1ts: 1; /*enable touch inactive interrupt*/ - uint32_t w1ts: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/ - uint32_t rtc_saradc1_w1ts: 1; /*enable saradc1 interrupt*/ - uint32_t rtc_tsens_w1ts: 1; /*enable tsens interrupt*/ - uint32_t rtc_cocpu_w1ts: 1; /*enable riscV cocpu interrupt*/ - uint32_t rtc_saradc2_w1ts: 1; /*enable saradc2 interrupt*/ - uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ - uint32_t rtc_cocpu_trap_w1ts: 1; /*enable cocpu trap interrupt*/ - uint32_t rtc_touch_timeout_w1ts: 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_touch_approach_loop_done_w1ts: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup_w1ts : 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1ts : 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle_w1ts : 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt_w1ts : 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done_w1ts : 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp_w1ts : 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done_w1ts : 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active_w1ts : 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive_w1ts : 1; /*enable touch inactive interrupt*/ + uint32_t w1ts : 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1ts : 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1_w1ts : 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens_w1ts : 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu_w1ts : 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2_w1ts : 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd_w1ts : 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1ts : 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap_w1ts : 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout_w1ts : 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det_w1ts : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done_w1ts: 1; + uint32_t reserved21 : 11; }; uint32_t val; } int_ena_w1ts; union { struct { - uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/ - uint32_t sdio_idle_w1tc: 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/ - uint32_t rtc_touch_scan_done_w1tc: 1; /*enable touch scan done interrupt*/ - uint32_t rtc_ulp_cp_w1tc: 1; /*enable ULP-coprocessor interrupt*/ - uint32_t rtc_touch_done_w1tc: 1; /*enable touch done interrupt*/ - uint32_t rtc_touch_active_w1tc: 1; /*enable touch active interrupt*/ - uint32_t rtc_touch_inactive_w1tc: 1; /*enable touch inactive interrupt*/ - uint32_t w1tc: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/ - uint32_t rtc_saradc1_w1tc: 1; /*enable saradc1 interrupt*/ - uint32_t rtc_tsens_w1tc: 1; /*enable tsens interrupt*/ - uint32_t rtc_cocpu_w1tc: 1; /*enable riscV cocpu interrupt*/ - uint32_t rtc_saradc2_w1tc: 1; /*enable saradc2 interrupt*/ - uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ - uint32_t rtc_cocpu_trap_w1tc: 1; /*enable cocpu trap interrupt*/ - uint32_t rtc_touch_timeout_w1tc: 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_touch_approach_loop_done_w1tc: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup_w1tc : 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1tc : 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle_w1tc : 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt_w1tc : 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done_w1tc : 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp_w1tc : 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done_w1tc : 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active_w1tc : 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive_w1tc : 1; /*enable touch inactive interrupt*/ + uint32_t w1tc : 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1tc : 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1_w1tc : 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens_w1tc : 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu_w1tc : 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2_w1tc : 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd_w1tc : 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1tc : 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap_w1tc : 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout_w1tc : 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det_w1tc : 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done_w1tc: 1; + uint32_t reserved21 : 11; }; uint32_t val; } int_ena_w1tc; union { struct { - uint32_t reserved0: 26; - uint32_t retention_en: 1; - uint32_t retention_wait: 5; /*wait cycles for rention operation*/ + uint32_t reserved0 : 26; + uint32_t retention_en : 1; + uint32_t retention_wait : 5; /*wait cycles for rention operation*/ }; uint32_t val; } retention_ctrl; union { struct { - uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/ - uint32_t reserved3: 29; + uint32_t rtc_fib_sel : 3; /*select use analog fib signal*/ + uint32_t reserved3 : 29; }; uint32_t val; } fib_sel; union { struct { - uint32_t date: 28; - uint32_t reserved28: 4; + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } date; } rtc_cntl_dev_t; - extern rtc_cntl_dev_t RTCCNTL; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_RTC_CNTL_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h b/components/soc/esp32s3/include/soc/rtc_i2c_reg.h index 9b75400590..cde345a091 100644 --- a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_i2c_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,670 +11,676 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_RTC_I2C_REG_H_ +#define _SOC_RTC_I2C_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000) +#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_I2C_BASE + 0x0) /* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ -/*description: time period that scl = 0*/ -#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V) << (RTC_I2C_SCL_LOW_PERIOD_S)) -#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_LOW_PERIOD_S 0 +/*description: time period that scl = 0.*/ +#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S)) +#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_LOW_PERIOD_S 0 -#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004) +#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x4) /* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: rtc i2c reg clk gating*/ -#define RTC_I2C_CLK_EN (BIT(31)) -#define RTC_I2C_CLK_EN_M (BIT(31)) -#define RTC_I2C_CLK_EN_V 0x1 -#define RTC_I2C_CLK_EN_S 31 +/*description: rtc i2c reg clk gating.*/ +#define RTC_I2C_CLK_EN (BIT(31)) +#define RTC_I2C_CLK_EN_M (BIT(31)) +#define RTC_I2C_CLK_EN_V 0x1 +#define RTC_I2C_CLK_EN_S 31 /* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: rtc i2c sw reset*/ -#define RTC_I2C_RESET (BIT(30)) -#define RTC_I2C_RESET_M (BIT(30)) -#define RTC_I2C_RESET_V 0x1 -#define RTC_I2C_RESET_S 30 +/*description: rtc i2c sw reset.*/ +#define RTC_I2C_RESET (BIT(30)) +#define RTC_I2C_RESET_M (BIT(30)) +#define RTC_I2C_RESET_V 0x1 +#define RTC_I2C_RESET_S 30 /* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) -#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) -#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 -#define RTC_I2C_CTRL_CLK_GATE_EN_S 29 +/*description: .*/ +#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) +#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) +#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 +#define RTC_I2C_CTRL_CLK_GATE_EN_S 29 /* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: receive lsb first*/ -#define RTC_I2C_RX_LSB_FIRST (BIT(5)) -#define RTC_I2C_RX_LSB_FIRST_M (BIT(5)) -#define RTC_I2C_RX_LSB_FIRST_V 0x1 -#define RTC_I2C_RX_LSB_FIRST_S 5 +/*description: receive lsb first.*/ +#define RTC_I2C_RX_LSB_FIRST (BIT(5)) +#define RTC_I2C_RX_LSB_FIRST_M (BIT(5)) +#define RTC_I2C_RX_LSB_FIRST_V 0x1 +#define RTC_I2C_RX_LSB_FIRST_S 5 /* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: transit lsb first*/ -#define RTC_I2C_TX_LSB_FIRST (BIT(4)) -#define RTC_I2C_TX_LSB_FIRST_M (BIT(4)) -#define RTC_I2C_TX_LSB_FIRST_V 0x1 -#define RTC_I2C_TX_LSB_FIRST_S 4 +/*description: transit lsb first.*/ +#define RTC_I2C_TX_LSB_FIRST (BIT(4)) +#define RTC_I2C_TX_LSB_FIRST_M (BIT(4)) +#define RTC_I2C_TX_LSB_FIRST_V 0x1 +#define RTC_I2C_TX_LSB_FIRST_S 4 /* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: force start*/ -#define RTC_I2C_TRANS_START (BIT(3)) -#define RTC_I2C_TRANS_START_M (BIT(3)) -#define RTC_I2C_TRANS_START_V 0x1 -#define RTC_I2C_TRANS_START_S 3 +/*description: force start.*/ +#define RTC_I2C_TRANS_START (BIT(3)) +#define RTC_I2C_TRANS_START_M (BIT(3)) +#define RTC_I2C_TRANS_START_V 0x1 +#define RTC_I2C_TRANS_START_S 3 /* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1=master 0=slave*/ -#define RTC_I2C_MS_MODE (BIT(2)) -#define RTC_I2C_MS_MODE_M (BIT(2)) -#define RTC_I2C_MS_MODE_V 0x1 -#define RTC_I2C_MS_MODE_S 2 +/*description: 1=master, 0=slave.*/ +#define RTC_I2C_MS_MODE (BIT(2)) +#define RTC_I2C_MS_MODE_M (BIT(2)) +#define RTC_I2C_MS_MODE_V 0x1 +#define RTC_I2C_MS_MODE_S 2 /* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: 1=push pull 0=open drain*/ -#define RTC_I2C_SCL_FORCE_OUT (BIT(1)) -#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1)) -#define RTC_I2C_SCL_FORCE_OUT_V 0x1 -#define RTC_I2C_SCL_FORCE_OUT_S 1 +/*description: 1=push pull, 0=open drain.*/ +#define RTC_I2C_SCL_FORCE_OUT (BIT(1)) +#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1)) +#define RTC_I2C_SCL_FORCE_OUT_V 0x1 +#define RTC_I2C_SCL_FORCE_OUT_S 1 /* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1=push pull 0=open drain*/ -#define RTC_I2C_SDA_FORCE_OUT (BIT(0)) -#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0)) -#define RTC_I2C_SDA_FORCE_OUT_V 0x1 -#define RTC_I2C_SDA_FORCE_OUT_S 0 +/*description: 1=push pull, 0=open drain.*/ +#define RTC_I2C_SDA_FORCE_OUT (BIT(0)) +#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0)) +#define RTC_I2C_SDA_FORCE_OUT_V 0x1 +#define RTC_I2C_SDA_FORCE_OUT_S 0 -#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008) +#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x8) /* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: scl last status*/ -#define RTC_I2C_SCL_STATE_LAST 0x00000007 -#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V) << (RTC_I2C_SCL_STATE_LAST_S)) -#define RTC_I2C_SCL_STATE_LAST_V 0x7 -#define RTC_I2C_SCL_STATE_LAST_S 28 +/*description: scl last status.*/ +#define RTC_I2C_SCL_STATE_LAST 0x00000007 +#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S)) +#define RTC_I2C_SCL_STATE_LAST_V 0x7 +#define RTC_I2C_SCL_STATE_LAST_S 28 /* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: i2c last main status*/ -#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V) << (RTC_I2C_SCL_MAIN_STATE_LAST_S)) -#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 +/*description: i2c last main status.*/ +#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S)) +#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 /* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: shifter content*/ -#define RTC_I2C_SHIFT 0x000000FF -#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V) << (RTC_I2C_SHIFT_S)) -#define RTC_I2C_SHIFT_V 0xFF -#define RTC_I2C_SHIFT_S 16 +/*description: shifter content.*/ +#define RTC_I2C_SHIFT 0x000000FF +#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S)) +#define RTC_I2C_SHIFT_V 0xFF +#define RTC_I2C_SHIFT_S 16 /* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: which operation is working*/ -#define RTC_I2C_OP_CNT 0x00000003 -#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V) << (RTC_I2C_OP_CNT_S)) -#define RTC_I2C_OP_CNT_V 0x3 -#define RTC_I2C_OP_CNT_S 6 +/*description: which operation is working.*/ +#define RTC_I2C_OP_CNT 0x00000003 +#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S)) +#define RTC_I2C_OP_CNT_V 0x3 +#define RTC_I2C_OP_CNT_S 6 /* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: One byte transit done*/ -#define RTC_I2C_BYTE_TRANS (BIT(5)) -#define RTC_I2C_BYTE_TRANS_M (BIT(5)) -#define RTC_I2C_BYTE_TRANS_V 0x1 -#define RTC_I2C_BYTE_TRANS_S 5 +/*description: One byte transit done.*/ +#define RTC_I2C_BYTE_TRANS (BIT(5)) +#define RTC_I2C_BYTE_TRANS_M (BIT(5)) +#define RTC_I2C_BYTE_TRANS_V 0x1 +#define RTC_I2C_BYTE_TRANS_S 5 /* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: slave reg sub address*/ -#define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) -#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4)) -#define RTC_I2C_SLAVE_ADDRESSED_V 0x1 -#define RTC_I2C_SLAVE_ADDRESSED_S 4 +/*description: slave reg sub address.*/ +#define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) +#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4)) +#define RTC_I2C_SLAVE_ADDRESSED_V 0x1 +#define RTC_I2C_SLAVE_ADDRESSED_S 4 /* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: bus is busy*/ -#define RTC_I2C_BUS_BUSY (BIT(3)) -#define RTC_I2C_BUS_BUSY_M (BIT(3)) -#define RTC_I2C_BUS_BUSY_V 0x1 -#define RTC_I2C_BUS_BUSY_S 3 +/*description: bus is busy.*/ +#define RTC_I2C_BUS_BUSY (BIT(3)) +#define RTC_I2C_BUS_BUSY_M (BIT(3)) +#define RTC_I2C_BUS_BUSY_V 0x1 +#define RTC_I2C_BUS_BUSY_S 3 /* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: arbitration is lost*/ -#define RTC_I2C_ARB_LOST (BIT(2)) -#define RTC_I2C_ARB_LOST_M (BIT(2)) -#define RTC_I2C_ARB_LOST_V 0x1 -#define RTC_I2C_ARB_LOST_S 2 +/*description: arbitration is lost.*/ +#define RTC_I2C_ARB_LOST (BIT(2)) +#define RTC_I2C_ARB_LOST_M (BIT(2)) +#define RTC_I2C_ARB_LOST_V 0x1 +#define RTC_I2C_ARB_LOST_S 2 /* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: slave read or write*/ -#define RTC_I2C_SLAVE_RW (BIT(1)) -#define RTC_I2C_SLAVE_RW_M (BIT(1)) -#define RTC_I2C_SLAVE_RW_V 0x1 -#define RTC_I2C_SLAVE_RW_S 1 +/*description: slave read or write.*/ +#define RTC_I2C_SLAVE_RW (BIT(1)) +#define RTC_I2C_SLAVE_RW_M (BIT(1)) +#define RTC_I2C_SLAVE_RW_V 0x1 +#define RTC_I2C_SLAVE_RW_S 1 /* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: ack response*/ -#define RTC_I2C_ACK_REC (BIT(0)) -#define RTC_I2C_ACK_REC_M (BIT(0)) -#define RTC_I2C_ACK_REC_V 0x1 -#define RTC_I2C_ACK_REC_S 0 +/*description: ack response.*/ +#define RTC_I2C_ACK_REC (BIT(0)) +#define RTC_I2C_ACK_REC_M (BIT(0)) +#define RTC_I2C_ACK_REC_V 0x1 +#define RTC_I2C_ACK_REC_S 0 -#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c) +#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0xC) /* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */ -/*description: time out threshold*/ -#define RTC_I2C_TIMEOUT 0x000FFFFF -#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V) << (RTC_I2C_TIMEOUT_S)) -#define RTC_I2C_TIMEOUT_V 0xFFFFF -#define RTC_I2C_TIMEOUT_S 0 +/*description: time out threshold.*/ +#define RTC_I2C_TIMEOUT 0x000FFFFF +#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S)) +#define RTC_I2C_TIMEOUT_V 0xFFFFF +#define RTC_I2C_TIMEOUT_S 0 -#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010) +#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x10) /* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: i2c 10bit mode enable*/ -#define RTC_I2C_ADDR_10BIT_EN (BIT(31)) -#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31)) -#define RTC_I2C_ADDR_10BIT_EN_V 0x1 -#define RTC_I2C_ADDR_10BIT_EN_S 31 +/*description: i2c 10bit mode enable.*/ +#define RTC_I2C_ADDR_10BIT_EN (BIT(31)) +#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31)) +#define RTC_I2C_ADDR_10BIT_EN_V 0x1 +#define RTC_I2C_ADDR_10BIT_EN_S 31 /* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: slave address*/ -#define RTC_I2C_SLAVE_ADDR 0x00007FFF -#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V) << (RTC_I2C_SLAVE_ADDR_S)) -#define RTC_I2C_SLAVE_ADDR_V 0x7FFF -#define RTC_I2C_SLAVE_ADDR_S 0 +/*description: slave address.*/ +#define RTC_I2C_SLAVE_ADDR 0x00007FFF +#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S)) +#define RTC_I2C_SLAVE_ADDR_V 0x7FFF +#define RTC_I2C_SLAVE_ADDR_S 0 -#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014) +#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x14) /* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ -/*description: time period that scl = 1*/ -#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V) << (RTC_I2C_SCL_HIGH_PERIOD_S)) -#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_HIGH_PERIOD_S 0 +/*description: time period that scl = 1.*/ +#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S)) +#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_S 0 -#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018) +#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x18) /* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */ -/*description: time period for SDA to toggle after SCL goes low*/ -#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF -#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V) << (RTC_I2C_SDA_DUTY_NUM_S)) -#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF -#define RTC_I2C_SDA_DUTY_NUM_S 0 +/*description: time period for SDA to toggle after SCL goes low.*/ +#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF +#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S)) +#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF +#define RTC_I2C_SDA_DUTY_NUM_S 0 -#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c) +#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x1C) /* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ -/*description: time period for SCL to toggle after I2C start is triggered*/ -#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V) << (RTC_I2C_SCL_START_PERIOD_S)) -#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_START_PERIOD_S 0 +/*description: time period for SCL to toggle after I2C start is triggered.*/ +#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S)) +#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_START_PERIOD_S 0 -#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020) +#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x20) /* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ -/*description: time period for SCL to stop after I2C end is triggered*/ -#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V) << (RTC_I2C_SCL_STOP_PERIOD_S)) -#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_STOP_PERIOD_S 0 +/*description: time period for SCL to stop after I2C end is triggered.*/ +#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S)) +#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_STOP_PERIOD_S 0 -#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024) +#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x24) /* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: clear detect start interrupt*/ -#define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) -#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_CLR_V 0x1 -#define RTC_I2C_DETECT_START_INT_CLR_S 8 +/*description: clear detect start interrupt.*/ +#define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) +#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_CLR_V 0x1 +#define RTC_I2C_DETECT_START_INT_CLR_S 8 /* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: clear transit load data complete interrupt*/ -#define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) -#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_CLR_V 0x1 -#define RTC_I2C_TX_DATA_INT_CLR_S 7 +/*description: clear transit load data complete interrupt.*/ +#define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) +#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_CLR_V 0x1 +#define RTC_I2C_TX_DATA_INT_CLR_S 7 /* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: clear receive data interrupt*/ -#define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) -#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_CLR_V 0x1 -#define RTC_I2C_RX_DATA_INT_CLR_S 6 +/*description: clear receive data interrupt.*/ +#define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) +#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_CLR_V 0x1 +#define RTC_I2C_RX_DATA_INT_CLR_S 6 /* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: clear ack error interrupt*/ -#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1 -#define RTC_I2C_ACK_ERR_INT_CLR_S 5 +/*description: clear ack error interrupt.*/ +#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1 +#define RTC_I2C_ACK_ERR_INT_CLR_S 5 /* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: clear time out interrupt*/ -#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1 -#define RTC_I2C_TIMEOUT_INT_CLR_S 4 +/*description: clear time out interrupt.*/ +#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1 +#define RTC_I2C_TIMEOUT_INT_CLR_S 4 /* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: clear transit complete interrupt*/ -#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 +/*description: clear transit complete interrupt.*/ +#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 /* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: clear master transit complete interrupt*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 +/*description: clear master transit complete interrupt.*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 /* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: clear arbitration lost interrupt*/ -#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 +/*description: clear arbitration lost interrupt.*/ +#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 /* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: clear slave transit complete interrupt*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0 +/*description: clear slave transit complete interrupt.*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0 -#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028) +#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x28) /* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: detect start interrupt raw*/ -#define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) -#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_RAW_V 0x1 -#define RTC_I2C_DETECT_START_INT_RAW_S 8 +/*description: detect start interrupt raw.*/ +#define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) +#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_RAW_V 0x1 +#define RTC_I2C_DETECT_START_INT_RAW_S 8 /* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: transit data interrupt raw*/ -#define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) -#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_RAW_V 0x1 -#define RTC_I2C_TX_DATA_INT_RAW_S 7 +/*description: transit data interrupt raw.*/ +#define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) +#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_RAW_V 0x1 +#define RTC_I2C_TX_DATA_INT_RAW_S 7 /* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: receive data interrupt raw*/ -#define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) -#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_RAW_V 0x1 -#define RTC_I2C_RX_DATA_INT_RAW_S 6 +/*description: receive data interrupt raw.*/ +#define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) +#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_RAW_V 0x1 +#define RTC_I2C_RX_DATA_INT_RAW_S 6 /* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ack error interrupt raw*/ -#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1 -#define RTC_I2C_ACK_ERR_INT_RAW_S 5 +/*description: ack error interrupt raw.*/ +#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1 +#define RTC_I2C_ACK_ERR_INT_RAW_S 5 /* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: time out interrupt raw*/ -#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1 -#define RTC_I2C_TIMEOUT_INT_RAW_S 4 +/*description: time out interrupt raw.*/ +#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1 +#define RTC_I2C_TIMEOUT_INT_RAW_S 4 /* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: transit complete interrupt raw*/ -#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 +/*description: transit complete interrupt raw.*/ +#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 /* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: master transit complete interrupt raw*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 +/*description: master transit complete interrupt raw.*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 /* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: arbitration lost interrupt raw*/ -#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 +/*description: arbitration lost interrupt raw.*/ +#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 /* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: slave transit complete interrupt raw*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0 +/*description: slave transit complete interrupt raw.*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0 -#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c) +#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x2C) /* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: detect start interrupt state*/ -#define RTC_I2C_DETECT_START_INT_ST (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ST_V 0x1 -#define RTC_I2C_DETECT_START_INT_ST_S 8 +/*description: detect start interrupt state.*/ +#define RTC_I2C_DETECT_START_INT_ST (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ST_V 0x1 +#define RTC_I2C_DETECT_START_INT_ST_S 8 /* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: transit data interrupt state*/ -#define RTC_I2C_TX_DATA_INT_ST (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ST_V 0x1 -#define RTC_I2C_TX_DATA_INT_ST_S 7 +/*description: transit data interrupt state.*/ +#define RTC_I2C_TX_DATA_INT_ST (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ST_V 0x1 +#define RTC_I2C_TX_DATA_INT_ST_S 7 /* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: receive data interrupt state*/ -#define RTC_I2C_RX_DATA_INT_ST (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ST_V 0x1 -#define RTC_I2C_RX_DATA_INT_ST_S 6 +/*description: receive data interrupt state.*/ +#define RTC_I2C_RX_DATA_INT_ST (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ST_V 0x1 +#define RTC_I2C_RX_DATA_INT_ST_S 6 /* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ack error interrupt state*/ -#define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ST_V 0x1 -#define RTC_I2C_ACK_ERR_INT_ST_S 5 +/*description: ack error interrupt state.*/ +#define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ST_V 0x1 +#define RTC_I2C_ACK_ERR_INT_ST_S 5 /* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: time out interrupt state*/ -#define RTC_I2C_TIMEOUT_INT_ST (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ST_V 0x1 -#define RTC_I2C_TIMEOUT_INT_ST_S 4 +/*description: time out interrupt state.*/ +#define RTC_I2C_TIMEOUT_INT_ST (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ST_V 0x1 +#define RTC_I2C_TIMEOUT_INT_ST_S 4 /* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: transit complete interrupt state*/ -#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 +/*description: transit complete interrupt state.*/ +#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 /* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: master transit complete interrupt state*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 +/*description: master transit complete interrupt state.*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 /* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: arbitration lost interrupt state*/ -#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 +/*description: arbitration lost interrupt state.*/ +#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 /* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: slave transit complete interrupt state*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0 +/*description: slave transit complete interrupt state.*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0 -#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030) +#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x30) /* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable detect start interrupt*/ -#define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ENA_V 0x1 -#define RTC_I2C_DETECT_START_INT_ENA_S 8 +/*description: enable detect start interrupt.*/ +#define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ENA_V 0x1 +#define RTC_I2C_DETECT_START_INT_ENA_S 8 /* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable transit data interrupt*/ -#define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ENA_V 0x1 -#define RTC_I2C_TX_DATA_INT_ENA_S 7 +/*description: enable transit data interrupt.*/ +#define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ENA_V 0x1 +#define RTC_I2C_TX_DATA_INT_ENA_S 7 /* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable receive data interrupt*/ -#define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ENA_V 0x1 -#define RTC_I2C_RX_DATA_INT_ENA_S 6 +/*description: enable receive data interrupt.*/ +#define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ENA_V 0x1 +#define RTC_I2C_RX_DATA_INT_ENA_S 6 /* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable eack error interrupt*/ -#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1 -#define RTC_I2C_ACK_ERR_INT_ENA_S 5 +/*description: enable eack error interrupt.*/ +#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1 +#define RTC_I2C_ACK_ERR_INT_ENA_S 5 /* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable time out interrupt*/ -#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1 -#define RTC_I2C_TIMEOUT_INT_ENA_S 4 +/*description: enable time out interrupt.*/ +#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1 +#define RTC_I2C_TIMEOUT_INT_ENA_S 4 /* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable transit complete interrupt*/ -#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 +/*description: enable transit complete interrupt.*/ +#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 /* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable master transit complete interrupt*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 +/*description: enable master transit complete interrupt.*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 /* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable arbitration lost interrupt*/ -#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 +/*description: enable arbitration lost interrupt.*/ +#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 /* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable slave transit complete interrupt*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0 +/*description: enable slave transit complete interrupt.*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0 -#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034) +#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x34) /* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: i2c done*/ -#define RTC_I2C_DONE (BIT(31)) -#define RTC_I2C_DONE_M (BIT(31)) -#define RTC_I2C_DONE_V 0x1 -#define RTC_I2C_DONE_S 31 +/*description: i2c done.*/ +#define RTC_I2C_DONE (BIT(31)) +#define RTC_I2C_DONE_M (BIT(31)) +#define RTC_I2C_DONE_V 0x1 +#define RTC_I2C_DONE_S 31 /* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: data sent by slave*/ -#define RTC_I2C_SLAVE_TX_DATA 0x000000FF -#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V) << (RTC_I2C_SLAVE_TX_DATA_S)) -#define RTC_I2C_SLAVE_TX_DATA_V 0xFF -#define RTC_I2C_SLAVE_TX_DATA_S 8 +/*description: data sent by slave.*/ +#define RTC_I2C_SLAVE_TX_DATA 0x000000FF +#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S)) +#define RTC_I2C_SLAVE_TX_DATA_V 0xFF +#define RTC_I2C_SLAVE_TX_DATA_S 8 /* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: data received*/ -#define RTC_I2C_RDATA 0x000000FF -#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V) << (RTC_I2C_RDATA_S)) -#define RTC_I2C_RDATA_V 0xFF -#define RTC_I2C_RDATA_S 0 +/*description: data received.*/ +#define RTC_I2C_RDATA 0x000000FF +#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S)) +#define RTC_I2C_RDATA_V 0xFF +#define RTC_I2C_RDATA_S 0 -#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038) +#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x38) /* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command0_done*/ -#define RTC_I2C_COMMAND0_DONE (BIT(31)) -#define RTC_I2C_COMMAND0_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND0_DONE_V 0x1 -#define RTC_I2C_COMMAND0_DONE_S 31 +/*description: command0_done.*/ +#define RTC_I2C_COMMAND0_DONE (BIT(31)) +#define RTC_I2C_COMMAND0_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND0_DONE_V 0x1 +#define RTC_I2C_COMMAND0_DONE_S 31 /* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ -/*description: command0*/ -#define RTC_I2C_COMMAND0 0x00003FFF -#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V) << (RTC_I2C_COMMAND0_S)) -#define RTC_I2C_COMMAND0_V 0x3FFF -#define RTC_I2C_COMMAND0_S 0 +/*description: command0.*/ +#define RTC_I2C_COMMAND0 0x00003FFF +#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S)) +#define RTC_I2C_COMMAND0_V 0x3FFF +#define RTC_I2C_COMMAND0_S 0 -#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c) +#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x3C) /* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command1_done*/ -#define RTC_I2C_COMMAND1_DONE (BIT(31)) -#define RTC_I2C_COMMAND1_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND1_DONE_V 0x1 -#define RTC_I2C_COMMAND1_DONE_S 31 +/*description: command1_done.*/ +#define RTC_I2C_COMMAND1_DONE (BIT(31)) +#define RTC_I2C_COMMAND1_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND1_DONE_V 0x1 +#define RTC_I2C_COMMAND1_DONE_S 31 /* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command1*/ -#define RTC_I2C_COMMAND1 0x00003FFF -#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V) << (RTC_I2C_COMMAND1_S)) -#define RTC_I2C_COMMAND1_V 0x3FFF -#define RTC_I2C_COMMAND1_S 0 +/*description: command1.*/ +#define RTC_I2C_COMMAND1 0x00003FFF +#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S)) +#define RTC_I2C_COMMAND1_V 0x3FFF +#define RTC_I2C_COMMAND1_S 0 -#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040) +#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x40) /* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command2_done*/ -#define RTC_I2C_COMMAND2_DONE (BIT(31)) -#define RTC_I2C_COMMAND2_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND2_DONE_V 0x1 -#define RTC_I2C_COMMAND2_DONE_S 31 +/*description: command2_done.*/ +#define RTC_I2C_COMMAND2_DONE (BIT(31)) +#define RTC_I2C_COMMAND2_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND2_DONE_V 0x1 +#define RTC_I2C_COMMAND2_DONE_S 31 /* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */ -/*description: command2*/ -#define RTC_I2C_COMMAND2 0x00003FFF -#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V) << (RTC_I2C_COMMAND2_S)) -#define RTC_I2C_COMMAND2_V 0x3FFF -#define RTC_I2C_COMMAND2_S 0 +/*description: command2.*/ +#define RTC_I2C_COMMAND2 0x00003FFF +#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S)) +#define RTC_I2C_COMMAND2_V 0x3FFF +#define RTC_I2C_COMMAND2_S 0 -#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044) +#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x44) /* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command3_done*/ -#define RTC_I2C_COMMAND3_DONE (BIT(31)) -#define RTC_I2C_COMMAND3_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND3_DONE_V 0x1 -#define RTC_I2C_COMMAND3_DONE_S 31 +/*description: command3_done.*/ +#define RTC_I2C_COMMAND3_DONE (BIT(31)) +#define RTC_I2C_COMMAND3_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND3_DONE_V 0x1 +#define RTC_I2C_COMMAND3_DONE_S 31 /* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ -/*description: command3*/ -#define RTC_I2C_COMMAND3 0x00003FFF -#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V) << (RTC_I2C_COMMAND3_S)) -#define RTC_I2C_COMMAND3_V 0x3FFF -#define RTC_I2C_COMMAND3_S 0 +/*description: command3.*/ +#define RTC_I2C_COMMAND3 0x00003FFF +#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S)) +#define RTC_I2C_COMMAND3_V 0x3FFF +#define RTC_I2C_COMMAND3_S 0 -#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048) +#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x48) /* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command4_done*/ -#define RTC_I2C_COMMAND4_DONE (BIT(31)) -#define RTC_I2C_COMMAND4_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND4_DONE_V 0x1 -#define RTC_I2C_COMMAND4_DONE_S 31 +/*description: command4_done.*/ +#define RTC_I2C_COMMAND4_DONE (BIT(31)) +#define RTC_I2C_COMMAND4_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND4_DONE_V 0x1 +#define RTC_I2C_COMMAND4_DONE_S 31 /* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ -/*description: command4*/ -#define RTC_I2C_COMMAND4 0x00003FFF -#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V) << (RTC_I2C_COMMAND4_S)) -#define RTC_I2C_COMMAND4_V 0x3FFF -#define RTC_I2C_COMMAND4_S 0 +/*description: command4.*/ +#define RTC_I2C_COMMAND4 0x00003FFF +#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S)) +#define RTC_I2C_COMMAND4_V 0x3FFF +#define RTC_I2C_COMMAND4_S 0 -#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c) +#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x4C) /* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command5_done*/ -#define RTC_I2C_COMMAND5_DONE (BIT(31)) -#define RTC_I2C_COMMAND5_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND5_DONE_V 0x1 -#define RTC_I2C_COMMAND5_DONE_S 31 +/*description: command5_done.*/ +#define RTC_I2C_COMMAND5_DONE (BIT(31)) +#define RTC_I2C_COMMAND5_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND5_DONE_V 0x1 +#define RTC_I2C_COMMAND5_DONE_S 31 /* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ -/*description: command5*/ -#define RTC_I2C_COMMAND5 0x00003FFF -#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V) << (RTC_I2C_COMMAND5_S)) -#define RTC_I2C_COMMAND5_V 0x3FFF -#define RTC_I2C_COMMAND5_S 0 +/*description: command5.*/ +#define RTC_I2C_COMMAND5 0x00003FFF +#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S)) +#define RTC_I2C_COMMAND5_V 0x3FFF +#define RTC_I2C_COMMAND5_S 0 -#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050) +#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x50) /* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command6_done*/ -#define RTC_I2C_COMMAND6_DONE (BIT(31)) -#define RTC_I2C_COMMAND6_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND6_DONE_V 0x1 -#define RTC_I2C_COMMAND6_DONE_S 31 +/*description: command6_done.*/ +#define RTC_I2C_COMMAND6_DONE (BIT(31)) +#define RTC_I2C_COMMAND6_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND6_DONE_V 0x1 +#define RTC_I2C_COMMAND6_DONE_S 31 /* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command6*/ -#define RTC_I2C_COMMAND6 0x00003FFF -#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V) << (RTC_I2C_COMMAND6_S)) -#define RTC_I2C_COMMAND6_V 0x3FFF -#define RTC_I2C_COMMAND6_S 0 +/*description: command6.*/ +#define RTC_I2C_COMMAND6 0x00003FFF +#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S)) +#define RTC_I2C_COMMAND6_V 0x3FFF +#define RTC_I2C_COMMAND6_S 0 -#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054) +#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x54) /* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command7_done*/ -#define RTC_I2C_COMMAND7_DONE (BIT(31)) -#define RTC_I2C_COMMAND7_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND7_DONE_V 0x1 -#define RTC_I2C_COMMAND7_DONE_S 31 +/*description: command7_done.*/ +#define RTC_I2C_COMMAND7_DONE (BIT(31)) +#define RTC_I2C_COMMAND7_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND7_DONE_V 0x1 +#define RTC_I2C_COMMAND7_DONE_S 31 /* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */ -/*description: command7*/ -#define RTC_I2C_COMMAND7 0x00003FFF -#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V) << (RTC_I2C_COMMAND7_S)) -#define RTC_I2C_COMMAND7_V 0x3FFF -#define RTC_I2C_COMMAND7_S 0 +/*description: command7.*/ +#define RTC_I2C_COMMAND7 0x00003FFF +#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S)) +#define RTC_I2C_COMMAND7_V 0x3FFF +#define RTC_I2C_COMMAND7_S 0 -#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058) +#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x58) /* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command8_done*/ -#define RTC_I2C_COMMAND8_DONE (BIT(31)) -#define RTC_I2C_COMMAND8_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND8_DONE_V 0x1 -#define RTC_I2C_COMMAND8_DONE_S 31 +/*description: command8_done.*/ +#define RTC_I2C_COMMAND8_DONE (BIT(31)) +#define RTC_I2C_COMMAND8_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND8_DONE_V 0x1 +#define RTC_I2C_COMMAND8_DONE_S 31 /* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command8*/ -#define RTC_I2C_COMMAND8 0x00003FFF -#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V) << (RTC_I2C_COMMAND8_S)) -#define RTC_I2C_COMMAND8_V 0x3FFF -#define RTC_I2C_COMMAND8_S 0 +/*description: command8.*/ +#define RTC_I2C_COMMAND8 0x00003FFF +#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S)) +#define RTC_I2C_COMMAND8_V 0x3FFF +#define RTC_I2C_COMMAND8_S 0 -#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c) +#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x5C) /* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command9_done*/ -#define RTC_I2C_COMMAND9_DONE (BIT(31)) -#define RTC_I2C_COMMAND9_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND9_DONE_V 0x1 -#define RTC_I2C_COMMAND9_DONE_S 31 +/*description: command9_done.*/ +#define RTC_I2C_COMMAND9_DONE (BIT(31)) +#define RTC_I2C_COMMAND9_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND9_DONE_V 0x1 +#define RTC_I2C_COMMAND9_DONE_S 31 /* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ -/*description: command9*/ -#define RTC_I2C_COMMAND9 0x00003FFF -#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V) << (RTC_I2C_COMMAND9_S)) -#define RTC_I2C_COMMAND9_V 0x3FFF -#define RTC_I2C_COMMAND9_S 0 +/*description: command9.*/ +#define RTC_I2C_COMMAND9 0x00003FFF +#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S)) +#define RTC_I2C_COMMAND9_V 0x3FFF +#define RTC_I2C_COMMAND9_S 0 -#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060) +#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x60) /* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command10_done*/ -#define RTC_I2C_COMMAND10_DONE (BIT(31)) -#define RTC_I2C_COMMAND10_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND10_DONE_V 0x1 -#define RTC_I2C_COMMAND10_DONE_S 31 +/*description: command10_done.*/ +#define RTC_I2C_COMMAND10_DONE (BIT(31)) +#define RTC_I2C_COMMAND10_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND10_DONE_V 0x1 +#define RTC_I2C_COMMAND10_DONE_S 31 /* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ -/*description: command10*/ -#define RTC_I2C_COMMAND10 0x00003FFF -#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V) << (RTC_I2C_COMMAND10_S)) -#define RTC_I2C_COMMAND10_V 0x3FFF -#define RTC_I2C_COMMAND10_S 0 +/*description: command10.*/ +#define RTC_I2C_COMMAND10 0x00003FFF +#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S)) +#define RTC_I2C_COMMAND10_V 0x3FFF +#define RTC_I2C_COMMAND10_S 0 -#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064) +#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x64) /* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command11_done*/ -#define RTC_I2C_COMMAND11_DONE (BIT(31)) -#define RTC_I2C_COMMAND11_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND11_DONE_V 0x1 -#define RTC_I2C_COMMAND11_DONE_S 31 +/*description: command11_done.*/ +#define RTC_I2C_COMMAND11_DONE (BIT(31)) +#define RTC_I2C_COMMAND11_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND11_DONE_V 0x1 +#define RTC_I2C_COMMAND11_DONE_S 31 /* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ -/*description: command11*/ -#define RTC_I2C_COMMAND11 0x00003FFF -#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V) << (RTC_I2C_COMMAND11_S)) -#define RTC_I2C_COMMAND11_V 0x3FFF -#define RTC_I2C_COMMAND11_S 0 +/*description: command11.*/ +#define RTC_I2C_COMMAND11 0x00003FFF +#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S)) +#define RTC_I2C_COMMAND11_V 0x3FFF +#define RTC_I2C_COMMAND11_S 0 -#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068) +#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x68) /* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command12_done*/ -#define RTC_I2C_COMMAND12_DONE (BIT(31)) -#define RTC_I2C_COMMAND12_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND12_DONE_V 0x1 -#define RTC_I2C_COMMAND12_DONE_S 31 +/*description: command12_done.*/ +#define RTC_I2C_COMMAND12_DONE (BIT(31)) +#define RTC_I2C_COMMAND12_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND12_DONE_V 0x1 +#define RTC_I2C_COMMAND12_DONE_S 31 /* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ -/*description: command12*/ -#define RTC_I2C_COMMAND12 0x00003FFF -#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V) << (RTC_I2C_COMMAND12_S)) -#define RTC_I2C_COMMAND12_V 0x3FFF -#define RTC_I2C_COMMAND12_S 0 +/*description: command12.*/ +#define RTC_I2C_COMMAND12 0x00003FFF +#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S)) +#define RTC_I2C_COMMAND12_V 0x3FFF +#define RTC_I2C_COMMAND12_S 0 -#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c) +#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x6C) /* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command13_done*/ -#define RTC_I2C_COMMAND13_DONE (BIT(31)) -#define RTC_I2C_COMMAND13_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND13_DONE_V 0x1 -#define RTC_I2C_COMMAND13_DONE_S 31 +/*description: command13_done.*/ +#define RTC_I2C_COMMAND13_DONE (BIT(31)) +#define RTC_I2C_COMMAND13_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND13_DONE_V 0x1 +#define RTC_I2C_COMMAND13_DONE_S 31 /* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command13*/ -#define RTC_I2C_COMMAND13 0x00003FFF -#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V) << (RTC_I2C_COMMAND13_S)) -#define RTC_I2C_COMMAND13_V 0x3FFF -#define RTC_I2C_COMMAND13_S 0 +/*description: command13.*/ +#define RTC_I2C_COMMAND13 0x00003FFF +#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S)) +#define RTC_I2C_COMMAND13_V 0x3FFF +#define RTC_I2C_COMMAND13_S 0 -#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070) +#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x70) /* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command14_done*/ -#define RTC_I2C_COMMAND14_DONE (BIT(31)) -#define RTC_I2C_COMMAND14_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND14_DONE_V 0x1 -#define RTC_I2C_COMMAND14_DONE_S 31 +/*description: command14_done.*/ +#define RTC_I2C_COMMAND14_DONE (BIT(31)) +#define RTC_I2C_COMMAND14_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND14_DONE_V 0x1 +#define RTC_I2C_COMMAND14_DONE_S 31 /* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: command14*/ -#define RTC_I2C_COMMAND14 0x00003FFF -#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V) << (RTC_I2C_COMMAND14_S)) -#define RTC_I2C_COMMAND14_V 0x3FFF -#define RTC_I2C_COMMAND14_S 0 +/*description: command14.*/ +#define RTC_I2C_COMMAND14 0x00003FFF +#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S)) +#define RTC_I2C_COMMAND14_V 0x3FFF +#define RTC_I2C_COMMAND14_S 0 -#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074) +#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x74) /* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command15_done*/ -#define RTC_I2C_COMMAND15_DONE (BIT(31)) -#define RTC_I2C_COMMAND15_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND15_DONE_V 0x1 -#define RTC_I2C_COMMAND15_DONE_S 31 +/*description: command15_done.*/ +#define RTC_I2C_COMMAND15_DONE (BIT(31)) +#define RTC_I2C_COMMAND15_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND15_DONE_V 0x1 +#define RTC_I2C_COMMAND15_DONE_S 31 /* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: command15*/ -#define RTC_I2C_COMMAND15 0x00003FFF -#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V) << (RTC_I2C_COMMAND15_S)) -#define RTC_I2C_COMMAND15_V 0x3FFF -#define RTC_I2C_COMMAND15_S 0 +/*description: command15.*/ +#define RTC_I2C_COMMAND15 0x00003FFF +#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S)) +#define RTC_I2C_COMMAND15_V 0x3FFF +#define RTC_I2C_COMMAND15_S 0 -#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC) +#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0xFC) /* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */ -/*description: */ -#define RTC_I2C_DATE 0x0FFFFFFF -#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V) << (RTC_I2C_DATE_S)) -#define RTC_I2C_DATE_V 0xFFFFFFF -#define RTC_I2C_DATE_S 0 +/*description: .*/ +#define RTC_I2C_DATE 0x0FFFFFFF +#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S)) +#define RTC_I2C_DATE_V 0xFFFFFFF +#define RTC_I2C_DATE_S 0 + #ifdef __cplusplus } #endif + + + +#endif /*_SOC_RTC_I2C_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h b/components/soc/esp32s3/include/soc/rtc_i2c_struct.h index 26b4e62f87..471acd720d 100644 --- a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32s3/include/soc/rtc_i2c_struct.h @@ -22,161 +22,161 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t period: 20; /*time period that scl = 0*/ - uint32_t reserved20: 12; + uint32_t period : 20; /*time period that scl = 0*/ + uint32_t reserved20 : 12; }; uint32_t val; } scl_low; union { struct { - uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/ - uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/ - uint32_t ms_mode: 1; /*1=master 0=slave*/ - uint32_t trans_start: 1; /*force start*/ - uint32_t tx_lsb_first: 1; /*transit lsb first*/ - uint32_t rx_lsb_first: 1; /*receive lsb first*/ - uint32_t reserved6: 23; - uint32_t i2c_ctrl_clk_gate_en: 1; - uint32_t i2c_reset: 1; /*rtc i2c sw reset*/ - uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/ + uint32_t sda_force_out : 1; /*1=push pull, 0=open drain*/ + uint32_t scl_force_out : 1; /*1=push pull, 0=open drain*/ + uint32_t ms_mode : 1; /*1=master, 0=slave*/ + uint32_t trans_start : 1; /*force start*/ + uint32_t tx_lsb_first : 1; /*transit lsb first*/ + uint32_t rx_lsb_first : 1; /*receive lsb first*/ + uint32_t reserved6 : 23; + uint32_t i2c_ctrl_clk_gate_en : 1; + uint32_t i2c_reset : 1; /*rtc i2c sw reset*/ + uint32_t i2cclk_en : 1; /*rtc i2c reg clk gating*/ }; uint32_t val; } ctrl; union { struct { - uint32_t ack_rec: 1; /*ack response*/ - uint32_t slave_rw: 1; /*slave read or write*/ - uint32_t arb_lost: 1; /*arbitration is lost*/ - uint32_t bus_busy: 1; /*bus is busy*/ - uint32_t slave_addressed: 1; /*slave reg sub address*/ - uint32_t byte_trans: 1; /*One byte transit done*/ - uint32_t op_cnt: 2; /*which operation is working*/ - uint32_t reserved8: 8; - uint32_t shift: 8; /*shifter content*/ - uint32_t scl_main_state_last: 3; /*i2c last main status*/ - uint32_t reserved27: 1; - uint32_t scl_state_last: 3; /*scl last status*/ - uint32_t reserved31: 1; + uint32_t ack_rec : 1; /*ack response*/ + uint32_t slave_rw : 1; /*slave read or write*/ + uint32_t arb_lost : 1; /*arbitration is lost*/ + uint32_t bus_busy : 1; /*bus is busy*/ + uint32_t slave_addressed : 1; /*slave reg sub address*/ + uint32_t byte_trans : 1; /*One byte transit done*/ + uint32_t op_cnt : 2; /*which operation is working*/ + uint32_t reserved8 : 8; + uint32_t shift : 8; /*shifter content*/ + uint32_t scl_main_state_last : 3; /*i2c last main status*/ + uint32_t reserved27 : 1; + uint32_t scl_state_last : 3; /*scl last status*/ + uint32_t reserved31 : 1; }; uint32_t val; } status; union { struct { - uint32_t time_out: 20; /*time out threshold*/ - uint32_t reserved20: 12; + uint32_t time_out : 20; /*time out threshold*/ + uint32_t reserved20 : 12; }; uint32_t val; } timeout; union { struct { - uint32_t addr: 15; /*slave address*/ - uint32_t reserved15: 16; - uint32_t en_10bit: 1; /*i2c 10bit mode enable*/ + uint32_t addr : 15; /*slave address*/ + uint32_t reserved15 : 16; + uint32_t en_10bit : 1; /*i2c 10bit mode enable*/ }; uint32_t val; } slave_addr; union { struct { - uint32_t period: 20; /*time period that scl = 1*/ - uint32_t reserved20: 12; + uint32_t period : 20; /*time period that scl = 1*/ + uint32_t reserved20 : 12; }; uint32_t val; } scl_high; union { struct { - uint32_t sda_duty_num: 20; /*time period for SDA to toggle after SCL goes low*/ - uint32_t reserved20: 12; + uint32_t sda_duty_num : 20; /*time period for SDA to toggle after SCL goes low*/ + uint32_t reserved20 : 12; }; uint32_t val; } sda_duty; union { struct { - uint32_t scl_start_period: 20; /*time period for SCL to toggle after I2C start is triggered*/ - uint32_t reserved20: 12; + uint32_t scl_start_period : 20; /*time period for SCL to toggle after I2C start is triggered*/ + uint32_t reserved20 : 12; }; uint32_t val; } scl_start_period; union { struct { - uint32_t scl_stop_period: 20; /*time period for SCL to stop after I2C end is triggered*/ - uint32_t reserved20: 12; + uint32_t scl_stop_period : 20; /*time period for SCL to stop after I2C end is triggered*/ + uint32_t reserved20 : 12; }; uint32_t val; } scl_stop_period; union { struct { - uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/ - uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/ - uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/ - uint32_t trans_complete: 1; /*clear transit complete interrupt*/ - uint32_t time_out: 1; /*clear time out interrupt*/ - uint32_t ack_err: 1; /*clear ack error interrupt*/ - uint32_t rx_data: 1; /*clear receive data interrupt*/ - uint32_t tx_data: 1; /*clear transit load data complete interrupt*/ - uint32_t detect_start: 1; /*clear detect start interrupt*/ - uint32_t reserved9: 23; + uint32_t slave_tran_comp : 1; /*clear slave transit complete interrupt*/ + uint32_t arbitration_lost : 1; /*clear arbitration lost interrupt*/ + uint32_t master_tran_comp : 1; /*clear master transit complete interrupt*/ + uint32_t trans_complete : 1; /*clear transit complete interrupt*/ + uint32_t time_out : 1; /*clear time out interrupt*/ + uint32_t ack_err : 1; /*clear ack error interrupt*/ + uint32_t rx_data : 1; /*clear receive data interrupt*/ + uint32_t tx_data : 1; /*clear transit load data complete interrupt*/ + uint32_t detect_start : 1; /*clear detect start interrupt*/ + uint32_t reserved9 : 23; }; uint32_t val; } int_clr; union { struct { - uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/ - uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/ - uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/ - uint32_t trans_complete: 1; /*transit complete interrupt raw*/ - uint32_t time_out: 1; /*time out interrupt raw*/ - uint32_t ack_err: 1; /*ack error interrupt raw*/ - uint32_t rx_data: 1; /*receive data interrupt raw*/ - uint32_t tx_data: 1; /*transit data interrupt raw*/ - uint32_t detect_start: 1; /*detect start interrupt raw*/ - uint32_t reserved9: 23; + uint32_t slave_tran_comp : 1; /*slave transit complete interrupt raw*/ + uint32_t arbitration_lost : 1; /*arbitration lost interrupt raw*/ + uint32_t master_tran_comp : 1; /*master transit complete interrupt raw*/ + uint32_t trans_complete : 1; /*transit complete interrupt raw*/ + uint32_t time_out : 1; /*time out interrupt raw*/ + uint32_t ack_err : 1; /*ack error interrupt raw*/ + uint32_t rx_data : 1; /*receive data interrupt raw*/ + uint32_t tx_data : 1; /*transit data interrupt raw*/ + uint32_t detect_start : 1; /*detect start interrupt raw*/ + uint32_t reserved9 : 23; }; uint32_t val; } int_raw; union { struct { - uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/ - uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/ - uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/ - uint32_t trans_complete: 1; /*transit complete interrupt state*/ - uint32_t time_out: 1; /*time out interrupt state*/ - uint32_t ack_err: 1; /*ack error interrupt state*/ - uint32_t rx_data: 1; /*receive data interrupt state*/ - uint32_t tx_data: 1; /*transit data interrupt state*/ - uint32_t detect_start: 1; /*detect start interrupt state*/ - uint32_t reserved9: 23; + uint32_t slave_tran_comp : 1; /*slave transit complete interrupt state*/ + uint32_t arbitration_lost : 1; /*arbitration lost interrupt state*/ + uint32_t master_tran_comp : 1; /*master transit complete interrupt state*/ + uint32_t trans_complete : 1; /*transit complete interrupt state*/ + uint32_t time_out : 1; /*time out interrupt state*/ + uint32_t ack_err : 1; /*ack error interrupt state*/ + uint32_t rx_data : 1; /*receive data interrupt state*/ + uint32_t tx_data : 1; /*transit data interrupt state*/ + uint32_t detect_start : 1; /*detect start interrupt state*/ + uint32_t reserved9 : 23; }; uint32_t val; } int_st; union { struct { - uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/ - uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/ - uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/ - uint32_t trans_complete: 1; /*enable transit complete interrupt*/ - uint32_t time_out: 1; /*enable time out interrupt*/ - uint32_t ack_err: 1; /*enable eack error interrupt*/ - uint32_t rx_data: 1; /*enable receive data interrupt*/ - uint32_t tx_data: 1; /*enable transit data interrupt*/ - uint32_t detect_start: 1; /*enable detect start interrupt*/ - uint32_t reserved9: 23; + uint32_t slave_tran_comp : 1; /*enable slave transit complete interrupt*/ + uint32_t arbitration_lost : 1; /*enable arbitration lost interrupt*/ + uint32_t master_tran_comp : 1; /*enable master transit complete interrupt*/ + uint32_t trans_complete : 1; /*enable transit complete interrupt*/ + uint32_t time_out : 1; /*enable time out interrupt*/ + uint32_t ack_err : 1; /*enable eack error interrupt*/ + uint32_t rx_data : 1; /*enable receive data interrupt*/ + uint32_t tx_data : 1; /*enable transit data interrupt*/ + uint32_t detect_start : 1; /*enable detect start interrupt*/ + uint32_t reserved9 : 23; }; uint32_t val; } int_ena; union { struct { - uint32_t i2c_rdata: 8; /*data received*/ - uint32_t slave_tx_data: 8; /*data sent by slave*/ - uint32_t reserved16: 15; - uint32_t i2c_done: 1; /*i2c done*/ + uint32_t i2c_rdata : 8; /*data received*/ + uint32_t slave_tx_data : 8; /*data sent by slave*/ + uint32_t reserved16 : 15; + uint32_t i2c_done : 1; /*i2c done*/ }; uint32_t val; } fifo_data; union { struct { - uint32_t command0: 14; /*command0*/ - uint32_t reserved14: 17; - uint32_t done: 1; /*command0_done*/ + uint32_t command0 : 14; /* command0*/ + uint32_t reserved14 : 17; + uint32_t done : 1; /* command0_done*/ }; uint32_t val; } command[16]; @@ -215,15 +215,13 @@ typedef volatile struct { uint32_t reserved_f8; union { struct { - uint32_t i2c_date: 28; - uint32_t reserved28: 4; + uint32_t i2c_date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } date; } rtc_i2c_dev_t; - extern rtc_i2c_dev_t RTC_I2C; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/rtc_io_reg.h b/components/soc/esp32s3/include/soc/rtc_io_reg.h index acd455d210..1c9506e8b3 100644 --- a/components/soc/esp32s3/include/soc/rtc_io_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_io_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,2282 +11,2220 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_RTC_IO_REG_H_ +#define _SOC_RTC_IO_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) +#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) /* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 output data*/ -#define RTC_GPIO_OUT_DATA 0x003FFFFF -#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V) << (RTC_GPIO_OUT_DATA_S)) -#define RTC_GPIO_OUT_DATA_V 0x3FFFFF -#define RTC_GPIO_OUT_DATA_S 10 +/*description: RTC GPIO 0 ~ 21 output data.*/ +#define RTC_GPIO_OUT_DATA 0x003FFFFF +#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S)) +#define RTC_GPIO_OUT_DATA_V 0x3FFFFF +#define RTC_GPIO_OUT_DATA_S 10 -#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) +#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) /* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 output data write 1 to set*/ -#define RTC_GPIO_OUT_DATA_W1TS 0x003FFFFF -#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V) << (RTC_GPIO_OUT_DATA_W1TS_S)) -#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFFF -#define RTC_GPIO_OUT_DATA_W1TS_S 10 +/*description: RTC GPIO 0 ~ 21 output data write 1 to set.*/ +#define RTC_GPIO_OUT_DATA_W1TS 0x003FFFFF +#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S)) +#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFFF +#define RTC_GPIO_OUT_DATA_W1TS_S 10 -#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) +#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) /* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 output data write 1 to clear*/ -#define RTC_GPIO_OUT_DATA_W1TC 0x003FFFFF -#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V) << (RTC_GPIO_OUT_DATA_W1TC_S)) -#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFFF -#define RTC_GPIO_OUT_DATA_W1TC_S 10 +/*description: RTC GPIO 0 ~ 21 output data write 1 to clear.*/ +#define RTC_GPIO_OUT_DATA_W1TC 0x003FFFFF +#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S)) +#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFFF +#define RTC_GPIO_OUT_DATA_W1TC_S 10 -#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xC) +#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xC) /* RTC_GPIO_ENABLE : R/W ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 enable*/ -#define RTC_GPIO_ENABLE 0x003FFFFF -#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V) << (RTC_GPIO_ENABLE_S)) -#define RTC_GPIO_ENABLE_V 0x3FFFFF -#define RTC_GPIO_ENABLE_S 10 +/*description: RTC GPIO 0 ~ 21 enable.*/ +#define RTC_GPIO_ENABLE 0x003FFFFF +#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S)) +#define RTC_GPIO_ENABLE_V 0x3FFFFF +#define RTC_GPIO_ENABLE_S 10 -#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) +#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) /* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 enable write 1 to set*/ -#define RTC_GPIO_ENABLE_W1TS 0x003FFFFF -#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V) << (RTC_GPIO_ENABLE_W1TS_S)) -#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFFF -#define RTC_GPIO_ENABLE_W1TS_S 10 +/*description: RTC GPIO 0 ~ 21 enable write 1 to set.*/ +#define RTC_GPIO_ENABLE_W1TS 0x003FFFFF +#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S)) +#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFFF +#define RTC_GPIO_ENABLE_W1TS_S 10 -#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) +#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) /* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 enable write 1 to clear*/ -#define RTC_GPIO_ENABLE_W1TC 0x003FFFFF -#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V) << (RTC_GPIO_ENABLE_W1TC_S)) -#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFFF -#define RTC_GPIO_ENABLE_W1TC_S 10 +/*description: RTC GPIO 0 ~ 21 enable write 1 to clear.*/ +#define RTC_GPIO_ENABLE_W1TC 0x003FFFFF +#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S)) +#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFFF +#define RTC_GPIO_ENABLE_W1TC_S 10 -#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) +#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) /* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 interrupt status*/ -#define RTC_GPIO_STATUS_INT 0x003FFFFF -#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V) << (RTC_GPIO_STATUS_INT_S)) -#define RTC_GPIO_STATUS_INT_V 0x3FFFFF -#define RTC_GPIO_STATUS_INT_S 10 +/*description: RTC GPIO 0 ~ 21 interrupt status.*/ +#define RTC_GPIO_STATUS_INT 0x003FFFFF +#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S)) +#define RTC_GPIO_STATUS_INT_V 0x3FFFFF +#define RTC_GPIO_STATUS_INT_S 10 -#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1C) +#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1C) /* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to set*/ -#define RTC_GPIO_STATUS_INT_W1TS 0x003FFFFF -#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V) << (RTC_GPIO_STATUS_INT_W1TS_S)) -#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFFF -#define RTC_GPIO_STATUS_INT_W1TS_S 10 +/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to set.*/ +#define RTC_GPIO_STATUS_INT_W1TS 0x003FFFFF +#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S)) +#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFFF +#define RTC_GPIO_STATUS_INT_W1TS_S 10 -#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) +#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) /* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */ -/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/ -#define RTC_GPIO_STATUS_INT_W1TC 0x003FFFFF -#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V) << (RTC_GPIO_STATUS_INT_W1TC_S)) -#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFFF -#define RTC_GPIO_STATUS_INT_W1TC_S 10 +/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to clear.*/ +#define RTC_GPIO_STATUS_INT_W1TC 0x003FFFFF +#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S)) +#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFFF +#define RTC_GPIO_STATUS_INT_W1TC_S 10 -#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) +#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) /* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:10] ;default: ; */ -/*description: RTC GPIO input data*/ -#define RTC_GPIO_IN_NEXT 0x003FFFFF -#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V) << (RTC_GPIO_IN_NEXT_S)) -#define RTC_GPIO_IN_NEXT_V 0x3FFFFF -#define RTC_GPIO_IN_NEXT_S 10 +/*description: RTC GPIO input data.*/ +#define RTC_GPIO_IN_NEXT 0x003FFFFF +#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S)) +#define RTC_GPIO_IN_NEXT_V 0x3FFFFF +#define RTC_GPIO_IN_NEXT_S 10 -#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) +#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) /* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V) << (RTC_GPIO_PIN0_INT_TYPE_S)) -#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN0_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S)) +#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN0_INT_TYPE_S 7 /* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2C) +#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2C) /* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V) << (RTC_GPIO_PIN1_INT_TYPE_S)) -#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN1_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S)) +#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN1_INT_TYPE_S 7 /* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) +#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) /* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V) << (RTC_GPIO_PIN2_INT_TYPE_S)) -#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN2_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S)) +#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN2_INT_TYPE_S 7 /* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) +#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) /* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V) << (RTC_GPIO_PIN3_INT_TYPE_S)) -#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN3_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S)) +#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN3_INT_TYPE_S 7 /* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) +#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) /* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V) << (RTC_GPIO_PIN4_INT_TYPE_S)) -#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN4_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S)) +#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN4_INT_TYPE_S 7 /* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3C) +#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3C) /* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V) << (RTC_GPIO_PIN5_INT_TYPE_S)) -#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN5_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S)) +#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN5_INT_TYPE_S 7 /* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) +#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) /* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V) << (RTC_GPIO_PIN6_INT_TYPE_S)) -#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN6_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S)) +#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN6_INT_TYPE_S 7 /* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) +#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) /* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V) << (RTC_GPIO_PIN7_INT_TYPE_S)) -#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN7_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S)) +#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN7_INT_TYPE_S 7 /* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) +#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) /* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V) << (RTC_GPIO_PIN8_INT_TYPE_S)) -#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN8_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S)) +#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN8_INT_TYPE_S 7 /* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4C) +#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4C) /* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V) << (RTC_GPIO_PIN9_INT_TYPE_S)) -#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN9_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S)) +#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN9_INT_TYPE_S 7 /* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) +#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) /* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V) << (RTC_GPIO_PIN10_INT_TYPE_S)) -#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN10_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S)) +#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN10_INT_TYPE_S 7 /* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) +#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) /* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V) << (RTC_GPIO_PIN11_INT_TYPE_S)) -#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN11_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S)) +#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN11_INT_TYPE_S 7 /* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) +#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) /* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V) << (RTC_GPIO_PIN12_INT_TYPE_S)) -#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN12_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S)) +#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN12_INT_TYPE_S 7 /* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5C) +#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5C) /* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V) << (RTC_GPIO_PIN13_INT_TYPE_S)) -#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN13_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S)) +#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN13_INT_TYPE_S 7 /* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) +#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) /* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V) << (RTC_GPIO_PIN14_INT_TYPE_S)) -#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN14_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S)) +#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN14_INT_TYPE_S 7 /* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) +#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) /* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V) << (RTC_GPIO_PIN15_INT_TYPE_S)) -#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN15_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S)) +#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN15_INT_TYPE_S 7 /* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) +#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) /* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V) << (RTC_GPIO_PIN16_INT_TYPE_S)) -#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN16_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S)) +#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN16_INT_TYPE_S 7 /* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6C) +#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6C) /* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V) << (RTC_GPIO_PIN17_INT_TYPE_S)) -#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN17_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S)) +#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN17_INT_TYPE_S 7 /* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN18_REG (DR_REG_RTCIO_BASE + 0x70) +#define RTC_GPIO_PIN18_REG (DR_REG_RTCIO_BASE + 0x70) /* RTC_GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN18_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN18_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN18_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN18_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN18_INT_TYPE_M ((RTC_GPIO_PIN18_INT_TYPE_V) << (RTC_GPIO_PIN18_INT_TYPE_S)) -#define RTC_GPIO_PIN18_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN18_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN18_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN18_INT_TYPE_M ((RTC_GPIO_PIN18_INT_TYPE_V)<<(RTC_GPIO_PIN18_INT_TYPE_S)) +#define RTC_GPIO_PIN18_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN18_INT_TYPE_S 7 /* RTC_GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN18_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN18_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN18_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN18_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN18_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN18_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN19_REG (DR_REG_RTCIO_BASE + 0x74) +#define RTC_GPIO_PIN19_REG (DR_REG_RTCIO_BASE + 0x74) /* RTC_GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN19_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN19_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN19_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN19_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN19_INT_TYPE_M ((RTC_GPIO_PIN19_INT_TYPE_V) << (RTC_GPIO_PIN19_INT_TYPE_S)) -#define RTC_GPIO_PIN19_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN19_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN19_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN19_INT_TYPE_M ((RTC_GPIO_PIN19_INT_TYPE_V)<<(RTC_GPIO_PIN19_INT_TYPE_S)) +#define RTC_GPIO_PIN19_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN19_INT_TYPE_S 7 /* RTC_GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN19_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN19_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN19_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN19_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN19_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN19_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN20_REG (DR_REG_RTCIO_BASE + 0x78) +#define RTC_GPIO_PIN20_REG (DR_REG_RTCIO_BASE + 0x78) /* RTC_GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN20_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN20_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN20_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN20_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN20_INT_TYPE_M ((RTC_GPIO_PIN20_INT_TYPE_V) << (RTC_GPIO_PIN20_INT_TYPE_S)) -#define RTC_GPIO_PIN20_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN20_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN20_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN20_INT_TYPE_M ((RTC_GPIO_PIN20_INT_TYPE_V)<<(RTC_GPIO_PIN20_INT_TYPE_S)) +#define RTC_GPIO_PIN20_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN20_INT_TYPE_S 7 /* RTC_GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN20_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN20_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN20_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN20_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN20_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN20_PAD_DRIVER_S 2 -#define RTC_GPIO_PIN21_REG (DR_REG_RTCIO_BASE + 0x7C) +#define RTC_GPIO_PIN21_REG (DR_REG_RTCIO_BASE + 0x7C) /* RTC_GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: RTC GPIO wakeup enable bit*/ -#define RTC_GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN21_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN21_WAKEUP_ENABLE_S 10 +/*description: RTC GPIO wakeup enable bit.*/ +#define RTC_GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN21_WAKEUP_ENABLE_S 10 /* RTC_GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN21_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN21_INT_TYPE_M ((RTC_GPIO_PIN21_INT_TYPE_V) << (RTC_GPIO_PIN21_INT_TYPE_S)) -#define RTC_GPIO_PIN21_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN21_INT_TYPE_S 7 +/*description: if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set +to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve +l trigger, if set to 5: high level trigger.*/ +#define RTC_GPIO_PIN21_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN21_INT_TYPE_M ((RTC_GPIO_PIN21_INT_TYPE_V)<<(RTC_GPIO_PIN21_INT_TYPE_S)) +#define RTC_GPIO_PIN21_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN21_INT_TYPE_S 7 /* RTC_GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN21_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN21_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN21_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN21_PAD_DRIVER_S 2 +/*description: if set to 0: normal output, if set to 1: open drain.*/ +#define RTC_GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN21_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN21_PAD_DRIVER_S 2 -#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x80) +#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x80) /* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) -#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) -#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 -#define RTC_IO_DEBUG_12M_NO_GATING_S 25 +/*description: .*/ +#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_IO_DEBUG_12M_NO_GATING_S 25 /* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL4 0x0000001F -#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V) << (RTC_IO_DEBUG_SEL4_S)) -#define RTC_IO_DEBUG_SEL4_V 0x1F -#define RTC_IO_DEBUG_SEL4_S 20 +/*description: .*/ +#define RTC_IO_DEBUG_SEL4 0x0000001F +#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S)) +#define RTC_IO_DEBUG_SEL4_V 0x1F +#define RTC_IO_DEBUG_SEL4_S 20 /* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL3 0x0000001F -#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V) << (RTC_IO_DEBUG_SEL3_S)) -#define RTC_IO_DEBUG_SEL3_V 0x1F -#define RTC_IO_DEBUG_SEL3_S 15 +/*description: .*/ +#define RTC_IO_DEBUG_SEL3 0x0000001F +#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S)) +#define RTC_IO_DEBUG_SEL3_V 0x1F +#define RTC_IO_DEBUG_SEL3_S 15 /* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL2 0x0000001F -#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V) << (RTC_IO_DEBUG_SEL2_S)) -#define RTC_IO_DEBUG_SEL2_V 0x1F -#define RTC_IO_DEBUG_SEL2_S 10 +/*description: .*/ +#define RTC_IO_DEBUG_SEL2 0x0000001F +#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S)) +#define RTC_IO_DEBUG_SEL2_V 0x1F +#define RTC_IO_DEBUG_SEL2_S 10 /* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL1 0x0000001F -#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V) << (RTC_IO_DEBUG_SEL1_S)) -#define RTC_IO_DEBUG_SEL1_V 0x1F -#define RTC_IO_DEBUG_SEL1_S 5 +/*description: .*/ +#define RTC_IO_DEBUG_SEL1 0x0000001F +#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S)) +#define RTC_IO_DEBUG_SEL1_V 0x1F +#define RTC_IO_DEBUG_SEL1_S 5 /* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL0 0x0000001F -#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V) << (RTC_IO_DEBUG_SEL0_S)) -#define RTC_IO_DEBUG_SEL0_V 0x1F -#define RTC_IO_DEBUG_SEL0_S 0 +/*description: .*/ +#define RTC_IO_DEBUG_SEL0 0x0000001F +#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S)) +#define RTC_IO_DEBUG_SEL0_V 0x1F +#define RTC_IO_DEBUG_SEL0_S 0 -#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x84) +#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x84) /* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V) << (RTC_IO_TOUCH_PAD0_DRV_S)) -#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD0_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S)) +#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD0_DRV_S 29 /* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD0_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RDE_S 28 /* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD0_RUE_S 27 -/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD0_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V) << (RTC_IO_TOUCH_PAD0_DAC_S)) -#define RTC_IO_TOUCH_PAD0_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD0_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RUE_S 27 /* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD0_START (BIT(22)) -#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD0_START_V 0x1 -#define RTC_IO_TOUCH_PAD0_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD0_START (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_V 0x1 +#define RTC_IO_TOUCH_PAD0_START_S 22 /* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD0_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD0_XPD_S 20 /* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V) << (RTC_IO_TOUCH_PAD0_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x88) +#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x88) /* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V) << (RTC_IO_TOUCH_PAD1_DRV_S)) -#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD1_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S)) +#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD1_DRV_S 29 /* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD1_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RDE_S 28 /* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD1_RUE_S 27 -/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD1_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V) << (RTC_IO_TOUCH_PAD1_DAC_S)) -#define RTC_IO_TOUCH_PAD1_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD1_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RUE_S 27 /* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD1_START (BIT(22)) -#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD1_START_V 0x1 -#define RTC_IO_TOUCH_PAD1_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD1_START (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_V 0x1 +#define RTC_IO_TOUCH_PAD1_START_S 22 /* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD1_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD1_XPD_S 20 /* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V) << (RTC_IO_TOUCH_PAD1_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x8C) +#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x8C) /* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V) << (RTC_IO_TOUCH_PAD2_DRV_S)) -#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD2_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S)) +#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD2_DRV_S 29 /* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD2_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RDE_S 28 /* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD2_RUE_S 27 -/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD2_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V) << (RTC_IO_TOUCH_PAD2_DAC_S)) -#define RTC_IO_TOUCH_PAD2_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD2_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RUE_S 27 /* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD2_START (BIT(22)) -#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD2_START_V 0x1 -#define RTC_IO_TOUCH_PAD2_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD2_START (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_V 0x1 +#define RTC_IO_TOUCH_PAD2_START_S 22 /* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD2_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD2_XPD_S 20 /* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V) << (RTC_IO_TOUCH_PAD2_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0x90) +#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0x90) /* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V) << (RTC_IO_TOUCH_PAD3_DRV_S)) -#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD3_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S)) +#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD3_DRV_S 29 /* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD3_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RDE_S 28 /* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD3_RUE_S 27 -/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD3_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V) << (RTC_IO_TOUCH_PAD3_DAC_S)) -#define RTC_IO_TOUCH_PAD3_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD3_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RUE_S 27 /* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD3_START (BIT(22)) -#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD3_START_V 0x1 -#define RTC_IO_TOUCH_PAD3_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD3_START (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_V 0x1 +#define RTC_IO_TOUCH_PAD3_START_S 22 /* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD3_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD3_XPD_S 20 /* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V) << (RTC_IO_TOUCH_PAD3_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0x94) +#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0x94) /* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V) << (RTC_IO_TOUCH_PAD4_DRV_S)) -#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD4_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S)) +#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD4_DRV_S 29 /* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD4_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RDE_S 28 /* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD4_RUE_S 27 -/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD4_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V) << (RTC_IO_TOUCH_PAD4_DAC_S)) -#define RTC_IO_TOUCH_PAD4_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD4_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RUE_S 27 /* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD4_START (BIT(22)) -#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD4_START_V 0x1 -#define RTC_IO_TOUCH_PAD4_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD4_START (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_V 0x1 +#define RTC_IO_TOUCH_PAD4_START_S 22 /* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD4_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD4_XPD_S 20 /* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V) << (RTC_IO_TOUCH_PAD4_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0x98) +#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0x98) /* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V) << (RTC_IO_TOUCH_PAD5_DRV_S)) -#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD5_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S)) +#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD5_DRV_S 29 /* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD5_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RDE_S 28 /* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD5_RUE_S 27 -/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD5_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V) << (RTC_IO_TOUCH_PAD5_DAC_S)) -#define RTC_IO_TOUCH_PAD5_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD5_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RUE_S 27 /* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD5_START (BIT(22)) -#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD5_START_V 0x1 -#define RTC_IO_TOUCH_PAD5_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD5_START (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_V 0x1 +#define RTC_IO_TOUCH_PAD5_START_S 22 /* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD5_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD5_XPD_S 20 /* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V) << (RTC_IO_TOUCH_PAD5_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0x9C) +#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0x9C) /* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V) << (RTC_IO_TOUCH_PAD6_DRV_S)) -#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD6_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S)) +#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD6_DRV_S 29 /* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD6_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RDE_S 28 /* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD6_RUE_S 27 -/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD6_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V) << (RTC_IO_TOUCH_PAD6_DAC_S)) -#define RTC_IO_TOUCH_PAD6_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD6_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RUE_S 27 /* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD6_START (BIT(22)) -#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD6_START_V 0x1 -#define RTC_IO_TOUCH_PAD6_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD6_START (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_V 0x1 +#define RTC_IO_TOUCH_PAD6_START_S 22 /* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD6_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD6_XPD_S 20 /* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V) << (RTC_IO_TOUCH_PAD6_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xA0) +#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xA0) /* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V) << (RTC_IO_TOUCH_PAD7_DRV_S)) -#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD7_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S)) +#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD7_DRV_S 29 /* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD7_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RDE_S 28 /* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD7_RUE_S 27 -/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD7_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V) << (RTC_IO_TOUCH_PAD7_DAC_S)) -#define RTC_IO_TOUCH_PAD7_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD7_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RUE_S 27 /* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD7_START (BIT(22)) -#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD7_START_V 0x1 -#define RTC_IO_TOUCH_PAD7_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD7_START (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_V 0x1 +#define RTC_IO_TOUCH_PAD7_START_S 22 /* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD7_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD7_XPD_S 20 /* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V) << (RTC_IO_TOUCH_PAD7_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xA4) +#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xA4) /* RTC_IO_TOUCH_PAD8_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD8_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD8_DRV_M ((RTC_IO_TOUCH_PAD8_DRV_V) << (RTC_IO_TOUCH_PAD8_DRV_S)) -#define RTC_IO_TOUCH_PAD8_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD8_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD8_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD8_DRV_M ((RTC_IO_TOUCH_PAD8_DRV_V)<<(RTC_IO_TOUCH_PAD8_DRV_S)) +#define RTC_IO_TOUCH_PAD8_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD8_DRV_S 29 /* RTC_IO_TOUCH_PAD8_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD8_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD8_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD8_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD8_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD8_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD8_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD8_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD8_RDE_S 28 /* RTC_IO_TOUCH_PAD8_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD8_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD8_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD8_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD8_RUE_S 27 -/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD8_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V) << (RTC_IO_TOUCH_PAD8_DAC_S)) -#define RTC_IO_TOUCH_PAD8_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD8_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD8_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD8_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD8_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD8_RUE_S 27 /* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD8_START (BIT(22)) -#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD8_START_V 0x1 -#define RTC_IO_TOUCH_PAD8_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD8_START (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_V 0x1 +#define RTC_IO_TOUCH_PAD8_START_S 22 /* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD8_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD8_XPD_S 20 /* RTC_IO_TOUCH_PAD8_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD8_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD8_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD8_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD8_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD8_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD8_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD8_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD8_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD8_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD8_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD8_FUN_SEL_M ((RTC_IO_TOUCH_PAD8_FUN_SEL_V) << (RTC_IO_TOUCH_PAD8_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD8_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD8_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD8_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD8_FUN_SEL_M ((RTC_IO_TOUCH_PAD8_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD8_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD8_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD8_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD8_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD8_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD8_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD8_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD8_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD8_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD8_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD8_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD8_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD8_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD8_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD8_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD8_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD8_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD8_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD8_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD8_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD8_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD8_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD8_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD8_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD8_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD8_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD8_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD8_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD8_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD8_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD8_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD8_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD8_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD8_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD8_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD8_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD8_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD8_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD8_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xA8) +#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xA8) /* RTC_IO_TOUCH_PAD9_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD9_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD9_DRV_M ((RTC_IO_TOUCH_PAD9_DRV_V) << (RTC_IO_TOUCH_PAD9_DRV_S)) -#define RTC_IO_TOUCH_PAD9_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD9_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD9_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD9_DRV_M ((RTC_IO_TOUCH_PAD9_DRV_V)<<(RTC_IO_TOUCH_PAD9_DRV_S)) +#define RTC_IO_TOUCH_PAD9_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD9_DRV_S 29 /* RTC_IO_TOUCH_PAD9_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD9_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD9_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD9_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD9_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD9_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD9_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD9_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD9_RDE_S 28 /* RTC_IO_TOUCH_PAD9_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD9_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD9_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD9_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD9_RUE_S 27 -/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD9_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V) << (RTC_IO_TOUCH_PAD9_DAC_S)) -#define RTC_IO_TOUCH_PAD9_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD9_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD9_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD9_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD9_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD9_RUE_S 27 /* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD9_START (BIT(22)) -#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD9_START_V 0x1 -#define RTC_IO_TOUCH_PAD9_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD9_START (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_V 0x1 +#define RTC_IO_TOUCH_PAD9_START_S 22 /* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD9_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD9_XPD_S 20 /* RTC_IO_TOUCH_PAD9_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD9_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD9_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD9_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD9_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD9_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD9_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD9_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD9_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD9_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD9_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD9_FUN_SEL_M ((RTC_IO_TOUCH_PAD9_FUN_SEL_V) << (RTC_IO_TOUCH_PAD9_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD9_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD9_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD9_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD9_FUN_SEL_M ((RTC_IO_TOUCH_PAD9_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD9_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD9_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD9_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD9_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD9_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD9_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD9_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD9_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD9_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD9_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD9_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD9_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD9_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD9_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD9_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD9_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD9_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD9_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD9_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD9_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD9_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD9_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD9_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD9_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD9_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD9_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD9_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD9_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD9_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD9_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD9_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD9_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD9_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD9_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD9_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD9_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD9_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD9_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD9_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD10_REG (DR_REG_RTCIO_BASE + 0xAC) +#define RTC_IO_TOUCH_PAD10_REG (DR_REG_RTCIO_BASE + 0xAC) /* RTC_IO_TOUCH_PAD10_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD10_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD10_DRV_M ((RTC_IO_TOUCH_PAD10_DRV_V) << (RTC_IO_TOUCH_PAD10_DRV_S)) -#define RTC_IO_TOUCH_PAD10_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD10_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD10_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD10_DRV_M ((RTC_IO_TOUCH_PAD10_DRV_V)<<(RTC_IO_TOUCH_PAD10_DRV_S)) +#define RTC_IO_TOUCH_PAD10_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD10_DRV_S 29 /* RTC_IO_TOUCH_PAD10_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD10_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD10_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD10_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD10_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD10_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD10_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD10_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD10_RDE_S 28 /* RTC_IO_TOUCH_PAD10_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD10_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD10_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD10_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD10_RUE_S 27 -/* RTC_IO_TOUCH_PAD10_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD10_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD10_DAC_M ((RTC_IO_TOUCH_PAD10_DAC_V) << (RTC_IO_TOUCH_PAD10_DAC_S)) -#define RTC_IO_TOUCH_PAD10_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD10_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD10_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD10_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD10_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD10_RUE_S 27 /* RTC_IO_TOUCH_PAD10_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD10_START (BIT(22)) -#define RTC_IO_TOUCH_PAD10_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD10_START_V 0x1 -#define RTC_IO_TOUCH_PAD10_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD10_START (BIT(22)) +#define RTC_IO_TOUCH_PAD10_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD10_START_V 0x1 +#define RTC_IO_TOUCH_PAD10_START_S 22 /* RTC_IO_TOUCH_PAD10_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD10_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD10_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD10_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD10_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD10_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD10_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD10_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD10_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD10_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD10_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD10_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD10_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD10_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD10_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD10_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD10_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD10_XPD_S 20 /* RTC_IO_TOUCH_PAD10_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD10_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD10_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD10_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD10_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD10_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD10_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD10_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD10_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD10_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD10_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD10_FUN_SEL_M ((RTC_IO_TOUCH_PAD10_FUN_SEL_V) << (RTC_IO_TOUCH_PAD10_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD10_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD10_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD10_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD10_FUN_SEL_M ((RTC_IO_TOUCH_PAD10_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD10_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD10_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD10_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD10_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD10_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD10_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD10_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD10_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD10_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD10_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD10_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD10_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD10_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD10_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD10_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD10_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD10_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD10_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD10_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD10_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD10_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD10_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD10_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD10_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD10_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD10_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD10_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD10_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD10_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD10_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD10_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD10_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD10_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD10_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD10_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD10_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD10_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD10_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD10_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD11_REG (DR_REG_RTCIO_BASE + 0xB0) +#define RTC_IO_TOUCH_PAD11_REG (DR_REG_RTCIO_BASE + 0xB0) /* RTC_IO_TOUCH_PAD11_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD11_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD11_DRV_M ((RTC_IO_TOUCH_PAD11_DRV_V) << (RTC_IO_TOUCH_PAD11_DRV_S)) -#define RTC_IO_TOUCH_PAD11_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD11_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD11_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD11_DRV_M ((RTC_IO_TOUCH_PAD11_DRV_V)<<(RTC_IO_TOUCH_PAD11_DRV_S)) +#define RTC_IO_TOUCH_PAD11_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD11_DRV_S 29 /* RTC_IO_TOUCH_PAD11_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD11_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD11_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD11_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD11_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD11_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD11_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD11_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD11_RDE_S 28 /* RTC_IO_TOUCH_PAD11_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD11_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD11_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD11_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD11_RUE_S 27 -/* RTC_IO_TOUCH_PAD11_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD11_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD11_DAC_M ((RTC_IO_TOUCH_PAD11_DAC_V) << (RTC_IO_TOUCH_PAD11_DAC_S)) -#define RTC_IO_TOUCH_PAD11_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD11_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD11_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD11_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD11_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD11_RUE_S 27 /* RTC_IO_TOUCH_PAD11_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD11_START (BIT(22)) -#define RTC_IO_TOUCH_PAD11_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD11_START_V 0x1 -#define RTC_IO_TOUCH_PAD11_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD11_START (BIT(22)) +#define RTC_IO_TOUCH_PAD11_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD11_START_V 0x1 +#define RTC_IO_TOUCH_PAD11_START_S 22 /* RTC_IO_TOUCH_PAD11_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD11_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD11_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD11_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD11_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD11_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD11_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD11_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD11_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD11_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD11_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD11_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD11_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD11_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD11_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD11_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD11_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD11_XPD_S 20 /* RTC_IO_TOUCH_PAD11_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD11_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD11_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD11_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD11_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD11_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD11_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD11_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD11_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD11_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD11_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD11_FUN_SEL_M ((RTC_IO_TOUCH_PAD11_FUN_SEL_V) << (RTC_IO_TOUCH_PAD11_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD11_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD11_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD11_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD11_FUN_SEL_M ((RTC_IO_TOUCH_PAD11_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD11_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD11_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD11_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD11_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD11_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD11_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD11_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD11_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD11_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD11_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD11_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD11_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD11_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD11_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD11_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD11_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD11_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD11_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD11_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD11_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD11_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD11_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD11_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD11_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD11_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD11_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD11_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD11_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD11_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD11_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD11_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD11_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD11_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD11_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD11_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD11_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD11_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD11_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD11_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD12_REG (DR_REG_RTCIO_BASE + 0xB4) +#define RTC_IO_TOUCH_PAD12_REG (DR_REG_RTCIO_BASE + 0xB4) /* RTC_IO_TOUCH_PAD12_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD12_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD12_DRV_M ((RTC_IO_TOUCH_PAD12_DRV_V) << (RTC_IO_TOUCH_PAD12_DRV_S)) -#define RTC_IO_TOUCH_PAD12_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD12_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD12_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD12_DRV_M ((RTC_IO_TOUCH_PAD12_DRV_V)<<(RTC_IO_TOUCH_PAD12_DRV_S)) +#define RTC_IO_TOUCH_PAD12_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD12_DRV_S 29 /* RTC_IO_TOUCH_PAD12_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD12_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD12_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD12_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD12_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD12_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD12_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD12_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD12_RDE_S 28 /* RTC_IO_TOUCH_PAD12_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD12_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD12_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD12_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD12_RUE_S 27 -/* RTC_IO_TOUCH_PAD12_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD12_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD12_DAC_M ((RTC_IO_TOUCH_PAD12_DAC_V) << (RTC_IO_TOUCH_PAD12_DAC_S)) -#define RTC_IO_TOUCH_PAD12_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD12_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD12_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD12_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD12_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD12_RUE_S 27 /* RTC_IO_TOUCH_PAD12_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD12_START (BIT(22)) -#define RTC_IO_TOUCH_PAD12_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD12_START_V 0x1 -#define RTC_IO_TOUCH_PAD12_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD12_START (BIT(22)) +#define RTC_IO_TOUCH_PAD12_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD12_START_V 0x1 +#define RTC_IO_TOUCH_PAD12_START_S 22 /* RTC_IO_TOUCH_PAD12_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD12_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD12_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD12_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD12_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD12_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD12_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD12_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD12_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD12_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD12_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD12_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD12_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD12_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD12_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD12_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD12_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD12_XPD_S 20 /* RTC_IO_TOUCH_PAD12_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD12_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD12_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD12_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD12_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD12_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD12_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD12_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD12_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD12_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD12_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD12_FUN_SEL_M ((RTC_IO_TOUCH_PAD12_FUN_SEL_V) << (RTC_IO_TOUCH_PAD12_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD12_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD12_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD12_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD12_FUN_SEL_M ((RTC_IO_TOUCH_PAD12_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD12_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD12_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD12_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD12_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD12_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD12_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD12_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD12_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD12_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD12_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD12_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD12_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD12_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD12_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD12_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD12_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD12_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD12_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD12_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD12_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD12_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD12_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD12_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD12_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD12_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD12_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD12_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD12_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD12_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD12_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD12_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD12_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD12_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD12_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD12_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD12_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD12_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD12_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD12_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD13_REG (DR_REG_RTCIO_BASE + 0xB8) +#define RTC_IO_TOUCH_PAD13_REG (DR_REG_RTCIO_BASE + 0xB8) /* RTC_IO_TOUCH_PAD13_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD13_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD13_DRV_M ((RTC_IO_TOUCH_PAD13_DRV_V) << (RTC_IO_TOUCH_PAD13_DRV_S)) -#define RTC_IO_TOUCH_PAD13_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD13_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD13_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD13_DRV_M ((RTC_IO_TOUCH_PAD13_DRV_V)<<(RTC_IO_TOUCH_PAD13_DRV_S)) +#define RTC_IO_TOUCH_PAD13_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD13_DRV_S 29 /* RTC_IO_TOUCH_PAD13_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD13_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD13_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD13_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD13_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD13_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD13_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD13_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD13_RDE_S 28 /* RTC_IO_TOUCH_PAD13_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD13_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD13_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD13_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD13_RUE_S 27 -/* RTC_IO_TOUCH_PAD13_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD13_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD13_DAC_M ((RTC_IO_TOUCH_PAD13_DAC_V) << (RTC_IO_TOUCH_PAD13_DAC_S)) -#define RTC_IO_TOUCH_PAD13_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD13_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD13_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD13_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD13_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD13_RUE_S 27 /* RTC_IO_TOUCH_PAD13_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD13_START (BIT(22)) -#define RTC_IO_TOUCH_PAD13_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD13_START_V 0x1 -#define RTC_IO_TOUCH_PAD13_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD13_START (BIT(22)) +#define RTC_IO_TOUCH_PAD13_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD13_START_V 0x1 +#define RTC_IO_TOUCH_PAD13_START_S 22 /* RTC_IO_TOUCH_PAD13_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD13_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD13_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD13_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD13_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD13_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD13_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD13_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD13_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD13_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD13_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD13_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD13_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD13_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD13_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD13_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD13_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD13_XPD_S 20 /* RTC_IO_TOUCH_PAD13_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD13_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD13_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD13_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD13_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD13_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD13_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD13_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD13_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD13_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD13_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD13_FUN_SEL_M ((RTC_IO_TOUCH_PAD13_FUN_SEL_V) << (RTC_IO_TOUCH_PAD13_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD13_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD13_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD13_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD13_FUN_SEL_M ((RTC_IO_TOUCH_PAD13_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD13_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD13_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD13_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD13_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD13_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD13_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD13_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD13_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD13_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD13_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD13_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD13_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD13_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD13_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD13_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD13_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD13_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD13_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD13_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD13_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD13_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD13_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD13_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD13_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD13_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD13_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD13_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD13_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD13_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD13_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD13_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD13_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD13_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD13_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD13_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD13_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD13_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD13_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD13_FUN_IE_S 13 -#define RTC_IO_TOUCH_PAD14_REG (DR_REG_RTCIO_BASE + 0xBC) +#define RTC_IO_TOUCH_PAD14_REG (DR_REG_RTCIO_BASE + 0xBC) /* RTC_IO_TOUCH_PAD14_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_TOUCH_PAD14_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD14_DRV_M ((RTC_IO_TOUCH_PAD14_DRV_V) << (RTC_IO_TOUCH_PAD14_DRV_S)) -#define RTC_IO_TOUCH_PAD14_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD14_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_TOUCH_PAD14_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD14_DRV_M ((RTC_IO_TOUCH_PAD14_DRV_V)<<(RTC_IO_TOUCH_PAD14_DRV_S)) +#define RTC_IO_TOUCH_PAD14_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD14_DRV_S 29 /* RTC_IO_TOUCH_PAD14_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_TOUCH_PAD14_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD14_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD14_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD14_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_TOUCH_PAD14_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD14_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD14_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD14_RDE_S 28 /* RTC_IO_TOUCH_PAD14_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_TOUCH_PAD14_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD14_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD14_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD14_RUE_S 27 -/* RTC_IO_TOUCH_PAD14_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: TOUCH_DAC*/ -#define RTC_IO_TOUCH_PAD14_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD14_DAC_M ((RTC_IO_TOUCH_PAD14_DAC_V) << (RTC_IO_TOUCH_PAD14_DAC_S)) -#define RTC_IO_TOUCH_PAD14_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD14_DAC_S 23 +/*description: RUE.*/ +#define RTC_IO_TOUCH_PAD14_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD14_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD14_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD14_RUE_S 27 /* RTC_IO_TOUCH_PAD14_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: TOUCH_START*/ -#define RTC_IO_TOUCH_PAD14_START (BIT(22)) -#define RTC_IO_TOUCH_PAD14_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD14_START_V 0x1 -#define RTC_IO_TOUCH_PAD14_START_S 22 +/*description: TOUCH_START.*/ +#define RTC_IO_TOUCH_PAD14_START (BIT(22)) +#define RTC_IO_TOUCH_PAD14_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD14_START_V 0x1 +#define RTC_IO_TOUCH_PAD14_START_S 22 /* RTC_IO_TOUCH_PAD14_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: TOUCH_TIE_OPT*/ -#define RTC_IO_TOUCH_PAD14_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD14_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD14_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD14_TIE_OPT_S 21 +/*description: TOUCH_TIE_OPT.*/ +#define RTC_IO_TOUCH_PAD14_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD14_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD14_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD14_TIE_OPT_S 21 /* RTC_IO_TOUCH_PAD14_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: TOUCH_XPD*/ -#define RTC_IO_TOUCH_PAD14_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD14_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD14_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD14_XPD_S 20 +/*description: TOUCH_XPD.*/ +#define RTC_IO_TOUCH_PAD14_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD14_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD14_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD14_XPD_S 20 /* RTC_IO_TOUCH_PAD14_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_TOUCH_PAD14_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD14_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD14_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD14_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_TOUCH_PAD14_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD14_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD14_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD14_MUX_SEL_S 19 /* RTC_IO_TOUCH_PAD14_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_TOUCH_PAD14_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD14_FUN_SEL_M ((RTC_IO_TOUCH_PAD14_FUN_SEL_V) << (RTC_IO_TOUCH_PAD14_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD14_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD14_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_TOUCH_PAD14_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD14_FUN_SEL_M ((RTC_IO_TOUCH_PAD14_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD14_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD14_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD14_FUN_SEL_S 17 /* RTC_IO_TOUCH_PAD14_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_TOUCH_PAD14_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD14_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD14_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD14_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_TOUCH_PAD14_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD14_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD14_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD14_SLP_SEL_S 16 /* RTC_IO_TOUCH_PAD14_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD14_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD14_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD14_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD14_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD14_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD14_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD14_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD14_SLP_IE_S 15 /* RTC_IO_TOUCH_PAD14_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_TOUCH_PAD14_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD14_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD14_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD14_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_TOUCH_PAD14_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD14_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD14_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD14_SLP_OE_S 14 /* RTC_IO_TOUCH_PAD14_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_TOUCH_PAD14_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD14_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD14_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD14_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_TOUCH_PAD14_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD14_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD14_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD14_FUN_IE_S 13 -#define RTC_IO_XTAL_32P_PAD_REG (DR_REG_RTCIO_BASE + 0xC0) +#define RTC_IO_XTAL_32P_PAD_REG (DR_REG_RTCIO_BASE + 0xC0) /* RTC_IO_X32P_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_X32P_DRV 0x00000003 -#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V) << (RTC_IO_X32P_DRV_S)) -#define RTC_IO_X32P_DRV_V 0x3 -#define RTC_IO_X32P_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_X32P_DRV 0x00000003 +#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S)) +#define RTC_IO_X32P_DRV_V 0x3 +#define RTC_IO_X32P_DRV_S 29 /* RTC_IO_X32P_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_X32P_RDE (BIT(28)) -#define RTC_IO_X32P_RDE_M (BIT(28)) -#define RTC_IO_X32P_RDE_V 0x1 -#define RTC_IO_X32P_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_X32P_RDE (BIT(28)) +#define RTC_IO_X32P_RDE_M (BIT(28)) +#define RTC_IO_X32P_RDE_V 0x1 +#define RTC_IO_X32P_RDE_S 28 /* RTC_IO_X32P_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_X32P_RUE (BIT(27)) -#define RTC_IO_X32P_RUE_M (BIT(27)) -#define RTC_IO_X32P_RUE_V 0x1 -#define RTC_IO_X32P_RUE_S 27 +/*description: RUE.*/ +#define RTC_IO_X32P_RUE (BIT(27)) +#define RTC_IO_X32P_RUE_M (BIT(27)) +#define RTC_IO_X32P_RUE_V 0x1 +#define RTC_IO_X32P_RUE_S 27 /* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_X32P_MUX_SEL (BIT(19)) -#define RTC_IO_X32P_MUX_SEL_M (BIT(19)) -#define RTC_IO_X32P_MUX_SEL_V 0x1 -#define RTC_IO_X32P_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_X32P_MUX_SEL (BIT(19)) +#define RTC_IO_X32P_MUX_SEL_M (BIT(19)) +#define RTC_IO_X32P_MUX_SEL_V 0x1 +#define RTC_IO_X32P_MUX_SEL_S 19 /* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_X32P_FUN_SEL 0x00000003 -#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V) << (RTC_IO_X32P_FUN_SEL_S)) -#define RTC_IO_X32P_FUN_SEL_V 0x3 -#define RTC_IO_X32P_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_X32P_FUN_SEL 0x00000003 +#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S)) +#define RTC_IO_X32P_FUN_SEL_V 0x3 +#define RTC_IO_X32P_FUN_SEL_S 17 /* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_X32P_SLP_SEL (BIT(16)) -#define RTC_IO_X32P_SLP_SEL_M (BIT(16)) -#define RTC_IO_X32P_SLP_SEL_V 0x1 -#define RTC_IO_X32P_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_X32P_SLP_SEL (BIT(16)) +#define RTC_IO_X32P_SLP_SEL_M (BIT(16)) +#define RTC_IO_X32P_SLP_SEL_V 0x1 +#define RTC_IO_X32P_SLP_SEL_S 16 /* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_X32P_SLP_IE (BIT(15)) -#define RTC_IO_X32P_SLP_IE_M (BIT(15)) -#define RTC_IO_X32P_SLP_IE_V 0x1 -#define RTC_IO_X32P_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_X32P_SLP_IE (BIT(15)) +#define RTC_IO_X32P_SLP_IE_M (BIT(15)) +#define RTC_IO_X32P_SLP_IE_V 0x1 +#define RTC_IO_X32P_SLP_IE_S 15 /* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_X32P_SLP_OE (BIT(14)) -#define RTC_IO_X32P_SLP_OE_M (BIT(14)) -#define RTC_IO_X32P_SLP_OE_V 0x1 -#define RTC_IO_X32P_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_X32P_SLP_OE (BIT(14)) +#define RTC_IO_X32P_SLP_OE_M (BIT(14)) +#define RTC_IO_X32P_SLP_OE_V 0x1 +#define RTC_IO_X32P_SLP_OE_S 14 /* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_X32P_FUN_IE (BIT(13)) -#define RTC_IO_X32P_FUN_IE_M (BIT(13)) -#define RTC_IO_X32P_FUN_IE_V 0x1 -#define RTC_IO_X32P_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_X32P_FUN_IE (BIT(13)) +#define RTC_IO_X32P_FUN_IE_M (BIT(13)) +#define RTC_IO_X32P_FUN_IE_V 0x1 +#define RTC_IO_X32P_FUN_IE_S 13 -#define RTC_IO_XTAL_32N_PAD_REG (DR_REG_RTCIO_BASE + 0xC4) +#define RTC_IO_XTAL_32N_PAD_REG (DR_REG_RTCIO_BASE + 0xC4) /* RTC_IO_X32N_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_X32N_DRV 0x00000003 -#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V) << (RTC_IO_X32N_DRV_S)) -#define RTC_IO_X32N_DRV_V 0x3 -#define RTC_IO_X32N_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_X32N_DRV 0x00000003 +#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S)) +#define RTC_IO_X32N_DRV_V 0x3 +#define RTC_IO_X32N_DRV_S 29 /* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RDE*/ -#define RTC_IO_X32N_RDE (BIT(28)) -#define RTC_IO_X32N_RDE_M (BIT(28)) -#define RTC_IO_X32N_RDE_V 0x1 -#define RTC_IO_X32N_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_X32N_RDE (BIT(28)) +#define RTC_IO_X32N_RDE_M (BIT(28)) +#define RTC_IO_X32N_RDE_V 0x1 +#define RTC_IO_X32N_RDE_S 28 /* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_X32N_RUE (BIT(27)) -#define RTC_IO_X32N_RUE_M (BIT(27)) -#define RTC_IO_X32N_RUE_V 0x1 -#define RTC_IO_X32N_RUE_S 27 +/*description: RUE.*/ +#define RTC_IO_X32N_RUE (BIT(27)) +#define RTC_IO_X32N_RUE_M (BIT(27)) +#define RTC_IO_X32N_RUE_V 0x1 +#define RTC_IO_X32N_RUE_S 27 /* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_X32N_MUX_SEL (BIT(19)) -#define RTC_IO_X32N_MUX_SEL_M (BIT(19)) -#define RTC_IO_X32N_MUX_SEL_V 0x1 -#define RTC_IO_X32N_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_X32N_MUX_SEL (BIT(19)) +#define RTC_IO_X32N_MUX_SEL_M (BIT(19)) +#define RTC_IO_X32N_MUX_SEL_V 0x1 +#define RTC_IO_X32N_MUX_SEL_S 19 /* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_X32N_FUN_SEL 0x00000003 -#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V) << (RTC_IO_X32N_FUN_SEL_S)) -#define RTC_IO_X32N_FUN_SEL_V 0x3 -#define RTC_IO_X32N_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_X32N_FUN_SEL 0x00000003 +#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S)) +#define RTC_IO_X32N_FUN_SEL_V 0x3 +#define RTC_IO_X32N_FUN_SEL_S 17 /* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_X32N_SLP_SEL (BIT(16)) -#define RTC_IO_X32N_SLP_SEL_M (BIT(16)) -#define RTC_IO_X32N_SLP_SEL_V 0x1 -#define RTC_IO_X32N_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_X32N_SLP_SEL (BIT(16)) +#define RTC_IO_X32N_SLP_SEL_M (BIT(16)) +#define RTC_IO_X32N_SLP_SEL_V 0x1 +#define RTC_IO_X32N_SLP_SEL_S 16 /* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_X32N_SLP_IE (BIT(15)) -#define RTC_IO_X32N_SLP_IE_M (BIT(15)) -#define RTC_IO_X32N_SLP_IE_V 0x1 -#define RTC_IO_X32N_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_X32N_SLP_IE (BIT(15)) +#define RTC_IO_X32N_SLP_IE_M (BIT(15)) +#define RTC_IO_X32N_SLP_IE_V 0x1 +#define RTC_IO_X32N_SLP_IE_S 15 /* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_X32N_SLP_OE (BIT(14)) -#define RTC_IO_X32N_SLP_OE_M (BIT(14)) -#define RTC_IO_X32N_SLP_OE_V 0x1 -#define RTC_IO_X32N_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_X32N_SLP_OE (BIT(14)) +#define RTC_IO_X32N_SLP_OE_M (BIT(14)) +#define RTC_IO_X32N_SLP_OE_V 0x1 +#define RTC_IO_X32N_SLP_OE_S 14 /* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_X32N_FUN_IE (BIT(13)) -#define RTC_IO_X32N_FUN_IE_M (BIT(13)) -#define RTC_IO_X32N_FUN_IE_V 0x1 -#define RTC_IO_X32N_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_X32N_FUN_IE (BIT(13)) +#define RTC_IO_X32N_FUN_IE_M (BIT(13)) +#define RTC_IO_X32N_FUN_IE_V 0x1 +#define RTC_IO_X32N_FUN_IE_S 13 -#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0xC8) +#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0xC8) /* RTC_IO_PDAC1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: PDAC1_DRV*/ -#define RTC_IO_PDAC1_DRV 0x00000003 -#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V) << (RTC_IO_PDAC1_DRV_S)) -#define RTC_IO_PDAC1_DRV_V 0x3 -#define RTC_IO_PDAC1_DRV_S 29 +/*description: PDAC1_DRV.*/ +#define RTC_IO_PDAC1_DRV 0x00000003 +#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S)) +#define RTC_IO_PDAC1_DRV_V 0x3 +#define RTC_IO_PDAC1_DRV_S 29 /* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: PDAC1_RDE*/ -#define RTC_IO_PDAC1_RDE (BIT(28)) -#define RTC_IO_PDAC1_RDE_M (BIT(28)) -#define RTC_IO_PDAC1_RDE_V 0x1 -#define RTC_IO_PDAC1_RDE_S 28 +/*description: PDAC1_RDE.*/ +#define RTC_IO_PDAC1_RDE (BIT(28)) +#define RTC_IO_PDAC1_RDE_M (BIT(28)) +#define RTC_IO_PDAC1_RDE_V 0x1 +#define RTC_IO_PDAC1_RDE_S 28 /* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: PDAC1_RUE*/ -#define RTC_IO_PDAC1_RUE (BIT(27)) -#define RTC_IO_PDAC1_RUE_M (BIT(27)) -#define RTC_IO_PDAC1_RUE_V 0x1 -#define RTC_IO_PDAC1_RUE_S 27 +/*description: PDAC1_RUE.*/ +#define RTC_IO_PDAC1_RUE (BIT(27)) +#define RTC_IO_PDAC1_RUE_M (BIT(27)) +#define RTC_IO_PDAC1_RUE_V 0x1 +#define RTC_IO_PDAC1_RUE_S 27 /* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_PDAC1_MUX_SEL (BIT(19)) -#define RTC_IO_PDAC1_MUX_SEL_M (BIT(19)) -#define RTC_IO_PDAC1_MUX_SEL_V 0x1 -#define RTC_IO_PDAC1_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_PDAC1_MUX_SEL (BIT(19)) +#define RTC_IO_PDAC1_MUX_SEL_M (BIT(19)) +#define RTC_IO_PDAC1_MUX_SEL_V 0x1 +#define RTC_IO_PDAC1_MUX_SEL_S 19 /* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: PDAC1 function sel*/ -#define RTC_IO_PDAC1_FUN_SEL 0x00000003 -#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V) << (RTC_IO_PDAC1_FUN_SEL_S)) -#define RTC_IO_PDAC1_FUN_SEL_V 0x3 -#define RTC_IO_PDAC1_FUN_SEL_S 17 +/*description: PDAC1 function sel.*/ +#define RTC_IO_PDAC1_FUN_SEL 0x00000003 +#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S)) +#define RTC_IO_PDAC1_FUN_SEL_V 0x3 +#define RTC_IO_PDAC1_FUN_SEL_S 17 /* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_PDAC1_SLP_SEL (BIT(16)) -#define RTC_IO_PDAC1_SLP_SEL_M (BIT(16)) -#define RTC_IO_PDAC1_SLP_SEL_V 0x1 -#define RTC_IO_PDAC1_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_PDAC1_SLP_SEL (BIT(16)) +#define RTC_IO_PDAC1_SLP_SEL_M (BIT(16)) +#define RTC_IO_PDAC1_SLP_SEL_V 0x1 +#define RTC_IO_PDAC1_SLP_SEL_S 16 /* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_PDAC1_SLP_IE (BIT(15)) -#define RTC_IO_PDAC1_SLP_IE_M (BIT(15)) -#define RTC_IO_PDAC1_SLP_IE_V 0x1 -#define RTC_IO_PDAC1_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_PDAC1_SLP_IE (BIT(15)) +#define RTC_IO_PDAC1_SLP_IE_M (BIT(15)) +#define RTC_IO_PDAC1_SLP_IE_V 0x1 +#define RTC_IO_PDAC1_SLP_IE_S 15 /* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_PDAC1_SLP_OE (BIT(14)) -#define RTC_IO_PDAC1_SLP_OE_M (BIT(14)) -#define RTC_IO_PDAC1_SLP_OE_V 0x1 -#define RTC_IO_PDAC1_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_PDAC1_SLP_OE (BIT(14)) +#define RTC_IO_PDAC1_SLP_OE_M (BIT(14)) +#define RTC_IO_PDAC1_SLP_OE_V 0x1 +#define RTC_IO_PDAC1_SLP_OE_S 14 /* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_PDAC1_FUN_IE (BIT(13)) -#define RTC_IO_PDAC1_FUN_IE_M (BIT(13)) -#define RTC_IO_PDAC1_FUN_IE_V 0x1 -#define RTC_IO_PDAC1_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_PDAC1_FUN_IE (BIT(13)) +#define RTC_IO_PDAC1_FUN_IE_M (BIT(13)) +#define RTC_IO_PDAC1_FUN_IE_V 0x1 +#define RTC_IO_PDAC1_FUN_IE_S 13 /* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR - ADC FSM to control PDAC1_XPD_DAC*/ -#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(12)) -#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(12)) -#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 -#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 12 +/*description: 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control +PDAC1_XPD_DAC.*/ +#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(12)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(12)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 12 /* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: PDAC1_XPD_DAC*/ -#define RTC_IO_PDAC1_XPD_DAC (BIT(11)) -#define RTC_IO_PDAC1_XPD_DAC_M (BIT(11)) -#define RTC_IO_PDAC1_XPD_DAC_V 0x1 -#define RTC_IO_PDAC1_XPD_DAC_S 11 +/*description: PDAC1_XPD_DAC.*/ +#define RTC_IO_PDAC1_XPD_DAC (BIT(11)) +#define RTC_IO_PDAC1_XPD_DAC_M (BIT(11)) +#define RTC_IO_PDAC1_XPD_DAC_V 0x1 +#define RTC_IO_PDAC1_XPD_DAC_S 11 /* RTC_IO_PDAC1_DAC : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: PDAC1_DAC*/ -#define RTC_IO_PDAC1_DAC 0x000000FF -#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V) << (RTC_IO_PDAC1_DAC_S)) -#define RTC_IO_PDAC1_DAC_V 0xFF -#define RTC_IO_PDAC1_DAC_S 3 +/*description: PDAC1_DAC.*/ +#define RTC_IO_PDAC1_DAC 0x000000FF +#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S)) +#define RTC_IO_PDAC1_DAC_V 0xFF +#define RTC_IO_PDAC1_DAC_S 3 -#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0xCC) +#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0xCC) /* RTC_IO_PDAC2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: PDAC2_DRV*/ -#define RTC_IO_PDAC2_DRV 0x00000003 -#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V) << (RTC_IO_PDAC2_DRV_S)) -#define RTC_IO_PDAC2_DRV_V 0x3 -#define RTC_IO_PDAC2_DRV_S 29 +/*description: PDAC2_DRV.*/ +#define RTC_IO_PDAC2_DRV 0x00000003 +#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S)) +#define RTC_IO_PDAC2_DRV_V 0x3 +#define RTC_IO_PDAC2_DRV_S 29 /* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: PDAC2_RDE*/ -#define RTC_IO_PDAC2_RDE (BIT(28)) -#define RTC_IO_PDAC2_RDE_M (BIT(28)) -#define RTC_IO_PDAC2_RDE_V 0x1 -#define RTC_IO_PDAC2_RDE_S 28 +/*description: PDAC2_RDE.*/ +#define RTC_IO_PDAC2_RDE (BIT(28)) +#define RTC_IO_PDAC2_RDE_M (BIT(28)) +#define RTC_IO_PDAC2_RDE_V 0x1 +#define RTC_IO_PDAC2_RDE_S 28 /* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: PDAC2_RUE*/ -#define RTC_IO_PDAC2_RUE (BIT(27)) -#define RTC_IO_PDAC2_RUE_M (BIT(27)) -#define RTC_IO_PDAC2_RUE_V 0x1 -#define RTC_IO_PDAC2_RUE_S 27 +/*description: PDAC2_RUE.*/ +#define RTC_IO_PDAC2_RUE (BIT(27)) +#define RTC_IO_PDAC2_RUE_M (BIT(27)) +#define RTC_IO_PDAC2_RUE_V 0x1 +#define RTC_IO_PDAC2_RUE_S 27 /* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_PDAC2_MUX_SEL (BIT(19)) -#define RTC_IO_PDAC2_MUX_SEL_M (BIT(19)) -#define RTC_IO_PDAC2_MUX_SEL_V 0x1 -#define RTC_IO_PDAC2_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_PDAC2_MUX_SEL (BIT(19)) +#define RTC_IO_PDAC2_MUX_SEL_M (BIT(19)) +#define RTC_IO_PDAC2_MUX_SEL_V 0x1 +#define RTC_IO_PDAC2_MUX_SEL_S 19 /* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: PDAC1 function sel*/ -#define RTC_IO_PDAC2_FUN_SEL 0x00000003 -#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V) << (RTC_IO_PDAC2_FUN_SEL_S)) -#define RTC_IO_PDAC2_FUN_SEL_V 0x3 -#define RTC_IO_PDAC2_FUN_SEL_S 17 +/*description: PDAC1 function sel.*/ +#define RTC_IO_PDAC2_FUN_SEL 0x00000003 +#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S)) +#define RTC_IO_PDAC2_FUN_SEL_V 0x3 +#define RTC_IO_PDAC2_FUN_SEL_S 17 /* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_PDAC2_SLP_SEL (BIT(16)) -#define RTC_IO_PDAC2_SLP_SEL_M (BIT(16)) -#define RTC_IO_PDAC2_SLP_SEL_V 0x1 -#define RTC_IO_PDAC2_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_PDAC2_SLP_SEL (BIT(16)) +#define RTC_IO_PDAC2_SLP_SEL_M (BIT(16)) +#define RTC_IO_PDAC2_SLP_SEL_V 0x1 +#define RTC_IO_PDAC2_SLP_SEL_S 16 /* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_PDAC2_SLP_IE (BIT(15)) -#define RTC_IO_PDAC2_SLP_IE_M (BIT(15)) -#define RTC_IO_PDAC2_SLP_IE_V 0x1 -#define RTC_IO_PDAC2_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_PDAC2_SLP_IE (BIT(15)) +#define RTC_IO_PDAC2_SLP_IE_M (BIT(15)) +#define RTC_IO_PDAC2_SLP_IE_V 0x1 +#define RTC_IO_PDAC2_SLP_IE_S 15 /* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_PDAC2_SLP_OE (BIT(14)) -#define RTC_IO_PDAC2_SLP_OE_M (BIT(14)) -#define RTC_IO_PDAC2_SLP_OE_V 0x1 -#define RTC_IO_PDAC2_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_PDAC2_SLP_OE (BIT(14)) +#define RTC_IO_PDAC2_SLP_OE_M (BIT(14)) +#define RTC_IO_PDAC2_SLP_OE_V 0x1 +#define RTC_IO_PDAC2_SLP_OE_S 14 /* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_PDAC2_FUN_IE (BIT(13)) -#define RTC_IO_PDAC2_FUN_IE_M (BIT(13)) -#define RTC_IO_PDAC2_FUN_IE_V 0x1 -#define RTC_IO_PDAC2_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_PDAC2_FUN_IE (BIT(13)) +#define RTC_IO_PDAC2_FUN_IE_M (BIT(13)) +#define RTC_IO_PDAC2_FUN_IE_V 0x1 +#define RTC_IO_PDAC2_FUN_IE_S 13 /* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC 0: use SAR - ADC FSM to control PDAC2_XPD_DAC*/ -#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(12)) -#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(12)) -#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 -#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 12 +/*description: 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control +PDAC2_XPD_DAC.*/ +#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(12)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(12)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 12 /* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: PDAC2_XPD_DAC*/ -#define RTC_IO_PDAC2_XPD_DAC (BIT(11)) -#define RTC_IO_PDAC2_XPD_DAC_M (BIT(11)) -#define RTC_IO_PDAC2_XPD_DAC_V 0x1 -#define RTC_IO_PDAC2_XPD_DAC_S 11 +/*description: PDAC2_XPD_DAC.*/ +#define RTC_IO_PDAC2_XPD_DAC (BIT(11)) +#define RTC_IO_PDAC2_XPD_DAC_M (BIT(11)) +#define RTC_IO_PDAC2_XPD_DAC_V 0x1 +#define RTC_IO_PDAC2_XPD_DAC_S 11 /* RTC_IO_PDAC2_DAC : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ -/*description: PDAC2_DAC*/ -#define RTC_IO_PDAC2_DAC 0x000000FF -#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V) << (RTC_IO_PDAC2_DAC_S)) -#define RTC_IO_PDAC2_DAC_V 0xFF -#define RTC_IO_PDAC2_DAC_S 3 +/*description: PDAC2_DAC.*/ +#define RTC_IO_PDAC2_DAC 0x000000FF +#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S)) +#define RTC_IO_PDAC2_DAC_V 0xFF +#define RTC_IO_PDAC2_DAC_S 3 -#define RTC_IO_RTC_PAD19_REG (DR_REG_RTCIO_BASE + 0xD0) +#define RTC_IO_RTC_PAD19_REG (DR_REG_RTCIO_BASE + 0xD0) /* RTC_IO_PAD19_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_PAD19_DRV 0x00000003 -#define RTC_IO_PAD19_DRV_M ((RTC_IO_PAD19_DRV_V) << (RTC_IO_PAD19_DRV_S)) -#define RTC_IO_PAD19_DRV_V 0x3 -#define RTC_IO_PAD19_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_PAD19_DRV 0x00000003 +#define RTC_IO_PAD19_DRV_M ((RTC_IO_PAD19_DRV_V)<<(RTC_IO_PAD19_DRV_S)) +#define RTC_IO_PAD19_DRV_V 0x3 +#define RTC_IO_PAD19_DRV_S 29 /* RTC_IO_PAD19_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: RDE*/ -#define RTC_IO_PAD19_RDE (BIT(28)) -#define RTC_IO_PAD19_RDE_M (BIT(28)) -#define RTC_IO_PAD19_RDE_V 0x1 -#define RTC_IO_PAD19_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_PAD19_RDE (BIT(28)) +#define RTC_IO_PAD19_RDE_M (BIT(28)) +#define RTC_IO_PAD19_RDE_V 0x1 +#define RTC_IO_PAD19_RDE_S 28 /* RTC_IO_PAD19_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_PAD19_RUE (BIT(27)) -#define RTC_IO_PAD19_RUE_M (BIT(27)) -#define RTC_IO_PAD19_RUE_V 0x1 -#define RTC_IO_PAD19_RUE_S 27 +/*description: RUE.*/ +#define RTC_IO_PAD19_RUE (BIT(27)) +#define RTC_IO_PAD19_RUE_M (BIT(27)) +#define RTC_IO_PAD19_RUE_V 0x1 +#define RTC_IO_PAD19_RUE_S 27 /* RTC_IO_PAD19_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_PAD19_MUX_SEL (BIT(19)) -#define RTC_IO_PAD19_MUX_SEL_M (BIT(19)) -#define RTC_IO_PAD19_MUX_SEL_V 0x1 -#define RTC_IO_PAD19_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_PAD19_MUX_SEL (BIT(19)) +#define RTC_IO_PAD19_MUX_SEL_M (BIT(19)) +#define RTC_IO_PAD19_MUX_SEL_V 0x1 +#define RTC_IO_PAD19_MUX_SEL_S 19 /* RTC_IO_PAD19_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_PAD19_FUN_SEL 0x00000003 -#define RTC_IO_PAD19_FUN_SEL_M ((RTC_IO_PAD19_FUN_SEL_V) << (RTC_IO_PAD19_FUN_SEL_S)) -#define RTC_IO_PAD19_FUN_SEL_V 0x3 -#define RTC_IO_PAD19_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_PAD19_FUN_SEL 0x00000003 +#define RTC_IO_PAD19_FUN_SEL_M ((RTC_IO_PAD19_FUN_SEL_V)<<(RTC_IO_PAD19_FUN_SEL_S)) +#define RTC_IO_PAD19_FUN_SEL_V 0x3 +#define RTC_IO_PAD19_FUN_SEL_S 17 /* RTC_IO_PAD19_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_PAD19_SLP_SEL (BIT(16)) -#define RTC_IO_PAD19_SLP_SEL_M (BIT(16)) -#define RTC_IO_PAD19_SLP_SEL_V 0x1 -#define RTC_IO_PAD19_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_PAD19_SLP_SEL (BIT(16)) +#define RTC_IO_PAD19_SLP_SEL_M (BIT(16)) +#define RTC_IO_PAD19_SLP_SEL_V 0x1 +#define RTC_IO_PAD19_SLP_SEL_S 16 /* RTC_IO_PAD19_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_PAD19_SLP_IE (BIT(15)) -#define RTC_IO_PAD19_SLP_IE_M (BIT(15)) -#define RTC_IO_PAD19_SLP_IE_V 0x1 -#define RTC_IO_PAD19_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_PAD19_SLP_IE (BIT(15)) +#define RTC_IO_PAD19_SLP_IE_M (BIT(15)) +#define RTC_IO_PAD19_SLP_IE_V 0x1 +#define RTC_IO_PAD19_SLP_IE_S 15 /* RTC_IO_PAD19_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_PAD19_SLP_OE (BIT(14)) -#define RTC_IO_PAD19_SLP_OE_M (BIT(14)) -#define RTC_IO_PAD19_SLP_OE_V 0x1 -#define RTC_IO_PAD19_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_PAD19_SLP_OE (BIT(14)) +#define RTC_IO_PAD19_SLP_OE_M (BIT(14)) +#define RTC_IO_PAD19_SLP_OE_V 0x1 +#define RTC_IO_PAD19_SLP_OE_S 14 /* RTC_IO_PAD19_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_PAD19_FUN_IE (BIT(13)) -#define RTC_IO_PAD19_FUN_IE_M (BIT(13)) -#define RTC_IO_PAD19_FUN_IE_V 0x1 -#define RTC_IO_PAD19_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_PAD19_FUN_IE (BIT(13)) +#define RTC_IO_PAD19_FUN_IE_M (BIT(13)) +#define RTC_IO_PAD19_FUN_IE_V 0x1 +#define RTC_IO_PAD19_FUN_IE_S 13 -#define RTC_IO_RTC_PAD20_REG (DR_REG_RTCIO_BASE + 0xD4) +#define RTC_IO_RTC_PAD20_REG (DR_REG_RTCIO_BASE + 0xD4) /* RTC_IO_PAD20_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_PAD20_DRV 0x00000003 -#define RTC_IO_PAD20_DRV_M ((RTC_IO_PAD20_DRV_V) << (RTC_IO_PAD20_DRV_S)) -#define RTC_IO_PAD20_DRV_V 0x3 -#define RTC_IO_PAD20_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_PAD20_DRV 0x00000003 +#define RTC_IO_PAD20_DRV_M ((RTC_IO_PAD20_DRV_V)<<(RTC_IO_PAD20_DRV_S)) +#define RTC_IO_PAD20_DRV_V 0x3 +#define RTC_IO_PAD20_DRV_S 29 /* RTC_IO_PAD20_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: RDE*/ -#define RTC_IO_PAD20_RDE (BIT(28)) -#define RTC_IO_PAD20_RDE_M (BIT(28)) -#define RTC_IO_PAD20_RDE_V 0x1 -#define RTC_IO_PAD20_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_PAD20_RDE (BIT(28)) +#define RTC_IO_PAD20_RDE_M (BIT(28)) +#define RTC_IO_PAD20_RDE_V 0x1 +#define RTC_IO_PAD20_RDE_S 28 /* RTC_IO_PAD20_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_PAD20_RUE (BIT(27)) -#define RTC_IO_PAD20_RUE_M (BIT(27)) -#define RTC_IO_PAD20_RUE_V 0x1 -#define RTC_IO_PAD20_RUE_S 27 +/*description: RUE.*/ +#define RTC_IO_PAD20_RUE (BIT(27)) +#define RTC_IO_PAD20_RUE_M (BIT(27)) +#define RTC_IO_PAD20_RUE_V 0x1 +#define RTC_IO_PAD20_RUE_S 27 /* RTC_IO_PAD20_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_PAD20_MUX_SEL (BIT(19)) -#define RTC_IO_PAD20_MUX_SEL_M (BIT(19)) -#define RTC_IO_PAD20_MUX_SEL_V 0x1 -#define RTC_IO_PAD20_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_PAD20_MUX_SEL (BIT(19)) +#define RTC_IO_PAD20_MUX_SEL_M (BIT(19)) +#define RTC_IO_PAD20_MUX_SEL_V 0x1 +#define RTC_IO_PAD20_MUX_SEL_S 19 /* RTC_IO_PAD20_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_PAD20_FUN_SEL 0x00000003 -#define RTC_IO_PAD20_FUN_SEL_M ((RTC_IO_PAD20_FUN_SEL_V) << (RTC_IO_PAD20_FUN_SEL_S)) -#define RTC_IO_PAD20_FUN_SEL_V 0x3 -#define RTC_IO_PAD20_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_PAD20_FUN_SEL 0x00000003 +#define RTC_IO_PAD20_FUN_SEL_M ((RTC_IO_PAD20_FUN_SEL_V)<<(RTC_IO_PAD20_FUN_SEL_S)) +#define RTC_IO_PAD20_FUN_SEL_V 0x3 +#define RTC_IO_PAD20_FUN_SEL_S 17 /* RTC_IO_PAD20_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_PAD20_SLP_SEL (BIT(16)) -#define RTC_IO_PAD20_SLP_SEL_M (BIT(16)) -#define RTC_IO_PAD20_SLP_SEL_V 0x1 -#define RTC_IO_PAD20_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_PAD20_SLP_SEL (BIT(16)) +#define RTC_IO_PAD20_SLP_SEL_M (BIT(16)) +#define RTC_IO_PAD20_SLP_SEL_V 0x1 +#define RTC_IO_PAD20_SLP_SEL_S 16 /* RTC_IO_PAD20_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_PAD20_SLP_IE (BIT(15)) -#define RTC_IO_PAD20_SLP_IE_M (BIT(15)) -#define RTC_IO_PAD20_SLP_IE_V 0x1 -#define RTC_IO_PAD20_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_PAD20_SLP_IE (BIT(15)) +#define RTC_IO_PAD20_SLP_IE_M (BIT(15)) +#define RTC_IO_PAD20_SLP_IE_V 0x1 +#define RTC_IO_PAD20_SLP_IE_S 15 /* RTC_IO_PAD20_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_PAD20_SLP_OE (BIT(14)) -#define RTC_IO_PAD20_SLP_OE_M (BIT(14)) -#define RTC_IO_PAD20_SLP_OE_V 0x1 -#define RTC_IO_PAD20_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_PAD20_SLP_OE (BIT(14)) +#define RTC_IO_PAD20_SLP_OE_M (BIT(14)) +#define RTC_IO_PAD20_SLP_OE_V 0x1 +#define RTC_IO_PAD20_SLP_OE_S 14 /* RTC_IO_PAD20_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_PAD20_FUN_IE (BIT(13)) -#define RTC_IO_PAD20_FUN_IE_M (BIT(13)) -#define RTC_IO_PAD20_FUN_IE_V 0x1 -#define RTC_IO_PAD20_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_PAD20_FUN_IE (BIT(13)) +#define RTC_IO_PAD20_FUN_IE_M (BIT(13)) +#define RTC_IO_PAD20_FUN_IE_V 0x1 +#define RTC_IO_PAD20_FUN_IE_S 13 -#define RTC_IO_RTC_PAD21_REG (DR_REG_RTCIO_BASE + 0xD8) +#define RTC_IO_RTC_PAD21_REG (DR_REG_RTCIO_BASE + 0xD8) /* RTC_IO_PAD21_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: DRV*/ -#define RTC_IO_PAD21_DRV 0x00000003 -#define RTC_IO_PAD21_DRV_M ((RTC_IO_PAD21_DRV_V) << (RTC_IO_PAD21_DRV_S)) -#define RTC_IO_PAD21_DRV_V 0x3 -#define RTC_IO_PAD21_DRV_S 29 +/*description: DRV.*/ +#define RTC_IO_PAD21_DRV 0x00000003 +#define RTC_IO_PAD21_DRV_M ((RTC_IO_PAD21_DRV_V)<<(RTC_IO_PAD21_DRV_S)) +#define RTC_IO_PAD21_DRV_V 0x3 +#define RTC_IO_PAD21_DRV_S 29 /* RTC_IO_PAD21_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: RDE*/ -#define RTC_IO_PAD21_RDE (BIT(28)) -#define RTC_IO_PAD21_RDE_M (BIT(28)) -#define RTC_IO_PAD21_RDE_V 0x1 -#define RTC_IO_PAD21_RDE_S 28 +/*description: RDE.*/ +#define RTC_IO_PAD21_RDE (BIT(28)) +#define RTC_IO_PAD21_RDE_M (BIT(28)) +#define RTC_IO_PAD21_RDE_V 0x1 +#define RTC_IO_PAD21_RDE_S 28 /* RTC_IO_PAD21_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: RUE*/ -#define RTC_IO_PAD21_RUE (BIT(27)) -#define RTC_IO_PAD21_RUE_M (BIT(27)) -#define RTC_IO_PAD21_RUE_V 0x1 -#define RTC_IO_PAD21_RUE_S 27 +/*description: RUE.*/ +#define RTC_IO_PAD21_RUE (BIT(27)) +#define RTC_IO_PAD21_RUE_M (BIT(27)) +#define RTC_IO_PAD21_RUE_V 0x1 +#define RTC_IO_PAD21_RUE_S 27 /* RTC_IO_PAD21_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: 1: use RTC GPIO 0: use digital GPIO*/ -#define RTC_IO_PAD21_MUX_SEL (BIT(19)) -#define RTC_IO_PAD21_MUX_SEL_M (BIT(19)) -#define RTC_IO_PAD21_MUX_SEL_V 0x1 -#define RTC_IO_PAD21_MUX_SEL_S 19 +/*description: 1: use RTC GPIO,0: use digital GPIO.*/ +#define RTC_IO_PAD21_MUX_SEL (BIT(19)) +#define RTC_IO_PAD21_MUX_SEL_M (BIT(19)) +#define RTC_IO_PAD21_MUX_SEL_V 0x1 +#define RTC_IO_PAD21_MUX_SEL_S 19 /* RTC_IO_PAD21_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: function sel*/ -#define RTC_IO_PAD21_FUN_SEL 0x00000003 -#define RTC_IO_PAD21_FUN_SEL_M ((RTC_IO_PAD21_FUN_SEL_V) << (RTC_IO_PAD21_FUN_SEL_S)) -#define RTC_IO_PAD21_FUN_SEL_V 0x3 -#define RTC_IO_PAD21_FUN_SEL_S 17 +/*description: function sel.*/ +#define RTC_IO_PAD21_FUN_SEL 0x00000003 +#define RTC_IO_PAD21_FUN_SEL_M ((RTC_IO_PAD21_FUN_SEL_V)<<(RTC_IO_PAD21_FUN_SEL_S)) +#define RTC_IO_PAD21_FUN_SEL_V 0x3 +#define RTC_IO_PAD21_FUN_SEL_S 17 /* RTC_IO_PAD21_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ -#define RTC_IO_PAD21_SLP_SEL (BIT(16)) -#define RTC_IO_PAD21_SLP_SEL_M (BIT(16)) -#define RTC_IO_PAD21_SLP_SEL_V 0x1 -#define RTC_IO_PAD21_SLP_SEL_S 16 +/*description: 1: enable sleep mode during sleep,0: no sleep mode.*/ +#define RTC_IO_PAD21_SLP_SEL (BIT(16)) +#define RTC_IO_PAD21_SLP_SEL_M (BIT(16)) +#define RTC_IO_PAD21_SLP_SEL_V 0x1 +#define RTC_IO_PAD21_SLP_SEL_S 16 /* RTC_IO_PAD21_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: input enable in sleep mode*/ -#define RTC_IO_PAD21_SLP_IE (BIT(15)) -#define RTC_IO_PAD21_SLP_IE_M (BIT(15)) -#define RTC_IO_PAD21_SLP_IE_V 0x1 -#define RTC_IO_PAD21_SLP_IE_S 15 +/*description: input enable in sleep mode.*/ +#define RTC_IO_PAD21_SLP_IE (BIT(15)) +#define RTC_IO_PAD21_SLP_IE_M (BIT(15)) +#define RTC_IO_PAD21_SLP_IE_V 0x1 +#define RTC_IO_PAD21_SLP_IE_S 15 /* RTC_IO_PAD21_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: output enable in sleep mode*/ -#define RTC_IO_PAD21_SLP_OE (BIT(14)) -#define RTC_IO_PAD21_SLP_OE_M (BIT(14)) -#define RTC_IO_PAD21_SLP_OE_V 0x1 -#define RTC_IO_PAD21_SLP_OE_S 14 +/*description: output enable in sleep mode.*/ +#define RTC_IO_PAD21_SLP_OE (BIT(14)) +#define RTC_IO_PAD21_SLP_OE_M (BIT(14)) +#define RTC_IO_PAD21_SLP_OE_V 0x1 +#define RTC_IO_PAD21_SLP_OE_S 14 /* RTC_IO_PAD21_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: input enable in work mode*/ -#define RTC_IO_PAD21_FUN_IE (BIT(13)) -#define RTC_IO_PAD21_FUN_IE_M (BIT(13)) -#define RTC_IO_PAD21_FUN_IE_V 0x1 -#define RTC_IO_PAD21_FUN_IE_S 13 +/*description: input enable in work mode.*/ +#define RTC_IO_PAD21_FUN_IE (BIT(13)) +#define RTC_IO_PAD21_FUN_IE_M (BIT(13)) +#define RTC_IO_PAD21_FUN_IE_V 0x1 +#define RTC_IO_PAD21_FUN_IE_S 13 -#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xDC) +#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xDC) /* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F -#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V) << (RTC_IO_EXT_WAKEUP0_SEL_S)) -#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F -#define RTC_IO_EXT_WAKEUP0_SEL_S 27 +/*description: .*/ +#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F +#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) +#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F +#define RTC_IO_EXT_WAKEUP0_SEL_S 27 -#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xE0) +#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xE0) /* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ -/*description: select RTC GPIO 0 ~ 17 to control XTAL*/ -#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F -#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V) << (RTC_IO_XTL_EXT_CTR_SEL_S)) -#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F -#define RTC_IO_XTL_EXT_CTR_SEL_S 27 +/*description: select RTC GPIO 0 ~ 17 to control XTAL.*/ +#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F +#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) +#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F +#define RTC_IO_XTL_EXT_CTR_SEL_S 27 -#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xE4) +#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xE4) /* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 -#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V) << (RTC_IO_SAR_I2C_SDA_SEL_S)) -#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 -#define RTC_IO_SAR_I2C_SDA_SEL_S 30 +/*description: .*/ +#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S)) +#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SDA_SEL_S 30 /* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: */ -#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 -#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V) << (RTC_IO_SAR_I2C_SCL_SEL_S)) -#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 -#define RTC_IO_SAR_I2C_SCL_SEL_S 28 +/*description: .*/ +#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S)) +#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SCL_SEL_S 28 /* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */ -/*description: */ -#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F -#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V) << (RTC_IO_SAR_DEBUG_BIT_SEL_S)) -#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F -#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 +/*description: .*/ +#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F +#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S)) +#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F +#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 -#define RTC_IO_TOUCH_CTRL_REG (DR_REG_RTCIO_BASE + 0xE8) +#define RTC_IO_TOUCH_CTRL_REG (DR_REG_RTCIO_BASE + 0xE8) /* RTC_IO_IO_TOUCH_BUFMODE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: BUF_MODE when touch work without fsm*/ -#define RTC_IO_IO_TOUCH_BUFMODE (BIT(4)) -#define RTC_IO_IO_TOUCH_BUFMODE_M (BIT(4)) -#define RTC_IO_IO_TOUCH_BUFMODE_V 0x1 -#define RTC_IO_IO_TOUCH_BUFMODE_S 4 +/*description: BUF_MODE when touch work without fsm.*/ +#define RTC_IO_IO_TOUCH_BUFMODE (BIT(4)) +#define RTC_IO_IO_TOUCH_BUFMODE_M (BIT(4)) +#define RTC_IO_IO_TOUCH_BUFMODE_V 0x1 +#define RTC_IO_IO_TOUCH_BUFMODE_S 4 /* RTC_IO_IO_TOUCH_BUFSEL : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ -/*description: BUF_SEL when touch work without fsm*/ -#define RTC_IO_IO_TOUCH_BUFSEL 0x0000000F -#define RTC_IO_IO_TOUCH_BUFSEL_M ((RTC_IO_IO_TOUCH_BUFSEL_V) << (RTC_IO_IO_TOUCH_BUFSEL_S)) -#define RTC_IO_IO_TOUCH_BUFSEL_V 0xF -#define RTC_IO_IO_TOUCH_BUFSEL_S 0 +/*description: BUF_SEL when touch work without fsm.*/ +#define RTC_IO_IO_TOUCH_BUFSEL 0x0000000F +#define RTC_IO_IO_TOUCH_BUFSEL_M ((RTC_IO_IO_TOUCH_BUFSEL_V)<<(RTC_IO_IO_TOUCH_BUFSEL_S)) +#define RTC_IO_IO_TOUCH_BUFSEL_V 0xF +#define RTC_IO_IO_TOUCH_BUFSEL_S 0 + +#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x1FC) +/* RTC_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */ +/*description: .*/ +#define RTC_IO_DATE 0x0FFFFFFF +#define RTC_IO_DATE_M ((RTC_IO_DATE_V)<<(RTC_IO_DATE_S)) +#define RTC_IO_DATE_V 0xFFFFFFF +#define RTC_IO_DATE_S 0 -#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x1FC) -/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1903170 ; */ -/*description: */ -#define RTC_IO_IO_DATE 0x0FFFFFFF -#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V) << (RTC_IO_IO_DATE_S)) -#define RTC_IO_IO_DATE_V 0xFFFFFFF -#define RTC_IO_IO_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_RTC_IO_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/rtc_io_struct.h b/components/soc/esp32s3/include/soc/rtc_io_struct.h index 70d2e24c09..4f434822bc 100644 --- a/components/soc/esp32s3/include/soc/rtc_io_struct.h +++ b/components/soc/esp32s3/include/soc/rtc_io_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,262 +11,263 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_RTC_IO_STRUCT_H_ +#define _SOC_RTC_IO_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { union { struct { - uint32_t reserved0: 10; - uint32_t data: 22; /*RTC GPIO 0 ~ 21 output data*/ + uint32_t reserved0 : 10; + uint32_t data : 22; /*RTC GPIO 0 ~ 21 output data*/ }; uint32_t val; } out; union { struct { - uint32_t reserved0: 10; - uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/ + uint32_t reserved0 : 10; + uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/ }; uint32_t val; } out_w1ts; union { struct { - uint32_t reserved0: 10; - uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/ + uint32_t reserved0 : 10; + uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/ }; uint32_t val; } out_w1tc; union { struct { - uint32_t reserved0: 10; - uint32_t enable: 22; /*RTC GPIO 0 ~ 21 enable*/ + uint32_t reserved0 : 10; + uint32_t enable : 22; /*RTC GPIO 0 ~ 21 enable*/ }; uint32_t val; } enable; union { struct { - uint32_t reserved0: 10; - uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/ + uint32_t reserved0 : 10; + uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/ }; uint32_t val; } enable_w1ts; union { struct { - uint32_t reserved0: 10; - uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/ + uint32_t reserved0 : 10; + uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/ }; uint32_t val; } enable_w1tc; union { struct { - uint32_t reserved0: 10; - uint32_t status: 22; /*RTC GPIO 0 ~ 21 interrupt status*/ + uint32_t reserved0 : 10; + uint32_t status : 22; /*RTC GPIO 0 ~ 21 interrupt status*/ }; uint32_t val; } status; union { struct { - uint32_t reserved0: 10; - uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/ + uint32_t reserved0 : 10; + uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/ }; uint32_t val; } status_w1ts; union { struct { - uint32_t reserved0: 10; - uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/ + uint32_t reserved0 : 10; + uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/ }; uint32_t val; } status_w1tc; union { struct { - uint32_t reserved0: 10; - uint32_t in: 22; /*RTC GPIO input data*/ + uint32_t reserved0 : 10; + uint32_t in : 22; /*RTC GPIO input data*/ }; uint32_t val; } in_val; union { struct { - uint32_t reserved0: 2; - uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ - uint32_t reserved3: 4; - uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ - uint32_t wakeup_enable: 1; /*RTC GPIO wakeup enable bit*/ - uint32_t reserved11: 21; + uint32_t reserved0 : 2; + uint32_t pad_driver : 1; /*if set to 0: normal output, if set to 1: open drain*/ + uint32_t reserved3 : 4; + uint32_t int_type : 3; /*if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger*/ + uint32_t wakeup_enable : 1; /*RTC GPIO wakeup enable bit*/ + uint32_t reserved11 : 21; }; uint32_t val; } pin[22]; union { struct { - uint32_t sel0: 5; - uint32_t sel1: 5; - uint32_t sel2: 5; - uint32_t sel3: 5; - uint32_t sel4: 5; - uint32_t no_gating_12m: 1; - uint32_t reserved26: 6; + uint32_t sel0 : 5; + uint32_t sel1 : 5; + uint32_t sel2 : 5; + uint32_t sel3 : 5; + uint32_t sel4 : 5; + uint32_t no_gating_12m : 1; + uint32_t reserved26 : 6; }; uint32_t val; } debug_sel; union { struct { - uint32_t reserved0: 13; - uint32_t fun_ie: 1; /*input enable in work mode*/ - uint32_t slp_oe: 1; /*output enable in sleep mode*/ - uint32_t slp_ie: 1; /*input enable in sleep mode*/ - uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ - uint32_t fun_sel: 2; /*function sel*/ - uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ - uint32_t xpd: 1; /*TOUCH_XPD*/ - uint32_t tie_opt: 1; /*TOUCH_TIE_OPT*/ - uint32_t start: 1; /*TOUCH_START*/ + uint32_t reserved0 : 13; + uint32_t fun_ie : 1; /*input enable in work mode*/ + uint32_t slp_oe : 1; /*output enable in sleep mode*/ + uint32_t slp_ie : 1; /*input enable in sleep mode*/ + uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/ + uint32_t fun_sel : 2; /*function sel*/ + uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/ + uint32_t xpd : 1; /*TOUCH_XPD*/ + uint32_t tie_opt : 1; /*TOUCH_TIE_OPT*/ + uint32_t start : 1; /*TOUCH_START*/ uint32_t dac: 3; /*TOUCH_DAC*/ uint32_t reserved26: 1; - uint32_t rue: 1; /*RUE*/ - uint32_t rde: 1; /*RDE*/ - uint32_t drv: 2; /*DRV*/ - uint32_t reserved31: 1; + uint32_t rue : 1; /*RUE*/ + uint32_t rde : 1; /*RDE*/ + uint32_t drv : 2; /*DRV*/ + uint32_t reserved31 : 1; }; uint32_t val; } touch_pad[15]; union { struct { - uint32_t reserved0: 13; - uint32_t x32p_fun_ie: 1; /*input enable in work mode*/ - uint32_t x32p_slp_oe: 1; /*output enable in sleep mode*/ - uint32_t x32p_slp_ie: 1; /*input enable in sleep mode*/ - uint32_t x32p_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ - uint32_t x32p_fun_sel: 2; /*function sel*/ - uint32_t x32p_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ - uint32_t reserved20: 7; - uint32_t x32p_rue: 1; /*RUE*/ - uint32_t x32p_rde: 1; /*RDE*/ - uint32_t x32p_drv: 2; /*DRV*/ - uint32_t reserved31: 1; + uint32_t reserved0 : 13; + uint32_t x32p_fun_ie : 1; /*input enable in work mode*/ + uint32_t x32p_slp_oe : 1; /*output enable in sleep mode*/ + uint32_t x32p_slp_ie : 1; /*input enable in sleep mode*/ + uint32_t x32p_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/ + uint32_t x32p_fun_sel : 2; /*function sel*/ + uint32_t x32p_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/ + uint32_t reserved20 : 7; + uint32_t x32p_rue : 1; /*RUE*/ + uint32_t x32p_rde : 1; /*RDE*/ + uint32_t x32p_drv : 2; /*DRV*/ + uint32_t reserved31 : 1; }; uint32_t val; } xtal_32p_pad; union { struct { - uint32_t reserved0: 13; - uint32_t x32n_fun_ie: 1; /*input enable in work mode*/ - uint32_t x32n_slp_oe: 1; /*output enable in sleep mode*/ - uint32_t x32n_slp_ie: 1; /*input enable in sleep mode*/ - uint32_t x32n_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ - uint32_t x32n_fun_sel: 2; /*function sel*/ - uint32_t x32n_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ - uint32_t reserved20: 7; - uint32_t x32n_rue: 1; /*RUE*/ - uint32_t x32n_rde: 1; /*RDE*/ - uint32_t x32n_drv: 2; /*DRV*/ - uint32_t reserved31: 1; + uint32_t reserved0 : 13; + uint32_t x32n_fun_ie : 1; /*input enable in work mode*/ + uint32_t x32n_slp_oe : 1; /*output enable in sleep mode*/ + uint32_t x32n_slp_ie : 1; /*input enable in sleep mode*/ + uint32_t x32n_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/ + uint32_t x32n_fun_sel : 2; /*function sel*/ + uint32_t x32n_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/ + uint32_t reserved20 : 7; + uint32_t x32n_rue : 1; /*RUE*/ + uint32_t x32n_rde : 1; /*RDE*/ + uint32_t x32n_drv : 2; /*DRV*/ + uint32_t reserved31 : 1; }; uint32_t val; } xtal_32n_pad; union { struct { - uint32_t reserved0: 3; - uint32_t dac: 8; /*PDAC1_DAC*/ - uint32_t xpd_dac: 1; /*PDAC1_XPD_DAC*/ - uint32_t dac_xpd_force: 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR ADC FSM to control PDAC1_XPD_DAC*/ - uint32_t fun_ie: 1; /*input enable in work mode*/ - uint32_t slp_oe: 1; /*output enable in sleep mode*/ - uint32_t slp_ie: 1; /*input enable in sleep mode*/ - uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ - uint32_t fun_sel: 2; /*PDAC1 function sel*/ - uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ - uint32_t reserved20: 7; - uint32_t rue: 1; /*PDAC1_RUE*/ - uint32_t rde: 1; /*PDAC1_RDE*/ - uint32_t drv: 2; /*PDAC1_DRV*/ - uint32_t reserved31: 1; + uint32_t reserved0 : 3; + uint32_t dac : 8; /*PDAC1_DAC*/ + uint32_t xpd_dac : 1; /*PDAC1_XPD_DAC*/ + uint32_t dac_xpd_force : 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC*/ + uint32_t fun_ie : 1; /*input enable in work mode*/ + uint32_t slp_oe : 1; /*output enable in sleep mode*/ + uint32_t slp_ie : 1; /*input enable in sleep mode*/ + uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/ + uint32_t fun_sel : 2; /*PDAC1 function sel*/ + uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/ + uint32_t reserved20 : 7; + uint32_t rue : 1; /*PDAC1_RUE*/ + uint32_t rde : 1; /*PDAC1_RDE*/ + uint32_t drv : 2; /*PDAC1_DRV*/ + uint32_t reserved31 : 1; }; uint32_t val; } pad_dac[2]; union { struct { - uint32_t reserved0: 13; - uint32_t rtc_pad19_fun_ie: 1; /*input enable in work mode*/ - uint32_t rtc_pad19_slp_oe: 1; /*output enable in sleep mode*/ - uint32_t rtc_pad19_slp_ie: 1; /*input enable in sleep mode*/ - uint32_t rtc_pad19_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ - uint32_t rtc_pad19_fun_sel: 2; /*function sel*/ - uint32_t rtc_pad19_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ - uint32_t reserved20: 7; - uint32_t rtc_pad19_rue: 1; /*RUE*/ - uint32_t rtc_pad19_rde: 1; /*RDE*/ - uint32_t rtc_pad19_drv: 2; /*DRV*/ - uint32_t reserved31: 1; + uint32_t reserved0 : 13; + uint32_t rtc_pad19_fun_ie : 1; /*input enable in work mode*/ + uint32_t rtc_pad19_slp_oe : 1; /*output enable in sleep mode*/ + uint32_t rtc_pad19_slp_ie : 1; /*input enable in sleep mode*/ + uint32_t rtc_pad19_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/ + uint32_t rtc_pad19_fun_sel : 2; /*function sel*/ + uint32_t rtc_pad19_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/ + uint32_t reserved20 : 7; + uint32_t rtc_pad19_rue : 1; /*RUE*/ + uint32_t rtc_pad19_rde : 1; /*RDE*/ + uint32_t rtc_pad19_drv : 2; /*DRV*/ + uint32_t reserved31 : 1; }; uint32_t val; } rtc_pad19; union { struct { - uint32_t reserved0: 13; - uint32_t rtc_pad20_fun_ie: 1; /*input enable in work mode*/ - uint32_t rtc_pad20_slp_oe: 1; /*output enable in sleep mode*/ - uint32_t rtc_pad20_slp_ie: 1; /*input enable in sleep mode*/ - uint32_t rtc_pad20_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ - uint32_t rtc_pad20_fun_sel: 2; /*function sel*/ - uint32_t rtc_pad20_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ - uint32_t reserved20: 7; - uint32_t rtc_pad20_rue: 1; /*RUE*/ - uint32_t rtc_pad20_rde: 1; /*RDE*/ - uint32_t rtc_pad20_drv: 2; /*DRV*/ - uint32_t reserved31: 1; + uint32_t reserved0 : 13; + uint32_t rtc_pad20_fun_ie : 1; /*input enable in work mode*/ + uint32_t rtc_pad20_slp_oe : 1; /*output enable in sleep mode*/ + uint32_t rtc_pad20_slp_ie : 1; /*input enable in sleep mode*/ + uint32_t rtc_pad20_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/ + uint32_t rtc_pad20_fun_sel : 2; /*function sel*/ + uint32_t rtc_pad20_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/ + uint32_t reserved20 : 7; + uint32_t rtc_pad20_rue : 1; /*RUE*/ + uint32_t rtc_pad20_rde : 1; /*RDE*/ + uint32_t rtc_pad20_drv : 2; /*DRV*/ + uint32_t reserved31 : 1; }; uint32_t val; } rtc_pad20; union { struct { - uint32_t reserved0: 13; - uint32_t rtc_pad21_fun_ie: 1; /*input enable in work mode*/ - uint32_t rtc_pad21_slp_oe: 1; /*output enable in sleep mode*/ - uint32_t rtc_pad21_slp_ie: 1; /*input enable in sleep mode*/ - uint32_t rtc_pad21_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ - uint32_t rtc_pad21_fun_sel: 2; /*function sel*/ - uint32_t rtc_pad21_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ - uint32_t reserved20: 7; - uint32_t rtc_pad21_rue: 1; /*RUE*/ - uint32_t rtc_pad21_rde: 1; /*RDE*/ - uint32_t rtc_pad21_drv: 2; /*DRV*/ - uint32_t reserved31: 1; + uint32_t reserved0 : 13; + uint32_t rtc_pad21_fun_ie : 1; /*input enable in work mode*/ + uint32_t rtc_pad21_slp_oe : 1; /*output enable in sleep mode*/ + uint32_t rtc_pad21_slp_ie : 1; /*input enable in sleep mode*/ + uint32_t rtc_pad21_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/ + uint32_t rtc_pad21_fun_sel : 2; /*function sel*/ + uint32_t rtc_pad21_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/ + uint32_t reserved20 : 7; + uint32_t rtc_pad21_rue : 1; /*RUE*/ + uint32_t rtc_pad21_rde : 1; /*RDE*/ + uint32_t rtc_pad21_drv : 2; /*DRV*/ + uint32_t reserved31 : 1; }; uint32_t val; } rtc_pad21; union { struct { - uint32_t reserved0: 27; - uint32_t sel: 5; + uint32_t reserved0 : 27; + uint32_t sel : 5; }; uint32_t val; } ext_wakeup0; union { struct { - uint32_t reserved0: 27; - uint32_t sel: 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/ + uint32_t reserved0 : 27; + uint32_t sel : 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/ }; uint32_t val; } xtl_ext_ctr; union { struct { - uint32_t reserved0: 23; - uint32_t debug_bit_sel: 5; - uint32_t scl_sel: 2; - uint32_t sda_sel: 2; + uint32_t reserved0 : 23; + uint32_t debug_bit_sel : 5; + uint32_t scl_sel : 2; + uint32_t sda_sel : 2; }; uint32_t val; } sar_i2c_io; union { struct { - uint32_t io_touch_bufsel: 4; /*BUF_SEL when touch work without fsm*/ - uint32_t io_touch_bufmode: 1; /*BUF_MODE when touch work without fsm*/ - uint32_t reserved5: 27; + uint32_t io_touch_bufsel : 4; /*BUF_SEL when touch work without fsm*/ + uint32_t io_touch_bufmode : 1; /*BUF_MODE when touch work without fsm*/ + uint32_t reserved5 : 27; }; uint32_t val; } touch_ctrl; @@ -340,15 +341,17 @@ typedef volatile struct { uint32_t reserved_1f8; union { struct { - uint32_t date: 28; - uint32_t reserved28: 4; + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } date; } rtc_io_dev_t; - extern rtc_io_dev_t RTCIO; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_RTC_IO_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/sens_reg.h b/components/soc/esp32s3/include/soc/sens_reg.h index 5be2afd38c..8fa951829b 100644 --- a/components/soc/esp32s3/include/soc/sens_reg.h +++ b/components/soc/esp32s3/include/soc/sens_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,1712 +11,1628 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SENS_REG_H_ +#define _SOC_SENS_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0000) +#define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0) /* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: enable saradc1 to send out interrupt*/ -#define SENS_SAR1_INT_EN (BIT(29)) -#define SENS_SAR1_INT_EN_M (BIT(29)) -#define SENS_SAR1_INT_EN_V 0x1 -#define SENS_SAR1_INT_EN_S 29 +/*description: enable saradc1 to send out interrupt.*/ +#define SENS_SAR1_INT_EN (BIT(29)) +#define SENS_SAR1_INT_EN_M (BIT(29)) +#define SENS_SAR1_INT_EN_V 0x1 +#define SENS_SAR1_INT_EN_S 29 /* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: Invert SAR ADC1 data*/ -#define SENS_SAR1_DATA_INV (BIT(28)) -#define SENS_SAR1_DATA_INV_M (BIT(28)) -#define SENS_SAR1_DATA_INV_V 0x1 -#define SENS_SAR1_DATA_INV_S 28 +/*description: Invert SAR ADC1 data.*/ +#define SENS_SAR1_DATA_INV (BIT(28)) +#define SENS_SAR1_DATA_INV_M (BIT(28)) +#define SENS_SAR1_DATA_INV_V 0x1 +#define SENS_SAR1_DATA_INV_S 28 /* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ -/*description: */ -#define SENS_SAR1_SAMPLE_NUM 0x000000FF -#define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR1_SAMPLE_NUM_V) << (SENS_SAR1_SAMPLE_NUM_S)) -#define SENS_SAR1_SAMPLE_NUM_V 0xFF -#define SENS_SAR1_SAMPLE_NUM_S 19 +/*description: .*/ +#define SENS_SAR1_SAMPLE_NUM 0x000000FF +#define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S)) +#define SENS_SAR1_SAMPLE_NUM_V 0xFF +#define SENS_SAR1_SAMPLE_NUM_S 19 /* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: */ -#define SENS_SAR1_CLK_GATED (BIT(18)) -#define SENS_SAR1_CLK_GATED_M (BIT(18)) -#define SENS_SAR1_CLK_GATED_V 0x1 -#define SENS_SAR1_CLK_GATED_S 18 +/*description: .*/ +#define SENS_SAR1_CLK_GATED (BIT(18)) +#define SENS_SAR1_CLK_GATED_M (BIT(18)) +#define SENS_SAR1_CLK_GATED_V 0x1 +#define SENS_SAR1_CLK_GATED_S 18 /* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: clock divider*/ -#define SENS_SAR1_CLK_DIV 0x000000FF -#define SENS_SAR1_CLK_DIV_M ((SENS_SAR1_CLK_DIV_V) << (SENS_SAR1_CLK_DIV_S)) -#define SENS_SAR1_CLK_DIV_V 0xFF -#define SENS_SAR1_CLK_DIV_S 0 +/*description: clock divider.*/ +#define SENS_SAR1_CLK_DIV 0x000000FF +#define SENS_SAR1_CLK_DIV_M ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S)) +#define SENS_SAR1_CLK_DIV_V 0xFF +#define SENS_SAR1_CLK_DIV_S 0 -#define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x0004) +#define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x4) /* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SENS_SAR1_READER_STATUS 0xFFFFFFFF -#define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V) << (SENS_SAR1_READER_STATUS_S)) -#define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF -#define SENS_SAR1_READER_STATUS_S 0 +/*description: .*/ +#define SENS_SAR1_READER_STATUS 0xFFFFFFFF +#define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S)) +#define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR1_READER_STATUS_S 0 -#define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x0008) +#define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x8) /* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 -#define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V) << (SENS_AMP_SHORT_REF_GND_FORCE_S)) -#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 -#define SENS_AMP_SHORT_REF_GND_FORCE_S 30 +/*description: .*/ +#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S)) +#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_GND_FORCE_S 30 /* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FORCE 0x00000003 -#define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V) << (SENS_AMP_SHORT_REF_FORCE_S)) -#define SENS_AMP_SHORT_REF_FORCE_V 0x3 -#define SENS_AMP_SHORT_REF_FORCE_S 28 +/*description: .*/ +#define SENS_AMP_SHORT_REF_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S)) +#define SENS_AMP_SHORT_REF_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_FORCE_S 28 /* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FORCE 0x00000003 -#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V) << (SENS_AMP_RST_FB_FORCE_S)) -#define SENS_AMP_RST_FB_FORCE_V 0x3 -#define SENS_AMP_RST_FB_FORCE_S 26 +/*description: .*/ +#define SENS_AMP_RST_FB_FORCE 0x00000003 +#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S)) +#define SENS_AMP_RST_FB_FORCE_V 0x3 +#define SENS_AMP_RST_FB_FORCE_S 26 /* SENS_FORCE_XPD_AMP : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: */ -#define SENS_FORCE_XPD_AMP 0x00000003 -#define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V) << (SENS_FORCE_XPD_AMP_S)) -#define SENS_FORCE_XPD_AMP_V 0x3 -#define SENS_FORCE_XPD_AMP_S 24 +/*description: .*/ +#define SENS_FORCE_XPD_AMP 0x00000003 +#define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S)) +#define SENS_FORCE_XPD_AMP_V 0x3 +#define SENS_FORCE_XPD_AMP_S 24 -#define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0x000c) +#define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0xC) /* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW*/ -#define SENS_SAR1_EN_PAD_FORCE (BIT(31)) -#define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) -#define SENS_SAR1_EN_PAD_FORCE_V 0x1 -#define SENS_SAR1_EN_PAD_FORCE_S 31 +/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW.*/ +#define SENS_SAR1_EN_PAD_FORCE (BIT(31)) +#define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) +#define SENS_SAR1_EN_PAD_FORCE_V 0x1 +#define SENS_SAR1_EN_PAD_FORCE_S 31 /* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ -/*description: SAR ADC1 pad enable bitmap*/ -#define SENS_SAR1_EN_PAD 0x00000FFF -#define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V) << (SENS_SAR1_EN_PAD_S)) -#define SENS_SAR1_EN_PAD_V 0xFFF -#define SENS_SAR1_EN_PAD_S 19 +/*description: SAR ADC1 pad enable bitmap.*/ +#define SENS_SAR1_EN_PAD 0x00000FFF +#define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S)) +#define SENS_SAR1_EN_PAD_V 0xFFF +#define SENS_SAR1_EN_PAD_S 19 /* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: 1: SAR ADC1 controller (in RTC) is started by SW*/ -#define SENS_MEAS1_START_FORCE (BIT(18)) -#define SENS_MEAS1_START_FORCE_M (BIT(18)) -#define SENS_MEAS1_START_FORCE_V 0x1 -#define SENS_MEAS1_START_FORCE_S 18 +/*description: 1: SAR ADC1 controller (in RTC) is started by SW.*/ +#define SENS_MEAS1_START_FORCE (BIT(18)) +#define SENS_MEAS1_START_FORCE_M (BIT(18)) +#define SENS_MEAS1_START_FORCE_V 0x1 +#define SENS_MEAS1_START_FORCE_S 18 /* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: SAR ADC1 controller (in RTC) starts conversion*/ -#define SENS_MEAS1_START_SAR (BIT(17)) -#define SENS_MEAS1_START_SAR_M (BIT(17)) -#define SENS_MEAS1_START_SAR_V 0x1 -#define SENS_MEAS1_START_SAR_S 17 +/*description: SAR ADC1 controller (in RTC) starts conversion.*/ +#define SENS_MEAS1_START_SAR (BIT(17)) +#define SENS_MEAS1_START_SAR_M (BIT(17)) +#define SENS_MEAS1_START_SAR_V 0x1 +#define SENS_MEAS1_START_SAR_S 17 /* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: SAR ADC1 conversion done indication*/ -#define SENS_MEAS1_DONE_SAR (BIT(16)) -#define SENS_MEAS1_DONE_SAR_M (BIT(16)) -#define SENS_MEAS1_DONE_SAR_V 0x1 -#define SENS_MEAS1_DONE_SAR_S 16 +/*description: SAR ADC1 conversion done indication.*/ +#define SENS_MEAS1_DONE_SAR (BIT(16)) +#define SENS_MEAS1_DONE_SAR_M (BIT(16)) +#define SENS_MEAS1_DONE_SAR_V 0x1 +#define SENS_MEAS1_DONE_SAR_S 16 /* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: SAR ADC1 data*/ -#define SENS_MEAS1_DATA_SAR 0x0000FFFF -#define SENS_MEAS1_DATA_SAR_M ((SENS_MEAS1_DATA_SAR_V) << (SENS_MEAS1_DATA_SAR_S)) -#define SENS_MEAS1_DATA_SAR_V 0xFFFF -#define SENS_MEAS1_DATA_SAR_S 0 +/*description: SAR ADC1 data.*/ +#define SENS_MEAS1_DATA_SAR 0x0000FFFF +#define SENS_MEAS1_DATA_SAR_M ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S)) +#define SENS_MEAS1_DATA_SAR_V 0xFFFF +#define SENS_MEAS1_DATA_SAR_S 0 -#define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x0010) +#define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x10) /* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL*/ -#define SENS_SAR1_DIG_FORCE (BIT(31)) -#define SENS_SAR1_DIG_FORCE_M (BIT(31)) -#define SENS_SAR1_DIG_FORCE_V 0x1 -#define SENS_SAR1_DIG_FORCE_S 31 +/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL.*/ +#define SENS_SAR1_DIG_FORCE (BIT(31)) +#define SENS_SAR1_DIG_FORCE_M (BIT(31)) +#define SENS_SAR1_DIG_FORCE_V 0x1 +#define SENS_SAR1_DIG_FORCE_S 31 -#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0014) +#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x14) /* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: 2-bit attenuation for each pad*/ -#define SENS_SAR1_ATTEN 0xFFFFFFFF -#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V) << (SENS_SAR1_ATTEN_S)) -#define SENS_SAR1_ATTEN_V 0xFFFFFFFF -#define SENS_SAR1_ATTEN_S 0 +/*description: 2-bit attenuation for each pad.*/ +#define SENS_SAR1_ATTEN 0xFFFFFFFF +#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S)) +#define SENS_SAR1_ATTEN_V 0xFFFFFFFF +#define SENS_SAR1_ATTEN_S 0 -#define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x0018) +#define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x18) /* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ -/*description: */ -#define SENS_SAR_AMP_WAIT2 0x0000FFFF -#define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V) << (SENS_SAR_AMP_WAIT2_S)) -#define SENS_SAR_AMP_WAIT2_V 0xFFFF -#define SENS_SAR_AMP_WAIT2_S 16 +/*description: .*/ +#define SENS_SAR_AMP_WAIT2 0x0000FFFF +#define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S)) +#define SENS_SAR_AMP_WAIT2_V 0xFFFF +#define SENS_SAR_AMP_WAIT2_S 16 /* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ -/*description: */ -#define SENS_SAR_AMP_WAIT1 0x0000FFFF -#define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V) << (SENS_SAR_AMP_WAIT1_S)) -#define SENS_SAR_AMP_WAIT1_V 0xFFFF -#define SENS_SAR_AMP_WAIT1_S 0 +/*description: .*/ +#define SENS_SAR_AMP_WAIT1 0x0000FFFF +#define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S)) +#define SENS_SAR_AMP_WAIT1_V 0xFFFF +#define SENS_SAR_AMP_WAIT1_S 0 -#define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x001c) +#define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x1C) /* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ -/*description: */ -#define SENS_SAR_AMP_WAIT3 0x0000FFFF -#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V) << (SENS_SAR_AMP_WAIT3_S)) -#define SENS_SAR_AMP_WAIT3_V 0xFFFF -#define SENS_SAR_AMP_WAIT3_S 16 +/*description: .*/ +#define SENS_SAR_AMP_WAIT3 0x0000FFFF +#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S)) +#define SENS_SAR_AMP_WAIT3_V 0xFFFF +#define SENS_SAR_AMP_WAIT3_S 16 /* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SAR_RSTB_FSM_IDLE (BIT(6)) -#define SENS_SAR_RSTB_FSM_IDLE_M (BIT(6)) -#define SENS_SAR_RSTB_FSM_IDLE_V 0x1 -#define SENS_SAR_RSTB_FSM_IDLE_S 6 +/*description: .*/ +#define SENS_SAR_RSTB_FSM_IDLE (BIT(6)) +#define SENS_SAR_RSTB_FSM_IDLE_M (BIT(6)) +#define SENS_SAR_RSTB_FSM_IDLE_V 0x1 +#define SENS_SAR_RSTB_FSM_IDLE_S 6 /* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_XPD_SAR_FSM_IDLE (BIT(5)) -#define SENS_XPD_SAR_FSM_IDLE_M (BIT(5)) -#define SENS_XPD_SAR_FSM_IDLE_V 0x1 -#define SENS_XPD_SAR_FSM_IDLE_S 5 +/*description: .*/ +#define SENS_XPD_SAR_FSM_IDLE (BIT(5)) +#define SENS_XPD_SAR_FSM_IDLE_M (BIT(5)) +#define SENS_XPD_SAR_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_FSM_IDLE_S 5 /* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(4)) -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(4)) -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 4 +/*description: .*/ +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(4)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(4)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 4 /* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(3)) -#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(3)) -#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 -#define SENS_AMP_SHORT_REF_FSM_IDLE_S 3 +/*description: .*/ +#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(3)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(3)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_FSM_IDLE_S 3 /* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FSM_IDLE (BIT(2)) -#define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(2)) -#define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 -#define SENS_AMP_RST_FB_FSM_IDLE_S 2 +/*description: .*/ +#define SENS_AMP_RST_FB_FSM_IDLE (BIT(2)) +#define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(2)) +#define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 +#define SENS_AMP_RST_FB_FSM_IDLE_S 2 /* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(1)) -#define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(1)) -#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 -#define SENS_XPD_SAR_AMP_FSM_IDLE_S 1 +/*description: .*/ +#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(1)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(1)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_AMP_FSM_IDLE_S 1 /* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(0)) -#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(0)) -#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 -#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 0 +/*description: .*/ +#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(0)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(0)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 +#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 0 -#define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x0020) +#define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x20) /* SENS_SAR_RSTB_FSM : R/W ;bitpos:[27:24] ;default: 4'b0000 ; */ -/*description: */ -#define SENS_SAR_RSTB_FSM 0x0000000F -#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V) << (SENS_SAR_RSTB_FSM_S)) -#define SENS_SAR_RSTB_FSM_V 0xF -#define SENS_SAR_RSTB_FSM_S 24 +/*description: .*/ +#define SENS_SAR_RSTB_FSM 0x0000000F +#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S)) +#define SENS_SAR_RSTB_FSM_V 0xF +#define SENS_SAR_RSTB_FSM_S 24 /* SENS_XPD_SAR_FSM : R/W ;bitpos:[23:20] ;default: 4'b0111 ; */ -/*description: */ -#define SENS_XPD_SAR_FSM 0x0000000F -#define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V) << (SENS_XPD_SAR_FSM_S)) -#define SENS_XPD_SAR_FSM_V 0xF -#define SENS_XPD_SAR_FSM_S 20 +/*description: .*/ +#define SENS_XPD_SAR_FSM 0x0000000F +#define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S)) +#define SENS_XPD_SAR_FSM_V 0xF +#define SENS_XPD_SAR_FSM_S 20 /* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[19:16] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F -#define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V) << (SENS_AMP_SHORT_REF_GND_FSM_S)) -#define SENS_AMP_SHORT_REF_GND_FSM_V 0xF -#define SENS_AMP_SHORT_REF_GND_FSM_S 16 +/*description: .*/ +#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S)) +#define SENS_AMP_SHORT_REF_GND_FSM_V 0xF +#define SENS_AMP_SHORT_REF_GND_FSM_S 16 /* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FSM 0x0000000F -#define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V) << (SENS_AMP_SHORT_REF_FSM_S)) -#define SENS_AMP_SHORT_REF_FSM_V 0xF -#define SENS_AMP_SHORT_REF_FSM_S 12 +/*description: .*/ +#define SENS_AMP_SHORT_REF_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S)) +#define SENS_AMP_SHORT_REF_FSM_V 0xF +#define SENS_AMP_SHORT_REF_FSM_S 12 /* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[11:8] ;default: 4'b1000 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FSM 0x0000000F -#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V) << (SENS_AMP_RST_FB_FSM_S)) -#define SENS_AMP_RST_FB_FSM_V 0xF -#define SENS_AMP_RST_FB_FSM_S 8 +/*description: .*/ +#define SENS_AMP_RST_FB_FSM 0x0000000F +#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S)) +#define SENS_AMP_RST_FB_FSM_V 0xF +#define SENS_AMP_RST_FB_FSM_S 8 /* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[7:4] ;default: 4'b1111 ; */ -/*description: */ -#define SENS_XPD_SAR_AMP_FSM 0x0000000F -#define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V) << (SENS_XPD_SAR_AMP_FSM_S)) -#define SENS_XPD_SAR_AMP_FSM_V 0xF -#define SENS_XPD_SAR_AMP_FSM_S 4 +/*description: .*/ +#define SENS_XPD_SAR_AMP_FSM 0x0000000F +#define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S)) +#define SENS_XPD_SAR_AMP_FSM_V 0xF +#define SENS_XPD_SAR_AMP_FSM_S 4 /* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_SAR1_DAC_XPD_FSM 0x0000000F -#define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V) << (SENS_SAR1_DAC_XPD_FSM_S)) -#define SENS_SAR1_DAC_XPD_FSM_V 0xF -#define SENS_SAR1_DAC_XPD_FSM_S 0 +/*description: .*/ +#define SENS_SAR1_DAC_XPD_FSM 0x0000000F +#define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S)) +#define SENS_SAR1_DAC_XPD_FSM_V 0xF +#define SENS_SAR1_DAC_XPD_FSM_S 0 -#define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x0024) +#define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x24) /* SENS_SAR2_INT_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: enable saradc2 to send out interrupt*/ -#define SENS_SAR2_INT_EN (BIT(30)) -#define SENS_SAR2_INT_EN_M (BIT(30)) -#define SENS_SAR2_INT_EN_V 0x1 -#define SENS_SAR2_INT_EN_S 30 +/*description: enable saradc2 to send out interrupt.*/ +#define SENS_SAR2_INT_EN (BIT(30)) +#define SENS_SAR2_INT_EN_M (BIT(30)) +#define SENS_SAR2_INT_EN_V 0x1 +#define SENS_SAR2_INT_EN_S 30 /* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Invert SAR ADC2 data*/ -#define SENS_SAR2_DATA_INV (BIT(29)) -#define SENS_SAR2_DATA_INV_M (BIT(29)) -#define SENS_SAR2_DATA_INV_V 0x1 -#define SENS_SAR2_DATA_INV_S 29 +/*description: Invert SAR ADC2 data.*/ +#define SENS_SAR2_DATA_INV (BIT(29)) +#define SENS_SAR2_DATA_INV_M (BIT(29)) +#define SENS_SAR2_DATA_INV_V 0x1 +#define SENS_SAR2_DATA_INV_S 29 /* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ -/*description: */ -#define SENS_SAR2_SAMPLE_NUM 0x000000FF -#define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR2_SAMPLE_NUM_V) << (SENS_SAR2_SAMPLE_NUM_S)) -#define SENS_SAR2_SAMPLE_NUM_V 0xFF -#define SENS_SAR2_SAMPLE_NUM_S 19 +/*description: .*/ +#define SENS_SAR2_SAMPLE_NUM 0x000000FF +#define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S)) +#define SENS_SAR2_SAMPLE_NUM_V 0xFF +#define SENS_SAR2_SAMPLE_NUM_S 19 /* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: */ -#define SENS_SAR2_CLK_GATED (BIT(18)) -#define SENS_SAR2_CLK_GATED_M (BIT(18)) -#define SENS_SAR2_CLK_GATED_V 0x1 -#define SENS_SAR2_CLK_GATED_S 18 +/*description: .*/ +#define SENS_SAR2_CLK_GATED (BIT(18)) +#define SENS_SAR2_CLK_GATED_M (BIT(18)) +#define SENS_SAR2_CLK_GATED_V 0x1 +#define SENS_SAR2_CLK_GATED_S 18 /* SENS_SAR2_WAIT_ARB_CYCLE : R/W ;bitpos:[17:16] ;default: 2'b1 ; */ -/*description: wait arbit stable after sar_done*/ -#define SENS_SAR2_WAIT_ARB_CYCLE 0x00000003 -#define SENS_SAR2_WAIT_ARB_CYCLE_M ((SENS_SAR2_WAIT_ARB_CYCLE_V) << (SENS_SAR2_WAIT_ARB_CYCLE_S)) -#define SENS_SAR2_WAIT_ARB_CYCLE_V 0x3 -#define SENS_SAR2_WAIT_ARB_CYCLE_S 16 +/*description: wait arbit stable after sar_done.*/ +#define SENS_SAR2_WAIT_ARB_CYCLE 0x00000003 +#define SENS_SAR2_WAIT_ARB_CYCLE_M ((SENS_SAR2_WAIT_ARB_CYCLE_V)<<(SENS_SAR2_WAIT_ARB_CYCLE_S)) +#define SENS_SAR2_WAIT_ARB_CYCLE_V 0x3 +#define SENS_SAR2_WAIT_ARB_CYCLE_S 16 /* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: clock divider*/ -#define SENS_SAR2_CLK_DIV 0x000000FF -#define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V) << (SENS_SAR2_CLK_DIV_S)) -#define SENS_SAR2_CLK_DIV_V 0xFF -#define SENS_SAR2_CLK_DIV_S 0 +/*description: clock divider.*/ +#define SENS_SAR2_CLK_DIV 0x000000FF +#define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S)) +#define SENS_SAR2_CLK_DIV_V 0xFF +#define SENS_SAR2_CLK_DIV_S 0 -#define SENS_SAR_READER2_STATUS_REG (DR_REG_SENS_BASE + 0x0028) +#define SENS_SAR_READER2_STATUS_REG (DR_REG_SENS_BASE + 0x28) /* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SENS_SAR2_READER_STATUS 0xFFFFFFFF -#define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V) << (SENS_SAR2_READER_STATUS_S)) -#define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF -#define SENS_SAR2_READER_STATUS_S 0 +/*description: .*/ +#define SENS_SAR2_READER_STATUS 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S)) +#define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_S 0 -#define SENS_SAR_MEAS2_CTRL1_REG (DR_REG_SENS_BASE + 0x002c) +#define SENS_SAR_MEAS2_CTRL1_REG (DR_REG_SENS_BASE + 0x2C) /* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ -/*description: */ -#define SENS_SAR2_XPD_WAIT 0x000000FF -#define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V) << (SENS_SAR2_XPD_WAIT_S)) -#define SENS_SAR2_XPD_WAIT_V 0xFF -#define SENS_SAR2_XPD_WAIT_S 24 +/*description: .*/ +#define SENS_SAR2_XPD_WAIT 0x000000FF +#define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S)) +#define SENS_SAR2_XPD_WAIT_V 0xFF +#define SENS_SAR2_XPD_WAIT_S 24 /* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[23:16] ;default: 8'd2 ; */ -/*description: */ -#define SENS_SAR2_RSTB_WAIT 0x000000FF -#define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V) << (SENS_SAR2_RSTB_WAIT_S)) -#define SENS_SAR2_RSTB_WAIT_V 0xFF -#define SENS_SAR2_RSTB_WAIT_S 16 +/*description: .*/ +#define SENS_SAR2_RSTB_WAIT 0x000000FF +#define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S)) +#define SENS_SAR2_RSTB_WAIT_V 0xFF +#define SENS_SAR2_RSTB_WAIT_S 16 /* SENS_SAR2_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd2 ; */ -/*description: */ -#define SENS_SAR2_STANDBY_WAIT 0x000000FF -#define SENS_SAR2_STANDBY_WAIT_M ((SENS_SAR2_STANDBY_WAIT_V) << (SENS_SAR2_STANDBY_WAIT_S)) -#define SENS_SAR2_STANDBY_WAIT_V 0xFF -#define SENS_SAR2_STANDBY_WAIT_S 8 +/*description: .*/ +#define SENS_SAR2_STANDBY_WAIT 0x000000FF +#define SENS_SAR2_STANDBY_WAIT_M ((SENS_SAR2_STANDBY_WAIT_V)<<(SENS_SAR2_STANDBY_WAIT_S)) +#define SENS_SAR2_STANDBY_WAIT_V 0xFF +#define SENS_SAR2_STANDBY_WAIT_S 8 /* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENS_SAR2_RSTB_FORCE 0x00000003 -#define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V) << (SENS_SAR2_RSTB_FORCE_S)) -#define SENS_SAR2_RSTB_FORCE_V 0x3 -#define SENS_SAR2_RSTB_FORCE_S 6 +/*description: .*/ +#define SENS_SAR2_RSTB_FORCE 0x00000003 +#define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S)) +#define SENS_SAR2_RSTB_FORCE_V 0x3 +#define SENS_SAR2_RSTB_FORCE_S 6 /* SENS_SAR2_EN_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: SAR2_EN_TEST*/ -#define SENS_SAR2_EN_TEST (BIT(5)) -#define SENS_SAR2_EN_TEST_M (BIT(5)) -#define SENS_SAR2_EN_TEST_V 0x1 -#define SENS_SAR2_EN_TEST_S 5 +/*description: SAR2_EN_TEST.*/ +#define SENS_SAR2_EN_TEST (BIT(5)) +#define SENS_SAR2_EN_TEST_M (BIT(5)) +#define SENS_SAR2_EN_TEST_V 0x1 +#define SENS_SAR2_EN_TEST_S 5 /* SENS_SAR2_PKDET_CAL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: rtc control pkdet enable*/ -#define SENS_SAR2_PKDET_CAL_EN (BIT(4)) -#define SENS_SAR2_PKDET_CAL_EN_M (BIT(4)) -#define SENS_SAR2_PKDET_CAL_EN_V 0x1 -#define SENS_SAR2_PKDET_CAL_EN_S 4 +/*description: rtc control pkdet enable.*/ +#define SENS_SAR2_PKDET_CAL_EN (BIT(4)) +#define SENS_SAR2_PKDET_CAL_EN_M (BIT(4)) +#define SENS_SAR2_PKDET_CAL_EN_V 0x1 +#define SENS_SAR2_PKDET_CAL_EN_S 4 /* SENS_SAR2_PWDET_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: rtc control pwdet enable*/ -#define SENS_SAR2_PWDET_CAL_EN (BIT(3)) -#define SENS_SAR2_PWDET_CAL_EN_M (BIT(3)) -#define SENS_SAR2_PWDET_CAL_EN_V 0x1 -#define SENS_SAR2_PWDET_CAL_EN_S 3 +/*description: rtc control pwdet enable.*/ +#define SENS_SAR2_PWDET_CAL_EN (BIT(3)) +#define SENS_SAR2_PWDET_CAL_EN_M (BIT(3)) +#define SENS_SAR2_PWDET_CAL_EN_V 0x1 +#define SENS_SAR2_PWDET_CAL_EN_S 3 /* SENS_SAR2_CNTL_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: saradc2_cntl_fsm*/ -#define SENS_SAR2_CNTL_STATE 0x00000007 -#define SENS_SAR2_CNTL_STATE_M ((SENS_SAR2_CNTL_STATE_V) << (SENS_SAR2_CNTL_STATE_S)) -#define SENS_SAR2_CNTL_STATE_V 0x7 -#define SENS_SAR2_CNTL_STATE_S 0 +/*description: saradc2_cntl_fsm.*/ +#define SENS_SAR2_CNTL_STATE 0x00000007 +#define SENS_SAR2_CNTL_STATE_M ((SENS_SAR2_CNTL_STATE_V)<<(SENS_SAR2_CNTL_STATE_S)) +#define SENS_SAR2_CNTL_STATE_V 0x7 +#define SENS_SAR2_CNTL_STATE_S 0 -#define SENS_SAR_MEAS2_CTRL2_REG (DR_REG_SENS_BASE + 0x0030) +#define SENS_SAR_MEAS2_CTRL2_REG (DR_REG_SENS_BASE + 0x30) /* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW*/ -#define SENS_SAR2_EN_PAD_FORCE (BIT(31)) -#define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) -#define SENS_SAR2_EN_PAD_FORCE_V 0x1 -#define SENS_SAR2_EN_PAD_FORCE_S 31 +/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW.*/ +#define SENS_SAR2_EN_PAD_FORCE (BIT(31)) +#define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) +#define SENS_SAR2_EN_PAD_FORCE_V 0x1 +#define SENS_SAR2_EN_PAD_FORCE_S 31 /* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ -/*description: SAR ADC2 pad enable bitmap*/ -#define SENS_SAR2_EN_PAD 0x00000FFF -#define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V) << (SENS_SAR2_EN_PAD_S)) -#define SENS_SAR2_EN_PAD_V 0xFFF -#define SENS_SAR2_EN_PAD_S 19 +/*description: SAR ADC2 pad enable bitmap.*/ +#define SENS_SAR2_EN_PAD 0x00000FFF +#define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S)) +#define SENS_SAR2_EN_PAD_V 0xFFF +#define SENS_SAR2_EN_PAD_S 19 /* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: 1: SAR ADC2 controller (in RTC) is started by SW*/ -#define SENS_MEAS2_START_FORCE (BIT(18)) -#define SENS_MEAS2_START_FORCE_M (BIT(18)) -#define SENS_MEAS2_START_FORCE_V 0x1 -#define SENS_MEAS2_START_FORCE_S 18 +/*description: 1: SAR ADC2 controller (in RTC) is started by SW.*/ +#define SENS_MEAS2_START_FORCE (BIT(18)) +#define SENS_MEAS2_START_FORCE_M (BIT(18)) +#define SENS_MEAS2_START_FORCE_V 0x1 +#define SENS_MEAS2_START_FORCE_S 18 /* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: SAR ADC2 controller (in RTC) starts conversion*/ -#define SENS_MEAS2_START_SAR (BIT(17)) -#define SENS_MEAS2_START_SAR_M (BIT(17)) -#define SENS_MEAS2_START_SAR_V 0x1 -#define SENS_MEAS2_START_SAR_S 17 +/*description: SAR ADC2 controller (in RTC) starts conversion.*/ +#define SENS_MEAS2_START_SAR (BIT(17)) +#define SENS_MEAS2_START_SAR_M (BIT(17)) +#define SENS_MEAS2_START_SAR_V 0x1 +#define SENS_MEAS2_START_SAR_S 17 /* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: SAR ADC2 conversion done indication*/ -#define SENS_MEAS2_DONE_SAR (BIT(16)) -#define SENS_MEAS2_DONE_SAR_M (BIT(16)) -#define SENS_MEAS2_DONE_SAR_V 0x1 -#define SENS_MEAS2_DONE_SAR_S 16 +/*description: SAR ADC2 conversion done indication.*/ +#define SENS_MEAS2_DONE_SAR (BIT(16)) +#define SENS_MEAS2_DONE_SAR_M (BIT(16)) +#define SENS_MEAS2_DONE_SAR_V 0x1 +#define SENS_MEAS2_DONE_SAR_S 16 /* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: SAR ADC2 data*/ -#define SENS_MEAS2_DATA_SAR 0x0000FFFF -#define SENS_MEAS2_DATA_SAR_M ((SENS_MEAS2_DATA_SAR_V) << (SENS_MEAS2_DATA_SAR_S)) -#define SENS_MEAS2_DATA_SAR_V 0xFFFF -#define SENS_MEAS2_DATA_SAR_S 0 +/*description: SAR ADC2 data.*/ +#define SENS_MEAS2_DATA_SAR 0x0000FFFF +#define SENS_MEAS2_DATA_SAR_M ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S)) +#define SENS_MEAS2_DATA_SAR_V 0xFFFF +#define SENS_MEAS2_DATA_SAR_S 0 -#define SENS_SAR_MEAS2_MUX_REG (DR_REG_SENS_BASE + 0x0034) +#define SENS_SAR_MEAS2_MUX_REG (DR_REG_SENS_BASE + 0x34) /* SENS_SAR2_RTC_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: in sleep force to use rtc to control ADC*/ -#define SENS_SAR2_RTC_FORCE (BIT(31)) -#define SENS_SAR2_RTC_FORCE_M (BIT(31)) -#define SENS_SAR2_RTC_FORCE_V 0x1 -#define SENS_SAR2_RTC_FORCE_S 31 +/*description: in sleep, force to use rtc to control ADC.*/ +#define SENS_SAR2_RTC_FORCE (BIT(31)) +#define SENS_SAR2_RTC_FORCE_M (BIT(31)) +#define SENS_SAR2_RTC_FORCE_V 0x1 +#define SENS_SAR2_RTC_FORCE_S 31 /* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: SAR2_PWDET_CCT*/ -#define SENS_SAR2_PWDET_CCT 0x00000007 -#define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V) << (SENS_SAR2_PWDET_CCT_S)) -#define SENS_SAR2_PWDET_CCT_V 0x7 -#define SENS_SAR2_PWDET_CCT_S 28 +/*description: SAR2_PWDET_CCT.*/ +#define SENS_SAR2_PWDET_CCT 0x00000007 +#define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S)) +#define SENS_SAR2_PWDET_CCT_V 0x7 +#define SENS_SAR2_PWDET_CCT_S 28 -#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038) +#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x38) /* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: 2-bit attenuation for each pad*/ -#define SENS_SAR2_ATTEN 0xFFFFFFFF -#define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V) << (SENS_SAR2_ATTEN_S)) -#define SENS_SAR2_ATTEN_V 0xFFFFFFFF -#define SENS_SAR2_ATTEN_S 0 +/*description: 2-bit attenuation for each pad.*/ +#define SENS_SAR2_ATTEN 0xFFFFFFFF +#define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S)) +#define SENS_SAR2_ATTEN_V 0xFFFFFFFF +#define SENS_SAR2_ATTEN_S 0 -#define SENS_SAR_POWER_XPD_SAR_REG (DR_REG_SENS_BASE + 0x003c) +#define SENS_SAR_POWER_XPD_SAR_REG (DR_REG_SENS_BASE + 0x3C) /* SENS_SARCLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SARCLK_EN (BIT(31)) -#define SENS_SARCLK_EN_M (BIT(31)) -#define SENS_SARCLK_EN_V 0x1 -#define SENS_SARCLK_EN_S 31 +/*description: .*/ +#define SENS_SARCLK_EN (BIT(31)) +#define SENS_SARCLK_EN_M (BIT(31)) +#define SENS_SARCLK_EN_V 0x1 +#define SENS_SARCLK_EN_S 31 /* SENS_FORCE_XPD_SAR : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ -/*description: */ -#define SENS_FORCE_XPD_SAR 0x00000003 -#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V) << (SENS_FORCE_XPD_SAR_S)) -#define SENS_FORCE_XPD_SAR_V 0x3 -#define SENS_FORCE_XPD_SAR_S 29 +/*description: .*/ +#define SENS_FORCE_XPD_SAR 0x00000003 +#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S)) +#define SENS_FORCE_XPD_SAR_V 0x3 +#define SENS_FORCE_XPD_SAR_S 29 -#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x0040) -/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ -/*description: */ -#define SENS_MEAS_STATUS 0x000000FF -#define SENS_MEAS_STATUS_M ((SENS_MEAS_STATUS_V) << (SENS_MEAS_STATUS_S)) -#define SENS_MEAS_STATUS_V 0xFF -#define SENS_MEAS_STATUS_S 22 +#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x40) +/* SENS_SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: .*/ +#define SENS_SARADC_MEAS_STATUS 0x000000FF +#define SENS_SARADC_MEAS_STATUS_M ((SENS_SARADC_MEAS_STATUS_V)<<(SENS_SARADC_MEAS_STATUS_S)) +#define SENS_SARADC_MEAS_STATUS_V 0xFF +#define SENS_SARADC_MEAS_STATUS_S 22 /* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR0 0x000007FF -#define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V) << (SENS_I2C_SLAVE_ADDR0_S)) -#define SENS_I2C_SLAVE_ADDR0_V 0x7FF -#define SENS_I2C_SLAVE_ADDR0_S 11 +/*description: .*/ +#define SENS_I2C_SLAVE_ADDR0 0x000007FF +#define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S)) +#define SENS_I2C_SLAVE_ADDR0_V 0x7FF +#define SENS_I2C_SLAVE_ADDR0_S 11 /* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR1 0x000007FF -#define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V) << (SENS_I2C_SLAVE_ADDR1_S)) -#define SENS_I2C_SLAVE_ADDR1_V 0x7FF -#define SENS_I2C_SLAVE_ADDR1_S 0 +/*description: .*/ +#define SENS_I2C_SLAVE_ADDR1 0x000007FF +#define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S)) +#define SENS_I2C_SLAVE_ADDR1_V 0x7FF +#define SENS_I2C_SLAVE_ADDR1_S 0 -#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x0044) +#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x44) /* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR2 0x000007FF -#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V) << (SENS_I2C_SLAVE_ADDR2_S)) -#define SENS_I2C_SLAVE_ADDR2_V 0x7FF -#define SENS_I2C_SLAVE_ADDR2_S 11 +/*description: .*/ +#define SENS_I2C_SLAVE_ADDR2 0x000007FF +#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S)) +#define SENS_I2C_SLAVE_ADDR2_V 0x7FF +#define SENS_I2C_SLAVE_ADDR2_S 11 /* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR3 0x000007FF -#define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V) << (SENS_I2C_SLAVE_ADDR3_S)) -#define SENS_I2C_SLAVE_ADDR3_V 0x7FF -#define SENS_I2C_SLAVE_ADDR3_S 0 +/*description: .*/ +#define SENS_I2C_SLAVE_ADDR3 0x000007FF +#define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S)) +#define SENS_I2C_SLAVE_ADDR3_V 0x7FF +#define SENS_I2C_SLAVE_ADDR3_S 0 -#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x0048) +#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x48) /* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR4 0x000007FF -#define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V) << (SENS_I2C_SLAVE_ADDR4_S)) -#define SENS_I2C_SLAVE_ADDR4_V 0x7FF -#define SENS_I2C_SLAVE_ADDR4_S 11 +/*description: .*/ +#define SENS_I2C_SLAVE_ADDR4 0x000007FF +#define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S)) +#define SENS_I2C_SLAVE_ADDR4_V 0x7FF +#define SENS_I2C_SLAVE_ADDR4_S 11 /* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR5 0x000007FF -#define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V) << (SENS_I2C_SLAVE_ADDR5_S)) -#define SENS_I2C_SLAVE_ADDR5_V 0x7FF -#define SENS_I2C_SLAVE_ADDR5_S 0 +/*description: .*/ +#define SENS_I2C_SLAVE_ADDR5 0x000007FF +#define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S)) +#define SENS_I2C_SLAVE_ADDR5_V 0x7FF +#define SENS_I2C_SLAVE_ADDR5_S 0 -#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x004c) +#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x4C) /* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR6 0x000007FF -#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V) << (SENS_I2C_SLAVE_ADDR6_S)) -#define SENS_I2C_SLAVE_ADDR6_V 0x7FF -#define SENS_I2C_SLAVE_ADDR6_S 11 +/*description: .*/ +#define SENS_I2C_SLAVE_ADDR6 0x000007FF +#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S)) +#define SENS_I2C_SLAVE_ADDR6_V 0x7FF +#define SENS_I2C_SLAVE_ADDR6_S 11 /* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR7 0x000007FF -#define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V) << (SENS_I2C_SLAVE_ADDR7_S)) -#define SENS_I2C_SLAVE_ADDR7_V 0x7FF -#define SENS_I2C_SLAVE_ADDR7_S 0 +/*description: .*/ +#define SENS_I2C_SLAVE_ADDR7 0x000007FF +#define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S)) +#define SENS_I2C_SLAVE_ADDR7_V 0x7FF +#define SENS_I2C_SLAVE_ADDR7_S 0 -#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x0050) +#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x50) /* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: temperature sensor dump out*/ -#define SENS_TSENS_DUMP_OUT (BIT(24)) -#define SENS_TSENS_DUMP_OUT_M (BIT(24)) -#define SENS_TSENS_DUMP_OUT_V 0x1 -#define SENS_TSENS_DUMP_OUT_S 24 +/*description: temperature sensor dump out.*/ +#define SENS_TSENS_DUMP_OUT (BIT(24)) +#define SENS_TSENS_DUMP_OUT_M (BIT(24)) +#define SENS_TSENS_DUMP_OUT_V 0x1 +#define SENS_TSENS_DUMP_OUT_S 24 /* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 1: dump out & power up controlled by SW*/ -#define SENS_TSENS_POWER_UP_FORCE (BIT(23)) -#define SENS_TSENS_POWER_UP_FORCE_M (BIT(23)) -#define SENS_TSENS_POWER_UP_FORCE_V 0x1 -#define SENS_TSENS_POWER_UP_FORCE_S 23 +/*description: 1: dump out & power up controlled by SW.*/ +#define SENS_TSENS_POWER_UP_FORCE (BIT(23)) +#define SENS_TSENS_POWER_UP_FORCE_M (BIT(23)) +#define SENS_TSENS_POWER_UP_FORCE_V 0x1 +#define SENS_TSENS_POWER_UP_FORCE_S 23 /* SENS_TSENS_POWER_UP : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: temperature sensor power up*/ -#define SENS_TSENS_POWER_UP (BIT(22)) -#define SENS_TSENS_POWER_UP_M (BIT(22)) -#define SENS_TSENS_POWER_UP_V 0x1 -#define SENS_TSENS_POWER_UP_S 22 +/*description: temperature sensor power up.*/ +#define SENS_TSENS_POWER_UP (BIT(22)) +#define SENS_TSENS_POWER_UP_M (BIT(22)) +#define SENS_TSENS_POWER_UP_V 0x1 +#define SENS_TSENS_POWER_UP_S 22 /* SENS_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ -/*description: temperature sensor clock divider*/ -#define SENS_TSENS_CLK_DIV 0x000000FF -#define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V) << (SENS_TSENS_CLK_DIV_S)) -#define SENS_TSENS_CLK_DIV_V 0xFF -#define SENS_TSENS_CLK_DIV_S 14 +/*description: temperature sensor clock divider.*/ +#define SENS_TSENS_CLK_DIV 0x000000FF +#define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S)) +#define SENS_TSENS_CLK_DIV_V 0xFF +#define SENS_TSENS_CLK_DIV_S 14 /* SENS_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: invert temperature sensor data*/ -#define SENS_TSENS_IN_INV (BIT(13)) -#define SENS_TSENS_IN_INV_M (BIT(13)) -#define SENS_TSENS_IN_INV_V 0x1 -#define SENS_TSENS_IN_INV_S 13 +/*description: invert temperature sensor data.*/ +#define SENS_TSENS_IN_INV (BIT(13)) +#define SENS_TSENS_IN_INV_M (BIT(13)) +#define SENS_TSENS_IN_INV_V 0x1 +#define SENS_TSENS_IN_INV_S 13 /* SENS_TSENS_INT_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: enable temperature sensor to send out interrupt*/ -#define SENS_TSENS_INT_EN (BIT(12)) -#define SENS_TSENS_INT_EN_M (BIT(12)) -#define SENS_TSENS_INT_EN_V 0x1 -#define SENS_TSENS_INT_EN_S 12 +/*description: enable temperature sensor to send out interrupt.*/ +#define SENS_TSENS_INT_EN (BIT(12)) +#define SENS_TSENS_INT_EN_M (BIT(12)) +#define SENS_TSENS_INT_EN_V 0x1 +#define SENS_TSENS_INT_EN_S 12 /* SENS_TSENS_READY : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: indicate temperature sensor out ready*/ -#define SENS_TSENS_READY (BIT(8)) -#define SENS_TSENS_READY_M (BIT(8)) -#define SENS_TSENS_READY_V 0x1 -#define SENS_TSENS_READY_S 8 +/*description: indicate temperature sensor out ready.*/ +#define SENS_TSENS_READY (BIT(8)) +#define SENS_TSENS_READY_M (BIT(8)) +#define SENS_TSENS_READY_V 0x1 +#define SENS_TSENS_READY_S 8 /* SENS_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: temperature sensor data out*/ -#define SENS_TSENS_OUT 0x000000FF -#define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V) << (SENS_TSENS_OUT_S)) -#define SENS_TSENS_OUT_V 0xFF -#define SENS_TSENS_OUT_S 0 +/*description: temperature sensor data out.*/ +#define SENS_TSENS_OUT 0x000000FF +#define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S)) +#define SENS_TSENS_OUT_V 0xFF +#define SENS_TSENS_OUT_S 0 -#define SENS_SAR_TSENS_CTRL2_REG (DR_REG_SENS_BASE + 0x0054) +#define SENS_SAR_TSENS_CTRL2_REG (DR_REG_SENS_BASE + 0x54) /* SENS_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define SENS_TSENS_CLK_INV (BIT(14)) -#define SENS_TSENS_CLK_INV_M (BIT(14)) -#define SENS_TSENS_CLK_INV_V 0x1 -#define SENS_TSENS_CLK_INV_S 14 +/*description: .*/ +#define SENS_TSENS_CLK_INV (BIT(14)) +#define SENS_TSENS_CLK_INV_M (BIT(14)) +#define SENS_TSENS_CLK_INV_V 0x1 +#define SENS_TSENS_CLK_INV_S 14 /* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define SENS_TSENS_XPD_FORCE 0x00000003 -#define SENS_TSENS_XPD_FORCE_M ((SENS_TSENS_XPD_FORCE_V) << (SENS_TSENS_XPD_FORCE_S)) -#define SENS_TSENS_XPD_FORCE_V 0x3 -#define SENS_TSENS_XPD_FORCE_S 12 +/*description: .*/ +#define SENS_TSENS_XPD_FORCE 0x00000003 +#define SENS_TSENS_XPD_FORCE_M ((SENS_TSENS_XPD_FORCE_V)<<(SENS_TSENS_XPD_FORCE_S)) +#define SENS_TSENS_XPD_FORCE_V 0x3 +#define SENS_TSENS_XPD_FORCE_S 12 /* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ -/*description: */ -#define SENS_TSENS_XPD_WAIT 0x00000FFF -#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V) << (SENS_TSENS_XPD_WAIT_S)) -#define SENS_TSENS_XPD_WAIT_V 0xFFF -#define SENS_TSENS_XPD_WAIT_S 0 +/*description: .*/ +#define SENS_TSENS_XPD_WAIT 0x00000FFF +#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S)) +#define SENS_TSENS_XPD_WAIT_V 0xFFF +#define SENS_TSENS_XPD_WAIT_S 0 -#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x0058) +#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x58) /* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 1: I2C started by SW*/ -#define SENS_SAR_I2C_START_FORCE (BIT(29)) -#define SENS_SAR_I2C_START_FORCE_M (BIT(29)) -#define SENS_SAR_I2C_START_FORCE_V 0x1 -#define SENS_SAR_I2C_START_FORCE_S 29 +/*description: 1: I2C started by SW.*/ +#define SENS_SAR_I2C_START_FORCE (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_M (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_V 0x1 +#define SENS_SAR_I2C_START_FORCE_S 29 /* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: start I2C*/ -#define SENS_SAR_I2C_START (BIT(28)) -#define SENS_SAR_I2C_START_M (BIT(28)) -#define SENS_SAR_I2C_START_V 0x1 -#define SENS_SAR_I2C_START_S 28 +/*description: start I2C.*/ +#define SENS_SAR_I2C_START (BIT(28)) +#define SENS_SAR_I2C_START_M (BIT(28)) +#define SENS_SAR_I2C_START_V 0x1 +#define SENS_SAR_I2C_START_S 28 /* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ -/*description: I2C control data*/ -#define SENS_SAR_I2C_CTRL 0x0FFFFFFF -#define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V) << (SENS_SAR_I2C_CTRL_S)) -#define SENS_SAR_I2C_CTRL_V 0xFFFFFFF -#define SENS_SAR_I2C_CTRL_S 0 +/*description: I2C control data.*/ +#define SENS_SAR_I2C_CTRL 0x0FFFFFFF +#define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S)) +#define SENS_SAR_I2C_CTRL_V 0xFFFFFFF +#define SENS_SAR_I2C_CTRL_S 0 -#define SENS_SAR_TOUCH_CONF_REG (DR_REG_SENS_BASE + 0x005c) -/* SENS_TOUCH_APPROACH_PAD0 : R/W ;bitpos:[31:28] ;default: 4'hF ; */ -/*description: indicate which pad is approach pad0*/ -#define SENS_TOUCH_APPROACH_PAD0 0x0000000F -#define SENS_TOUCH_APPROACH_PAD0_M ((SENS_TOUCH_APPROACH_PAD0_V) << (SENS_TOUCH_APPROACH_PAD0_S)) -#define SENS_TOUCH_APPROACH_PAD0_V 0xF -#define SENS_TOUCH_APPROACH_PAD0_S 28 -/* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hF ; */ -/*description: indicate which pad is approach pad1*/ -#define SENS_TOUCH_APPROACH_PAD1 0x0000000F -#define SENS_TOUCH_APPROACH_PAD1_M ((SENS_TOUCH_APPROACH_PAD1_V) << (SENS_TOUCH_APPROACH_PAD1_S)) -#define SENS_TOUCH_APPROACH_PAD1_V 0xF -#define SENS_TOUCH_APPROACH_PAD1_S 24 -/* SENS_TOUCH_APPROACH_PAD2 : R/W ;bitpos:[23:20] ;default: 4'hF ; */ -/*description: indicate which pad is approach pad2*/ -#define SENS_TOUCH_APPROACH_PAD2 0x0000000F -#define SENS_TOUCH_APPROACH_PAD2_M ((SENS_TOUCH_APPROACH_PAD2_V) << (SENS_TOUCH_APPROACH_PAD2_S)) -#define SENS_TOUCH_APPROACH_PAD2_V 0xF -#define SENS_TOUCH_APPROACH_PAD2_S 20 +#define SENS_SAR_TOUCH_CONF_REG (DR_REG_SENS_BASE + 0x5C) +/* SENS_TOUCH_APPROACH_PAD0 : R/W ;bitpos:[31:28] ;default: 4'hf ; */ +/*description: indicate which pad is approach pad0.*/ +#define SENS_TOUCH_APPROACH_PAD0 0x0000000F +#define SENS_TOUCH_APPROACH_PAD0_M ((SENS_TOUCH_APPROACH_PAD0_V)<<(SENS_TOUCH_APPROACH_PAD0_S)) +#define SENS_TOUCH_APPROACH_PAD0_V 0xF +#define SENS_TOUCH_APPROACH_PAD0_S 28 +/* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hf ; */ +/*description: indicate which pad is approach pad1.*/ +#define SENS_TOUCH_APPROACH_PAD1 0x0000000F +#define SENS_TOUCH_APPROACH_PAD1_M ((SENS_TOUCH_APPROACH_PAD1_V)<<(SENS_TOUCH_APPROACH_PAD1_S)) +#define SENS_TOUCH_APPROACH_PAD1_V 0xF +#define SENS_TOUCH_APPROACH_PAD1_S 24 +/* SENS_TOUCH_APPROACH_PAD2 : R/W ;bitpos:[23:20] ;default: 4'hf ; */ +/*description: indicate which pad is approach pad2.*/ +#define SENS_TOUCH_APPROACH_PAD2 0x0000000F +#define SENS_TOUCH_APPROACH_PAD2_M ((SENS_TOUCH_APPROACH_PAD2_V)<<(SENS_TOUCH_APPROACH_PAD2_S)) +#define SENS_TOUCH_APPROACH_PAD2_V 0xF +#define SENS_TOUCH_APPROACH_PAD2_S 20 /* SENS_TOUCH_UNIT_END : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: touch_unit_done*/ -#define SENS_TOUCH_UNIT_END (BIT(19)) -#define SENS_TOUCH_UNIT_END_M (BIT(19)) -#define SENS_TOUCH_UNIT_END_V 0x1 -#define SENS_TOUCH_UNIT_END_S 19 +/*description: touch_unit_done.*/ +#define SENS_TOUCH_UNIT_END (BIT(19)) +#define SENS_TOUCH_UNIT_END_M (BIT(19)) +#define SENS_TOUCH_UNIT_END_V 0x1 +#define SENS_TOUCH_UNIT_END_S 19 /* SENS_TOUCH_DENOISE_END : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: touch_denoise_done*/ -#define SENS_TOUCH_DENOISE_END (BIT(18)) -#define SENS_TOUCH_DENOISE_END_M (BIT(18)) -#define SENS_TOUCH_DENOISE_END_V 0x1 -#define SENS_TOUCH_DENOISE_END_S 18 +/*description: touch_denoise_done.*/ +#define SENS_TOUCH_DENOISE_END (BIT(18)) +#define SENS_TOUCH_DENOISE_END_M (BIT(18)) +#define SENS_TOUCH_DENOISE_END_V 0x1 +#define SENS_TOUCH_DENOISE_END_S 18 /* SENS_TOUCH_DATA_SEL : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 3: smooth data 2: baseline 1 0: raw_data*/ -#define SENS_TOUCH_DATA_SEL 0x00000003 -#define SENS_TOUCH_DATA_SEL_M ((SENS_TOUCH_DATA_SEL_V) << (SENS_TOUCH_DATA_SEL_S)) -#define SENS_TOUCH_DATA_SEL_V 0x3 -#define SENS_TOUCH_DATA_SEL_S 16 +/*description: 3: smooth data 2: baseline 1,0: raw_data.*/ +#define SENS_TOUCH_DATA_SEL 0x00000003 +#define SENS_TOUCH_DATA_SEL_M ((SENS_TOUCH_DATA_SEL_V)<<(SENS_TOUCH_DATA_SEL_S)) +#define SENS_TOUCH_DATA_SEL_V 0x3 +#define SENS_TOUCH_DATA_SEL_S 16 /* SENS_TOUCH_STATUS_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: clear all touch active status*/ -#define SENS_TOUCH_STATUS_CLR (BIT(15)) -#define SENS_TOUCH_STATUS_CLR_M (BIT(15)) -#define SENS_TOUCH_STATUS_CLR_V 0x1 -#define SENS_TOUCH_STATUS_CLR_S 15 -/* SENS_TOUCH_OUTEN : R/W ;bitpos:[14:0] ;default: 15'h7FFF ; */ -/*description: touch controller output enable*/ -#define SENS_TOUCH_OUTEN 0x00007FFF -#define SENS_TOUCH_OUTEN_M ((SENS_TOUCH_OUTEN_V) << (SENS_TOUCH_OUTEN_S)) -#define SENS_TOUCH_OUTEN_V 0x7FFF -#define SENS_TOUCH_OUTEN_S 0 +/*description: clear all touch active status.*/ +#define SENS_TOUCH_STATUS_CLR (BIT(15)) +#define SENS_TOUCH_STATUS_CLR_M (BIT(15)) +#define SENS_TOUCH_STATUS_CLR_V 0x1 +#define SENS_TOUCH_STATUS_CLR_S 15 +/* SENS_TOUCH_OUTEN : R/W ;bitpos:[14:0] ;default: 15'h7fff ; */ +/*description: touch controller output enable.*/ +#define SENS_TOUCH_OUTEN 0x00007FFF +#define SENS_TOUCH_OUTEN_M ((SENS_TOUCH_OUTEN_V)<<(SENS_TOUCH_OUTEN_S)) +#define SENS_TOUCH_OUTEN_V 0x7FFF +#define SENS_TOUCH_OUTEN_S 0 -#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x0060) +#define SENS_SAR_TOUCH_DENOISE_REG (DR_REG_SENS_BASE + 0x60) +/* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: .*/ +#define SENS_TOUCH_DENOISE_DATA 0x003FFFFF +#define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V)<<(SENS_TOUCH_DENOISE_DATA_S)) +#define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF +#define SENS_TOUCH_DENOISE_DATA_S 0 + +#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x64) /* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 1*/ -#define SENS_TOUCH_OUT_TH1 0x003FFFFF -#define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V) << (SENS_TOUCH_OUT_TH1_S)) -#define SENS_TOUCH_OUT_TH1_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH1_S 0 +/*description: Finger threshold for touch pad 1.*/ +#define SENS_TOUCH_OUT_TH1 0x003FFFFF +#define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S)) +#define SENS_TOUCH_OUT_TH1_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH1_S 0 -#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x0064) +#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x68) /* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 2*/ -#define SENS_TOUCH_OUT_TH2 0x003FFFFF -#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V) << (SENS_TOUCH_OUT_TH2_S)) -#define SENS_TOUCH_OUT_TH2_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH2_S 0 +/*description: Finger threshold for touch pad 2.*/ +#define SENS_TOUCH_OUT_TH2 0x003FFFFF +#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S)) +#define SENS_TOUCH_OUT_TH2_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH2_S 0 -#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x0068) +#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x6C) /* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 3*/ -#define SENS_TOUCH_OUT_TH3 0x003FFFFF -#define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V) << (SENS_TOUCH_OUT_TH3_S)) -#define SENS_TOUCH_OUT_TH3_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH3_S 0 +/*description: Finger threshold for touch pad 3.*/ +#define SENS_TOUCH_OUT_TH3 0x003FFFFF +#define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S)) +#define SENS_TOUCH_OUT_TH3_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH3_S 0 -#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x006c) +#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x70) /* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 4*/ -#define SENS_TOUCH_OUT_TH4 0x003FFFFF -#define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V) << (SENS_TOUCH_OUT_TH4_S)) -#define SENS_TOUCH_OUT_TH4_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH4_S 0 +/*description: Finger threshold for touch pad 4.*/ +#define SENS_TOUCH_OUT_TH4 0x003FFFFF +#define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S)) +#define SENS_TOUCH_OUT_TH4_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH4_S 0 -#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x0070) +#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x74) /* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 5*/ -#define SENS_TOUCH_OUT_TH5 0x003FFFFF -#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V) << (SENS_TOUCH_OUT_TH5_S)) -#define SENS_TOUCH_OUT_TH5_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH5_S 0 +/*description: Finger threshold for touch pad 5.*/ +#define SENS_TOUCH_OUT_TH5 0x003FFFFF +#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S)) +#define SENS_TOUCH_OUT_TH5_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH5_S 0 -#define SENS_SAR_TOUCH_THRES6_REG (DR_REG_SENS_BASE + 0x0074) +#define SENS_SAR_TOUCH_THRES6_REG (DR_REG_SENS_BASE + 0x78) /* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 6*/ -#define SENS_TOUCH_OUT_TH6 0x003FFFFF -#define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V) << (SENS_TOUCH_OUT_TH6_S)) -#define SENS_TOUCH_OUT_TH6_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH6_S 0 +/*description: Finger threshold for touch pad 6.*/ +#define SENS_TOUCH_OUT_TH6 0x003FFFFF +#define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S)) +#define SENS_TOUCH_OUT_TH6_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH6_S 0 -#define SENS_SAR_TOUCH_THRES7_REG (DR_REG_SENS_BASE + 0x0078) +#define SENS_SAR_TOUCH_THRES7_REG (DR_REG_SENS_BASE + 0x7C) /* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 7*/ -#define SENS_TOUCH_OUT_TH7 0x003FFFFF -#define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V) << (SENS_TOUCH_OUT_TH7_S)) -#define SENS_TOUCH_OUT_TH7_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH7_S 0 +/*description: Finger threshold for touch pad 7.*/ +#define SENS_TOUCH_OUT_TH7 0x003FFFFF +#define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S)) +#define SENS_TOUCH_OUT_TH7_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH7_S 0 -#define SENS_SAR_TOUCH_THRES8_REG (DR_REG_SENS_BASE + 0x007c) +#define SENS_SAR_TOUCH_THRES8_REG (DR_REG_SENS_BASE + 0x80) /* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 8*/ -#define SENS_TOUCH_OUT_TH8 0x003FFFFF -#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V) << (SENS_TOUCH_OUT_TH8_S)) -#define SENS_TOUCH_OUT_TH8_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH8_S 0 +/*description: Finger threshold for touch pad 8.*/ +#define SENS_TOUCH_OUT_TH8 0x003FFFFF +#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S)) +#define SENS_TOUCH_OUT_TH8_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH8_S 0 -#define SENS_SAR_TOUCH_THRES9_REG (DR_REG_SENS_BASE + 0x0080) +#define SENS_SAR_TOUCH_THRES9_REG (DR_REG_SENS_BASE + 0x84) /* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 9*/ -#define SENS_TOUCH_OUT_TH9 0x003FFFFF -#define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V) << (SENS_TOUCH_OUT_TH9_S)) -#define SENS_TOUCH_OUT_TH9_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH9_S 0 +/*description: Finger threshold for touch pad 9.*/ +#define SENS_TOUCH_OUT_TH9 0x003FFFFF +#define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S)) +#define SENS_TOUCH_OUT_TH9_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH9_S 0 -#define SENS_SAR_TOUCH_THRES10_REG (DR_REG_SENS_BASE + 0x0084) +#define SENS_SAR_TOUCH_THRES10_REG (DR_REG_SENS_BASE + 0x88) /* SENS_TOUCH_OUT_TH10 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 10*/ -#define SENS_TOUCH_OUT_TH10 0x003FFFFF -#define SENS_TOUCH_OUT_TH10_M ((SENS_TOUCH_OUT_TH10_V) << (SENS_TOUCH_OUT_TH10_S)) -#define SENS_TOUCH_OUT_TH10_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH10_S 0 +/*description: Finger threshold for touch pad 10.*/ +#define SENS_TOUCH_OUT_TH10 0x003FFFFF +#define SENS_TOUCH_OUT_TH10_M ((SENS_TOUCH_OUT_TH10_V)<<(SENS_TOUCH_OUT_TH10_S)) +#define SENS_TOUCH_OUT_TH10_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH10_S 0 -#define SENS_SAR_TOUCH_THRES11_REG (DR_REG_SENS_BASE + 0x0088) +#define SENS_SAR_TOUCH_THRES11_REG (DR_REG_SENS_BASE + 0x8C) /* SENS_TOUCH_OUT_TH11 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 11*/ -#define SENS_TOUCH_OUT_TH11 0x003FFFFF -#define SENS_TOUCH_OUT_TH11_M ((SENS_TOUCH_OUT_TH11_V) << (SENS_TOUCH_OUT_TH11_S)) -#define SENS_TOUCH_OUT_TH11_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH11_S 0 +/*description: Finger threshold for touch pad 11.*/ +#define SENS_TOUCH_OUT_TH11 0x003FFFFF +#define SENS_TOUCH_OUT_TH11_M ((SENS_TOUCH_OUT_TH11_V)<<(SENS_TOUCH_OUT_TH11_S)) +#define SENS_TOUCH_OUT_TH11_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH11_S 0 -#define SENS_SAR_TOUCH_THRES12_REG (DR_REG_SENS_BASE + 0x008c) +#define SENS_SAR_TOUCH_THRES12_REG (DR_REG_SENS_BASE + 0x90) /* SENS_TOUCH_OUT_TH12 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 12*/ -#define SENS_TOUCH_OUT_TH12 0x003FFFFF -#define SENS_TOUCH_OUT_TH12_M ((SENS_TOUCH_OUT_TH12_V) << (SENS_TOUCH_OUT_TH12_S)) -#define SENS_TOUCH_OUT_TH12_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH12_S 0 +/*description: Finger threshold for touch pad 12.*/ +#define SENS_TOUCH_OUT_TH12 0x003FFFFF +#define SENS_TOUCH_OUT_TH12_M ((SENS_TOUCH_OUT_TH12_V)<<(SENS_TOUCH_OUT_TH12_S)) +#define SENS_TOUCH_OUT_TH12_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH12_S 0 -#define SENS_SAR_TOUCH_THRES13_REG (DR_REG_SENS_BASE + 0x0090) +#define SENS_SAR_TOUCH_THRES13_REG (DR_REG_SENS_BASE + 0x94) /* SENS_TOUCH_OUT_TH13 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 13*/ -#define SENS_TOUCH_OUT_TH13 0x003FFFFF -#define SENS_TOUCH_OUT_TH13_M ((SENS_TOUCH_OUT_TH13_V) << (SENS_TOUCH_OUT_TH13_S)) -#define SENS_TOUCH_OUT_TH13_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH13_S 0 +/*description: Finger threshold for touch pad 13.*/ +#define SENS_TOUCH_OUT_TH13 0x003FFFFF +#define SENS_TOUCH_OUT_TH13_M ((SENS_TOUCH_OUT_TH13_V)<<(SENS_TOUCH_OUT_TH13_S)) +#define SENS_TOUCH_OUT_TH13_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH13_S 0 -#define SENS_SAR_TOUCH_THRES14_REG (DR_REG_SENS_BASE + 0x0094) +#define SENS_SAR_TOUCH_THRES14_REG (DR_REG_SENS_BASE + 0x98) /* SENS_TOUCH_OUT_TH14 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 14*/ -#define SENS_TOUCH_OUT_TH14 0x003FFFFF -#define SENS_TOUCH_OUT_TH14_M ((SENS_TOUCH_OUT_TH14_V) << (SENS_TOUCH_OUT_TH14_S)) -#define SENS_TOUCH_OUT_TH14_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH14_S 0 +/*description: Finger threshold for touch pad 14.*/ +#define SENS_TOUCH_OUT_TH14 0x003FFFFF +#define SENS_TOUCH_OUT_TH14_M ((SENS_TOUCH_OUT_TH14_V)<<(SENS_TOUCH_OUT_TH14_S)) +#define SENS_TOUCH_OUT_TH14_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH14_S 0 -#define SENS_SAR_TOUCH_CHN_ST_REG (DR_REG_SENS_BASE + 0x00d4) +#define SENS_SAR_TOUCH_CHN_ST_REG (DR_REG_SENS_BASE + 0x9C) /* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SENS_TOUCH_MEAS_DONE (BIT(31)) -#define SENS_TOUCH_MEAS_DONE_M (BIT(31)) -#define SENS_TOUCH_MEAS_DONE_V 0x1 -#define SENS_TOUCH_MEAS_DONE_S 31 +/*description: .*/ +#define SENS_TOUCH_MEAS_DONE (BIT(31)) +#define SENS_TOUCH_MEAS_DONE_M (BIT(31)) +#define SENS_TOUCH_MEAS_DONE_V 0x1 +#define SENS_TOUCH_MEAS_DONE_S 31 /* SENS_TOUCH_CHANNEL_CLR : WO ;bitpos:[29:15] ;default: 15'd0 ; */ -/*description: Clear touch channel*/ -#define SENS_TOUCH_CHANNEL_CLR 0x00007FFF -#define SENS_TOUCH_CHANNEL_CLR_M ((SENS_TOUCH_CHANNEL_CLR_V) << (SENS_TOUCH_CHANNEL_CLR_S)) -#define SENS_TOUCH_CHANNEL_CLR_V 0x7FFF -#define SENS_TOUCH_CHANNEL_CLR_S 15 +/*description: Clear touch channel.*/ +#define SENS_TOUCH_CHANNEL_CLR 0x00007FFF +#define SENS_TOUCH_CHANNEL_CLR_M ((SENS_TOUCH_CHANNEL_CLR_V)<<(SENS_TOUCH_CHANNEL_CLR_S)) +#define SENS_TOUCH_CHANNEL_CLR_V 0x7FFF +#define SENS_TOUCH_CHANNEL_CLR_S 15 /* SENS_TOUCH_PAD_ACTIVE : RO ;bitpos:[14:0] ;default: 15'd0 ; */ -/*description: touch active status*/ -#define SENS_TOUCH_PAD_ACTIVE 0x00007FFF -#define SENS_TOUCH_PAD_ACTIVE_M ((SENS_TOUCH_PAD_ACTIVE_V) << (SENS_TOUCH_PAD_ACTIVE_S)) -#define SENS_TOUCH_PAD_ACTIVE_V 0x7FFF -#define SENS_TOUCH_PAD_ACTIVE_S 0 +/*description: touch active status.*/ +#define SENS_TOUCH_PAD_ACTIVE 0x00007FFF +#define SENS_TOUCH_PAD_ACTIVE_M ((SENS_TOUCH_PAD_ACTIVE_V)<<(SENS_TOUCH_PAD_ACTIVE_S)) +#define SENS_TOUCH_PAD_ACTIVE_V 0x7FFF +#define SENS_TOUCH_PAD_ACTIVE_S 0 -#define SENS_SAR_TOUCH_STATUS0_REG (DR_REG_SENS_BASE + 0x00d8) +#define SENS_SAR_TOUCH_STATUS0_REG (DR_REG_SENS_BASE + 0xA0) /* SENS_TOUCH_SCAN_CURR : RO ;bitpos:[25:22] ;default: 4'd0 ; */ -/*description: */ -#define SENS_TOUCH_SCAN_CURR 0x0000000F -#define SENS_TOUCH_SCAN_CURR_M ((SENS_TOUCH_SCAN_CURR_V) << (SENS_TOUCH_SCAN_CURR_S)) -#define SENS_TOUCH_SCAN_CURR_V 0xF -#define SENS_TOUCH_SCAN_CURR_S 22 +/*description: .*/ +#define SENS_TOUCH_SCAN_CURR 0x0000000F +#define SENS_TOUCH_SCAN_CURR_M ((SENS_TOUCH_SCAN_CURR_V)<<(SENS_TOUCH_SCAN_CURR_S)) +#define SENS_TOUCH_SCAN_CURR_V 0xF +#define SENS_TOUCH_SCAN_CURR_S 22 /* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: the counter for touch pad 0*/ -#define SENS_TOUCH_DENOISE_DATA 0x003FFFFF -#define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V) << (SENS_TOUCH_DENOISE_DATA_S)) -#define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF -#define SENS_TOUCH_DENOISE_DATA_S 0 +/*description: the counter for touch pad 0.*/ +#define SENS_TOUCH_DENOISE_DATA 0x003FFFFF +#define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V)<<(SENS_TOUCH_DENOISE_DATA_S)) +#define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF +#define SENS_TOUCH_DENOISE_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS1_REG (DR_REG_SENS_BASE + 0x00dc) +#define SENS_SAR_TOUCH_STATUS1_REG (DR_REG_SENS_BASE + 0xA4) /* SENS_TOUCH_PAD1_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD1_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD1_DEBOUNCE_M ((SENS_TOUCH_PAD1_DEBOUNCE_V) << (SENS_TOUCH_PAD1_DEBOUNCE_S)) -#define SENS_TOUCH_PAD1_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD1_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD1_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD1_DEBOUNCE_M ((SENS_TOUCH_PAD1_DEBOUNCE_V)<<(SENS_TOUCH_PAD1_DEBOUNCE_S)) +#define SENS_TOUCH_PAD1_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD1_DEBOUNCE_S 29 /* SENS_TOUCH_PAD1_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD1_DATA 0x003FFFFF -#define SENS_TOUCH_PAD1_DATA_M ((SENS_TOUCH_PAD1_DATA_V) << (SENS_TOUCH_PAD1_DATA_S)) -#define SENS_TOUCH_PAD1_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD1_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD1_DATA 0x003FFFFF +#define SENS_TOUCH_PAD1_DATA_M ((SENS_TOUCH_PAD1_DATA_V)<<(SENS_TOUCH_PAD1_DATA_S)) +#define SENS_TOUCH_PAD1_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD1_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS2_REG (DR_REG_SENS_BASE + 0x00e0) +#define SENS_SAR_TOUCH_STATUS2_REG (DR_REG_SENS_BASE + 0xA8) /* SENS_TOUCH_PAD2_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD2_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD2_DEBOUNCE_M ((SENS_TOUCH_PAD2_DEBOUNCE_V) << (SENS_TOUCH_PAD2_DEBOUNCE_S)) -#define SENS_TOUCH_PAD2_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD2_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD2_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD2_DEBOUNCE_M ((SENS_TOUCH_PAD2_DEBOUNCE_V)<<(SENS_TOUCH_PAD2_DEBOUNCE_S)) +#define SENS_TOUCH_PAD2_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD2_DEBOUNCE_S 29 /* SENS_TOUCH_PAD2_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD2_DATA 0x003FFFFF -#define SENS_TOUCH_PAD2_DATA_M ((SENS_TOUCH_PAD2_DATA_V) << (SENS_TOUCH_PAD2_DATA_S)) -#define SENS_TOUCH_PAD2_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD2_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD2_DATA 0x003FFFFF +#define SENS_TOUCH_PAD2_DATA_M ((SENS_TOUCH_PAD2_DATA_V)<<(SENS_TOUCH_PAD2_DATA_S)) +#define SENS_TOUCH_PAD2_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD2_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS3_REG (DR_REG_SENS_BASE + 0x00e4) +#define SENS_SAR_TOUCH_STATUS3_REG (DR_REG_SENS_BASE + 0xAC) /* SENS_TOUCH_PAD3_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD3_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD3_DEBOUNCE_M ((SENS_TOUCH_PAD3_DEBOUNCE_V) << (SENS_TOUCH_PAD3_DEBOUNCE_S)) -#define SENS_TOUCH_PAD3_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD3_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD3_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD3_DEBOUNCE_M ((SENS_TOUCH_PAD3_DEBOUNCE_V)<<(SENS_TOUCH_PAD3_DEBOUNCE_S)) +#define SENS_TOUCH_PAD3_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD3_DEBOUNCE_S 29 /* SENS_TOUCH_PAD3_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD3_DATA 0x003FFFFF -#define SENS_TOUCH_PAD3_DATA_M ((SENS_TOUCH_PAD3_DATA_V) << (SENS_TOUCH_PAD3_DATA_S)) -#define SENS_TOUCH_PAD3_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD3_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD3_DATA 0x003FFFFF +#define SENS_TOUCH_PAD3_DATA_M ((SENS_TOUCH_PAD3_DATA_V)<<(SENS_TOUCH_PAD3_DATA_S)) +#define SENS_TOUCH_PAD3_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD3_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS4_REG (DR_REG_SENS_BASE + 0x00e8) +#define SENS_SAR_TOUCH_STATUS4_REG (DR_REG_SENS_BASE + 0xB0) /* SENS_TOUCH_PAD4_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD4_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD4_DEBOUNCE_M ((SENS_TOUCH_PAD4_DEBOUNCE_V) << (SENS_TOUCH_PAD4_DEBOUNCE_S)) -#define SENS_TOUCH_PAD4_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD4_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD4_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD4_DEBOUNCE_M ((SENS_TOUCH_PAD4_DEBOUNCE_V)<<(SENS_TOUCH_PAD4_DEBOUNCE_S)) +#define SENS_TOUCH_PAD4_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD4_DEBOUNCE_S 29 /* SENS_TOUCH_PAD4_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD4_DATA 0x003FFFFF -#define SENS_TOUCH_PAD4_DATA_M ((SENS_TOUCH_PAD4_DATA_V) << (SENS_TOUCH_PAD4_DATA_S)) -#define SENS_TOUCH_PAD4_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD4_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD4_DATA 0x003FFFFF +#define SENS_TOUCH_PAD4_DATA_M ((SENS_TOUCH_PAD4_DATA_V)<<(SENS_TOUCH_PAD4_DATA_S)) +#define SENS_TOUCH_PAD4_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD4_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS5_REG (DR_REG_SENS_BASE + 0x00ec) +#define SENS_SAR_TOUCH_STATUS5_REG (DR_REG_SENS_BASE + 0xB4) /* SENS_TOUCH_PAD5_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD5_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD5_DEBOUNCE_M ((SENS_TOUCH_PAD5_DEBOUNCE_V) << (SENS_TOUCH_PAD5_DEBOUNCE_S)) -#define SENS_TOUCH_PAD5_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD5_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD5_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD5_DEBOUNCE_M ((SENS_TOUCH_PAD5_DEBOUNCE_V)<<(SENS_TOUCH_PAD5_DEBOUNCE_S)) +#define SENS_TOUCH_PAD5_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD5_DEBOUNCE_S 29 /* SENS_TOUCH_PAD5_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD5_DATA 0x003FFFFF -#define SENS_TOUCH_PAD5_DATA_M ((SENS_TOUCH_PAD5_DATA_V) << (SENS_TOUCH_PAD5_DATA_S)) -#define SENS_TOUCH_PAD5_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD5_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD5_DATA 0x003FFFFF +#define SENS_TOUCH_PAD5_DATA_M ((SENS_TOUCH_PAD5_DATA_V)<<(SENS_TOUCH_PAD5_DATA_S)) +#define SENS_TOUCH_PAD5_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD5_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS6_REG (DR_REG_SENS_BASE + 0x00f0) +#define SENS_SAR_TOUCH_STATUS6_REG (DR_REG_SENS_BASE + 0xB8) /* SENS_TOUCH_PAD6_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD6_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD6_DEBOUNCE_M ((SENS_TOUCH_PAD6_DEBOUNCE_V) << (SENS_TOUCH_PAD6_DEBOUNCE_S)) -#define SENS_TOUCH_PAD6_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD6_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD6_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD6_DEBOUNCE_M ((SENS_TOUCH_PAD6_DEBOUNCE_V)<<(SENS_TOUCH_PAD6_DEBOUNCE_S)) +#define SENS_TOUCH_PAD6_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD6_DEBOUNCE_S 29 /* SENS_TOUCH_PAD6_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD6_DATA 0x003FFFFF -#define SENS_TOUCH_PAD6_DATA_M ((SENS_TOUCH_PAD6_DATA_V) << (SENS_TOUCH_PAD6_DATA_S)) -#define SENS_TOUCH_PAD6_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD6_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD6_DATA 0x003FFFFF +#define SENS_TOUCH_PAD6_DATA_M ((SENS_TOUCH_PAD6_DATA_V)<<(SENS_TOUCH_PAD6_DATA_S)) +#define SENS_TOUCH_PAD6_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD6_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS7_REG (DR_REG_SENS_BASE + 0x00f4) +#define SENS_SAR_TOUCH_STATUS7_REG (DR_REG_SENS_BASE + 0xBC) /* SENS_TOUCH_PAD7_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD7_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD7_DEBOUNCE_M ((SENS_TOUCH_PAD7_DEBOUNCE_V) << (SENS_TOUCH_PAD7_DEBOUNCE_S)) -#define SENS_TOUCH_PAD7_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD7_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD7_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD7_DEBOUNCE_M ((SENS_TOUCH_PAD7_DEBOUNCE_V)<<(SENS_TOUCH_PAD7_DEBOUNCE_S)) +#define SENS_TOUCH_PAD7_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD7_DEBOUNCE_S 29 /* SENS_TOUCH_PAD7_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD7_DATA 0x003FFFFF -#define SENS_TOUCH_PAD7_DATA_M ((SENS_TOUCH_PAD7_DATA_V) << (SENS_TOUCH_PAD7_DATA_S)) -#define SENS_TOUCH_PAD7_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD7_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD7_DATA 0x003FFFFF +#define SENS_TOUCH_PAD7_DATA_M ((SENS_TOUCH_PAD7_DATA_V)<<(SENS_TOUCH_PAD7_DATA_S)) +#define SENS_TOUCH_PAD7_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD7_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS8_REG (DR_REG_SENS_BASE + 0x00f8) +#define SENS_SAR_TOUCH_STATUS8_REG (DR_REG_SENS_BASE + 0xC0) /* SENS_TOUCH_PAD8_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD8_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD8_DEBOUNCE_M ((SENS_TOUCH_PAD8_DEBOUNCE_V) << (SENS_TOUCH_PAD8_DEBOUNCE_S)) -#define SENS_TOUCH_PAD8_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD8_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD8_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD8_DEBOUNCE_M ((SENS_TOUCH_PAD8_DEBOUNCE_V)<<(SENS_TOUCH_PAD8_DEBOUNCE_S)) +#define SENS_TOUCH_PAD8_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD8_DEBOUNCE_S 29 /* SENS_TOUCH_PAD8_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD8_DATA 0x003FFFFF -#define SENS_TOUCH_PAD8_DATA_M ((SENS_TOUCH_PAD8_DATA_V) << (SENS_TOUCH_PAD8_DATA_S)) -#define SENS_TOUCH_PAD8_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD8_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD8_DATA 0x003FFFFF +#define SENS_TOUCH_PAD8_DATA_M ((SENS_TOUCH_PAD8_DATA_V)<<(SENS_TOUCH_PAD8_DATA_S)) +#define SENS_TOUCH_PAD8_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD8_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS9_REG (DR_REG_SENS_BASE + 0x00fc) +#define SENS_SAR_TOUCH_STATUS9_REG (DR_REG_SENS_BASE + 0xC4) /* SENS_TOUCH_PAD9_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD9_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD9_DEBOUNCE_M ((SENS_TOUCH_PAD9_DEBOUNCE_V) << (SENS_TOUCH_PAD9_DEBOUNCE_S)) -#define SENS_TOUCH_PAD9_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD9_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD9_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD9_DEBOUNCE_M ((SENS_TOUCH_PAD9_DEBOUNCE_V)<<(SENS_TOUCH_PAD9_DEBOUNCE_S)) +#define SENS_TOUCH_PAD9_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD9_DEBOUNCE_S 29 /* SENS_TOUCH_PAD9_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD9_DATA 0x003FFFFF -#define SENS_TOUCH_PAD9_DATA_M ((SENS_TOUCH_PAD9_DATA_V) << (SENS_TOUCH_PAD9_DATA_S)) -#define SENS_TOUCH_PAD9_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD9_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD9_DATA 0x003FFFFF +#define SENS_TOUCH_PAD9_DATA_M ((SENS_TOUCH_PAD9_DATA_V)<<(SENS_TOUCH_PAD9_DATA_S)) +#define SENS_TOUCH_PAD9_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD9_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS10_REG (DR_REG_SENS_BASE + 0x0100) +#define SENS_SAR_TOUCH_STATUS10_REG (DR_REG_SENS_BASE + 0xC8) /* SENS_TOUCH_PAD10_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD10_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD10_DEBOUNCE_M ((SENS_TOUCH_PAD10_DEBOUNCE_V) << (SENS_TOUCH_PAD10_DEBOUNCE_S)) -#define SENS_TOUCH_PAD10_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD10_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD10_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD10_DEBOUNCE_M ((SENS_TOUCH_PAD10_DEBOUNCE_V)<<(SENS_TOUCH_PAD10_DEBOUNCE_S)) +#define SENS_TOUCH_PAD10_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD10_DEBOUNCE_S 29 /* SENS_TOUCH_PAD10_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD10_DATA 0x003FFFFF -#define SENS_TOUCH_PAD10_DATA_M ((SENS_TOUCH_PAD10_DATA_V) << (SENS_TOUCH_PAD10_DATA_S)) -#define SENS_TOUCH_PAD10_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD10_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD10_DATA 0x003FFFFF +#define SENS_TOUCH_PAD10_DATA_M ((SENS_TOUCH_PAD10_DATA_V)<<(SENS_TOUCH_PAD10_DATA_S)) +#define SENS_TOUCH_PAD10_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD10_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS11_REG (DR_REG_SENS_BASE + 0x0104) +#define SENS_SAR_TOUCH_STATUS11_REG (DR_REG_SENS_BASE + 0xCC) /* SENS_TOUCH_PAD11_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD11_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD11_DEBOUNCE_M ((SENS_TOUCH_PAD11_DEBOUNCE_V) << (SENS_TOUCH_PAD11_DEBOUNCE_S)) -#define SENS_TOUCH_PAD11_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD11_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD11_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD11_DEBOUNCE_M ((SENS_TOUCH_PAD11_DEBOUNCE_V)<<(SENS_TOUCH_PAD11_DEBOUNCE_S)) +#define SENS_TOUCH_PAD11_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD11_DEBOUNCE_S 29 /* SENS_TOUCH_PAD11_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD11_DATA 0x003FFFFF -#define SENS_TOUCH_PAD11_DATA_M ((SENS_TOUCH_PAD11_DATA_V) << (SENS_TOUCH_PAD11_DATA_S)) -#define SENS_TOUCH_PAD11_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD11_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD11_DATA 0x003FFFFF +#define SENS_TOUCH_PAD11_DATA_M ((SENS_TOUCH_PAD11_DATA_V)<<(SENS_TOUCH_PAD11_DATA_S)) +#define SENS_TOUCH_PAD11_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD11_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS12_REG (DR_REG_SENS_BASE + 0x0108) +#define SENS_SAR_TOUCH_STATUS12_REG (DR_REG_SENS_BASE + 0xD0) /* SENS_TOUCH_PAD12_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD12_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD12_DEBOUNCE_M ((SENS_TOUCH_PAD12_DEBOUNCE_V) << (SENS_TOUCH_PAD12_DEBOUNCE_S)) -#define SENS_TOUCH_PAD12_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD12_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD12_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD12_DEBOUNCE_M ((SENS_TOUCH_PAD12_DEBOUNCE_V)<<(SENS_TOUCH_PAD12_DEBOUNCE_S)) +#define SENS_TOUCH_PAD12_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD12_DEBOUNCE_S 29 /* SENS_TOUCH_PAD12_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD12_DATA 0x003FFFFF -#define SENS_TOUCH_PAD12_DATA_M ((SENS_TOUCH_PAD12_DATA_V) << (SENS_TOUCH_PAD12_DATA_S)) -#define SENS_TOUCH_PAD12_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD12_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD12_DATA 0x003FFFFF +#define SENS_TOUCH_PAD12_DATA_M ((SENS_TOUCH_PAD12_DATA_V)<<(SENS_TOUCH_PAD12_DATA_S)) +#define SENS_TOUCH_PAD12_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD12_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS13_REG (DR_REG_SENS_BASE + 0x010c) +#define SENS_SAR_TOUCH_STATUS13_REG (DR_REG_SENS_BASE + 0xD4) /* SENS_TOUCH_PAD13_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD13_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD13_DEBOUNCE_M ((SENS_TOUCH_PAD13_DEBOUNCE_V) << (SENS_TOUCH_PAD13_DEBOUNCE_S)) -#define SENS_TOUCH_PAD13_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD13_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD13_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD13_DEBOUNCE_M ((SENS_TOUCH_PAD13_DEBOUNCE_V)<<(SENS_TOUCH_PAD13_DEBOUNCE_S)) +#define SENS_TOUCH_PAD13_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD13_DEBOUNCE_S 29 /* SENS_TOUCH_PAD13_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD13_DATA 0x003FFFFF -#define SENS_TOUCH_PAD13_DATA_M ((SENS_TOUCH_PAD13_DATA_V) << (SENS_TOUCH_PAD13_DATA_S)) -#define SENS_TOUCH_PAD13_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD13_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD13_DATA 0x003FFFFF +#define SENS_TOUCH_PAD13_DATA_M ((SENS_TOUCH_PAD13_DATA_V)<<(SENS_TOUCH_PAD13_DATA_S)) +#define SENS_TOUCH_PAD13_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD13_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS14_REG (DR_REG_SENS_BASE + 0x0110) +#define SENS_SAR_TOUCH_STATUS14_REG (DR_REG_SENS_BASE + 0xD8) /* SENS_TOUCH_PAD14_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD14_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD14_DEBOUNCE_M ((SENS_TOUCH_PAD14_DEBOUNCE_V) << (SENS_TOUCH_PAD14_DEBOUNCE_S)) -#define SENS_TOUCH_PAD14_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD14_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_PAD14_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD14_DEBOUNCE_M ((SENS_TOUCH_PAD14_DEBOUNCE_V)<<(SENS_TOUCH_PAD14_DEBOUNCE_S)) +#define SENS_TOUCH_PAD14_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD14_DEBOUNCE_S 29 /* SENS_TOUCH_PAD14_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD14_DATA 0x003FFFFF -#define SENS_TOUCH_PAD14_DATA_M ((SENS_TOUCH_PAD14_DATA_V) << (SENS_TOUCH_PAD14_DATA_S)) -#define SENS_TOUCH_PAD14_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD14_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_PAD14_DATA 0x003FFFFF +#define SENS_TOUCH_PAD14_DATA_M ((SENS_TOUCH_PAD14_DATA_V)<<(SENS_TOUCH_PAD14_DATA_S)) +#define SENS_TOUCH_PAD14_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD14_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS15_REG (DR_REG_SENS_BASE + 0x0114) +#define SENS_SAR_TOUCH_SLP_STATUS_REG (DR_REG_SENS_BASE + 0xDC) /* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 -#define SENS_TOUCH_SLP_DEBOUNCE_M ((SENS_TOUCH_SLP_DEBOUNCE_V) << (SENS_TOUCH_SLP_DEBOUNCE_S)) -#define SENS_TOUCH_SLP_DEBOUNCE_V 0x7 -#define SENS_TOUCH_SLP_DEBOUNCE_S 29 +/*description: .*/ +#define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 +#define SENS_TOUCH_SLP_DEBOUNCE_M ((SENS_TOUCH_SLP_DEBOUNCE_V)<<(SENS_TOUCH_SLP_DEBOUNCE_S)) +#define SENS_TOUCH_SLP_DEBOUNCE_V 0x7 +#define SENS_TOUCH_SLP_DEBOUNCE_S 29 /* SENS_TOUCH_SLP_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_SLP_DATA 0x003FFFFF -#define SENS_TOUCH_SLP_DATA_M ((SENS_TOUCH_SLP_DATA_V) << (SENS_TOUCH_SLP_DATA_S)) -#define SENS_TOUCH_SLP_DATA_V 0x3FFFFF -#define SENS_TOUCH_SLP_DATA_S 0 +/*description: .*/ +#define SENS_TOUCH_SLP_DATA 0x003FFFFF +#define SENS_TOUCH_SLP_DATA_M ((SENS_TOUCH_SLP_DATA_V)<<(SENS_TOUCH_SLP_DATA_S)) +#define SENS_TOUCH_SLP_DATA_V 0x3FFFFF +#define SENS_TOUCH_SLP_DATA_S 0 -#define SENS_SAR_TOUCH_STATUS16_REG (DR_REG_SENS_BASE + 0x0118) +#define SENS_SAR_TOUCH_APPR_STATUS_REG (DR_REG_SENS_BASE + 0xE0) /* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */ -/*description: */ -#define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF -#define SENS_TOUCH_SLP_APPROACH_CNT_M ((SENS_TOUCH_SLP_APPROACH_CNT_V) << (SENS_TOUCH_SLP_APPROACH_CNT_S)) -#define SENS_TOUCH_SLP_APPROACH_CNT_V 0xFF -#define SENS_TOUCH_SLP_APPROACH_CNT_S 24 +/*description: .*/ +#define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF +#define SENS_TOUCH_SLP_APPROACH_CNT_M ((SENS_TOUCH_SLP_APPROACH_CNT_V)<<(SENS_TOUCH_SLP_APPROACH_CNT_S)) +#define SENS_TOUCH_SLP_APPROACH_CNT_V 0xFF +#define SENS_TOUCH_SLP_APPROACH_CNT_S 24 /* SENS_TOUCH_APPROACH_PAD0_CNT : RO ;bitpos:[23:16] ;default: 8'd0 ; */ -/*description: */ -#define SENS_TOUCH_APPROACH_PAD0_CNT 0x000000FF -#define SENS_TOUCH_APPROACH_PAD0_CNT_M ((SENS_TOUCH_APPROACH_PAD0_CNT_V) << (SENS_TOUCH_APPROACH_PAD0_CNT_S)) -#define SENS_TOUCH_APPROACH_PAD0_CNT_V 0xFF -#define SENS_TOUCH_APPROACH_PAD0_CNT_S 16 +/*description: .*/ +#define SENS_TOUCH_APPROACH_PAD0_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD0_CNT_M ((SENS_TOUCH_APPROACH_PAD0_CNT_V)<<(SENS_TOUCH_APPROACH_PAD0_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD0_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD0_CNT_S 16 /* SENS_TOUCH_APPROACH_PAD1_CNT : RO ;bitpos:[15:8] ;default: 8'd0 ; */ -/*description: */ -#define SENS_TOUCH_APPROACH_PAD1_CNT 0x000000FF -#define SENS_TOUCH_APPROACH_PAD1_CNT_M ((SENS_TOUCH_APPROACH_PAD1_CNT_V) << (SENS_TOUCH_APPROACH_PAD1_CNT_S)) -#define SENS_TOUCH_APPROACH_PAD1_CNT_V 0xFF -#define SENS_TOUCH_APPROACH_PAD1_CNT_S 8 +/*description: .*/ +#define SENS_TOUCH_APPROACH_PAD1_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD1_CNT_M ((SENS_TOUCH_APPROACH_PAD1_CNT_V)<<(SENS_TOUCH_APPROACH_PAD1_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD1_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD1_CNT_S 8 /* SENS_TOUCH_APPROACH_PAD2_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */ -/*description: */ -#define SENS_TOUCH_APPROACH_PAD2_CNT 0x000000FF -#define SENS_TOUCH_APPROACH_PAD2_CNT_M ((SENS_TOUCH_APPROACH_PAD2_CNT_V) << (SENS_TOUCH_APPROACH_PAD2_CNT_S)) -#define SENS_TOUCH_APPROACH_PAD2_CNT_V 0xFF -#define SENS_TOUCH_APPROACH_PAD2_CNT_S 0 +/*description: .*/ +#define SENS_TOUCH_APPROACH_PAD2_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD2_CNT_M ((SENS_TOUCH_APPROACH_PAD2_CNT_V)<<(SENS_TOUCH_APPROACH_PAD2_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD2_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD2_CNT_S 0 -#define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x011c) -/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: 1: invert PDAC_CLK*/ -#define SENS_DAC_CLK_INV (BIT(25)) -#define SENS_DAC_CLK_INV_M (BIT(25)) -#define SENS_DAC_CLK_INV_V 0x1 -#define SENS_DAC_CLK_INV_S 25 -/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: 1: force PDAC_CLK to high*/ -#define SENS_DAC_CLK_FORCE_HIGH (BIT(24)) -#define SENS_DAC_CLK_FORCE_HIGH_M (BIT(24)) -#define SENS_DAC_CLK_FORCE_HIGH_V 0x1 -#define SENS_DAC_CLK_FORCE_HIGH_S 24 -/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 1: force PDAC_CLK to low*/ -#define SENS_DAC_CLK_FORCE_LOW (BIT(23)) -#define SENS_DAC_CLK_FORCE_LOW_M (BIT(23)) -#define SENS_DAC_CLK_FORCE_LOW_V 0x1 -#define SENS_DAC_CLK_FORCE_LOW_S 23 -/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: 1: DAC1 & DAC2 use DMA*/ -#define SENS_DAC_DIG_FORCE (BIT(22)) -#define SENS_DAC_DIG_FORCE_M (BIT(22)) -#define SENS_DAC_DIG_FORCE_V 0x1 -#define SENS_DAC_DIG_FORCE_S 22 -/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ -/*description: */ -#define SENS_DEBUG_BIT_SEL 0x0000001F -#define SENS_DEBUG_BIT_SEL_M ((SENS_DEBUG_BIT_SEL_V) << (SENS_DEBUG_BIT_SEL_S)) -#define SENS_DEBUG_BIT_SEL_V 0x1F -#define SENS_DEBUG_BIT_SEL_S 17 -/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: 1: enable CW generator*/ -#define SENS_SW_TONE_EN (BIT(16)) -#define SENS_SW_TONE_EN_M (BIT(16)) -#define SENS_SW_TONE_EN_V 0x1 -#define SENS_SW_TONE_EN_S 16 -/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: frequency step for CW generator*/ -#define SENS_SW_FSTEP 0x0000FFFF -#define SENS_SW_FSTEP_M ((SENS_SW_FSTEP_V) << (SENS_SW_FSTEP_S)) -#define SENS_SW_FSTEP_V 0xFFFF -#define SENS_SW_FSTEP_S 0 - -#define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x0120) -/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]*/ -#define SENS_DAC_CW_EN2 (BIT(25)) -#define SENS_DAC_CW_EN2_M (BIT(25)) -#define SENS_DAC_CW_EN2_V 0x1 -#define SENS_DAC_CW_EN2_S 25 -/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]*/ -#define SENS_DAC_CW_EN1 (BIT(24)) -#define SENS_DAC_CW_EN1_M (BIT(24)) -#define SENS_DAC_CW_EN1_V 0x1 -#define SENS_DAC_CW_EN1_S 24 -/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: 00: do not invert any bits*/ -#define SENS_DAC_INV2 0x00000003 -#define SENS_DAC_INV2_M ((SENS_DAC_INV2_V) << (SENS_DAC_INV2_S)) -#define SENS_DAC_INV2_V 0x3 -#define SENS_DAC_INV2_S 22 -/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ -/*description: 00: do not invert any bits*/ -#define SENS_DAC_INV1 0x00000003 -#define SENS_DAC_INV1_M ((SENS_DAC_INV1_V) << (SENS_DAC_INV1_S)) -#define SENS_DAC_INV1_V 0x3 -#define SENS_DAC_INV1_S 20 -/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: 00: no scale*/ -#define SENS_DAC_SCALE2 0x00000003 -#define SENS_DAC_SCALE2_M ((SENS_DAC_SCALE2_V) << (SENS_DAC_SCALE2_S)) -#define SENS_DAC_SCALE2_V 0x3 -#define SENS_DAC_SCALE2_S 18 -/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ -/*description: 00: no scale*/ -#define SENS_DAC_SCALE1 0x00000003 -#define SENS_DAC_SCALE1_M ((SENS_DAC_SCALE1_V) << (SENS_DAC_SCALE1_S)) -#define SENS_DAC_SCALE1_V 0x3 -#define SENS_DAC_SCALE1_S 16 -/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ -/*description: DC offset for DAC2 CW generator*/ -#define SENS_DAC_DC2 0x000000FF -#define SENS_DAC_DC2_M ((SENS_DAC_DC2_V) << (SENS_DAC_DC2_S)) -#define SENS_DAC_DC2_V 0xFF -#define SENS_DAC_DC2_S 8 -/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: DC offset for DAC1 CW generator*/ -#define SENS_DAC_DC1 0x000000FF -#define SENS_DAC_DC1_M ((SENS_DAC_DC1_V) << (SENS_DAC_DC1_S)) -#define SENS_DAC_DC1_V 0xFF -#define SENS_DAC_DC1_S 0 - -#define SENS_SAR_COCPU_STATE_REG (DR_REG_SENS_BASE + 0x0124) +#define SENS_SAR_COCPU_STATE_REG (DR_REG_SENS_BASE + 0xE4) /* SENS_COCPU_EBREAK : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: check cocpu whether in ebreak*/ -#define SENS_COCPU_EBREAK (BIT(30)) -#define SENS_COCPU_EBREAK_M (BIT(30)) -#define SENS_COCPU_EBREAK_V 0x1 -#define SENS_COCPU_EBREAK_S 30 +/*description: check cocpu whether in ebreak.*/ +#define SENS_COCPU_EBREAK (BIT(30)) +#define SENS_COCPU_EBREAK_M (BIT(30)) +#define SENS_COCPU_EBREAK_V 0x1 +#define SENS_COCPU_EBREAK_S 30 /* SENS_COCPU_TRAP : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: check cocpu whether in trap state*/ -#define SENS_COCPU_TRAP (BIT(29)) -#define SENS_COCPU_TRAP_M (BIT(29)) -#define SENS_COCPU_TRAP_V 0x1 -#define SENS_COCPU_TRAP_S 29 +/*description: check cocpu whether in trap state.*/ +#define SENS_COCPU_TRAP (BIT(29)) +#define SENS_COCPU_TRAP_M (BIT(29)) +#define SENS_COCPU_TRAP_V 0x1 +#define SENS_COCPU_TRAP_S 29 /* SENS_COCPU_EOI : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: check cocpu whether in interrupt state*/ -#define SENS_COCPU_EOI (BIT(28)) -#define SENS_COCPU_EOI_M (BIT(28)) -#define SENS_COCPU_EOI_V 0x1 -#define SENS_COCPU_EOI_S 28 +/*description: check cocpu whether in interrupt state.*/ +#define SENS_COCPU_EOI (BIT(28)) +#define SENS_COCPU_EOI_M (BIT(28)) +#define SENS_COCPU_EOI_V 0x1 +#define SENS_COCPU_EOI_S 28 /* SENS_COCPU_RESET_N : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: check cocpu whether in reset state*/ -#define SENS_COCPU_RESET_N (BIT(27)) -#define SENS_COCPU_RESET_N_M (BIT(27)) -#define SENS_COCPU_RESET_N_V 0x1 -#define SENS_COCPU_RESET_N_S 27 +/*description: check cocpu whether in reset state.*/ +#define SENS_COCPU_RESET_N (BIT(27)) +#define SENS_COCPU_RESET_N_M (BIT(27)) +#define SENS_COCPU_RESET_N_V 0x1 +#define SENS_COCPU_RESET_N_S 27 /* SENS_COCPU_CLK_EN_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: check cocpu whether clk on*/ -#define SENS_COCPU_CLK_EN_ST (BIT(26)) -#define SENS_COCPU_CLK_EN_ST_M (BIT(26)) -#define SENS_COCPU_CLK_EN_ST_V 0x1 -#define SENS_COCPU_CLK_EN_ST_S 26 +/*description: check cocpu whether clk on.*/ +#define SENS_COCPU_CLK_EN_ST (BIT(26)) +#define SENS_COCPU_CLK_EN_ST_M (BIT(26)) +#define SENS_COCPU_CLK_EN_ST_V 0x1 +#define SENS_COCPU_CLK_EN_ST_S 26 /* SENS_COCPU_DBG_TRIGGER : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: trigger cocpu debug registers*/ -#define SENS_COCPU_DBG_TRIGGER (BIT(25)) -#define SENS_COCPU_DBG_TRIGGER_M (BIT(25)) -#define SENS_COCPU_DBG_TRIGGER_V 0x1 -#define SENS_COCPU_DBG_TRIGGER_S 25 +/*description: trigger cocpu debug registers.*/ +#define SENS_COCPU_DBG_TRIGGER (BIT(25)) +#define SENS_COCPU_DBG_TRIGGER_M (BIT(25)) +#define SENS_COCPU_DBG_TRIGGER_V 0x1 +#define SENS_COCPU_DBG_TRIGGER_S 25 -#define SENS_SAR_COCPU_INT_RAW_REG (DR_REG_SENS_BASE + 0x0128) +#define SENS_SAR_COCPU_INT_RAW_REG (DR_REG_SENS_BASE + 0xE8) /* SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_S 11 +/*description: .*/ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_S 11 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 10 +/*description: .*/ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 10 /* SENS_COCPU_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_S 9 +/*description: .*/ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_S 9 /* SENS_COCPU_SWD_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: int from super watch dog*/ -#define SENS_COCPU_SWD_INT_RAW (BIT(8)) -#define SENS_COCPU_SWD_INT_RAW_M (BIT(8)) -#define SENS_COCPU_SWD_INT_RAW_V 0x1 -#define SENS_COCPU_SWD_INT_RAW_S 8 +/*description: int from super watch dog.*/ +#define SENS_COCPU_SWD_INT_RAW (BIT(8)) +#define SENS_COCPU_SWD_INT_RAW_M (BIT(8)) +#define SENS_COCPU_SWD_INT_RAW_V 0x1 +#define SENS_COCPU_SWD_INT_RAW_S 8 /* SENS_COCPU_SW_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: int from software*/ -#define SENS_COCPU_SW_INT_RAW (BIT(7)) -#define SENS_COCPU_SW_INT_RAW_M (BIT(7)) -#define SENS_COCPU_SW_INT_RAW_V 0x1 -#define SENS_COCPU_SW_INT_RAW_S 7 +/*description: int from software.*/ +#define SENS_COCPU_SW_INT_RAW (BIT(7)) +#define SENS_COCPU_SW_INT_RAW_M (BIT(7)) +#define SENS_COCPU_SW_INT_RAW_V 0x1 +#define SENS_COCPU_SW_INT_RAW_S 7 /* SENS_COCPU_START_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: int from start*/ -#define SENS_COCPU_START_INT_RAW (BIT(6)) -#define SENS_COCPU_START_INT_RAW_M (BIT(6)) -#define SENS_COCPU_START_INT_RAW_V 0x1 -#define SENS_COCPU_START_INT_RAW_S 6 +/*description: int from start.*/ +#define SENS_COCPU_START_INT_RAW (BIT(6)) +#define SENS_COCPU_START_INT_RAW_M (BIT(6)) +#define SENS_COCPU_START_INT_RAW_V 0x1 +#define SENS_COCPU_START_INT_RAW_S 6 /* SENS_COCPU_TSENS_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: int from tsens*/ -#define SENS_COCPU_TSENS_INT_RAW (BIT(5)) -#define SENS_COCPU_TSENS_INT_RAW_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_RAW_V 0x1 -#define SENS_COCPU_TSENS_INT_RAW_S 5 -/* SENS_COCPU_SENS2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: int from saradc2*/ -#define SENS_COCPU_SENS2_INT_RAW (BIT(4)) -#define SENS_COCPU_SENS2_INT_RAW_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_RAW_V 0x1 -#define SENS_COCPU_SENS2_INT_RAW_S 4 -/* SENS_COCPU_SENS1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: int from saradc1*/ -#define SENS_COCPU_SENS1_INT_RAW (BIT(3)) -#define SENS_COCPU_SENS1_INT_RAW_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_RAW_V 0x1 -#define SENS_COCPU_SENS1_INT_RAW_S 3 +/*description: int from tsens.*/ +#define SENS_COCPU_TSENS_INT_RAW (BIT(5)) +#define SENS_COCPU_TSENS_INT_RAW_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_RAW_V 0x1 +#define SENS_COCPU_TSENS_INT_RAW_S 5 +/* SENS_COCPU_SARADC2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: int from saradc2.*/ +#define SENS_COCPU_SARADC2_INT_RAW (BIT(4)) +#define SENS_COCPU_SARADC2_INT_RAW_M (BIT(4)) +#define SENS_COCPU_SARADC2_INT_RAW_V 0x1 +#define SENS_COCPU_SARADC2_INT_RAW_S 4 +/* SENS_COCPU_SARADC1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: int from saradc1.*/ +#define SENS_COCPU_SARADC1_INT_RAW (BIT(3)) +#define SENS_COCPU_SARADC1_INT_RAW_M (BIT(3)) +#define SENS_COCPU_SARADC1_INT_RAW_V 0x1 +#define SENS_COCPU_SARADC1_INT_RAW_S 3 /* SENS_COCPU_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: int from touch active*/ -#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S 2 +/*description: int from touch active.*/ +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S 2 /* SENS_COCPU_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: int from touch inactive*/ -#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S 1 +/*description: int from touch inactive.*/ +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S 1 /* SENS_COCPU_TOUCH_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: int from touch done*/ -#define SENS_COCPU_TOUCH_DONE_INT_RAW (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_RAW_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_RAW_S 0 +/*description: int from touch done.*/ +#define SENS_COCPU_TOUCH_DONE_INT_RAW (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_RAW_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_RAW_S 0 -#define SENS_SAR_COCPU_INT_ENA_REG (DR_REG_SENS_BASE + 0x012c) +#define SENS_SAR_COCPU_INT_ENA_REG (DR_REG_SENS_BASE + 0xEC) /* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_S 11 +/*description: .*/ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_S 11 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 10 +/*description: .*/ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 10 /* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_S 9 +/*description: .*/ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_S 9 /* SENS_COCPU_SWD_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_ENA (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_M (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_V 0x1 -#define SENS_COCPU_SWD_INT_ENA_S 8 +/*description: .*/ +#define SENS_COCPU_SWD_INT_ENA (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_V 0x1 +#define SENS_COCPU_SWD_INT_ENA_S 8 /* SENS_COCPU_SW_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: cocpu int enable*/ -#define SENS_COCPU_SW_INT_ENA (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_M (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_V 0x1 -#define SENS_COCPU_SW_INT_ENA_S 7 +/*description: cocpu int enable.*/ +#define SENS_COCPU_SW_INT_ENA (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_M (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_V 0x1 +#define SENS_COCPU_SW_INT_ENA_S 7 /* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ENA (BIT(6)) -#define SENS_COCPU_START_INT_ENA_M (BIT(6)) -#define SENS_COCPU_START_INT_ENA_V 0x1 -#define SENS_COCPU_START_INT_ENA_S 6 +/*description: .*/ +#define SENS_COCPU_START_INT_ENA (BIT(6)) +#define SENS_COCPU_START_INT_ENA_M (BIT(6)) +#define SENS_COCPU_START_INT_ENA_V 0x1 +#define SENS_COCPU_START_INT_ENA_S 6 /* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ENA (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_V 0x1 -#define SENS_COCPU_TSENS_INT_ENA_S 5 -/* SENS_COCPU_SENS2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_ENA (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_V 0x1 -#define SENS_COCPU_SENS2_INT_ENA_S 4 -/* SENS_COCPU_SENS1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_ENA (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_V 0x1 -#define SENS_COCPU_SENS1_INT_ENA_S 3 +/*description: .*/ +#define SENS_COCPU_TSENS_INT_ENA (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_V 0x1 +#define SENS_COCPU_TSENS_INT_ENA_S 5 +/* SENS_COCPU_SARADC2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC2_INT_ENA (BIT(4)) +#define SENS_COCPU_SARADC2_INT_ENA_M (BIT(4)) +#define SENS_COCPU_SARADC2_INT_ENA_V 0x1 +#define SENS_COCPU_SARADC2_INT_ENA_S 4 +/* SENS_COCPU_SARADC1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC1_INT_ENA (BIT(3)) +#define SENS_COCPU_SARADC1_INT_ENA_M (BIT(3)) +#define SENS_COCPU_SARADC1_INT_ENA_V 0x1 +#define SENS_COCPU_SARADC1_INT_ENA_S 3 /* SENS_COCPU_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S 2 +/*description: .*/ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S 2 /* SENS_COCPU_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S 1 +/*description: .*/ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S 1 /* SENS_COCPU_TOUCH_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_ENA (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_ENA_S 0 +/*description: .*/ +#define SENS_COCPU_TOUCH_DONE_INT_ENA (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ENA_S 0 -#define SENS_SAR_COCPU_INT_ST_REG (DR_REG_SENS_BASE + 0x0130) +#define SENS_SAR_COCPU_INT_ST_REG (DR_REG_SENS_BASE + 0xF0) /* SENS_COCPU_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_S 11 +/*description: .*/ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_S 11 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 10 +/*description: .*/ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 10 /* SENS_COCPU_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_S 9 +/*description: .*/ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_S 9 /* SENS_COCPU_SWD_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_ST (BIT(8)) -#define SENS_COCPU_SWD_INT_ST_M (BIT(8)) -#define SENS_COCPU_SWD_INT_ST_V 0x1 -#define SENS_COCPU_SWD_INT_ST_S 8 +/*description: .*/ +#define SENS_COCPU_SWD_INT_ST (BIT(8)) +#define SENS_COCPU_SWD_INT_ST_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ST_V 0x1 +#define SENS_COCPU_SWD_INT_ST_S 8 /* SENS_COCPU_SW_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: cocpu int status*/ -#define SENS_COCPU_SW_INT_ST (BIT(7)) -#define SENS_COCPU_SW_INT_ST_M (BIT(7)) -#define SENS_COCPU_SW_INT_ST_V 0x1 -#define SENS_COCPU_SW_INT_ST_S 7 +/*description: cocpu int status.*/ +#define SENS_COCPU_SW_INT_ST (BIT(7)) +#define SENS_COCPU_SW_INT_ST_M (BIT(7)) +#define SENS_COCPU_SW_INT_ST_V 0x1 +#define SENS_COCPU_SW_INT_ST_S 7 /* SENS_COCPU_START_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ST (BIT(6)) -#define SENS_COCPU_START_INT_ST_M (BIT(6)) -#define SENS_COCPU_START_INT_ST_V 0x1 -#define SENS_COCPU_START_INT_ST_S 6 +/*description: .*/ +#define SENS_COCPU_START_INT_ST (BIT(6)) +#define SENS_COCPU_START_INT_ST_M (BIT(6)) +#define SENS_COCPU_START_INT_ST_V 0x1 +#define SENS_COCPU_START_INT_ST_S 6 /* SENS_COCPU_TSENS_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ST (BIT(5)) -#define SENS_COCPU_TSENS_INT_ST_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_ST_V 0x1 -#define SENS_COCPU_TSENS_INT_ST_S 5 -/* SENS_COCPU_SENS2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_ST (BIT(4)) -#define SENS_COCPU_SENS2_INT_ST_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_ST_V 0x1 -#define SENS_COCPU_SENS2_INT_ST_S 4 -/* SENS_COCPU_SENS1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_ST (BIT(3)) -#define SENS_COCPU_SENS1_INT_ST_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_ST_V 0x1 -#define SENS_COCPU_SENS1_INT_ST_S 3 +/*description: .*/ +#define SENS_COCPU_TSENS_INT_ST (BIT(5)) +#define SENS_COCPU_TSENS_INT_ST_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ST_V 0x1 +#define SENS_COCPU_TSENS_INT_ST_S 5 +/* SENS_COCPU_SARADC2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC2_INT_ST (BIT(4)) +#define SENS_COCPU_SARADC2_INT_ST_M (BIT(4)) +#define SENS_COCPU_SARADC2_INT_ST_V 0x1 +#define SENS_COCPU_SARADC2_INT_ST_S 4 +/* SENS_COCPU_SARADC1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC1_INT_ST (BIT(3)) +#define SENS_COCPU_SARADC1_INT_ST_M (BIT(3)) +#define SENS_COCPU_SARADC1_INT_ST_V 0x1 +#define SENS_COCPU_SARADC1_INT_ST_S 3 /* SENS_COCPU_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_ST (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_S 2 +/*description: .*/ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_S 2 /* SENS_COCPU_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_ST (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S 1 +/*description: .*/ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S 1 /* SENS_COCPU_TOUCH_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_ST (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ST_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_ST_S 0 +/*description: .*/ +#define SENS_COCPU_TOUCH_DONE_INT_ST (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ST_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ST_S 0 -#define SENS_SAR_COCPU_INT_CLR_REG (DR_REG_SENS_BASE + 0x0134) +#define SENS_SAR_COCPU_INT_CLR_REG (DR_REG_SENS_BASE + 0xF4) /* SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_S 11 +/*description: .*/ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_S 11 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 10 +/*description: .*/ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 10 /* SENS_COCPU_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_S 9 +/*description: .*/ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_S 9 /* SENS_COCPU_SWD_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_CLR (BIT(8)) -#define SENS_COCPU_SWD_INT_CLR_M (BIT(8)) -#define SENS_COCPU_SWD_INT_CLR_V 0x1 -#define SENS_COCPU_SWD_INT_CLR_S 8 +/*description: .*/ +#define SENS_COCPU_SWD_INT_CLR (BIT(8)) +#define SENS_COCPU_SWD_INT_CLR_M (BIT(8)) +#define SENS_COCPU_SWD_INT_CLR_V 0x1 +#define SENS_COCPU_SWD_INT_CLR_S 8 /* SENS_COCPU_SW_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: cocpu int clear*/ -#define SENS_COCPU_SW_INT_CLR (BIT(7)) -#define SENS_COCPU_SW_INT_CLR_M (BIT(7)) -#define SENS_COCPU_SW_INT_CLR_V 0x1 -#define SENS_COCPU_SW_INT_CLR_S 7 +/*description: cocpu int clear.*/ +#define SENS_COCPU_SW_INT_CLR (BIT(7)) +#define SENS_COCPU_SW_INT_CLR_M (BIT(7)) +#define SENS_COCPU_SW_INT_CLR_V 0x1 +#define SENS_COCPU_SW_INT_CLR_S 7 /* SENS_COCPU_START_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_CLR (BIT(6)) -#define SENS_COCPU_START_INT_CLR_M (BIT(6)) -#define SENS_COCPU_START_INT_CLR_V 0x1 -#define SENS_COCPU_START_INT_CLR_S 6 +/*description: .*/ +#define SENS_COCPU_START_INT_CLR (BIT(6)) +#define SENS_COCPU_START_INT_CLR_M (BIT(6)) +#define SENS_COCPU_START_INT_CLR_V 0x1 +#define SENS_COCPU_START_INT_CLR_S 6 /* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_CLR (BIT(5)) -#define SENS_COCPU_TSENS_INT_CLR_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_CLR_V 0x1 -#define SENS_COCPU_TSENS_INT_CLR_S 5 -/* SENS_COCPU_SENS2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_CLR (BIT(4)) -#define SENS_COCPU_SENS2_INT_CLR_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_CLR_V 0x1 -#define SENS_COCPU_SENS2_INT_CLR_S 4 -/* SENS_COCPU_SENS1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_CLR (BIT(3)) -#define SENS_COCPU_SENS1_INT_CLR_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_CLR_V 0x1 -#define SENS_COCPU_SENS1_INT_CLR_S 3 +/*description: .*/ +#define SENS_COCPU_TSENS_INT_CLR (BIT(5)) +#define SENS_COCPU_TSENS_INT_CLR_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_CLR_V 0x1 +#define SENS_COCPU_TSENS_INT_CLR_S 5 +/* SENS_COCPU_SARADC2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC2_INT_CLR (BIT(4)) +#define SENS_COCPU_SARADC2_INT_CLR_M (BIT(4)) +#define SENS_COCPU_SARADC2_INT_CLR_V 0x1 +#define SENS_COCPU_SARADC2_INT_CLR_S 4 +/* SENS_COCPU_SARADC1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC1_INT_CLR (BIT(3)) +#define SENS_COCPU_SARADC1_INT_CLR_M (BIT(3)) +#define SENS_COCPU_SARADC1_INT_CLR_V 0x1 +#define SENS_COCPU_SARADC1_INT_CLR_S 3 /* SENS_COCPU_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S 2 +/*description: .*/ +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S 2 /* SENS_COCPU_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S 1 +/*description: .*/ +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S 1 /* SENS_COCPU_TOUCH_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_CLR (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_CLR_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_CLR_S 0 +/*description: .*/ +#define SENS_COCPU_TOUCH_DONE_INT_CLR (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_CLR_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_CLR_S 0 -#define SENS_SAR_COCPU_DEBUG_REG (DR_REG_SENS_BASE + 0x0138) +#define SENS_SAR_COCPU_DEBUG_REG (DR_REG_SENS_BASE + 0xF8) /* SENS_COCPU_MEM_ADDR : RO ;bitpos:[31:19] ;default: 13'd0 ; */ -/*description: cocpu mem address output*/ -#define SENS_COCPU_MEM_ADDR 0x00001FFF -#define SENS_COCPU_MEM_ADDR_M ((SENS_COCPU_MEM_ADDR_V) << (SENS_COCPU_MEM_ADDR_S)) -#define SENS_COCPU_MEM_ADDR_V 0x1FFF -#define SENS_COCPU_MEM_ADDR_S 19 +/*description: cocpu mem address output.*/ +#define SENS_COCPU_MEM_ADDR 0x00001FFF +#define SENS_COCPU_MEM_ADDR_M ((SENS_COCPU_MEM_ADDR_V)<<(SENS_COCPU_MEM_ADDR_S)) +#define SENS_COCPU_MEM_ADDR_V 0x1FFF +#define SENS_COCPU_MEM_ADDR_S 19 /* SENS_COCPU_MEM_WEN : RO ;bitpos:[18:15] ;default: 4'd0 ; */ -/*description: cocpu mem write enable output*/ -#define SENS_COCPU_MEM_WEN 0x0000000F -#define SENS_COCPU_MEM_WEN_M ((SENS_COCPU_MEM_WEN_V) << (SENS_COCPU_MEM_WEN_S)) -#define SENS_COCPU_MEM_WEN_V 0xF -#define SENS_COCPU_MEM_WEN_S 15 +/*description: cocpu mem write enable output.*/ +#define SENS_COCPU_MEM_WEN 0x0000000F +#define SENS_COCPU_MEM_WEN_M ((SENS_COCPU_MEM_WEN_V)<<(SENS_COCPU_MEM_WEN_S)) +#define SENS_COCPU_MEM_WEN_V 0xF +#define SENS_COCPU_MEM_WEN_S 15 /* SENS_COCPU_MEM_RDY : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: cocpu mem ready input*/ -#define SENS_COCPU_MEM_RDY (BIT(14)) -#define SENS_COCPU_MEM_RDY_M (BIT(14)) -#define SENS_COCPU_MEM_RDY_V 0x1 -#define SENS_COCPU_MEM_RDY_S 14 +/*description: cocpu mem ready input.*/ +#define SENS_COCPU_MEM_RDY (BIT(14)) +#define SENS_COCPU_MEM_RDY_M (BIT(14)) +#define SENS_COCPU_MEM_RDY_V 0x1 +#define SENS_COCPU_MEM_RDY_S 14 /* SENS_COCPU_MEM_VLD : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: cocpu mem valid output*/ -#define SENS_COCPU_MEM_VLD (BIT(13)) -#define SENS_COCPU_MEM_VLD_M (BIT(13)) -#define SENS_COCPU_MEM_VLD_V 0x1 -#define SENS_COCPU_MEM_VLD_S 13 +/*description: cocpu mem valid output.*/ +#define SENS_COCPU_MEM_VLD (BIT(13)) +#define SENS_COCPU_MEM_VLD_M (BIT(13)) +#define SENS_COCPU_MEM_VLD_V 0x1 +#define SENS_COCPU_MEM_VLD_S 13 /* SENS_COCPU_PC : RO ;bitpos:[12:0] ;default: 13'd0 ; */ -/*description: cocpu Program counter*/ -#define SENS_COCPU_PC 0x00001FFF -#define SENS_COCPU_PC_M ((SENS_COCPU_PC_V) << (SENS_COCPU_PC_S)) -#define SENS_COCPU_PC_V 0x1FFF -#define SENS_COCPU_PC_S 0 +/*description: cocpu Program counter.*/ +#define SENS_COCPU_PC 0x00001FFF +#define SENS_COCPU_PC_M ((SENS_COCPU_PC_V)<<(SENS_COCPU_PC_S)) +#define SENS_COCPU_PC_V 0x1FFF +#define SENS_COCPU_PC_S 0 -#define SENS_SAR_HALL_CTRL_REG (DR_REG_SENS_BASE + 0x013c) +#define SENS_SAR_HALL_CTRL_REG (DR_REG_SENS_BASE + 0xFC) /* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled - by FSM in ULP-coprocessor*/ -#define SENS_HALL_PHASE_FORCE (BIT(31)) -#define SENS_HALL_PHASE_FORCE_M (BIT(31)) -#define SENS_HALL_PHASE_FORCE_V 0x1 -#define SENS_HALL_PHASE_FORCE_S 31 +/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-cop +rocessor.*/ +#define SENS_HALL_PHASE_FORCE (BIT(31)) +#define SENS_HALL_PHASE_FORCE_M (BIT(31)) +#define SENS_HALL_PHASE_FORCE_V 0x1 +#define SENS_HALL_PHASE_FORCE_S 31 /* SENS_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Reverse phase of hall sensor*/ -#define SENS_HALL_PHASE (BIT(30)) -#define SENS_HALL_PHASE_M (BIT(30)) -#define SENS_HALL_PHASE_V 0x1 -#define SENS_HALL_PHASE_S 30 +/*description: Reverse phase of hall sensor.*/ +#define SENS_HALL_PHASE (BIT(30)) +#define SENS_HALL_PHASE_M (BIT(30)) +#define SENS_HALL_PHASE_V 0x1 +#define SENS_HALL_PHASE_S 30 /* SENS_XPD_HALL_FORCE : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by - FSM in ULP-coprocessor*/ -#define SENS_XPD_HALL_FORCE (BIT(29)) -#define SENS_XPD_HALL_FORCE_M (BIT(29)) -#define SENS_XPD_HALL_FORCE_V 0x1 -#define SENS_XPD_HALL_FORCE_S 29 +/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coproce +ssor.*/ +#define SENS_XPD_HALL_FORCE (BIT(29)) +#define SENS_XPD_HALL_FORCE_M (BIT(29)) +#define SENS_XPD_HALL_FORCE_V 0x1 +#define SENS_XPD_HALL_FORCE_S 29 /* SENS_XPD_HALL : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Power on hall sensor and connect to VP and VN*/ -#define SENS_XPD_HALL (BIT(28)) -#define SENS_XPD_HALL_M (BIT(28)) -#define SENS_XPD_HALL_V 0x1 -#define SENS_XPD_HALL_S 28 +/*description: Power on hall sensor and connect to VP and VN.*/ +#define SENS_XPD_HALL (BIT(28)) +#define SENS_XPD_HALL_M (BIT(28)) +#define SENS_XPD_HALL_V 0x1 +#define SENS_XPD_HALL_S 28 -#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x0140) +#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x100) /* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SENS_SAR_NOUSE 0xFFFFFFFF -#define SENS_SAR_NOUSE_M ((SENS_SAR_NOUSE_V) << (SENS_SAR_NOUSE_S)) -#define SENS_SAR_NOUSE_V 0xFFFFFFFF -#define SENS_SAR_NOUSE_S 0 +/*description: .*/ +#define SENS_SAR_NOUSE 0xFFFFFFFF +#define SENS_SAR_NOUSE_M ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S)) +#define SENS_SAR_NOUSE_V 0xFFFFFFFF +#define SENS_SAR_NOUSE_S 0 -#define SENS_SAR_PERI_CLK_GATE_CONF_REG (DR_REG_SENS_BASE + 0x0144) +#define SENS_SAR_PERI_CLK_GATE_CONF_REG (DR_REG_SENS_BASE + 0x104) /* SENS_IOMUX_CLK_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define SENS_IOMUX_CLK_EN (BIT(31)) -#define SENS_IOMUX_CLK_EN_M (BIT(31)) -#define SENS_IOMUX_CLK_EN_V 0x1 -#define SENS_IOMUX_CLK_EN_S 31 -/* SENS_CLK_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SENS_CLK_EN (BIT(30)) -#define SENS_CLK_EN_M (BIT(30)) -#define SENS_CLK_EN_V 0x1 -#define SENS_CLK_EN_S 30 +/*description: .*/ +#define SENS_IOMUX_CLK_EN (BIT(31)) +#define SENS_IOMUX_CLK_EN_M (BIT(31)) +#define SENS_IOMUX_CLK_EN_V 0x1 +#define SENS_IOMUX_CLK_EN_S 31 +/* SENS_SARADC_CLK_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_SARADC_CLK_EN (BIT(30)) +#define SENS_SARADC_CLK_EN_M (BIT(30)) +#define SENS_SARADC_CLK_EN_V 0x1 +#define SENS_SARADC_CLK_EN_S 30 /* SENS_TSENS_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SENS_TSENS_CLK_EN (BIT(29)) -#define SENS_TSENS_CLK_EN_M (BIT(29)) -#define SENS_TSENS_CLK_EN_V 0x1 -#define SENS_TSENS_CLK_EN_S 29 +/*description: .*/ +#define SENS_TSENS_CLK_EN (BIT(29)) +#define SENS_TSENS_CLK_EN_M (BIT(29)) +#define SENS_TSENS_CLK_EN_V 0x1 +#define SENS_TSENS_CLK_EN_S 29 /* SENS_RTC_I2C_CLK_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SENS_RTC_I2C_CLK_EN (BIT(27)) -#define SENS_RTC_I2C_CLK_EN_M (BIT(27)) -#define SENS_RTC_I2C_CLK_EN_V 0x1 -#define SENS_RTC_I2C_CLK_EN_S 27 -/* SENS_DAC_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SENS_DAC_CLK_EN (BIT(26)) -#define SENS_DAC_CLK_EN_M (BIT(26)) -#define SENS_DAC_CLK_EN_V 0x1 -#define SENS_DAC_CLK_EN_S 26 +/*description: .*/ +#define SENS_RTC_I2C_CLK_EN (BIT(27)) +#define SENS_RTC_I2C_CLK_EN_M (BIT(27)) +#define SENS_RTC_I2C_CLK_EN_V 0x1 +#define SENS_RTC_I2C_CLK_EN_S 27 -#define SENS_SAR_PERI_RESET_CONF_REG (DR_REG_SENS_BASE + 0x0148) -/* SENS_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SENS_RESET (BIT(30)) -#define SENS_RESET_M (BIT(30)) -#define SENS_RESET_V 0x1 -#define SENS_RESET_S 30 +#define SENS_SAR_PERI_RESET_CONF_REG (DR_REG_SENS_BASE + 0x108) +/* SENS_SARADC_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_SARADC_RESET (BIT(30)) +#define SENS_SARADC_RESET_M (BIT(30)) +#define SENS_SARADC_RESET_V 0x1 +#define SENS_SARADC_RESET_S 30 /* SENS_TSENS_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SENS_TSENS_RESET (BIT(29)) -#define SENS_TSENS_RESET_M (BIT(29)) -#define SENS_TSENS_RESET_V 0x1 -#define SENS_TSENS_RESET_S 29 +/*description: .*/ +#define SENS_TSENS_RESET (BIT(29)) +#define SENS_TSENS_RESET_M (BIT(29)) +#define SENS_TSENS_RESET_V 0x1 +#define SENS_TSENS_RESET_S 29 /* SENS_RTC_I2C_RESET : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SENS_RTC_I2C_RESET (BIT(27)) -#define SENS_RTC_I2C_RESET_M (BIT(27)) -#define SENS_RTC_I2C_RESET_V 0x1 -#define SENS_RTC_I2C_RESET_S 27 -/* SENS_DAC_RESET : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SENS_DAC_RESET (BIT(26)) -#define SENS_DAC_RESET_M (BIT(26)) -#define SENS_DAC_RESET_V 0x1 -#define SENS_DAC_RESET_S 26 +/*description: .*/ +#define SENS_RTC_I2C_RESET (BIT(27)) +#define SENS_RTC_I2C_RESET_M (BIT(27)) +#define SENS_RTC_I2C_RESET_V 0x1 +#define SENS_RTC_I2C_RESET_S 27 /* SENS_COCPU_RESET : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_RESET (BIT(25)) -#define SENS_COCPU_RESET_M (BIT(25)) -#define SENS_COCPU_RESET_V 0x1 -#define SENS_COCPU_RESET_S 25 +/*description: .*/ +#define SENS_COCPU_RESET (BIT(25)) +#define SENS_COCPU_RESET_M (BIT(25)) +#define SENS_COCPU_RESET_V 0x1 +#define SENS_COCPU_RESET_S 25 -#define SENS_SAR_COCPU_INT_ENA_W1TS_REG (DR_REG_SENS_BASE + 0x014c) +#define SENS_SAR_COCPU_INT_ENA_W1TS_REG (DR_REG_SENS_BASE + 0x10C) /* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 11 +/*description: .*/ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 11 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 10 +/*description: .*/ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 10 /* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_S 9 +/*description: .*/ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_S 9 /* SENS_COCPU_SWD_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_ENA_W1TS (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_W1TS_M (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_SWD_INT_ENA_W1TS_S 8 +/*description: .*/ +#define SENS_COCPU_SWD_INT_ENA_W1TS (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_W1TS_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_SWD_INT_ENA_W1TS_S 8 /* SENS_COCPU_SW_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SW_INT_ENA_W1TS (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_W1TS_M (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_SW_INT_ENA_W1TS_S 7 +/*description: .*/ +#define SENS_COCPU_SW_INT_ENA_W1TS (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_W1TS_M (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_SW_INT_ENA_W1TS_S 7 /* SENS_COCPU_START_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ENA_W1TS (BIT(6)) -#define SENS_COCPU_START_INT_ENA_W1TS_M (BIT(6)) -#define SENS_COCPU_START_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_START_INT_ENA_W1TS_S 6 +/*description: .*/ +#define SENS_COCPU_START_INT_ENA_W1TS (BIT(6)) +#define SENS_COCPU_START_INT_ENA_W1TS_M (BIT(6)) +#define SENS_COCPU_START_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_START_INT_ENA_W1TS_S 6 /* SENS_COCPU_TSENS_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ENA_W1TS (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_W1TS_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TSENS_INT_ENA_W1TS_S 5 -/* SENS_COCPU_SENS2_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_ENA_W1TS (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_W1TS_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_SENS2_INT_ENA_W1TS_S 4 -/* SENS_COCPU_SENS1_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_ENA_W1TS (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_W1TS_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_SENS1_INT_ENA_W1TS_S 3 +/*description: .*/ +#define SENS_COCPU_TSENS_INT_ENA_W1TS (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_W1TS_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TSENS_INT_ENA_W1TS_S 5 +/* SENS_COCPU_SARADC2_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC2_INT_ENA_W1TS (BIT(4)) +#define SENS_COCPU_SARADC2_INT_ENA_W1TS_M (BIT(4)) +#define SENS_COCPU_SARADC2_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_SARADC2_INT_ENA_W1TS_S 4 +/* SENS_COCPU_SARADC1_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC1_INT_ENA_W1TS (BIT(3)) +#define SENS_COCPU_SARADC1_INT_ENA_W1TS_M (BIT(3)) +#define SENS_COCPU_SARADC1_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_SARADC1_INT_ENA_W1TS_S 3 /* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_S 2 +/*description: .*/ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_S 2 /* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_S 1 +/*description: .*/ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_S 1 /* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_S 0 +/*description: .*/ +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_S 0 -#define SENS_SAR_COCPU_INT_ENA_W1TC_REG (DR_REG_SENS_BASE + 0x0150) +#define SENS_SAR_COCPU_INT_ENA_W1TC_REG (DR_REG_SENS_BASE + 0x110) /* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 11 +/*description: .*/ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 11 /* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 10 +/*description: .*/ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 10 /* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_S 9 +/*description: .*/ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_S 9 /* SENS_COCPU_SWD_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_ENA_W1TC (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_W1TC_M (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_SWD_INT_ENA_W1TC_S 8 +/*description: .*/ +#define SENS_COCPU_SWD_INT_ENA_W1TC (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_W1TC_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_SWD_INT_ENA_W1TC_S 8 /* SENS_COCPU_SW_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SW_INT_ENA_W1TC (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_W1TC_M (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_SW_INT_ENA_W1TC_S 7 +/*description: .*/ +#define SENS_COCPU_SW_INT_ENA_W1TC (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_W1TC_M (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_SW_INT_ENA_W1TC_S 7 /* SENS_COCPU_START_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ENA_W1TC (BIT(6)) -#define SENS_COCPU_START_INT_ENA_W1TC_M (BIT(6)) -#define SENS_COCPU_START_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_START_INT_ENA_W1TC_S 6 +/*description: .*/ +#define SENS_COCPU_START_INT_ENA_W1TC (BIT(6)) +#define SENS_COCPU_START_INT_ENA_W1TC_M (BIT(6)) +#define SENS_COCPU_START_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_START_INT_ENA_W1TC_S 6 /* SENS_COCPU_TSENS_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ENA_W1TC (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_W1TC_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TSENS_INT_ENA_W1TC_S 5 -/* SENS_COCPU_SENS2_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_ENA_W1TC (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_W1TC_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_SENS2_INT_ENA_W1TC_S 4 -/* SENS_COCPU_SENS1_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_ENA_W1TC (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_W1TC_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_SENS1_INT_ENA_W1TC_S 3 +/*description: .*/ +#define SENS_COCPU_TSENS_INT_ENA_W1TC (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_W1TC_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TSENS_INT_ENA_W1TC_S 5 +/* SENS_COCPU_SARADC2_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC2_INT_ENA_W1TC (BIT(4)) +#define SENS_COCPU_SARADC2_INT_ENA_W1TC_M (BIT(4)) +#define SENS_COCPU_SARADC2_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_SARADC2_INT_ENA_W1TC_S 4 +/* SENS_COCPU_SARADC1_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define SENS_COCPU_SARADC1_INT_ENA_W1TC (BIT(3)) +#define SENS_COCPU_SARADC1_INT_ENA_W1TC_M (BIT(3)) +#define SENS_COCPU_SARADC1_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_SARADC1_INT_ENA_W1TC_S 3 /* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_S 2 +/*description: .*/ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_S 2 /* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_S 1 +/*description: .*/ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_S 1 /* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_S 0 +/*description: .*/ +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_S 0 + +#define SENS_SAR_DEBUG_CONF_REG (DR_REG_SENS_BASE + 0x114) +/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: .*/ +#define SENS_DEBUG_BIT_SEL 0x0000001F +#define SENS_DEBUG_BIT_SEL_M ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S)) +#define SENS_DEBUG_BIT_SEL_V 0x1F +#define SENS_DEBUG_BIT_SEL_S 0 + +#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x1FC) +/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */ +/*description: .*/ +#define SENS_SAR_DATE 0x0FFFFFFF +#define SENS_SAR_DATE_M ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S)) +#define SENS_SAR_DATE_V 0xFFFFFFF +#define SENS_SAR_DATE_S 0 -#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x0154) -/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1909160 ; */ -/*description: */ -#define SENS_SAR_DATE 0x0FFFFFFF -#define SENS_SAR_DATE_M ((SENS_SAR_DATE_V) << (SENS_SAR_DATE_S)) -#define SENS_SAR_DATE_V 0xFFFFFFF -#define SENS_SAR_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SENS_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/sens_struct.h b/components/soc/esp32s3/include/soc/sens_struct.h index 98f3680c22..1c2fdcbf39 100644 --- a/components/soc/esp32s3/include/soc/sens_struct.h +++ b/components/soc/esp32s3/include/soc/sens_struct.h @@ -11,13 +11,14 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SENS_STRUCT_H_ +#define _SOC_SENS_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { union { @@ -234,26 +235,18 @@ typedef volatile struct { } sar_touch_conf; union { struct { - uint32_t thresh: 22; /*Finger threshold for touch pad 1*/ - uint32_t reserved22: 10; + uint32_t touch_denoise_data : 22; + uint32_t reserved22 : 10; + }; + uint32_t val; + } sar_touch_denoise; + union { + struct { + uint32_t thresh : 22; /*Finger threshold for touch pad 1*/ + uint32_t reserved22 : 10; }; uint32_t val; } touch_thresh[14]; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; union { struct { uint32_t touch_pad_active: 15; /*touch active status*/ @@ -431,13 +424,12 @@ typedef volatile struct { uint32_t sar_nouse; /**/ union { struct { - uint32_t reserved0: 26; - uint32_t dac_clk_en: 1; - uint32_t rtc_i2c_clk_en: 1; - uint32_t reserved28: 1; - uint32_t tsens_clk_en: 1; - uint32_t saradc_clk_en: 1; - uint32_t iomux_clk_en: 1; + uint32_t reserved0 : 27; + uint32_t rtc_i2c_clk_en : 1; + uint32_t reserved28 : 1; + uint32_t tsens_clk_en : 1; + uint32_t saradc_clk_en : 1; + uint32_t iomux_clk_en : 1; }; uint32_t val; } sar_peri_clk_gate_conf; @@ -445,7 +437,7 @@ typedef volatile struct { struct { uint32_t reserved0: 25; uint32_t reset: 1; - uint32_t dac_reset: 1; + uint32_t reserved26 : 1; uint32_t rtc_i2c_reset: 1; uint32_t reserved28: 1; uint32_t tsens_reset: 1; @@ -492,15 +484,81 @@ typedef volatile struct { } sar_cocpu_int_ena_w1tc; union { struct { - uint32_t sar_date: 28; - uint32_t reserved28: 4; + uint32_t debug_bit_sel : 5; + uint32_t reserved5 : 27; + }; + uint32_t val; + } sar_debug_conf; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + union { + struct { + uint32_t sar_date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } sardate; } sens_dev_t; - extern sens_dev_t SENS; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SENS_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/sensitive_reg.h b/components/soc/esp32s3/include/soc/sensitive_reg.h index 0c3ed14969..e0dffd6ce1 100644 --- a/components/soc/esp32s3/include/soc/sensitive_reg.h +++ b/components/soc/esp32s3/include/soc/sensitive_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,4126 +11,4746 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SENSITIVE_REG_H_ +#define _SOC_SENSITIVE_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG (DR_REG_SENSITIVE_BASE + 0x000) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG (DR_REG_SENSITIVE_BASE + 0x0) /* SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK (BIT(0)) -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_M (BIT(0)) -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V 0x1 -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK (BIT(0)) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V 0x1 +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S 0 -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG (DR_REG_SENSITIVE_BASE + 0x004) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG (DR_REG_SENSITIVE_BASE + 0x4) /* SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN : R/W ;bitpos:[7:0] ;default: ~8'b0 ; */ -/*description: */ -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN 0x000000FF -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_M ((SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V) << (SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S)) -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V 0xFF -#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S 0 +/*description: .*/ +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN 0x000000FF +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_M ((SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V)<<(SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S)) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V 0xFF +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S 0 -#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x008) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8) /* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1 -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 -#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x00C) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xC) /* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1 -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 +/*description: .*/ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 -#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x010) +#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10) /* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1 -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 -#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x014) -/* SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0 : R/W ;bitpos:[10:0] ;default: ~11'h0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0 0x000007FF -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_M ((SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_V) << (SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_S)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_V 0x7FF -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_S 0 +#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14) +/* SENSITIVE_INTERNAL_SRAM_CPU_USAGE : R/W ;bitpos:[10:4] ;default: ~7'h0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE 0x0000007F +#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_M ((SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S)) +#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V 0x7F +#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S 4 +/* SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE : R/W ;bitpos:[3:2] ;default: ~2'h0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_M ((SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S)) +#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V 0x3 +#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S 2 +/* SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE : R/W ;bitpos:[1:0] ;default: ~2'h0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_M ((SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S)) +#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V 0x3 +#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S 0 -#define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG (DR_REG_SENSITIVE_BASE + 0x018) -/* SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1 : R/W ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1 0x0003FFFF -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_M ((SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_V) << (SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_S)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_V 0x3FFFF -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_S 0 +#define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG (DR_REG_SENSITIVE_BASE + 0x18) +/* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_M ((SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V)<<(SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S)) +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V 0x3 +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S 16 +/* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_M ((SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V)<<(SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S)) +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V 0x3 +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S 14 +/* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE : R/W ;bitpos:[13:7] ;default: 7'b0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE 0x0000007F +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_M ((SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S)) +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V 0x7F +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S 7 +/* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE 0x0000007F +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_M ((SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S)) +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V 0x7F +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S 0 -#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x01C) -/* SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2 0x0000000F -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_M ((SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_V) << (SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_S)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_V 0xF -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_S 0 +#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x1C) +/* SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE 0x0000000F +#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_M ((SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S)) +#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V 0xF +#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S 0 -#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x020) -/* SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3 : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3 0x0000007F -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_M ((SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_V) << (SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_S)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_V 0x7F -#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_S 0 +#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x20) +/* SENSITIVE_INTERNAL_SRAM_LOG_USAGE : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ +/*description: .*/ +#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE 0x0000007F +#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_M ((SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S)) +#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V 0x7F +#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S 0 -#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x024) +#define SENSITIVE_RETENTION_DISABLE_REG (DR_REG_SENSITIVE_BASE + 0x24) +/* SENSITIVE_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_RETENTION_DISABLE (BIT(0)) +#define SENSITIVE_RETENTION_DISABLE_M (BIT(0)) +#define SENSITIVE_RETENTION_DISABLE_V 0x1 +#define SENSITIVE_RETENTION_DISABLE_S 0 + +#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x28) /* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1 -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 -#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x028) +#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x2C) /* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) -#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3)) -#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1 -#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 +/*description: .*/ +#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1 +#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 /* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) -#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2)) -#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1 -#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 +/*description: .*/ +#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 /* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) -#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1)) -#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1 -#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 +/*description: .*/ +#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 /* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) -#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0)) -#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1 -#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 +/*description: .*/ +#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 -#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x02C) +#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x30) /* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1 -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 -#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x030) +#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x34) /* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) -#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1)) -#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1 -#define SENSITIVE_PRO_MMU_WR_ACS_S 1 +/*description: .*/ +#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_WR_ACS_S 1 /* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) -#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0)) -#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1 -#define SENSITIVE_PRO_MMU_RD_ACS_S 0 +/*description: .*/ +#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_RD_ACS_S 0 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x034) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x38) /* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x038) -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x3C) +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x03C) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x40) /* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x040) -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x44) +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x044) -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S 0 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x48) +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x048) -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x4C) +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x04C) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x50) /* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x050) -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x54) +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x054) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x58) /* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x058) -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x5C) +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x05C) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x60) /* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x060) -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x64) +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x064) -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK_S 0 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x68) +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x068) -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x6C) +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x06C) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x70) /* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x070) -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x74) +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x074) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x78) /* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x078) -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x7C) +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x07C) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x80) /* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x080) -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x84) +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x084) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x88) +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x8C) +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x90) /* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x088) -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x94) +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x08C) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x98) /* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x090) -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x9C) +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x094) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xA0) /* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x098) -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xA4) +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x09C) -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S 0 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xA8) +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0A0) -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xAC) +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0A4) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xB0) /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0A8) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xB4) /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S 1 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0AC) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xB8) /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[24:3] ;default: 22'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 3 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 3 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 1 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 1 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x0B0) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0xBC) /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V) << (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 +/*description: .*/ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0B4) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xC0) /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0B8) -/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x0000007F -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V 0x7F -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S 14 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xC4) +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S 14 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S 12 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S 12 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S 10 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S 10 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S 8 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S 8 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S 6 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S 6 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S 4 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S 4 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S 2 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0BC) -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x0000007F -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V 0x7F -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S 14 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xC8) +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S 14 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S 12 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S 12 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S 10 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S 10 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S 8 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S 8 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S 6 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S 6 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S 4 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S 4 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S 2 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x0C0) -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x0000007F -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V 0x7F -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S 14 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0xCC) +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S 14 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S 12 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S 12 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S 10 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S 10 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S 8 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S 8 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S 6 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S 6 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S 4 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S 4 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S 2 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x0C4) -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x0000007F -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V 0x7F -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S 14 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0xD0) +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S 14 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S 12 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S 12 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S 10 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S 10 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S 8 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S 8 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S 6 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S 6 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S 4 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S 4 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S 2 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x0C8) -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x0000007F -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V 0x7F -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S 14 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0xD4) +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x000000FF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V 0xFF +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S 14 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S 12 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S 12 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S 10 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S 10 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S 8 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S 8 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S 6 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S 6 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S 4 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S 4 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S 2 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0CC) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xD8) /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0D0) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xDC) /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 18 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 18 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 15 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 15 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 12 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 12 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 9 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 9 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 6 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 6 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 3 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 3 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0D4) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xE0) /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 18 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 18 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 15 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 15 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 12 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 12 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 9 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 9 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 6 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 6 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 3 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 3 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0D8) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xE4) /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0DC) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xE8) /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0E0) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xEC) /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 +/*description: .*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 +/*description: .*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0E4) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xF0) /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0E8) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xF4) /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0EC) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xF8) /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 +/*description: .*/ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 +/*description: .*/ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0F0) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xFC) /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0F4) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x100) /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 26 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 26 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 24 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 24 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0F8) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x104) /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0FC) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x108) /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x100) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x10C) /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x104) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x110) /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V) << (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x108) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x114) /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x10C) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x118) /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x110) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x11C) /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x114) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x120) /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V) << (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 -#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x118) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x124) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x11C) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x128) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 28 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 28 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_S 22 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S 18 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S 20 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_S 14 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x120) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x12C) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S 24 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S 24 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S 18 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S 18 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S 14 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S 14 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S 12 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S 8 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x124) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_S 30 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x130) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_S 24 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_S 18 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S 16 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S 16 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S 12 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S 10 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S 10 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S 8 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S 2 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x128) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 24 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S 12 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x134) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S 10 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S 10 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x12C) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x138) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 28 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 28 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_S 22 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S 18 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S 20 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_S 14 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x130) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x13C) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S 24 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S 24 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S 18 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S 18 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S 14 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S 14 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S 12 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S 8 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x134) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_S 30 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x140) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_S 24 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_S 18 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S 16 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S 16 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S 12 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S 10 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S 10 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S 8 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S 2 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x138) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 24 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S 12 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x144) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S 10 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S 10 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x13C) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x148) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x140) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x14C) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x144) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x150) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 0x000007FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V 0x7FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S 11 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S 11 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V 0x7FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x148) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x154) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S 9 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S 9 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S 3 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S 3 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x14C) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x158) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 0x000007FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V 0x7FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S 11 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S 11 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V 0x7FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x150) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x15C) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S 9 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S 9 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S 6 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S 3 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S 3 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x154) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x160) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x164) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S 20 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S 18 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S 16 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S 14 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S 12 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S 10 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S 8 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S 6 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S 4 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S 2 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x168) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S 20 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S 18 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S 16 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S 14 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S 12 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S 10 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S 8 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S 6 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S 4 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S 2 +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x3 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x16C) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x170) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x174) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x178) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x17C) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x180) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x184) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x188) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x18C) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x190) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x194) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S 0 + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x198) +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_M ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V 0x3FFFFFFF +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x19C) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x158) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x1A0) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S 1 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x15C) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x1A4) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x160) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x1A8) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x164) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x1AC) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x168) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x1B0) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x16C) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x1B4) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x170) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x1B8) /* SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V 0x1 -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V 0x1 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S 0 -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x174) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x1BC) +/* SENSITIVE_CORE_0_VECBASE_WORLD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK (BIT(0)) +#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_M (BIT(0)) +#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_V 0x1 +#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_S 0 + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x1C0) /* SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL 0x00000003 -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_M ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V) << (SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S)) -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V 0x3 -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S 22 -/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE 0x003FFFFF -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_M ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_V) << (SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_S)) -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_V 0x3FFFFF -#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL 0x00000003 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_M ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V 0x3 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S 22 +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE 0x003FFFFF +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_M ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V 0x3FFFFF +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S 0 -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x178) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_REG (DR_REG_SENSITIVE_BASE + 0x1C4) +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE 0x003FFFFF +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_M ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V 0x3FFFFF +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S 0 + +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x1C8) /* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V 0x1 -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V 0x1 +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S 0 -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x17C) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x1CC) /* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0)) -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_M (BIT(0)) -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x1 -#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0 +/*description: .*/ +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_M (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x1 +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x180) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x1D0) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x184) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x1D4) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 28 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 28 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_S 22 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S 20 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S 18 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S 20 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_S 14 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x188) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x1D8) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S 24 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S 24 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_S 20 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S 18 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S 18 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S 14 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S 14 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S 12 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S 12 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S 8 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S 8 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x18C) -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_S 30 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x1DC) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_S 24 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_S 20 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_S 18 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S 16 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S 16 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S 12 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S 10 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S 10 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S 8 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S 8 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S 2 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x190) -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 28 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 26 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 24 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 22 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 20 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 18 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 16 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 14 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S 12 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x1E0) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 30 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S 12 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S 10 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S 10 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x194) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x1E4) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 28 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 28 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_S 22 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S 20 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S 18 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S 20 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_S 14 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x198) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x1E8) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S 24 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S 24 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_S 20 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S 18 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S 18 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S 14 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S 14 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S 12 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S 12 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S 8 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S 8 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x19C) -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_S 30 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x1EC) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_S 24 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_S 20 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_S 18 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S 16 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S 16 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S 12 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S 10 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S 10 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S 8 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S 8 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S 2 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x1A0) -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 28 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 26 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 24 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 22 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 20 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 18 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 16 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 14 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S 12 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x1F0) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 30 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S 12 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S 10 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S 10 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 -/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x1A4) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x1F4) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x1A8) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x1F8) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x1AC) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x1FC) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 0x000007FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V 0x7FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S 11 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S 11 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V 0x7FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x1B0) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x200) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S 9 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S 9 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S 3 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S 3 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x1B4) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x204) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 0x000007FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V 0x7FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S 11 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S 11 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V 0x7FF -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x1B8) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x208) /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S 9 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S 9 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S 6 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S 3 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S 3 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S)) -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x1BC) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x20C) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x210) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S 20 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S 18 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S 16 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S 14 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S 12 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S 10 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S 8 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S 6 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S 4 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S 2 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x214) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S 20 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S 18 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S 16 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S 14 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S 12 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S 10 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S 8 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S 6 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S 4 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S 2 +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x3 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x218) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x21C) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x220) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x224) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x228) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x22C) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x230) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x234) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x238) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x23C) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x240) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S 0 + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x244) +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_M ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V 0x3FFFFFFF +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x248) /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x1C0) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x24C) /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S 1 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x1C4) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x250) /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x1C8) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x254) /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x1CC) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x258) /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x1D0) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x25C) /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x1D4) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x260) /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF -#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x1D8) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x264) /* SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK (BIT(0)) -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V 0x1 -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V 0x1 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S 0 -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x1DC) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x268) +/* SENSITIVE_CORE_1_VECBASE_WORLD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK (BIT(0)) +#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_M (BIT(0)) +#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_V 0x1 +#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_S 0 + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x26C) /* SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL 0x00000003 -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_M ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V) << (SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S)) -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V 0x3 -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S 22 -/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE 0x003FFFFF -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_M ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_V) << (SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_S)) -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_V 0x3FFFFF -#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL 0x00000003 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_M ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V 0x3 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S 22 +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE 0x003FFFFF +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_M ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V 0x3FFFFF +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S 0 -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x1E0) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_2_REG (DR_REG_SENSITIVE_BASE + 0x270) +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: .*/ +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE 0x003FFFFF +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_M ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V 0x3FFFFF +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S 0 + +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x274) /* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK (BIT(0)) -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V 0x1 -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V 0x1 +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S 0 -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x1E4) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x278) /* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0)) -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_M (BIT(0)) -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x1 -#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0 +/*description: .*/ +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_M (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x1 +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0 -#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x1E8) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x27C) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x280) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S 24 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S 20 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S 12 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S 8 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S 2 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x284) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S 24 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S 22 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S 18 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S 12 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S 8 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x288) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S 22 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S 12 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S 8 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S 2 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x28C) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S 24 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S 22 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S 20 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S 18 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S 16 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S 14 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S 12 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S 10 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S 8 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S 4 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S 2 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x290) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR 0x000007FF +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V 0x7FF +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x294) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V 0x7 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S 3 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V 0x7 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x298) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x29C) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x2A0) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(6)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(6)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 6 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 3 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S 1 +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x2A4) +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: .*/ +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR 0xFFFFFFFF +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V 0xFFFFFFFF +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S 0 + +#define SENSITIVE_EDMA_BOUNDARY_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2A8) +/* SENSITIVE_EDMA_BOUNDARY_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_BOUNDARY_LOCK (BIT(0)) +#define SENSITIVE_EDMA_BOUNDARY_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_BOUNDARY_LOCK_V 0x1 +#define SENSITIVE_EDMA_BOUNDARY_LOCK_S 0 + +#define SENSITIVE_EDMA_BOUNDARY_0_REG (DR_REG_SENSITIVE_BASE + 0x2AC) +/* SENSITIVE_EDMA_BOUNDARY_0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_BOUNDARY_0 0x00003FFF +#define SENSITIVE_EDMA_BOUNDARY_0_M ((SENSITIVE_EDMA_BOUNDARY_0_V)<<(SENSITIVE_EDMA_BOUNDARY_0_S)) +#define SENSITIVE_EDMA_BOUNDARY_0_V 0x3FFF +#define SENSITIVE_EDMA_BOUNDARY_0_S 0 + +#define SENSITIVE_EDMA_BOUNDARY_1_REG (DR_REG_SENSITIVE_BASE + 0x2B0) +/* SENSITIVE_EDMA_BOUNDARY_1 : R/W ;bitpos:[13:0] ;default: 14'h2000 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_BOUNDARY_1 0x00003FFF +#define SENSITIVE_EDMA_BOUNDARY_1_M ((SENSITIVE_EDMA_BOUNDARY_1_V)<<(SENSITIVE_EDMA_BOUNDARY_1_S)) +#define SENSITIVE_EDMA_BOUNDARY_1_V 0x3FFF +#define SENSITIVE_EDMA_BOUNDARY_1_S 0 + +#define SENSITIVE_EDMA_BOUNDARY_2_REG (DR_REG_SENSITIVE_BASE + 0x2B4) +/* SENSITIVE_EDMA_BOUNDARY_2 : R/W ;bitpos:[13:0] ;default: 14'h2000 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_BOUNDARY_2 0x00003FFF +#define SENSITIVE_EDMA_BOUNDARY_2_M ((SENSITIVE_EDMA_BOUNDARY_2_V)<<(SENSITIVE_EDMA_BOUNDARY_2_S)) +#define SENSITIVE_EDMA_BOUNDARY_2_V 0x3FFF +#define SENSITIVE_EDMA_BOUNDARY_2_S 0 + +#define SENSITIVE_EDMA_PMS_SPI2_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2B8) +/* SENSITIVE_EDMA_PMS_SPI2_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SPI2_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_SPI2_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_SPI2_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_SPI2_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_SPI2_REG (DR_REG_SENSITIVE_BASE + 0x2BC) +/* SENSITIVE_EDMA_PMS_SPI2_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SPI2_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_M ((SENSITIVE_EDMA_PMS_SPI2_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_SPI2_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SPI2_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_M ((SENSITIVE_EDMA_PMS_SPI2_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_SPI3_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2C0) +/* SENSITIVE_EDMA_PMS_SPI3_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SPI3_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_SPI3_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_SPI3_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_SPI3_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_SPI3_REG (DR_REG_SENSITIVE_BASE + 0x2C4) +/* SENSITIVE_EDMA_PMS_SPI3_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SPI3_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_M ((SENSITIVE_EDMA_PMS_SPI3_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_SPI3_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SPI3_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_M ((SENSITIVE_EDMA_PMS_SPI3_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2C8) +/* SENSITIVE_EDMA_PMS_UHCI0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_UHCI0_REG (DR_REG_SENSITIVE_BASE + 0x2CC) +/* SENSITIVE_EDMA_PMS_UHCI0_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_M ((SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_UHCI0_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_M ((SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_I2S0_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2D0) +/* SENSITIVE_EDMA_PMS_I2S0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_I2S0_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_I2S0_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_I2S0_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_I2S0_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_I2S0_REG (DR_REG_SENSITIVE_BASE + 0x2D4) +/* SENSITIVE_EDMA_PMS_I2S0_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_I2S0_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_M ((SENSITIVE_EDMA_PMS_I2S0_ATTR2_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_I2S0_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_I2S0_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_M ((SENSITIVE_EDMA_PMS_I2S0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_I2S1_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2D8) +/* SENSITIVE_EDMA_PMS_I2S1_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_I2S1_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_I2S1_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_I2S1_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_I2S1_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_I2S1_REG (DR_REG_SENSITIVE_BASE + 0x2DC) +/* SENSITIVE_EDMA_PMS_I2S1_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_I2S1_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_M ((SENSITIVE_EDMA_PMS_I2S1_ATTR2_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_I2S1_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_I2S1_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_M ((SENSITIVE_EDMA_PMS_I2S1_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2E0) +/* SENSITIVE_EDMA_PMS_LCD_CAM_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_LCD_CAM_REG (DR_REG_SENSITIVE_BASE + 0x2E4) +/* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_M ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_M ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_AES_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2E8) +/* SENSITIVE_EDMA_PMS_AES_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_AES_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_AES_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_AES_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_AES_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_AES_REG (DR_REG_SENSITIVE_BASE + 0x2EC) +/* SENSITIVE_EDMA_PMS_AES_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_AES_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_AES_ATTR2_M ((SENSITIVE_EDMA_PMS_AES_ATTR2_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_AES_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_AES_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_AES_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_AES_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_AES_ATTR1_M ((SENSITIVE_EDMA_PMS_AES_ATTR1_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_AES_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_AES_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_SHA_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2F0) +/* SENSITIVE_EDMA_PMS_SHA_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SHA_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_SHA_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_SHA_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_SHA_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_SHA_REG (DR_REG_SENSITIVE_BASE + 0x2F4) +/* SENSITIVE_EDMA_PMS_SHA_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SHA_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_SHA_ATTR2_M ((SENSITIVE_EDMA_PMS_SHA_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_SHA_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_SHA_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_SHA_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_SHA_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_SHA_ATTR1_M ((SENSITIVE_EDMA_PMS_SHA_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_SHA_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_SHA_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2F8) +/* SENSITIVE_EDMA_PMS_ADC_DAC_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_ADC_DAC_REG (DR_REG_SENSITIVE_BASE + 0x2FC) +/* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_M ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_M ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S 0 + +#define SENSITIVE_EDMA_PMS_RMT_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x300) +/* SENSITIVE_EDMA_PMS_RMT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_RMT_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_RMT_LOCK_M (BIT(0)) +#define SENSITIVE_EDMA_PMS_RMT_LOCK_V 0x1 +#define SENSITIVE_EDMA_PMS_RMT_LOCK_S 0 + +#define SENSITIVE_EDMA_PMS_RMT_REG (DR_REG_SENSITIVE_BASE + 0x304) +/* SENSITIVE_EDMA_PMS_RMT_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_RMT_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_RMT_ATTR2_M ((SENSITIVE_EDMA_PMS_RMT_ATTR2_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR2_S)) +#define SENSITIVE_EDMA_PMS_RMT_ATTR2_V 0x3 +#define SENSITIVE_EDMA_PMS_RMT_ATTR2_S 2 +/* SENSITIVE_EDMA_PMS_RMT_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ +/*description: .*/ +#define SENSITIVE_EDMA_PMS_RMT_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_RMT_ATTR1_M ((SENSITIVE_EDMA_PMS_RMT_ATTR1_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR1_S)) +#define SENSITIVE_EDMA_PMS_RMT_ATTR1_V 0x3 +#define SENSITIVE_EDMA_PMS_RMT_ATTR1_S 0 + +#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x308) /* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_CLK_EN (BIT(0)) -#define SENSITIVE_CLK_EN_M (BIT(0)) -#define SENSITIVE_CLK_EN_V 0x1 -#define SENSITIVE_CLK_EN_S 0 +/*description: .*/ +#define SENSITIVE_CLK_EN (BIT(0)) +#define SENSITIVE_CLK_EN_M (BIT(0)) +#define SENSITIVE_CLK_EN_V 0x1 +#define SENSITIVE_CLK_EN_S 0 + +#define SENSITIVE_RTC_PMS_REG (DR_REG_SENSITIVE_BASE + 0x30C) +/* SENSITIVE_DIS_RTC_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SENSITIVE_DIS_RTC_CPU (BIT(0)) +#define SENSITIVE_DIS_RTC_CPU_M (BIT(0)) +#define SENSITIVE_DIS_RTC_CPU_V 0x1 +#define SENSITIVE_DIS_RTC_CPU_S 0 + +#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) +/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */ +/*description: .*/ +#define SENSITIVE_DATE 0x0FFFFFFF +#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S)) +#define SENSITIVE_DATE_V 0xFFFFFFF +#define SENSITIVE_DATE_S 0 -#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) -/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003240 ; */ -/*description: */ -#define SENSITIVE_DATE 0x0FFFFFFF -#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V) << (SENSITIVE_DATE_S)) -#define SENSITIVE_DATE_V 0xFFFFFFF -#define SENSITIVE_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SENSITIVE_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/sensitive_struct.h b/components/soc/esp32s3/include/soc/sensitive_struct.h index db2d3e1be7..14ee602f95 100644 --- a/components/soc/esp32s3/include/soc/sensitive_struct.h +++ b/components/soc/esp32s3/include/soc/sensitive_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,976 +11,1049 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SENSITIVE_STRUCT_H_ +#define _SOC_SENSITIVE_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { union { struct { - uint32_t cache_dataarray_connect_lock: 1; - uint32_t reserved1: 31; + uint32_t cache_dataarray_connect_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } cache_dataarray_connect_0; union { struct { - uint32_t cache_dataarray_connect_flatten: 8; - uint32_t reserved8: 24; + uint32_t cache_dataarray_connect_flatten: 8; + uint32_t reserved8 : 24; }; uint32_t val; } cache_dataarray_connect_1; union { struct { - uint32_t apb_peripheral_access_lock: 1; - uint32_t reserved1: 31; + uint32_t apb_peripheral_access_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } apb_peripheral_access_0; union { struct { - uint32_t apb_peripheral_access_split_burst: 1; - uint32_t reserved1: 31; + uint32_t apb_peripheral_access_split_burst: 1; + uint32_t reserved1 : 31; }; uint32_t val; } apb_peripheral_access_1; union { struct { - uint32_t internal_sram_usage_lock: 1; - uint32_t reserved1: 31; + uint32_t internal_sram_usage_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } internal_sram_usage_0; union { struct { - uint32_t internal_sram_usage_flatten_0: 11; - uint32_t reserved11: 21; + uint32_t internal_sram_icache_usage : 2; + uint32_t internal_sram_dcache_usage : 2; + uint32_t internal_sram_cpu_usage : 7; + uint32_t reserved11 : 21; }; uint32_t val; } internal_sram_usage_1; union { struct { - uint32_t internal_sram_usage_flatten_1: 18; - uint32_t reserved18: 14; + uint32_t internal_sram_core0_trace_usage: 7; + uint32_t internal_sram_core1_trace_usage: 7; + uint32_t internal_sram_core0_trace_alloc: 2; + uint32_t internal_sram_core1_trace_alloc: 2; + uint32_t reserved18 : 14; }; uint32_t val; } internal_sram_usage_2; union { struct { - uint32_t internal_sram_usage_flatten_2: 4; - uint32_t reserved4: 28; + uint32_t internal_sram_mac_dump_usage : 4; + uint32_t reserved4 : 28; }; uint32_t val; } internal_sram_usage_3; union { struct { - uint32_t internal_sram_usage_flatten_3: 7; - uint32_t reserved7: 25; + uint32_t internal_sram_log_usage : 7; + uint32_t reserved7 : 25; }; uint32_t val; } internal_sram_usage_4; union { struct { - uint32_t cache_tag_access_lock: 1; - uint32_t reserved1: 31; + uint32_t retention_disable : 1; + uint32_t reserved1 : 31; + }; + uint32_t val; + } retention_disable; + union { + struct { + uint32_t cache_tag_access_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } cache_tag_access_0; union { struct { - uint32_t pro_i_tag_rd_acs: 1; - uint32_t pro_i_tag_wr_acs: 1; - uint32_t pro_d_tag_rd_acs: 1; - uint32_t pro_d_tag_wr_acs: 1; - uint32_t reserved4: 28; + uint32_t pro_i_tag_rd_acs : 1; + uint32_t pro_i_tag_wr_acs : 1; + uint32_t pro_d_tag_rd_acs : 1; + uint32_t pro_d_tag_wr_acs : 1; + uint32_t reserved4 : 28; }; uint32_t val; } cache_tag_access_1; union { struct { - uint32_t cache_mmu_access_lock: 1; - uint32_t reserved1: 31; + uint32_t cache_mmu_access_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } cache_mmu_access_0; union { struct { - uint32_t pro_mmu_rd_acs: 1; - uint32_t pro_mmu_wr_acs: 1; - uint32_t reserved2: 30; + uint32_t pro_mmu_rd_acs : 1; + uint32_t pro_mmu_wr_acs : 1; + uint32_t reserved2 : 30; }; uint32_t val; } cache_mmu_access_1; union { struct { - uint32_t dma_apbperi_spi2_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_spi2_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_spi2_pms_constrain_0; union { struct { - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_spi2_pms_constrain_1; union { struct { - uint32_t dma_apbperi_spi3_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_spi3_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_spi3_pms_constrain_0; union { struct { - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_spi3_pms_constrain_1; union { struct { - uint32_t dma_apbperi_uchi0_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_uhci0_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; - } dma_apbperi_uchi0_pms_constrain_0; + } dma_apbperi_uhci0_pms_constrain_0; union { struct { - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; - } dma_apbperi_uchi0_pms_constrain_1; + } dma_apbperi_uhci0_pms_constrain_1; union { struct { - uint32_t dma_apbperi_i2s0_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_i2s0_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_i2s0_pms_constrain_0; union { struct { - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_i2s0_pms_constrain_1; union { struct { - uint32_t dma_apbperi_i2s1_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_i2s1_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_i2s1_pms_constrain_0; union { struct { - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_i2s1_pms_constrain_1; union { struct { - uint32_t dma_apbperi_mac_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_mac_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_mac_pms_constrain_0; union { struct { - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_mac_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_mac_pms_constrain_1; union { struct { - uint32_t dma_apbperi_slc_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_backup_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; - } dma_apbperi_slc_pms_constrain_0; + } dma_apbperi_backup_pms_constrain_0; union { struct { - uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_backup_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_backup_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_backup_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_backup_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; - } dma_apbperi_slc_pms_constrain_1; + } dma_apbperi_backup_pms_constrain_1; union { struct { - uint32_t dma_apbperi_aes_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_aes_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_aes_pms_constrain_0; union { struct { - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_aes_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_aes_pms_constrain_1; union { struct { - uint32_t dma_apbperi_sha_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_sha_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_sha_pms_constrain_0; union { struct { - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_sha_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_sha_pms_constrain_1; union { struct { - uint32_t dma_apbperi_adc_dac_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_adc_dac_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_adc_dac_pms_constrain_0; union { struct { - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_adc_dac_pms_constrain_1; union { struct { - uint32_t dma_apbperi_lcd_cam_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_rmt_pms_constrain_lock: 1; + uint32_t reserved1 : 31; + }; + uint32_t val; + } dma_apbperi_rmt_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; + }; + uint32_t val; + } dma_apbperi_rmt_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_lcd_cam_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_lcd_cam_pms_constrain_0; union { struct { - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_lcd_cam_pms_constrain_1; union { struct { - uint32_t dma_apbperi_usb_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_usb_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_usb_pms_constrain_0; union { struct { - uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_usb_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_usb_pms_constrain_1; union { struct { - uint32_t dma_apbperi_lc_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_lc_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_lc_pms_constrain_0; union { struct { - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_lc_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; } dma_apbperi_lc_pms_constrain_1; union { struct { - uint32_t dma_apbperi_sdio_host_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_sdio_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; - } dma_apbperi_sdio_host_pms_constrain_0; + } dma_apbperi_sdio_pms_constrain_0; union { struct { - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t reserved24: 8; + uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_0: 2; + uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_1: 2; + uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_2: 2; + uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_3: 2; + uint32_t dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_1: 2; + uint32_t reserved12 : 20; }; uint32_t val; - } dma_apbperi_sdio_host_pms_constrain_1; + } dma_apbperi_sdio_pms_constrain_1; union { struct { - uint32_t dma_apbperi_pms_monitor_lock: 1; - uint32_t reserved1: 31; + uint32_t dma_apbperi_pms_monitor_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } dma_apbperi_pms_monitor_0; union { struct { - uint32_t dma_apbperi_pms_monitor_violate_clr: 1; - uint32_t dma_apbperi_pms_monitor_violate_en: 1; - uint32_t reserved2: 30; + uint32_t dma_apbperi_pms_monitor_violate_clr: 1; + uint32_t dma_apbperi_pms_monitor_violate_en: 1; + uint32_t reserved2 : 30; }; uint32_t val; } dma_apbperi_pms_monitor_1; union { struct { - uint32_t dma_apbperi_pms_monitor_violate_intr: 1; - uint32_t dma_apbperi_pms_monitor_violate_status_world: 2; - uint32_t dma_apbperi_pms_monitor_violate_status_addr: 22; - uint32_t reserved25: 7; + uint32_t dma_apbperi_pms_monitor_violate_intr: 1; + uint32_t dma_apbperi_pms_monitor_violate_status_world: 2; + uint32_t dma_apbperi_pms_monitor_violate_status_addr: 22; + uint32_t reserved25 : 7; }; uint32_t val; } dma_apbperi_pms_monitor_2; union { struct { - uint32_t dma_apbperi_pms_monitor_violate_status_wr: 1; - uint32_t dma_apbperi_pms_monitor_violate_status_byteen: 16; - uint32_t reserved17: 15; + uint32_t dma_apbperi_pms_monitor_violate_status_wr: 1; + uint32_t dma_apbperi_pms_monitor_violate_status_byteen: 16; + uint32_t reserved17 : 15; }; uint32_t val; } dma_apbperi_pms_monitor_3; union { struct { - uint32_t core_x_iram0_dram0_dma_split_line_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t core_x_iram0_dram0_dma_split_line_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } core_x_iram0_dram0_dma_split_line_constrain_0; union { struct { - uint32_t core_x_iram0_dram0_dma_sram_category_0: 2; - uint32_t core_x_iram0_dram0_dma_sram_category_1: 2; - uint32_t core_x_iram0_dram0_dma_sram_category_2: 2; - uint32_t core_x_iram0_dram0_dma_sram_category_3: 2; - uint32_t core_x_iram0_dram0_dma_sram_category_4: 2; - uint32_t core_x_iram0_dram0_dma_sram_category_5: 2; - uint32_t core_x_iram0_dram0_dma_sram_category_6: 2; - uint32_t core_x_iram0_dram0_dma_sram_splitaddr: 7; - uint32_t reserved21: 11; + uint32_t core_x_iram0_dram0_dma_sram_category_0: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_1: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_2: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_3: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_4: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_5: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_6: 2; + uint32_t core_x_iram0_dram0_dma_sram_splitaddr: 8; + uint32_t reserved22 : 10; }; uint32_t val; } core_x_iram0_dram0_dma_split_line_constrain_1; union { struct { - uint32_t core_x_iram0_sram_line_0_category_0: 2; - uint32_t core_x_iram0_sram_line_0_category_1: 2; - uint32_t core_x_iram0_sram_line_0_category_2: 2; - uint32_t core_x_iram0_sram_line_0_category_3: 2; - uint32_t core_x_iram0_sram_line_0_category_4: 2; - uint32_t core_x_iram0_sram_line_0_category_5: 2; - uint32_t core_x_iram0_sram_line_0_category_6: 2; - uint32_t core_x_iram0_sram_line_0_splitaddr: 7; - uint32_t reserved21: 11; + uint32_t core_x_iram0_sram_line_0_category_0: 2; + uint32_t core_x_iram0_sram_line_0_category_1: 2; + uint32_t core_x_iram0_sram_line_0_category_2: 2; + uint32_t core_x_iram0_sram_line_0_category_3: 2; + uint32_t core_x_iram0_sram_line_0_category_4: 2; + uint32_t core_x_iram0_sram_line_0_category_5: 2; + uint32_t core_x_iram0_sram_line_0_category_6: 2; + uint32_t core_x_iram0_sram_line_0_splitaddr: 8; + uint32_t reserved22 : 10; }; uint32_t val; } core_x_iram0_dram0_dma_split_line_constrain_2; union { struct { - uint32_t core_x_iram0_sram_line_1_category_0: 2; - uint32_t core_x_iram0_sram_line_1_category_1: 2; - uint32_t core_x_iram0_sram_line_1_category_2: 2; - uint32_t core_x_iram0_sram_line_1_category_3: 2; - uint32_t core_x_iram0_sram_line_1_category_4: 2; - uint32_t core_x_iram0_sram_line_1_category_5: 2; - uint32_t core_x_iram0_sram_line_1_category_6: 2; - uint32_t core_x_iram0_sram_line_1_splitaddr: 7; - uint32_t reserved21: 11; + uint32_t core_x_iram0_sram_line_1_category_0: 2; + uint32_t core_x_iram0_sram_line_1_category_1: 2; + uint32_t core_x_iram0_sram_line_1_category_2: 2; + uint32_t core_x_iram0_sram_line_1_category_3: 2; + uint32_t core_x_iram0_sram_line_1_category_4: 2; + uint32_t core_x_iram0_sram_line_1_category_5: 2; + uint32_t core_x_iram0_sram_line_1_category_6: 2; + uint32_t core_x_iram0_sram_line_1_splitaddr: 8; + uint32_t reserved22 : 10; }; uint32_t val; } core_x_iram0_dram0_dma_split_line_constrain_3; union { struct { - uint32_t core_x_dram0_dma_sram_line_0_category_0: 2; - uint32_t core_x_dram0_dma_sram_line_0_category_1: 2; - uint32_t core_x_dram0_dma_sram_line_0_category_2: 2; - uint32_t core_x_dram0_dma_sram_line_0_category_3: 2; - uint32_t core_x_dram0_dma_sram_line_0_category_4: 2; - uint32_t core_x_dram0_dma_sram_line_0_category_5: 2; - uint32_t core_x_dram0_dma_sram_line_0_category_6: 2; - uint32_t core_x_dram0_dma_sram_line_0_splitaddr: 7; - uint32_t reserved21: 11; + uint32_t core_x_dram0_dma_sram_line_0_category_0: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_1: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_2: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_3: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_4: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_5: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_6: 2; + uint32_t core_x_dram0_dma_sram_line_0_splitaddr: 8; + uint32_t reserved22 : 10; }; uint32_t val; } core_x_iram0_dram0_dma_split_line_constrain_4; union { struct { - uint32_t core_x_dram0_dma_sram_line_1_category_0: 2; - uint32_t core_x_dram0_dma_sram_line_1_category_1: 2; - uint32_t core_x_dram0_dma_sram_line_1_category_2: 2; - uint32_t core_x_dram0_dma_sram_line_1_category_3: 2; - uint32_t core_x_dram0_dma_sram_line_1_category_4: 2; - uint32_t core_x_dram0_dma_sram_line_1_category_5: 2; - uint32_t core_x_dram0_dma_sram_line_1_category_6: 2; - uint32_t core_x_dram0_dma_sram_line_1_splitaddr: 7; - uint32_t reserved21: 11; + uint32_t core_x_dram0_dma_sram_line_1_category_0: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_1: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_2: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_3: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_4: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_5: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_6: 2; + uint32_t core_x_dram0_dma_sram_line_1_splitaddr: 8; + uint32_t reserved22 : 10; }; uint32_t val; } core_x_iram0_dram0_dma_split_line_constrain_5; union { struct { - uint32_t core_x_iram0_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t core_x_iram0_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } core_x_iram0_pms_constrain_0; union { struct { - uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_0: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_1: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_2: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_3: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1: 3; - uint32_t core_x_iram0_pms_constrain_rom_world_1_pms: 3; - uint32_t reserved21: 11; + uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_0: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_1: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_2: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_3: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1: 3; + uint32_t core_x_iram0_pms_constrain_rom_world_1_pms: 3; + uint32_t reserved21 : 11; }; uint32_t val; } core_x_iram0_pms_constrain_1; union { struct { - uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_0: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_1: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_2: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_3: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0: 3; - uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1: 3; - uint32_t core_x_iram0_pms_constrain_rom_world_0_pms: 3; - uint32_t reserved21: 11; + uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_0: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_1: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_2: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_3: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1: 3; + uint32_t core_x_iram0_pms_constrain_rom_world_0_pms: 3; + uint32_t reserved21 : 11; }; uint32_t val; } core_x_iram0_pms_constrain_2; union { struct { - uint32_t core_0_iram0_pms_monitor_lock: 1; - uint32_t reserved1: 31; + uint32_t core_0_iram0_pms_monitor_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } core_0_iram0_pms_monitor_0; union { struct { - uint32_t core_0_iram0_pms_monitor_violate_clr: 1; - uint32_t core_0_iram0_pms_monitor_violate_en: 1; - uint32_t reserved2: 30; + uint32_t core_0_iram0_pms_monitor_violate_clr: 1; + uint32_t core_0_iram0_pms_monitor_violate_en: 1; + uint32_t reserved2 : 30; }; uint32_t val; } core_0_iram0_pms_monitor_1; union { struct { - uint32_t core_0_iram0_pms_monitor_violate_intr: 1; - uint32_t core_0_iram0_pms_monitor_violate_status_wr: 1; - uint32_t core_0_iram0_pms_monitor_violate_status_loadstore: 1; - uint32_t core_0_iram0_pms_monitor_violate_status_world: 2; - uint32_t core_0_iram0_pms_monitor_violate_status_addr: 24; - uint32_t reserved29: 3; + uint32_t core_0_iram0_pms_monitor_violate_intr: 1; + uint32_t core_0_iram0_pms_monitor_violate_status_wr: 1; + uint32_t core_0_iram0_pms_monitor_violate_status_loadstore: 1; + uint32_t core_0_iram0_pms_monitor_violate_status_world: 2; + uint32_t core_0_iram0_pms_monitor_violate_status_addr: 24; + uint32_t reserved29 : 3; }; uint32_t val; } core_0_iram0_pms_monitor_2; union { struct { - uint32_t core_1_iram0_pms_monitor_lock: 1; - uint32_t reserved1: 31; + uint32_t core_1_iram0_pms_monitor_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } core_1_iram0_pms_monitor_0; union { struct { - uint32_t core_1_iram0_pms_monitor_violate_clr: 1; - uint32_t core_1_iram0_pms_monitor_violate_en: 1; - uint32_t reserved2: 30; + uint32_t core_1_iram0_pms_monitor_violate_clr: 1; + uint32_t core_1_iram0_pms_monitor_violate_en: 1; + uint32_t reserved2 : 30; }; uint32_t val; } core_1_iram0_pms_monitor_1; union { struct { - uint32_t core_1_iram0_pms_monitor_violate_intr: 1; - uint32_t core_1_iram0_pms_monitor_violate_status_wr: 1; - uint32_t core_1_iram0_pms_monitor_violate_status_loadstore: 1; - uint32_t core_1_iram0_pms_monitor_violate_status_world: 2; - uint32_t core_1_iram0_pms_monitor_violate_status_addr: 24; - uint32_t reserved29: 3; + uint32_t core_1_iram0_pms_monitor_violate_intr: 1; + uint32_t core_1_iram0_pms_monitor_violate_status_wr: 1; + uint32_t core_1_iram0_pms_monitor_violate_status_loadstore: 1; + uint32_t core_1_iram0_pms_monitor_violate_status_world: 2; + uint32_t core_1_iram0_pms_monitor_violate_status_addr: 24; + uint32_t reserved29 : 3; }; uint32_t val; } core_1_iram0_pms_monitor_2; union { struct { - uint32_t core_x_dram0_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t core_x_dram0_pms_constrain_lock: 1; + uint32_t reserved1 : 31; }; uint32_t val; } core_x_dram0_pms_constrain_0; union { struct { - uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_0: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_1: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_2: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_3: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_0: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_1: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_2: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_3: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; - uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; - uint32_t core_x_dram0_pms_constrain_rom_world_0_pms: 2; - uint32_t core_x_dram0_pms_constrain_rom_world_1_pms: 2; - uint32_t reserved28: 4; + uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_0: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_1: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_2: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_3: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_0: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_1: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_2: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_3: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t core_x_dram0_pms_constrain_rom_world_0_pms: 2; + uint32_t core_x_dram0_pms_constrain_rom_world_1_pms: 2; + uint32_t reserved28 : 4; }; uint32_t val; } core_x_dram0_pms_constrain_1; union { struct { - uint32_t core_0_dram0_pms_monitor_lock: 1; - uint32_t reserved1: 31; + uint32_t core_0_dram0_pms_monitor_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } core_0_dram0_pms_monitor_0; union { struct { - uint32_t core_0_dram0_pms_monitor_violate_clr: 1; - uint32_t core_0_dram0_pms_monitor_violate_en: 1; - uint32_t reserved2: 30; + uint32_t core_0_dram0_pms_monitor_violate_clr: 1; + uint32_t core_0_dram0_pms_monitor_violate_en: 1; + uint32_t reserved2 : 30; }; uint32_t val; } core_0_dram0_pms_monitor_1; union { struct { - uint32_t core_0_dram0_pms_monitor_violate_intr: 1; - uint32_t core_0_dram0_pms_monitor_violate_status_lock: 1; - uint32_t core_0_dram0_pms_monitor_violate_status_world: 2; - uint32_t core_0_dram0_pms_monitor_violate_status_addr: 22; - uint32_t reserved26: 6; + uint32_t core_0_dram0_pms_monitor_violate_intr: 1; + uint32_t core_0_dram0_pms_monitor_violate_status_lock: 1; + uint32_t core_0_dram0_pms_monitor_violate_status_world: 2; + uint32_t core_0_dram0_pms_monitor_violate_status_addr: 22; + uint32_t reserved26 : 6; }; uint32_t val; } core_0_dram0_pms_monitor_2; union { struct { - uint32_t core_0_dram0_pms_monitor_violate_status_wr: 1; - uint32_t core_0_dram0_pms_monitor_violate_status_byteen: 16; - uint32_t reserved17: 15; + uint32_t core_0_dram0_pms_monitor_violate_status_wr: 1; + uint32_t core_0_dram0_pms_monitor_violate_status_byteen: 16; + uint32_t reserved17 : 15; }; uint32_t val; } core_0_dram0_pms_monitor_3; union { struct { - uint32_t core_1_dram0_pms_monitor_lock: 1; - uint32_t reserved1: 31; + uint32_t core_1_dram0_pms_monitor_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } core_1_dram0_pms_monitor_0; union { struct { - uint32_t core_1_dram0_pms_monitor_violate_clr: 1; - uint32_t core_1_dram0_pms_monitor_violate_en: 1; - uint32_t reserved2: 30; + uint32_t core_1_dram0_pms_monitor_violate_clr: 1; + uint32_t core_1_dram0_pms_monitor_violate_en: 1; + uint32_t reserved2 : 30; }; uint32_t val; } core_1_dram0_pms_monitor_1; union { struct { - uint32_t core_1_dram0_pms_monitor_violate_intr: 1; - uint32_t core_1_dram0_pms_monitor_violate_status_lock: 1; - uint32_t core_1_dram0_pms_monitor_violate_status_world: 2; - uint32_t core_1_dram0_pms_monitor_violate_status_addr: 22; - uint32_t reserved26: 6; + uint32_t core_1_dram0_pms_monitor_violate_intr: 1; + uint32_t core_1_dram0_pms_monitor_violate_status_lock: 1; + uint32_t core_1_dram0_pms_monitor_violate_status_world: 2; + uint32_t core_1_dram0_pms_monitor_violate_status_addr: 22; + uint32_t reserved26 : 6; }; uint32_t val; } core_1_dram0_pms_monitor_2; union { struct { - uint32_t core_1_dram0_pms_monitor_violate_status_wr: 1; - uint32_t core_1_dram0_pms_monitor_violate_status_byteen: 16; - uint32_t reserved17: 15; + uint32_t core_1_dram0_pms_monitor_violate_status_wr: 1; + uint32_t core_1_dram0_pms_monitor_violate_status_byteen: 16; + uint32_t reserved17 : 15; }; uint32_t val; } core_1_dram0_pms_monitor_3; union { struct { - uint32_t core_0_pif_pms_constrain_lock: 1; - uint32_t reserved1: 31; + uint32_t core_0_pif_pms_constrain_lock : 1; + uint32_t reserved1 : 31; }; uint32_t val; } core_0_pif_pms_constrain_0; union { struct { - uint32_t core_0_pif_pms_constrain_world_0_uart: 2; + uint32_t core_0_pif_pms_constrain_world_0_uart: 2; uint32_t core_0_pif_pms_constrain_world_0_g0spi_1: 2; uint32_t core_0_pif_pms_constrain_world_0_g0spi_0: 2; - uint32_t core_0_pif_pms_constrain_world_0_gpio: 2; - uint32_t core_0_pif_pms_constrain_world_0_fe2: 2; - uint32_t core_0_pif_pms_constrain_world_0_fe: 2; - uint32_t core_0_pif_pms_constrain_world_0_timer: 2; - uint32_t core_0_pif_pms_constrain_world_0_rtc_config: 2; - uint32_t core_0_pif_pms_constrain_world_0_io_mux: 2; - uint32_t core_0_pif_pms_constrain_world_0_wdg: 2; - uint32_t core_0_pif_pms_constrain_world_0_hinf: 2; - uint32_t core_0_pif_pms_constrain_world_0_uhci1: 2; - uint32_t core_0_pif_pms_constrain_world_0_misc: 2; - uint32_t core_0_pif_pms_constrain_world_0_i2c: 2; - uint32_t core_0_pif_pms_constrain_world_0_i2s0: 2; - uint32_t core_0_pif_pms_constrain_world_0_uart1: 2; + uint32_t core_0_pif_pms_constrain_world_0_gpio: 2; + uint32_t core_0_pif_pms_constrain_world_0_fe2: 2; + uint32_t core_0_pif_pms_constrain_world_0_fe: 2; + uint32_t core_0_pif_pms_constrain_world_0_timer: 2; + uint32_t core_0_pif_pms_constrain_world_0_rtc: 2; + uint32_t core_0_pif_pms_constrain_world_0_io_mux: 2; + uint32_t reserved18 : 2; + uint32_t core_0_pif_pms_constrain_world_0_hinf: 2; + uint32_t reserved22 : 2; + uint32_t core_0_pif_pms_constrain_world_0_misc: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2c: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2s0: 2; + uint32_t core_0_pif_pms_constrain_world_0_uart1: 2; }; uint32_t val; } core_0_pif_pms_constrain_1; union { struct { - uint32_t core_0_pif_pms_constrain_world_0_bt: 2; - uint32_t core_0_pif_pms_constrain_world_0_bt_buffer: 2; - uint32_t core_0_pif_pms_constrain_world_0_i2c_ext0: 2; - uint32_t core_0_pif_pms_constrain_world_0_uhci0: 2; - uint32_t core_0_pif_pms_constrain_world_0_slchost: 2; - uint32_t core_0_pif_pms_constrain_world_0_rmt: 2; - uint32_t core_0_pif_pms_constrain_world_0_pcnt: 2; - uint32_t core_0_pif_pms_constrain_world_0_slc: 2; - uint32_t core_0_pif_pms_constrain_world_0_ledc: 2; - uint32_t core_0_pif_pms_constrain_world_0_efuse: 2; - uint32_t core_0_pif_pms_constrain_world_0_g0spi_encrypt: 2; - uint32_t core_0_pif_pms_constrain_world_0_bb: 2; - uint32_t core_0_pif_pms_constrain_world_0_pwm0: 2; + uint32_t core_0_pif_pms_constrain_world_0_bt: 2; + uint32_t reserved2 : 2; + uint32_t core_0_pif_pms_constrain_world_0_i2c_ext0: 2; + uint32_t core_0_pif_pms_constrain_world_0_uhci0: 2; + uint32_t core_0_pif_pms_constrain_world_0_slchost: 2; + uint32_t core_0_pif_pms_constrain_world_0_rmt: 2; + uint32_t core_0_pif_pms_constrain_world_0_pcnt: 2; + uint32_t core_0_pif_pms_constrain_world_0_slc: 2; + uint32_t core_0_pif_pms_constrain_world_0_ledc: 2; + uint32_t core_0_pif_pms_constrain_world_0_backup: 2; + uint32_t reserved20 : 2; + uint32_t core_0_pif_pms_constrain_world_0_bb: 2; + uint32_t core_0_pif_pms_constrain_world_0_pwm0: 2; uint32_t core_0_pif_pms_constrain_world_0_timergroup: 2; - uint32_t core_0_pif_pms_constrain_world_0_timergroup1: 2; - uint32_t core_0_pif_pms_constrain_world_0_systimer: 2; + uint32_t core_0_pif_pms_constrain_world_0_timergroup1: 2; + uint32_t core_0_pif_pms_constrain_world_0_systimer: 2; }; uint32_t val; } core_0_pif_pms_constrain_2; union { struct { - uint32_t core_0_pif_pms_constrain_world_0_spi_2: 2; - uint32_t core_0_pif_pms_constrain_world_0_spi_3: 2; - uint32_t core_0_pif_pms_constrain_world_0_apb_ctrl: 2; - uint32_t core_0_pif_pms_constrain_world_0_i2c_ext1: 2; - uint32_t core_0_pif_pms_constrain_world_0_sdio_host: 2; - uint32_t core_0_pif_pms_constrain_world_0_can: 2; - uint32_t core_0_pif_pms_constrain_world_0_pwm1: 2; - uint32_t core_0_pif_pms_constrain_world_0_i2s1: 2; - uint32_t core_0_pif_pms_constrain_world_0_uart2: 2; - uint32_t core_0_pif_pms_constrain_world_0_pwm2: 2; - uint32_t core_0_pif_pms_constrain_world_0_pwm3: 2; - uint32_t core_0_pif_pms_constrain_world_0_rwbt: 2; - uint32_t core_0_pif_pms_constrain_world_0_btmac: 2; - uint32_t core_0_pif_pms_constrain_world_0_wifimac: 2; - uint32_t core_0_pif_pms_constrain_world_0_pwr: 2; - uint32_t core_0_pif_pms_constrain_world_0_g1spi_0: 2; + uint32_t core_0_pif_pms_constrain_world_0_spi_2: 2; + uint32_t core_0_pif_pms_constrain_world_0_spi_3: 2; + uint32_t core_0_pif_pms_constrain_world_0_apb_ctrl: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2c_ext1: 2; + uint32_t core_0_pif_pms_constrain_world_0_sdio_host: 2; + uint32_t core_0_pif_pms_constrain_world_0_can: 2; + uint32_t core_0_pif_pms_constrain_world_0_pwm1: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2s1: 2; + uint32_t core_0_pif_pms_constrain_world_0_uart2: 2; + uint32_t reserved18 : 2; + uint32_t reserved20 : 2; + uint32_t core_0_pif_pms_constrain_world_0_rwbt: 2; + uint32_t reserved24 : 2; + uint32_t core_0_pif_pms_constrain_world_0_wifimac: 2; + uint32_t core_0_pif_pms_constrain_world_0_pwr: 2; + uint32_t reserved30 : 2; }; uint32_t val; } core_0_pif_pms_constrain_3; union { struct { - uint32_t core_0_pif_pms_constrain_world_0_g1spi_encrypt: 2; - uint32_t core_0_pif_pms_constrain_world_0_usb_wrap: 2; - uint32_t core_0_pif_pms_constrain_world_0_crypto_peri: 2; - uint32_t core_0_pif_pms_constrain_world_0_crypto_dma: 2; - uint32_t core_0_pif_pms_constrain_world_0_apb_adc: 2; - uint32_t core_0_pif_pms_constrain_world_0_lcd_cam: 2; - uint32_t core_0_pif_pms_constrain_world_0_usb: 2; - uint32_t core_0_pif_pms_constrain_world_0_system: 2; - uint32_t core_0_pif_pms_constrain_world_0_sensitive: 2; - uint32_t core_0_pif_pms_constrain_world_0_interrupt: 2; - uint32_t core_0_pif_pms_constrain_world_0_dma_copy: 2; - uint32_t core_0_pif_pms_constrain_world_0_cache_config: 2; - uint32_t core_0_pif_pms_constrain_world_0_ad: 2; - uint32_t core_0_pif_pms_constrain_world_0_dio: 2; - uint32_t core_0_pif_pms_constrain_world_0_world_controller: 2; - uint32_t reserved30: 2; + uint32_t core_0_pif_pms_constrain_world_0_usb_device: 2; + uint32_t core_0_pif_pms_constrain_world_0_usb_wrap: 2; + uint32_t core_0_pif_pms_constrain_world_0_crypto_peri: 2; + uint32_t core_0_pif_pms_constrain_world_0_crypto_dma: 2; + uint32_t core_0_pif_pms_constrain_world_0_apb_adc: 2; + uint32_t core_0_pif_pms_constrain_world_0_lcd_cam: 2; + uint32_t core_0_pif_pms_constrain_world_0_bt_pwr: 2; + uint32_t core_0_pif_pms_constrain_world_0_usb: 2; + uint32_t core_0_pif_pms_constrain_world_0_system: 2; + uint32_t core_0_pif_pms_constrain_world_0_sensitive: 2; + uint32_t core_0_pif_pms_constrain_world_0_interrupt: 2; + uint32_t core_0_pif_pms_constrain_world_0_dma_copy: 2; + uint32_t core_0_pif_pms_constrain_world_0_cache_config: 2; + uint32_t core_0_pif_pms_constrain_world_0_ad: 2; + uint32_t core_0_pif_pms_constrain_world_0_dio: 2; + uint32_t core_0_pif_pms_constrain_world_0_world_controller: 2; }; uint32_t val; } core_0_pif_pms_constrain_4; union { struct { - uint32_t core_0_pif_pms_constrain_world_1_uart: 2; + uint32_t core_0_pif_pms_constrain_world_1_uart: 2; uint32_t core_0_pif_pms_constrain_world_1_g0spi_1: 2; uint32_t core_0_pif_pms_constrain_world_1_g0spi_0: 2; - uint32_t core_0_pif_pms_constrain_world_1_gpio: 2; - uint32_t core_0_pif_pms_constrain_world_1_fe2: 2; - uint32_t core_0_pif_pms_constrain_world_1_fe: 2; - uint32_t core_0_pif_pms_constrain_world_1_timer: 2; - uint32_t core_0_pif_pms_constrain_world_1_rtc_config: 2; - uint32_t core_0_pif_pms_constrain_world_1_io_mux: 2; - uint32_t core_0_pif_pms_constrain_world_1_wdg: 2; - uint32_t core_0_pif_pms_constrain_world_1_hinf: 2; - uint32_t core_0_pif_pms_constrain_world_1_uhci1: 2; - uint32_t core_0_pif_pms_constrain_world_1_misc: 2; - uint32_t core_0_pif_pms_constrain_world_1_i2c: 2; - uint32_t core_0_pif_pms_constrain_world_1_i2s0: 2; - uint32_t core_0_pif_pms_constrain_world_1_uart1: 2; + uint32_t core_0_pif_pms_constrain_world_1_gpio: 2; + uint32_t core_0_pif_pms_constrain_world_1_fe2: 2; + uint32_t core_0_pif_pms_constrain_world_1_fe: 2; + uint32_t core_0_pif_pms_constrain_world_1_timer: 2; + uint32_t core_0_pif_pms_constrain_world_1_rtc: 2; + uint32_t core_0_pif_pms_constrain_world_1_io_mux: 2; + uint32_t reserved18 : 2; + uint32_t core_0_pif_pms_constrain_world_1_hinf: 2; + uint32_t reserved22 : 2; + uint32_t core_0_pif_pms_constrain_world_1_misc: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2c: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2s0: 2; + uint32_t core_0_pif_pms_constrain_world_1_uart1: 2; }; uint32_t val; } core_0_pif_pms_constrain_5; union { struct { - uint32_t core_0_pif_pms_constrain_world_1_bt: 2; - uint32_t core_0_pif_pms_constrain_world_1_bt_buffer: 2; - uint32_t core_0_pif_pms_constrain_world_1_i2c_ext0: 2; - uint32_t core_0_pif_pms_constrain_world_1_uhci0: 2; - uint32_t core_0_pif_pms_constrain_world_1_slchost: 2; - uint32_t core_0_pif_pms_constrain_world_1_rmt: 2; - uint32_t core_0_pif_pms_constrain_world_1_pcnt: 2; - uint32_t core_0_pif_pms_constrain_world_1_slc: 2; - uint32_t core_0_pif_pms_constrain_world_1_ledc: 2; - uint32_t core_0_pif_pms_constrain_world_1_efuse: 2; - uint32_t core_0_pif_pms_constrain_world_1_g0spi_encrypt: 2; - uint32_t core_0_pif_pms_constrain_world_1_bb: 2; - uint32_t core_0_pif_pms_constrain_world_1_pwm0: 2; + uint32_t core_0_pif_pms_constrain_world_1_bt: 2; + uint32_t reserved2 : 2; + uint32_t core_0_pif_pms_constrain_world_1_i2c_ext0: 2; + uint32_t core_0_pif_pms_constrain_world_1_uhci0: 2; + uint32_t core_0_pif_pms_constrain_world_1_slchost: 2; + uint32_t core_0_pif_pms_constrain_world_1_rmt: 2; + uint32_t core_0_pif_pms_constrain_world_1_pcnt: 2; + uint32_t core_0_pif_pms_constrain_world_1_slc: 2; + uint32_t core_0_pif_pms_constrain_world_1_ledc: 2; + uint32_t core_0_pif_pms_constrain_world_1_backup: 2; + uint32_t reserved20 : 2; + uint32_t core_0_pif_pms_constrain_world_1_bb: 2; + uint32_t core_0_pif_pms_constrain_world_1_pwm0: 2; uint32_t core_0_pif_pms_constrain_world_1_timergroup: 2; - uint32_t core_0_pif_pms_constrain_world_1_timergroup1: 2; - uint32_t core_0_pif_pms_constrain_world_1_systimer: 2; + uint32_t core_0_pif_pms_constrain_world_1_timergroup1: 2; + uint32_t core_0_pif_pms_constrain_world_1_systimer: 2; }; uint32_t val; } core_0_pif_pms_constrain_6; union { struct { - uint32_t core_0_pif_pms_constrain_world_1_spi_2: 2; - uint32_t core_0_pif_pms_constrain_world_1_spi_3: 2; - uint32_t core_0_pif_pms_constrain_world_1_apb_ctrl: 2; - uint32_t core_0_pif_pms_constrain_world_1_i2c_ext1: 2; - uint32_t core_0_pif_pms_constrain_world_1_sdio_host: 2; - uint32_t core_0_pif_pms_constrain_world_1_can: 2; - uint32_t core_0_pif_pms_constrain_world_1_pwm1: 2; - uint32_t core_0_pif_pms_constrain_world_1_i2s1: 2; - uint32_t core_0_pif_pms_constrain_world_1_uart2: 2; - uint32_t core_0_pif_pms_constrain_world_1_pwm2: 2; - uint32_t core_0_pif_pms_constrain_world_1_pwm3: 2; - uint32_t core_0_pif_pms_constrain_world_1_rwbt: 2; - uint32_t core_0_pif_pms_constrain_world_1_btmac: 2; - uint32_t core_0_pif_pms_constrain_world_1_wifimac: 2; - uint32_t core_0_pif_pms_constrain_world_1_pwr: 2; - uint32_t core_0_pif_pms_constrain_world_1_g1spi_0: 2; + uint32_t core_0_pif_pms_constrain_world_1_spi_2: 2; + uint32_t core_0_pif_pms_constrain_world_1_spi_3: 2; + uint32_t core_0_pif_pms_constrain_world_1_apb_ctrl: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2c_ext1: 2; + uint32_t core_0_pif_pms_constrain_world_1_sdio_host: 2; + uint32_t core_0_pif_pms_constrain_world_1_can: 2; + uint32_t core_0_pif_pms_constrain_world_1_pwm1: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2s1: 2; + uint32_t core_0_pif_pms_constrain_world_1_uart2: 2; + uint32_t reserved18 : 2; + uint32_t reserved20 : 2; + uint32_t core_0_pif_pms_constrain_world_1_rwbt: 2; + uint32_t reserved24 : 2; + uint32_t core_0_pif_pms_constrain_world_1_wifimac: 2; + uint32_t core_0_pif_pms_constrain_world_1_pwr: 2; + uint32_t reserved30 : 2; }; uint32_t val; } core_0_pif_pms_constrain_7; union { struct { - uint32_t core_0_pif_pms_constrain_world_1_g1spi_encrypt: 2; - uint32_t core_0_pif_pms_constrain_world_1_usb_wrap: 2; - uint32_t core_0_pif_pms_constrain_world_1_crypto_peri: 2; - uint32_t core_0_pif_pms_constrain_world_1_crypto_dma: 2; - uint32_t core_0_pif_pms_constrain_world_1_apb_adc: 2; - uint32_t core_0_pif_pms_constrain_world_1_lcd_cam: 2; - uint32_t core_0_pif_pms_constrain_world_1_usb: 2; - uint32_t core_0_pif_pms_constrain_world_1_system: 2; - uint32_t core_0_pif_pms_constrain_world_1_sensitive: 2; - uint32_t core_0_pif_pms_constrain_world_1_interrupt: 2; - uint32_t core_0_pif_pms_constrain_world_1_dma_copy: 2; - uint32_t core_0_pif_pms_constrain_world_1_cache_config: 2; - uint32_t core_0_pif_pms_constrain_world_1_ad: 2; - uint32_t core_0_pif_pms_constrain_world_1_dio: 2; - uint32_t core_0_pif_pms_constrain_world_1_world_controller: 2; - uint32_t reserved30: 2; + uint32_t core_0_pif_pms_constrain_world_1_usb_device: 2; + uint32_t core_0_pif_pms_constrain_world_1_usb_wrap: 2; + uint32_t core_0_pif_pms_constrain_world_1_crypto_peri: 2; + uint32_t core_0_pif_pms_constrain_world_1_crypto_dma: 2; + uint32_t core_0_pif_pms_constrain_world_1_apb_adc: 2; + uint32_t core_0_pif_pms_constrain_world_1_lcd_cam: 2; + uint32_t core_0_pif_pms_constrain_world_1_bt_pwr: 2; + uint32_t core_0_pif_pms_constrain_world_1_usb: 2; + uint32_t core_0_pif_pms_constrain_world_1_system: 2; + uint32_t core_0_pif_pms_constrain_world_1_sensitive: 2; + uint32_t core_0_pif_pms_constrain_world_1_interrupt: 2; + uint32_t core_0_pif_pms_constrain_world_1_dma_copy: 2; + uint32_t core_0_pif_pms_constrain_world_1_cache_config: 2; + uint32_t core_0_pif_pms_constrain_world_1_ad: 2; + uint32_t core_0_pif_pms_constrain_world_1_dio: 2; + uint32_t core_0_pif_pms_constrain_world_1_world_controller: 2; }; uint32_t val; } core_0_pif_pms_constrain_8; union { struct { - uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_0: 11; - uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_1: 11; - uint32_t reserved22: 10; + uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_0: 11; + uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_1: 11; + uint32_t reserved22 : 10; }; uint32_t val; } core_0_pif_pms_constrain_9; union { struct { - uint32_t core_0_pif_pms_constrain_rtcfast_world_0_l: 3; - uint32_t core_0_pif_pms_constrain_rtcfast_world_0_h: 3; - uint32_t core_0_pif_pms_constrain_rtcfast_world_1_l: 3; - uint32_t core_0_pif_pms_constrain_rtcfast_world_1_h: 3; - uint32_t reserved12: 20; + uint32_t core_0_pif_pms_constrain_rtcfast_world_0_l: 3; + uint32_t core_0_pif_pms_constrain_rtcfast_world_0_h: 3; + uint32_t core_0_pif_pms_constrain_rtcfast_world_1_l: 3; + uint32_t core_0_pif_pms_constrain_rtcfast_world_1_h: 3; + uint32_t reserved12 : 20; }; uint32_t val; } core_0_pif_pms_constrain_10; union { struct { - uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0: 11; - uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1: 11; - uint32_t reserved22: 10; + uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0: 11; + uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1: 11; + uint32_t reserved22 : 10; }; uint32_t val; } core_0_pif_pms_constrain_11; union { struct { - uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_l: 3; - uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_h: 3; - uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_l: 3; - uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_h: 3; - uint32_t reserved12: 20; + uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_l: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_h: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_l: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_h: 3; + uint32_t reserved12 : 20; }; uint32_t val; } core_0_pif_pms_constrain_12; union { struct { - uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0: 11; - uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1: 11; - uint32_t reserved22: 10; + uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0: 11; + uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1: 11; + uint32_t reserved22 : 10; }; uint32_t val; } core_0_pif_pms_constrain_13; union { struct { - uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_l: 3; - uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_h: 3; - uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_l: 3; - uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_h: 3; - uint32_t reserved12: 20; + uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_l: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_h: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_l: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_h: 3; + uint32_t reserved12 : 20; }; uint32_t val; } core_0_pif_pms_constrain_14; + union { + struct { + uint32_t core_0ion_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0ion_pms_constrain_0; + union { + struct { + uint32_t core_0ion_pms_constrain_world_0_area_0: 2; + uint32_t core_0ion_pms_constrain_world_0_area_1: 2; + uint32_t core_0ion_pms_constrain_world_0_area_2: 2; + uint32_t core_0ion_pms_constrain_world_0_area_3: 2; + uint32_t core_0ion_pms_constrain_world_0_area_4: 2; + uint32_t core_0ion_pms_constrain_world_0_area_5: 2; + uint32_t core_0ion_pms_constrain_world_0_area_6: 2; + uint32_t core_0ion_pms_constrain_world_0_area_7: 2; + uint32_t core_0ion_pms_constrain_world_0_area_8: 2; + uint32_t core_0ion_pms_constrain_world_0_area_9: 2; + uint32_t core_0ion_pms_constrain_world_0_area_10: 2; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_0ion_pms_constrain_1; + union { + struct { + uint32_t core_0ion_pms_constrain_world_1_area_0: 2; + uint32_t core_0ion_pms_constrain_world_1_area_1: 2; + uint32_t core_0ion_pms_constrain_world_1_area_2: 2; + uint32_t core_0ion_pms_constrain_world_1_area_3: 2; + uint32_t core_0ion_pms_constrain_world_1_area_4: 2; + uint32_t core_0ion_pms_constrain_world_1_area_5: 2; + uint32_t core_0ion_pms_constrain_world_1_area_6: 2; + uint32_t core_0ion_pms_constrain_world_1_area_7: 2; + uint32_t core_0ion_pms_constrain_world_1_area_8: 2; + uint32_t core_0ion_pms_constrain_world_1_area_9: 2; + uint32_t core_0ion_pms_constrain_world_1_area_10: 2; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_0ion_pms_constrain_2; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_0:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_3; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_1:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_4; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_2:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_5; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_3:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_6; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_4:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_7; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_5:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_8; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_6:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_9; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_7:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_10; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_8:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_11; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_9:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_12; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_10:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_13; + union { + struct { + uint32_t core_0ion_pms_constrain_addr_11:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0ion_pms_constrain_14; union { struct { uint32_t core_0_pif_pms_monitor_lock: 1; @@ -1007,7 +1080,7 @@ typedef volatile struct { }; uint32_t val; } core_0_pif_pms_monitor_2; - uint32_t core_0_pif_pms_monitor_3; /**/ + uint32_t core_0_pif_pms_monitor_3; /**/ union { struct { uint32_t core_0_pif_pms_monitor_nonword_violate_clr: 1; @@ -1025,22 +1098,36 @@ typedef volatile struct { }; uint32_t val; } core_0_pif_pms_monitor_5; - uint32_t core_0_pif_pms_monitor_6; /**/ + uint32_t core_0_pif_pms_monitor_6; /**/ union { struct { uint32_t core_0_vecbase_override_lock: 1; uint32_t reserved1: 31; }; uint32_t val; + } core_0_vecbase_override_lock; + union { + struct { + uint32_t core_0_vecbase_world_mask : 1; + uint32_t reserved1 : 31; + }; + uint32_t val; } core_0_vecbase_override_0; union { struct { - uint32_t core_0_vecbase_override_value: 22; + uint32_t core_0_vecbase_override_value:22; uint32_t core_0_vecbase_override_sel: 2; uint32_t reserved24: 8; }; uint32_t val; } core_0_vecbase_override_1; + union { + struct { + uint32_t core_0_vecbase_override_world1_value: 22; + uint32_t reserved22 : 10; + }; + uint32_t val; + } core_0_vecbase_override_2; union { struct { uint32_t core_0_toomanyexceptions_m_override_lock: 1; @@ -1064,43 +1151,43 @@ typedef volatile struct { } core_1_pif_pms_constrain_0; union { struct { - uint32_t core_1_pif_pms_constrain_world_0_uart: 2; - uint32_t core_1_pif_pms_constrain_world_0_g0spi_1: 2; - uint32_t core_1_pif_pms_constrain_world_0_g0spi_0: 2; - uint32_t core_1_pif_pms_constrain_world_0_gpio: 2; - uint32_t core_1_pif_pms_constrain_world_0_fe2: 2; - uint32_t core_1_pif_pms_constrain_world_0_fe: 2; - uint32_t core_1_pif_pms_constrain_world_0_timer: 2; - uint32_t core_1_pif_pms_constrain_world_0_rtc_config: 2; - uint32_t core_1_pif_pms_constrain_world_0_io_mux: 2; - uint32_t core_1_pif_pms_constrain_world_0_wdg: 2; - uint32_t core_1_pif_pms_constrain_world_0_hinf: 2; - uint32_t core_1_pif_pms_constrain_world_0_uhci1: 2; - uint32_t core_1_pif_pms_constrain_world_0_misc: 2; - uint32_t core_1_pif_pms_constrain_world_0_i2c: 2; - uint32_t core_1_pif_pms_constrain_world_0_i2s0: 2; - uint32_t core_1_pif_pms_constrain_world_0_uart1: 2; + uint32_t core_1_pif_pms_constrain_world_0_uart: 2; + uint32_t core_1_pif_pms_constrain_world_0_g0spi_1: 2; + uint32_t core_1_pif_pms_constrain_world_0_g0spi_0: 2; + uint32_t core_1_pif_pms_constrain_world_0_gpio: 2; + uint32_t core_1_pif_pms_constrain_world_0_fe2: 2; + uint32_t core_1_pif_pms_constrain_world_0_fe: 2; + uint32_t core_1_pif_pms_constrain_world_0_timer: 2; + uint32_t core_1_pif_pms_constrain_world_0_rtc: 2; + uint32_t core_1_pif_pms_constrain_world_0_io_mux: 2; + uint32_t reserved18: 2; + uint32_t core_1_pif_pms_constrain_world_0_hinf: 2; + uint32_t reserved22: 2; + uint32_t core_1_pif_pms_constrain_world_0_misc: 2; + uint32_t core_1_pif_pms_constrain_world_0_i2c: 2; + uint32_t core_1_pif_pms_constrain_world_0_i2s0: 2; + uint32_t core_1_pif_pms_constrain_world_0_uart1: 2; }; uint32_t val; } core_1_pif_pms_constrain_1; union { struct { - uint32_t core_1_pif_pms_constrain_world_0_bt: 2; - uint32_t core_1_pif_pms_constrain_world_0_bt_buffer: 2; - uint32_t core_1_pif_pms_constrain_world_0_i2c_ext0: 2; - uint32_t core_1_pif_pms_constrain_world_0_uhci0: 2; - uint32_t core_1_pif_pms_constrain_world_0_slchost: 2; - uint32_t core_1_pif_pms_constrain_world_0_rmt: 2; - uint32_t core_1_pif_pms_constrain_world_0_pcnt: 2; - uint32_t core_1_pif_pms_constrain_world_0_slc: 2; - uint32_t core_1_pif_pms_constrain_world_0_ledc: 2; - uint32_t core_1_pif_pms_constrain_world_0_efuse: 2; - uint32_t core_1_pif_pms_constrain_world_0_g0spi_encrypt: 2; - uint32_t core_1_pif_pms_constrain_world_0_bb: 2; - uint32_t core_1_pif_pms_constrain_world_0_pwm0: 2; - uint32_t core_1_pif_pms_constrain_world_0_timergroup: 2; - uint32_t core_1_pif_pms_constrain_world_0_timergroup1: 2; - uint32_t core_1_pif_pms_constrain_world_0_systimer: 2; + uint32_t core_1_pif_pms_constrain_world_0_bt: 2; + uint32_t reserved2: 2; + uint32_t core_1_pif_pms_constrain_world_0_i2c_ext0: 2; + uint32_t core_1_pif_pms_constrain_world_0_uhci0: 2; + uint32_t core_1_pif_pms_constrain_world_0_slchost: 2; + uint32_t core_1_pif_pms_constrain_world_0_rmt: 2; + uint32_t core_1_pif_pms_constrain_world_0_pcnt: 2; + uint32_t core_1_pif_pms_constrain_world_0_slc: 2; + uint32_t core_1_pif_pms_constrain_world_0_ledc: 2; + uint32_t core_1_pif_pms_constrain_world_0_backup: 2; + uint32_t reserved20: 2; + uint32_t core_1_pif_pms_constrain_world_0_bb: 2; + uint32_t core_1_pif_pms_constrain_world_0_pwm0: 2; + uint32_t core_1_pif_pms_constrain_world_0_timergroup: 2; + uint32_t core_1_pif_pms_constrain_world_0_timergroup1: 2; + uint32_t core_1_pif_pms_constrain_world_0_systimer: 2; }; uint32_t val; } core_1_pif_pms_constrain_2; @@ -1115,24 +1202,25 @@ typedef volatile struct { uint32_t core_1_pif_pms_constrain_world_0_pwm1: 2; uint32_t core_1_pif_pms_constrain_world_0_i2s1: 2; uint32_t core_1_pif_pms_constrain_world_0_uart2: 2; - uint32_t core_1_pif_pms_constrain_world_0_pwm2: 2; - uint32_t core_1_pif_pms_constrain_world_0_pwm3: 2; + uint32_t reserved18: 2; + uint32_t reserved20: 2; uint32_t core_1_pif_pms_constrain_world_0_rwbt: 2; - uint32_t core_1_pif_pms_constrain_world_0_btmac: 2; + uint32_t reserved24: 2; uint32_t core_1_pif_pms_constrain_world_0_wifimac: 2; uint32_t core_1_pif_pms_constrain_world_0_pwr: 2; - uint32_t core_1_pif_pms_constrain_world_0_g1spi_0: 2; + uint32_t reserved30: 2; }; uint32_t val; } core_1_pif_pms_constrain_3; union { struct { - uint32_t core_1_pif_pms_constrain_world_0_g1spi_encrypt: 2; + uint32_t core_1_pif_pms_constrain_world_0_usb_device: 2; uint32_t core_1_pif_pms_constrain_world_0_usb_wrap: 2; uint32_t core_1_pif_pms_constrain_world_0_crypto_peri: 2; uint32_t core_1_pif_pms_constrain_world_0_crypto_dma: 2; uint32_t core_1_pif_pms_constrain_world_0_apb_adc: 2; uint32_t core_1_pif_pms_constrain_world_0_lcd_cam: 2; + uint32_t core_1_pif_pms_constrain_world_0_bt_pwr: 2; uint32_t core_1_pif_pms_constrain_world_0_usb: 2; uint32_t core_1_pif_pms_constrain_world_0_system: 2; uint32_t core_1_pif_pms_constrain_world_0_sensitive: 2; @@ -1142,49 +1230,48 @@ typedef volatile struct { uint32_t core_1_pif_pms_constrain_world_0_ad: 2; uint32_t core_1_pif_pms_constrain_world_0_dio: 2; uint32_t core_1_pif_pms_constrain_world_0_world_controller: 2; - uint32_t reserved30: 2; }; uint32_t val; } core_1_pif_pms_constrain_4; union { struct { - uint32_t core_1_pif_pms_constrain_world_1_uart: 2; - uint32_t core_1_pif_pms_constrain_world_1_g0spi_1: 2; - uint32_t core_1_pif_pms_constrain_world_1_g0spi_0: 2; - uint32_t core_1_pif_pms_constrain_world_1_gpio: 2; - uint32_t core_1_pif_pms_constrain_world_1_fe2: 2; - uint32_t core_1_pif_pms_constrain_world_1_fe: 2; - uint32_t core_1_pif_pms_constrain_world_1_timer: 2; - uint32_t core_1_pif_pms_constrain_world_1_rtc_config: 2; - uint32_t core_1_pif_pms_constrain_world_1_io_mux: 2; - uint32_t core_1_pif_pms_constrain_world_1_wdg: 2; - uint32_t core_1_pif_pms_constrain_world_1_hinf: 2; - uint32_t core_1_pif_pms_constrain_world_1_uhci1: 2; - uint32_t core_1_pif_pms_constrain_world_1_misc: 2; - uint32_t core_1_pif_pms_constrain_world_1_i2c: 2; - uint32_t core_1_pif_pms_constrain_world_1_i2s0: 2; - uint32_t core_1_pif_pms_constrain_world_1_uart1: 2; + uint32_t core_1_pif_pms_constrain_world_1_uart: 2; + uint32_t core_1_pif_pms_constrain_world_1_g0spi_1: 2; + uint32_t core_1_pif_pms_constrain_world_1_g0spi_0: 2; + uint32_t core_1_pif_pms_constrain_world_1_gpio: 2; + uint32_t core_1_pif_pms_constrain_world_1_fe2: 2; + uint32_t core_1_pif_pms_constrain_world_1_fe: 2; + uint32_t core_1_pif_pms_constrain_world_1_timer: 2; + uint32_t core_1_pif_pms_constrain_world_1_rtc: 2; + uint32_t core_1_pif_pms_constrain_world_1_io_mux: 2; + uint32_t reserved18: 2; + uint32_t core_1_pif_pms_constrain_world_1_hinf: 2; + uint32_t reserved22: 2; + uint32_t core_1_pif_pms_constrain_world_1_misc: 2; + uint32_t core_1_pif_pms_constrain_world_1_i2c: 2; + uint32_t core_1_pif_pms_constrain_world_1_i2s0: 2; + uint32_t core_1_pif_pms_constrain_world_1_uart1: 2; }; uint32_t val; } core_1_pif_pms_constrain_5; union { struct { - uint32_t core_1_pif_pms_constrain_world_1_bt: 2; - uint32_t core_1_pif_pms_constrain_world_1_bt_buffer: 2; - uint32_t core_1_pif_pms_constrain_world_1_i2c_ext0: 2; - uint32_t core_1_pif_pms_constrain_world_1_uhci0: 2; - uint32_t core_1_pif_pms_constrain_world_1_slchost: 2; - uint32_t core_1_pif_pms_constrain_world_1_rmt: 2; - uint32_t core_1_pif_pms_constrain_world_1_pcnt: 2; - uint32_t core_1_pif_pms_constrain_world_1_slc: 2; - uint32_t core_1_pif_pms_constrain_world_1_ledc: 2; - uint32_t core_1_pif_pms_constrain_world_1_efuse: 2; - uint32_t core_1_pif_pms_constrain_world_1_g0spi_encrypt: 2; - uint32_t core_1_pif_pms_constrain_world_1_bb: 2; - uint32_t core_1_pif_pms_constrain_world_1_pwm0: 2; - uint32_t core_1_pif_pms_constrain_world_1_timergroup: 2; - uint32_t core_1_pif_pms_constrain_world_1_timergroup1: 2; - uint32_t core_1_pif_pms_constrain_world_1_systimer: 2; + uint32_t core_1_pif_pms_constrain_world_1_bt: 2; + uint32_t reserved2: 2; + uint32_t core_1_pif_pms_constrain_world_1_i2c_ext0: 2; + uint32_t core_1_pif_pms_constrain_world_1_uhci0: 2; + uint32_t core_1_pif_pms_constrain_world_1_slchost: 2; + uint32_t core_1_pif_pms_constrain_world_1_rmt: 2; + uint32_t core_1_pif_pms_constrain_world_1_pcnt: 2; + uint32_t core_1_pif_pms_constrain_world_1_slc: 2; + uint32_t core_1_pif_pms_constrain_world_1_ledc: 2; + uint32_t core_1_pif_pms_constrain_world_1_backup: 2; + uint32_t reserved20: 2; + uint32_t core_1_pif_pms_constrain_world_1_bb: 2; + uint32_t core_1_pif_pms_constrain_world_1_pwm0: 2; + uint32_t core_1_pif_pms_constrain_world_1_timergroup: 2; + uint32_t core_1_pif_pms_constrain_world_1_timergroup1: 2; + uint32_t core_1_pif_pms_constrain_world_1_systimer: 2; }; uint32_t val; } core_1_pif_pms_constrain_6; @@ -1199,24 +1286,25 @@ typedef volatile struct { uint32_t core_1_pif_pms_constrain_world_1_pwm1: 2; uint32_t core_1_pif_pms_constrain_world_1_i2s1: 2; uint32_t core_1_pif_pms_constrain_world_1_uart2: 2; - uint32_t core_1_pif_pms_constrain_world_1_pwm2: 2; - uint32_t core_1_pif_pms_constrain_world_1_pwm3: 2; + uint32_t reserved18: 2; + uint32_t reserved20: 2; uint32_t core_1_pif_pms_constrain_world_1_rwbt: 2; - uint32_t core_1_pif_pms_constrain_world_1_btmac: 2; + uint32_t reserved24: 2; uint32_t core_1_pif_pms_constrain_world_1_wifimac: 2; uint32_t core_1_pif_pms_constrain_world_1_pwr: 2; - uint32_t core_1_pif_pms_constrain_world_1_g1spi_0: 2; + uint32_t reserved30: 2; }; uint32_t val; } core_1_pif_pms_constrain_7; union { struct { - uint32_t core_1_pif_pms_constrain_world_1_g1spi_encrypt: 2; + uint32_t core_1_pif_pms_constrain_world_1_usb_device: 2; uint32_t core_1_pif_pms_constrain_world_1_usb_wrap: 2; uint32_t core_1_pif_pms_constrain_world_1_crypto_peri: 2; uint32_t core_1_pif_pms_constrain_world_1_crypto_dma: 2; uint32_t core_1_pif_pms_constrain_world_1_apb_adc: 2; uint32_t core_1_pif_pms_constrain_world_1_lcd_cam: 2; + uint32_t core_1_pif_pms_constrain_world_1_bt_pwr: 2; uint32_t core_1_pif_pms_constrain_world_1_usb: 2; uint32_t core_1_pif_pms_constrain_world_1_system: 2; uint32_t core_1_pif_pms_constrain_world_1_sensitive: 2; @@ -1226,14 +1314,13 @@ typedef volatile struct { uint32_t core_1_pif_pms_constrain_world_1_ad: 2; uint32_t core_1_pif_pms_constrain_world_1_dio: 2; uint32_t core_1_pif_pms_constrain_world_1_world_controller: 2; - uint32_t reserved30: 2; }; uint32_t val; } core_1_pif_pms_constrain_8; union { struct { - uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_0: 11; - uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_1: 11; + uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_0:11; + uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_1:11; uint32_t reserved22: 10; }; uint32_t val; @@ -1250,8 +1337,8 @@ typedef volatile struct { } core_1_pif_pms_constrain_10; union { struct { - uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0: 11; - uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1: 11; + uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0:11; + uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1:11; uint32_t reserved22: 10; }; uint32_t val; @@ -1268,8 +1355,8 @@ typedef volatile struct { } core_1_pif_pms_constrain_12; union { struct { - uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0: 11; - uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1: 11; + uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0:11; + uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1:11; uint32_t reserved22: 10; }; uint32_t val; @@ -1284,6 +1371,131 @@ typedef volatile struct { }; uint32_t val; } core_1_pif_pms_constrain_14; + union { + struct { + uint32_t core_1ion_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1ion_pms_constrain_0; + union { + struct { + uint32_t core_1ion_pms_constrain_world_0_area_0: 2; + uint32_t core_1ion_pms_constrain_world_0_area_1: 2; + uint32_t core_1ion_pms_constrain_world_0_area_2: 2; + uint32_t core_1ion_pms_constrain_world_0_area_3: 2; + uint32_t core_1ion_pms_constrain_world_0_area_4: 2; + uint32_t core_1ion_pms_constrain_world_0_area_5: 2; + uint32_t core_1ion_pms_constrain_world_0_area_6: 2; + uint32_t core_1ion_pms_constrain_world_0_area_7: 2; + uint32_t core_1ion_pms_constrain_world_0_area_8: 2; + uint32_t core_1ion_pms_constrain_world_0_area_9: 2; + uint32_t core_1ion_pms_constrain_world_0_area_10: 2; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_1ion_pms_constrain_1; + union { + struct { + uint32_t core_1ion_pms_constrain_world_1_area_0: 2; + uint32_t core_1ion_pms_constrain_world_1_area_1: 2; + uint32_t core_1ion_pms_constrain_world_1_area_2: 2; + uint32_t core_1ion_pms_constrain_world_1_area_3: 2; + uint32_t core_1ion_pms_constrain_world_1_area_4: 2; + uint32_t core_1ion_pms_constrain_world_1_area_5: 2; + uint32_t core_1ion_pms_constrain_world_1_area_6: 2; + uint32_t core_1ion_pms_constrain_world_1_area_7: 2; + uint32_t core_1ion_pms_constrain_world_1_area_8: 2; + uint32_t core_1ion_pms_constrain_world_1_area_9: 2; + uint32_t core_1ion_pms_constrain_world_1_area_10: 2; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_1ion_pms_constrain_2; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_0:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_3; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_1:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_4; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_2:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_5; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_3:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_6; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_4:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_7; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_5:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_8; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_6:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_9; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_7:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_10; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_8:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_11; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_9:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_12; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_10:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_13; + union { + struct { + uint32_t core_1ion_pms_constrain_addr_11:30; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1ion_pms_constrain_14; union { struct { uint32_t core_1_pif_pms_monitor_lock: 1; @@ -1310,7 +1522,7 @@ typedef volatile struct { }; uint32_t val; } core_1_pif_pms_monitor_2; - uint32_t core_1_pif_pms_monitor_3; /**/ + uint32_t core_1_pif_pms_monitor_3; /**/ union { struct { uint32_t core_1_pif_pms_monitor_nonword_violate_clr: 1; @@ -1328,22 +1540,36 @@ typedef volatile struct { }; uint32_t val; } core_1_pif_pms_monitor_5; - uint32_t core_1_pif_pms_monitor_6; /**/ + uint32_t core_1_pif_pms_monitor_6; /**/ union { struct { uint32_t core_1_vecbase_override_lock: 1; uint32_t reserved1: 31; }; uint32_t val; + } core_1_vecbase_override_lock; + union { + struct { + uint32_t core_1_vecbase_world_mask : 1; + uint32_t reserved1 : 31; + }; + uint32_t val; } core_1_vecbase_override_0; union { struct { - uint32_t core_1_vecbase_override_value: 22; + uint32_t core_1_vecbase_override_value:22; uint32_t core_1_vecbase_override_sel: 2; uint32_t reserved24: 8; }; uint32_t val; } core_1_vecbase_override_1; + union { + struct { + uint32_t core_1_vecbase_override_world1_value: 22; + uint32_t reserved22 : 10; + }; + uint32_t val; + } core_1_vecbase_override_2; union { struct { uint32_t core_1_toomanyexceptions_m_override_lock: 1; @@ -1358,6 +1584,316 @@ typedef volatile struct { }; uint32_t val; } core_1_toomanyexceptions_m_override_1; + union { + struct { + uint32_t backup_bus_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } backup_bus_pms_constrain_0; + union { + struct { + uint32_t backup_bus_pms_constrain_uart: 2; + uint32_t backup_bus_pms_constrain_g0spi_1: 2; + uint32_t backup_bus_pms_constrain_g0spi_0: 2; + uint32_t backup_bus_pms_constrain_gpio: 2; + uint32_t backup_bus_pms_constrain_fe2: 2; + uint32_t backup_bus_pms_constrain_fe: 2; + uint32_t backup_bus_pms_constrain_timer: 2; + uint32_t backup_bus_pms_constrain_rtc: 2; + uint32_t backup_bus_pms_constrain_io_mux: 2; + uint32_t reserved18: 2; + uint32_t backup_bus_pms_constrain_hinf: 2; + uint32_t reserved22: 2; + uint32_t backup_bus_pms_constrain_misc: 2; + uint32_t backup_bus_pms_constrain_i2c: 2; + uint32_t backup_bus_pms_constrain_i2s0: 2; + uint32_t backup_bus_pms_constrain_uart1: 2; + }; + uint32_t val; + } backup_bus_pms_constrain_1; + union { + struct { + uint32_t backup_bus_pms_constrain_bt: 2; + uint32_t reserved2: 2; + uint32_t backup_bus_pms_constrain_i2c_ext0: 2; + uint32_t backup_bus_pms_constrain_uhci0: 2; + uint32_t backup_bus_pms_constrain_slchost: 2; + uint32_t backup_bus_pms_constrain_rmt: 2; + uint32_t backup_bus_pms_constrain_pcnt: 2; + uint32_t backup_bus_pms_constrain_slc: 2; + uint32_t backup_bus_pms_constrain_ledc: 2; + uint32_t backup_bus_pms_constrain_backup: 2; + uint32_t reserved20: 2; + uint32_t backup_bus_pms_constrain_bb: 2; + uint32_t backup_bus_pms_constrain_pwm0: 2; + uint32_t backup_bus_pms_constrain_timergroup: 2; + uint32_t backup_bus_pms_constrain_timergroup1: 2; + uint32_t backup_bus_pms_constrain_systimer: 2; + }; + uint32_t val; + } backup_bus_pms_constrain_2; + union { + struct { + uint32_t backup_bus_pms_constrain_spi_2: 2; + uint32_t backup_bus_pms_constrain_spi_3: 2; + uint32_t backup_bus_pms_constrain_apb_ctrl: 2; + uint32_t backup_bus_pms_constrain_i2c_ext1: 2; + uint32_t backup_bus_pms_constrain_sdio_host: 2; + uint32_t backup_bus_pms_constrain_can: 2; + uint32_t backup_bus_pms_constrain_pwm1: 2; + uint32_t backup_bus_pms_constrain_i2s1: 2; + uint32_t backup_bus_pms_constrain_uart2: 2; + uint32_t reserved18: 2; + uint32_t reserved20: 2; + uint32_t backup_bus_pms_constrain_rwbt: 2; + uint32_t reserved24: 2; + uint32_t backup_bus_pms_constrain_wifimac: 2; + uint32_t backup_bus_pms_constrain_pwr: 2; + uint32_t reserved30: 2; + }; + uint32_t val; + } backup_bus_pms_constrain_3; + union { + struct { + uint32_t backup_bus_pms_constrain_usb_device: 2; + uint32_t backup_bus_pms_constrain_usb_wrap: 2; + uint32_t backup_bus_pms_constrain_crypto_peri: 2; + uint32_t backup_bus_pms_constrain_crypto_dma: 2; + uint32_t backup_bus_pms_constrain_apb_adc: 2; + uint32_t backup_bus_pms_constrain_lcd_cam: 2; + uint32_t backup_bus_pms_constrain_bt_pwr: 2; + uint32_t backup_bus_pms_constrain_usb: 2; + uint32_t backup_bus_pms_constrain_system: 2; + uint32_t backup_bus_pms_constrain_sensitive: 2; + uint32_t backup_bus_pms_constrain_interrupt: 2; + uint32_t backup_bus_pms_constrain_dma_copy: 2; + uint32_t backup_bus_pms_constrain_cache_config: 2; + uint32_t backup_bus_pms_constrain_ad: 2; + uint32_t backup_bus_pms_constrain_dio: 2; + uint32_t backup_bus_pms_constrain_world_controller: 2; + }; + uint32_t val; + } backup_bus_pms_constrain_4; + union { + struct { + uint32_t backup_bus_pms_constrain_rtcfast_spltaddr:11; + uint32_t reserved11: 21; + }; + uint32_t val; + } backup_bus_pms_constrain_5; + union { + struct { + uint32_t backup_bus_pms_constrain_rtcfast_l: 3; + uint32_t backup_bus_pms_constrain_rtcfast_h: 3; + uint32_t reserved6: 26; + }; + uint32_t val; + } backup_bus_pms_constrain_6; + union { + struct { + uint32_t backup_bus_pms_monitor_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } backup_bus_pms_monitor_0; + union { + struct { + uint32_t backup_bus_pms_monitor_violate_clr: 1; + uint32_t backup_bus_pms_monitor_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } backup_bus_pms_monitor_1; + union { + struct { + uint32_t backup_bus_pms_monitor_violate_intr: 1; + uint32_t backup_bus_pms_monitor_violate_status_htrans: 2; + uint32_t backup_bus_pms_monitor_violate_status_hsize: 3; + uint32_t backup_bus_pms_monitor_violate_status_hwrite: 1; + uint32_t reserved7: 25; + }; + uint32_t val; + } backup_bus_pms_monitor_2; + uint32_t backup_bus_pms_monitor_3; /**/ + union { + struct { + uint32_t edma_boundary_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_boundary_lock; + union { + struct { + uint32_t edma_boundary_0:14; + uint32_t reserved14: 18; + }; + uint32_t val; + } edma_boundary_0; + union { + struct { + uint32_t edma_boundary_1:14; + uint32_t reserved14: 18; + }; + uint32_t val; + } edma_boundary_1; + union { + struct { + uint32_t edma_boundary_2:14; + uint32_t reserved14: 18; + }; + uint32_t val; + } edma_boundary_2; + union { + struct { + uint32_t edma_pms_spi2_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_spi2_lock; + union { + struct { + uint32_t edma_pms_spi2_attr1: 2; + uint32_t edma_pms_spi2_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_spi2; + union { + struct { + uint32_t edma_pms_spi3_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_spi3_lock; + union { + struct { + uint32_t edma_pms_spi3_attr1: 2; + uint32_t edma_pms_spi3_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_spi3; + union { + struct { + uint32_t edma_pms_uhci0_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_uhci0_lock; + union { + struct { + uint32_t edma_pms_uhci0_attr1: 2; + uint32_t edma_pms_uhci0_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_uhci0; + union { + struct { + uint32_t edma_pms_i2s0_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_i2s0_lock; + union { + struct { + uint32_t edma_pms_i2s0_attr1: 2; + uint32_t edma_pms_i2s0_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_i2s0; + union { + struct { + uint32_t edma_pms_i2s1_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_i2s1_lock; + union { + struct { + uint32_t edma_pms_i2s1_attr1: 2; + uint32_t edma_pms_i2s1_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_i2s1; + union { + struct { + uint32_t edma_pms_lcd_cam_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_lcd_cam_lock; + union { + struct { + uint32_t edma_pms_lcd_cam_attr1: 2; + uint32_t edma_pms_lcd_cam_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_lcd_cam; + union { + struct { + uint32_t edma_pms_aes_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_aes_lock; + union { + struct { + uint32_t edma_pms_aes_attr1: 2; + uint32_t edma_pms_aes_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_aes; + union { + struct { + uint32_t edma_pms_sha_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_sha_lock; + union { + struct { + uint32_t edma_pms_sha_attr1: 2; + uint32_t edma_pms_sha_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_sha; + union { + struct { + uint32_t edma_pms_adc_dac_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_adc_dac_lock; + union { + struct { + uint32_t edma_pms_adc_dac_attr1: 2; + uint32_t edma_pms_adc_dac_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_adc_dac; + union { + struct { + uint32_t edma_pms_rmt_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } edma_pms_rmt_lock; + union { + struct { + uint32_t edma_pms_rmt_attr1: 2; + uint32_t edma_pms_rmt_attr2: 2; + uint32_t reserved4: 28; + }; + uint32_t val; + } edma_pms_rmt; union { struct { uint32_t clk_en: 1; @@ -1365,79 +1901,13 @@ typedef volatile struct { }; uint32_t val; } clock_gate; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; + union { + struct { + uint32_t dis_rtc_cpu : 1; + uint32_t reserved1 : 31; + }; + uint32_t val; + } rtc_pms; uint32_t reserved_310; uint32_t reserved_314; uint32_t reserved_318; @@ -2273,9 +2743,11 @@ typedef volatile struct { uint32_t val; } date; } sensitive_dev_t; - extern sensitive_dev_t SENSITIVE; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SENSITIVE_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/sigmadelta_caps.h b/components/soc/esp32s3/include/soc/sigmadelta_caps.h new file mode 100644 index 0000000000..0a3d99c2b1 --- /dev/null +++ b/components/soc/esp32s3/include/soc/sigmadelta_caps.h @@ -0,0 +1,37 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32-S3 have 1 SIGMADELTA peripheral. +#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */ +#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */ +#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX) + +#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */ +#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */ +#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */ +#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */ +#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */ +#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */ +#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */ +#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */ +#define SIGMADELTA_CHANNEL_MAX (8) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index dcc0572303..68cad71176 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -71,7 +71,7 @@ #define DR_REG_PCNT_BASE 0x60017000 #define DR_REG_SLC_BASE 0x60018000 #define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x6001A000 +#define DR_REG_EFUSE_BASE 0x60007000 #define DR_REG_NRX_BASE 0x6001CC00 #define DR_REG_BB_BASE 0x6001D000 #define DR_REG_PWM0_BASE 0x6001E000 @@ -85,11 +85,13 @@ #define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ #define DR_REG_I2C1_EXT_BASE 0x60027000 #define DR_REG_SDMMC_BASE 0x60028000 +#define DR_REG_PERI_BACKUP_BASE 0x6002A000 #define DR_REG_TWAI_BASE 0x6002B000 #define DR_REG_PWM1_BASE 0x6002C000 #define DR_REG_I2S1_BASE 0x6002D000 #define DR_REG_UART2_BASE 0x6002E000 #define DR_REG_SPI4_BASE 0x60037000 +#define DR_REG_USB_DEVICE_BASE 0x60038000 #define DR_REG_USB_WRAP_BASE 0x60039000 #define DR_REG_APB_SARADC_BASE 0x60040000 #define DR_REG_LCD_CAM_BASE 0x60041000 diff --git a/components/soc/esp32s3/include/soc/spi_mem_reg.h b/components/soc/esp32s3/include/soc/spi_mem_reg.h index 39e9e2a828..d83db3b5cd 100644 --- a/components/soc/esp32s3/include/soc/spi_mem_reg.h +++ b/components/soc/esp32s3/include/soc/spi_mem_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,1974 +11,2219 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SPI_MEM_REG_H_ +#define _SOC_SPI_MEM_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000) -/* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Read flash enable. Read flash operation will be triggered when - the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_MEM_FLASH_READ (BIT(31)) -#define SPI_MEM_FLASH_READ_M (BIT(31)) -#define SPI_MEM_FLASH_READ_V 0x1 -#define SPI_MEM_FLASH_READ_S 31 -/* SPI_MEM_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Write flash enable. Write enable command will be sent when the - bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_MEM_FLASH_WREN (BIT(30)) -#define SPI_MEM_FLASH_WREN_M (BIT(30)) -#define SPI_MEM_FLASH_WREN_V 0x1 -#define SPI_MEM_FLASH_WREN_S 30 -/* SPI_MEM_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Write flash disable. Write disable command will be sent when - the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_MEM_FLASH_WRDI (BIT(29)) -#define SPI_MEM_FLASH_WRDI_M (BIT(29)) -#define SPI_MEM_FLASH_WRDI_V 0x1 -#define SPI_MEM_FLASH_WRDI_S 29 -/* SPI_MEM_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Read JEDEC ID . Read ID command will be sent when the bit is - set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_MEM_FLASH_RDID (BIT(28)) -#define SPI_MEM_FLASH_RDID_M (BIT(28)) -#define SPI_MEM_FLASH_RDID_V 0x1 -#define SPI_MEM_FLASH_RDID_S 28 -/* SPI_MEM_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Read status register-1. Read status operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_RDSR (BIT(27)) -#define SPI_MEM_FLASH_RDSR_M (BIT(27)) -#define SPI_MEM_FLASH_RDSR_V 0x1 -#define SPI_MEM_FLASH_RDSR_S 27 -/* SPI_MEM_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Write status register enable. Write status operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_WRSR (BIT(26)) -#define SPI_MEM_FLASH_WRSR_M (BIT(26)) -#define SPI_MEM_FLASH_WRSR_V 0x1 -#define SPI_MEM_FLASH_WRSR_S 26 -/* SPI_MEM_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Page program enable(1 byte ~256 bytes data to be programmed). - Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ -#define SPI_MEM_FLASH_PP (BIT(25)) -#define SPI_MEM_FLASH_PP_M (BIT(25)) -#define SPI_MEM_FLASH_PP_V 0x1 -#define SPI_MEM_FLASH_PP_S 25 -/* SPI_MEM_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Sector erase enable(4KB). Sector erase operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_SE (BIT(24)) -#define SPI_MEM_FLASH_SE_M (BIT(24)) -#define SPI_MEM_FLASH_SE_V 0x1 -#define SPI_MEM_FLASH_SE_S 24 -/* SPI_MEM_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Block erase enable(32KB) . Block erase operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_BE (BIT(23)) -#define SPI_MEM_FLASH_BE_M (BIT(23)) -#define SPI_MEM_FLASH_BE_V 0x1 -#define SPI_MEM_FLASH_BE_S 23 -/* SPI_MEM_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Chip erase enable. Chip erase operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_CE (BIT(22)) -#define SPI_MEM_FLASH_CE_M (BIT(22)) -#define SPI_MEM_FLASH_CE_V 0x1 -#define SPI_MEM_FLASH_CE_S 22 -/* SPI_MEM_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Drive Flash into power down. An operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_DP (BIT(21)) -#define SPI_MEM_FLASH_DP_M (BIT(21)) -#define SPI_MEM_FLASH_DP_V 0x1 -#define SPI_MEM_FLASH_DP_S 21 -/* SPI_MEM_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This bit combined with reg_resandres bit releases Flash from - the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_RES (BIT(20)) -#define SPI_MEM_FLASH_RES_M (BIT(20)) -#define SPI_MEM_FLASH_RES_V 0x1 -#define SPI_MEM_FLASH_RES_S 20 -/* SPI_MEM_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Drive Flash into high performance mode. The bit will be cleared - once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_HPM (BIT(19)) -#define SPI_MEM_FLASH_HPM_M (BIT(19)) -#define SPI_MEM_FLASH_HPM_V 0x1 -#define SPI_MEM_FLASH_HPM_S 19 -/* SPI_MEM_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: User define command enable. An operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_USR (BIT(18)) -#define SPI_MEM_USR_M (BIT(18)) -#define SPI_MEM_USR_V 0x1 -#define SPI_MEM_USR_S 18 -/* SPI_MEM_FLASH_PE : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: In user mode it is set to indicate that program/erase operation - will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_PE (BIT(17)) -#define SPI_MEM_FLASH_PE_M (BIT(17)) -#define SPI_MEM_FLASH_PE_V 0x1 -#define SPI_MEM_FLASH_PE_S 17 +#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T +he bit will be cleared once the operation done. 1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (BIT(31)) +#define SPI_MEM_FLASH_READ_V 0x1 +#define SPI_MEM_FLASH_READ_S 31 +/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the bit is set. The +bit will be cleared once the operation done. 1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (BIT(30)) +#define SPI_MEM_FLASH_WREN_V 0x1 +#define SPI_MEM_FLASH_WREN_S 30 +/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when the bit is set. The + bit will be cleared once the operation done. 1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (BIT(29)) +#define SPI_MEM_FLASH_WRDI_V 0x1 +#define SPI_MEM_FLASH_WRDI_S 29 +/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b +e cleared once the operation done. 1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (BIT(28)) +#define SPI_MEM_FLASH_RDID_V 0x1 +#define SPI_MEM_FLASH_RDID_S 28 +/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered when the bit is + set. The bit will be cleared once the operation done.1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (BIT(27)) +#define SPI_MEM_FLASH_RDSR_V 0x1 +#define SPI_MEM_FLASH_RDSR_S 27 +/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will be triggered when t +he bit is set. The bit will be cleared once the operation done.1: enable 0: disa +ble. .*/ +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (BIT(26)) +#define SPI_MEM_FLASH_WRSR_V 0x1 +#define SPI_MEM_FLASH_WRSR_S 26 +/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~64 bytes data to be programmed). Page program operat +ion will be triggered when the bit is set. The bit will be cleared once the ope +ration done .1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (BIT(25)) +#define SPI_MEM_FLASH_PP_V 0x1 +#define SPI_MEM_FLASH_PP_S 25 +/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit +is set. The bit will be cleared once the operation done.1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (BIT(24)) +#define SPI_MEM_FLASH_SE_V 0x1 +#define SPI_MEM_FLASH_SE_S 24 +/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable(32KB) . Block erase operation will be triggered when the bit + is set. The bit will be cleared once the operation done.1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (BIT(23)) +#define SPI_MEM_FLASH_BE_V 0x1 +#define SPI_MEM_FLASH_BE_S 23 +/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T +he bit will be cleared once the operation done.1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (BIT(22)) +#define SPI_MEM_FLASH_CE_V 0x1 +#define SPI_MEM_FLASH_CE_S 22 +/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered when the bit is set +. The bit will be cleared once the operation done.1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (BIT(21)) +#define SPI_MEM_FLASH_DP_V 0x1 +#define SPI_MEM_FLASH_DP_S 21 +/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down +state or high performance mode and obtains the devices ID. The bit will be clear +ed once the operation done.1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (BIT(20)) +#define SPI_MEM_FLASH_RES_V 0x1 +#define SPI_MEM_FLASH_RES_S 20 +/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared once the operat +ion done.1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (BIT(19)) +#define SPI_MEM_FLASH_HPM_V 0x1 +#define SPI_MEM_FLASH_HPM_S 19 +/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when the bit is set. + The bit will be cleared once the operation done.1: enable 0: disable. .*/ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (BIT(18)) +#define SPI_MEM_USR_V 0x1 +#define SPI_MEM_USR_S 18 +/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ +/*description: In user mode, it is set to indicate that program/erase operation will be trigger +ed. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the o +peration done.1: enable 0: disable. .*/ +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (BIT(17)) +#define SPI_MEM_FLASH_PE_V 0x1 +#define SPI_MEM_FLASH_PE_S 17 -#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x004) +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) /* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: In user mode it is the memory address. other then the bit0-bit23 - is the memory address the bit24-bit31 are the byte length of a transfer.*/ -#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF -#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V) << (SPI_MEM_USR_ADDR_VALUE_S)) -#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF -#define SPI_MEM_USR_ADDR_VALUE_S 0 +/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory +address, the bit24-bit31 are the byte length of a transfer..*/ +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 -#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x008) +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) /* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: In the read operations address phase and read-data phase apply - 4 signals. 1: enable 0: disable.*/ -#define SPI_MEM_FREAD_QIO (BIT(24)) -#define SPI_MEM_FREAD_QIO_M (BIT(24)) -#define SPI_MEM_FREAD_QIO_V 0x1 -#define SPI_MEM_FREAD_QIO_S 24 +/*description: In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit- +mode). 1: enable 0: disable. .*/ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 /* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: In the read operations address phase and read-data phase apply - 2 signals. 1: enable 0: disable.*/ -#define SPI_MEM_FREAD_DIO (BIT(23)) -#define SPI_MEM_FREAD_DIO_M (BIT(23)) -#define SPI_MEM_FREAD_DIO_V 0x1 -#define SPI_MEM_FREAD_DIO_S 23 +/*description: In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit- +mode). 1: enable 0: disable. .*/ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 /* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: two bytes data will be written to status register when it is - set. 1: enable 0: disable.*/ -#define SPI_MEM_WRSR_2B (BIT(22)) -#define SPI_MEM_WRSR_2B_M (BIT(22)) -#define SPI_MEM_WRSR_2B_V 0x1 -#define SPI_MEM_WRSR_2B_S 22 +/*description: Two bytes data will be written to status register when it is set. 1: enable 0: d +isable. .*/ +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (BIT(22)) +#define SPI_MEM_WRSR_2B_V 0x1 +#define SPI_MEM_WRSR_2B_S 22 /* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ -#define SPI_MEM_WP_REG (BIT(21)) -#define SPI_MEM_WP_REG_M (BIT(21)) -#define SPI_MEM_WP_REG_V 0x1 -#define SPI_MEM_WP_REG_S 21 +/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low. .*/ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 /* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ -#define SPI_MEM_FREAD_QUAD (BIT(20)) -#define SPI_MEM_FREAD_QUAD_M (BIT(20)) -#define SPI_MEM_FREAD_QUAD_V 0x1 -#define SPI_MEM_FREAD_QUAD_S 20 +/*description: In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enabl +e 0: disable. .*/ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 /* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ -/*description: The bit is used to set MOSI line polarity 1: high 0 low*/ -#define SPI_MEM_D_POL (BIT(19)) -#define SPI_MEM_D_POL_M (BIT(19)) -#define SPI_MEM_D_POL_V 0x1 -#define SPI_MEM_D_POL_S 19 +/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 /* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: The bit is used to set MISO line polarity 1: high 0 low*/ -#define SPI_MEM_Q_POL (BIT(18)) -#define SPI_MEM_Q_POL_M (BIT(18)) -#define SPI_MEM_Q_POL_V 0x1 -#define SPI_MEM_Q_POL_S 18 +/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 /* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: The Device ID is read out to SPI_MEM_RD_STATUS register this - bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/ -#define SPI_MEM_RESANDRES (BIT(15)) -#define SPI_MEM_RESANDRES_M (BIT(15)) -#define SPI_MEM_RESANDRES_V 0x1 -#define SPI_MEM_RESANDRES_S 15 +/*description: The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with +spi_mem_flash_res bit. 1: enable 0: disable. .*/ +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (BIT(15)) +#define SPI_MEM_RESANDRES_V 0x1 +#define SPI_MEM_RESANDRES_S 15 /* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ -#define SPI_MEM_FREAD_DUAL (BIT(14)) -#define SPI_MEM_FREAD_DUAL_M (BIT(14)) -#define SPI_MEM_FREAD_DUAL_V 0x1 -#define SPI_MEM_FREAD_DUAL_S 14 +/*description: In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable +. .*/ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 /* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio - spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ -#define SPI_MEM_FASTRD_MODE (BIT(13)) -#define SPI_MEM_FASTRD_MODE_M (BIT(13)) -#define SPI_MEM_FASTRD_MODE_V 0x1 -#define SPI_MEM_FASTRD_MODE_S 13 +/*description: This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_ +QUAD or SPI_MEM_FREAD_DUAL is set..*/ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 /* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI1 enable crc32 when writing encrypted data to flash. - 1: enable 0:disable*/ -#define SPI_MEM_TX_CRC_EN (BIT(11)) -#define SPI_MEM_TX_CRC_EN_M (BIT(11)) -#define SPI_MEM_TX_CRC_EN_V 0x1 -#define SPI_MEM_TX_CRC_EN_S 11 +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +e.*/ +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 /* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: For SPI1 initialize crc32 module before writing encrypted data - to flash. Active low.*/ -#define SPI_MEM_FCS_CRC_EN (BIT(10)) -#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) -#define SPI_MEM_FCS_CRC_EN_V 0x1 -#define SPI_MEM_FCS_CRC_EN_S 10 +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +e low..*/ +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 /* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Apply 8 signals during command phase 1:enable 0: disable*/ -#define SPI_MEM_FCMD_OCT (BIT(9)) -#define SPI_MEM_FCMD_OCT_M (BIT(9)) -#define SPI_MEM_FCMD_OCT_V 0x1 -#define SPI_MEM_FCMD_OCT_S 9 +/*description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase..*/ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 /* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Apply 4 signals during command phase 1:enable 0: disable*/ -#define SPI_MEM_FCMD_QUAD (BIT(8)) -#define SPI_MEM_FCMD_QUAD_M (BIT(8)) -#define SPI_MEM_FCMD_QUAD_V 0x1 -#define SPI_MEM_FCMD_QUAD_S 8 +/*description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase..*/ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 /* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Apply 2 signals during command phase 1:enable 0: disable*/ -#define SPI_MEM_FCMD_DUAL (BIT(7)) -#define SPI_MEM_FCMD_DUAL_M (BIT(7)) -#define SPI_MEM_FCMD_DUAL_V 0x1 -#define SPI_MEM_FCMD_DUAL_S 7 +/*description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase..*/ +#define SPI_MEM_FCMD_DUAL (BIT(7)) +#define SPI_MEM_FCMD_DUAL_M (BIT(7)) +#define SPI_MEM_FCMD_DUAL_V 0x1 +#define SPI_MEM_FCMD_DUAL_S 7 /* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Apply 8 signals during address phase 1:enable 0: disable*/ -#define SPI_MEM_FADDR_OCT (BIT(6)) -#define SPI_MEM_FADDR_OCT_M (BIT(6)) -#define SPI_MEM_FADDR_OCT_V 0x1 -#define SPI_MEM_FADDR_OCT_S 6 +/*description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase..*/ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 +#define SPI_MEM_FADDR_OCT_S 6 /* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Apply 8 signals during read-data phase 1:enable 0: disable*/ -#define SPI_MEM_FDIN_OCT (BIT(5)) -#define SPI_MEM_FDIN_OCT_M (BIT(5)) -#define SPI_MEM_FDIN_OCT_V 0x1 -#define SPI_MEM_FDIN_OCT_S 5 +/*description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase..*/ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 /* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Apply 8 signals during write-data phase 1:enable 0: disable*/ -#define SPI_MEM_FDOUT_OCT (BIT(4)) -#define SPI_MEM_FDOUT_OCT_M (BIT(4)) -#define SPI_MEM_FDOUT_OCT_V 0x1 -#define SPI_MEM_FDOUT_OCT_S 4 +/*description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase..*/ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 /* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: In the dummy phase the signal level of spi is output by the spi controller.*/ -#define SPI_MEM_FDUMMY_OUT (BIT(3)) -#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) -#define SPI_MEM_FDUMMY_OUT_V 0x1 -#define SPI_MEM_FDUMMY_OUT_S 3 +/*description: In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller..*/ +#define SPI_MEM_FDUMMY_OUT (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_V 0x1 +#define SPI_MEM_FDUMMY_OUT_S 3 -#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0x00C) -/* SPI_MEM_CS_DLY_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify CS line timing.*/ -#define SPI_MEM_CS_DLY_EDGE (BIT(31)) -#define SPI_MEM_CS_DLY_EDGE_M (BIT(31)) -#define SPI_MEM_CS_DLY_EDGE_V 0x1 -#define SPI_MEM_CS_DLY_EDGE_S 31 -/* SPI_MEM_CS_DLY_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ -/*description: The cs signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk*/ -#define SPI_MEM_CS_DLY_MODE 0x00000003 -#define SPI_MEM_CS_DLY_MODE_M ((SPI_MEM_CS_DLY_MODE_V) << (SPI_MEM_CS_DLY_MODE_S)) -#define SPI_MEM_CS_DLY_MODE_V 0x3 -#define SPI_MEM_CS_DLY_MODE_S 28 -/* SPI_MEM_CS_DLY_NUM : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: spi_mem_cs signal is delayed by system clock cycles*/ -#define SPI_MEM_CS_DLY_NUM 0x00000003 -#define SPI_MEM_CS_DLY_NUM_M ((SPI_MEM_CS_DLY_NUM_V) << (SPI_MEM_CS_DLY_NUM_S)) -#define SPI_MEM_CS_DLY_NUM_V 0x3 -#define SPI_MEM_CS_DLY_NUM_S 26 -/* SPI_MEM_CS_HOLD_DLY : R/W ;bitpos:[25:14] ;default: 12'h1 ; */ -/*description: SPI fsm is delayed to idle by spi clock cycles.*/ -#define SPI_MEM_CS_HOLD_DLY 0x00000FFF -#define SPI_MEM_CS_HOLD_DLY_M ((SPI_MEM_CS_HOLD_DLY_V) << (SPI_MEM_CS_HOLD_DLY_S)) -#define SPI_MEM_CS_HOLD_DLY_V 0xFFF -#define SPI_MEM_CS_HOLD_DLY_S 14 -/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[13:2] ;default: 12'hfff ; */ -/*description: Delay cycles of resume Flash when resume Flash from standby mode - is enable by spi clock.*/ -#define SPI_MEM_CS_HOLD_DLY_RES 0x00000FFF -#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V) << (SPI_MEM_CS_HOLD_DLY_RES_S)) -#define SPI_MEM_CS_HOLD_DLY_RES_V 0xFFF -#define SPI_MEM_CS_HOLD_DLY_RES_S 2 +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) +/* SPI_MEM_RXFIFO_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts +..*/ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (BIT(30)) +#define SPI_MEM_RXFIFO_RST_V 0x1 +#define SPI_MEM_RXFIFO_RST_S 30 +/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ +/*description: Delay cycles of resume Flash when resume Flash from standby mode is enable by SP +I_CLK..*/ +#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF +#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ -#define SPI_MEM_CLK_MODE 0x00000003 -#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V) << (SPI_MEM_CLK_MODE_S)) -#define SPI_MEM_CLK_MODE_V 0x3 -#define SPI_MEM_CLK_MODE_S 0 +/*description: SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS ina +ctive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delaye +d two cycles after SPI_CS inactive 3: SPI_CLK is always on..*/ +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 -#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x010) -/* SPI_MEM_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: The FSM will be reset.*/ -#define SPI_MEM_SYNC_RESET (BIT(31)) -#define SPI_MEM_SYNC_RESET_M (BIT(31)) -#define SPI_MEM_SYNC_RESET_V 0x1 -#define SPI_MEM_SYNC_RESET_S 31 +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +/* SPI_MEM_SYNC_RESET : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The FSM will be reset..*/ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 +#define SPI_MEM_SYNC_RESET_S 31 +/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core + clock cycles..*/ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_CS_HOLD_DELAY_S 25 /* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes - mode when accesses flash.*/ -#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 -#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse +s flash..*/ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 /* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: 1: MSPI skips page corner when accesses flash. 0: Not skip page - corner when accesses flash.*/ -#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/*description: 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when acce +sses flash..*/ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 /* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ -/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS - hold cycle in ECC mode when accessed flash.*/ -#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 -#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V) << (SPI_MEM_ECC_CS_HOLD_TIME_S)) -#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 -#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC +mode when accessed flash..*/ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 /* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ -/*description: Spi cs signal is delayed to inactive by spi clock this bits are - combined with spi_mem_cs_hold bit.*/ -#define SPI_MEM_CS_HOLD_TIME 0x0000001F -#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V) << (SPI_MEM_CS_HOLD_TIME_S)) -#define SPI_MEM_CS_HOLD_TIME_V 0x1F -#define SPI_MEM_CS_HOLD_TIME_S 5 +/*description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), wh +ich is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_ME +M_CS_HOLD bit..*/ +#define SPI_MEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_CS_HOLD_TIME_S 5 /* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ -/*description: (cycles-1) of prepare phase by spi clock this bits are combined - with spi_mem_cs_setup bit.*/ -#define SPI_MEM_CS_SETUP_TIME 0x0000001F -#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V) << (SPI_MEM_CS_SETUP_TIME_S)) -#define SPI_MEM_CS_SETUP_TIME_V 0x1F -#define SPI_MEM_CS_SETUP_TIME_S 0 +/*description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits +are combined with SPI_MEM_CS_SETUP bit..*/ +#define SPI_MEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_CS_SETUP_TIME_S 0 -#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x014) +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) /* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Set this bit in 1-division mode.*/ -#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 -#define SPI_MEM_CLK_EQU_SYSCLK_S 31 +/*description: When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK + = f_MSPI_CORE_CLK..*/ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 /* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ -/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk - frequency is system/(spi_mem_clkcnt_N+1)*/ -#define SPI_MEM_CLKCNT_N 0x000000FF -#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V) << (SPI_MEM_CLKCNT_N_S)) -#define SPI_MEM_CLKCNT_N_V 0xFF -#define SPI_MEM_CLKCNT_N_S 16 +/*description: When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLK +CNT_N+1).*/ +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 /* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ -#define SPI_MEM_CLKCNT_H 0x000000FF -#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V) << (SPI_MEM_CLKCNT_H_S)) -#define SPI_MEM_CLKCNT_H_V 0xFF -#define SPI_MEM_CLKCNT_H_S 8 +/*description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1)..*/ +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 /* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ -/*description: In the master mode it must be equal to spi_mem_clkcnt_N.*/ -#define SPI_MEM_CLKCNT_L 0x000000FF -#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V) << (SPI_MEM_CLKCNT_L_S)) -#define SPI_MEM_CLKCNT_L_V 0xFF -#define SPI_MEM_CLKCNT_L_S 0 +/*description: It must equal to the value of SPI_MEM_CLKCNT_N. .*/ +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 -#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x018) +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) /* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation.*/ -#define SPI_MEM_USR_COMMAND (BIT(31)) -#define SPI_MEM_USR_COMMAND_M (BIT(31)) -#define SPI_MEM_USR_COMMAND_V 0x1 -#define SPI_MEM_USR_COMMAND_S 31 +/*description: This bit enable the CMD phase of an operation..*/ +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (BIT(31)) +#define SPI_MEM_USR_COMMAND_V 0x1 +#define SPI_MEM_USR_COMMAND_S 31 /* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation.*/ -#define SPI_MEM_USR_ADDR (BIT(30)) -#define SPI_MEM_USR_ADDR_M (BIT(30)) -#define SPI_MEM_USR_ADDR_V 0x1 -#define SPI_MEM_USR_ADDR_S 30 +/*description: This bit enable the ADDR phase of an operation..*/ +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (BIT(30)) +#define SPI_MEM_USR_ADDR_V 0x1 +#define SPI_MEM_USR_ADDR_S 30 /* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: This bit enable the dummy phase of an operation.*/ -#define SPI_MEM_USR_DUMMY (BIT(29)) -#define SPI_MEM_USR_DUMMY_M (BIT(29)) -#define SPI_MEM_USR_DUMMY_V 0x1 -#define SPI_MEM_USR_DUMMY_S 29 +/*description: This bit enable the DUMMY phase of an operation..*/ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 +#define SPI_MEM_USR_DUMMY_S 29 /* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: This bit enable the read-data phase of an operation.*/ -#define SPI_MEM_USR_MISO (BIT(28)) -#define SPI_MEM_USR_MISO_M (BIT(28)) -#define SPI_MEM_USR_MISO_V 0x1 -#define SPI_MEM_USR_MISO_S 28 +/*description: This bit enable the DIN phase of a read-data operation..*/ +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (BIT(28)) +#define SPI_MEM_USR_MISO_V 0x1 +#define SPI_MEM_USR_MISO_S 28 /* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This bit enable the write-data phase of an operation.*/ -#define SPI_MEM_USR_MOSI (BIT(27)) -#define SPI_MEM_USR_MOSI_M (BIT(27)) -#define SPI_MEM_USR_MOSI_V 0x1 -#define SPI_MEM_USR_MOSI_S 27 +/*description: This bit enable the DOUT phase of an write-data operation..*/ +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (BIT(27)) +#define SPI_MEM_USR_MOSI_V 0x1 +#define SPI_MEM_USR_MOSI_S 27 /* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: spi clock is disable in dummy phase when the bit is enable.*/ -#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 -#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/*description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable..*/ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 /* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. - 1: enable 0: disable.*/ -#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) -#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 -#define SPI_MEM_USR_MOSI_HIGHPART_S 25 +/*description: DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG +. 1: enable 0: disable. .*/ +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 /* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. - 1: enable 0: disable.*/ -#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) -#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) -#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 -#define SPI_MEM_USR_MISO_HIGHPART_S 24 +/*description: DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. + 1: enable 0: disable. .*/ +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 +#define SPI_MEM_USR_MISO_HIGHPART_S 24 /* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: In the write operations address phase and read-data phase apply 4 signals.*/ -#define SPI_MEM_FWRITE_QIO (BIT(15)) -#define SPI_MEM_FWRITE_QIO_M (BIT(15)) -#define SPI_MEM_FWRITE_QIO_V 0x1 -#define SPI_MEM_FWRITE_QIO_S 15 +/*description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write ope +ration..*/ +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (BIT(15)) +#define SPI_MEM_FWRITE_QIO_V 0x1 +#define SPI_MEM_FWRITE_QIO_S 15 /* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the write operations address phase and read-data phase apply 2 signals.*/ -#define SPI_MEM_FWRITE_DIO (BIT(14)) -#define SPI_MEM_FWRITE_DIO_M (BIT(14)) -#define SPI_MEM_FWRITE_DIO_V 0x1 -#define SPI_MEM_FWRITE_DIO_S 14 +/*description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation..*/ +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (BIT(14)) +#define SPI_MEM_FWRITE_DIO_V 0x1 +#define SPI_MEM_FWRITE_DIO_S 14 /* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 4 signals*/ -#define SPI_MEM_FWRITE_QUAD (BIT(13)) -#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) -#define SPI_MEM_FWRITE_QUAD_V 0x1 -#define SPI_MEM_FWRITE_QUAD_S 13 +/*description: Set this bit to enable 4-bm in DOUT phase in SPI1 write operation..*/ +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_V 0x1 +#define SPI_MEM_FWRITE_QUAD_S 13 /* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 2 signals*/ -#define SPI_MEM_FWRITE_DUAL (BIT(12)) -#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) -#define SPI_MEM_FWRITE_DUAL_V 0x1 -#define SPI_MEM_FWRITE_DUAL_S 12 +/*description: Set this bit to enable 2-bm in DOUT phase in SPI1 write operation..*/ +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_V 0x1 +#define SPI_MEM_FWRITE_DUAL_S 12 /* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi - signal delay mode.*/ -#define SPI_MEM_CK_OUT_EDGE (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_V 0x1 -#define SPI_MEM_CK_OUT_EDGE_S 9 +/*description: This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mo +de 0~3 of SPI_CLK. .*/ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 /* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ -#define SPI_MEM_CS_SETUP (BIT(7)) -#define SPI_MEM_CS_SETUP_M (BIT(7)) -#define SPI_MEM_CS_SETUP_V 0x1 -#define SPI_MEM_CS_SETUP_S 7 +/*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 /* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ -#define SPI_MEM_CS_HOLD (BIT(6)) -#define SPI_MEM_CS_HOLD_M (BIT(6)) -#define SPI_MEM_CS_HOLD_V 0x1 -#define SPI_MEM_CS_HOLD_S 6 +/*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 -#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x01C) +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) /* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ -/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ -#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F -#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V) << (SPI_MEM_USR_ADDR_BITLEN_S)) -#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F -#define SPI_MEM_USR_ADDR_BITLEN_S 26 +/*description: The length in bits of ADDR phase. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F +#define SPI_MEM_USR_ADDR_BITLEN_S 26 /* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ -/*description: The length in spi_mem_clk cycles of dummy phase. The register - value shall be (cycle_num-1).*/ -#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V) << (SPI_MEM_USR_DUMMY_CYCLELEN_S)) -#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 +/*description: The SPI_CLK cycle length minus 1 of DUMMY phase..*/ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 -#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x020) +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) /* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ -/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ -#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F -#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V) << (SPI_MEM_USR_COMMAND_BITLEN_S)) -#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF -#define SPI_MEM_USR_COMMAND_BITLEN_S 28 +/*description: The length in bits of CMD phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 /* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: The value of command.*/ -#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V) << (SPI_MEM_USR_COMMAND_VALUE_S)) -#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF -#define SPI_MEM_USR_COMMAND_VALUE_S 0 +/*description: The value of user defined(USR) command..*/ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 -#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x024) -/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ -#define SPI_MEM_USR_MOSI_DBITLEN 0x000007FF -#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V) << (SPI_MEM_USR_MOSI_DBITLEN_S)) -#define SPI_MEM_USR_MOSI_DBITLEN_V 0x7FF -#define SPI_MEM_USR_MOSI_DBITLEN_S 0 +#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) +/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of DOUT phase. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF +#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 -#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x028) -/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ -#define SPI_MEM_USR_MISO_DBITLEN 0x000007FF -#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V) << (SPI_MEM_USR_MISO_DBITLEN_S)) -#define SPI_MEM_USR_MISO_DBITLEN_V 0x7FF -#define SPI_MEM_USR_MISO_DBITLEN_S 0 +#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) +/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of DIN phase. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF +#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MISO_DBITLEN_S 0 -#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x02C) +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) /* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ -/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode - bit.*/ -#define SPI_MEM_WB_MODE 0x000000FF -#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V) << (SPI_MEM_WB_MODE_S)) -#define SPI_MEM_WB_MODE_V 0xFF -#define SPI_MEM_WB_MODE_S 16 -/* SPI_MEM_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ -#define SPI_MEM_STATUS 0x0000FFFF -#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V) << (SPI_MEM_STATUS_S)) -#define SPI_MEM_STATUS_V 0xFFFF -#define SPI_MEM_STATUS_S 0 +/*description: Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE b +it..*/ +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 +/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit..*/ +#define SPI_MEM_STATUS 0x0000FFFF +#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) +#define SPI_MEM_STATUS_V 0xFFFF +#define SPI_MEM_STATUS_S 0 -#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x030) +#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x30) /* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The register are the higher 32bits in the 64 bits address mode.*/ -#define SPI_MEM_EXT_ADDR 0xFFFFFFFF -#define SPI_MEM_EXT_ADDR_M ((SPI_MEM_EXT_ADDR_V) << (SPI_MEM_EXT_ADDR_S)) -#define SPI_MEM_EXT_ADDR_V 0xFFFFFFFF -#define SPI_MEM_EXT_ADDR_S 0 +/*description: The register are the higher 32bits in the 64 bits address mode..*/ +#define SPI_MEM_EXT_ADDR 0xFFFFFFFF +#define SPI_MEM_EXT_ADDR_M ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S)) +#define SPI_MEM_EXT_ADDR_V 0xFFFFFFFF +#define SPI_MEM_EXT_ADDR_S 0 -#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x034) +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) /* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: reserved*/ -#define SPI_MEM_AUTO_PER (BIT(11)) -#define SPI_MEM_AUTO_PER_M (BIT(11)) -#define SPI_MEM_AUTO_PER_V 0x1 -#define SPI_MEM_AUTO_PER_S 11 +/*description: Set this bit to enable auto PER function. Hardware will sent out PER command if +PES command is sent..*/ +#define SPI_MEM_AUTO_PER (BIT(11)) +#define SPI_MEM_AUTO_PER_M (BIT(11)) +#define SPI_MEM_AUTO_PER_V 0x1 +#define SPI_MEM_AUTO_PER_S 11 /* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: spi cs line keep low when the bit is set.*/ -#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 -#define SPI_MEM_CS_KEEP_ACTIVE_S 10 +/*description: SPI_CS line keep low when the bit is set..*/ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 /* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ -#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_V 0x1 -#define SPI_MEM_CK_IDLE_EDGE_S 9 +/*description: 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is i +dle..*/ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 /* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: For SPI0 sram is connected to SUBPINs.*/ -#define SPI_MEM_SSUB_PIN (BIT(8)) -#define SPI_MEM_SSUB_PIN_M (BIT(8)) -#define SPI_MEM_SSUB_PIN_V 0x1 -#define SPI_MEM_SSUB_PIN_S 8 +/*description: Ext_RAM is connected to SPI SUBPIN bus..*/ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (BIT(8)) +#define SPI_MEM_SSUB_PIN_V 0x1 +#define SPI_MEM_SSUB_PIN_S 8 /* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: For SPI0 flash is connected to SUBPINs.*/ -#define SPI_MEM_FSUB_PIN (BIT(7)) -#define SPI_MEM_FSUB_PIN_M (BIT(7)) -#define SPI_MEM_FSUB_PIN_V 0x1 -#define SPI_MEM_FSUB_PIN_S 7 -/* SPI_MEM_CS_POL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ -/*description: In the master mode the bits are the polarity of spi cs line - the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/ -#define SPI_MEM_CS_POL 0x00000003 -#define SPI_MEM_CS_POL_M ((SPI_MEM_CS_POL_V) << (SPI_MEM_CS_POL_S)) -#define SPI_MEM_CS_POL_V 0x3 -#define SPI_MEM_CS_POL_S 5 +/*description: Flash is connected to SPI SUBPIN bus..*/ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (BIT(7)) +#define SPI_MEM_FSUB_PIN_V 0x1 +#define SPI_MEM_FSUB_PIN_S 7 /* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable the intterrupt of SPI transmitting done.*/ -#define SPI_MEM_TRANS_END_INT_ENA (BIT(4)) -#define SPI_MEM_TRANS_END_INT_ENA_M (BIT(4)) -#define SPI_MEM_TRANS_END_INT_ENA_V 0x1 -#define SPI_MEM_TRANS_END_INT_ENA_S 4 -/* SPI_MEM_TRANS_END : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the transimitting is done.*/ -#define SPI_MEM_TRANS_END (BIT(3)) -#define SPI_MEM_TRANS_END_M (BIT(3)) -#define SPI_MEM_TRANS_END_V 0x1 -#define SPI_MEM_TRANS_END_S 3 +/*description: The bit is used to enable the interrupt of SPI transmitting done..*/ +#define SPI_MEM_TRANS_END_INT_ENA (BIT(4)) +#define SPI_MEM_TRANS_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_TRANS_END_INT_ENA_V 0x1 +#define SPI_MEM_TRANS_END_INT_ENA_S 4 +/* SPI_MEM_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the transmitting is done..*/ +#define SPI_MEM_TRANS_END (BIT(3)) +#define SPI_MEM_TRANS_END_M (BIT(3)) +#define SPI_MEM_TRANS_END_V 0x1 +#define SPI_MEM_TRANS_END_S 3 /* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: SPI CS1 pin enable 1: disable CS1 0: spi_mem_cs1 signal is from/to CS1 pin*/ -#define SPI_MEM_CS1_DIS (BIT(1)) -#define SPI_MEM_CS1_DIS_M (BIT(1)) -#define SPI_MEM_CS1_DIS_V 0x1 -#define SPI_MEM_CS1_DIS_S 1 +/*description: Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) + connected to SPI_CS1 is inactive when SPI1 transfer starts..*/ +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (BIT(1)) +#define SPI_MEM_CS1_DIS_V 0x1 +#define SPI_MEM_CS1_DIS_S 1 /* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: SPI CS0 pin enable 1: disable CS0 0: spi_mem_cs0 signal is from/to CS0 pin*/ -#define SPI_MEM_CS0_DIS (BIT(0)) -#define SPI_MEM_CS0_DIS_M (BIT(0)) -#define SPI_MEM_CS0_DIS_V 0x1 -#define SPI_MEM_CS0_DIS_S 0 +/*description: Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) co +nnected to SPI_CS is inactive when SPI1 transfer starts..*/ +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (BIT(0)) +#define SPI_MEM_CS0_DIS_V 0x1 +#define SPI_MEM_CS0_DIS_S 0 -#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x038) -/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: For SPI1 the value of crc32.*/ -#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF -#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V) << (SPI_MEM_TX_CRC_DATA_S)) -#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF -#define SPI_MEM_TX_CRC_DATA_S 0 +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: For SPI1, the value of crc32..*/ +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 -#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x03C) +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) /* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: For SPI0 flash address phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_qio.*/ -#define SPI_MEM_FADDR_QUAD (BIT(8)) -#define SPI_MEM_FADDR_QUAD_M (BIT(8)) -#define SPI_MEM_FADDR_QUAD_V 0x1 -#define SPI_MEM_FADDR_QUAD_S 8 +/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phas +e..*/ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 +#define SPI_MEM_FADDR_QUAD_S 8 /* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_qio.*/ -#define SPI_MEM_FDOUT_QUAD (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_V 0x1 -#define SPI_MEM_FDOUT_QUAD_S 7 +/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phas +e..*/ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 /* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: For SPI0 flash din phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_qio.*/ -#define SPI_MEM_FDIN_QUAD (BIT(6)) -#define SPI_MEM_FDIN_QUAD_M (BIT(6)) -#define SPI_MEM_FDIN_QUAD_V 0x1 -#define SPI_MEM_FDIN_QUAD_S 6 +/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase +..*/ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 /* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: For SPI0 flash address phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_dio.*/ -#define SPI_MEM_FADDR_DUAL (BIT(5)) -#define SPI_MEM_FADDR_DUAL_M (BIT(5)) -#define SPI_MEM_FADDR_DUAL_V 0x1 -#define SPI_MEM_FADDR_DUAL_S 5 +/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phas +e..*/ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 /* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: For SPI0 flash dout phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_dio.*/ -#define SPI_MEM_FDOUT_DUAL (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_V 0x1 -#define SPI_MEM_FDOUT_DUAL_S 4 +/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phas +e..*/ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 /* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: For SPI0 flash din phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_dio.*/ -#define SPI_MEM_FDIN_DUAL (BIT(3)) -#define SPI_MEM_FDIN_DUAL_M (BIT(3)) -#define SPI_MEM_FDIN_DUAL_V 0x1 -#define SPI_MEM_FDIN_DUAL_S 3 +/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase +..*/ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 /* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ -#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 -#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/*description: 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardwa +re read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_M +EM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits..*/ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 /* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ -#define SPI_MEM_CACHE_USR_CMD_4BYTE (BIT(1)) -#define SPI_MEM_CACHE_USR_CMD_4BYTE_M (BIT(1)) -#define SPI_MEM_CACHE_USR_CMD_4BYTE_V 0x1 -#define SPI_MEM_CACHE_USR_CMD_4BYTE_S 1 +/*description: Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_ +USR_ADDR_BITLEN should be 31..*/ +#define SPI_MEM_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_CMD_4BYTE_S 1 /* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ -#define SPI_MEM_CACHE_REQ_EN (BIT(0)) -#define SPI_MEM_CACHE_REQ_EN_M (BIT(0)) -#define SPI_MEM_CACHE_REQ_EN_V 0x1 -#define SPI_MEM_CACHE_REQ_EN_S 0 +/*description: Set this bit to enable Cache's access and SPI0's transfer..*/ +#define SPI_MEM_CACHE_REQ_EN (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_M (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_V 0x1 +#define SPI_MEM_CACHE_REQ_EN_S 0 -#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x040) +#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) /* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */ -/*description: For SPI0 In the sram mode it is the length in bits of write - dummy phase. The register value shall be (bit_num-1).*/ -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V) << (SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 +/*description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase i +n write data transfer..*/ +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 /* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: reserved*/ -#define SPI_MEM_SRAM_OCT (BIT(21)) -#define SPI_MEM_SRAM_OCT_M (BIT(21)) -#define SPI_MEM_SRAM_OCT_V 0x1 -#define SPI_MEM_SRAM_OCT_S 21 +/*description: Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer..*/ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 /* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode cache write sram for user define command*/ -#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 -#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 +/*description: 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALU +E. 0: The value is 0x3..*/ +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 /* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */ -/*description: For SPI0 In the sram mode it is the length in bits of address - phase. The register value shall be (bit_num-1).*/ -#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F -#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V) << (SPI_MEM_SRAM_ADDR_BITLEN_S)) -#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F -#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 +/*description: When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The regis +ter value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 /* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */ -/*description: For SPI0 In the sram mode it is the length in bits of read - dummy phase. The register value shall be (bit_num-1).*/ -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V) << (SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 +/*description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase i +n read data transfer..*/ +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 /* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/ -#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 -#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 +/*description: 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE +. 0: The value is 0x2..*/ +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 /* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode it is the enable bit of dummy - phase for read operations.*/ -#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 -#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operat +ions..*/ +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 /* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode it is the enable bit of dummy - phase for write operations.*/ -#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 -#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write opera +tions..*/ +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 /* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ -#define SPI_MEM_USR_SRAM_QIO (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_V 0x1 -#define SPI_MEM_USR_SRAM_QIO_S 2 +/*description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer..*/ +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_V 0x1 +#define SPI_MEM_USR_SRAM_QIO_S 2 /* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ -#define SPI_MEM_USR_SRAM_DIO (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_V 0x1 -#define SPI_MEM_USR_SRAM_DIO_S 1 +/*description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer..*/ +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_V 0x1 +#define SPI_MEM_USR_SRAM_DIO_S 1 /* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode cache read flash with 4 bytes - command 1: enable 0:disable.*/ -#define SPI_MEM_CACHE_USR_SCMD_4BYTE (BIT(0)) -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M (BIT(0)) -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V 0x1 -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0 +/*description: Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_ +MEM_SRAM_ADDR_BITLEN should be 31..*/ +#define SPI_MEM_CACHE_USR_SCMD_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M (BIT(0)) +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0 -#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x044) +#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) /* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: In the dummy phase the signal level of spi is output by the spi controller.*/ -#define SPI_MEM_SDUMMY_OUT (BIT(22)) -#define SPI_MEM_SDUMMY_OUT_M (BIT(22)) -#define SPI_MEM_SDUMMY_OUT_V 0x1 -#define SPI_MEM_SDUMMY_OUT_S 22 +/*description: When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is + output by the SPI0 controller..*/ +#define SPI_MEM_SDUMMY_OUT (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_M (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_V 0x1 +#define SPI_MEM_SDUMMY_OUT_S 22 /* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/ -#define SPI_MEM_SCMD_OCT (BIT(21)) -#define SPI_MEM_SCMD_OCT_M (BIT(21)) -#define SPI_MEM_SCMD_OCT_V 0x1 -#define SPI_MEM_SCMD_OCT_S 21 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase..*/ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 /* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/ -#define SPI_MEM_SADDR_OCT (BIT(20)) -#define SPI_MEM_SADDR_OCT_M (BIT(20)) -#define SPI_MEM_SADDR_OCT_V 0x1 -#define SPI_MEM_SADDR_OCT_S 20 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase..*/ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 /* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/ -#define SPI_MEM_SDOUT_OCT (BIT(19)) -#define SPI_MEM_SDOUT_OCT_M (BIT(19)) -#define SPI_MEM_SDOUT_OCT_V 0x1 -#define SPI_MEM_SDOUT_OCT_S 19 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase..*/ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 /* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/ -#define SPI_MEM_SDIN_OCT (BIT(18)) -#define SPI_MEM_SDIN_OCT_M (BIT(18)) -#define SPI_MEM_SDIN_OCT_V 0x1 -#define SPI_MEM_SDIN_OCT_S 18 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase..*/ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 /* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_usr_sram_qio.*/ -#define SPI_MEM_SCMD_QUAD (BIT(17)) -#define SPI_MEM_SCMD_QUAD_M (BIT(17)) -#define SPI_MEM_SCMD_QUAD_V 0x1 -#define SPI_MEM_SCMD_QUAD_S 17 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase..*/ +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (BIT(17)) +#define SPI_MEM_SCMD_QUAD_V 0x1 +#define SPI_MEM_SCMD_QUAD_S 17 /* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_usr_sram_qio.*/ -#define SPI_MEM_SADDR_QUAD (BIT(16)) -#define SPI_MEM_SADDR_QUAD_M (BIT(16)) -#define SPI_MEM_SADDR_QUAD_V 0x1 -#define SPI_MEM_SADDR_QUAD_S 16 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase..*/ +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (BIT(16)) +#define SPI_MEM_SADDR_QUAD_V 0x1 +#define SPI_MEM_SADDR_QUAD_S 16 /* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_usr_sram_qio.*/ -#define SPI_MEM_SDOUT_QUAD (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_V 0x1 -#define SPI_MEM_SDOUT_QUAD_S 15 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase..*/ +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_V 0x1 +#define SPI_MEM_SDOUT_QUAD_S 15 /* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_usr_sram_qio.*/ -#define SPI_MEM_SDIN_QUAD (BIT(14)) -#define SPI_MEM_SDIN_QUAD_M (BIT(14)) -#define SPI_MEM_SDIN_QUAD_V 0x1 -#define SPI_MEM_SDIN_QUAD_S 14 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase..*/ +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (BIT(14)) +#define SPI_MEM_SDIN_QUAD_V 0x1 +#define SPI_MEM_SDIN_QUAD_S 14 /* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_usr_sram_dio.*/ -#define SPI_MEM_SCMD_DUAL (BIT(13)) -#define SPI_MEM_SCMD_DUAL_M (BIT(13)) -#define SPI_MEM_SCMD_DUAL_V 0x1 -#define SPI_MEM_SCMD_DUAL_S 13 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase..*/ +#define SPI_MEM_SCMD_DUAL (BIT(13)) +#define SPI_MEM_SCMD_DUAL_M (BIT(13)) +#define SPI_MEM_SCMD_DUAL_V 0x1 +#define SPI_MEM_SCMD_DUAL_S 13 /* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_usr_sram_dio.*/ -#define SPI_MEM_SADDR_DUAL (BIT(12)) -#define SPI_MEM_SADDR_DUAL_M (BIT(12)) -#define SPI_MEM_SADDR_DUAL_V 0x1 -#define SPI_MEM_SADDR_DUAL_S 12 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase..*/ +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (BIT(12)) +#define SPI_MEM_SADDR_DUAL_V 0x1 +#define SPI_MEM_SADDR_DUAL_S 12 /* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_usr_sram_dio.*/ -#define SPI_MEM_SDOUT_DUAL (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_V 0x1 -#define SPI_MEM_SDOUT_DUAL_S 11 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase..*/ +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_V 0x1 +#define SPI_MEM_SDOUT_DUAL_S 11 /* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_usr_sram_dio.*/ -#define SPI_MEM_SDIN_DUAL (BIT(10)) -#define SPI_MEM_SDIN_DUAL_M (BIT(10)) -#define SPI_MEM_SDIN_DUAL_V 0x1 -#define SPI_MEM_SDIN_DUAL_S 10 +/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase..*/ +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (BIT(10)) +#define SPI_MEM_SDIN_DUAL_V 0x1 +#define SPI_MEM_SDIN_DUAL_S 10 /* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */ -/*description: Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode - bit.*/ -#define SPI_MEM_SWB_MODE 0x000000FF -#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V) << (SPI_MEM_SWB_MODE_S)) -#define SPI_MEM_SWB_MODE_V 0xFF -#define SPI_MEM_SWB_MODE_S 2 +/*description: Mode bits when SPI0 accesses to Ext_RAM..*/ +#define SPI_MEM_SWB_MODE 0x000000FF +#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) +#define SPI_MEM_SWB_MODE_V 0xFF +#define SPI_MEM_SWB_MODE_S 2 /* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ -#define SPI_MEM_SCLK_MODE 0x00000003 -#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V) << (SPI_MEM_SCLK_MODE_S)) -#define SPI_MEM_SCLK_MODE_V 0x3 -#define SPI_MEM_SCLK_MODE_S 0 +/*description: SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inac +tive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two + cycles after CS inactive 3: SPI_CLK is always on..*/ +#define SPI_MEM_SCLK_MODE 0x00000003 +#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) +#define SPI_MEM_SCLK_MODE_V 0x3 +#define SPI_MEM_SCLK_MODE_S 0 -#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x048) +#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) /* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the length in bits of - command phase for sram. The register value shall be (bit_num-1).*/ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V) << (SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/*description: When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register val +ue shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 /* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the read command value - of command phase for sram.*/ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V) << (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 +/*description: When SPI0 reads Ext_RAM, it is the command value of CMD phase..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 -#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x04C) +#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) /* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the in bits of command - phase for sram. The register value shall be (bit_num-1).*/ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V) << (SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/*description: When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register va +lue shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 /* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the write command value - of command phase for sram.*/ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V) << (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 +/*description: When SPI0 writes Ext_RAM, it is the command value of CMD phase..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 -#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x050) +#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) /* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: - spi_mem_clk is divided from system clock.*/ -#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 -#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 +/*description: When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MS +PI_CORE_CLK..*/ +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 /* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ -/*description: For SPI0 sram interface it is the divider of spi_mem_clk. So - spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ -#define SPI_MEM_SCLKCNT_N 0x000000FF -#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V) << (SPI_MEM_SCLKCNT_N_S)) -#define SPI_MEM_SCLKCNT_N_V 0xFF -#define SPI_MEM_SCLKCNT_N_S 16 +/*description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1).*/ +#define SPI_MEM_SCLKCNT_N 0x000000FF +#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) +#define SPI_MEM_SCLKCNT_N_V 0xFF +#define SPI_MEM_SCLKCNT_N_S 16 /* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ -#define SPI_MEM_SCLKCNT_H 0x000000FF -#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V) << (SPI_MEM_SCLKCNT_H_S)) -#define SPI_MEM_SCLKCNT_H_V 0xFF -#define SPI_MEM_SCLKCNT_H_S 8 +/*description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1)..*/ +#define SPI_MEM_SCLKCNT_H 0x000000FF +#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) +#define SPI_MEM_SCLKCNT_H_V 0xFF +#define SPI_MEM_SCLKCNT_H_S 8 /* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ -/*description: For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/ -#define SPI_MEM_SCLKCNT_L 0x000000FF -#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V) << (SPI_MEM_SCLKCNT_L_S)) -#define SPI_MEM_SCLKCNT_L_V 0xFF -#define SPI_MEM_SCLKCNT_L_S 0 +/*description: It must equal to the value of SPI_MEM_SCLKCNT_N. .*/ +#define SPI_MEM_SCLKCNT_L 0x000000FF +#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) +#define SPI_MEM_SCLKCNT_L_V 0xFF +#define SPI_MEM_SCLKCNT_L_S 0 -#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x054) +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) /* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The status of spi state machine. 0: idle state 1: preparation - state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ -#define SPI_MEM_ST 0x00000007 -#define SPI_MEM_ST_M ((SPI_MEM_ST_V) << (SPI_MEM_ST_S)) -#define SPI_MEM_ST_V 0x7 -#define SPI_MEM_ST_S 0 +/*description: The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP +), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DI +N), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE)..*/ +#define SPI_MEM_ST 0x00000007 +#define SPI_MEM_ST_M ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S)) +#define SPI_MEM_ST_V 0x7 +#define SPI_MEM_ST_S 0 -#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x058) -/* SPI_MEM_BUF0 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF0 0xFFFFFFFF -#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V) << (SPI_MEM_BUF0_S)) -#define SPI_MEM_BUF0_V 0xFFFFFFFF -#define SPI_MEM_BUF0_S 0 +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) +/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF0 0xFFFFFFFF +#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) +#define SPI_MEM_BUF0_V 0xFFFFFFFF +#define SPI_MEM_BUF0_S 0 -#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x05C) -/* SPI_MEM_BUF1 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF1 0xFFFFFFFF -#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V) << (SPI_MEM_BUF1_S)) -#define SPI_MEM_BUF1_V 0xFFFFFFFF -#define SPI_MEM_BUF1_S 0 +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) +/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF1 0xFFFFFFFF +#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) +#define SPI_MEM_BUF1_V 0xFFFFFFFF +#define SPI_MEM_BUF1_S 0 -#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x060) -/* SPI_MEM_BUF2 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF2 0xFFFFFFFF -#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V) << (SPI_MEM_BUF2_S)) -#define SPI_MEM_BUF2_V 0xFFFFFFFF -#define SPI_MEM_BUF2_S 0 +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) +/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF2 0xFFFFFFFF +#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) +#define SPI_MEM_BUF2_V 0xFFFFFFFF +#define SPI_MEM_BUF2_S 0 -#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x064) -/* SPI_MEM_BUF3 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF3 0xFFFFFFFF -#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V) << (SPI_MEM_BUF3_S)) -#define SPI_MEM_BUF3_V 0xFFFFFFFF -#define SPI_MEM_BUF3_S 0 +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) +/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF3 0xFFFFFFFF +#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) +#define SPI_MEM_BUF3_V 0xFFFFFFFF +#define SPI_MEM_BUF3_S 0 -#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x068) -/* SPI_MEM_BUF4 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF4 0xFFFFFFFF -#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V) << (SPI_MEM_BUF4_S)) -#define SPI_MEM_BUF4_V 0xFFFFFFFF -#define SPI_MEM_BUF4_S 0 +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) +/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF4 0xFFFFFFFF +#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) +#define SPI_MEM_BUF4_V 0xFFFFFFFF +#define SPI_MEM_BUF4_S 0 -#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x06C) -/* SPI_MEM_BUF5 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF5 0xFFFFFFFF -#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V) << (SPI_MEM_BUF5_S)) -#define SPI_MEM_BUF5_V 0xFFFFFFFF -#define SPI_MEM_BUF5_S 0 +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) +/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF5 0xFFFFFFFF +#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) +#define SPI_MEM_BUF5_V 0xFFFFFFFF +#define SPI_MEM_BUF5_S 0 -#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x070) -/* SPI_MEM_BUF6 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF6 0xFFFFFFFF -#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V) << (SPI_MEM_BUF6_S)) -#define SPI_MEM_BUF6_V 0xFFFFFFFF -#define SPI_MEM_BUF6_S 0 +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) +/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF6 0xFFFFFFFF +#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) +#define SPI_MEM_BUF6_V 0xFFFFFFFF +#define SPI_MEM_BUF6_S 0 -#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x074) -/* SPI_MEM_BUF7 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF7 0xFFFFFFFF -#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V) << (SPI_MEM_BUF7_S)) -#define SPI_MEM_BUF7_V 0xFFFFFFFF -#define SPI_MEM_BUF7_S 0 +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) +/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF7 0xFFFFFFFF +#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) +#define SPI_MEM_BUF7_V 0xFFFFFFFF +#define SPI_MEM_BUF7_S 0 -#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x078) -/* SPI_MEM_BUF8 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF8 0xFFFFFFFF -#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V) << (SPI_MEM_BUF8_S)) -#define SPI_MEM_BUF8_V 0xFFFFFFFF -#define SPI_MEM_BUF8_S 0 +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) +/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF8 0xFFFFFFFF +#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) +#define SPI_MEM_BUF8_V 0xFFFFFFFF +#define SPI_MEM_BUF8_S 0 -#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x07C) -/* SPI_MEM_BUF9 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF9 0xFFFFFFFF -#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V) << (SPI_MEM_BUF9_S)) -#define SPI_MEM_BUF9_V 0xFFFFFFFF -#define SPI_MEM_BUF9_S 0 +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) +/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF9 0xFFFFFFFF +#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) +#define SPI_MEM_BUF9_V 0xFFFFFFFF +#define SPI_MEM_BUF9_S 0 -#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x080) -/* SPI_MEM_BUF10 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF10 0xFFFFFFFF -#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V) << (SPI_MEM_BUF10_S)) -#define SPI_MEM_BUF10_V 0xFFFFFFFF -#define SPI_MEM_BUF10_S 0 +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) +/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF10 0xFFFFFFFF +#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) +#define SPI_MEM_BUF10_V 0xFFFFFFFF +#define SPI_MEM_BUF10_S 0 -#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x084) -/* SPI_MEM_BUF11 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF11 0xFFFFFFFF -#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V) << (SPI_MEM_BUF11_S)) -#define SPI_MEM_BUF11_V 0xFFFFFFFF -#define SPI_MEM_BUF11_S 0 +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) +/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF11 0xFFFFFFFF +#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) +#define SPI_MEM_BUF11_V 0xFFFFFFFF +#define SPI_MEM_BUF11_S 0 -#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x088) -/* SPI_MEM_BUF12 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF12 0xFFFFFFFF -#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V) << (SPI_MEM_BUF12_S)) -#define SPI_MEM_BUF12_V 0xFFFFFFFF -#define SPI_MEM_BUF12_S 0 +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) +/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF12 0xFFFFFFFF +#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) +#define SPI_MEM_BUF12_V 0xFFFFFFFF +#define SPI_MEM_BUF12_S 0 -#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x08C) -/* SPI_MEM_BUF13 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF13 0xFFFFFFFF -#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V) << (SPI_MEM_BUF13_S)) -#define SPI_MEM_BUF13_V 0xFFFFFFFF -#define SPI_MEM_BUF13_S 0 +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) +/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF13 0xFFFFFFFF +#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) +#define SPI_MEM_BUF13_V 0xFFFFFFFF +#define SPI_MEM_BUF13_S 0 -#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x090) -/* SPI_MEM_BUF14 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF14 0xFFFFFFFF -#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V) << (SPI_MEM_BUF14_S)) -#define SPI_MEM_BUF14_V 0xFFFFFFFF -#define SPI_MEM_BUF14_S 0 +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) +/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF14 0xFFFFFFFF +#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) +#define SPI_MEM_BUF14_V 0xFFFFFFFF +#define SPI_MEM_BUF14_S 0 -#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x094) -/* SPI_MEM_BUF15 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_MEM_BUF15 0xFFFFFFFF -#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V) << (SPI_MEM_BUF15_S)) -#define SPI_MEM_BUF15_V 0xFFFFFFFF -#define SPI_MEM_BUF15_S 0 +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) +/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF15 0xFFFFFFFF +#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) +#define SPI_MEM_BUF15_V 0xFFFFFFFF +#define SPI_MEM_BUF15_S 0 -#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x098) -/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: The dummy cycle length when auto wait flash idle*/ -#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x000000FF -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V) << (SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0xFF -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) +/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: The dummy cycle length when auto wait flash idle .*/ +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 /* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */ -/*description: The command to auto wait idle*/ -#define SPI_MEM_WAITI_CMD 0x000000FF -#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V) << (SPI_MEM_WAITI_CMD_S)) -#define SPI_MEM_WAITI_CMD_V 0xFF -#define SPI_MEM_WAITI_CMD_S 2 +/*description: The command to auto wait idle.*/ +#define SPI_MEM_WAITI_CMD 0x000000FF +#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) +#define SPI_MEM_WAITI_CMD_V 0xFF +#define SPI_MEM_WAITI_CMD_S 2 /* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The dummy phase enable when auto wait flash idle*/ -#define SPI_MEM_WAITI_DUMMY (BIT(1)) -#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) -#define SPI_MEM_WAITI_DUMMY_V 0x1 -#define SPI_MEM_WAITI_DUMMY_S 1 +/*description: The dummy phase enable when auto wait flash idle.*/ +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_V 0x1 +#define SPI_MEM_WAITI_DUMMY_S 1 /* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: auto-waiting flash idle operation when program flash or erase - flash. 1: enable 0: disable.*/ -#define SPI_MEM_WAITI_EN (BIT(0)) -#define SPI_MEM_WAITI_EN_M (BIT(0)) -#define SPI_MEM_WAITI_EN_V 0x1 -#define SPI_MEM_WAITI_EN_S 0 +/*description: Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/P +ES command is sent..*/ +#define SPI_MEM_WAITI_EN (BIT(0)) +#define SPI_MEM_WAITI_EN_M (BIT(0)) +#define SPI_MEM_WAITI_EN_V 0x1 +#define SPI_MEM_WAITI_EN_S 0 -#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x09C) -/* SPI_MEM_FLASH_PES : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program erase suspend bit program erase suspend operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_PES (BIT(1)) -#define SPI_MEM_FLASH_PES_M (BIT(1)) -#define SPI_MEM_FLASH_PES_V 0x1 -#define SPI_MEM_FLASH_PES_S 1 -/* SPI_MEM_FLASH_PER : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: program erase resume bit program erase suspend operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_MEM_FLASH_PER (BIT(0)) -#define SPI_MEM_FLASH_PER_M (BIT(0)) -#define SPI_MEM_FLASH_PER_V 0x1 -#define SPI_MEM_FLASH_PER_S 0 +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) +/* SPI_MEM_PESR_IDLE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate..*/ +#define SPI_MEM_PESR_IDLE_EN (BIT(5)) +#define SPI_MEM_PESR_IDLE_EN_M (BIT(5)) +#define SPI_MEM_PESR_IDLE_EN_V 0x1 +#define SPI_MEM_PESR_IDLE_EN_S 5 +/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable PES transfer trigger PES transfer option..*/ +#define SPI_MEM_PES_PER_EN (BIT(4)) +#define SPI_MEM_PES_PER_EN_M (BIT(4)) +#define SPI_MEM_PES_PER_EN_V 0x1 +#define SPI_MEM_PES_PER_EN_S 4 +/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to add delay time after program erase suspend(PES) command is sent..*/ +#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 +/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to add delay time after program erase resume(PER) is sent..*/ +#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 +/* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program erase suspend bit, program erase suspend operation will be triggered whe +n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +isable. .*/ +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (BIT(1)) +#define SPI_MEM_FLASH_PES_V 0x1 +#define SPI_MEM_FLASH_PES_S 1 +/* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: program erase resume bit, program erase suspend operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: di +sable. .*/ +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (BIT(0)) +#define SPI_MEM_FLASH_PER_V 0x1 +#define SPI_MEM_FLASH_PER_S 0 -#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A0) +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) /* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */ -/*description: Program/Erase suspend command.*/ -#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF -#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V) << (SPI_MEM_FLASH_PES_COMMAND_S)) -#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF -#define SPI_MEM_FLASH_PES_COMMAND_S 9 +/*description: Program/Erase suspend command value..*/ +#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF +#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) +#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF +#define SPI_MEM_FLASH_PES_COMMAND_S 9 /* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */ -/*description: Program/Erase resume command.*/ -#define SPI_MEM_FLASH_PER_COMMAND 0x000000FF -#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V) << (SPI_MEM_FLASH_PER_COMMAND_S)) -#define SPI_MEM_FLASH_PER_COMMAND_V 0xFF -#define SPI_MEM_FLASH_PER_COMMAND_S 1 +/*description: Program/Erase resume command value..*/ +#define SPI_MEM_FLASH_PER_COMMAND 0x000000FF +#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) +#define SPI_MEM_FLASH_PER_COMMAND_V 0xFF +#define SPI_MEM_FLASH_PER_COMMAND_S 1 /* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Auto-suspending enable*/ -#define SPI_MEM_FLASH_PES_EN (BIT(0)) -#define SPI_MEM_FLASH_PES_EN_M (BIT(0)) -#define SPI_MEM_FLASH_PES_EN_V 0x1 -#define SPI_MEM_FLASH_PES_EN_S 0 +/*description: Set this bit to enable auto-suspend function..*/ +#define SPI_MEM_FLASH_PES_EN (BIT(0)) +#define SPI_MEM_FLASH_PES_EN_M (BIT(0)) +#define SPI_MEM_FLASH_PES_EN_V 0x1 +#define SPI_MEM_FLASH_PES_EN_S 0 -#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A4) -/* SPI_MEM_FLASH_SUS : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The status of flash suspend only used in SPI1.*/ -#define SPI_MEM_FLASH_SUS (BIT(0)) -#define SPI_MEM_FLASH_SUS_M (BIT(0)) -#define SPI_MEM_FLASH_SUS_V 0x1 -#define SPI_MEM_FLASH_SUS_S 0 +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) +/* SPI_MEM_FLASH_PES_DLY_256 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/ +#define SPI_MEM_FLASH_PES_DLY_256 (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_256_M (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_256_V 0x1 +#define SPI_MEM_FLASH_PES_DLY_256_S 6 +/* SPI_MEM_FLASH_PER_DLY_256 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/ +#define SPI_MEM_FLASH_PER_DLY_256 (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_256_M (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_256_V 0x1 +#define SPI_MEM_FLASH_PER_DLY_256_S 5 +/* SPI_MEM_FLASH_DP_DLY_256 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP com +mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles +after DP command is sent..*/ +#define SPI_MEM_FLASH_DP_DLY_256 (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_256_M (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_256_V 0x1 +#define SPI_MEM_FLASH_DP_DLY_256_S 4 +/* SPI_MEM_FLASH_RES_DLY_256 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after RES command is sent..*/ +#define SPI_MEM_FLASH_RES_DLY_256 (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_256_M (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_256_V 0x1 +#define SPI_MEM_FLASH_RES_DLY_256_S 3 +/* SPI_MEM_FLASH_HPM_DLY_256 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after HPM command is sent..*/ +#define SPI_MEM_FLASH_HPM_DLY_256 (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_256_M (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_256_V 0x1 +#define SPI_MEM_FLASH_HPM_DLY_256_S 2 +/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The status of flash suspend. This bit is set when PES command is sent, and clear +ed when PER is sent. Only used in SPI1..*/ +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (BIT(0)) +#define SPI_MEM_FLASH_SUS_V 0x1 +#define SPI_MEM_FLASH_SUS_S 0 -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A8) +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xA8) /* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ -/*description: add extra dummy spi clock cycle length for spi clock calibration.*/ -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V) << (SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 acc +esses to flash. Active when SPI_MEM_TIMING_CALI bit is set..*/ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 /* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable timing auto-calibration for all reading operations.*/ -#define SPI_MEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_TIMING_CALI_M (BIT(1)) -#define SPI_MEM_TIMING_CALI_V 0x1 -#define SPI_MEM_TIMING_CALI_S 1 +/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio +ns..*/ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 /* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable timing adjust clock for all reading operations.*/ -#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_V 0x1 -#define SPI_MEM_TIMING_CLK_ENA_S 0 +/*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ +als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 -#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0AC) -/* SPI_MEM_DINS_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_MEM_DINS_MODE 0x00000003 -#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V) << (SPI_MEM_DINS_MODE_S)) -#define SPI_MEM_DINS_MODE_V 0x3 -#define SPI_MEM_DINS_MODE_S 16 -/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_MEM_DIN7_MODE 0x00000003 -#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V) << (SPI_MEM_DIN7_MODE_S)) -#define SPI_MEM_DIN7_MODE_V 0x3 -#define SPI_MEM_DIN7_MODE_S 14 -/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_MEM_DIN6_MODE 0x00000003 -#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V) << (SPI_MEM_DIN6_MODE_S)) -#define SPI_MEM_DIN6_MODE_V 0x3 -#define SPI_MEM_DIN6_MODE_S 12 -/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_MEM_DIN5_MODE 0x00000003 -#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V) << (SPI_MEM_DIN5_MODE_S)) -#define SPI_MEM_DIN5_MODE_V 0x3 -#define SPI_MEM_DIN5_MODE_S 10 -/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_MEM_DIN4_MODE 0x00000003 -#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V) << (SPI_MEM_DIN4_MODE_S)) -#define SPI_MEM_DIN4_MODE_V 0x3 -#define SPI_MEM_DIN4_MODE_S 8 -/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_DIN3_MODE 0x00000003 -#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V) << (SPI_MEM_DIN3_MODE_S)) -#define SPI_MEM_DIN3_MODE_V 0x3 -#define SPI_MEM_DIN3_MODE_S 6 -/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_DIN2_MODE 0x00000003 -#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V) << (SPI_MEM_DIN2_MODE_S)) -#define SPI_MEM_DIN2_MODE_V 0x3 -#define SPI_MEM_DIN2_MODE_S 4 -/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_DIN1_MODE 0x00000003 -#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V) << (SPI_MEM_DIN1_MODE_S)) -#define SPI_MEM_DIN1_MODE_V 0x3 -#define SPI_MEM_DIN1_MODE_S 2 -/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_DIN0_MODE 0x00000003 -#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V) << (SPI_MEM_DIN0_MODE_S)) -#define SPI_MEM_DIN0_MODE_V 0x3 -#define SPI_MEM_DIN0_MODE_S 0 +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xAC) +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles +at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK + positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M +EM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negat +ive edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one + cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles +at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DINS_MODE 0x00000007 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x7 +#define SPI_MEM_DINS_MODE_S 24 +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles + at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC +LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI +_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne +gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and + one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy +cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DIN7_MODE 0x00000007 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x7 +#define SPI_MEM_DIN7_MODE_S 21 +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles + at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC +LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI +_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne +gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and + one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy +cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DIN6_MODE 0x00000007 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x7 +#define SPI_MEM_DIN6_MODE_S 18 +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles + at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC +LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI +_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne +gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and + one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy +cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DIN5_MODE 0x00000007 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x7 +#define SPI_MEM_DIN5_MODE_S 15 +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles + at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC +LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI +_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne +gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and + one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy +cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DIN4_MODE 0x00000007 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x7 +#define SPI_MEM_DIN4_MODE_S 12 +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles +at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL +K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_ +MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg +ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and +one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc +les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DIN3_MODE 0x00000007 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x7 +#define SPI_MEM_DIN3_MODE_S 9 +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles +at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL +K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_ +MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg +ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and +one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc +les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DIN2_MODE 0x00000007 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x7 +#define SPI_MEM_DIN2_MODE_S 6 +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a +t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK + positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M +EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega +tive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o +ne cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycl +es at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DIN1_MODE 0x00000007 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x7 +#define SPI_MEM_DIN1_MODE_S 3 +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a +t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK + positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M +EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega +tive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o +ne cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycl +es at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_DIN0_MODE 0x00000007 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x7 +#define SPI_MEM_DIN0_MODE_S 0 -#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B0) +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xB0) /* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DINS_NUM 0x00000003 -#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V) << (SPI_MEM_DINS_NUM_S)) -#define SPI_MEM_DINS_NUM_V 0x3 -#define SPI_MEM_DINS_NUM_S 16 +/*description: SPI_DQS input delay number..*/ +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 +#define SPI_MEM_DINS_NUM_S 16 /* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DIN7_NUM 0x00000003 -#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V) << (SPI_MEM_DIN7_NUM_S)) -#define SPI_MEM_DIN7_NUM_V 0x3 -#define SPI_MEM_DIN7_NUM_S 14 +/*description: SPI_IO7 input delay number..*/ +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 /* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DIN6_NUM 0x00000003 -#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V) << (SPI_MEM_DIN6_NUM_S)) -#define SPI_MEM_DIN6_NUM_V 0x3 -#define SPI_MEM_DIN6_NUM_S 12 +/*description: SPI_IO6 input delay number..*/ +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 /* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DIN5_NUM 0x00000003 -#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V) << (SPI_MEM_DIN5_NUM_S)) -#define SPI_MEM_DIN5_NUM_V 0x3 -#define SPI_MEM_DIN5_NUM_S 10 +/*description: SPI_IO5 input delay number..*/ +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 /* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DIN4_NUM 0x00000003 -#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V) << (SPI_MEM_DIN4_NUM_S)) -#define SPI_MEM_DIN4_NUM_V 0x3 -#define SPI_MEM_DIN4_NUM_S 8 +/*description: SPI_IO4 input delay number..*/ +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 /* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DIN3_NUM 0x00000003 -#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V) << (SPI_MEM_DIN3_NUM_S)) -#define SPI_MEM_DIN3_NUM_V 0x3 -#define SPI_MEM_DIN3_NUM_S 6 +/*description: SPI_HD input delay number..*/ +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 /* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DIN2_NUM 0x00000003 -#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V) << (SPI_MEM_DIN2_NUM_S)) -#define SPI_MEM_DIN2_NUM_V 0x3 -#define SPI_MEM_DIN2_NUM_S 4 +/*description: SPI_WP input delay number..*/ +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 /* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DIN1_NUM 0x00000003 -#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V) << (SPI_MEM_DIN1_NUM_S)) -#define SPI_MEM_DIN1_NUM_V 0x3 -#define SPI_MEM_DIN1_NUM_S 2 +/*description: SPI_Q input delay number..*/ +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 /* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DIN0_NUM 0x00000003 -#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V) << (SPI_MEM_DIN0_NUM_S)) -#define SPI_MEM_DIN0_NUM_V 0x3 -#define SPI_MEM_DIN0_NUM_S 0 +/*description: SPI_D input delay number..*/ +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 -#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B4) +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xB4) /* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_MEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_DOUTS_MODE_M (BIT(8)) -#define SPI_MEM_DOUTS_MODE_V 0x1 -#define SPI_MEM_DOUTS_MODE_S 8 +/*description: SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_DOUTS_MODE_S 8 /* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_MEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_DOUT7_MODE_M (BIT(7)) -#define SPI_MEM_DOUT7_MODE_V 0x1 -#define SPI_MEM_DOUT7_MODE_S 7 +/*description: SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_DOUT7_MODE_S 7 /* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_MEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_DOUT6_MODE_M (BIT(6)) -#define SPI_MEM_DOUT6_MODE_V 0x1 -#define SPI_MEM_DOUT6_MODE_S 6 +/*description: SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_DOUT6_MODE_S 6 /* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_MEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_DOUT5_MODE_M (BIT(5)) -#define SPI_MEM_DOUT5_MODE_V 0x1 -#define SPI_MEM_DOUT5_MODE_S 5 +/*description: SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_DOUT5_MODE_S 5 /* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_MEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_DOUT4_MODE_M (BIT(4)) -#define SPI_MEM_DOUT4_MODE_V 0x1 -#define SPI_MEM_DOUT4_MODE_S 4 +/*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_DOUT4_MODE_S 4 /* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_DOUT3_MODE_M (BIT(3)) -#define SPI_MEM_DOUT3_MODE_V 0x1 -#define SPI_MEM_DOUT3_MODE_S 3 +/*description: SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat +ive edge..*/ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_DOUT3_MODE_S 3 /* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_DOUT2_MODE_M (BIT(2)) -#define SPI_MEM_DOUT2_MODE_V 0x1 -#define SPI_MEM_DOUT2_MODE_S 2 +/*description: SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat +ive edge..*/ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_DOUT2_MODE_S 2 /* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_DOUT1_MODE_M (BIT(1)) -#define SPI_MEM_DOUT1_MODE_V 0x1 -#define SPI_MEM_DOUT1_MODE_S 1 +/*description: SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati +ve edge..*/ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_DOUT1_MODE_S 1 /* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_DOUT0_MODE_M (BIT(0)) -#define SPI_MEM_DOUT0_MODE_V 0x1 -#define SPI_MEM_DOUT0_MODE_S 0 +/*description: SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati +ve edge..*/ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_DOUT0_MODE_S 0 -#define SPI_MEM_DOUT_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B8) -/* SPI_MEM_DOUTS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUTS_NUM 0x00000003 -#define SPI_MEM_DOUTS_NUM_M ((SPI_MEM_DOUTS_NUM_V) << (SPI_MEM_DOUTS_NUM_S)) -#define SPI_MEM_DOUTS_NUM_V 0x3 -#define SPI_MEM_DOUTS_NUM_S 16 -/* SPI_MEM_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUT7_NUM 0x00000003 -#define SPI_MEM_DOUT7_NUM_M ((SPI_MEM_DOUT7_NUM_V) << (SPI_MEM_DOUT7_NUM_S)) -#define SPI_MEM_DOUT7_NUM_V 0x3 -#define SPI_MEM_DOUT7_NUM_S 14 -/* SPI_MEM_DOUT6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUT6_NUM 0x00000003 -#define SPI_MEM_DOUT6_NUM_M ((SPI_MEM_DOUT6_NUM_V) << (SPI_MEM_DOUT6_NUM_S)) -#define SPI_MEM_DOUT6_NUM_V 0x3 -#define SPI_MEM_DOUT6_NUM_S 12 -/* SPI_MEM_DOUT5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUT5_NUM 0x00000003 -#define SPI_MEM_DOUT5_NUM_M ((SPI_MEM_DOUT5_NUM_V) << (SPI_MEM_DOUT5_NUM_S)) -#define SPI_MEM_DOUT5_NUM_V 0x3 -#define SPI_MEM_DOUT5_NUM_S 10 -/* SPI_MEM_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUT4_NUM 0x00000003 -#define SPI_MEM_DOUT4_NUM_M ((SPI_MEM_DOUT4_NUM_V) << (SPI_MEM_DOUT4_NUM_S)) -#define SPI_MEM_DOUT4_NUM_V 0x3 -#define SPI_MEM_DOUT4_NUM_S 8 -/* SPI_MEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUT3_NUM 0x00000003 -#define SPI_MEM_DOUT3_NUM_M ((SPI_MEM_DOUT3_NUM_V) << (SPI_MEM_DOUT3_NUM_S)) -#define SPI_MEM_DOUT3_NUM_V 0x3 -#define SPI_MEM_DOUT3_NUM_S 6 -/* SPI_MEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUT2_NUM 0x00000003 -#define SPI_MEM_DOUT2_NUM_M ((SPI_MEM_DOUT2_NUM_V) << (SPI_MEM_DOUT2_NUM_S)) -#define SPI_MEM_DOUT2_NUM_V 0x3 -#define SPI_MEM_DOUT2_NUM_S 4 -/* SPI_MEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUT1_NUM 0x00000003 -#define SPI_MEM_DOUT1_NUM_M ((SPI_MEM_DOUT1_NUM_V) << (SPI_MEM_DOUT1_NUM_S)) -#define SPI_MEM_DOUT1_NUM_V 0x3 -#define SPI_MEM_DOUT1_NUM_S 2 -/* SPI_MEM_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_DOUT0_NUM 0x00000003 -#define SPI_MEM_DOUT0_NUM_M ((SPI_MEM_DOUT0_NUM_V) << (SPI_MEM_DOUT0_NUM_S)) -#define SPI_MEM_DOUT0_NUM_V 0x3 -#define SPI_MEM_DOUT0_NUM_S 0 - -#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0BC) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xBC) /* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ -/*description: For sram add extra dummy spi clock cycle length for spi clock calibration.*/ -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V) << (SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 acc +esses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set..*/ +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 /* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For sram the bit is used to enable timing auto-calibration for - all reading operations.*/ -#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 -#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 +/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio +ns..*/ +#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 /* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: For sram the bit is used to enable timing adjust clock for all - reading operations.*/ -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 +/*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ +als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/ +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 -#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C0) -/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V) << (SPI_MEM_SPI_SMEM_DINS_MODE_S)) -#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DINS_MODE_S 16 -/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V) << (SPI_MEM_SPI_SMEM_DIN7_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 14 -/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V) << (SPI_MEM_SPI_SMEM_DIN6_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 12 -/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V) << (SPI_MEM_SPI_SMEM_DIN5_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 10 -/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V) << (SPI_MEM_SPI_SMEM_DIN4_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 8 -/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V) << (SPI_MEM_SPI_SMEM_DIN3_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 6 -/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V) << (SPI_MEM_SPI_SMEM_DIN2_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 4 -/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V) << (SPI_MEM_SPI_SMEM_DIN1_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 2 -/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V) << (SPI_MEM_SPI_SMEM_DIN0_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) +/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles + at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HC +LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI +_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne +gative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and + one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cy +cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S)) +#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DINS_MODE_S 24 +/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle +s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at +HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S +PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK + negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge + and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+ +1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 21 +/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle +s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at +HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S +PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK + negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge + and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+ +1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18 +/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle +s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at +HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S +PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK + negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge + and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+ +1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 15 +/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle +s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at +HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S +PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK + negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge + and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+ +1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 12 +/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles + at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at H +CLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SP +I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK +negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge +and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1 +) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 9 +/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles + at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at H +CLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SP +I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK +negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge +and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1 +) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles +at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC +LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI +_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n +egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a +nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) + cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 3 +/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles +at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC +LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI +_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n +egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a +nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) + cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/ +#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 -#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C4) +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) /* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V) << (SPI_MEM_SPI_SMEM_DINS_NUM_S)) -#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 +/*description: SPI_DQS input delay number..*/ +#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S)) +#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 /* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V) << (SPI_MEM_SPI_SMEM_DIN7_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 +/*description: SPI_IO7 input delay number..*/ +#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 /* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V) << (SPI_MEM_SPI_SMEM_DIN6_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 +/*description: SPI_IO6 input delay number..*/ +#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 /* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V) << (SPI_MEM_SPI_SMEM_DIN5_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 +/*description: SPI_IO5 input delay number..*/ +#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 /* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V) << (SPI_MEM_SPI_SMEM_DIN4_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 +/*description: SPI_IO4 input delay number..*/ +#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 /* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V) << (SPI_MEM_SPI_SMEM_DIN3_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 +/*description: SPI_HD input delay number..*/ +#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 /* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V) << (SPI_MEM_SPI_SMEM_DIN2_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 +/*description: SPI_WP input delay number..*/ +#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 /* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V) << (SPI_MEM_SPI_SMEM_DIN1_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 +/*description: SPI_Q input delay number..*/ +#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 /* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V) << (SPI_MEM_SPI_SMEM_DIN0_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 +/*description: SPI_D input delay number..*/ +#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 -#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C8) +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) /* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 8 +/*description: SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_SPI_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 8 /* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7 +/*description: SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7 /* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 6 +/*description: SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_SPI_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 6 /* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 5 +/*description: SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_SPI_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 5 /* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4 +/*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega +tive edge..*/ +#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4 /* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 3 +/*description: SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat +ive edge..*/ +#define SPI_MEM_SPI_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 3 /* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 2 +/*description: SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat +ive edge..*/ +#define SPI_MEM_SPI_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 2 /* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1 +/*description: SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati +ve edge..*/ +#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1 /* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 +/*description: SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati +ve edge..*/ +#define SPI_MEM_SPI_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 -#define SPI_MEM_SPI_SMEM_DOUT_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0CC) -/* SPI_MEM_SPI_SMEM_DOUTS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUTS_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUTS_NUM_M ((SPI_MEM_SPI_SMEM_DOUTS_NUM_V) << (SPI_MEM_SPI_SMEM_DOUTS_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUTS_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUTS_NUM_S 16 -/* SPI_MEM_SPI_SMEM_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT7_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUT7_NUM_M ((SPI_MEM_SPI_SMEM_DOUT7_NUM_V) << (SPI_MEM_SPI_SMEM_DOUT7_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUT7_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUT7_NUM_S 14 -/* SPI_MEM_SPI_SMEM_DOUT6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT6_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUT6_NUM_M ((SPI_MEM_SPI_SMEM_DOUT6_NUM_V) << (SPI_MEM_SPI_SMEM_DOUT6_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUT6_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUT6_NUM_S 12 -/* SPI_MEM_SPI_SMEM_DOUT5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT5_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUT5_NUM_M ((SPI_MEM_SPI_SMEM_DOUT5_NUM_V) << (SPI_MEM_SPI_SMEM_DOUT5_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUT5_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUT5_NUM_S 10 -/* SPI_MEM_SPI_SMEM_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_MEM_SPI_SMEM_DOUT4_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUT4_NUM_M ((SPI_MEM_SPI_SMEM_DOUT4_NUM_V) << (SPI_MEM_SPI_SMEM_DOUT4_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUT4_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUT4_NUM_S 8 -/* SPI_MEM_SPI_SMEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DOUT3_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUT3_NUM_M ((SPI_MEM_SPI_SMEM_DOUT3_NUM_V) << (SPI_MEM_SPI_SMEM_DOUT3_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUT3_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUT3_NUM_S 6 -/* SPI_MEM_SPI_SMEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DOUT2_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUT2_NUM_M ((SPI_MEM_SPI_SMEM_DOUT2_NUM_V) << (SPI_MEM_SPI_SMEM_DOUT2_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUT2_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUT2_NUM_S 4 -/* SPI_MEM_SPI_SMEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DOUT1_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUT1_NUM_M ((SPI_MEM_SPI_SMEM_DOUT1_NUM_V) << (SPI_MEM_SPI_SMEM_DOUT1_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUT1_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUT1_NUM_S 2 -/* SPI_MEM_SPI_SMEM_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_MEM_SPI_SMEM_DOUT0_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DOUT0_NUM_M ((SPI_MEM_SPI_SMEM_DOUT0_NUM_V) << (SPI_MEM_SPI_SMEM_DOUT0_NUM_S)) -#define SPI_MEM_SPI_SMEM_DOUT0_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DOUT0_NUM_S 0 +#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) +/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas +h..*/ +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN (BIT(8)) +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M (BIT(8)) +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S 8 +/* SPI_MEM_ECC_ERR_INT_NUM : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ +/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr +upt..*/ +#define SPI_MEM_ECC_ERR_INT_NUM 0x000000FF +#define SPI_MEM_ECC_ERR_INT_NUM_M ((SPI_MEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_ECC_ERR_INT_NUM_S)) +#define SPI_MEM_ECC_ERR_INT_NUM_V 0xFF +#define SPI_MEM_ECC_ERR_INT_NUM_S 0 -#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D0) +#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD0) +/* SPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SP +I_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte e +rror and data error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/ +#define SPI_MEM_ECC_ERR_ADDR 0xFFFFFFFF +#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) +#define SPI_MEM_ECC_ERR_ADDR_V 0xFFFFFFFF +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +#define SPI_MEM_ECC_ERR_BIT_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) +/* SPI_MEM_ECC_ERR_CNT : RO ;bitpos:[24:17] ;default: 8'd0 ; */ +/*description: This bits show the error times of MSPI ECC read, including ECC byte error and da +ta byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/ +#define SPI_MEM_ECC_ERR_CNT 0x000000FF +#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) +#define SPI_MEM_ECC_ERR_CNT_V 0xFF +#define SPI_MEM_ECC_ERR_CNT_S 17 +/* SPI_MEM_ECC_BYTE_ERR : R/SS/WTC ;bitpos:[16] ;default: 1'd0 ; */ +/*description: It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ER +R_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_ +INT_CLR bit..*/ +#define SPI_MEM_ECC_BYTE_ERR (BIT(16)) +#define SPI_MEM_ECC_BYTE_ERR_M (BIT(16)) +#define SPI_MEM_ECC_BYTE_ERR_V 0x1 +#define SPI_MEM_ECC_BYTE_ERR_S 16 +/* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */ +/*description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC by +te..*/ +#define SPI_MEM_ECC_CHK_ERR_BIT 0x00000007 +#define SPI_MEM_ECC_CHK_ERR_BIT_M ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S)) +#define SPI_MEM_ECC_CHK_ERR_BIT_V 0x7 +#define SPI_MEM_ECC_CHK_ERR_BIT_S 13 +/* SPI_MEM_ECC_DATA_ERR_BIT : R/SS/WTC ;bitpos:[12:6] ;default: 7'd0 ; */ +/*description: It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_ +SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from +0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_ME +M_ECC_ERR_INT_CLR bit..*/ +#define SPI_MEM_ECC_DATA_ERR_BIT 0x0000007F +#define SPI_MEM_ECC_DATA_ERR_BIT_M ((SPI_MEM_ECC_DATA_ERR_BIT_V)<<(SPI_MEM_ECC_DATA_ERR_BIT_S)) +#define SPI_MEM_ECC_DATA_ERR_BIT_V 0x7F +#define SPI_MEM_ECC_DATA_ERR_BIT_S 6 + +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0xDC) +/* SPI_MEM_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M +SPI core clock cycles..*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte +rnal RAM..*/ +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN (BIT(24)) +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M (BIT(24)) +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S 24 /* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes - mode when accesses external RAM.*/ -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 +/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse +s to external RAM..*/ +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 /* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: 1: MSPI skips page corner when accesses external RAM. 0: Not - skip page corner when accesses external RAM.*/ -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/*description: 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner + when accesses to external RAM..*/ +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 /* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ -/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI - CS hold cycles in ECC mode when accessed external RAM.*/ -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007 -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V) << (SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S)) -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7 -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12 +/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in +ECC mode when accesses to external RAM..*/ +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12 /* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */ -/*description: For spi0 spi cs signal is delayed to inactive by spi clock this - bits are combined with spi_mem_cs_hold bit.*/ -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x0000001F -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V) << (SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1F -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 7 +/*description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), wh +ich is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_ME +M_CS_HOLD bit..*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 7 /* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */ -/*description: For spi0 (cycles-1) of prepare phase by spi clock this bits - are combined with spi_mem_cs_setup bit.*/ -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V) << (SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 +/*description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits +are combined with SPI_MEM_CS_SETUP bit..*/ +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 /* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ -#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 -#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 +/*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 /* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ -#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 -#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 +/*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/ +#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 -#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D4) +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xE0) /* SPI_MEM_SPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to enable HyperRAM address out when accesses to - flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/ -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30 +/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/ +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30 /* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable octa_ram address out when accesses to - flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/ -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M (BIT(29)) -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V 0x1 -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S 29 +/*description: Set this bit to enable octa_ram address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0} +..*/ +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S 29 /* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to invert SPI_DIFF when accesses to flash. .*/ -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M (BIT(28)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V 0x1 -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S 28 +/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/ +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S 28 /* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to enable the vary dummy function in SPI HyperBus - mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/ -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses to flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 /* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases - of CMD and ADDR.*/ -#define SPI_MEM_SPI_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M (BIT(26)) -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V 0x1 -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S 26 +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S 26 /* SPI_MEM_SPI_FMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to enable the SPI HyperBus mode.*/ -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE (BIT(25)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M (BIT(25)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S 25 +/*description: Set this bit to enable the SPI HyperBus mode..*/ +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE (BIT(25)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M (BIT(25)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S 25 /* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to enable the differential SPI_CLK#.*/ -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24 -/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: the bits are combined with the bit spi_fmem_ddr_fdqs_loop which - used to select data strobe generating mode in ddr mode.*/ -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE 0x00000003 -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V) << (SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V 0x3 -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S 22 +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK + as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is + not active..*/ +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE (BIT(22)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M (BIT(22)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S 22 /* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: the data strobe is generated by SPI.*/ -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 +/*description: 1: Use internal signal as data strobe, the strobe can not be delayed by input t +iming module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe ca +n be delayed by input timing module.*/ +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 /* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: The delay number of data strobe which from memory based on SPI clock.*/ -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V) << (SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14 +/*description: The delay number of data strobe which from memory based on SPI_CLK..*/ +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14 /* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR - read mode when accesses to flash.*/ -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M (BIT(13)) -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S 13 +/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when +accesses to flash..*/ +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S 13 /* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR - write mode when accesses to flash.*/ -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M (BIT(12)) -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S 12 +/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when + accesses to flash..*/ +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S 12 /* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ -/*description: It is the minimum output data length in the panda device.*/ -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V) << (SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 +/*description: It is the minimum output data length in the panda device..*/ +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 /* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: the bit is used to disable dual edge in command phase when ddr mode.*/ -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 +/*description: the bit is used to disable dual edge in CMD phase when ddr mode..*/ +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 /* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set the bit to reorder tx data of the word in spi ddr mode.*/ -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 +/*description: Set the bit to swap TX data of a word in DDR mode..*/ +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 /* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set the bit to reorder rx data of the word in spi ddr mode.*/ -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 +/*description: Set the bit to reorder RX data of the word in DDR mode..*/ +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 /* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set the bit to enable variable dummy cycle in spi ddr mode.*/ -#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 +/*description: Set the bit to enable variable dummy cycle in DDR mode..*/ +#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 /* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1: in ddr mode 0 in sdr mode*/ -#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) -#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) -#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 +/*description: 1: in ddr mode, 0 in sdr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 -#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D8) +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xE4) /* SPI_MEM_SPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to enable HyperRAM address out when accesses to - external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/ -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30 +/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1 +]}..*/ +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30 /* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable octa_ram address out when accesses to - external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/ -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M (BIT(29)) -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V 0x1 -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S 29 +/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1] +, 1'b0}..*/ +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S 29 /* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M (BIT(28)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V 0x1 -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S 28 +/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/ +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S 28 /* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to enable the vary dummy function in SPI HyperBus - mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/ -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses to flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 /* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases - of CMD and ADDR.*/ -#define SPI_MEM_SPI_SMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M (BIT(26)) -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V 0x1 -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S 26 +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_SPI_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S 26 /* SPI_MEM_SPI_SMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to enable the SPI HyperBus mode.*/ -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE (BIT(25)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M (BIT(25)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S 25 +/*description: Set this bit to enable the SPI HyperBus mode..*/ +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE (BIT(25)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M (BIT(25)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S 25 /* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to enable the differential SPI_CLK#.*/ -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24 -/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: the bits are combined with the bit spi_smem_ddr_fdqs_loop which - used to select data strobe generating mode in ddr mode.*/ -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE 0x00000003 -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V) << (SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x3 -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22 +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK + as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is + not active..*/ +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE (BIT(22)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M (BIT(22)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22 /* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: the data strobe is generated by SPI.*/ -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 +/*description: 1: Use internal signal as data strobe, the strobe can not be delayed by input t +iming module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe ca +n be delayed by input timing module.*/ +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 /* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: The delay number of data strobe which from memory based on SPI clock.*/ -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V) << (SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14 +/*description: The delay number of data strobe which from memory based on SPI_CLK..*/ +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14 /* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR - read mode when accesses to external RAM.*/ -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M (BIT(13)) -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S 13 +/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when +accesses to external RAM..*/ +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S 13 /* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR - write mode when accesses to external RAM.*/ -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M (BIT(12)) -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S 12 +/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when + accesses to external RAM..*/ +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S 12 /* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ -/*description: It is the minimum output data length in the ddr psram.*/ -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V) << (SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 +/*description: It is the minimum output data length in the ddr psram..*/ +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 /* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: the bit is used to disable dual edge in command phase when ddr mode.*/ -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 +/*description: the bit is used to disable dual edge in CMD phase when ddr mode..*/ +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 /* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set the bit to reorder tx data of the word in spi ddr mode.*/ -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 +/*description: Set the bit to reorder tx data of the word in spi ddr mode..*/ +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 /* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set the bit to reorder rx data of the word in spi ddr mode.*/ -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 +/*description: Set the bit to reorder rx data of the word in spi ddr mode..*/ +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 /* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set the bit to enable variable dummy cycle in spi ddr mode.*/ -#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 +/*description: Set the bit to enable variable dummy cycle in spi ddr mode..*/ +#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 /* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1: in ddr mode 0 in sdr mode*/ -#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) -#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 +/*description: 1: in ddr mode, 0 in sdr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0DC) +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0xE8) /* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Register clock gate enable signal. 1: Enable. 0: Disable.*/ -#define SPI_MEM_CLK_EN (BIT(0)) -#define SPI_MEM_CLK_EN_M (BIT(0)) -#define SPI_MEM_CLK_EN_V 0x1 -#define SPI_MEM_CLK_EN_S 0 +/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/ +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 -#define SPI_MEM_CORE_CLK_SEL_REG(i) (REG_SPI_MEM_BASE(i) + 0x0E0) -/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: When the digital system clock selects PLL clock and the frequency - of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ -#define SPI_MEM_SPI01_CLK_SEL 0x00000003 -#define SPI_MEM_SPI01_CLK_SEL_M ((SPI_MEM_SPI01_CLK_SEL_V) << (SPI_MEM_SPI01_CLK_SEL_S)) -#define SPI_MEM_SPI01_CLK_SEL_V 0x3 -#define SPI_MEM_SPI01_CLK_SEL_S 0 +#define SPI_MEM_CORE_CLK_SEL_REG(i) (REG_SPI_MEM_BASE(i) + 0xEC) +/* SPI_MEM_CORE_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: When the digital system clock selects PLL clock and the frequency of PLL clock i +s 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_ +CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_ +CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the freq +uency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_C +LK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. .*/ +#define SPI_MEM_CORE_CLK_SEL 0x00000003 +#define SPI_MEM_CORE_CLK_SEL_M ((SPI_MEM_CORE_CLK_SEL_V)<<(SPI_MEM_CORE_CLK_SEL_S)) +#define SPI_MEM_CORE_CLK_SEL_V 0x3 +#define SPI_MEM_CORE_CLK_SEL_S 0 + +#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xF0) +/* SPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ENA_S 4 +/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ENA_S 3 +/* SPI_MEM_TOTAL_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/ +#define SPI_MEM_TOTAL_TRANS_END_INT_ENA (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_M (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_V 0x1 +#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_S 2 +/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_V 0x1 +#define SPI_MEM_PES_END_INT_ENA_S 1 +/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_V 0x1 +#define SPI_MEM_PER_END_INT_ENA_S 0 + +#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xF4) +/* SPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_ME +M_ECC_ERR_CNT will be cleared by the pulse of this bit..*/ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 +#define SPI_MEM_ECC_ERR_INT_CLR_S 4 +/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_CLR_S 3 +/* SPI_MEM_TOTAL_TRANS_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/ +#define SPI_MEM_TOTAL_TRANS_END_INT_CLR (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_M (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_V 0x1 +#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_S 2 +/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_V 0x1 +#define SPI_MEM_PES_END_INT_CLR_S 1 +/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_V 0x1 +#define SPI_MEM_PER_END_INT_CLR_S 0 + +#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xF8) +/* SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is +set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the err +or times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_ +NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is s +et, this bit is triggered when the error times of SPI0/1 ECC read external RAM a +re equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN +and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total erro +r times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_C +TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN + are cleared, this bit will not be triggered..*/ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 +#define SPI_MEM_ECC_ERR_INT_RAW_S 4 +/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that +chip is loosing power and RTC module sends out brown out close flash request to +SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + and MSPI returns to idle state. 0: Others..*/ +#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_RAW_S 3 +/* SPI_MEM_TOTAL_TRANS_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 tr +ansfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/ +PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Other +s..*/ +#define SPI_MEM_TOTAL_TRANS_END_INT_RAW (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_M (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_V 0x1 +#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_S 2 +/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com +mand (0x75) is sent and flash is suspended successfully. 0: Others..*/ +#define SPI_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_V 0x1 +#define SPI_MEM_PES_END_INT_RAW_S 1 +/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com +mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/ +#define SPI_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_V 0x1 +#define SPI_MEM_PER_END_INT_RAW_S 0 + +#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xFC) +/* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ST_S 4 +/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ST (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ST_S 3 +/* SPI_MEM_TOTAL_TRANS_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/ +#define SPI_MEM_TOTAL_TRANS_END_INT_ST (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_ST_M (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_ST_V 0x1 +#define SPI_MEM_TOTAL_TRANS_END_INT_ST_S 2 +/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ST (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_V 0x1 +#define SPI_MEM_PES_END_INT_ST_S 1 +/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ST (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_V 0x1 +#define SPI_MEM_PER_END_INT_ST_S 0 + +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) +/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101040 ; */ +/*description: SPI register version..*/ +#define SPI_MEM_DATE 0x0FFFFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0xFFFFFFF +#define SPI_MEM_DATE_S 0 -#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) -/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003220 ; */ -/*description: SPI register version.*/ -#define SPI_MEM_DATE 0x0FFFFFFF -#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V) << (SPI_MEM_DATE_S)) -#define SPI_MEM_DATE_V 0xFFFFFFF -#define SPI_MEM_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SPI_MEM_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/spi_mem_struct.h b/components/soc/esp32s3/include/soc/spi_mem_struct.h index e74152156d..f5c51b3b57 100644 --- a/components/soc/esp32s3/include/soc/spi_mem_struct.h +++ b/components/soc/esp32s3/include/soc/spi_mem_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,489 +11,563 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_SPI_MEM_STRUCT_H_ +#define _SOC_SPI_MEM_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif -#include - typedef volatile struct { union { struct { - uint32_t reserved0 : 17; /*reserved*/ - uint32_t flash_pe : 1; /*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ - uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ - uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ - uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ - uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t reserved0 : 17; /*reserved*/ + uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_res : 1; /*This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pp : 1; /*Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */ + uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ }; uint32_t val; } cmd; - uint32_t addr; /*In user mode it is the memory address. other then the bit0-bit23 is the memory address the bit24-bit31 are the byte length of a transfer.*/ + uint32_t addr; union { struct { - uint32_t reserved0 : 3; /*reserved*/ - uint32_t fdummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ - uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/ - uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/ - uint32_t faddr_oct : 1; /*Apply 8 signals during address phase 1:enable 0: disable*/ - uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable*/ - uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ - uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ - uint32_t fcs_crc_en : 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ - uint32_t tx_crc_en : 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ - uint32_t reserved12 : 1; /*reserved*/ - uint32_t fastrd_mode : 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ - uint32_t fread_dual : 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ - uint32_t reserved15 : 3; /*reserved*/ - uint32_t q_pol : 1; /*The bit is used to set MISO line polarity 1: high 0 low*/ - uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/ - uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ - uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ - uint32_t reserved22 : 1; /*reserved*/ - uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ - uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ - uint32_t reserved25 : 7; /*reserved*/ + uint32_t reserved0 : 3; /*reserved*/ + uint32_t fdummy_out : 1; /*In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/ + uint32_t fdout_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.*/ + uint32_t fdin_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in DIN phase.*/ + uint32_t faddr_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.*/ + uint32_t fcmd_dual : 1; /*Set this bit to enable 2-bit-mode(2-bm) in CMD phase.*/ + uint32_t fcmd_quad : 1; /*Set this bit to enable 4-bit-mode(4-bm) in CMD phase.*/ + uint32_t fcmd_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in CMD phase.*/ + uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t reserved12 : 1; /*reserved*/ + uint32_t fastrd_mode : 1; /*This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.*/ + uint32_t fread_dual : 1; /*In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. */ + uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */ + uint32_t reserved16 : 2; /*reserved*/ + uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/ + uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/ + uint32_t fread_quad : 1; /*In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */ + uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */ + uint32_t wrsr_2b : 1; /*Two bytes data will be written to status register when it is set. 1: enable 0: disable. */ + uint32_t fread_dio : 1; /*In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. */ + uint32_t fread_qio : 1; /*In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */ + uint32_t reserved25 : 7; /*reserved*/ }; uint32_t val; } ctrl; union { struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ - uint32_t cs_hold_dly_res : 12; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by spi clock.*/ - uint32_t cs_hold_dly : 12; /*SPI fsm is delayed to idle by spi clock cycles.*/ - uint32_t cs_dly_num : 2; /*spi_mem_cs signal is delayed by system clock cycles*/ - uint32_t cs_dly_mode : 2; /*The cs signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk*/ - uint32_t reserved30 : 1; - uint32_t cs_dly_edge : 1; /*The bit is used to select the spi clock edge to modify CS line timing.*/ + uint32_t clk_mode : 2; /*SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.*/ + uint32_t cs_hold_dly_res : 10; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by SPI_CLK.*/ + uint32_t reserved12 : 18; /*reserved*/ + uint32_t rxfifo_rst : 1; /*SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.*/ + uint32_t reserved31 : 1; /*reserved*/ }; uint32_t val; } ctrl1; union { struct { - uint32_t cs_setup_time : 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ - uint32_t cs_hold_time : 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ - uint32_t ecc_cs_hold_time : 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycle in ECC mode when accessed flash.*/ - uint32_t reserved13 : 18; /*reserved*/ - uint32_t sync_reset : 1; /*The FSM will be reset.*/ + uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t cs_hold_time: 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t ecc_cs_hold_time: 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycle in ECC mode when accessed flash.*/ + uint32_t ecc_skip_page_corner: 1; /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/ + uint32_t ecc_16to18_byte_en: 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/ + uint32_t reserved15: 10; /*reserved*/ + uint32_t cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t sync_reset : 1; /*The FSM will be reset.*/ }; uint32_t val; } ctrl2; union { struct { - uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/ - uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ - uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ - uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk.*/ - uint32_t clk_equ_sysclk : 1; /*reserved*/ + uint32_t clkcnt_l : 8; /*It must equal to the value of SPI_MEM_CLKCNT_N. */ + uint32_t clkcnt_h : 8; /*It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).*/ + uint32_t clkcnt_n : 8; /*When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/ + uint32_t reserved24 : 7; /*reserved*/ + uint32_t clk_equ_sysclk : 1; /*When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/ }; uint32_t val; } clock; union { struct { - uint32_t reserved0 : 6; /*reserved*/ - uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ - uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ - uint32_t reserved8 : 1; /*reserved*/ - uint32_t ck_out_edge : 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/ - uint32_t reserved10 : 2; /*reserved*/ - uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/ - uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/ - uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ - uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ - uint32_t reserved16 : 8; /*reserved*/ - uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/ - uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/ - uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/ - uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/ - uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/ - uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/ - uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/ - uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/ + uint32_t reserved0: 6; /*reserved*/ + uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ + uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ + uint32_t reserved8: 1; /*reserved*/ + uint32_t ck_out_edge : 1; /*This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. */ + uint32_t reserved10 : 2; /*reserved*/ + uint32_t fwrite_dual : 1; /*Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.*/ + uint32_t fwrite_quad : 1; /*Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.*/ + uint32_t fwrite_dio : 1; /*Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.*/ + uint32_t fwrite_qio : 1; /*Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.*/ + uint32_t reserved16 : 8; /*reserved*/ + uint32_t usr_miso_highpart : 1; /*DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */ + uint32_t usr_mosi_highpart : 1; /*DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */ + uint32_t usr_dummy_idle : 1; /*SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.*/ + uint32_t usr_mosi : 1; /*This bit enable the DOUT phase of an write-data operation.*/ + uint32_t usr_miso : 1; /*This bit enable the DIN phase of a read-data operation.*/ + uint32_t usr_dummy : 1; /*This bit enable the DUMMY phase of an operation.*/ + uint32_t usr_addr : 1; /*This bit enable the ADDR phase of an operation.*/ + uint32_t usr_command : 1; /*This bit enable the CMD phase of an operation.*/ }; uint32_t val; } user; union { struct { - uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ - uint32_t reserved6 : 20; /*reserved*/ - uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t usr_dummy_cyclelen : 6; /*The SPI_CLK cycle length minus 1 of DUMMY phase.*/ + uint32_t reserved6 : 20; /*reserved*/ + uint32_t usr_addr_bitlen : 6; /*The length in bits of ADDR phase. The register value shall be (bit_num-1).*/ }; uint32_t val; } user1; union { struct { - uint32_t usr_command_value : 16; /*The value of command.*/ - uint32_t reserved16 : 12; /*reserved*/ - uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + uint32_t usr_command_value : 16; /*The value of user defined(USR) command.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t usr_command_bitlen : 4; /*The length in bits of CMD phase. The register value shall be (bit_num-1)*/ }; uint32_t val; } user2; union { struct { - uint32_t usr_mosi_bit_len : 11; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ - uint32_t reserved11 : 21; /*reserved*/ + uint32_t usr_mosi_bit_len:10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10: 22; /*reserved*/ }; uint32_t val; } mosi_dlen; union { struct { - uint32_t usr_miso_bit_len : 11; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ - uint32_t reserved11 : 21; /*reserved*/ + uint32_t usr_miso_bit_len:10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10: 22; /*reserved*/ }; uint32_t val; } miso_dlen; union { struct { - uint32_t status : 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ - uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ - uint32_t reserved24 : 8; /*reserved*/ + uint32_t status: 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ + uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t reserved24: 8; /*reserved*/ }; uint32_t val; } rd_status; - uint32_t ext_addr; /*The register are the higher 32bits in the 64 bits address mode.*/ + uint32_t ext_addr; /*The register are the higher 32bits in the 64 bits address mode.*/ union { struct { - uint32_t cs0_dis : 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_mem_cs0 signal is from/to CS0 pin*/ - uint32_t cs1_dis : 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_mem_cs1 signal is from/to CS1 pin*/ - uint32_t reserved2 : 1; /*reserved*/ - uint32_t trans_end : 1; /*The bit is used to indicate the transimitting is done.*/ - uint32_t trans_end_en : 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/ - uint32_t cs_pol : 2; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/ - uint32_t fsub_pin : 1; /*For SPI0 flash is connected to SUBPINs.*/ - uint32_t ssub_pin : 1; /*For SPI0 sram is connected to SUBPINs.*/ - uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ - uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set.*/ - uint32_t auto_per : 1; /*reserved*/ - uint32_t reserved12 : 20; /*reserved*/ + uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_mem_cs0 signal is from/to CS0 pin*/ + uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_mem_cs1 signal is from/to CS1 pin*/ + uint32_t reserved2: 1; /*reserved*/ + uint32_t trans_end: 1; /*The bit is used to indicate the transimitting is done.*/ + uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/ + uint32_t reserved5: 2; /*reserved*/ + uint32_t fsub_pin: 1; /*For SPI0 flash is connected to SUBPINs.*/ + uint32_t ssub_pin: 1; /*For SPI0 sram is connected to SUBPINs.*/ + uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ + uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ + uint32_t auto_per: 1; /*reserved*/ + uint32_t reserved12: 20; /*reserved*/ }; uint32_t val; } misc; - uint32_t tx_crc; /*For SPI1 the value of crc32.*/ + uint32_t tx_crc; /*For SPI1 the value of crc32.*/ union { struct { - uint32_t req_en : 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ - uint32_t usr_cmd_4byte : 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ - uint32_t flash_usr_cmd : 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ - uint32_t fdin_dual : 1; /*For SPI0 flash din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ - uint32_t fdout_dual : 1; /*For SPI0 flash dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ - uint32_t faddr_dual : 1; /*For SPI0 flash address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ - uint32_t fdin_quad : 1; /*For SPI0 flash din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ - uint32_t fdout_quad : 1; /*For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ - uint32_t faddr_quad : 1; /*For SPI0 flash address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ - uint32_t reserved9 : 23; /*reserved*/ + uint32_t req_en : 1; /*Set this bit to enable Cache's access and SPI0's transfer.*/ + uint32_t usr_cmd_4byte : 1; /*Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.*/ + uint32_t flash_usr_cmd : 1; /*1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.*/ + uint32_t fdin_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.*/ + uint32_t fdout_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.*/ + uint32_t faddr_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.*/ + uint32_t fdin_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.*/ + uint32_t fdout_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.*/ + uint32_t faddr_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.*/ + uint32_t reserved9 : 23; /*reserved*/ }; uint32_t val; } cache_fctrl; union { struct { - uint32_t usr_scmd_4byte : 1; /*For SPI0 In the spi sram mode cache read flash with 4 bytes command 1: enable 0:disable.*/ - uint32_t usr_sram_dio : 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ - uint32_t usr_sram_qio : 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ - uint32_t usr_wr_sram_dummy : 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ - uint32_t usr_rd_sram_dummy : 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ - uint32_t cache_sram_usr_rcmd : 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ - uint32_t sram_rdummy_cyclelen : 6; /*For SPI0 In the sram mode it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/ - uint32_t reserved12 : 2; /*reserved*/ - uint32_t sram_addr_bitlen : 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ - uint32_t cache_sram_usr_wcmd : 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ - uint32_t sram_oct : 1; /*reserved*/ - uint32_t sram_wdummy_cyclelen : 6; /*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/ - uint32_t reserved28 : 4; /*reserved*/ + uint32_t usr_scmd_4byte : 1; /*Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.*/ + uint32_t usr_sram_dio : 1; /*Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.*/ + uint32_t usr_sram_qio : 1; /*Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.*/ + uint32_t usr_wr_sram_dummy : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.*/ + uint32_t usr_rd_sram_dummy : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.*/ + uint32_t usr_rcmd : 1; /*1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.*/ + uint32_t sram_rdummy_cyclelen : 6; /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.*/ + uint32_t reserved12 : 2; /*reserved*/ + uint32_t sram_addr_bitlen : 6; /*When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).*/ + uint32_t usr_wcmd : 1; /*1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.*/ + uint32_t sram_oct : 1; /*Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.*/ + uint32_t sram_wdummy_cyclelen : 6; /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.*/ + uint32_t reserved28 : 4; /*reserved*/ }; uint32_t val; } cache_sctrl; union { struct { - uint32_t sclk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ - uint32_t swb_mode : 8; /*Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode bit.*/ - uint32_t sdin_dual : 1; /*For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ - uint32_t sdout_dual : 1; /*For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ - uint32_t saddr_dual : 1; /*For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ - uint32_t scmd_dual : 1; /*For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ - uint32_t sdin_quad : 1; /*For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t sdout_quad : 1; /*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t saddr_quad : 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t scmd_quad : 1; /*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t sdin_oct : 1; /*For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/ - uint32_t sdout_oct : 1; /*For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/ - uint32_t saddr_oct : 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/ - uint32_t scmd_oct : 1; /*For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/ - uint32_t sdummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ - uint32_t reserved23 : 9; /*reserved*/ + uint32_t sclk_mode : 2; /*SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.*/ + uint32_t swb_mode : 8; /*Mode bits when SPI0 accesses to Ext_RAM.*/ + uint32_t sdin_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.*/ + uint32_t sdout_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.*/ + uint32_t saddr_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.*/ + uint32_t scmd_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.*/ + uint32_t sdin_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.*/ + uint32_t sdout_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.*/ + uint32_t saddr_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.*/ + uint32_t scmd_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.*/ + uint32_t sdin_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.*/ + uint32_t sdout_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.*/ + uint32_t saddr_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.*/ + uint32_t scmd_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.*/ + uint32_t sdummy_out : 1; /*When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/ + uint32_t reserved23 : 9; /*reserved*/ }; uint32_t val; } sram_cmd; union { struct { - uint32_t usr_rd_cmd_value : 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for sram.*/ - uint32_t reserved16 : 12; /*reserved*/ - uint32_t usr_rd_cmd_bitlen : 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/ + uint32_t usr_rd_cmd_value : 16; /*When SPI0 reads Ext_RAM, it is the command value of CMD phase.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t usr_rd_cmd_bitlen : 4; /*When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/ }; uint32_t val; } sram_drd_cmd; union { struct { - uint32_t usr_wr_cmd_value : 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/ - uint32_t reserved16 : 12; /*reserved*/ - uint32_t usr_wr_cmd_bitlen : 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/ + uint32_t usr_wr_cmd_value : 16; /*When SPI0 writes Ext_RAM, it is the command value of CMD phase.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t usr_wr_cmd_bitlen : 4; /*When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/ }; uint32_t val; } sram_dwr_cmd; union { struct { - uint32_t cnt_l : 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/ - uint32_t cnt_h : 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ - uint32_t cnt_n : 8; /*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ - uint32_t reserved24 : 7; /*reserved*/ - uint32_t equ_sysclk : 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ + uint32_t cnt_l : 8; /*It must equal to the value of SPI_MEM_SCLKCNT_N. */ + uint32_t cnt_h : 8; /*It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1).*/ + uint32_t cnt_n : 8; /*When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)*/ + uint32_t reserved24 : 7; /*reserved*/ + uint32_t equ_sysclk : 1; /*When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/ }; uint32_t val; } sram_clk; union { struct { - uint32_t st : 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ - uint32_t reserved3 : 29; /*reserved*/ + uint32_t st : 3; /*The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).*/ + uint32_t reserved3 : 29; /*reserved*/ }; uint32_t val; } fsm; - uint32_t data_buf[18]; /*data buffer*/ + uint32_t data_buf[16]; /*data buffer*/ union { struct { - uint32_t waiti_en : 1; /*auto-waiting flash idle operation when program flash or erase flash. 1: enable 0: disable.*/ - uint32_t waiti_dummy : 1; /*The dummy phase enable when auto wait flash idle*/ - uint32_t waiti_cmd : 8; /*The command to auto wait idle*/ - uint32_t waiti_dummy_cyclelen : 8; /*The dummy cycle length when auto wait flash idle*/ - uint32_t reserved18 : 14; /*reserved*/ + uint32_t waiti_en : 1; /*Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.*/ + uint32_t waiti_dummy : 1; /*The dummy phase enable when auto wait flash idle*/ + uint32_t waiti_cmd : 8; /*The command to auto wait idle*/ + uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when auto wait flash idle */ + uint32_t reserved16 : 16; /*reserved*/ }; uint32_t val; } flash_waiti_ctrl; union { struct { - uint32_t flash_per : 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t flash_pes : 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t reserved2 : 30; + uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_per_wait_en : 1; /*Set this bit to add delay time after program erase resume(PER) is sent.*/ + uint32_t flash_pes_wait_en : 1; /*Set this bit to add delay time after program erase suspend(PES) command is sent.*/ + uint32_t pes_per_en : 1; /*Set this bit to enable PES transfer trigger PES transfer option.*/ + uint32_t pesr_idle_en : 1; /*1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.*/ + uint32_t reserved6 : 26; /*reserved*/ }; uint32_t val; } flash_sus_cmd; union { struct { - uint32_t flash_pes_en : 1; /*Auto-suspending enable*/ - uint32_t flash_per_command : 8; /*Program/Erase resume command.*/ - uint32_t flash_pes_command : 8; /*Program/Erase suspend command.*/ - uint32_t reserved17 : 15; + uint32_t flash_pes_en : 1; /*Set this bit to enable auto-suspend function.*/ + uint32_t flash_per_command : 8; /*Program/Erase resume command value.*/ + uint32_t flash_pes_command : 8; /*Program/Erase suspend command value.*/ + uint32_t reserved17 : 15; /*reserved*/ }; uint32_t val; } flash_sus_ctrl; union { struct { - uint32_t flash_sus : 1; /*The status of flash suspend only used in SPI1.*/ - uint32_t reserved1 : 31; + uint32_t flash_sus : 1; /*The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1.*/ + uint32_t reserved1 : 1; /*reserved*/ + uint32_t flash_hpm_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/ + uint32_t flash_res_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/ + uint32_t flash_dp_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/ + uint32_t flash_per_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/ + uint32_t flash_pes_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/ + uint32_t reserved7 : 25; /*reserved*/ }; uint32_t val; } sus_status; union { struct { - uint32_t timing_clk_ena : 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ - uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ - uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ - uint32_t reserved5 : 27; + uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reserved5: 27; }; uint32_t val; } timing_cali; union { struct { - uint32_t din0_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t din1_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t din2_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t din3_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t din4_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din5_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din6_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din7_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t dins_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t reserved18 : 14; /*reserved*/ + uint32_t din0_mode : 3; /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t din3_mode : 3; /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t din4_mode : 3; /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t din5_mode : 3; /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t dins_mode : 3; /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t reserved27 : 5; /*reserved*/ }; uint32_t val; } din_mode; union { struct { - uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t reserved18 : 14; /*reserved*/ + uint32_t din0_num : 2; /*SPI_D input delay number.*/ + uint32_t din1_num : 2; /*SPI_Q input delay number.*/ + uint32_t din2_num : 2; /*SPI_WP input delay number.*/ + uint32_t din3_num : 2; /*SPI_HD input delay number.*/ + uint32_t din4_num : 2; /*SPI_IO4 input delay number.*/ + uint32_t din5_num : 2; /*SPI_IO5 input delay number.*/ + uint32_t din6_num : 2; /*SPI_IO6 input delay number.*/ + uint32_t din7_num : 2; /*SPI_IO7 input delay number.*/ + uint32_t dins_num : 2; /*SPI_DQS input delay number.*/ + uint32_t reserved18 : 14; /*reserved*/ }; uint32_t val; } din_num; union { struct { - uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t reserved9 : 23; /*reserved*/ + uint32_t dout0_mode : 1; /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t dout3_mode : 1; /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t dout6_mode : 1; /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t dout7_mode : 1; /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t reserved9 : 23; /*reserved*/ }; uint32_t val; } dout_mode; uint32_t reserved_b8; union { struct { - uint32_t spi_smem_timing_clk_ena : 1; /*For sram the bit is used to enable timing adjust clock for all reading operations.*/ - uint32_t spi_smem_timing_cali : 1; /*For sram the bit is used to enable timing auto-calibration for all reading operations.*/ - uint32_t spi_smem_extra_dummy_cyclelen : 3; /*For sram add extra dummy spi clock cycle length for spi clock calibration.*/ - uint32_t reserved5 : 27; + uint32_t smem_timing_clk_ena : 1; /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/ + uint32_t smem_timing_cali : 1; /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/ + uint32_t smem_extra_dummy_cyclelen : 3; /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set.*/ + uint32_t reserved5 : 27; /*reserved*/ }; uint32_t val; } spi_smem_timing_cali; union { struct { - uint32_t spi_smem_din0_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t spi_smem_din1_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t spi_smem_din2_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t spi_smem_din3_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t spi_smem_din4_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t spi_smem_din5_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t spi_smem_din6_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t spi_smem_din7_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t spi_smem_dins_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t reserved18 : 14; /*reserved*/ + uint32_t smem_din0_mode : 3; /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_din3_mode : 3; /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_din4_mode : 3; /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_din5_mode : 3; /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_dins_mode : 3; /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t reserved27 : 5; /*reserved*/ }; uint32_t val; } spi_smem_din_mode; union { struct { - uint32_t spi_smem_din0_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t spi_smem_din1_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t spi_smem_din2_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t spi_smem_din3_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t spi_smem_din4_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t spi_smem_din5_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t spi_smem_din6_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t spi_smem_din7_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t spi_smem_dins_num : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ - uint32_t reserved18 : 14; /*reserved*/ + uint32_t smem_din0_num : 2; /*SPI_D input delay number.*/ + uint32_t smem_din1_num : 2; /*SPI_Q input delay number.*/ + uint32_t smem_din2_num : 2; /*SPI_WP input delay number.*/ + uint32_t smem_din3_num : 2; /*SPI_HD input delay number.*/ + uint32_t smem_din4_num : 2; /*SPI_IO4 input delay number.*/ + uint32_t smem_din5_num : 2; /*SPI_IO5 input delay number.*/ + uint32_t smem_din6_num : 2; /*SPI_IO6 input delay number.*/ + uint32_t smem_din7_num : 2; /*SPI_IO7 input delay number.*/ + uint32_t smem_dins_num : 2; /*SPI_DQS input delay number.*/ + uint32_t reserved18 : 14; /*reserved*/ }; uint32_t val; } spi_smem_din_num; union { struct { - uint32_t spi_smem_dout0_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t spi_smem_dout1_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t spi_smem_dout2_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t spi_smem_dout3_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t spi_smem_dout4_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t spi_smem_dout5_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t spi_smem_dout6_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t spi_smem_dout7_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t spi_smem_douts_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ - uint32_t reserved9 : 23; /*reserved*/ + uint32_t smem_dout0_mode : 1; /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_dout3_mode : 1; /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_dout6_mode : 1; /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_dout7_mode : 1; /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t smem_douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/ + uint32_t reserved9 : 23; /*reserved*/ }; uint32_t val; } spi_smem_dout_mode; - uint32_t reserved_cc; union { struct { - uint32_t spi_smem_cs_setup : 1; /*For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ - uint32_t spi_smem_cs_hold : 1; /*For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ - uint32_t spi_smem_cs_setup_time : 5; /*For spi0 (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ - uint32_t spi_smem_cs_hold_time : 5; /*For spi0 spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ - uint32_t spi_smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accessed external RAM.*/ - uint32_t reserved15 : 17; + uint32_t ecc_err_int_num : 8; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } ecc_ctrl; + uint32_t ecc_err_addr; + union { + struct { + uint32_t reserved0 : 6; /*reserved*/ + uint32_t ecc_data_err_bit : 7; /*It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/ + uint32_t ecc_chk_err_bit : 3; /*When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte.*/ + uint32_t ecc_byte_err : 1; /*It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/ + uint32_t ecc_err_cnt : 8; /*This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + uint32_t reserved25 : 7; /*reserved*/ + }; + uint32_t val; + } ecc_err_bit; + uint32_t reserved_d8; + union { + struct { + uint32_t smem_cs_setup : 1; /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/ + uint32_t smem_cs_hold : 1; /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/ + uint32_t smem_cs_setup_time : 5; /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/ + uint32_t smem_cs_hold_time : 5; /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/ + uint32_t smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM.*/ + uint32_t smem_ecc_skip_page_corner : 1; /*1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM.*/ + uint32_t smem_ecc_16to18_byte_en : 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM.*/ + uint32_t reserved17 : 7; /*reserved*/ + uint32_t smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/ + uint32_t smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t reserved31 : 1; /*reserved*/ }; uint32_t val; } spi_smem_ac; union { struct { - uint32_t spi_fmem_ddr_en : 1; /*1: in ddr mode 0 in sdr mode*/ - uint32_t spi_fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/ - uint32_t spi_fmem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/ - uint32_t spi_fmem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/ - uint32_t spi_fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/ - uint32_t spi_fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/ - uint32_t spi_fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to flash.*/ - uint32_t spi_fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to flash.*/ - uint32_t spi_fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ - uint32_t spi_fmem_ddr_dqs_loop : 1; /*the data strobe is generated by SPI.*/ - uint32_t spi_fmem_ddr_dqs_loop_mode : 2; /*the bits are combined with the bit spi_fmem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/ - uint32_t spi_fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ - uint32_t spi_fmem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/ - uint32_t spi_fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ - uint32_t spi_fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/ - uint32_t spi_fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/ - uint32_t spi_fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/ - uint32_t spi_fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/ - uint32_t reserved31 : 1; /*reserved*/ + uint32_t fmem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/ + uint32_t fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in DDR mode.*/ + uint32_t fmem_ddr_rdat_swp : 1; /*Set the bit to reorder RX data of the word in DDR mode.*/ + uint32_t fmem_ddr_wdat_swp : 1; /*Set the bit to swap TX data of a word in DDR mode.*/ + uint32_t fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in CMD phase when ddr mode.*/ + uint32_t fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/ + uint32_t fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.*/ + uint32_t fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.*/ + uint32_t fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/ + uint32_t fmem_ddr_dqs_loop : 1; /*1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/ + uint32_t fmem_ddr_dqs_loop_mode : 1; /*When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.*/ + uint32_t reserved23 : 1; /*reserved*/ + uint32_t fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t fmem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/ + uint32_t fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/ + uint32_t fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/ + uint32_t fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ }; uint32_t val; } ddr; union { struct { - uint32_t spi_smem_ddr_en : 1; /*1: in ddr mode 0 in sdr mode*/ - uint32_t spi_smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/ - uint32_t spi_smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/ - uint32_t spi_smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/ - uint32_t spi_smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/ - uint32_t spi_smem_outminbytelen : 7; /*It is the minimum output data length in the ddr psram.*/ - uint32_t spi_smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to external RAM.*/ - uint32_t spi_smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to external RAM.*/ - uint32_t spi_smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ - uint32_t spi_smem_ddr_dqs_loop : 1; /*the data strobe is generated by SPI.*/ - uint32_t spi_smem_ddr_dqs_loop_mode : 2; /*the bits are combined with the bit spi_smem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/ - uint32_t spi_smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ - uint32_t spi_smem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/ - uint32_t spi_smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ - uint32_t spi_smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/ - uint32_t spi_smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ - uint32_t spi_smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/ - uint32_t spi_smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/ - uint32_t reserved31 : 1; /*reserved*/ + uint32_t smem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/ + uint32_t smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/ + uint32_t smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/ + uint32_t smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/ + uint32_t smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in CMD phase when ddr mode.*/ + uint32_t smem_outminbytelen : 7; /*It is the minimum output data length in the ddr psram.*/ + uint32_t smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM.*/ + uint32_t smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM.*/ + uint32_t smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/ + uint32_t smem_ddr_dqs_loop : 1; /*1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/ + uint32_t smem_ddr_dqs_loop_mode : 1; /*When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.*/ + uint32_t reserved23 : 1; /*reserved*/ + uint32_t smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t smem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/ + uint32_t smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/ + uint32_t smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ + uint32_t smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ }; uint32_t val; } spi_smem_ddr; union { struct { - uint32_t clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ - uint32_t reserved1 : 31; /*reserved*/ + uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ + uint32_t reserved1: 31; /*reserved*/ }; uint32_t val; } clock_gate; union { struct { - uint32_t spi01_clk_sel : 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ - uint32_t reserved2 : 30; /*reserved*/ + uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ + uint32_t reserved2: 30; /*reserved*/ }; uint32_t val; } core_clk_sel; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; + union { + struct { + uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t total_trans_end_en : 1; /*The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/ + uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t per_end_int_clr : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end_int_clr : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t total_trans_end_int_clr : 1; /*The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/ + uint32_t brown_out_int_clr : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t ecc_err_int_clr : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t per_end_int_raw : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/ + uint32_t pes_end_int_raw : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/ + uint32_t total_trans_end_int_raw : 1; /*The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others.*/ + uint32_t brown_out_int_raw : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t ecc_err_int_raw : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t per_end_int_st : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end_int_st : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t total_trans_end_int_st : 1; /*The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/ + uint32_t brown_out_int_st : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t ecc_err_int_st : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } int_st; uint32_t reserved_100; uint32_t reserved_104; uint32_t reserved_108; @@ -687,14 +761,19 @@ typedef volatile struct { uint32_t reserved_3f8; union { struct { - uint32_t date : 28; /*SPI register version.*/ - uint32_t reserved28 : 4; /*reserved*/ + uint32_t date : 28; /*SPI register version.*/ + uint32_t reserved28 : 4; /*reserved*/ }; uint32_t val; } date; } spi_mem_dev_t; extern spi_mem_dev_t SPIMEM0; extern spi_mem_dev_t SPIMEM1; + +_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!"); + #ifdef __cplusplus } #endif + +#endif /* _SOC_SPI_MEM_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/spi_reg.h b/components/soc/esp32s3/include/soc/spi_reg.h index 89b4afeae9..7f6a157760 100644 --- a/components/soc/esp32s3/include/soc/spi_reg.h +++ b/components/soc/esp32s3/include/soc/spi_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,1578 +11,1747 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SPI_REG_H_ +#define _SOC_SPI_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) -/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: User define command enable. An operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ -#define SPI_USR (BIT(24)) -#define SPI_USR_M (BIT(24)) -#define SPI_USR_V 0x1 -#define SPI_USR_S 24 -/* SPI_UPDATE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to synchronize SPI registers from APB clock domain - into SPI module clock domain which is only used in SPI master mode.*/ -#define SPI_UPDATE (BIT(23)) -#define SPI_UPDATE_M (BIT(23)) -#define SPI_UPDATE_V 0x1 -#define SPI_UPDATE_S 23 +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) +/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when the bit is set. + The bit will be cleared once the operation done.1: enable 0: disable. Can not b +e changed by CONF_buf..*/ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (BIT(24)) +#define SPI_USR_V 0x1 +#define SPI_USR_S 24 +/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module +clock domain, which is only used in SPI master mode..*/ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (BIT(23)) +#define SPI_UPDATE_V 0x1 +#define SPI_UPDATE_S 23 /* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ -/*description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ -#define SPI_CONF_BITLEN 0x0003FFFF -#define SPI_CONF_BITLEN_M ((SPI_CONF_BITLEN_V) << (SPI_CONF_BITLEN_S)) -#define SPI_CONF_BITLEN_V 0x3FFFF -#define SPI_CONF_BITLEN_S 0 +/*description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state..*/ +#define SPI_CONF_BITLEN 0x0003FFFF +#define SPI_CONF_BITLEN_M ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S)) +#define SPI_CONF_BITLEN_V 0x3FFFF +#define SPI_CONF_BITLEN_S 0 -#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x004) +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) /* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: Address to slave. Can be configured in CONF state.*/ -#define SPI_USR_ADDR_VALUE 0xFFFFFFFF -#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V) << (SPI_USR_ADDR_VALUE_S)) -#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF -#define SPI_USR_ADDR_VALUE_S 0 +/*description: Address to slave. Can be configured in CONF state..*/ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S)) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_S 0 -#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008) -/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB - first. Can be configured in CONF state.*/ -#define SPI_WR_BIT_ORDER (BIT(26)) -#define SPI_WR_BIT_ORDER_M (BIT(26)) -#define SPI_WR_BIT_ORDER_V 0x1 -#define SPI_WR_BIT_ORDER_S 26 -/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured - in CONF state.*/ -#define SPI_RD_BIT_ORDER (BIT(25)) -#define SPI_RD_BIT_ORDER_M (BIT(25)) -#define SPI_RD_BIT_ORDER_V 0x1 -#define SPI_RD_BIT_ORDER_S 25 +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con +figured in CONF state..*/ +#define SPI_WR_BIT_ORDER 0x00000003 +#define SPI_WR_BIT_ORDER_M ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S)) +#define SPI_WR_BIT_ORDER_V 0x3 +#define SPI_WR_BIT_ORDER_S 25 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s +tate..*/ +#define SPI_RD_BIT_ORDER 0x00000003 +#define SPI_RD_BIT_ORDER_M ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S)) +#define SPI_RD_BIT_ORDER_V 0x3 +#define SPI_RD_BIT_ORDER_S 23 /* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: Write protect signal output when SPI is idle. 1: output high - 0: output low. Can be configured in CONF state.*/ -#define SPI_WP_POL (BIT(21)) -#define SPI_WP_POL_M (BIT(21)) -#define SPI_WP_POL_V 0x1 -#define SPI_WP_POL_S 21 +/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low. C +an be configured in CONF state..*/ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (BIT(21)) +#define SPI_WP_POL_V 0x1 +#define SPI_WP_POL_S 21 /* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: SPI_HOLD output value when SPI is idle. 1: output high 0: output - low. Can be configured in CONF state.*/ -#define SPI_HOLD_POL (BIT(20)) -#define SPI_HOLD_POL_M (BIT(20)) -#define SPI_HOLD_POL_V 0x1 -#define SPI_HOLD_POL_S 20 +/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co +nfigured in CONF state..*/ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (BIT(20)) +#define SPI_HOLD_POL_V 0x1 +#define SPI_HOLD_POL_S 20 /* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ -/*description: The bit is used to set MOSI line polarity 1: high 0 low. Can - be configured in CONF state.*/ -#define SPI_D_POL (BIT(19)) -#define SPI_D_POL_M (BIT(19)) -#define SPI_D_POL_V 0x1 -#define SPI_D_POL_S 19 +/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in +CONF state..*/ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (BIT(19)) +#define SPI_D_POL_V 0x1 +#define SPI_D_POL_S 19 /* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: The bit is used to set MISO line polarity 1: high 0 low. Can - be configured in CONF state.*/ -#define SPI_Q_POL (BIT(18)) -#define SPI_Q_POL_M (BIT(18)) -#define SPI_Q_POL_V 0x1 -#define SPI_Q_POL_S 18 +/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in +CONF state..*/ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (BIT(18)) +#define SPI_Q_POL_V 0x1 +#define SPI_Q_POL_S 18 /* SPI_FREAD_OCT : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 8 signals. 1: enable - 0: disable. Can be configured in CONF state.*/ -#define SPI_FREAD_OCT (BIT(16)) -#define SPI_FREAD_OCT_M (BIT(16)) -#define SPI_FREAD_OCT_V 0x1 -#define SPI_FREAD_OCT_S 16 +/*description: In the read operations read-data phase apply 8 signals. 1: enable 0: disable. C +an be configured in CONF state..*/ +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (BIT(16)) +#define SPI_FREAD_OCT_V 0x1 +#define SPI_FREAD_OCT_S 16 /* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 4 signals. 1: enable - 0: disable. Can be configured in CONF state.*/ -#define SPI_FREAD_QUAD (BIT(15)) -#define SPI_FREAD_QUAD_M (BIT(15)) -#define SPI_FREAD_QUAD_V 0x1 -#define SPI_FREAD_QUAD_S 15 +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable. C +an be configured in CONF state..*/ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (BIT(15)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 15 /* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 2 signals. 1: enable - 0: disable. Can be configured in CONF state.*/ -#define SPI_FREAD_DUAL (BIT(14)) -#define SPI_FREAD_DUAL_M (BIT(14)) -#define SPI_FREAD_DUAL_V 0x1 -#define SPI_FREAD_DUAL_S 14 +/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C +an be configured in CONF state..*/ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (BIT(14)) +#define SPI_FREAD_DUAL_V 0x1 +#define SPI_FREAD_DUAL_S 14 /* SPI_FCMD_OCT : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Apply 8 signals during command phase 1:enable 0: disable. Can - be configured in CONF state.*/ -#define SPI_FCMD_OCT (BIT(10)) -#define SPI_FCMD_OCT_M (BIT(10)) -#define SPI_FCMD_OCT_V 0x1 -#define SPI_FCMD_OCT_S 10 +/*description: Apply 8 signals during command phase 1:enable 0: disable. Can be configured in C +ONF state..*/ +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (BIT(10)) +#define SPI_FCMD_OCT_V 0x1 +#define SPI_FCMD_OCT_S 10 /* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Apply 4 signals during command phase 1:enable 0: disable. Can - be configured in CONF state.*/ -#define SPI_FCMD_QUAD (BIT(9)) -#define SPI_FCMD_QUAD_M (BIT(9)) -#define SPI_FCMD_QUAD_V 0x1 -#define SPI_FCMD_QUAD_S 9 +/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C +ONF state..*/ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (BIT(9)) +#define SPI_FCMD_QUAD_V 0x1 +#define SPI_FCMD_QUAD_S 9 /* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Apply 2 signals during command phase 1:enable 0: disable. Can - be configured in CONF state.*/ -#define SPI_FCMD_DUAL (BIT(8)) -#define SPI_FCMD_DUAL_M (BIT(8)) -#define SPI_FCMD_DUAL_V 0x1 -#define SPI_FCMD_DUAL_S 8 +/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C +ONF state..*/ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (BIT(8)) +#define SPI_FCMD_DUAL_V 0x1 +#define SPI_FCMD_DUAL_S 8 /* SPI_FADDR_OCT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be - configured in CONF state.*/ -#define SPI_FADDR_OCT (BIT(7)) -#define SPI_FADDR_OCT_M (BIT(7)) -#define SPI_FADDR_OCT_V 0x1 -#define SPI_FADDR_OCT_S 7 +/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + state..*/ +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (BIT(7)) +#define SPI_FADDR_OCT_V 0x1 +#define SPI_FADDR_OCT_S 7 /* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be - configured in CONF state.*/ -#define SPI_FADDR_QUAD (BIT(6)) -#define SPI_FADDR_QUAD_M (BIT(6)) -#define SPI_FADDR_QUAD_V 0x1 -#define SPI_FADDR_QUAD_S 6 +/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + state..*/ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (BIT(6)) +#define SPI_FADDR_QUAD_V 0x1 +#define SPI_FADDR_QUAD_S 6 /* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be - configured in CONF state.*/ -#define SPI_FADDR_DUAL (BIT(5)) -#define SPI_FADDR_DUAL_M (BIT(5)) -#define SPI_FADDR_DUAL_V 0x1 -#define SPI_FADDR_DUAL_S 5 +/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + state..*/ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (BIT(5)) +#define SPI_FADDR_DUAL_V 0x1 +#define SPI_FADDR_DUAL_S 5 /* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: In the dummy phase the signal level of spi is output by the spi - controller. Can be configured in CONF state.*/ -#define SPI_DUMMY_OUT (BIT(3)) -#define SPI_DUMMY_OUT_M (BIT(3)) -#define SPI_DUMMY_OUT_V 0x1 -#define SPI_DUMMY_OUT_S 3 +/*description: In the dummy phase the signal level of spi is output by the spi controller. Can +be configured in CONF state..*/ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (BIT(3)) +#define SPI_DUMMY_OUT_V 0x1 +#define SPI_DUMMY_OUT_S 3 -#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x00C) +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) /* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is - divided from system clock. Can be configured in CONF state.*/ -#define SPI_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_CLK_EQU_SYSCLK_V 0x1 -#define SPI_CLK_EQU_SYSCLK_S 31 -/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ -/*description: In the master mode it is pre-divider of spi_clk. Can be configured - in CONF state.*/ -#define SPI_CLKDIV_PRE 0x00001FFF -#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V) << (SPI_CLKDIV_PRE_S)) -#define SPI_CLKDIV_PRE_V 0x1FFF -#define SPI_CLKDIV_PRE_S 18 +/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst +em clock. Can be configured in CONF state..*/ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_V 0x1 +#define SPI_CLK_EQU_SYSCLK_S 31 +/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */ +/*description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF stat +e..*/ +#define SPI_CLKDIV_PRE 0x0000000F +#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) +#define SPI_CLKDIV_PRE_V 0xF +#define SPI_CLKDIV_PRE_S 18 /* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ -/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency - is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ -#define SPI_CLKCNT_N 0x0000003F -#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V) << (SPI_CLKCNT_N_S)) -#define SPI_CLKCNT_N_V 0x3F -#define SPI_CLKCNT_N_S 12 +/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/ +(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/ +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) +#define SPI_CLKCNT_N_V 0x3F +#define SPI_CLKCNT_N_S 12 /* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ -/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In - the slave mode it must be 0. Can be configured in CONF state.*/ -#define SPI_CLKCNT_H 0x0000003F -#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V) << (SPI_CLKCNT_H_S)) -#define SPI_CLKCNT_H_V 0x3F -#define SPI_CLKCNT_H_S 6 +/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it +must be 0. Can be configured in CONF state..*/ +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) +#define SPI_CLKCNT_H_V 0x3F +#define SPI_CLKCNT_H_S 6 /* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ -/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave - mode it must be 0. Can be configured in CONF state.*/ -#define SPI_CLKCNT_L 0x0000003F -#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V) << (SPI_CLKCNT_L_S)) -#define SPI_CLKCNT_L_V 0x3F -#define SPI_CLKCNT_L_S 0 +/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b +e 0. Can be configured in CONF state..*/ +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) +#define SPI_CLKCNT_L_V 0x3F +#define SPI_CLKCNT_L_S 0 -#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x010) +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation. Can be configured - in CONF state.*/ -#define SPI_USR_COMMAND (BIT(31)) -#define SPI_USR_COMMAND_M (BIT(31)) -#define SPI_USR_COMMAND_V 0x1 -#define SPI_USR_COMMAND_S 31 +/*description: This bit enable the command phase of an operation. Can be configured in CONF sta +te..*/ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (BIT(31)) +#define SPI_USR_COMMAND_V 0x1 +#define SPI_USR_COMMAND_S 31 /* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation. Can be configured - in CONF state.*/ -#define SPI_USR_ADDR (BIT(30)) -#define SPI_USR_ADDR_M (BIT(30)) -#define SPI_USR_ADDR_V 0x1 -#define SPI_USR_ADDR_S 30 +/*description: This bit enable the address phase of an operation. Can be configured in CONF sta +te..*/ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (BIT(30)) +#define SPI_USR_ADDR_V 0x1 +#define SPI_USR_ADDR_S 30 /* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: This bit enable the dummy phase of an operation. Can be configured - in CONF state.*/ -#define SPI_USR_DUMMY (BIT(29)) -#define SPI_USR_DUMMY_M (BIT(29)) -#define SPI_USR_DUMMY_V 0x1 -#define SPI_USR_DUMMY_S 29 +/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state +..*/ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (BIT(29)) +#define SPI_USR_DUMMY_V 0x1 +#define SPI_USR_DUMMY_S 29 /* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: This bit enable the read-data phase of an operation. Can be configured - in CONF state.*/ -#define SPI_USR_MISO (BIT(28)) -#define SPI_USR_MISO_M (BIT(28)) -#define SPI_USR_MISO_V 0x1 -#define SPI_USR_MISO_S 28 +/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s +tate..*/ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (BIT(28)) +#define SPI_USR_MISO_V 0x1 +#define SPI_USR_MISO_S 28 /* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This bit enable the write-data phase of an operation. Can be - configured in CONF state.*/ -#define SPI_USR_MOSI (BIT(27)) -#define SPI_USR_MOSI_M (BIT(27)) -#define SPI_USR_MOSI_V 0x1 -#define SPI_USR_MOSI_S 27 +/*description: This bit enable the write-data phase of an operation. Can be configured in CONF +state..*/ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (BIT(27)) +#define SPI_USR_MOSI_V 0x1 +#define SPI_USR_MOSI_S 27 /* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: spi clock is disable in dummy phase when the bit is enable. Can - be configured in CONF state.*/ -#define SPI_USR_DUMMY_IDLE (BIT(26)) -#define SPI_USR_DUMMY_IDLE_M (BIT(26)) -#define SPI_USR_DUMMY_IDLE_V 0x1 -#define SPI_USR_DUMMY_IDLE_S 26 +/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in + CONF state..*/ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_USR_DUMMY_IDLE_V 0x1 +#define SPI_USR_DUMMY_IDLE_S 26 /* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable. Can be configured in CONF state.*/ -#define SPI_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) -#define SPI_USR_MOSI_HIGHPART_V 0x1 -#define SPI_USR_MOSI_HIGHPART_S 25 +/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl +e 0: disable. Can be configured in CONF state..*/ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_V 0x1 +#define SPI_USR_MOSI_HIGHPART_S 25 /* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable. Can be configured in CONF state.*/ -#define SPI_USR_MISO_HIGHPART (BIT(24)) -#define SPI_USR_MISO_HIGHPART_M (BIT(24)) -#define SPI_USR_MISO_HIGHPART_V 0x1 -#define SPI_USR_MISO_HIGHPART_S 24 +/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + 0: disable. Can be configured in CONF state..*/ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_USR_MISO_HIGHPART_V 0x1 +#define SPI_USR_MISO_HIGHPART_S 24 /* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set the bit to enable 3-line half duplex communication mosi and - miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ -#define SPI_SIO (BIT(17)) -#define SPI_SIO_M (BIT(17)) -#define SPI_SIO_V 0x1 -#define SPI_SIO_S 17 +/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha +re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (BIT(17)) +#define SPI_SIO_V 0x1 +#define SPI_SIO_S 17 /* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 1: Enable the DMA CONF phase of next seg-trans operation which - means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ -#define SPI_USR_CONF_NXT (BIT(15)) -#define SPI_USR_CONF_NXT_M (BIT(15)) -#define SPI_USR_CONF_NXT_V 0x1 -#define SPI_USR_CONF_NXT_S 15 +/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans +will continue. 0: The seg-trans will end after the current SPI seg-trans or this + is not seg-trans mode. Can be configured in CONF state..*/ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (BIT(15)) +#define SPI_USR_CONF_NXT_V 0x1 +#define SPI_USR_CONF_NXT_S 15 /* SPI_FWRITE_OCT : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 8 signals. Can - be configured in CONF state.*/ -#define SPI_FWRITE_OCT (BIT(14)) -#define SPI_FWRITE_OCT_M (BIT(14)) -#define SPI_FWRITE_OCT_V 0x1 -#define SPI_FWRITE_OCT_S 14 +/*description: In the write operations read-data phase apply 8 signals. Can be configured in CO +NF state..*/ +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (BIT(14)) +#define SPI_FWRITE_OCT_V 0x1 +#define SPI_FWRITE_OCT_S 14 /* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 4 signals. Can - be configured in CONF state.*/ -#define SPI_FWRITE_QUAD (BIT(13)) -#define SPI_FWRITE_QUAD_M (BIT(13)) -#define SPI_FWRITE_QUAD_V 0x1 -#define SPI_FWRITE_QUAD_S 13 +/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO +NF state..*/ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (BIT(13)) +#define SPI_FWRITE_QUAD_V 0x1 +#define SPI_FWRITE_QUAD_S 13 /* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 2 signals. Can - be configured in CONF state.*/ -#define SPI_FWRITE_DUAL (BIT(12)) -#define SPI_FWRITE_DUAL_M (BIT(12)) -#define SPI_FWRITE_DUAL_V 0x1 -#define SPI_FWRITE_DUAL_S 12 +/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO +NF state..*/ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (BIT(12)) +#define SPI_FWRITE_DUAL_V 0x1 +#define SPI_FWRITE_DUAL_S 12 /* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal - delay mode. Can be configured in CONF state.*/ -#define SPI_CK_OUT_EDGE (BIT(9)) -#define SPI_CK_OUT_EDGE_M (BIT(9)) -#define SPI_CK_OUT_EDGE_V 0x1 -#define SPI_CK_OUT_EDGE_S 9 +/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca +n be configured in CONF state..*/ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (BIT(9)) +#define SPI_CK_OUT_EDGE_V 0x1 +#define SPI_CK_OUT_EDGE_S 9 /* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: In the slave mode this bit can be used to change the polarity - of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ -#define SPI_RSCK_I_EDGE (BIT(8)) -#define SPI_RSCK_I_EDGE_M (BIT(8)) -#define SPI_RSCK_I_EDGE_V 0x1 -#define SPI_RSCK_I_EDGE_S 8 +/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck += !spi_ck_i. 1:rsck = spi_ck_i..*/ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (BIT(8)) +#define SPI_RSCK_I_EDGE_V 0x1 +#define SPI_RSCK_I_EDGE_S 8 /* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: - disable. Can be configured in CONF state.*/ -#define SPI_CS_SETUP (BIT(7)) -#define SPI_CS_SETUP_M (BIT(7)) -#define SPI_CS_SETUP_V 0x1 -#define SPI_CS_SETUP_S 7 +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be co +nfigured in CONF state..*/ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (BIT(7)) +#define SPI_CS_SETUP_V 0x1 +#define SPI_CS_SETUP_S 7 /* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable. - Can be configured in CONF state.*/ -#define SPI_CS_HOLD (BIT(6)) -#define SPI_CS_HOLD_M (BIT(6)) -#define SPI_CS_HOLD_V 0x1 -#define SPI_CS_HOLD_S 6 +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be config +ured in CONF state..*/ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (BIT(6)) +#define SPI_CS_HOLD_V 0x1 +#define SPI_CS_HOLD_S 6 /* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: In the slave mode this bit can be used to change the polarity - of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ -#define SPI_TSCK_I_EDGE (BIT(5)) -#define SPI_TSCK_I_EDGE_M (BIT(5)) -#define SPI_TSCK_I_EDGE_V 0x1 -#define SPI_TSCK_I_EDGE_S 5 +/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck += spi_ck_i. 1:tsck = !spi_ck_i..*/ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (BIT(5)) +#define SPI_TSCK_I_EDGE_V 0x1 +#define SPI_TSCK_I_EDGE_S 5 /* SPI_OPI_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Just for master mode. 1: spi controller is in OPI mode (all in - 8-b-m). 0: others. Can be configured in CONF state.*/ -#define SPI_OPI_MODE (BIT(4)) -#define SPI_OPI_MODE_M (BIT(4)) -#define SPI_OPI_MODE_V 0x1 -#define SPI_OPI_MODE_S 4 -/* SPI_QPI_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Both for master mode and slave mode. 1: spi controller is in - QPI mode. 0: others. Can be configured in CONF state.*/ -#define SPI_QPI_MODE (BIT(3)) -#define SPI_QPI_MODE_M (BIT(3)) -#define SPI_QPI_MODE_V 0x1 -#define SPI_QPI_MODE_S 3 +/*description: Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others +. Can be configured in CONF state..*/ +#define SPI_OPI_MODE (BIT(4)) +#define SPI_OPI_MODE_M (BIT(4)) +#define SPI_OPI_MODE_V 0x1 +#define SPI_OPI_MODE_S 4 +/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others +. Can be configured in CONF state..*/ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (BIT(3)) +#define SPI_QPI_MODE_V 0x1 +#define SPI_QPI_MODE_S 3 /* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set the bit to enable full duplex communication. 1: enable 0: - disable. Can be configured in CONF state.*/ -#define SPI_DOUTDIN (BIT(0)) -#define SPI_DOUTDIN_M (BIT(0)) -#define SPI_DOUTDIN_V 0x1 -#define SPI_DOUTDIN_S 0 +/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co +nfigured in CONF state..*/ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (BIT(0)) +#define SPI_DOUTDIN_V 0x1 +#define SPI_DOUTDIN_S 0 -#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x014) +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) /* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */ -/*description: The length in bits of address phase. The register value shall - be (bit_num-1). Can be configured in CONF state.*/ -#define SPI_USR_ADDR_BITLEN 0x0000001F -#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V) << (SPI_USR_ADDR_BITLEN_S)) -#define SPI_USR_ADDR_BITLEN_V 0x1F -#define SPI_USR_ADDR_BITLEN_S 27 +/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca +n be configured in CONF state..*/ +#define SPI_USR_ADDR_BITLEN 0x0000001F +#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) +#define SPI_USR_ADDR_BITLEN_V 0x1F +#define SPI_USR_ADDR_BITLEN_S 27 /* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */ -/*description: delay cycles of cs pin by spi clock this bits are combined with - spi_cs_hold bit. Can be configured in CONF state.*/ -#define SPI_CS_HOLD_TIME 0x0000001F -#define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V) << (SPI_CS_HOLD_TIME_S)) -#define SPI_CS_HOLD_TIME_V 0x1F -#define SPI_CS_HOLD_TIME_S 22 +/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + Can be configured in CONF state..*/ +#define SPI_CS_HOLD_TIME 0x0000001F +#define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S)) +#define SPI_CS_HOLD_TIME_V 0x1F +#define SPI_CS_HOLD_TIME_S 22 /* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ -/*description: (cycles+1) of prepare phase by spi clock this bits are combined - with spi_cs_setup bit. Can be configured in CONF state.*/ -#define SPI_CS_SETUP_TIME 0x0000001F -#define SPI_CS_SETUP_TIME_M ((SPI_CS_SETUP_TIME_V) << (SPI_CS_SETUP_TIME_S)) -#define SPI_CS_SETUP_TIME_V 0x1F -#define SPI_CS_SETUP_TIME_S 17 +/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu +p bit. Can be configured in CONF state..*/ +#define SPI_CS_SETUP_TIME 0x0000001F +#define SPI_CS_SETUP_TIME_M ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S)) +#define SPI_CS_SETUP_TIME_V 0x1F +#define SPI_CS_SETUP_TIME_S 17 +/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid + in GP-SPI master FD/HD-mode..*/ +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_V 0x1 +#define SPI_MST_WFULL_ERR_END_EN_S 16 /* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ -/*description: The length in spi_clk cycles of dummy phase. The register value - shall be (cycle_num-1). Can be configured in CONF state.*/ -#define SPI_USR_DUMMY_CYCLELEN 0x000000FF -#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V) << (SPI_USR_DUMMY_CYCLELEN_S)) -#define SPI_USR_DUMMY_CYCLELEN_V 0xFF -#define SPI_USR_DUMMY_CYCLELEN_S 0 +/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_ +num-1). Can be configured in CONF state..*/ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) +#define SPI_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_USR_DUMMY_CYCLELEN_S 0 -#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x018) +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18) /* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ -/*description: The length in bits of command phase. The register value shall - be (bit_num-1). Can be configured in CONF state.*/ -#define SPI_USR_COMMAND_BITLEN 0x0000000F -#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V) << (SPI_USR_COMMAND_BITLEN_S)) -#define SPI_USR_COMMAND_BITLEN_V 0xF -#define SPI_USR_COMMAND_BITLEN_S 28 +/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca +n be configured in CONF state..*/ +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) +#define SPI_USR_COMMAND_BITLEN_V 0xF +#define SPI_USR_COMMAND_BITLEN_S 28 +/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m +aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro +r is valid in GP-SPI master FD/HD-mode..*/ +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x1 +#define SPI_MST_REMPTY_ERR_END_EN_S 27 /* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: The value of command. Can be configured in CONF state.*/ -#define SPI_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V) << (SPI_USR_COMMAND_VALUE_S)) -#define SPI_USR_COMMAND_VALUE_V 0xFFFF -#define SPI_USR_COMMAND_VALUE_S 0 +/*description: The value of command. Can be configured in CONF state..*/ +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) +#define SPI_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_USR_COMMAND_VALUE_S 0 -#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x01C) +#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1C) /* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: The value of these bits is the configured SPI transmission data - bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ -#define SPI_MS_DATA_BITLEN 0x0003FFFF -#define SPI_MS_DATA_BITLEN_M ((SPI_MS_DATA_BITLEN_V) << (SPI_MS_DATA_BITLEN_S)) -#define SPI_MS_DATA_BITLEN_V 0x3FFFF -#define SPI_MS_DATA_BITLEN_S 0 +/*description: The value of these bits is the configured SPI transmission data bit length in ma +ster mode DMA controlled transfer or CPU controlled transfer. The value is also +the configured bit length in slave mode DMA RX controlled transfer. The register + value shall be (bit_num-1). Can be configured in CONF state..*/ +#define SPI_MS_DATA_BITLEN 0x0003FFFF +#define SPI_MS_DATA_BITLEN_M ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S)) +#define SPI_MS_DATA_BITLEN_V 0x3FFFF +#define SPI_MS_DATA_BITLEN_S 0 -#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x020) +#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) /* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: spi quad input swap enable 0: spi quad input swap disable. - Can be configured in CONF state.*/ -#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) -#define SPI_QUAD_DIN_PIN_SWAP_M (BIT(31)) -#define SPI_QUAD_DIN_PIN_SWAP_V 0x1 -#define SPI_QUAD_DIN_PIN_SWAP_S 31 +/*description: 1: spi quad input swap enable 0: spi quad input swap disable. Can be configur +ed in CONF state..*/ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x1 +#define SPI_QUAD_DIN_PIN_SWAP_S 31 /* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: spi cs line keep low when the bit is set. Can be configured in CONF state.*/ -#define SPI_CS_KEEP_ACTIVE (BIT(30)) -#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) -#define SPI_CS_KEEP_ACTIVE_V 0x1 -#define SPI_CS_KEEP_ACTIVE_S 30 +/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_V 0x1 +#define SPI_CS_KEEP_ACTIVE_S 30 /* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 1: spi clk line is high when idle 0: spi clk line is low - when idle. Can be configured in CONF state.*/ -#define SPI_CK_IDLE_EDGE (BIT(29)) -#define SPI_CK_IDLE_EDGE_M (BIT(29)) -#define SPI_CK_IDLE_EDGE_V 0x1 -#define SPI_CK_IDLE_EDGE_S 29 +/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be c +onfigured in CONF state..*/ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (BIT(29)) +#define SPI_CK_IDLE_EDGE_V 0x1 +#define SPI_CK_IDLE_EDGE_S 29 /* SPI_DQS_IDLE_EDGE : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: The default value of spi_dqs. Can be configured in CONF state.*/ -#define SPI_DQS_IDLE_EDGE (BIT(24)) -#define SPI_DQS_IDLE_EDGE_M (BIT(24)) -#define SPI_DQS_IDLE_EDGE_V 0x1 -#define SPI_DQS_IDLE_EDGE_S 24 +/*description: The default value of spi_dqs. Can be configured in CONF state..*/ +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (BIT(24)) +#define SPI_DQS_IDLE_EDGE_V 0x1 +#define SPI_DQS_IDLE_EDGE_S 24 /* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: spi slave input cs polarity select. 1: inv 0: not change. Can - be configured in CONF state.*/ -#define SPI_SLAVE_CS_POL (BIT(23)) -#define SPI_SLAVE_CS_POL_M (BIT(23)) -#define SPI_SLAVE_CS_POL_V 0x1 -#define SPI_SLAVE_CS_POL_S 23 +/*description: spi slave input cs polarity select. 1: inv 0: not change. Can be configured in +CONF state..*/ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (BIT(23)) +#define SPI_SLAVE_CS_POL_V 0x1 +#define SPI_SLAVE_CS_POL_S 23 /* SPI_CMD_DTR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including - master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/ -#define SPI_CMD_DTR_EN (BIT(19)) -#define SPI_CMD_DTR_EN_M (BIT(19)) -#define SPI_CMD_DTR_EN_V 0x1 -#define SPI_CMD_DTR_EN_S 19 +/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/ +4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be confi +gured in CONF state..*/ +#define SPI_CMD_DTR_EN (BIT(19)) +#define SPI_CMD_DTR_EN_M (BIT(19)) +#define SPI_CMD_DTR_EN_V 0x1 +#define SPI_CMD_DTR_EN_S 19 /* SPI_ADDR_DTR_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including - master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/ -#define SPI_ADDR_DTR_EN (BIT(18)) -#define SPI_ADDR_DTR_EN_M (BIT(18)) -#define SPI_ADDR_DTR_EN_V 0x1 -#define SPI_ADDR_DTR_EN_S 18 +/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2 +/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be co +nfigured in CONF state..*/ +#define SPI_ADDR_DTR_EN (BIT(18)) +#define SPI_ADDR_DTR_EN_M (BIT(18)) +#define SPI_ADDR_DTR_EN_V 0x1 +#define SPI_ADDR_DTR_EN_S 18 /* SPI_DATA_DTR_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR - mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/ -#define SPI_DATA_DTR_EN (BIT(17)) -#define SPI_DATA_DTR_EN_M (BIT(17)) -#define SPI_DATA_DTR_EN_V 0x1 -#define SPI_DATA_DTR_EN_S 17 +/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including mas +ter 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR m +ode. Can be configured in CONF state..*/ +#define SPI_DATA_DTR_EN (BIT(17)) +#define SPI_DATA_DTR_EN_M (BIT(17)) +#define SPI_DATA_DTR_EN_V 0x1 +#define SPI_DATA_DTR_EN_S 17 /* SPI_CLK_DATA_DTR_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: 1: SPI master DTR mode is applied to SPI clk data and spi_dqs. - 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.*/ -#define SPI_CLK_DATA_DTR_EN (BIT(16)) -#define SPI_CLK_DATA_DTR_EN_M (BIT(16)) -#define SPI_CLK_DATA_DTR_EN_V 0x1 -#define SPI_CLK_DATA_DTR_EN_S 16 +/*description: 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master D +TR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. .*/ +#define SPI_CLK_DATA_DTR_EN (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_M (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_V 0x1 +#define SPI_CLK_DATA_DTR_EN_S 16 /* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */ -/*description: In the master mode the bits are the polarity of spi cs line - the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ -#define SPI_MASTER_CS_POL 0x0000003F -#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V) << (SPI_MASTER_CS_POL_S)) -#define SPI_MASTER_CS_POL_V 0x3F -#define SPI_MASTER_CS_POL_S 7 +/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva +lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/ +#define SPI_MASTER_CS_POL 0x0000003F +#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) +#define SPI_MASTER_CS_POL_V 0x3F +#define SPI_MASTER_CS_POL_S 7 /* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/ -#define SPI_CK_DIS (BIT(6)) -#define SPI_CK_DIS_M (BIT(6)) -#define SPI_CK_DIS_V 0x1 -#define SPI_CK_DIS_S 6 +/*description: 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state..*/ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (BIT(6)) +#define SPI_CK_DIS_V 0x1 +#define SPI_CK_DIS_S 6 /* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to - CS$n pin. Can be configured in CONF state.*/ -#define SPI_CS5_DIS (BIT(5)) -#define SPI_CS5_DIS_M (BIT(5)) -#define SPI_CS5_DIS_V 0x1 -#define SPI_CS5_DIS_S 5 +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (BIT(5)) +#define SPI_CS5_DIS_V 0x1 +#define SPI_CS5_DIS_S 5 /* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to - CS$n pin. Can be configured in CONF state.*/ -#define SPI_CS4_DIS (BIT(4)) -#define SPI_CS4_DIS_M (BIT(4)) -#define SPI_CS4_DIS_V 0x1 -#define SPI_CS4_DIS_S 4 +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (BIT(4)) +#define SPI_CS4_DIS_V 0x1 +#define SPI_CS4_DIS_S 4 /* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to - CS$n pin. Can be configured in CONF state.*/ -#define SPI_CS3_DIS (BIT(3)) -#define SPI_CS3_DIS_M (BIT(3)) -#define SPI_CS3_DIS_V 0x1 -#define SPI_CS3_DIS_S 3 +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (BIT(3)) +#define SPI_CS3_DIS_V 0x1 +#define SPI_CS3_DIS_S 3 /* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to - CS$n pin. Can be configured in CONF state.*/ -#define SPI_CS2_DIS (BIT(2)) -#define SPI_CS2_DIS_M (BIT(2)) -#define SPI_CS2_DIS_V 0x1 -#define SPI_CS2_DIS_S 2 +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (BIT(2)) +#define SPI_CS2_DIS_V 0x1 +#define SPI_CS2_DIS_S 2 /* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to - CS$n pin. Can be configured in CONF state.*/ -#define SPI_CS1_DIS (BIT(1)) -#define SPI_CS1_DIS_M (BIT(1)) -#define SPI_CS1_DIS_V 0x1 -#define SPI_CS1_DIS_S 1 +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (BIT(1)) +#define SPI_CS1_DIS_V 0x1 +#define SPI_CS1_DIS_S 1 /* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to - CS$n pin. Can be configured in CONF state.*/ -#define SPI_CS0_DIS (BIT(0)) -#define SPI_CS0_DIS_M (BIT(0)) -#define SPI_CS0_DIS_V 0x1 -#define SPI_CS0_DIS_S 0 +/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca +n be configured in CONF state..*/ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (BIT(0)) +#define SPI_CS0_DIS_V 0x1 +#define SPI_CS0_DIS_S 0 -#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x024) +#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) /* SPI_TIMING_HCLK_ACTIVE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: 1:enable hclk in SPI input timing module. 0: disable it. Can - be configured in CONF state.*/ -#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) -#define SPI_TIMING_HCLK_ACTIVE_M (BIT(16)) -#define SPI_TIMING_HCLK_ACTIVE_V 0x1 -#define SPI_TIMING_HCLK_ACTIVE_S 16 +/*description: 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in C +ONF state..*/ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_V 0x1 +#define SPI_TIMING_HCLK_ACTIVE_S 16 /* SPI_DIN7_MODE : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ -#define SPI_DIN7_MODE 0x00000003 -#define SPI_DIN7_MODE_M ((SPI_DIN7_MODE_V) << (SPI_DIN7_MODE_S)) -#define SPI_DIN7_MODE_V 0x3 -#define SPI_DIN7_MODE_S 14 +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN7_MODE 0x00000003 +#define SPI_DIN7_MODE_M ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S)) +#define SPI_DIN7_MODE_V 0x3 +#define SPI_DIN7_MODE_S 14 /* SPI_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ -#define SPI_DIN6_MODE 0x00000003 -#define SPI_DIN6_MODE_M ((SPI_DIN6_MODE_V) << (SPI_DIN6_MODE_S)) -#define SPI_DIN6_MODE_V 0x3 -#define SPI_DIN6_MODE_S 12 +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN6_MODE 0x00000003 +#define SPI_DIN6_MODE_M ((SPI_DIN6_MODE_V)<<(SPI_DIN6_MODE_S)) +#define SPI_DIN6_MODE_V 0x3 +#define SPI_DIN6_MODE_S 12 /* SPI_DIN5_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ -#define SPI_DIN5_MODE 0x00000003 -#define SPI_DIN5_MODE_M ((SPI_DIN5_MODE_V) << (SPI_DIN5_MODE_S)) -#define SPI_DIN5_MODE_V 0x3 -#define SPI_DIN5_MODE_S 10 +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN5_MODE 0x00000003 +#define SPI_DIN5_MODE_M ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S)) +#define SPI_DIN5_MODE_V 0x3 +#define SPI_DIN5_MODE_S 10 /* SPI_DIN4_MODE : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ -#define SPI_DIN4_MODE 0x00000003 -#define SPI_DIN4_MODE_M ((SPI_DIN4_MODE_V) << (SPI_DIN4_MODE_S)) -#define SPI_DIN4_MODE_V 0x3 -#define SPI_DIN4_MODE_S 8 +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN4_MODE 0x00000003 +#define SPI_DIN4_MODE_M ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S)) +#define SPI_DIN4_MODE_V 0x3 +#define SPI_DIN4_MODE_S 8 /* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ -#define SPI_DIN3_MODE 0x00000003 -#define SPI_DIN3_MODE_M ((SPI_DIN3_MODE_V) << (SPI_DIN3_MODE_S)) -#define SPI_DIN3_MODE_V 0x3 -#define SPI_DIN3_MODE_S 6 +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN3_MODE 0x00000003 +#define SPI_DIN3_MODE_M ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S)) +#define SPI_DIN3_MODE_V 0x3 +#define SPI_DIN3_MODE_S 6 /* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ -#define SPI_DIN2_MODE 0x00000003 -#define SPI_DIN2_MODE_M ((SPI_DIN2_MODE_V) << (SPI_DIN2_MODE_S)) -#define SPI_DIN2_MODE_V 0x3 -#define SPI_DIN2_MODE_S 4 +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN2_MODE 0x00000003 +#define SPI_DIN2_MODE_M ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S)) +#define SPI_DIN2_MODE_V 0x3 +#define SPI_DIN2_MODE_S 4 /* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ -#define SPI_DIN1_MODE 0x00000003 -#define SPI_DIN1_MODE_M ((SPI_DIN1_MODE_V) << (SPI_DIN1_MODE_S)) -#define SPI_DIN1_MODE_V 0x3 -#define SPI_DIN1_MODE_S 2 +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN1_MODE 0x00000003 +#define SPI_DIN1_MODE_M ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S)) +#define SPI_DIN1_MODE_V 0x3 +#define SPI_DIN1_MODE_S 2 /* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ -#define SPI_DIN0_MODE 0x00000003 -#define SPI_DIN0_MODE_M ((SPI_DIN0_MODE_V) << (SPI_DIN0_MODE_S)) -#define SPI_DIN0_MODE_V 0x3 -#define SPI_DIN0_MODE_S 0 +/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay +ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: + input with the spi_clk. Can be configured in CONF state..*/ +#define SPI_DIN0_MODE 0x00000003 +#define SPI_DIN0_MODE_M ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S)) +#define SPI_DIN0_MODE_V 0x3 +#define SPI_DIN0_MODE_S 0 -#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x028) +#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28) /* SPI_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ -#define SPI_DIN7_NUM 0x00000003 -#define SPI_DIN7_NUM_M ((SPI_DIN7_NUM_V) << (SPI_DIN7_NUM_S)) -#define SPI_DIN7_NUM_V 0x3 -#define SPI_DIN7_NUM_S 14 +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN7_NUM 0x00000003 +#define SPI_DIN7_NUM_M ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S)) +#define SPI_DIN7_NUM_V 0x3 +#define SPI_DIN7_NUM_S 14 /* SPI_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ -#define SPI_DIN6_NUM 0x00000003 -#define SPI_DIN6_NUM_M ((SPI_DIN6_NUM_V) << (SPI_DIN6_NUM_S)) -#define SPI_DIN6_NUM_V 0x3 -#define SPI_DIN6_NUM_S 12 +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN6_NUM 0x00000003 +#define SPI_DIN6_NUM_M ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S)) +#define SPI_DIN6_NUM_V 0x3 +#define SPI_DIN6_NUM_S 12 /* SPI_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ -#define SPI_DIN5_NUM 0x00000003 -#define SPI_DIN5_NUM_M ((SPI_DIN5_NUM_V) << (SPI_DIN5_NUM_S)) -#define SPI_DIN5_NUM_V 0x3 -#define SPI_DIN5_NUM_S 10 +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN5_NUM 0x00000003 +#define SPI_DIN5_NUM_M ((SPI_DIN5_NUM_V)<<(SPI_DIN5_NUM_S)) +#define SPI_DIN5_NUM_V 0x3 +#define SPI_DIN5_NUM_S 10 /* SPI_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ -#define SPI_DIN4_NUM 0x00000003 -#define SPI_DIN4_NUM_M ((SPI_DIN4_NUM_V) << (SPI_DIN4_NUM_S)) -#define SPI_DIN4_NUM_V 0x3 -#define SPI_DIN4_NUM_S 8 +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN4_NUM 0x00000003 +#define SPI_DIN4_NUM_M ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S)) +#define SPI_DIN4_NUM_V 0x3 +#define SPI_DIN4_NUM_S 8 /* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ -#define SPI_DIN3_NUM 0x00000003 -#define SPI_DIN3_NUM_M ((SPI_DIN3_NUM_V) << (SPI_DIN3_NUM_S)) -#define SPI_DIN3_NUM_V 0x3 -#define SPI_DIN3_NUM_S 6 +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN3_NUM 0x00000003 +#define SPI_DIN3_NUM_M ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S)) +#define SPI_DIN3_NUM_V 0x3 +#define SPI_DIN3_NUM_S 6 /* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ -#define SPI_DIN2_NUM 0x00000003 -#define SPI_DIN2_NUM_M ((SPI_DIN2_NUM_V) << (SPI_DIN2_NUM_S)) -#define SPI_DIN2_NUM_V 0x3 -#define SPI_DIN2_NUM_S 4 +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN2_NUM 0x00000003 +#define SPI_DIN2_NUM_M ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S)) +#define SPI_DIN2_NUM_V 0x3 +#define SPI_DIN2_NUM_S 4 /* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ -#define SPI_DIN1_NUM 0x00000003 -#define SPI_DIN1_NUM_M ((SPI_DIN1_NUM_V) << (SPI_DIN1_NUM_S)) -#define SPI_DIN1_NUM_V 0x3 -#define SPI_DIN1_NUM_S 2 +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN1_NUM 0x00000003 +#define SPI_DIN1_NUM_M ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S)) +#define SPI_DIN1_NUM_V 0x3 +#define SPI_DIN1_NUM_S 2 /* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: the input signals are delayed by SPI module clock cycles 0: - delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ -#define SPI_DIN0_NUM 0x00000003 -#define SPI_DIN0_NUM_M ((SPI_DIN0_NUM_V) << (SPI_DIN0_NUM_S)) -#define SPI_DIN0_NUM_V 0x3 -#define SPI_DIN0_NUM_S 0 +/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, + 1: delayed by 2 cycles,... Can be configured in CONF state..*/ +#define SPI_DIN0_NUM 0x00000003 +#define SPI_DIN0_NUM_M ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S)) +#define SPI_DIN0_NUM_V 0x3 +#define SPI_DIN0_NUM_S 0 -#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x02C) +#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2C) /* SPI_D_DQS_MODE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The output signal SPI_DQS is delayed by the SPI module clock - 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_D_DQS_MODE (BIT(8)) -#define SPI_D_DQS_MODE_M (BIT(8)) -#define SPI_D_DQS_MODE_V 0x1 -#define SPI_D_DQS_MODE_S 8 +/*description: The output signal SPI_DQS is delayed by the SPI module clock, 0: output without +delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can +be configured in CONF state..*/ +#define SPI_D_DQS_MODE (BIT(8)) +#define SPI_D_DQS_MODE_M (BIT(8)) +#define SPI_D_DQS_MODE_V 0x1 +#define SPI_D_DQS_MODE_S 8 /* SPI_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The output signal $n is delayed by the SPI module clock 0: output - without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_DOUT7_MODE (BIT(7)) -#define SPI_DOUT7_MODE_M (BIT(7)) -#define SPI_DOUT7_MODE_V 0x1 -#define SPI_DOUT7_MODE_S 7 +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT7_MODE (BIT(7)) +#define SPI_DOUT7_MODE_M (BIT(7)) +#define SPI_DOUT7_MODE_V 0x1 +#define SPI_DOUT7_MODE_S 7 /* SPI_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The output signal $n is delayed by the SPI module clock 0: output - without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_DOUT6_MODE (BIT(6)) -#define SPI_DOUT6_MODE_M (BIT(6)) -#define SPI_DOUT6_MODE_V 0x1 -#define SPI_DOUT6_MODE_S 6 +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT6_MODE (BIT(6)) +#define SPI_DOUT6_MODE_M (BIT(6)) +#define SPI_DOUT6_MODE_V 0x1 +#define SPI_DOUT6_MODE_S 6 /* SPI_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The output signal $n is delayed by the SPI module clock 0: output - without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_DOUT5_MODE (BIT(5)) -#define SPI_DOUT5_MODE_M (BIT(5)) -#define SPI_DOUT5_MODE_V 0x1 -#define SPI_DOUT5_MODE_S 5 +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT5_MODE (BIT(5)) +#define SPI_DOUT5_MODE_M (BIT(5)) +#define SPI_DOUT5_MODE_V 0x1 +#define SPI_DOUT5_MODE_S 5 /* SPI_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The output signal $n is delayed by the SPI module clock 0: output - without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_DOUT4_MODE (BIT(4)) -#define SPI_DOUT4_MODE_M (BIT(4)) -#define SPI_DOUT4_MODE_V 0x1 -#define SPI_DOUT4_MODE_S 4 +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT4_MODE (BIT(4)) +#define SPI_DOUT4_MODE_M (BIT(4)) +#define SPI_DOUT4_MODE_V 0x1 +#define SPI_DOUT4_MODE_S 4 /* SPI_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The output signal $n is delayed by the SPI module clock 0: output - without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_DOUT3_MODE (BIT(3)) -#define SPI_DOUT3_MODE_M (BIT(3)) -#define SPI_DOUT3_MODE_V 0x1 -#define SPI_DOUT3_MODE_S 3 +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (BIT(3)) +#define SPI_DOUT3_MODE_V 0x1 +#define SPI_DOUT3_MODE_S 3 /* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The output signal $n is delayed by the SPI module clock 0: output - without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_DOUT2_MODE (BIT(2)) -#define SPI_DOUT2_MODE_M (BIT(2)) -#define SPI_DOUT2_MODE_V 0x1 -#define SPI_DOUT2_MODE_S 2 +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (BIT(2)) +#define SPI_DOUT2_MODE_V 0x1 +#define SPI_DOUT2_MODE_S 2 /* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The output signal $n is delayed by the SPI module clock 0: output - without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_DOUT1_MODE (BIT(1)) -#define SPI_DOUT1_MODE_M (BIT(1)) -#define SPI_DOUT1_MODE_V 0x1 -#define SPI_DOUT1_MODE_S 1 +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (BIT(1)) +#define SPI_DOUT1_MODE_V 0x1 +#define SPI_DOUT1_MODE_S 1 /* SPI_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The output signal $n is delayed by the SPI module clock 0: output - without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ -#define SPI_DOUT0_MODE (BIT(0)) -#define SPI_DOUT0_MODE_M (BIT(0)) -#define SPI_DOUT0_MODE_V 0x1 -#define SPI_DOUT0_MODE_S 0 +/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay +ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co +nfigured in CONF state..*/ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (BIT(0)) +#define SPI_DOUT0_MODE_V 0x1 +#define SPI_DOUT0_MODE_S 0 -#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x030) -/* SPI_DMA_AFIFO_RST : WO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Set this bit to reset DMA TX AFIFO which is used to send data - out in SPI slave DMA controlled mode transfer.*/ -#define SPI_DMA_AFIFO_RST (BIT(31)) -#define SPI_DMA_AFIFO_RST_M (BIT(31)) -#define SPI_DMA_AFIFO_RST_V 0x1 -#define SPI_DMA_AFIFO_RST_S 31 -/* SPI_BUF_AFIFO_RST : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to reset BUF TX AFIFO which is used send data out - in SPI slave CPU controlled mode transfer and master mode transfer.*/ -#define SPI_BUF_AFIFO_RST (BIT(30)) -#define SPI_BUF_AFIFO_RST_M (BIT(30)) -#define SPI_BUF_AFIFO_RST_V 0x1 -#define SPI_BUF_AFIFO_RST_S 30 -/* SPI_RX_AFIFO_RST : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to reset RX AFIFO which is used to receive data - in SPI master and slave mode transfer.*/ -#define SPI_RX_AFIFO_RST (BIT(29)) -#define SPI_RX_AFIFO_RST_M (BIT(29)) -#define SPI_RX_AFIFO_RST_V 0x1 -#define SPI_RX_AFIFO_RST_S 29 +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30) +/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave +DMA controlled mode transfer..*/ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (BIT(31)) +#define SPI_DMA_AFIFO_RST_V 0x1 +#define SPI_DMA_AFIFO_RST_S 31 +/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + controlled mode transfer and master mode transfer..*/ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (BIT(30)) +#define SPI_BUF_AFIFO_RST_V 0x1 +#define SPI_BUF_AFIFO_RST_S 30 +/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and +slave mode transfer..*/ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (BIT(29)) +#define SPI_RX_AFIFO_RST_V 0x1 +#define SPI_RX_AFIFO_RST_S 29 /* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to enable SPI DMA controlled send data mode.*/ -#define SPI_DMA_TX_ENA (BIT(28)) -#define SPI_DMA_TX_ENA_M (BIT(28)) -#define SPI_DMA_TX_ENA_V 0x1 -#define SPI_DMA_TX_ENA_S 28 +/*description: Set this bit to enable SPI DMA controlled send data mode..*/ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (BIT(28)) +#define SPI_DMA_TX_ENA_V 0x1 +#define SPI_DMA_TX_ENA_S 28 /* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: Set this bit to enable SPI DMA controlled receive data mode.*/ -#define SPI_DMA_RX_ENA (BIT(27)) -#define SPI_DMA_RX_ENA_M (BIT(27)) -#define SPI_DMA_RX_ENA_V 0x1 -#define SPI_DMA_RX_ENA_S 27 +/*description: Set this bit to enable SPI DMA controlled receive data mode..*/ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (BIT(27)) +#define SPI_DMA_RX_ENA_V 0x1 +#define SPI_DMA_RX_ENA_S 27 /* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data - bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ -#define SPI_RX_EOF_EN (BIT(21)) -#define SPI_RX_EOF_EN_M (BIT(21)) -#define SPI_RX_EOF_EN_V 0x1 -#define SPI_RX_EOF_EN_S 21 +/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t +o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_d +ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don +e in seg-trans..*/ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (BIT(21)) +#define SPI_RX_EOF_EN_V 0x1 +#define SPI_RX_EOF_EN_S 21 /* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: - spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ -#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) -#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (BIT(20)) -#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x1 -#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e +mpty_vld is cleared by spi_trans_done..*/ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x1 +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 /* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: - spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ -#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) -#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (BIT(19)) -#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x1 -#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full +_vld is cleared by spi_trans_done..*/ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x1 +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 /* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ -#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) -#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18)) -#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1 -#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1 +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat +a. 0: DMA RX FIFO is ready for receiving data..*/ +#define SPI_DMA_INFIFO_FULL (BIT(1)) +#define SPI_DMA_INFIFO_FULL_M (BIT(1)) +#define SPI_DMA_INFIFO_FULL_V 0x1 +#define SPI_DMA_INFIFO_FULL_S 1 +/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. + 0: DMA TX FIFO is ready for sending data..*/ +#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_M (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_S 0 -#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x034) -/* SPI_MST_TX_AFIFO_RERR_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_MST_TX_AFIFO_RERR_INT_ENA (BIT(21)) -#define SPI_MST_TX_AFIFO_RERR_INT_ENA_M (BIT(21)) -#define SPI_MST_TX_AFIFO_RERR_INT_ENA_V 0x1 -#define SPI_MST_TX_AFIFO_RERR_INT_ENA_S 21 -/* SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA (BIT(20)) -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA_M (BIT(20)) -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA_V 0x1 -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA_S 20 -/* SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA (BIT(19)) -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA_M (BIT(19)) -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA_V 0x1 -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA_S 19 -/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(18)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (BIT(18)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x1 -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 18 -/* SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA_M (BIT(17)) -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x1 -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34) +/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_APP1_INT interrupt..*/ +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (BIT(20)) +#define SPI_APP1_INT_ENA_V 0x1 +#define SPI_APP1_INT_ENA_S 20 +/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_APP2_INT interrupt..*/ +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (BIT(19)) +#define SPI_APP2_INT_ENA_V 0x1 +#define SPI_APP2_INT_ENA_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 /* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ -#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_ENA_M (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_ENA_V 0x1 -#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x1 +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 /* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ -#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x1 -#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 /* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ -#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_ENA_M (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x1 -#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/ +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 /* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ -#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x1 -#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 /* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_TRANS_DONE_INT interrupt.*/ -#define SPI_TRANS_DONE_INT_ENA (BIT(12)) -#define SPI_TRANS_DONE_INT_ENA_M (BIT(12)) -#define SPI_TRANS_DONE_INT_ENA_V 0x1 -#define SPI_TRANS_DONE_INT_ENA_S 12 +/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_V 0x1 +#define SPI_TRANS_DONE_INT_ENA_S 12 /* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ -#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x1 -#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 /* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ -#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x1 -#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 /* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ -#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x1 -#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 /* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ -#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x1 -#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 /* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for SPI slave CMDA interrupt.*/ -#define SPI_SLV_CMDA_INT_ENA (BIT(7)) -#define SPI_SLV_CMDA_INT_ENA_M (BIT(7)) -#define SPI_SLV_CMDA_INT_ENA_V 0x1 -#define SPI_SLV_CMDA_INT_ENA_S 7 +/*description: The enable bit for SPI slave CMDA interrupt..*/ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_V 0x1 +#define SPI_SLV_CMDA_INT_ENA_S 7 /* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for SPI slave CMD9 interrupt.*/ -#define SPI_SLV_CMD9_INT_ENA (BIT(6)) -#define SPI_SLV_CMD9_INT_ENA_M (BIT(6)) -#define SPI_SLV_CMD9_INT_ENA_V 0x1 -#define SPI_SLV_CMD9_INT_ENA_S 6 +/*description: The enable bit for SPI slave CMD9 interrupt..*/ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_V 0x1 +#define SPI_SLV_CMD9_INT_ENA_S 6 /* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for SPI slave CMD8 interrupt.*/ -#define SPI_SLV_CMD8_INT_ENA (BIT(5)) -#define SPI_SLV_CMD8_INT_ENA_M (BIT(5)) -#define SPI_SLV_CMD8_INT_ENA_V 0x1 -#define SPI_SLV_CMD8_INT_ENA_S 5 +/*description: The enable bit for SPI slave CMD8 interrupt..*/ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_V 0x1 +#define SPI_SLV_CMD8_INT_ENA_S 5 /* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for SPI slave CMD7 interrupt.*/ -#define SPI_SLV_CMD7_INT_ENA (BIT(4)) -#define SPI_SLV_CMD7_INT_ENA_M (BIT(4)) -#define SPI_SLV_CMD7_INT_ENA_V 0x1 -#define SPI_SLV_CMD7_INT_ENA_S 4 +/*description: The enable bit for SPI slave CMD7 interrupt..*/ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_V 0x1 +#define SPI_SLV_CMD7_INT_ENA_S 4 /* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for SPI slave En_QPI interrupt.*/ -#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) -#define SPI_SLV_EN_QPI_INT_ENA_M (BIT(3)) -#define SPI_SLV_EN_QPI_INT_ENA_V 0x1 -#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/*description: The enable bit for SPI slave En_QPI interrupt..*/ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x1 +#define SPI_SLV_EN_QPI_INT_ENA_S 3 /* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for SPI slave Ex_QPI interrupt.*/ -#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) -#define SPI_SLV_EX_QPI_INT_ENA_M (BIT(2)) -#define SPI_SLV_EX_QPI_INT_ENA_V 0x1 -#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/*description: The enable bit for SPI slave Ex_QPI interrupt..*/ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x1 +#define SPI_SLV_EX_QPI_INT_ENA_S 2 /* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x1 -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 /* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ -#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x1 -#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 +/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 -#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x038) -/* SPI_MST_TX_AFIFO_RERR_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_MST_TX_AFIFO_RERR_INT_CLR (BIT(21)) -#define SPI_MST_TX_AFIFO_RERR_INT_CLR_M (BIT(21)) -#define SPI_MST_TX_AFIFO_RERR_INT_CLR_V 0x1 -#define SPI_MST_TX_AFIFO_RERR_INT_CLR_S 21 -/* SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR (BIT(20)) -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR_M (BIT(20)) -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR_V 0x1 -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR_S 20 -/* SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR (BIT(19)) -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR_M (BIT(19)) -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR_V 0x1 -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR_S 19 -/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(18)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(18)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1 -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 18 -/* SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(17)) -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1 -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 -/* SPI_SLV_CMD_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ -#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_CLR_M (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_CLR_V 0x1 -#define SPI_SLV_CMD_ERR_INT_CLR_S 16 -/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ -#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x1 -#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 -/* SPI_SEG_MAGIC_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ -#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_CLR_M (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x1 -#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 -/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ -#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x1 -#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 -/* SPI_TRANS_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_TRANS_DONE_INT interrupt.*/ -#define SPI_TRANS_DONE_INT_CLR (BIT(12)) -#define SPI_TRANS_DONE_INT_CLR_M (BIT(12)) -#define SPI_TRANS_DONE_INT_CLR_V 0x1 -#define SPI_TRANS_DONE_INT_CLR_S 12 -/* SPI_SLV_WR_BUF_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ -#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x1 -#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 -/* SPI_SLV_RD_BUF_DONE_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ -#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x1 -#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 -/* SPI_SLV_WR_DMA_DONE_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ -#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x1 -#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 -/* SPI_SLV_RD_DMA_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ -#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x1 -#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 -/* SPI_SLV_CMDA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The clear bit for SPI slave CMDA interrupt.*/ -#define SPI_SLV_CMDA_INT_CLR (BIT(7)) -#define SPI_SLV_CMDA_INT_CLR_M (BIT(7)) -#define SPI_SLV_CMDA_INT_CLR_V 0x1 -#define SPI_SLV_CMDA_INT_CLR_S 7 -/* SPI_SLV_CMD9_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The clear bit for SPI slave CMD9 interrupt.*/ -#define SPI_SLV_CMD9_INT_CLR (BIT(6)) -#define SPI_SLV_CMD9_INT_CLR_M (BIT(6)) -#define SPI_SLV_CMD9_INT_CLR_V 0x1 -#define SPI_SLV_CMD9_INT_CLR_S 6 -/* SPI_SLV_CMD8_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The clear bit for SPI slave CMD8 interrupt.*/ -#define SPI_SLV_CMD8_INT_CLR (BIT(5)) -#define SPI_SLV_CMD8_INT_CLR_M (BIT(5)) -#define SPI_SLV_CMD8_INT_CLR_V 0x1 -#define SPI_SLV_CMD8_INT_CLR_S 5 -/* SPI_SLV_CMD7_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The clear bit for SPI slave CMD7 interrupt.*/ -#define SPI_SLV_CMD7_INT_CLR (BIT(4)) -#define SPI_SLV_CMD7_INT_CLR_M (BIT(4)) -#define SPI_SLV_CMD7_INT_CLR_V 0x1 -#define SPI_SLV_CMD7_INT_CLR_S 4 -/* SPI_SLV_EN_QPI_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The clear bit for SPI slave En_QPI interrupt.*/ -#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) -#define SPI_SLV_EN_QPI_INT_CLR_M (BIT(3)) -#define SPI_SLV_EN_QPI_INT_CLR_V 0x1 -#define SPI_SLV_EN_QPI_INT_CLR_S 3 -/* SPI_SLV_EX_QPI_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The clear bit for SPI slave Ex_QPI interrupt.*/ -#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) -#define SPI_SLV_EX_QPI_INT_CLR_M (BIT(2)) -#define SPI_SLV_EX_QPI_INT_CLR_V 0x1 -#define SPI_SLV_EX_QPI_INT_CLR_S 2 -/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1 -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 -/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ -#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x1 -#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38) +/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_APP1_INT interrupt..*/ +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (BIT(20)) +#define SPI_APP1_INT_CLR_V 0x1 +#define SPI_APP1_INT_CLR_S 20 +/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_APP2_INT interrupt..*/ +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (BIT(19)) +#define SPI_APP2_INT_CLR_V 0x1 +#define SPI_APP2_INT_CLR_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x1 +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/ +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_V 0x1 +#define SPI_TRANS_DONE_INT_CLR_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMDA interrupt..*/ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_V 0x1 +#define SPI_SLV_CMDA_INT_CLR_S 7 +/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD9 interrupt..*/ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_V 0x1 +#define SPI_SLV_CMD9_INT_CLR_S 6 +/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD8 interrupt..*/ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_V 0x1 +#define SPI_SLV_CMD8_INT_CLR_S 5 +/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD7 interrupt..*/ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_V 0x1 +#define SPI_SLV_CMD7_INT_CLR_S 4 +/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave En_QPI interrupt..*/ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x1 +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave Ex_QPI interrupt..*/ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x1 +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 -#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x03C) -/* SPI_MST_TX_AFIFO_RERR_INT_RAW : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MST_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO - underflow when SPI master sends data out in CPU/DMA controlled mode. 0: Others.*/ -#define SPI_MST_TX_AFIFO_RERR_INT_RAW (BIT(21)) -#define SPI_MST_TX_AFIFO_RERR_INT_RAW_M (BIT(21)) -#define SPI_MST_TX_AFIFO_RERR_INT_RAW_V 0x1 -#define SPI_MST_TX_AFIFO_RERR_INT_RAW_S 21 -/* SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt. 1: SPI - AFIFO underflow when SPI slave sent data out in DMA controlled mode 0: Others.*/ -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW (BIT(20)) -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW_M (BIT(20)) -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW_V 0x1 -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW_S 20 -/* SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt. 1: SPI - AFIFO underflow when SPI slave sent data out in CPU controlled mode 0: Others.*/ -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW (BIT(19)) -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW_M (BIT(19)) -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW_V 0x1 -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW_S 19 -/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: - SPI AFIFO overflow when SPI master reads data in CPU/DMA controlled mode. 0: Others.*/ -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(18)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (BIT(18)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x1 -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 18 -/* SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt. 1: - SPI AFIFO overflow when SPI slave reads data in CPU/DMA controlled mode. 0: Others.*/ -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW_M (BIT(17)) -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x1 -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 -/* SPI_SLV_CMD_ERR_INT_RAW : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command - value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ -#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_RAW_M (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1 -#define SPI_SLV_CMD_ERR_INT_RAW_S 16 -/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing - data address of the current SPI slave mode CPU controlled FD Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ -#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x1 -#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 -/* SPI_SEG_MAGIC_ERR_INT_RAW : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic - value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ -#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_RAW_M (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x1 -#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 -/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi - master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.*/ -#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x1 -#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 -/* SPI_TRANS_DONE_INT_RAW : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode - transmission is ended. 0: others.*/ -#define SPI_TRANS_DONE_INT_RAW (BIT(12)) -#define SPI_TRANS_DONE_INT_RAW_M (BIT(12)) -#define SPI_TRANS_DONE_INT_RAW_V 0x1 -#define SPI_TRANS_DONE_INT_RAW_S 12 -/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave - mode Wr_BUF transmission is ended. 0: Others.*/ -#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x1 -#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 -/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave - mode Rd_BUF transmission is ended. 0: Others.*/ -#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x1 -#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 -/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave - mode Wr_DMA transmission is ended. 0: Others.*/ -#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x1 -#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 -/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave - mode Rd_DMA transmission is ended. 0: Others.*/ -#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x1 -#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 -/* SPI_SLV_CMDA_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA - transmission is ended. 0: Others.*/ -#define SPI_SLV_CMDA_INT_RAW (BIT(7)) -#define SPI_SLV_CMDA_INT_RAW_M (BIT(7)) -#define SPI_SLV_CMDA_INT_RAW_V 0x1 -#define SPI_SLV_CMDA_INT_RAW_S 7 -/* SPI_SLV_CMD9_INT_RAW : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 - transmission is ended. 0: Others.*/ -#define SPI_SLV_CMD9_INT_RAW (BIT(6)) -#define SPI_SLV_CMD9_INT_RAW_M (BIT(6)) -#define SPI_SLV_CMD9_INT_RAW_V 0x1 -#define SPI_SLV_CMD9_INT_RAW_S 6 -/* SPI_SLV_CMD8_INT_RAW : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 - transmission is ended. 0: Others.*/ -#define SPI_SLV_CMD8_INT_RAW (BIT(5)) -#define SPI_SLV_CMD8_INT_RAW_M (BIT(5)) -#define SPI_SLV_CMD8_INT_RAW_V 0x1 -#define SPI_SLV_CMD8_INT_RAW_S 5 -/* SPI_SLV_CMD7_INT_RAW : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 - transmission is ended. 0: Others.*/ -#define SPI_SLV_CMD7_INT_RAW (BIT(4)) -#define SPI_SLV_CMD7_INT_RAW_M (BIT(4)) -#define SPI_SLV_CMD7_INT_RAW_V 0x1 -#define SPI_SLV_CMD7_INT_RAW_S 4 -/* SPI_SLV_EN_QPI_INT_RAW : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode - En_QPI transmission is ended. 0: Others.*/ -#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) -#define SPI_SLV_EN_QPI_INT_RAW_M (BIT(3)) -#define SPI_SLV_EN_QPI_INT_RAW_V 0x1 -#define SPI_SLV_EN_QPI_INT_RAW_S 3 -/* SPI_SLV_EX_QPI_INT_RAW : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode - Ex_QPI transmission is ended. 0: Others.*/ -#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) -#define SPI_SLV_EX_QPI_INT_RAW_M (BIT(2)) -#define SPI_SLV_EX_QPI_INT_RAW_V 0x1 -#define SPI_SLV_EX_QPI_INT_RAW_S 2 -/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: 1: The current data rate of DMA TX is smaller than that of SPI. - SPI will stop in master mode and send out all 0 in slave mode. 0: Others.*/ -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1 -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 -/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1: The current data rate of DMA Rx is smaller than that of SPI - which will lose the receive data. 0: Others.*/ -#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x1 -#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3C) +/* SPI_APP1_INT_RAW : R/WTC/SS ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software +..*/ +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (BIT(20)) +#define SPI_APP1_INT_RAW_V 0x1 +#define SPI_APP1_INT_RAW_S 20 +/* SPI_APP2_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software +..*/ +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (BIT(19)) +#define SPI_APP2_INT_RAW_V 0x1 +#define SPI_APP2_INT_RAW_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF +AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + write-full error when SPI inputs data in master mode. 0: Others..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/* SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + current SPI slave HD mode transmission is not supported. 0: Others..*/ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1 +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres +s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission + is bigger than 63. 0: Others..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/* SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff +er is error in the DMA seg-conf-trans. 0: others..*/ +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-du +plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da +ta has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is +not ended or not occurred. .*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/* SPI_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + ended. 0: others..*/ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_V 0x1 +#define SPI_TRANS_DONE_INT_RAW_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran +smission is ended. 0: Others..*/ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran +smission is ended. 0: Others..*/ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran +smission is ended. 0: Others..*/ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran +smission is ended. 0: Others..*/ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/* SPI_SLV_CMDA_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + ended. 0: Others..*/ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_V 0x1 +#define SPI_SLV_CMDA_INT_RAW_S 7 +/* SPI_SLV_CMD9_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + ended. 0: Others..*/ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_V 0x1 +#define SPI_SLV_CMD9_INT_RAW_S 6 +/* SPI_SLV_CMD8_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + ended. 0: Others..*/ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_V 0x1 +#define SPI_SLV_CMD8_INT_RAW_S 5 +/* SPI_SLV_CMD7_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + ended. 0: Others..*/ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_V 0x1 +#define SPI_SLV_CMD7_INT_RAW_S 4 +/* SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio +n is ended. 0: Others..*/ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x1 +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/* SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio +n is ended. 0: Others..*/ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x1 +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + master mode and send out all 0 in slave mode. 0: Others. .*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose +the receive data. 0: Others. .*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 -#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x040) -/* SPI_MST_TX_AFIFO_RERR_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_MST_TX_AFIFO_RERR_INT_ST (BIT(21)) -#define SPI_MST_TX_AFIFO_RERR_INT_ST_M (BIT(21)) -#define SPI_MST_TX_AFIFO_RERR_INT_ST_V 0x1 -#define SPI_MST_TX_AFIFO_RERR_INT_ST_S 21 -/* SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST (BIT(20)) -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST_M (BIT(20)) -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST_V 0x1 -#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST_S 20 -/* SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST (BIT(19)) -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST_M (BIT(19)) -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST_V 0x1 -#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST_S 19 -/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(18)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (BIT(18)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x1 -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 18 -/* SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST_M (BIT(17)) -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST_V 0x1 -#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40) +/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The status bit for SPI_APP1_INT interrupt..*/ +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (BIT(20)) +#define SPI_APP1_INT_ST_V 0x1 +#define SPI_APP1_INT_ST_S 20 +/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The status bit for SPI_APP2_INT interrupt..*/ +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (BIT(19)) +#define SPI_APP2_INT_ST_V 0x1 +#define SPI_APP2_INT_ST_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 /* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ -#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_ST_M (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_ST_V 0x1 -#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x1 +#define SPI_SLV_CMD_ERR_INT_ST_S 16 /* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ -#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x1 -#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 /* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ -#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_ST_M (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x1 -#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/ +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 /* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ -#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x1 -#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 /* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The status bit for SPI_TRANS_DONE_INT interrupt.*/ -#define SPI_TRANS_DONE_INT_ST (BIT(12)) -#define SPI_TRANS_DONE_INT_ST_M (BIT(12)) -#define SPI_TRANS_DONE_INT_ST_V 0x1 -#define SPI_TRANS_DONE_INT_ST_S 12 +/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_V 0x1 +#define SPI_TRANS_DONE_INT_ST_S 12 /* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ -#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_ST_M (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x1 -#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 /* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ -#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_ST_M (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x1 -#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 /* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ -#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_ST_M (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x1 -#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 /* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ -#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_ST_M (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x1 -#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 /* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The status bit for SPI slave CMDA interrupt.*/ -#define SPI_SLV_CMDA_INT_ST (BIT(7)) -#define SPI_SLV_CMDA_INT_ST_M (BIT(7)) -#define SPI_SLV_CMDA_INT_ST_V 0x1 -#define SPI_SLV_CMDA_INT_ST_S 7 +/*description: The status bit for SPI slave CMDA interrupt..*/ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_V 0x1 +#define SPI_SLV_CMDA_INT_ST_S 7 /* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The status bit for SPI slave CMD9 interrupt.*/ -#define SPI_SLV_CMD9_INT_ST (BIT(6)) -#define SPI_SLV_CMD9_INT_ST_M (BIT(6)) -#define SPI_SLV_CMD9_INT_ST_V 0x1 -#define SPI_SLV_CMD9_INT_ST_S 6 +/*description: The status bit for SPI slave CMD9 interrupt..*/ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_V 0x1 +#define SPI_SLV_CMD9_INT_ST_S 6 /* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The status bit for SPI slave CMD8 interrupt.*/ -#define SPI_SLV_CMD8_INT_ST (BIT(5)) -#define SPI_SLV_CMD8_INT_ST_M (BIT(5)) -#define SPI_SLV_CMD8_INT_ST_V 0x1 -#define SPI_SLV_CMD8_INT_ST_S 5 +/*description: The status bit for SPI slave CMD8 interrupt..*/ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_V 0x1 +#define SPI_SLV_CMD8_INT_ST_S 5 /* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The status bit for SPI slave CMD7 interrupt.*/ -#define SPI_SLV_CMD7_INT_ST (BIT(4)) -#define SPI_SLV_CMD7_INT_ST_M (BIT(4)) -#define SPI_SLV_CMD7_INT_ST_V 0x1 -#define SPI_SLV_CMD7_INT_ST_S 4 +/*description: The status bit for SPI slave CMD7 interrupt..*/ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_V 0x1 +#define SPI_SLV_CMD7_INT_ST_S 4 /* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The status bit for SPI slave En_QPI interrupt.*/ -#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) -#define SPI_SLV_EN_QPI_INT_ST_M (BIT(3)) -#define SPI_SLV_EN_QPI_INT_ST_V 0x1 -#define SPI_SLV_EN_QPI_INT_ST_S 3 +/*description: The status bit for SPI slave En_QPI interrupt..*/ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_V 0x1 +#define SPI_SLV_EN_QPI_INT_ST_S 3 /* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The status bit for SPI slave Ex_QPI interrupt.*/ -#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) -#define SPI_SLV_EX_QPI_INT_ST_M (BIT(2)) -#define SPI_SLV_EX_QPI_INT_ST_V 0x1 -#define SPI_SLV_EX_QPI_INT_ST_S 2 +/*description: The status bit for SPI slave Ex_QPI interrupt..*/ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_V 0x1 +#define SPI_SLV_EX_QPI_INT_ST_S 2 /* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x1 -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 /* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ -#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x1 -#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 +/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 -#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x098) -/* SPI_BUF0 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF0 0xFFFFFFFF -#define SPI_BUF0_M ((SPI_BUF0_V) << (SPI_BUF0_S)) -#define SPI_BUF0_V 0xFFFFFFFF -#define SPI_BUF0_S 0 +#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44) +/* SPI_APP1_INT_SET : WT ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_APP1_INT interrupt..*/ +#define SPI_APP1_INT_SET (BIT(20)) +#define SPI_APP1_INT_SET_M (BIT(20)) +#define SPI_APP1_INT_SET_V 0x1 +#define SPI_APP1_INT_SET_S 20 +/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_APP2_INT interrupt..*/ +#define SPI_APP2_INT_SET (BIT(19)) +#define SPI_APP2_INT_SET_M (BIT(19)) +#define SPI_APP2_INT_SET_V 0x1 +#define SPI_APP2_INT_SET_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/* SPI_SLV_CMD_ERR_INT_SET : WT ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt..*/ +#define SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_V 0x1 +#define SPI_SLV_CMD_ERR_INT_SET_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/* SPI_SEG_MAGIC_ERR_INT_SET : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/ +#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_SET_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_SET : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13 +/* SPI_TRANS_DONE_INT_SET : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_TRANS_DONE_INT interrupt..*/ +#define SPI_TRANS_DONE_INT_SET (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_M (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_V 0x1 +#define SPI_TRANS_DONE_INT_SET_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_SET : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/ +#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_SET : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_SET : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/ +#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8 +/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave CMDA interrupt..*/ +#define SPI_SLV_CMDA_INT_SET (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_M (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_V 0x1 +#define SPI_SLV_CMDA_INT_SET_S 7 +/* SPI_SLV_CMD9_INT_SET : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave CMD9 interrupt..*/ +#define SPI_SLV_CMD9_INT_SET (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_M (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_V 0x1 +#define SPI_SLV_CMD9_INT_SET_S 6 +/* SPI_SLV_CMD8_INT_SET : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave CMD8 interrupt..*/ +#define SPI_SLV_CMD8_INT_SET (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_M (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_V 0x1 +#define SPI_SLV_CMD8_INT_SET_S 5 +/* SPI_SLV_CMD7_INT_SET : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave CMD7 interrupt..*/ +#define SPI_SLV_CMD7_INT_SET (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_M (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_V 0x1 +#define SPI_SLV_CMD7_INT_SET_S 4 +/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave En_QPI interrupt..*/ +#define SPI_SLV_EN_QPI_INT_SET (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_V 0x1 +#define SPI_SLV_EN_QPI_INT_SET_S 3 +/* SPI_SLV_EX_QPI_INT_SET : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave Ex_QPI interrupt..*/ +#define SPI_SLV_EX_QPI_INT_SET (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_V 0x1 +#define SPI_SLV_EX_QPI_INT_SET_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0 -#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x09C) -/* SPI_BUF1 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF1 0xFFFFFFFF -#define SPI_BUF1_M ((SPI_BUF1_V) << (SPI_BUF1_S)) -#define SPI_BUF1_V 0xFFFFFFFF -#define SPI_BUF1_S 0 +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98) +/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 -#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x0A0) -/* SPI_BUF2 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF2 0xFFFFFFFF -#define SPI_BUF2_M ((SPI_BUF2_V) << (SPI_BUF2_S)) -#define SPI_BUF2_V 0xFFFFFFFF -#define SPI_BUF2_S 0 +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9C) +/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 -#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x0A4) -/* SPI_BUF3 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF3 0xFFFFFFFF -#define SPI_BUF3_M ((SPI_BUF3_V) << (SPI_BUF3_S)) -#define SPI_BUF3_V 0xFFFFFFFF -#define SPI_BUF3_S 0 +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xA0) +/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 -#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x0A8) -/* SPI_BUF4 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF4 0xFFFFFFFF -#define SPI_BUF4_M ((SPI_BUF4_V) << (SPI_BUF4_S)) -#define SPI_BUF4_V 0xFFFFFFFF -#define SPI_BUF4_S 0 +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xA4) +/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 -#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x0AC) -/* SPI_BUF5 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF5 0xFFFFFFFF -#define SPI_BUF5_M ((SPI_BUF5_V) << (SPI_BUF5_S)) -#define SPI_BUF5_V 0xFFFFFFFF -#define SPI_BUF5_S 0 +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xA8) +/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 -#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x0B0) -/* SPI_BUF6 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF6 0xFFFFFFFF -#define SPI_BUF6_M ((SPI_BUF6_V) << (SPI_BUF6_S)) -#define SPI_BUF6_V 0xFFFFFFFF -#define SPI_BUF6_S 0 +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xAC) +/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 -#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x0B4) -/* SPI_BUF7 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF7 0xFFFFFFFF -#define SPI_BUF7_M ((SPI_BUF7_V) << (SPI_BUF7_S)) -#define SPI_BUF7_V 0xFFFFFFFF -#define SPI_BUF7_S 0 +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xB0) +/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 -#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0x0B8) -/* SPI_BUF8 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF8 0xFFFFFFFF -#define SPI_BUF8_M ((SPI_BUF8_V) << (SPI_BUF8_S)) -#define SPI_BUF8_V 0xFFFFFFFF -#define SPI_BUF8_S 0 +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xB4) +/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 -#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0x0BC) -/* SPI_BUF9 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF9 0xFFFFFFFF -#define SPI_BUF9_M ((SPI_BUF9_V) << (SPI_BUF9_S)) -#define SPI_BUF9_V 0xFFFFFFFF -#define SPI_BUF9_S 0 +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xB8) +/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 -#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0x0C0) -/* SPI_BUF10 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF10 0xFFFFFFFF -#define SPI_BUF10_M ((SPI_BUF10_V) << (SPI_BUF10_S)) -#define SPI_BUF10_V 0xFFFFFFFF -#define SPI_BUF10_S 0 +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xBC) +/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 -#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0x0C4) -/* SPI_BUF11 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF11 0xFFFFFFFF -#define SPI_BUF11_M ((SPI_BUF11_V) << (SPI_BUF11_S)) -#define SPI_BUF11_V 0xFFFFFFFF -#define SPI_BUF11_S 0 +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xC0) +/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 -#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0x0C8) -/* SPI_BUF12 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF12 0xFFFFFFFF -#define SPI_BUF12_M ((SPI_BUF12_V) << (SPI_BUF12_S)) -#define SPI_BUF12_V 0xFFFFFFFF -#define SPI_BUF12_S 0 +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xC4) +/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 -#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0x0CC) -/* SPI_BUF13 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF13 0xFFFFFFFF -#define SPI_BUF13_M ((SPI_BUF13_V) << (SPI_BUF13_S)) -#define SPI_BUF13_V 0xFFFFFFFF -#define SPI_BUF13_S 0 +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xC8) +/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 -#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0x0D0) -/* SPI_BUF14 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF14 0xFFFFFFFF -#define SPI_BUF14_M ((SPI_BUF14_V) << (SPI_BUF14_S)) -#define SPI_BUF14_V 0xFFFFFFFF -#define SPI_BUF14_S 0 +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xCC) +/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 -#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0x0D4) -/* SPI_BUF15 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer*/ -#define SPI_BUF15 0xFFFFFFFF -#define SPI_BUF15_M ((SPI_BUF15_V) << (SPI_BUF15_S)) -#define SPI_BUF15_V 0xFFFFFFFF -#define SPI_BUF15_S 0 +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xD0) +/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 -#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x0E0) +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xD4) +/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer.*/ +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xE0) /* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: 1: Enable the DMA CONF phase of current seg-trans operation - which means seg-trans will start. 0: This is not seg-trans mode.*/ -#define SPI_USR_CONF (BIT(28)) -#define SPI_USR_CONF_M (BIT(28)) -#define SPI_USR_CONF_V 0x1 -#define SPI_USR_CONF_S 28 -/* SPI_SOFT_RESET : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Software reset enable reset the spi clock line cs line and data - lines. Can be configured in CONF state.*/ -#define SPI_SOFT_RESET (BIT(27)) -#define SPI_SOFT_RESET_M (BIT(27)) -#define SPI_SOFT_RESET_V 0x1 -#define SPI_SOFT_RESET_S 27 +/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra +ns will start. 0: This is not seg-trans mode..*/ +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (BIT(28)) +#define SPI_USR_CONF_V 0x1 +#define SPI_USR_CONF_S 28 +/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c +onfigured in CONF state..*/ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (BIT(27)) +#define SPI_SOFT_RESET_V 0x1 +#define SPI_SOFT_RESET_S 27 /* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set SPI work mode. 1: slave mode 0: master mode.*/ -#define SPI_SLAVE_MODE (BIT(26)) -#define SPI_SLAVE_MODE_M (BIT(26)) -#define SPI_SLAVE_MODE_V 0x1 -#define SPI_SLAVE_MODE_S 26 +/*description: Set SPI work mode. 1: slave mode 0: master mode..*/ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (BIT(26)) +#define SPI_SLAVE_MODE_V 0x1 +#define SPI_SLAVE_MODE_S 26 /* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */ -/*description: The magic value of BM table in master DMA seg-trans.*/ -#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F -#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V) << (SPI_DMA_SEG_MAGIC_VALUE_S)) -#define SPI_DMA_SEG_MAGIC_VALUE_V 0xF -#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/*description: The magic value of BM table in master DMA seg-trans..*/ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F +#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S)) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0xF +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 /* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave - data length in CPU controlled mode(Wr_BUF). 0: others*/ -#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) -#define SPI_SLV_WRBUF_BITLEN_EN_M (BIT(11)) -#define SPI_SLV_WRBUF_BITLEN_EN_V 0x1 -#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng +th in CPU controlled mode(Wr_BUF). 0: others.*/ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x1 +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 /* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave - data length in CPU controlled mode(Rd_BUF). 0: others*/ -#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) -#define SPI_SLV_RDBUF_BITLEN_EN_M (BIT(10)) -#define SPI_SLV_RDBUF_BITLEN_EN_V 0x1 -#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i +n CPU controlled mode(Rd_BUF). 0: others.*/ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x1 +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 /* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave - data length in DMA controlled mode(Wr_DMA). 0: others*/ -#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) -#define SPI_SLV_WRDMA_BITLEN_EN_M (BIT(9)) -#define SPI_SLV_WRDMA_BITLEN_EN_V 0x1 -#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng +th in DMA controlled mode(Wr_DMA). 0: others.*/ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x1 +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 /* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave - data length in DMA controlled mode(Rd_DMA). 0: others*/ -#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) -#define SPI_SLV_RDDMA_BITLEN_EN_M (BIT(8)) -#define SPI_SLV_RDDMA_BITLEN_EN_V 0x1 -#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i +n DMA controlled mode(Rd_DMA). 0: others.*/ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x1 +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 /* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: It saves half a cycle when tsck is the same as rsck. 1: output - data at rsck posedge 0: output data at tsck posedge*/ -#define SPI_RSCK_DATA_OUT (BIT(3)) -#define SPI_RSCK_DATA_OUT_M (BIT(3)) -#define SPI_RSCK_DATA_OUT_V 0x1 -#define SPI_RSCK_DATA_OUT_S 3 +/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose +dge 0: output data at tsck posedge .*/ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (BIT(3)) +#define SPI_RSCK_DATA_OUT_V 0x1 +#define SPI_RSCK_DATA_OUT_S 3 /* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: {CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output - data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ -#define SPI_CLK_MODE_13 (BIT(2)) -#define SPI_CLK_MODE_13_M (BIT(2)) -#define SPI_CLK_MODE_13_V 0x1 -#define SPI_CLK_MODE_13_S 2 +/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. + 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (BIT(2)) +#define SPI_CLK_MODE_13_V 0x1 +#define SPI_CLK_MODE_13_S 2 /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ -#define SPI_CLK_MODE 0x00000003 -#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V) << (SPI_CLK_MODE_S)) -#define SPI_CLK_MODE_V 0x3 -#define SPI_CLK_MODE_S 0 +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/ +#define SPI_CLK_MODE 0x00000003 +#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) +#define SPI_CLK_MODE_V 0x3 +#define SPI_CLK_MODE_S 0 -#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x0E4) -/* SPI_SLV_LAST_ADDR : SRW ;bitpos:[31:26] ;default: 6'd0 ; */ -/*description: In the slave mode it is the value of address.*/ -#define SPI_SLV_LAST_ADDR 0x0000003F -#define SPI_SLV_LAST_ADDR_M ((SPI_SLV_LAST_ADDR_V) << (SPI_SLV_LAST_ADDR_S)) -#define SPI_SLV_LAST_ADDR_V 0x3F -#define SPI_SLV_LAST_ADDR_S 26 -/* SPI_SLV_LAST_COMMAND : SRW ;bitpos:[25:18] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of command.*/ -#define SPI_SLV_LAST_COMMAND 0x000000FF -#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V) << (SPI_SLV_LAST_COMMAND_S)) -#define SPI_SLV_LAST_COMMAND_V 0xFF -#define SPI_SLV_LAST_COMMAND_S 18 -/* SPI_SLV_DATA_BITLEN : SRW ;bitpos:[17:0] ;default: 18'd0 ; */ -/*description: The transferred data bit length in SPI slave FD and HD mode.*/ -#define SPI_SLV_DATA_BITLEN 0x0003FFFF -#define SPI_SLV_DATA_BITLEN_M ((SPI_SLV_DATA_BITLEN_V) << (SPI_SLV_DATA_BITLEN_S)) -#define SPI_SLV_DATA_BITLEN_V 0x3FFFF -#define SPI_SLV_DATA_BITLEN_S 0 +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xE4) +/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */ +/*description: In the slave mode it is the value of address..*/ +#define SPI_SLV_LAST_ADDR 0x0000003F +#define SPI_SLV_LAST_ADDR_M ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S)) +#define SPI_SLV_LAST_ADDR_V 0x3F +#define SPI_SLV_LAST_ADDR_S 26 +/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of command..*/ +#define SPI_SLV_LAST_COMMAND 0x000000FF +#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) +#define SPI_SLV_LAST_COMMAND_V 0xFF +#define SPI_SLV_LAST_COMMAND_S 18 +/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: The transferred data bit length in SPI slave FD and HD mode. .*/ +#define SPI_SLV_DATA_BITLEN 0x0003FFFF +#define SPI_SLV_DATA_BITLEN_M ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S)) +#define SPI_SLV_DATA_BITLEN_V 0x3FFFF +#define SPI_SLV_DATA_BITLEN_S 0 -#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0x0E8) +#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xE8) /* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This bit is used to select SPI module clock source in master - mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ -#define SPI_MST_CLK_SEL (BIT(2)) -#define SPI_MST_CLK_SEL_M (BIT(2)) -#define SPI_MST_CLK_SEL_V 0x1 -#define SPI_MST_CLK_SEL_S 2 +/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80 +M. 0: XTAL CLK..*/ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (BIT(2)) +#define SPI_MST_CLK_SEL_V 0x1 +#define SPI_MST_CLK_SEL_S 2 /* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to power on the SPI module clock.*/ -#define SPI_MST_CLK_ACTIVE (BIT(1)) -#define SPI_MST_CLK_ACTIVE_M (BIT(1)) -#define SPI_MST_CLK_ACTIVE_V 0x1 -#define SPI_MST_CLK_ACTIVE_S 1 +/*description: Set this bit to power on the SPI module clock..*/ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (BIT(1)) +#define SPI_MST_CLK_ACTIVE_V 0x1 +#define SPI_MST_CLK_ACTIVE_S 1 /* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable clk gate*/ -#define SPI_CLK_EN (BIT(0)) -#define SPI_CLK_EN_M (BIT(0)) -#define SPI_CLK_EN_V 0x1 -#define SPI_CLK_EN_S 0 +/*description: Set this bit to enable clk gate.*/ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (BIT(0)) +#define SPI_CLK_EN_V 0x1 +#define SPI_CLK_EN_S 0 + +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xF0) +/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012290 ; */ +/*description: SPI register version..*/ +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) +#define SPI_DATE_V 0xFFFFFFF +#define SPI_DATE_S 0 -#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x0F0) -/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003110 ; */ -/*description: SPI register version.*/ -#define SPI_DATE 0x0FFFFFFF -#define SPI_DATE_M ((SPI_DATE_V) << (SPI_DATE_S)) -#define SPI_DATE_V 0xFFFFFFF -#define SPI_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SPI_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/spi_struct.h b/components/soc/esp32s3/include/soc/spi_struct.h index 057ebd999e..799ef15149 100644 --- a/components/soc/esp32s3/include/soc/spi_struct.h +++ b/components/soc/esp32s3/include/soc/spi_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,316 +11,341 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_SPI_STRUCT_H_ +#define _SOC_SPI_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif -#include - typedef volatile struct { union { struct { - uint32_t conf_bitlen: 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ - uint32_t reserved18: 5; /*reserved*/ - uint32_t update: 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain which is only used in SPI master mode.*/ - uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ - uint32_t reserved25: 7; /*reserved*/ + uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ + uint32_t reserved18 : 5; /*reserved*/ + uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/ + uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ + uint32_t reserved25 : 7; /*reserved*/ }; uint32_t val; } cmd; - uint32_t addr; /*Address to slave. Can be configured in CONF state.*/ + uint32_t addr; union { struct { - uint32_t reserved0: 3; /*reserved*/ - uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/ - uint32_t reserved4: 1; /*reserved*/ - uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_oct: 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved11: 3; /*reserved*/ - uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_oct: 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved17: 1; /*reserved*/ - uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low. Can be configured in CONF state.*/ - uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low. Can be configured in CONF state.*/ - uint32_t hold_pol: 1; /*SPI_HOLD output value when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/ - uint32_t wp_pol: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/ - uint32_t reserved22: 3; /*reserved*/ - uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ - uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ - uint32_t reserved27: 5; /*reserved*/ + uint32_t reserved0 : 3; /*reserved*/ + uint32_t dummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/ + uint32_t reserved4 : 1; /*reserved*/ + uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t faddr_oct : 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved11 : 3; /*reserved*/ + uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t fread_oct : 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved17 : 1; /*reserved*/ + uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/ + uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/ + uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ + uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ + uint32_t reserved22 : 1; /*reserved*/ + uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ + uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ + uint32_t reserved27 : 5; /*reserved*/ }; uint32_t val; } ctrl; union { struct { - uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ - uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ - uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ + uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/ + uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/ + uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ + uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ + uint32_t reserved22 : 9; /*reserved*/ + uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ }; uint32_t val; } clock; union { struct { - uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved1: 2; /*reserved*/ - uint32_t qpi_mode: 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/ - uint32_t opi_mode: 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/ - uint32_t tsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ - uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t rsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ - uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/ - uint32_t reserved10: 2; /*reserved*/ - uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/ - uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/ - uint32_t fwrite_oct: 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/ - uint32_t usr_conf_nxt: 1; /*1: Enable the DMA CONF phase of next seg-trans operation which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ - uint32_t reserved16: 1; /*reserved*/ - uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved18: 6; /*reserved*/ - uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/ - uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_addr: 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_command: 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/ + uint32_t doutdin : 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved1 : 2; /*reserved*/ + uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/ + uint32_t opi_mode : 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/ + uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ + uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ + uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/ + uint32_t reserved10 : 2; /*reserved*/ + uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/ + uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/ + uint32_t fwrite_oct : 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/ + uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ + uint32_t reserved16 : 1; /*reserved*/ + uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved18 : 6; /*reserved*/ + uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/ + uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_addr : 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_command : 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/ }; uint32_t val; } user; union { struct { - uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/ - uint32_t reserved8: 9; /*reserved*/ - uint32_t cs_setup_time: 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/ - uint32_t cs_hold_time: 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/ - uint32_t usr_addr_bitlen: 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/ + uint32_t reserved8 : 8; /*reserved*/ + uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/ + uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/ + uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/ + uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ }; uint32_t val; } user1; union { struct { - uint32_t usr_command_value: 16; /*The value of command. Can be configured in CONF state.*/ - uint32_t reserved16: 12; /*reserved*/ - uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/ + uint32_t reserved16 : 11; /*reserved*/ + uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/ + uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ }; uint32_t val; } user2; union { struct { - uint32_t ms_data_bitlen: 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - uint32_t reserved18: 14; /*reserved*/ + uint32_t ms_data_bitlen : 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + uint32_t reserved18 : 14; /*reserved*/ }; uint32_t val; } ms_dlen; union { struct { - uint32_t cs0_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs1_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs2_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs3_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs4_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs5_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/ - uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ - uint32_t reserved13: 3; /*reserved*/ - uint32_t clk_data_dtr_en: 1; /*1: SPI master DTR mode is applied to SPI clk data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.*/ - uint32_t data_dtr_en: 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/ - uint32_t addr_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/ - uint32_t cmd_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/ - uint32_t reserved20: 3; /*reserved*/ - uint32_t slave_cs_pol: 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/ - uint32_t dqs_idle_edge: 1; /*The default value of spi_dqs. Can be configured in CONF state.*/ - uint32_t reserved25: 4; /*reserved*/ - uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ - uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ - uint32_t quad_din_pin_swap: 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.*/ + uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/ + uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ + uint32_t reserved13 : 3; /*reserved*/ + uint32_t clk_data_dtr_en : 1; /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. */ + uint32_t data_dtr_en : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/ + uint32_t addr_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/ + uint32_t cmd_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/ + uint32_t reserved20 : 3; /*reserved*/ + uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/ + uint32_t dqs_idle_edge : 1; /*The default value of spi_dqs. Can be configured in CONF state.*/ + uint32_t reserved25 : 4; /*reserved*/ + uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ + uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ + uint32_t quad_din_pin_swap : 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.*/ }; uint32_t val; } misc; union { struct { - uint32_t din0_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din1_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din2_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din3_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din4_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din5_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din6_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din7_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t timing_hclk_active: 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/ - uint32_t reserved17: 15; /*reserved*/ + uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din4_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din5_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din6_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din7_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/ + uint32_t reserved17 : 15; /*reserved*/ }; uint32_t val; } din_mode; union { struct { - uint32_t din0_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din1_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din2_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din3_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din4_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din5_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din6_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din7_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t reserved16: 16; /*reserved*/ + uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din4_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din5_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din6_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t din7_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ + uint32_t reserved16 : 16; /*reserved*/ }; uint32_t val; } din_num; union { struct { - uint32_t dout0_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout1_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout2_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout3_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout4_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout5_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout6_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout7_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t d_dqs_mode: 1; /*The output signal SPI_DQS is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t reserved9: 23; /*reserved*/ + uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout4_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout5_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout6_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout7_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t d_dqs_mode : 1; /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t reserved9 : 23; /*reserved*/ }; uint32_t val; } dout_mode; union { struct { - uint32_t reserved0: 18; /*reserved*/ - uint32_t dma_seg_trans_en: 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ - uint32_t rx_seg_trans_clr_en: 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ - uint32_t tx_seg_trans_clr_en: 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ - uint32_t rx_eof_en: 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ - uint32_t reserved22: 5; /*reserved*/ - uint32_t dma_rx_ena: 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ - uint32_t dma_tx_ena: 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ - uint32_t rx_afifo_rst: 1; /*Set this bit to reset RX AFIFO which is used to receive data in SPI master and slave mode transfer.*/ - uint32_t buf_afifo_rst: 1; /*Set this bit to reset BUF TX AFIFO which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ - uint32_t dma_afifo_rst: 1; /*Set this bit to reset DMA TX AFIFO which is used to send data out in SPI slave DMA controlled mode transfer.*/ + uint32_t outfifo_empty : 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/ + uint32_t infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/ + uint32_t reserved2 : 16; /*reserved*/ + uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ + uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ + uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ + uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ + uint32_t reserved22 : 5; /*reserved*/ + uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ + uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ + uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/ + uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ + uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/ }; uint32_t val; } dma_conf; union { struct { - uint32_t infifo_full_err: 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err: 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi: 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi: 1; /*The enable bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7: 1; /*The enable bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8: 1; /*The enable bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9: 1; /*The enable bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda: 1; /*The enable bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done: 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done: 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done: 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done: 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done: 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done: 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err: 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err: 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err: 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t rx_afifo_wfull_err: 1; /*The enable bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ - uint32_t mst_rx_afifo_wfull_err: 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ - uint32_t buf_tx_afifo_rerr: 1; /*The enable bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ - uint32_t dma_tx_afifo_rerr: 1; /*The enable bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ - uint32_t mst_tx_afifo_rerr: 1; /*The enable bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t infifo_full_err : 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda : 1; /*The enable bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done : 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done : 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ + uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ + uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/ + uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/ + uint32_t reserved21 : 11; /*reserved*/ }; uint32_t val; } dma_int_ena; union { struct { - uint32_t infifo_full_err: 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err: 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi: 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi: 1; /*The clear bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7: 1; /*The clear bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8: 1; /*The clear bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9: 1; /*The clear bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda: 1; /*The clear bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done: 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done: 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done: 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done: 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done: 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done: 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err: 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err: 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err: 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t rx_afifo_wfull_err: 1; /*The clear bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ - uint32_t mst_rx_afifo_wfull_err: 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ - uint32_t buf_tx_afifo_rerr: 1; /*The clear bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ - uint32_t dma_tx_afifo_rerr: 1; /*The clear bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ - uint32_t mst_tx_afifo_rerr: 1; /*The clear bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi : 1; /*The clear bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7 : 1; /*The clear bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8 : 1; /*The clear bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done : 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done : 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ + uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ + uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/ + uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/ + uint32_t reserved21 : 11; /*reserved*/ }; uint32_t val; } dma_int_clr; union { struct { - uint32_t infifo_full_err: 1; /*1: The current data rate of DMA Rx is smaller than that of SPI which will lose the receive data. 0: Others.*/ - uint32_t outfifo_empty_err: 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.*/ - uint32_t ex_qpi: 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/ - uint32_t en_qpi: 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/ - uint32_t cmd7: 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/ - uint32_t cmd8: 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/ - uint32_t cmd9: 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/ - uint32_t cmda: 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/ - uint32_t rd_dma_done: 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/ - uint32_t wr_dma_done: 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/ - uint32_t rd_buf_done: 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/ - uint32_t wr_buf_done: 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/ - uint32_t trans_done: 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/ - uint32_t dma_seg_trans_done: 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.*/ - uint32_t seg_magic_err: 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ - uint32_t buf_addr_err: 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ - uint32_t cmd_err: 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ - uint32_t rx_afifo_wfull_err: 1; /*The raw bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt. 1: SPI AFIFO overflow when SPI slave reads data in CPU/DMA controlled mode. 0: Others.*/ - uint32_t mst_rx_afifo_wfull_err: 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: SPI AFIFO overflow when SPI master reads data in CPU/DMA controlled mode. 0: Others.*/ - uint32_t buf_tx_afifo_rerr: 1; /*The raw bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI slave sent data out in CPU controlled mode 0: Others.*/ - uint32_t dma_tx_afifo_rerr: 1; /*The raw bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI slave sent data out in DMA controlled mode 0: Others.*/ - uint32_t mst_tx_afifo_rerr: 1; /*The raw bit for SPI_MST_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI master sends data out in CPU/DMA controlled mode. 0: Others.*/ - uint32_t reserved22: 10; /*SPI interrupt raw register. Can be configured in CONF state.*/ + uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */ + uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */ + uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/ + uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/ + uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/ + uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/ + uint32_t cmd9 : 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/ + uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/ + uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/ + uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/ + uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/ + uint32_t wr_buf_done : 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/ + uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/ + uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */ + uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ + uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ + uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ + uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/ + uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/ + uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/ + uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/ + uint32_t reserved21 : 11; /*reserved*/ }; uint32_t val; } dma_int_raw; union { struct { - uint32_t infifo_full_err: 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err: 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi: 1; /*The status bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi: 1; /*The status bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7: 1; /*The status bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8: 1; /*The status bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9: 1; /*The status bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda: 1; /*The status bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done: 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done: 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done: 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done: 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done: 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done: 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err: 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err: 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err: 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t rx_afifo_wfull_err: 1; /*The status bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ - uint32_t mst_rx_afifo_wfull_err: 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ - uint32_t buf_tx_afifo_rerr: 1; /*The status bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ - uint32_t dma_tx_afifo_rerr: 1; /*The status bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ - uint32_t mst_tx_afifo_rerr: 1; /*The status bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t infifo_full_err : 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err : 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done : 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done : 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ + uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ + uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/ + uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/ + uint32_t reserved21 : 11; /*reserved*/ }; uint32_t val; } dma_int_st; - uint32_t reserved_44; + union { + struct { + uint32_t infifo_full_err_int_set : 1; /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err_int_set : 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi_int_set : 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi_int_set : 1; /*The software set bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7_int_set : 1; /*The software set bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8_int_set : 1; /*The software set bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9_int_set : 1; /*The software set bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda_int_set : 1; /*The software set bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done_int_set : 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done_int_set : 1; /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done_int_set : 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done_int_set : 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done_int_set : 1; /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done_int_set : 1; /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err_int_set : 1; /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err_int_set : 1; /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err_int_set : 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ + uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ + uint32_t app2_int_set : 1; /*The software set bit for SPI_APP2_INT interrupt.*/ + uint32_t app1_int_set : 1; /*The software set bit for SPI_APP1_INT interrupt.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } dma_int_set; uint32_t reserved_48; uint32_t reserved_4c; uint32_t reserved_50; @@ -341,58 +366,58 @@ typedef volatile struct { uint32_t reserved_8c; uint32_t reserved_90; uint32_t reserved_94; - uint32_t data_buf[16]; /*data buffer*/ + uint32_t data_buf[16]; /*SPI CPU-controlled buffer0*/ uint32_t reserved_d8; uint32_t reserved_dc; union { struct { - uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ - uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ - uint32_t rsck_data_out: 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge*/ - uint32_t reserved4: 4; /*reserved*/ - uint32_t rddma_bitlen_en: 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/ - uint32_t wrdma_bitlen_en: 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/ - uint32_t rdbuf_bitlen_en: 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/ - uint32_t wrbuf_bitlen_en: 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/ - uint32_t reserved12: 10; /*reserved*/ - uint32_t dma_seg_magic_value: 4; /*The magic value of BM table in master DMA seg-trans.*/ - uint32_t slave_mode: 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ - uint32_t soft_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines. Can be configured in CONF state.*/ - uint32_t usr_conf: 1; /*1: Enable the DMA CONF phase of current seg-trans operation which means seg-trans will start. 0: This is not seg-trans mode.*/ - uint32_t reserved29: 3; /*reserved*/ + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ + uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ + uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ + uint32_t reserved4 : 4; /*reserved*/ + uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/ + uint32_t wrdma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/ + uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/ + uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/ + uint32_t reserved12 : 10; /*reserved*/ + uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/ + uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ + uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/ + uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/ + uint32_t reserved29 : 3; /*reserved*/ }; uint32_t val; } slave; union { struct { - uint32_t data_bitlen: 18; /*The transferred data bit length in SPI slave FD and HD mode.*/ - uint32_t last_command: 8; /*In the slave mode it is the value of command.*/ - uint32_t last_addr: 6; /*In the slave mode it is the value of address.*/ + uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */ + uint32_t last_command : 8; /*In the slave mode it is the value of command.*/ + uint32_t last_addr : 6; /*In the slave mode it is the value of address.*/ }; uint32_t val; } slave1; union { struct { - uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ - uint32_t mst_clk_active: 1; /*Set this bit to power on the SPI module clock.*/ - uint32_t mst_clk_sel: 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ - uint32_t reserved3: 29; /*reserved*/ + uint32_t clk_en : 1; /*Set this bit to enable clk gate*/ + uint32_t mst_clk_active : 1; /*Set this bit to power on the SPI module clock.*/ + uint32_t mst_clk_sel : 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ + uint32_t reserved3 : 29; /*reserved*/ }; uint32_t val; } clk_gate; uint32_t reserved_ec; union { struct { - uint32_t date: 28; /*SPI register version.*/ - uint32_t reserved28: 4; /*reserved*/ + uint32_t date : 28; /*SPI register version.*/ + uint32_t reserved28 : 4; /*reserved*/ }; uint32_t val; } date; } spi_dev_t; - extern spi_dev_t GPSPI2; extern spi_dev_t GPSPI3; - #ifdef __cplusplus } #endif + +#endif /* _SOC_SPI_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/sys_timer_reg.h b/components/soc/esp32s3/include/soc/sys_timer_reg.h index 090663a2b5..55c1802312 100644 --- a/components/soc/esp32s3/include/soc/sys_timer_reg.h +++ b/components/soc/esp32s3/include/soc/sys_timer_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,410 +11,464 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SYS_TIMER_REG_H_ +#define _SOC_SYS_TIMER_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000) +#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0) /* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: register file clk gating*/ -#define SYS_TIMER_CLK_EN (BIT(31)) -#define SYS_TIMER_CLK_EN_M (BIT(31)) -#define SYS_TIMER_CLK_EN_V 0x1 -#define SYS_TIMER_CLK_EN_S 31 +/*description: register file clk gating.*/ +#define SYS_TIMER_CLK_EN (BIT(31)) +#define SYS_TIMER_CLK_EN_M (BIT(31)) +#define SYS_TIMER_CLK_EN_V 0x1 +#define SYS_TIMER_CLK_EN_S 31 /* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: timer unit0 work enable*/ -#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 +/*description: timer unit0 work enable.*/ +#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 /* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer unit1 work enable*/ -#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 +/*description: timer unit1 work enable.*/ +#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 /* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core0 stalled*/ -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/*description: If timer unit0 is stalled when core0 stalled.*/ +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 /* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core1 stalled*/ -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/*description: If timer unit0 is stalled when core1 stalled.*/ +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 /* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core0 stalled*/ -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/*description: If timer unit1 is stalled when core0 stalled.*/ +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 /* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core1 stalled*/ -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/*description: If timer unit1 is stalled when core1 stalled.*/ +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 /* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: target0 work enable*/ -#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET0_WORK_EN_S 24 +/*description: target0 work enable.*/ +#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) +#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) +#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET0_WORK_EN_S 24 /* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: target1 work enable*/ -#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET1_WORK_EN_S 23 +/*description: target1 work enable.*/ +#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) +#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) +#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET1_WORK_EN_S 23 /* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: target2 work enable*/ -#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET2_WORK_EN_S 22 +/*description: target2 work enable.*/ +#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) +#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) +#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET2_WORK_EN_S 22 /* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: systimer clock force on*/ -#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 -#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 +/*description: systimer clock force on.*/ +#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) +#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 +#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004) -/* SYS_TIMER_TIMER_UNIT0_UPDATE : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer_unit0*/ -#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 +#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x4) +/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: update timer_unit0.*/ +#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 +/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 -#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008) -/* SYS_TIMER_TIMER_UNIT1_UPDATE : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer unit1*/ -#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer value is sync and valid*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 +#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x8) +/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: update timer unit1.*/ +#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 +/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: timer value is sync and valid.*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000C) +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0xC) /* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit0 load high 32 bit*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V) << (SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 +/*description: timer unit0 load high 32 bit.*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010) +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x10) /* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit0 load low 32 bit*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V) << (SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 +/*description: timer unit0 load low 32 bit.*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014) +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x14) /* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit1 load high 32 bit*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V) << (SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 +/*description: timer unit1 load high 32 bit.*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018) +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x18) /* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit1 load low 32 bit*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V) << (SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 +/*description: timer unit1 load low 32 bit.*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001C) +#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x1C) /* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget0 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V) << (SYS_TIMER_TIMER_TARGET0_HI_S)) -#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_S 0 +/*description: timer taget0 high 32 bit.*/ +#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S)) +#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET0_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020) +#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x20) /* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget0 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V) << (SYS_TIMER_TIMER_TARGET0_LO_S)) -#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_S 0 +/*description: timer taget0 low 32 bit.*/ +#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S)) +#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET0_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024) +#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x24) /* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget1 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V) << (SYS_TIMER_TIMER_TARGET1_HI_S)) -#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_S 0 +/*description: timer taget1 high 32 bit.*/ +#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S)) +#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET1_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028) +#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x28) /* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget1 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V) << (SYS_TIMER_TIMER_TARGET1_LO_S)) -#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_S 0 +/*description: timer taget1 low 32 bit.*/ +#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S)) +#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET1_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002C) +#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x2C) /* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget2 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V) << (SYS_TIMER_TIMER_TARGET2_HI_S)) -#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_S 0 +/*description: timer taget2 high 32 bit.*/ +#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S)) +#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET2_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030) +#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x30) /* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget2 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V) << (SYS_TIMER_TIMER_TARGET2_LO_S)) -#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_S 0 +/*description: timer taget2 low 32 bit.*/ +#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S)) +#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET2_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034) +#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x34) /* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 +/*description: select which unit to compare.*/ +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 /* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target0 to period mode*/ -#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 +/*description: Set target0 to period mode.*/ +#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 /* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target0 period*/ -#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V) << (SYS_TIMER_TARGET0_PERIOD_S)) -#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_S 0 +/*description: target0 period.*/ +#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S)) +#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET0_PERIOD_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038) +#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x38) /* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 +/*description: select which unit to compare.*/ +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 /* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target1 to period mode*/ -#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 +/*description: Set target1 to period mode.*/ +#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 /* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target1 period*/ -#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V) << (SYS_TIMER_TARGET1_PERIOD_S)) -#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_S 0 +/*description: target1 period.*/ +#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S)) +#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET1_PERIOD_S 0 -#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003C) +#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x3C) /* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 +/*description: select which unit to compare.*/ +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 /* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target2 to period mode*/ -#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 +/*description: Set target2 to period mode.*/ +#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 /* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target2 period*/ -#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V) << (SYS_TIMER_TARGET2_PERIOD_S)) -#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_S 0 +/*description: target2 period.*/ +#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S)) +#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET2_PERIOD_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040) +#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x40) /* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V) << (SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 +/*description: timer read value high 32bit.*/ +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044) +#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x44) /* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V) << (SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 +/*description: timer read value low 32bit.*/ +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048) +#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x48) /* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V) << (SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 +/*description: timer read value high 32bit.*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004C) +#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x4C) /* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V) << (SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 +/*description: timer read value low 32bit.*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 -#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050) -/* SYS_TIMER_TIMER_COMP0_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp0 load value*/ -#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x50) +/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp0 load value.*/ +#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054) -/* SYS_TIMER_TIMER_COMP1_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp1 load value*/ -#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x54) +/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp1 load value.*/ +#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058) -/* SYS_TIMER_TIMER_COMP2_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp2 load value*/ -#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x58) +/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp2 load value.*/ +#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005C) -/* SYS_TIMER_TIMER_UNIT0_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit0 load value*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x5C) +/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer unit0 load value.*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060) -/* SYS_TIMER_TIMER_UNIT1_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit1 load value*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x60) +/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer unit1 load value.*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064) -/* SYS_TIMER_SYSTIMER_INT2_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 enable*/ -#define SYS_TIMER_SYSTIMER_INT2_ENA (BIT(2)) -#define SYS_TIMER_SYSTIMER_INT2_ENA_M (BIT(2)) -#define SYS_TIMER_SYSTIMER_INT2_ENA_V 0x1 -#define SYS_TIMER_SYSTIMER_INT2_ENA_S 2 -/* SYS_TIMER_SYSTIMER_INT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 enable*/ -#define SYS_TIMER_SYSTIMER_INT1_ENA (BIT(1)) -#define SYS_TIMER_SYSTIMER_INT1_ENA_M (BIT(1)) -#define SYS_TIMER_SYSTIMER_INT1_ENA_V 0x1 -#define SYS_TIMER_SYSTIMER_INT1_ENA_S 1 -/* SYS_TIMER_SYSTIMER_INT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 enable*/ -#define SYS_TIMER_SYSTIMER_INT0_ENA (BIT(0)) -#define SYS_TIMER_SYSTIMER_INT0_ENA_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_INT0_ENA_V 0x1 -#define SYS_TIMER_SYSTIMER_INT0_ENA_S 0 +#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x64) +/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 enable.*/ +#define SYS_TIMER_TARGET2_INT_ENA (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET2_INT_ENA_S 2 +/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 enable.*/ +#define SYS_TIMER_TARGET1_INT_ENA (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET1_INT_ENA_S 1 +/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 enable.*/ +#define SYS_TIMER_TARGET0_INT_ENA (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET0_INT_ENA_S 0 -#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068) -/* SYS_TIMER_SYSTIMER_INT2_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 raw*/ -#define SYS_TIMER_SYSTIMER_INT2_RAW (BIT(2)) -#define SYS_TIMER_SYSTIMER_INT2_RAW_M (BIT(2)) -#define SYS_TIMER_SYSTIMER_INT2_RAW_V 0x1 -#define SYS_TIMER_SYSTIMER_INT2_RAW_S 2 -/* SYS_TIMER_SYSTIMER_INT1_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 raw*/ -#define SYS_TIMER_SYSTIMER_INT1_RAW (BIT(1)) -#define SYS_TIMER_SYSTIMER_INT1_RAW_M (BIT(1)) -#define SYS_TIMER_SYSTIMER_INT1_RAW_V 0x1 -#define SYS_TIMER_SYSTIMER_INT1_RAW_S 1 -/* SYS_TIMER_SYSTIMER_INT0_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 raw*/ -#define SYS_TIMER_SYSTIMER_INT0_RAW (BIT(0)) -#define SYS_TIMER_SYSTIMER_INT0_RAW_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_INT0_RAW_V 0x1 -#define SYS_TIMER_SYSTIMER_INT0_RAW_S 0 +#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x68) +/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 raw.*/ +#define SYS_TIMER_TARGET2_INT_RAW (BIT(2)) +#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET2_INT_RAW_S 2 +/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 raw.*/ +#define SYS_TIMER_TARGET1_INT_RAW (BIT(1)) +#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET1_INT_RAW_S 1 +/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 raw.*/ +#define SYS_TIMER_TARGET0_INT_RAW (BIT(0)) +#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET0_INT_RAW_S 0 -#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c) -/* SYS_TIMER_SYSTIMER_INT2_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 clear*/ -#define SYS_TIMER_SYSTIMER_INT2_CLR (BIT(2)) -#define SYS_TIMER_SYSTIMER_INT2_CLR_M (BIT(2)) -#define SYS_TIMER_SYSTIMER_INT2_CLR_V 0x1 -#define SYS_TIMER_SYSTIMER_INT2_CLR_S 2 -/* SYS_TIMER_SYSTIMER_INT1_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 clear*/ -#define SYS_TIMER_SYSTIMER_INT1_CLR (BIT(1)) -#define SYS_TIMER_SYSTIMER_INT1_CLR_M (BIT(1)) -#define SYS_TIMER_SYSTIMER_INT1_CLR_V 0x1 -#define SYS_TIMER_SYSTIMER_INT1_CLR_S 1 -/* SYS_TIMER_SYSTIMER_INT0_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 clear*/ -#define SYS_TIMER_SYSTIMER_INT0_CLR (BIT(0)) -#define SYS_TIMER_SYSTIMER_INT0_CLR_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_INT0_CLR_V 0x1 -#define SYS_TIMER_SYSTIMER_INT0_CLR_S 0 +#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x6C) +/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 clear.*/ +#define SYS_TIMER_TARGET2_INT_CLR (BIT(2)) +#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET2_INT_CLR_S 2 +/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 clear.*/ +#define SYS_TIMER_TARGET1_INT_CLR (BIT(1)) +#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET1_INT_CLR_S 1 +/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 clear.*/ +#define SYS_TIMER_TARGET0_INT_CLR (BIT(0)) +#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET0_INT_CLR_S 0 -#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070) -/* SYS_TIMER_SYSTIMER_INT2_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_SYSTIMER_INT2_ST (BIT(2)) -#define SYS_TIMER_SYSTIMER_INT2_ST_M (BIT(2)) -#define SYS_TIMER_SYSTIMER_INT2_ST_V 0x1 -#define SYS_TIMER_SYSTIMER_INT2_ST_S 2 -/* SYS_TIMER_SYSTIMER_INT1_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_SYSTIMER_INT1_ST (BIT(1)) -#define SYS_TIMER_SYSTIMER_INT1_ST_M (BIT(1)) -#define SYS_TIMER_SYSTIMER_INT1_ST_V 0x1 -#define SYS_TIMER_SYSTIMER_INT1_ST_S 1 -/* SYS_TIMER_SYSTIMER_INT0_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_SYSTIMER_INT0_ST (BIT(0)) -#define SYS_TIMER_SYSTIMER_INT0_ST_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_INT0_ST_V 0x1 -#define SYS_TIMER_SYSTIMER_INT0_ST_S 0 +#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x70) +/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET2_INT_ST (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ST_V 0x1 +#define SYS_TIMER_TARGET2_INT_ST_S 2 +/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET1_INT_ST (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ST_V 0x1 +#define SYS_TIMER_TARGET1_INT_ST_S 1 +/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET0_INT_ST (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ST_V 0x1 +#define SYS_TIMER_TARGET0_INT_ST_S 0 + +#define SYS_TIMER_SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x74) +/* SYS_TIMER_TARGET0_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET0_LO_RO 0xFFFFFFFF +#define SYS_TIMER_TARGET0_LO_RO_M ((SYS_TIMER_TARGET0_LO_RO_V)<<(SYS_TIMER_TARGET0_LO_RO_S)) +#define SYS_TIMER_TARGET0_LO_RO_V 0xFFFFFFFF +#define SYS_TIMER_TARGET0_LO_RO_S 0 + +#define SYS_TIMER_SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x78) +/* SYS_TIMER_TARGET0_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET0_HI_RO 0x000FFFFF +#define SYS_TIMER_TARGET0_HI_RO_M ((SYS_TIMER_TARGET0_HI_RO_V)<<(SYS_TIMER_TARGET0_HI_RO_S)) +#define SYS_TIMER_TARGET0_HI_RO_V 0xFFFFF +#define SYS_TIMER_TARGET0_HI_RO_S 0 + +#define SYS_TIMER_SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x7C) +/* SYS_TIMER_TARGET1_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET1_LO_RO 0xFFFFFFFF +#define SYS_TIMER_TARGET1_LO_RO_M ((SYS_TIMER_TARGET1_LO_RO_V)<<(SYS_TIMER_TARGET1_LO_RO_S)) +#define SYS_TIMER_TARGET1_LO_RO_V 0xFFFFFFFF +#define SYS_TIMER_TARGET1_LO_RO_S 0 + +#define SYS_TIMER_SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x80) +/* SYS_TIMER_TARGET1_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET1_HI_RO 0x000FFFFF +#define SYS_TIMER_TARGET1_HI_RO_M ((SYS_TIMER_TARGET1_HI_RO_V)<<(SYS_TIMER_TARGET1_HI_RO_S)) +#define SYS_TIMER_TARGET1_HI_RO_V 0xFFFFF +#define SYS_TIMER_TARGET1_HI_RO_S 0 + +#define SYS_TIMER_SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x84) +/* SYS_TIMER_TARGET2_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET2_LO_RO 0xFFFFFFFF +#define SYS_TIMER_TARGET2_LO_RO_M ((SYS_TIMER_TARGET2_LO_RO_V)<<(SYS_TIMER_TARGET2_LO_RO_S)) +#define SYS_TIMER_TARGET2_LO_RO_V 0xFFFFFFFF +#define SYS_TIMER_TARGET2_LO_RO_S 0 + +#define SYS_TIMER_SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x88) +/* SYS_TIMER_TARGET2_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: .*/ +#define SYS_TIMER_TARGET2_HI_RO 0x000FFFFF +#define SYS_TIMER_TARGET2_HI_RO_M ((SYS_TIMER_TARGET2_HI_RO_V)<<(SYS_TIMER_TARGET2_HI_RO_S)) +#define SYS_TIMER_TARGET2_HI_RO_V 0xFFFFF +#define SYS_TIMER_TARGET2_HI_RO_S 0 + +#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0xFC) +/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2012251 ; */ +/*description: .*/ +#define SYS_TIMER_DATE 0xFFFFFFFF +#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S)) +#define SYS_TIMER_DATE_V 0xFFFFFFFF +#define SYS_TIMER_DATE_S 0 -#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc) -/* SYS_TIMER_SYSTIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2003071 ; */ -/*description: */ -#define SYS_TIMER_SYSTIMER_DATE 0xFFFFFFFF -#define SYS_TIMER_SYSTIMER_DATE_M ((SYS_TIMER_SYSTIMER_DATE_V) << (SYS_TIMER_SYSTIMER_DATE_S)) -#define SYS_TIMER_SYSTIMER_DATE_V 0xFFFFFFFF -#define SYS_TIMER_SYSTIMER_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SYS_TIMER_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/sys_timer_struct.h b/components/soc/esp32s3/include/soc/sys_timer_struct.h index e6689754da..1641f7e44c 100644 --- a/components/soc/esp32s3/include/soc/sys_timer_struct.h +++ b/components/soc/esp32s3/include/soc/sys_timer_struct.h @@ -11,8 +11,8 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_SYS_TIMER_STRUCT_H_ +#define _SOC_SYS_TIMER_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif @@ -22,199 +22,217 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t systimer_clk_fo: 1; /*systimer clock force on*/ - uint32_t reserved1: 21; - uint32_t target2_work_en: 1; /*target2 work enable*/ - uint32_t target1_work_en: 1; /*target1 work enable*/ - uint32_t target0_work_en: 1; /*target0 work enable*/ - uint32_t timer_unit1_core1_stall_en: 1; /*If timer unit1 is stalled when core1 stalled*/ - uint32_t timer_unit1_core0_stall_en: 1; /*If timer unit1 is stalled when core0 stalled*/ - uint32_t timer_unit0_core1_stall_en: 1; /*If timer unit0 is stalled when core1 stalled*/ - uint32_t timer_unit0_core0_stall_en: 1; /*If timer unit0 is stalled when core0 stalled*/ - uint32_t timer_unit1_work_en: 1; /*timer unit1 work enable*/ - uint32_t timer_unit0_work_en: 1; /*timer unit0 work enable*/ - uint32_t clk_en: 1; /*register file clk gating*/ + uint32_t systimer_clk_fo : 1; /*systimer clock force on*/ + uint32_t reserved1 : 21; + uint32_t target2_work_en : 1; /*target2 work enable*/ + uint32_t target1_work_en : 1; /*target1 work enable*/ + uint32_t target0_work_en : 1; /*target0 work enable*/ + uint32_t timer_unit1_core1_stall_en : 1; /*If timer unit1 is stalled when core1 stalled*/ + uint32_t timer_unit1_core0_stall_en : 1; /*If timer unit1 is stalled when core0 stalled*/ + uint32_t timer_unit0_core1_stall_en : 1; /*If timer unit0 is stalled when core1 stalled*/ + uint32_t timer_unit0_core0_stall_en : 1; /*If timer unit0 is stalled when core0 stalled*/ + uint32_t timer_unit1_work_en : 1; /*timer unit1 work enable*/ + uint32_t timer_unit0_work_en : 1; /*timer unit0 work enable*/ + uint32_t clk_en : 1; /*register file clk gating*/ }; uint32_t val; } systimer_conf; union { struct { - uint32_t reserved0: 29; - uint32_t timer_unit0_value_valid: 1; - uint32_t timer_unit0_update: 1; /*update timer_unit0*/ - uint32_t reserved31: 1; + uint32_t reserved0 : 29; + uint32_t timer_unit0_value_valid : 1; + uint32_t timer_unit0_update : 1; /*update timer_unit0*/ + uint32_t reserved31 : 1; }; uint32_t val; } systimer_unit0_op; union { struct { - uint32_t reserved0: 29; - uint32_t timer_unit1_value_valid: 1; /*timer value is sync and valid*/ - uint32_t timer_unit1_update: 1; /*update timer unit1*/ - uint32_t reserved31: 1; + uint32_t reserved0 : 29; + uint32_t timer_unit1_value_valid : 1; /*timer value is sync and valid*/ + uint32_t timer_unit1_update : 1; /*update timer unit1*/ + uint32_t reserved31 : 1; }; uint32_t val; } systimer_unit1_op; union { struct { - uint32_t timer_unit0_load_hi: 20; /*timer unit0 load high 32 bit*/ - uint32_t reserved20: 12; + uint32_t timer_unit0_load_hi : 20; /*timer unit0 load high 32 bit*/ + uint32_t reserved20 : 12; }; uint32_t val; } systimer_unit0_load_hi; - uint32_t systimer_unit0_load_lo; /*timer unit0 load low 32 bit*/ + uint32_t systimer_unit0_load_lo; union { struct { - uint32_t timer_unit1_load_hi: 20; /*timer unit1 load high 32 bit*/ - uint32_t reserved20: 12; + uint32_t timer_unit1_load_hi : 20; /*timer unit1 load high 32 bit*/ + uint32_t reserved20 : 12; }; uint32_t val; } systimer_unit1_load_hi; - uint32_t systimer_unit1_load_lo; /*timer unit1 load low 32 bit*/ + uint32_t systimer_unit1_load_lo; union { struct { - uint32_t timer_target0_hi: 20; /*timer taget0 high 32 bit*/ - uint32_t reserved20: 12; + uint32_t timer_target0_hi : 20; /*timer taget0 high 32 bit*/ + uint32_t reserved20 : 12; }; uint32_t val; } systimer_target0_hi; - uint32_t systimer_target0_lo; /*timer taget0 low 32 bit*/ + uint32_t systimer_target0_lo; union { struct { - uint32_t timer_target1_hi: 20; /*timer taget1 high 32 bit*/ - uint32_t reserved20: 12; + uint32_t timer_target1_hi : 20; /*timer taget1 high 32 bit*/ + uint32_t reserved20 : 12; }; uint32_t val; } systimer_target1_hi; - uint32_t systimer_target1_lo; /*timer taget1 low 32 bit*/ + uint32_t systimer_target1_lo; union { struct { - uint32_t timer_target2_hi: 20; /*timer taget2 high 32 bit*/ - uint32_t reserved20: 12; + uint32_t timer_target2_hi : 20; /*timer taget2 high 32 bit*/ + uint32_t reserved20 : 12; }; uint32_t val; } systimer_target2_hi; - uint32_t systimer_target2_lo; /*timer taget2 low 32 bit*/ + uint32_t systimer_target2_lo; union { struct { - uint32_t target0_period: 26; /*target0 period*/ - uint32_t reserved26: 4; - uint32_t target0_period_mode: 1; /*Set target0 to period mode*/ - uint32_t target0_timer_unit_sel: 1; /*select which unit to compare*/ + uint32_t target0_period : 26; /*target0 period*/ + uint32_t reserved26 : 4; + uint32_t target0_period_mode : 1; /*Set target0 to period mode*/ + uint32_t target0_timer_unit_sel : 1; /*select which unit to compare*/ }; uint32_t val; } systimer_target0_conf; union { struct { - uint32_t target1_period: 26; /*target1 period*/ - uint32_t reserved26: 4; - uint32_t target1_period_mode: 1; /*Set target1 to period mode*/ - uint32_t target1_timer_unit_sel: 1; /*select which unit to compare*/ + uint32_t target1_period : 26; /*target1 period*/ + uint32_t reserved26 : 4; + uint32_t target1_period_mode : 1; /*Set target1 to period mode*/ + uint32_t target1_timer_unit_sel : 1; /*select which unit to compare*/ }; uint32_t val; } systimer_target1_conf; union { struct { - uint32_t target2_period: 26; /*target2 period*/ - uint32_t reserved26: 4; - uint32_t target2_period_mode: 1; /*Set target2 to period mode*/ - uint32_t target2_timer_unit_sel: 1; /*select which unit to compare*/ + uint32_t target2_period : 26; /*target2 period*/ + uint32_t reserved26 : 4; + uint32_t target2_period_mode : 1; /*Set target2 to period mode*/ + uint32_t target2_timer_unit_sel : 1; /*select which unit to compare*/ }; uint32_t val; } systimer_target2_conf; union { struct { - uint32_t timer_unit0_value_hi: 20; /*timer read value high 32bit*/ - uint32_t reserved20: 12; + uint32_t timer_unit0_value_hi : 20; /*timer read value high 32bit*/ + uint32_t reserved20 : 12; }; uint32_t val; } systimer_unit0_value_hi; - uint32_t systimer_unit0_value_lo; /*timer read value low 32bit*/ + uint32_t systimer_unit0_value_lo; union { struct { - uint32_t timer_unit1_value_hi: 20; /*timer read value high 32bit*/ - uint32_t reserved20: 12; + uint32_t timer_unit1_value_hi : 20; /*timer read value high 32bit*/ + uint32_t reserved20 : 12; }; uint32_t val; } systimer_unit1_value_hi; - uint32_t systimer_unit1_value_lo; /*timer read value low 32bit*/ + uint32_t systimer_unit1_value_lo; union { struct { - uint32_t timer_comp0_load: 1; /*timer comp0 load value*/ - uint32_t reserved1: 31; + uint32_t timer_comp0_load : 1; /*timer comp0 load value*/ + uint32_t reserved1 : 31; }; uint32_t val; } systimer_comp0_load; union { struct { - uint32_t timer_comp1_load: 1; /*timer comp1 load value*/ - uint32_t reserved1: 31; + uint32_t timer_comp1_load : 1; /*timer comp1 load value*/ + uint32_t reserved1 : 31; }; uint32_t val; } systimer_comp1_load; union { struct { - uint32_t timer_comp2_load: 1; /*timer comp2 load value*/ - uint32_t reserved1: 31; + uint32_t timer_comp2_load : 1; /*timer comp2 load value*/ + uint32_t reserved1 : 31; }; uint32_t val; } systimer_comp2_load; union { struct { - uint32_t timer_unit0_load: 1; /*timer unit0 load value*/ - uint32_t reserved1: 31; + uint32_t timer_unit0_load : 1; /*timer unit0 load value*/ + uint32_t reserved1 : 31; }; uint32_t val; } systimer_unit0_load; union { struct { - uint32_t timer_unit1_load: 1; /*timer unit1 load value*/ - uint32_t reserved1: 31; + uint32_t timer_unit1_load : 1; /*timer unit1 load value*/ + uint32_t reserved1 : 31; }; uint32_t val; } systimer_unit1_load; union { struct { - uint32_t systimer_int0_ena: 1; /*interupt0 enable*/ - uint32_t systimer_int1_ena: 1; /*interupt1 enable*/ - uint32_t systimer_int2_ena: 1; /*interupt2 enable*/ - uint32_t reserved3: 29; + uint32_t target0 : 1; /*interupt0 enable*/ + uint32_t target1 : 1; /*interupt1 enable*/ + uint32_t target2 : 1; /*interupt2 enable*/ + uint32_t reserved3 : 29; }; uint32_t val; } systimer_int_ena; union { struct { - uint32_t systimer_int0_raw: 1; /*interupt0 raw*/ - uint32_t systimer_int1_raw: 1; /*interupt1 raw*/ - uint32_t systimer_int2_raw: 1; /*interupt2 raw*/ - uint32_t reserved3: 29; + uint32_t target0 : 1; /*interupt0 raw*/ + uint32_t target1 : 1; /*interupt1 raw*/ + uint32_t target2 : 1; /*interupt2 raw*/ + uint32_t reserved3 : 29; }; uint32_t val; } systimer_int_raw; union { struct { - uint32_t systimer_int0_clr: 1; /*interupt0 clear*/ - uint32_t systimer_int1_clr: 1; /*interupt1 clear*/ - uint32_t systimer_int2_clr: 1; /*interupt2 clear*/ - uint32_t reserved3: 29; + uint32_t target0 : 1; /*interupt0 clear*/ + uint32_t target1 : 1; /*interupt1 clear*/ + uint32_t target2 : 1; /*interupt2 clear*/ + uint32_t reserved3 : 29; }; uint32_t val; } systimer_int_clr; union { struct { - uint32_t systimer_int0_st: 1; - uint32_t systimer_int1_st: 1; - uint32_t systimer_int2_st: 1; - uint32_t reserved3: 29; + uint32_t target0 : 1; + uint32_t target1 : 1; + uint32_t target2 : 1; + uint32_t reserved3 : 29; }; uint32_t val; } systimer_int_st; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; + uint32_t systimer_real_target0_lo; + union { + struct { + uint32_t target0_hi_ro : 20; + uint32_t reserved20 : 12; + }; + uint32_t val; + } systimer_real_target0_hi; + uint32_t systimer_real_target1_lo; + union { + struct { + uint32_t target1_hi_ro : 20; + uint32_t reserved20 : 12; + }; + uint32_t val; + } systimer_real_target1_hi; + uint32_t systimer_real_target2_lo; + union { + struct { + uint32_t target2_hi_ro : 20; + uint32_t reserved20 : 12; + }; + uint32_t val; + } systimer_real_target2_hi; uint32_t reserved_8c; uint32_t reserved_90; uint32_t reserved_94; @@ -243,11 +261,11 @@ typedef volatile struct { uint32_t reserved_f0; uint32_t reserved_f4; uint32_t reserved_f8; - uint32_t systimer_date; /**/ + uint32_t systimer_date; } sys_timer_dev_t; - extern sys_timer_dev_t SYS_TIMER; - #ifdef __cplusplus } #endif + +#endif /* _SOC_SYS_TIMER_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/syscon_reg.h b/components/soc/esp32s3/include/soc/syscon_reg.h index 2ada57fd74..5ad3ba945c 100644 --- a/components/soc/esp32s3/include/soc/syscon_reg.h +++ b/components/soc/esp32s3/include/soc/syscon_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,187 +11,182 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SYSCON_REG_H_ +#define _SOC_SYSCON_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) -/* SYSCON_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: */ -#define SYSCON_SOC_CLK_SEL 0x00000003 -#define SYSCON_SOC_CLK_SEL_M ((SYSCON_SOC_CLK_SEL_V) << (SYSCON_SOC_CLK_SEL_S)) -#define SYSCON_SOC_CLK_SEL_V 0x3 -#define SYSCON_SOC_CLK_SEL_S 14 +#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_RST_TICK_CNT (BIT(12)) -#define SYSCON_RST_TICK_CNT_M (BIT(12)) -#define SYSCON_RST_TICK_CNT_V 0x1 -#define SYSCON_RST_TICK_CNT_S 12 +#define SYSCON_RST_TICK_CNT (BIT(12)) +#define SYSCON_RST_TICK_CNT_M (BIT(12)) +#define SYSCON_RST_TICK_CNT_V 0x1 +#define SYSCON_RST_TICK_CNT_S 12 /* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_CLK_EN (BIT(11)) -#define SYSCON_CLK_EN_M (BIT(11)) -#define SYSCON_CLK_EN_V 0x1 -#define SYSCON_CLK_EN_S 11 +#define SYSCON_CLK_EN (BIT(11)) +#define SYSCON_CLK_EN_M (BIT(11)) +#define SYSCON_CLK_EN_V 0x1 +#define SYSCON_CLK_EN_S 11 /* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_CLK_320M_EN (BIT(10)) -#define SYSCON_CLK_320M_EN_M (BIT(10)) -#define SYSCON_CLK_320M_EN_V 0x1 -#define SYSCON_CLK_320M_EN_S 10 +#define SYSCON_CLK_320M_EN (BIT(10)) +#define SYSCON_CLK_320M_EN_M (BIT(10)) +#define SYSCON_CLK_320M_EN_V 0x1 +#define SYSCON_CLK_320M_EN_S 10 /* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ /*description: */ -#define SYSCON_PRE_DIV_CNT 0x000003FF -#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V) << (SYSCON_PRE_DIV_CNT_S)) -#define SYSCON_PRE_DIV_CNT_V 0x3FF -#define SYSCON_PRE_DIV_CNT_S 0 +#define SYSCON_PRE_DIV_CNT 0x000003FF +#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) +#define SYSCON_PRE_DIV_CNT_V 0x3FF +#define SYSCON_PRE_DIV_CNT_S 0 -#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) +#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) /* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ /*description: */ -#define SYSCON_TICK_ENABLE (BIT(16)) -#define SYSCON_TICK_ENABLE_M (BIT(16)) -#define SYSCON_TICK_ENABLE_V 0x1 -#define SYSCON_TICK_ENABLE_S 16 +#define SYSCON_TICK_ENABLE (BIT(16)) +#define SYSCON_TICK_ENABLE_M (BIT(16)) +#define SYSCON_TICK_ENABLE_V 0x1 +#define SYSCON_TICK_ENABLE_S 16 /* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ /*description: */ -#define SYSCON_CK8M_TICK_NUM 0x000000FF -#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V) << (SYSCON_CK8M_TICK_NUM_S)) -#define SYSCON_CK8M_TICK_NUM_V 0xFF -#define SYSCON_CK8M_TICK_NUM_S 8 +#define SYSCON_CK8M_TICK_NUM 0x000000FF +#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) +#define SYSCON_CK8M_TICK_NUM_V 0xFF +#define SYSCON_CK8M_TICK_NUM_S 8 /* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ /*description: */ -#define SYSCON_XTAL_TICK_NUM 0x000000FF -#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V) << (SYSCON_XTAL_TICK_NUM_S)) -#define SYSCON_XTAL_TICK_NUM_V 0xFF -#define SYSCON_XTAL_TICK_NUM_S 0 +#define SYSCON_XTAL_TICK_NUM 0x000000FF +#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) +#define SYSCON_XTAL_TICK_NUM_V 0xFF +#define SYSCON_XTAL_TICK_NUM_S 0 -#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) +#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) /* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK_XTAL_OEN (BIT(10)) -#define SYSCON_CLK_XTAL_OEN_M (BIT(10)) -#define SYSCON_CLK_XTAL_OEN_V 0x1 -#define SYSCON_CLK_XTAL_OEN_S 10 +#define SYSCON_CLK_XTAL_OEN (BIT(10)) +#define SYSCON_CLK_XTAL_OEN_M (BIT(10)) +#define SYSCON_CLK_XTAL_OEN_V 0x1 +#define SYSCON_CLK_XTAL_OEN_S 10 /* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK40X_BB_OEN (BIT(9)) -#define SYSCON_CLK40X_BB_OEN_M (BIT(9)) -#define SYSCON_CLK40X_BB_OEN_V 0x1 -#define SYSCON_CLK40X_BB_OEN_S 9 +#define SYSCON_CLK40X_BB_OEN (BIT(9)) +#define SYSCON_CLK40X_BB_OEN_M (BIT(9)) +#define SYSCON_CLK40X_BB_OEN_V 0x1 +#define SYSCON_CLK40X_BB_OEN_S 9 /* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) -#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) -#define SYSCON_CLK_DAC_CPU_OEN_V 0x1 -#define SYSCON_CLK_DAC_CPU_OEN_S 8 +#define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) +#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) +#define SYSCON_CLK_DAC_CPU_OEN_V 0x1 +#define SYSCON_CLK_DAC_CPU_OEN_S 8 /* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK_ADC_INF_OEN (BIT(7)) -#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) -#define SYSCON_CLK_ADC_INF_OEN_V 0x1 -#define SYSCON_CLK_ADC_INF_OEN_S 7 +#define SYSCON_CLK_ADC_INF_OEN (BIT(7)) +#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) +#define SYSCON_CLK_ADC_INF_OEN_V 0x1 +#define SYSCON_CLK_ADC_INF_OEN_S 7 /* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK_320M_OEN (BIT(6)) -#define SYSCON_CLK_320M_OEN_M (BIT(6)) -#define SYSCON_CLK_320M_OEN_V 0x1 -#define SYSCON_CLK_320M_OEN_S 6 +#define SYSCON_CLK_320M_OEN (BIT(6)) +#define SYSCON_CLK_320M_OEN_M (BIT(6)) +#define SYSCON_CLK_320M_OEN_V 0x1 +#define SYSCON_CLK_320M_OEN_S 6 /* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK160_OEN (BIT(5)) -#define SYSCON_CLK160_OEN_M (BIT(5)) -#define SYSCON_CLK160_OEN_V 0x1 -#define SYSCON_CLK160_OEN_S 5 +#define SYSCON_CLK160_OEN (BIT(5)) +#define SYSCON_CLK160_OEN_M (BIT(5)) +#define SYSCON_CLK160_OEN_V 0x1 +#define SYSCON_CLK160_OEN_S 5 /* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK80_OEN (BIT(4)) -#define SYSCON_CLK80_OEN_M (BIT(4)) -#define SYSCON_CLK80_OEN_V 0x1 -#define SYSCON_CLK80_OEN_S 4 +#define SYSCON_CLK80_OEN (BIT(4)) +#define SYSCON_CLK80_OEN_M (BIT(4)) +#define SYSCON_CLK80_OEN_V 0x1 +#define SYSCON_CLK80_OEN_S 4 /* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK_BB_OEN (BIT(3)) -#define SYSCON_CLK_BB_OEN_M (BIT(3)) -#define SYSCON_CLK_BB_OEN_V 0x1 -#define SYSCON_CLK_BB_OEN_S 3 +#define SYSCON_CLK_BB_OEN (BIT(3)) +#define SYSCON_CLK_BB_OEN_M (BIT(3)) +#define SYSCON_CLK_BB_OEN_V 0x1 +#define SYSCON_CLK_BB_OEN_S 3 /* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK44_OEN (BIT(2)) -#define SYSCON_CLK44_OEN_M (BIT(2)) -#define SYSCON_CLK44_OEN_V 0x1 -#define SYSCON_CLK44_OEN_S 2 +#define SYSCON_CLK44_OEN (BIT(2)) +#define SYSCON_CLK44_OEN_M (BIT(2)) +#define SYSCON_CLK44_OEN_V 0x1 +#define SYSCON_CLK44_OEN_S 2 /* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK22_OEN (BIT(1)) -#define SYSCON_CLK22_OEN_M (BIT(1)) -#define SYSCON_CLK22_OEN_V 0x1 -#define SYSCON_CLK22_OEN_S 1 +#define SYSCON_CLK22_OEN (BIT(1)) +#define SYSCON_CLK22_OEN_M (BIT(1)) +#define SYSCON_CLK22_OEN_V 0x1 +#define SYSCON_CLK22_OEN_S 1 /* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_CLK20_OEN (BIT(0)) -#define SYSCON_CLK20_OEN_M (BIT(0)) -#define SYSCON_CLK20_OEN_V 0x1 -#define SYSCON_CLK20_OEN_S 0 +#define SYSCON_CLK20_OEN (BIT(0)) +#define SYSCON_CLK20_OEN_M (BIT(0)) +#define SYSCON_CLK20_OEN_V 0x1 +#define SYSCON_CLK20_OEN_S 0 -#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C) +#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C) /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF -#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V) << (SYSCON_WIFI_BB_CFG_S)) -#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF -#define SYSCON_WIFI_BB_CFG_S 0 +#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) +#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_S 0 -#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010) +#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010) /* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF -#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V) << (SYSCON_WIFI_BB_CFG_2_S)) -#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF -#define SYSCON_WIFI_BB_CFG_2_S 0 +#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) +#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_2_S 0 -#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014) +#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014) /* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ /*description: */ -#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF -#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V) << (SYSCON_WIFI_CLK_EN_S)) -#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF -#define SYSCON_WIFI_CLK_EN_S 0 +#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF +#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) +#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF +#define SYSCON_WIFI_CLK_EN_S 0 -#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018) +#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018) /* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define SYSCON_WIFI_RST 0xFFFFFFFF -#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V) << (SYSCON_WIFI_RST_S)) -#define SYSCON_WIFI_RST_V 0xFFFFFFFF -#define SYSCON_WIFI_RST_S 0 +#define SYSCON_WIFI_RST 0xFFFFFFFF +#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) +#define SYSCON_WIFI_RST_V 0xFFFFFFFF +#define SYSCON_WIFI_RST_S 0 #define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG /* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ /*description: */ -#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF +#define SYSTEM_WIFI_CLK_EN 0xFFFFFFFF #define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S)) -#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF +#define SYSTEM_WIFI_CLK_EN_V 0xFFFFFFFF #define SYSTEM_WIFI_CLK_EN_S 0 /* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21 Bit15 not included here because of the bit now can't be cleared */ -#define SYSTEM_WIFI_CLK_WIFI_EN 0x0 +#define SYSTEM_WIFI_CLK_WIFI_EN 0x003807cf #define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V) << (SYSTEM_WIFI_CLK_WIFI_EN_S)) -#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 +#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x7cf #define SYSTEM_WIFI_CLK_WIFI_EN_S 0 /* Mask for all Bluetooth clock bits - 11, 16, 17 */ -#define SYSTEM_WIFI_CLK_BT_EN 0x0 +#define SYSTEM_WIFI_CLK_BT_EN 0x61 #define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V) << (SYSTEM_WIFI_CLK_BT_EN_S)) -#define SYSTEM_WIFI_CLK_BT_EN_V 0x0 -#define SYSTEM_WIFI_CLK_BT_EN_S 0 +#define SYSTEM_WIFI_CLK_BT_EN_V 0x61 +#define SYSTEM_WIFI_CLK_BT_EN_S 11 /* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */ -#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F +#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 /* Digital team to check */ //bluetooth baseband bit11 @@ -228,324 +223,481 @@ extern "C" { #define SYSTEM_FE_RST (BIT(1)) #define SYSTEM_BB_RST (BIT(0)) -#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) +#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: */ -#define SYSCON_PERI_IO_SWAP 0x000000FF -#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V) << (SYSCON_PERI_IO_SWAP_S)) -#define SYSCON_PERI_IO_SWAP_V 0xFF -#define SYSCON_PERI_IO_SWAP_S 0 +#define SYSCON_PERI_IO_SWAP 0x000000FF +#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) +#define SYSCON_PERI_IO_SWAP_V 0xFF +#define SYSCON_PERI_IO_SWAP_S 0 -#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020) +#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020) /* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) -#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) -#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 -#define SYSCON_EXT_MEM_PMS_LOCK_S 0 +#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) +#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) +#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 +#define SYSCON_EXT_MEM_PMS_LOCK_S 0 -#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x024) -/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +#define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_SYSCON_BASE + 0x024) +/* SYSCON_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set 1 to bypass cache writeback request to external memory so + that spi will not check its attribute.*/ +#define SYSCON_WRITEBACK_BYPASS (BIT(0)) +#define SYSCON_WRITEBACK_BYPASS_M (BIT(0)) +#define SYSCON_WRITEBACK_BYPASS_V 0x1 +#define SYSCON_WRITEBACK_BYPASS_S 0 + +#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028) +/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ /*description: */ -#define SYSCON_FLASH_ACE0_ATTR 0x000000FF -#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V) << (SYSCON_FLASH_ACE0_ATTR_S)) -#define SYSCON_FLASH_ACE0_ATTR_V 0xFF -#define SYSCON_FLASH_ACE0_ATTR_S 0 +#define SYSCON_FLASH_ACE0_ATTR 0x000001FF +#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) +#define SYSCON_FLASH_ACE0_ATTR_V 0x1FF +#define SYSCON_FLASH_ACE0_ATTR_S 0 -#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x028) -/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C) +/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ /*description: */ -#define SYSCON_FLASH_ACE1_ATTR 0x000000FF -#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V) << (SYSCON_FLASH_ACE1_ATTR_S)) -#define SYSCON_FLASH_ACE1_ATTR_V 0xFF -#define SYSCON_FLASH_ACE1_ATTR_S 0 +#define SYSCON_FLASH_ACE1_ATTR 0x000001FF +#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) +#define SYSCON_FLASH_ACE1_ATTR_V 0x1FF +#define SYSCON_FLASH_ACE1_ATTR_S 0 -#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C) -/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030) +/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ /*description: */ -#define SYSCON_FLASH_ACE2_ATTR 0x000000FF -#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V) << (SYSCON_FLASH_ACE2_ATTR_S)) -#define SYSCON_FLASH_ACE2_ATTR_V 0xFF -#define SYSCON_FLASH_ACE2_ATTR_S 0 +#define SYSCON_FLASH_ACE2_ATTR 0x000001FF +#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) +#define SYSCON_FLASH_ACE2_ATTR_V 0x1FF +#define SYSCON_FLASH_ACE2_ATTR_S 0 -#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x030) -/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034) +/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ /*description: */ -#define SYSCON_FLASH_ACE3_ATTR 0x000000FF -#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V) << (SYSCON_FLASH_ACE3_ATTR_S)) -#define SYSCON_FLASH_ACE3_ATTR_V 0xFF -#define SYSCON_FLASH_ACE3_ATTR_S 0 +#define SYSCON_FLASH_ACE3_ATTR 0x000001FF +#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) +#define SYSCON_FLASH_ACE3_ATTR_V 0x1FF +#define SYSCON_FLASH_ACE3_ATTR_S 0 -#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x034) +#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038) /* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF -#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V) << (SYSCON_FLASH_ACE0_ADDR_S_S)) -#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF -#define SYSCON_FLASH_ACE0_ADDR_S_S 0 +#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) +#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE0_ADDR_S_S 0 -#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x038) +#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C) /* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ /*description: */ -#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF -#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V) << (SYSCON_FLASH_ACE1_ADDR_S_S)) -#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF -#define SYSCON_FLASH_ACE1_ADDR_S_S 0 +#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) +#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE1_ADDR_S_S 0 -#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C) +#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x040) /* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ /*description: */ -#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF -#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V) << (SYSCON_FLASH_ACE2_ADDR_S_S)) -#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF -#define SYSCON_FLASH_ACE2_ADDR_S_S 0 +#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) +#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE2_ADDR_S_S 0 -#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x040) +#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x044) /* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ /*description: */ -#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF -#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V) << (SYSCON_FLASH_ACE3_ADDR_S_S)) -#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF -#define SYSCON_FLASH_ACE3_ADDR_S_S 0 +#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) +#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE3_ADDR_S_S 0 -#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x044) +#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x048) /* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ -#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF -#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V) << (SYSCON_FLASH_ACE0_SIZE_S)) -#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF -#define SYSCON_FLASH_ACE0_SIZE_S 0 +#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) +#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE0_SIZE_S 0 -#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x048) +#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C) /* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ -#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF -#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V) << (SYSCON_FLASH_ACE1_SIZE_S)) -#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF -#define SYSCON_FLASH_ACE1_SIZE_S 0 +#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) +#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE1_SIZE_S 0 -#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C) +#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x050) /* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ -#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF -#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V) << (SYSCON_FLASH_ACE2_SIZE_S)) -#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF -#define SYSCON_FLASH_ACE2_SIZE_S 0 +#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) +#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE2_SIZE_S 0 -#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x050) +#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x054) /* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ -#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF -#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V) << (SYSCON_FLASH_ACE3_SIZE_S)) -#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF -#define SYSCON_FLASH_ACE3_SIZE_S 0 +#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) +#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE3_SIZE_S 0 -#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x054) -/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x058) +/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ /*description: */ -#define SYSCON_SRAM_ACE0_ATTR 0x000000FF -#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V) << (SYSCON_SRAM_ACE0_ATTR_S)) -#define SYSCON_SRAM_ACE0_ATTR_V 0xFF -#define SYSCON_SRAM_ACE0_ATTR_S 0 +#define SYSCON_SRAM_ACE0_ATTR 0x000001FF +#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S)) +#define SYSCON_SRAM_ACE0_ATTR_V 0x1FF +#define SYSCON_SRAM_ACE0_ATTR_S 0 -#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x058) -/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C) +/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ /*description: */ -#define SYSCON_SRAM_ACE1_ATTR 0x000000FF -#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V) << (SYSCON_SRAM_ACE1_ATTR_S)) -#define SYSCON_SRAM_ACE1_ATTR_V 0xFF -#define SYSCON_SRAM_ACE1_ATTR_S 0 +#define SYSCON_SRAM_ACE1_ATTR 0x000001FF +#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S)) +#define SYSCON_SRAM_ACE1_ATTR_V 0x1FF +#define SYSCON_SRAM_ACE1_ATTR_S 0 -#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C) -/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x060) +/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ /*description: */ -#define SYSCON_SRAM_ACE2_ATTR 0x000000FF -#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V) << (SYSCON_SRAM_ACE2_ATTR_S)) -#define SYSCON_SRAM_ACE2_ATTR_V 0xFF -#define SYSCON_SRAM_ACE2_ATTR_S 0 +#define SYSCON_SRAM_ACE2_ATTR 0x000001FF +#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S)) +#define SYSCON_SRAM_ACE2_ATTR_V 0x1FF +#define SYSCON_SRAM_ACE2_ATTR_S 0 -#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x060) -/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x064) +/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ /*description: */ -#define SYSCON_SRAM_ACE3_ATTR 0x000000FF -#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V) << (SYSCON_SRAM_ACE3_ATTR_S)) -#define SYSCON_SRAM_ACE3_ATTR_V 0xFF -#define SYSCON_SRAM_ACE3_ATTR_S 0 +#define SYSCON_SRAM_ACE3_ATTR 0x000001FF +#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S)) +#define SYSCON_SRAM_ACE3_ATTR_V 0x1FF +#define SYSCON_SRAM_ACE3_ATTR_S 0 -#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x064) +#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x068) /* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF -#define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V) << (SYSCON_SRAM_ACE0_ADDR_S_S)) -#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF -#define SYSCON_SRAM_ACE0_ADDR_S_S 0 +#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S)) +#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE0_ADDR_S_S 0 -#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x068) +#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C) /* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ /*description: */ -#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF -#define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V) << (SYSCON_SRAM_ACE1_ADDR_S_S)) -#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF -#define SYSCON_SRAM_ACE1_ADDR_S_S 0 +#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S)) +#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE1_ADDR_S_S 0 -#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C) +#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x070) /* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ /*description: */ -#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF -#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V) << (SYSCON_SRAM_ACE2_ADDR_S_S)) -#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF -#define SYSCON_SRAM_ACE2_ADDR_S_S 0 +#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S)) +#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE2_ADDR_S_S 0 -#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x070) +#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x074) /* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ /*description: */ -#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF -#define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V) << (SYSCON_SRAM_ACE3_ADDR_S_S)) -#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF -#define SYSCON_SRAM_ACE3_ADDR_S_S 0 +#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S)) +#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE3_ADDR_S_S 0 -#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x074) +#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x078) /* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ -#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF -#define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V) << (SYSCON_SRAM_ACE0_SIZE_S)) -#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF -#define SYSCON_SRAM_ACE0_SIZE_S 0 +#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S)) +#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE0_SIZE_S 0 -#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x078) +#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C) /* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ -#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF -#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V) << (SYSCON_SRAM_ACE1_SIZE_S)) -#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF -#define SYSCON_SRAM_ACE1_SIZE_S 0 +#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S)) +#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE1_SIZE_S 0 -#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C) +#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x080) /* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ -#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF -#define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V) << (SYSCON_SRAM_ACE2_SIZE_S)) -#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF -#define SYSCON_SRAM_ACE2_SIZE_S 0 +#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S)) +#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE2_SIZE_S 0 -#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x080) +#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x084) /* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ -#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF -#define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V) << (SYSCON_SRAM_ACE3_SIZE_S)) -#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF -#define SYSCON_SRAM_ACE3_SIZE_S 0 +#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S)) +#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE3_SIZE_S 0 -#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x084) +#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x088) /* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ /*description: */ -#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F -#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V) << (SYSCON_SPI_MEM_REJECT_CDE_S)) -#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F -#define SYSCON_SPI_MEM_REJECT_CDE_S 2 +#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F +#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) +#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F +#define SYSCON_SPI_MEM_REJECT_CDE_S 2 /* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) -#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) -#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 -#define SYSCON_SPI_MEM_REJECT_CLR_S 1 +#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 +#define SYSCON_SPI_MEM_REJECT_CLR_S 1 /* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) -#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) -#define SYSCON_SPI_MEM_REJECT_INT_V 0x1 -#define SYSCON_SPI_MEM_REJECT_INT_S 0 +#define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_V 0x1 +#define SYSCON_SPI_MEM_REJECT_INT_S 0 -#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x088) +#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x08C) /* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF -#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V) << (SYSCON_SPI_MEM_REJECT_ADDR_S)) -#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF -#define SYSCON_SPI_MEM_REJECT_ADDR_S 0 +#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) +#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_S 0 -#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x08C) +#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x090) /* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ /*description: */ -#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) -#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) -#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 -#define SYSCON_SDIO_WIN_ACCESS_EN_S 0 +#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) +#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) +#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 +#define SYSCON_SDIO_WIN_ACCESS_EN_S 0 -#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x090) +#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x094) /* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ /*description: */ -#define SYSCON_REDCY_ANDOR (BIT(31)) -#define SYSCON_REDCY_ANDOR_M (BIT(31)) -#define SYSCON_REDCY_ANDOR_V 0x1 -#define SYSCON_REDCY_ANDOR_S 31 +#define SYSCON_REDCY_ANDOR (BIT(31)) +#define SYSCON_REDCY_ANDOR_M (BIT(31)) +#define SYSCON_REDCY_ANDOR_V 0x1 +#define SYSCON_REDCY_ANDOR_S 31 /* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ /*description: */ -#define SYSCON_REDCY_SIG0 0x7FFFFFFF -#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V) << (SYSCON_REDCY_SIG0_S)) -#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF -#define SYSCON_REDCY_SIG0_S 0 +#define SYSCON_REDCY_SIG0 0x7FFFFFFF +#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) +#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF +#define SYSCON_REDCY_SIG0_S 0 -#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x094) +#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x098) /* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ /*description: */ -#define SYSCON_REDCY_NANDOR (BIT(31)) -#define SYSCON_REDCY_NANDOR_M (BIT(31)) -#define SYSCON_REDCY_NANDOR_V 0x1 -#define SYSCON_REDCY_NANDOR_S 31 +#define SYSCON_REDCY_NANDOR (BIT(31)) +#define SYSCON_REDCY_NANDOR_M (BIT(31)) +#define SYSCON_REDCY_NANDOR_V 0x1 +#define SYSCON_REDCY_NANDOR_S 31 /* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ /*description: */ -#define SYSCON_REDCY_SIG1 0x7FFFFFFF -#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V) << (SYSCON_REDCY_SIG1_S)) -#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF -#define SYSCON_REDCY_SIG1_S 0 +#define SYSCON_REDCY_SIG1 0x7FFFFFFF +#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) +#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF +#define SYSCON_REDCY_SIG1_S 0 -#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098) +#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x09C) +/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_FREQ_MEM_FORCE_PD (BIT(7)) +#define SYSCON_FREQ_MEM_FORCE_PD_M (BIT(7)) +#define SYSCON_FREQ_MEM_FORCE_PD_V 0x1 +#define SYSCON_FREQ_MEM_FORCE_PD_S 7 +/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_FREQ_MEM_FORCE_PU (BIT(6)) +#define SYSCON_FREQ_MEM_FORCE_PU_M (BIT(6)) +#define SYSCON_FREQ_MEM_FORCE_PU_V 0x1 +#define SYSCON_FREQ_MEM_FORCE_PU_S 6 /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_DC_MEM_FORCE_PD (BIT(5)) -#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) -#define SYSCON_DC_MEM_FORCE_PD_V 0x1 -#define SYSCON_DC_MEM_FORCE_PD_S 5 +#define SYSCON_DC_MEM_FORCE_PD (BIT(5)) +#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) +#define SYSCON_DC_MEM_FORCE_PD_V 0x1 +#define SYSCON_DC_MEM_FORCE_PD_S 5 /* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_DC_MEM_FORCE_PU (BIT(4)) -#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) -#define SYSCON_DC_MEM_FORCE_PU_V 0x1 -#define SYSCON_DC_MEM_FORCE_PU_S 4 +#define SYSCON_DC_MEM_FORCE_PU (BIT(4)) +#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) +#define SYSCON_DC_MEM_FORCE_PU_V 0x1 +#define SYSCON_DC_MEM_FORCE_PU_S 4 /* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) -#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) -#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 -#define SYSCON_PBUS_MEM_FORCE_PD_S 3 +#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) +#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 +#define SYSCON_PBUS_MEM_FORCE_PD_S 3 /* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) -#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) -#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 -#define SYSCON_PBUS_MEM_FORCE_PU_S 2 +#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) +#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 +#define SYSCON_PBUS_MEM_FORCE_PU_S 2 /* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) -#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) -#define SYSCON_AGC_MEM_FORCE_PD_V 0x1 -#define SYSCON_AGC_MEM_FORCE_PD_S 1 +#define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) +#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) +#define SYSCON_AGC_MEM_FORCE_PD_V 0x1 +#define SYSCON_AGC_MEM_FORCE_PD_S 1 /* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ -#define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) -#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) -#define SYSCON_AGC_MEM_FORCE_PU_V 0x1 -#define SYSCON_AGC_MEM_FORCE_PU_S 0 +#define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) +#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) +#define SYSCON_AGC_MEM_FORCE_PU_V 0x1 +#define SYSCON_AGC_MEM_FORCE_PU_S 0 -#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) -/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h1907100 ; */ +#define SYSCON_SPI_MEM_ECC_CTRL_REG (DR_REG_SYSCON_BASE + 0x0A0) +/* SYSCON_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */ +/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. + 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ +#define SYSCON_SRAM_PAGE_SIZE 0x00000003 +#define SYSCON_SRAM_PAGE_SIZE_M ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S)) +#define SYSCON_SRAM_PAGE_SIZE_V 0x3 +#define SYSCON_SRAM_PAGE_SIZE_S 20 +/* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 + bytes. 2: 1024 bytes. 3: 2048 bytes.*/ +#define SYSCON_FLASH_PAGE_SIZE 0x00000003 +#define SYSCON_FLASH_PAGE_SIZE_M ((SYSCON_FLASH_PAGE_SIZE_V)<<(SYSCON_FLASH_PAGE_SIZE_S)) +#define SYSCON_FLASH_PAGE_SIZE_V 0x3 +#define SYSCON_FLASH_PAGE_SIZE_S 18 + +#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A8) +/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ /*description: */ -#define SYSCON_DATE 0xFFFFFFFF -#define SYSCON_DATE_M ((SYSCON_DATE_V) << (SYSCON_DATE_S)) -#define SYSCON_DATE_V 0xFFFFFFFF -#define SYSCON_DATE_S 0 +#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x000007FF +#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S)) +#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0x7FF +#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3 +/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007 +#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S)) +#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7 +#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 + +#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0x0AC) +/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */ +/*description: */ +#define SYSCON_SRAM_POWER_DOWN 0x000007FF +#define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S)) +#define SYSCON_SRAM_POWER_DOWN_V 0x7FF +#define SYSCON_SRAM_POWER_DOWN_S 3 +/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define SYSCON_ROM_POWER_DOWN 0x00000007 +#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S)) +#define SYSCON_ROM_POWER_DOWN_V 0x7 +#define SYSCON_ROM_POWER_DOWN_S 0 + +#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0x0B0) +/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ +/*description: */ +#define SYSCON_SRAM_POWER_UP 0x000007FF +#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S)) +#define SYSCON_SRAM_POWER_UP_V 0x7FF +#define SYSCON_SRAM_POWER_UP_S 3 +/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SYSCON_ROM_POWER_UP 0x00000007 +#define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S)) +#define SYSCON_ROM_POWER_UP_V 0x7 +#define SYSCON_ROM_POWER_UP_S 0 + +#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B4) +/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) +#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) +#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 +#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 +/* SYSCON_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: */ +#define SYSCON_RETENTION_CPU_LINK_ADDR 0x07FFFFFF +#define SYSCON_RETENTION_CPU_LINK_ADDR_M ((SYSCON_RETENTION_CPU_LINK_ADDR_V)<<(SYSCON_RETENTION_CPU_LINK_ADDR_S)) +#define SYSCON_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF +#define SYSCON_RETENTION_CPU_LINK_ADDR_S 0 + +#define SYSCON_RETENTION_CTRL1_REG (DR_REG_SYSCON_BASE + 0x0B8) +/* SYSCON_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: */ +#define SYSCON_RETENTION_TAG_LINK_ADDR 0x07FFFFFF +#define SYSCON_RETENTION_TAG_LINK_ADDR_M ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S)) +#define SYSCON_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF +#define SYSCON_RETENTION_TAG_LINK_ADDR_S 0 + +#define SYSCON_RETENTION_CTRL2_REG (DR_REG_SYSCON_BASE + 0x0BC) +/* SYSCON_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_RET_ICACHE_ENABLE (BIT(31)) +#define SYSCON_RET_ICACHE_ENABLE_M (BIT(31)) +#define SYSCON_RET_ICACHE_ENABLE_V 0x1 +#define SYSCON_RET_ICACHE_ENABLE_S 31 +/* SYSCON_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */ +/*description: */ +#define SYSCON_RET_ICACHE_START_POINT 0x000000FF +#define SYSCON_RET_ICACHE_START_POINT_M ((SYSCON_RET_ICACHE_START_POINT_V)<<(SYSCON_RET_ICACHE_START_POINT_S)) +#define SYSCON_RET_ICACHE_START_POINT_V 0xFF +#define SYSCON_RET_ICACHE_START_POINT_S 22 +/* SYSCON_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_RET_ICACHE_VLD_SIZE 0x000000FF +#define SYSCON_RET_ICACHE_VLD_SIZE_M ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S)) +#define SYSCON_RET_ICACHE_VLD_SIZE_V 0xFF +#define SYSCON_RET_ICACHE_VLD_SIZE_S 13 +/* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_RET_ICACHE_SIZE 0x000000FF +#define SYSCON_RET_ICACHE_SIZE_M ((SYSCON_RET_ICACHE_SIZE_V)<<(SYSCON_RET_ICACHE_SIZE_S)) +#define SYSCON_RET_ICACHE_SIZE_V 0xFF +#define SYSCON_RET_ICACHE_SIZE_S 4 + +#define SYSCON_RETENTION_CTRL3_REG (DR_REG_SYSCON_BASE + 0x0C0) +/* SYSCON_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_RET_DCACHE_ENABLE (BIT(31)) +#define SYSCON_RET_DCACHE_ENABLE_M (BIT(31)) +#define SYSCON_RET_DCACHE_ENABLE_V 0x1 +#define SYSCON_RET_DCACHE_ENABLE_S 31 +/* SYSCON_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */ +/*description: */ +#define SYSCON_RET_DCACHE_START_POINT 0x000001FF +#define SYSCON_RET_DCACHE_START_POINT_M ((SYSCON_RET_DCACHE_START_POINT_V)<<(SYSCON_RET_DCACHE_START_POINT_S)) +#define SYSCON_RET_DCACHE_START_POINT_V 0x1FF +#define SYSCON_RET_DCACHE_START_POINT_S 22 +/* SYSCON_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */ +/*description: */ +#define SYSCON_RET_DCACHE_VLD_SIZE 0x000001FF +#define SYSCON_RET_DCACHE_VLD_SIZE_M ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S)) +#define SYSCON_RET_DCACHE_VLD_SIZE_V 0x1FF +#define SYSCON_RET_DCACHE_VLD_SIZE_S 13 +/* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */ +/*description: */ +#define SYSCON_RET_DCACHE_SIZE 0x000001FF +#define SYSCON_RET_DCACHE_SIZE_M ((SYSCON_RET_DCACHE_SIZE_V)<<(SYSCON_RET_DCACHE_SIZE_S)) +#define SYSCON_RET_DCACHE_SIZE_V 0x1FF +#define SYSCON_RET_DCACHE_SIZE_S 4 + +#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) +/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h21010400 ; */ +/*description: Version control*/ +#define SYSCON_DATE 0xFFFFFFFF +#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) +#define SYSCON_DATE_V 0xFFFFFFFF +#define SYSCON_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SYSCON_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/syscon_struct.h b/components/soc/esp32s3/include/soc/syscon_struct.h index 31ab5575d1..04ae4c2488 100644 --- a/components/soc/esp32s3/include/soc/syscon_struct.h +++ b/components/soc/esp32s3/include/soc/syscon_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,33 +11,29 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_SYSCON_STRUCT_H_ +#define _SOC_SYSCON_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif -#include - typedef volatile struct { union { struct { - uint32_t pre_div: 10; - uint32_t clk_320m_en: 1; - uint32_t clk_en: 1; - uint32_t rst_tick: 1; - uint32_t reserved13: 1; - uint32_t soc_clk_sel: 2; - uint32_t reserved16: 16; + uint32_t apb_ctrl_pre_div_cnt: 10; + uint32_t apb_ctrl_clk_320m_en: 1; + uint32_t clk_en: 1; + uint32_t apb_ctrl_rst_tick_cnt: 1; + uint32_t reserved13: 19; }; uint32_t val; } apb_ctrl_sysclk_conf; union { struct { - uint32_t xtal_tick: 8; - uint32_t ck8m_tick: 8; - uint32_t tick_enable: 1; - uint32_t reserved17: 15; + uint32_t apb_ctrl_xtal_tick_num: 8; + uint32_t apb_ctrl_ck8m_tick_num: 8; + uint32_t apb_ctrl_tick_enable: 1; + uint32_t reserved17: 15; }; uint32_t val; } apb_ctrl_tick_conf; @@ -58,6 +54,10 @@ typedef volatile struct { }; uint32_t val; } apb_ctrl_clk_out_en; + uint32_t wifi_bb_cfg; /**/ + uint32_t wifi_bb_cfg_2; /**/ + uint32_t wifi_clk_en; /**/ + uint32_t wifi_rst_en; /**/ union { struct { uint32_t peri_io_swap: 8; @@ -74,120 +74,127 @@ typedef volatile struct { } ext_mem_pms_lock; union { struct { - uint32_t flash_ace0_attr: 3; - uint32_t reserved3: 29; + uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } ext_mem_writeback_bypass; + union { + struct { + uint32_t flash_ace0_attr: 9; + uint32_t reserved9: 23; }; uint32_t val; } flash_ace0_attr; union { struct { - uint32_t flash_ace1_attr: 3; - uint32_t reserved3: 29; + uint32_t flash_ace1_attr: 9; + uint32_t reserved9: 23; }; uint32_t val; } flash_ace1_attr; union { struct { - uint32_t flash_ace2_attr: 3; - uint32_t reserved3: 29; + uint32_t flash_ace2_attr: 9; + uint32_t reserved9: 23; }; uint32_t val; } flash_ace2_attr; union { struct { - uint32_t flash_ace3_attr: 3; - uint32_t reserved3: 29; + uint32_t flash_ace3_attr: 9; + uint32_t reserved9: 23; }; uint32_t val; } flash_ace3_attr; - uint32_t flash_ace0_addr; /**/ - uint32_t flash_ace1_addr; /**/ - uint32_t flash_ace2_addr; /**/ - uint32_t flash_ace3_addr; /**/ + uint32_t flash_ace0_addr; /**/ + uint32_t flash_ace1_addr; /**/ + uint32_t flash_ace2_addr; /**/ + uint32_t flash_ace3_addr; /**/ union { struct { - uint32_t flash_ace0_size: 16; + uint32_t flash_ace0_size:16; uint32_t reserved16: 16; }; uint32_t val; } flash_ace0_size; union { struct { - uint32_t flash_ace1_size: 16; + uint32_t flash_ace1_size:16; uint32_t reserved16: 16; }; uint32_t val; } flash_ace1_size; union { struct { - uint32_t flash_ace2_size: 16; + uint32_t flash_ace2_size:16; uint32_t reserved16: 16; }; uint32_t val; } flash_ace2_size; union { struct { - uint32_t flash_ace3_size: 16; + uint32_t flash_ace3_size:16; uint32_t reserved16: 16; }; uint32_t val; } flash_ace3_size; union { struct { - uint32_t sram_ace0_attr: 3; - uint32_t reserved3: 29; + uint32_t sram_ace0_attr: 9; + uint32_t reserved9: 23; }; uint32_t val; } sram_ace0_attr; union { struct { - uint32_t sram_ace1_attr: 3; - uint32_t reserved3: 29; + uint32_t sram_ace1_attr: 9; + uint32_t reserved9: 23; }; uint32_t val; } sram_ace1_attr; union { struct { - uint32_t sram_ace2_attr: 3; - uint32_t reserved3: 29; + uint32_t sram_ace2_attr: 9; + uint32_t reserved9: 23; }; uint32_t val; } sram_ace2_attr; union { struct { - uint32_t sram_ace3_attr: 3; - uint32_t reserved3: 29; + uint32_t sram_ace3_attr: 9; + uint32_t reserved9: 23; }; uint32_t val; } sram_ace3_attr; - uint32_t sram_ace0_addr; /**/ - uint32_t sram_ace1_addr; /**/ - uint32_t sram_ace2_addr; /**/ - uint32_t sram_ace3_addr; /**/ + uint32_t sram_ace0_addr; /**/ + uint32_t sram_ace1_addr; /**/ + uint32_t sram_ace2_addr; /**/ + uint32_t sram_ace3_addr; /**/ union { struct { - uint32_t sram_ace0_size: 16; + uint32_t sram_ace0_size:16; uint32_t reserved16: 16; }; uint32_t val; } sram_ace0_size; union { struct { - uint32_t sram_ace1_size: 16; + uint32_t sram_ace1_size:16; uint32_t reserved16: 16; }; uint32_t val; } sram_ace1_size; union { struct { - uint32_t sram_ace2_size: 16; + uint32_t sram_ace2_size:16; uint32_t reserved16: 16; }; uint32_t val; } sram_ace2_size; union { struct { - uint32_t sram_ace3_size: 16; + uint32_t sram_ace3_size:16; uint32_t reserved16: 16; }; uint32_t val; @@ -201,14 +208,14 @@ typedef volatile struct { }; uint32_t val; } spi_mem_pms_ctrl; - uint32_t spi_mem_reject_addr; /**/ + uint32_t spi_mem_reject_addr; /**/ union { struct { uint32_t sdio_win_access_en: 1; uint32_t reserved1: 31; }; uint32_t val; - } sdio_ctrl; + } apb_ctrl_sdio_ctrl; union { struct { uint32_t redcy_sig0: 31; @@ -223,10 +230,6 @@ typedef volatile struct { }; uint32_t val; } redcy_sig1; - uint32_t wifi_bb_cfg; /**/ - uint32_t wifi_bb_cfg_2; /**/ - uint32_t wifi_clk_en; /**/ - uint32_t wifi_rst_en; /**/ union { struct { uint32_t agc_mem_force_pu: 1; @@ -235,20 +238,84 @@ typedef volatile struct { uint32_t pbus_mem_force_pd: 1; uint32_t dc_mem_force_pu: 1; uint32_t dc_mem_force_pd: 1; - uint32_t reserved6: 26; + uint32_t freq_mem_force_pu: 1; + uint32_t freq_mem_force_pd: 1; + uint32_t reserved8: 24; }; uint32_t val; } front_end_mem_pd; - uint32_t reserved_9c; - uint32_t reserved_a0; + union { + struct { + uint32_t reserved0: 18; /*reserved*/ + uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reserved22: 10; /*reserved*/ + }; + uint32_t val; + } spi_mem_ecc_ctrl; uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; + union { + struct { + uint32_t rom_clkgate_force_on: 3; + uint32_t sram_clkgate_force_on:11; + uint32_t reserved14: 18; + }; + uint32_t val; + } clkgate_force_on; + union { + struct { + uint32_t rom_power_down: 3; + uint32_t sram_power_down:11; + uint32_t reserved14: 18; + }; + uint32_t val; + } mem_power_down; + union { + struct { + uint32_t rom_power_up: 3; + uint32_t sram_power_up:11; + uint32_t reserved14: 18; + }; + uint32_t val; + } mem_power_up; + union { + struct { + uint32_t retention_cpu_link_addr:27; + uint32_t nobypass_cpu_iso_rst: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } retention_ctrl; + union { + struct { + uint32_t retention_tag_link_addr:27; + uint32_t reserved27: 5; + }; + uint32_t val; + } retention_ctrl1; + union { + struct { + uint32_t reserved0: 4; + uint32_t ret_icache_size: 8; + uint32_t reserved12: 1; + uint32_t ret_icache_vld_size: 8; + uint32_t reserved21: 1; + uint32_t ret_icache_start_point: 8; + uint32_t reserved30: 1; + uint32_t ret_icache_enable: 1; + }; + uint32_t val; + } retention_ctrl2; + union { + struct { + uint32_t reserved0: 4; + uint32_t ret_dcache_size: 9; + uint32_t ret_dcache_vld_size: 9; + uint32_t ret_dcache_start_point: 9; + uint32_t ret_dcache_enable: 1; + }; + uint32_t val; + } retention_ctrl3; uint32_t reserved_c4; uint32_t reserved_c8; uint32_t reserved_cc; @@ -455,11 +522,11 @@ typedef volatile struct { uint32_t reserved_3f0; uint32_t reserved_3f4; uint32_t reserved_3f8; - uint32_t date; /**/ + uint32_t apb_ctrl_date; /*Version control*/ } syscon_dev_t; - extern syscon_dev_t SYSCON; - #ifdef __cplusplus } #endif + +#endif /* _SOC_SYSCON_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/system_reg.h b/components/soc/esp32s3/include/soc/system_reg.h index 443fb87371..e1bc980152 100644 --- a/components/soc/esp32s3/include/soc/system_reg.h +++ b/components/soc/esp32s3/include/soc/system_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,1052 +11,1145 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SYSTEM_REG_H_ +#define _SOC_SYSTEM_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define SYSTEM_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x000) -/* SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON : R/W ;bitpos:[2] ;default: ~1'b0 ; */ -/*description: */ -#define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON (BIT(2)) -#define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON_M (BIT(2)) -#define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON_V 0x1 -#define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON_S 2 -/* SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON 0x00000003 -#define SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_M ((SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_V) << (SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_S)) -#define SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_V 0x3 -#define SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_S 0 - -#define SYSTEM_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004) -/* SYSTEM_ROM_IRAM0_DRAM0_POWER_UP : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP (BIT(5)) -#define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP_M (BIT(5)) -#define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP_V 0x1 -#define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP_S 5 -/* SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN (BIT(4)) -#define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN_M (BIT(4)) -#define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN_V 0x1 -#define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN_S 4 -/* SYSTEM_ROM_IRAM0_POWER_UP : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ -/*description: */ -#define SYSTEM_ROM_IRAM0_POWER_UP 0x00000003 -#define SYSTEM_ROM_IRAM0_POWER_UP_M ((SYSTEM_ROM_IRAM0_POWER_UP_V) << (SYSTEM_ROM_IRAM0_POWER_UP_S)) -#define SYSTEM_ROM_IRAM0_POWER_UP_V 0x3 -#define SYSTEM_ROM_IRAM0_POWER_UP_S 2 -/* SYSTEM_ROM_IRAM0_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SYSTEM_ROM_IRAM0_POWER_DOWN 0x00000003 -#define SYSTEM_ROM_IRAM0_POWER_DOWN_M ((SYSTEM_ROM_IRAM0_POWER_DOWN_V) << (SYSTEM_ROM_IRAM0_POWER_DOWN_S)) -#define SYSTEM_ROM_IRAM0_POWER_DOWN_V 0x3 -#define SYSTEM_ROM_IRAM0_POWER_DOWN_S 0 - -#define SYSTEM_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008) -/* SYSTEM_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SYSTEM_SRAM_CLKGATE_FORCE_ON 0x000007FF -#define SYSTEM_SRAM_CLKGATE_FORCE_ON_M ((SYSTEM_SRAM_CLKGATE_FORCE_ON_V) << (SYSTEM_SRAM_CLKGATE_FORCE_ON_S)) -#define SYSTEM_SRAM_CLKGATE_FORCE_ON_V 0x7FF -#define SYSTEM_SRAM_CLKGATE_FORCE_ON_S 0 - -#define SYSTEM_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C) -/* SYSTEM_SRAM_POWER_DOWN : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ -/*description: */ -#define SYSTEM_SRAM_POWER_DOWN 0x000007FF -#define SYSTEM_SRAM_POWER_DOWN_M ((SYSTEM_SRAM_POWER_DOWN_V) << (SYSTEM_SRAM_POWER_DOWN_S)) -#define SYSTEM_SRAM_POWER_DOWN_V 0x7FF -#define SYSTEM_SRAM_POWER_DOWN_S 0 - -#define SYSTEM_SRAM_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x010) -/* SYSTEM_SRAM_POWER_UP : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SYSTEM_SRAM_POWER_UP 0x000007FF -#define SYSTEM_SRAM_POWER_UP_M ((SYSTEM_SRAM_POWER_UP_V) << (SYSTEM_SRAM_POWER_UP_S)) -#define SYSTEM_SRAM_POWER_UP_V 0x7FF -#define SYSTEM_SRAM_POWER_UP_S 0 - -#define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x014) +#define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x0) /* SYSTEM_CONTROL_CORE_1_RESETING : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CONTROL_CORE_1_RESETING (BIT(2)) -#define SYSTEM_CONTROL_CORE_1_RESETING_M (BIT(2)) -#define SYSTEM_CONTROL_CORE_1_RESETING_V 0x1 -#define SYSTEM_CONTROL_CORE_1_RESETING_S 2 +/*description: .*/ +#define SYSTEM_CONTROL_CORE_1_RESETING (BIT(2)) +#define SYSTEM_CONTROL_CORE_1_RESETING_M (BIT(2)) +#define SYSTEM_CONTROL_CORE_1_RESETING_V 0x1 +#define SYSTEM_CONTROL_CORE_1_RESETING_S 2 /* SYSTEM_CONTROL_CORE_1_CLKGATE_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1)) -#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (BIT(1)) -#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V 0x1 -#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S 1 +/*description: .*/ +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1)) +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (BIT(1)) +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V 0x1 +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S 1 /* SYSTEM_CONTROL_CORE_1_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CONTROL_CORE_1_RUNSTALL (BIT(0)) -#define SYSTEM_CONTROL_CORE_1_RUNSTALL_M (BIT(0)) -#define SYSTEM_CONTROL_CORE_1_RUNSTALL_V 0x1 -#define SYSTEM_CONTROL_CORE_1_RUNSTALL_S 0 +/*description: .*/ +#define SYSTEM_CONTROL_CORE_1_RUNSTALL (BIT(0)) +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_M (BIT(0)) +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_V 0x1 +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_S 0 -#define SYSTEM_CORE_1_CONTROL_1_REG (DR_REG_SYSTEM_BASE + 0x018) +#define SYSTEM_CORE_1_CONTROL_1_REG (DR_REG_SYSTEM_BASE + 0x4) /* SYSTEM_CONTROL_CORE_1_MESSAGE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CONTROL_CORE_1_MESSAGE 0xFFFFFFFF -#define SYSTEM_CONTROL_CORE_1_MESSAGE_M ((SYSTEM_CONTROL_CORE_1_MESSAGE_V) << (SYSTEM_CONTROL_CORE_1_MESSAGE_S)) -#define SYSTEM_CONTROL_CORE_1_MESSAGE_V 0xFFFFFFFF -#define SYSTEM_CONTROL_CORE_1_MESSAGE_S 0 +/*description: .*/ +#define SYSTEM_CONTROL_CORE_1_MESSAGE 0xFFFFFFFF +#define SYSTEM_CONTROL_CORE_1_MESSAGE_M ((SYSTEM_CONTROL_CORE_1_MESSAGE_V)<<(SYSTEM_CONTROL_CORE_1_MESSAGE_S)) +#define SYSTEM_CONTROL_CORE_1_MESSAGE_V 0xFFFFFFFF +#define SYSTEM_CONTROL_CORE_1_MESSAGE_S 0 -#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x01C) +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x8) /* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 -#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 +/*description: .*/ +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 /* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 -#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 +/*description: .*/ +#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 -#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x020) +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0xC) /* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) -#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 -#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 +/*description: .*/ +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 /* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) -#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 -#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 +/*description: .*/ +#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 -#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x024) +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x10) /* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: */ -#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F -#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V) << (SYSTEM_CPU_WAITI_DELAY_NUM_S)) -#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF -#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 +/*description: .*/ +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S)) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 /* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 +/*description: .*/ +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 /* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_PLL_FREQ_SEL (BIT(2)) -#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) -#define SYSTEM_PLL_FREQ_SEL_V 0x1 -#define SYSTEM_PLL_FREQ_SEL_S 2 +/*description: .*/ +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_V 0x1 +#define SYSTEM_PLL_FREQ_SEL_S 2 /* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SYSTEM_CPUPERIOD_SEL 0x00000003 -#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V) << (SYSTEM_CPUPERIOD_SEL_S)) -#define SYSTEM_CPUPERIOD_SEL_V 0x3 -#define SYSTEM_CPUPERIOD_SEL_S 0 +/*description: .*/ +#define SYSTEM_CPUPERIOD_SEL 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) +#define SYSTEM_CPUPERIOD_SEL_V 0x3 +#define SYSTEM_CPUPERIOD_SEL_S 0 -#define SYSTEM_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x028) +#define SYSTEM_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x14) /* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 +/*description: .*/ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 -#define SYSTEM_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x02C) +#define SYSTEM_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x18) /* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 +/*description: .*/ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 -#define SYSTEM_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x030) +#define SYSTEM_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x1C) /* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 +/*description: .*/ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 -#define SYSTEM_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x034) +#define SYSTEM_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x20) /* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 +/*description: .*/ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 -#define SYSTEM_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x038) +#define SYSTEM_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x24) /* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 +/*description: .*/ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 -#define SYSTEM_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x03C) +#define SYSTEM_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x28) /* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 +/*description: .*/ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 -#define SYSTEM_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x040) +#define SYSTEM_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x2C) /* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 +/*description: .*/ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 -#define SYSTEM_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x044) +#define SYSTEM_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x30) /* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 +/*description: .*/ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 -#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x048) +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x34) /* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) -#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) -#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 -#define SYSTEM_LSLP_MEM_PD_MASK_S 0 +/*description: .*/ +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 -#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x04C) +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x38) /* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ -/*description: */ -#define SYSTEM_SPI4_CLK_EN (BIT(31)) -#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) -#define SYSTEM_SPI4_CLK_EN_V 0x1 -#define SYSTEM_SPI4_CLK_EN_S 31 +/*description: .*/ +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_V 0x1 +#define SYSTEM_SPI4_CLK_EN_S 31 /* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 -#define SYSTEM_ADC2_ARB_CLK_EN_S 30 +/*description: .*/ +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 /* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 -#define SYSTEM_SYSTIMER_CLK_EN_S 29 +/*description: .*/ +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 /* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 -#define SYSTEM_APB_SARADC_CLK_EN_S 28 +/*description: .*/ +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 /* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) -#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) -#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 -#define SYSTEM_SPI3_DMA_CLK_EN_S 27 +/*description: .*/ +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 /* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM3_CLK_EN (BIT(26)) -#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) -#define SYSTEM_PWM3_CLK_EN_V 0x1 -#define SYSTEM_PWM3_CLK_EN_S 26 +/*description: .*/ +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_V 0x1 +#define SYSTEM_PWM3_CLK_EN_S 26 /* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM2_CLK_EN (BIT(25)) -#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) -#define SYSTEM_PWM2_CLK_EN_V 0x1 -#define SYSTEM_PWM2_CLK_EN_S 25 +/*description: .*/ +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_V 0x1 +#define SYSTEM_PWM2_CLK_EN_S 25 /* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_V 0x1 -#define SYSTEM_UART_MEM_CLK_EN_S 24 +/*description: .*/ +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_V 0x1 +#define SYSTEM_UART_MEM_CLK_EN_S 24 /* SYSTEM_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_USB_CLK_EN (BIT(23)) -#define SYSTEM_USB_CLK_EN_M (BIT(23)) -#define SYSTEM_USB_CLK_EN_V 0x1 -#define SYSTEM_USB_CLK_EN_S 23 +/*description: .*/ +#define SYSTEM_USB_CLK_EN (BIT(23)) +#define SYSTEM_USB_CLK_EN_M (BIT(23)) +#define SYSTEM_USB_CLK_EN_V 0x1 +#define SYSTEM_USB_CLK_EN_S 23 /* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) -#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) -#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 -#define SYSTEM_SPI2_DMA_CLK_EN_S 22 +/*description: .*/ +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 /* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S1_CLK_EN (BIT(21)) -#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) -#define SYSTEM_I2S1_CLK_EN_V 0x1 -#define SYSTEM_I2S1_CLK_EN_S 21 +/*description: .*/ +#define SYSTEM_I2S1_CLK_EN (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_V 0x1 +#define SYSTEM_I2S1_CLK_EN_S 21 /* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM1_CLK_EN (BIT(20)) -#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) -#define SYSTEM_PWM1_CLK_EN_V 0x1 -#define SYSTEM_PWM1_CLK_EN_S 20 +/*description: .*/ +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_V 0x1 +#define SYSTEM_PWM1_CLK_EN_S 20 /* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TWAI_CLK_EN (BIT(19)) -#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) -#define SYSTEM_TWAI_CLK_EN_V 0x1 -#define SYSTEM_TWAI_CLK_EN_S 19 +/*description: .*/ +#define SYSTEM_TWAI_CLK_EN (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_V 0x1 +#define SYSTEM_TWAI_CLK_EN_S 19 /* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) -#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) -#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 -#define SYSTEM_I2C_EXT1_CLK_EN_S 18 +/*description: .*/ +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 /* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM0_CLK_EN (BIT(17)) -#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) -#define SYSTEM_PWM0_CLK_EN_V 0x1 -#define SYSTEM_PWM0_CLK_EN_S 17 +/*description: .*/ +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_V 0x1 +#define SYSTEM_PWM0_CLK_EN_S 17 /* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI3_CLK_EN (BIT(16)) -#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) -#define SYSTEM_SPI3_CLK_EN_V 0x1 -#define SYSTEM_SPI3_CLK_EN_S 16 +/*description: .*/ +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_V 0x1 +#define SYSTEM_SPI3_CLK_EN_S 16 /* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) -#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) -#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 -#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 +/*description: .*/ +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 /* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_EFUSE_CLK_EN (BIT(14)) -#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) -#define SYSTEM_EFUSE_CLK_EN_V 0x1 -#define SYSTEM_EFUSE_CLK_EN_S 14 +/*description: .*/ +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_V 0x1 +#define SYSTEM_EFUSE_CLK_EN_S 14 /* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 -#define SYSTEM_TIMERGROUP_CLK_EN_S 13 +/*description: .*/ +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 /* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI1_CLK_EN (BIT(12)) -#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) -#define SYSTEM_UHCI1_CLK_EN_V 0x1 -#define SYSTEM_UHCI1_CLK_EN_S 12 +/*description: .*/ +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_V 0x1 +#define SYSTEM_UHCI1_CLK_EN_S 12 /* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LEDC_CLK_EN (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_V 0x1 -#define SYSTEM_LEDC_CLK_EN_S 11 +/*description: .*/ +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_V 0x1 +#define SYSTEM_LEDC_CLK_EN_S 11 /* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PCNT_CLK_EN (BIT(10)) -#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) -#define SYSTEM_PCNT_CLK_EN_V 0x1 -#define SYSTEM_PCNT_CLK_EN_S 10 +/*description: .*/ +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_V 0x1 +#define SYSTEM_PCNT_CLK_EN_S 10 /* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RMT_CLK_EN (BIT(9)) -#define SYSTEM_RMT_CLK_EN_M (BIT(9)) -#define SYSTEM_RMT_CLK_EN_V 0x1 -#define SYSTEM_RMT_CLK_EN_S 9 +/*description: .*/ +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (BIT(9)) +#define SYSTEM_RMT_CLK_EN_V 0x1 +#define SYSTEM_RMT_CLK_EN_S 9 /* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI0_CLK_EN (BIT(8)) -#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) -#define SYSTEM_UHCI0_CLK_EN_V 0x1 -#define SYSTEM_UHCI0_CLK_EN_S 8 +/*description: .*/ +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_V 0x1 +#define SYSTEM_UHCI0_CLK_EN_S 8 /* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 -#define SYSTEM_I2C_EXT0_CLK_EN_S 7 +/*description: .*/ +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 /* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI2_CLK_EN (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_V 0x1 -#define SYSTEM_SPI2_CLK_EN_S 6 +/*description: .*/ +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_V 0x1 +#define SYSTEM_SPI2_CLK_EN_S 6 /* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART1_CLK_EN (BIT(5)) -#define SYSTEM_UART1_CLK_EN_M (BIT(5)) -#define SYSTEM_UART1_CLK_EN_V 0x1 -#define SYSTEM_UART1_CLK_EN_S 5 +/*description: .*/ +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (BIT(5)) +#define SYSTEM_UART1_CLK_EN_V 0x1 +#define SYSTEM_UART1_CLK_EN_S 5 /* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S0_CLK_EN (BIT(4)) -#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) -#define SYSTEM_I2S0_CLK_EN_V 0x1 -#define SYSTEM_I2S0_CLK_EN_S 4 +/*description: .*/ +#define SYSTEM_I2S0_CLK_EN (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_V 0x1 +#define SYSTEM_I2S0_CLK_EN_S 4 /* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_WDG_CLK_EN (BIT(3)) -#define SYSTEM_WDG_CLK_EN_M (BIT(3)) -#define SYSTEM_WDG_CLK_EN_V 0x1 -#define SYSTEM_WDG_CLK_EN_S 3 +/*description: .*/ +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (BIT(3)) +#define SYSTEM_WDG_CLK_EN_V 0x1 +#define SYSTEM_WDG_CLK_EN_S 3 /* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART_CLK_EN (BIT(2)) -#define SYSTEM_UART_CLK_EN_M (BIT(2)) -#define SYSTEM_UART_CLK_EN_V 0x1 -#define SYSTEM_UART_CLK_EN_S 2 +/*description: .*/ +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (BIT(2)) +#define SYSTEM_UART_CLK_EN_V 0x1 +#define SYSTEM_UART_CLK_EN_S 2 /* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI01_CLK_EN (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_V 0x1 -#define SYSTEM_SPI01_CLK_EN_S 1 +/*description: .*/ +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_V 0x1 +#define SYSTEM_SPI01_CLK_EN_S 1 /* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERS_CLK_EN (BIT(0)) -#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) -#define SYSTEM_TIMERS_CLK_EN_V 0x1 -#define SYSTEM_TIMERS_CLK_EN_S 0 +/*description: .*/ +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_V 0x1 +#define SYSTEM_TIMERS_CLK_EN_S 0 -#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x050) +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x3C) +/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: .*/ +#define SYSTEM_USB_DEVICE_CLK_EN (BIT(10)) +#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(10)) +#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 +#define SYSTEM_USB_DEVICE_CLK_EN_S 10 /* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART2_CLK_EN (BIT(9)) -#define SYSTEM_UART2_CLK_EN_M (BIT(9)) -#define SYSTEM_UART2_CLK_EN_V 0x1 -#define SYSTEM_UART2_CLK_EN_S 9 +/*description: .*/ +#define SYSTEM_UART2_CLK_EN (BIT(9)) +#define SYSTEM_UART2_CLK_EN_M (BIT(9)) +#define SYSTEM_UART2_CLK_EN_V 0x1 +#define SYSTEM_UART2_CLK_EN_S 9 /* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) -#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) -#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 -#define SYSTEM_LCD_CAM_CLK_EN_S 8 +/*description: .*/ +#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 +#define SYSTEM_LCD_CAM_CLK_EN_S 8 /* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) -#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) -#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 -#define SYSTEM_SDIO_HOST_CLK_EN_S 7 +/*description: .*/ +#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 +#define SYSTEM_SDIO_HOST_CLK_EN_S 7 /* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_DMA_CLK_EN (BIT(6)) -#define SYSTEM_DMA_CLK_EN_M (BIT(6)) -#define SYSTEM_DMA_CLK_EN_V 0x1 -#define SYSTEM_DMA_CLK_EN_S 6 +/*description: .*/ +#define SYSTEM_DMA_CLK_EN (BIT(6)) +#define SYSTEM_DMA_CLK_EN_M (BIT(6)) +#define SYSTEM_DMA_CLK_EN_V 0x1 +#define SYSTEM_DMA_CLK_EN_S 6 /* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 +/*description: .*/ +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 /* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) -#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) -#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 +/*description: .*/ +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 /* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) -#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) -#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 +/*description: .*/ +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 /* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 +/*description: .*/ +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 /* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) -#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) -#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 +/*description: .*/ +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 +/* SYSTEM_PERI_BACKUP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PERI_BACKUP_CLK_EN (BIT(0)) +#define SYSTEM_PERI_BACKUP_CLK_EN_M (BIT(0)) +#define SYSTEM_PERI_BACKUP_CLK_EN_V 0x1 +#define SYSTEM_PERI_BACKUP_CLK_EN_S 0 -#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x054) +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x40) /* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define SYSTEM_SPI4_RST (BIT(31)) -#define SYSTEM_SPI4_RST_M (BIT(31)) -#define SYSTEM_SPI4_RST_V 0x1 -#define SYSTEM_SPI4_RST_S 31 +/*description: .*/ +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (BIT(31)) +#define SYSTEM_SPI4_RST_V 0x1 +#define SYSTEM_SPI4_RST_S 31 /* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ADC2_ARB_RST (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_V 0x1 -#define SYSTEM_ADC2_ARB_RST_S 30 +/*description: .*/ +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_V 0x1 +#define SYSTEM_ADC2_ARB_RST_S 30 /* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SYSTIMER_RST (BIT(29)) -#define SYSTEM_SYSTIMER_RST_M (BIT(29)) -#define SYSTEM_SYSTIMER_RST_V 0x1 -#define SYSTEM_SYSTIMER_RST_S 29 +/*description: .*/ +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (BIT(29)) +#define SYSTEM_SYSTIMER_RST_V 0x1 +#define SYSTEM_SYSTIMER_RST_S 29 /* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_APB_SARADC_RST (BIT(28)) -#define SYSTEM_APB_SARADC_RST_M (BIT(28)) -#define SYSTEM_APB_SARADC_RST_V 0x1 -#define SYSTEM_APB_SARADC_RST_S 28 +/*description: .*/ +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (BIT(28)) +#define SYSTEM_APB_SARADC_RST_V 0x1 +#define SYSTEM_APB_SARADC_RST_S 28 /* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI3_DMA_RST (BIT(27)) -#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) -#define SYSTEM_SPI3_DMA_RST_V 0x1 -#define SYSTEM_SPI3_DMA_RST_S 27 +/*description: .*/ +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_V 0x1 +#define SYSTEM_SPI3_DMA_RST_S 27 /* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM3_RST (BIT(26)) -#define SYSTEM_PWM3_RST_M (BIT(26)) -#define SYSTEM_PWM3_RST_V 0x1 -#define SYSTEM_PWM3_RST_S 26 +/*description: .*/ +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (BIT(26)) +#define SYSTEM_PWM3_RST_V 0x1 +#define SYSTEM_PWM3_RST_S 26 /* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM2_RST (BIT(25)) -#define SYSTEM_PWM2_RST_M (BIT(25)) -#define SYSTEM_PWM2_RST_V 0x1 -#define SYSTEM_PWM2_RST_S 25 +/*description: .*/ +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (BIT(25)) +#define SYSTEM_PWM2_RST_V 0x1 +#define SYSTEM_PWM2_RST_S 25 /* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART_MEM_RST (BIT(24)) -#define SYSTEM_UART_MEM_RST_M (BIT(24)) -#define SYSTEM_UART_MEM_RST_V 0x1 -#define SYSTEM_UART_MEM_RST_S 24 +/*description: .*/ +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (BIT(24)) +#define SYSTEM_UART_MEM_RST_V 0x1 +#define SYSTEM_UART_MEM_RST_S 24 /* SYSTEM_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_USB_RST (BIT(23)) -#define SYSTEM_USB_RST_M (BIT(23)) -#define SYSTEM_USB_RST_V 0x1 -#define SYSTEM_USB_RST_S 23 +/*description: .*/ +#define SYSTEM_USB_RST (BIT(23)) +#define SYSTEM_USB_RST_M (BIT(23)) +#define SYSTEM_USB_RST_V 0x1 +#define SYSTEM_USB_RST_S 23 /* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI2_DMA_RST (BIT(22)) -#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) -#define SYSTEM_SPI2_DMA_RST_V 0x1 -#define SYSTEM_SPI2_DMA_RST_S 22 +/*description: .*/ +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_V 0x1 +#define SYSTEM_SPI2_DMA_RST_S 22 /* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S1_RST (BIT(21)) -#define SYSTEM_I2S1_RST_M (BIT(21)) -#define SYSTEM_I2S1_RST_V 0x1 -#define SYSTEM_I2S1_RST_S 21 +/*description: .*/ +#define SYSTEM_I2S1_RST (BIT(21)) +#define SYSTEM_I2S1_RST_M (BIT(21)) +#define SYSTEM_I2S1_RST_V 0x1 +#define SYSTEM_I2S1_RST_S 21 /* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM1_RST (BIT(20)) -#define SYSTEM_PWM1_RST_M (BIT(20)) -#define SYSTEM_PWM1_RST_V 0x1 -#define SYSTEM_PWM1_RST_S 20 +/*description: .*/ +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (BIT(20)) +#define SYSTEM_PWM1_RST_V 0x1 +#define SYSTEM_PWM1_RST_S 20 /* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TWAI_RST (BIT(19)) -#define SYSTEM_TWAI_RST_M (BIT(19)) -#define SYSTEM_TWAI_RST_V 0x1 -#define SYSTEM_TWAI_RST_S 19 +/*description: .*/ +#define SYSTEM_TWAI_RST (BIT(19)) +#define SYSTEM_TWAI_RST_M (BIT(19)) +#define SYSTEM_TWAI_RST_V 0x1 +#define SYSTEM_TWAI_RST_S 19 /* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT1_RST (BIT(18)) -#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) -#define SYSTEM_I2C_EXT1_RST_V 0x1 -#define SYSTEM_I2C_EXT1_RST_S 18 +/*description: .*/ +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_V 0x1 +#define SYSTEM_I2C_EXT1_RST_S 18 /* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM0_RST (BIT(17)) -#define SYSTEM_PWM0_RST_M (BIT(17)) -#define SYSTEM_PWM0_RST_V 0x1 -#define SYSTEM_PWM0_RST_S 17 +/*description: .*/ +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (BIT(17)) +#define SYSTEM_PWM0_RST_V 0x1 +#define SYSTEM_PWM0_RST_S 17 /* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI3_RST (BIT(16)) -#define SYSTEM_SPI3_RST_M (BIT(16)) -#define SYSTEM_SPI3_RST_V 0x1 -#define SYSTEM_SPI3_RST_S 16 +/*description: .*/ +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (BIT(16)) +#define SYSTEM_SPI3_RST_V 0x1 +#define SYSTEM_SPI3_RST_S 16 /* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP1_RST (BIT(15)) -#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) -#define SYSTEM_TIMERGROUP1_RST_V 0x1 -#define SYSTEM_TIMERGROUP1_RST_S 15 +/*description: .*/ +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_V 0x1 +#define SYSTEM_TIMERGROUP1_RST_S 15 /* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_EFUSE_RST (BIT(14)) -#define SYSTEM_EFUSE_RST_M (BIT(14)) -#define SYSTEM_EFUSE_RST_V 0x1 -#define SYSTEM_EFUSE_RST_S 14 +/*description: .*/ +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (BIT(14)) +#define SYSTEM_EFUSE_RST_V 0x1 +#define SYSTEM_EFUSE_RST_S 14 /* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP_RST (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_V 0x1 -#define SYSTEM_TIMERGROUP_RST_S 13 +/*description: .*/ +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_V 0x1 +#define SYSTEM_TIMERGROUP_RST_S 13 /* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI1_RST (BIT(12)) -#define SYSTEM_UHCI1_RST_M (BIT(12)) -#define SYSTEM_UHCI1_RST_V 0x1 -#define SYSTEM_UHCI1_RST_S 12 +/*description: .*/ +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (BIT(12)) +#define SYSTEM_UHCI1_RST_V 0x1 +#define SYSTEM_UHCI1_RST_S 12 /* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LEDC_RST (BIT(11)) -#define SYSTEM_LEDC_RST_M (BIT(11)) -#define SYSTEM_LEDC_RST_V 0x1 -#define SYSTEM_LEDC_RST_S 11 +/*description: .*/ +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (BIT(11)) +#define SYSTEM_LEDC_RST_V 0x1 +#define SYSTEM_LEDC_RST_S 11 /* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PCNT_RST (BIT(10)) -#define SYSTEM_PCNT_RST_M (BIT(10)) -#define SYSTEM_PCNT_RST_V 0x1 -#define SYSTEM_PCNT_RST_S 10 +/*description: .*/ +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (BIT(10)) +#define SYSTEM_PCNT_RST_V 0x1 +#define SYSTEM_PCNT_RST_S 10 /* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RMT_RST (BIT(9)) -#define SYSTEM_RMT_RST_M (BIT(9)) -#define SYSTEM_RMT_RST_V 0x1 -#define SYSTEM_RMT_RST_S 9 +/*description: .*/ +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (BIT(9)) +#define SYSTEM_RMT_RST_V 0x1 +#define SYSTEM_RMT_RST_S 9 /* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI0_RST (BIT(8)) -#define SYSTEM_UHCI0_RST_M (BIT(8)) -#define SYSTEM_UHCI0_RST_V 0x1 -#define SYSTEM_UHCI0_RST_S 8 +/*description: .*/ +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (BIT(8)) +#define SYSTEM_UHCI0_RST_V 0x1 +#define SYSTEM_UHCI0_RST_S 8 /* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT0_RST (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_V 0x1 -#define SYSTEM_I2C_EXT0_RST_S 7 +/*description: .*/ +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_V 0x1 +#define SYSTEM_I2C_EXT0_RST_S 7 /* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI2_RST (BIT(6)) -#define SYSTEM_SPI2_RST_M (BIT(6)) -#define SYSTEM_SPI2_RST_V 0x1 -#define SYSTEM_SPI2_RST_S 6 +/*description: .*/ +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (BIT(6)) +#define SYSTEM_SPI2_RST_V 0x1 +#define SYSTEM_SPI2_RST_S 6 /* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART1_RST (BIT(5)) -#define SYSTEM_UART1_RST_M (BIT(5)) -#define SYSTEM_UART1_RST_V 0x1 -#define SYSTEM_UART1_RST_S 5 +/*description: .*/ +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (BIT(5)) +#define SYSTEM_UART1_RST_V 0x1 +#define SYSTEM_UART1_RST_S 5 /* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S0_RST (BIT(4)) -#define SYSTEM_I2S0_RST_M (BIT(4)) -#define SYSTEM_I2S0_RST_V 0x1 -#define SYSTEM_I2S0_RST_S 4 +/*description: .*/ +#define SYSTEM_I2S0_RST (BIT(4)) +#define SYSTEM_I2S0_RST_M (BIT(4)) +#define SYSTEM_I2S0_RST_V 0x1 +#define SYSTEM_I2S0_RST_S 4 /* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_WDG_RST (BIT(3)) -#define SYSTEM_WDG_RST_M (BIT(3)) -#define SYSTEM_WDG_RST_V 0x1 -#define SYSTEM_WDG_RST_S 3 +/*description: .*/ +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (BIT(3)) +#define SYSTEM_WDG_RST_V 0x1 +#define SYSTEM_WDG_RST_S 3 /* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART_RST (BIT(2)) -#define SYSTEM_UART_RST_M (BIT(2)) -#define SYSTEM_UART_RST_V 0x1 -#define SYSTEM_UART_RST_S 2 +/*description: .*/ +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (BIT(2)) +#define SYSTEM_UART_RST_V 0x1 +#define SYSTEM_UART_RST_S 2 /* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI01_RST (BIT(1)) -#define SYSTEM_SPI01_RST_M (BIT(1)) -#define SYSTEM_SPI01_RST_V 0x1 -#define SYSTEM_SPI01_RST_S 1 +/*description: .*/ +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (BIT(1)) +#define SYSTEM_SPI01_RST_V 0x1 +#define SYSTEM_SPI01_RST_S 1 /* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERS_RST (BIT(0)) -#define SYSTEM_TIMERS_RST_M (BIT(0)) -#define SYSTEM_TIMERS_RST_V 0x1 -#define SYSTEM_TIMERS_RST_S 0 +/*description: .*/ +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (BIT(0)) +#define SYSTEM_TIMERS_RST_V 0x1 +#define SYSTEM_TIMERS_RST_S 0 -#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x058) +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x44) +/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_USB_DEVICE_RST (BIT(10)) +#define SYSTEM_USB_DEVICE_RST_M (BIT(10)) +#define SYSTEM_USB_DEVICE_RST_V 0x1 +#define SYSTEM_USB_DEVICE_RST_S 10 /* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART2_RST (BIT(9)) -#define SYSTEM_UART2_RST_M (BIT(9)) -#define SYSTEM_UART2_RST_V 0x1 -#define SYSTEM_UART2_RST_S 9 +/*description: .*/ +#define SYSTEM_UART2_RST (BIT(9)) +#define SYSTEM_UART2_RST_M (BIT(9)) +#define SYSTEM_UART2_RST_V 0x1 +#define SYSTEM_UART2_RST_S 9 /* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_LCD_CAM_RST (BIT(8)) -#define SYSTEM_LCD_CAM_RST_M (BIT(8)) -#define SYSTEM_LCD_CAM_RST_V 0x1 -#define SYSTEM_LCD_CAM_RST_S 8 +/*description: .*/ +#define SYSTEM_LCD_CAM_RST (BIT(8)) +#define SYSTEM_LCD_CAM_RST_M (BIT(8)) +#define SYSTEM_LCD_CAM_RST_V 0x1 +#define SYSTEM_LCD_CAM_RST_S 8 /* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SDIO_HOST_RST (BIT(7)) -#define SYSTEM_SDIO_HOST_RST_M (BIT(7)) -#define SYSTEM_SDIO_HOST_RST_V 0x1 -#define SYSTEM_SDIO_HOST_RST_S 7 +/*description: .*/ +#define SYSTEM_SDIO_HOST_RST (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_M (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_V 0x1 +#define SYSTEM_SDIO_HOST_RST_S 7 /* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_DMA_RST (BIT(6)) -#define SYSTEM_DMA_RST_M (BIT(6)) -#define SYSTEM_DMA_RST_V 0x1 -#define SYSTEM_DMA_RST_S 6 +/*description: .*/ +#define SYSTEM_DMA_RST (BIT(6)) +#define SYSTEM_DMA_RST_M (BIT(6)) +#define SYSTEM_DMA_RST_V 0x1 +#define SYSTEM_DMA_RST_S 6 /* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 -#define SYSTEM_CRYPTO_HMAC_RST_S 5 +/*description: .*/ +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 /* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_DS_RST (BIT(4)) -#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) -#define SYSTEM_CRYPTO_DS_RST_V 0x1 -#define SYSTEM_CRYPTO_DS_RST_S 4 +/*description: .*/ +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_V 0x1 +#define SYSTEM_CRYPTO_DS_RST_S 4 /* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) -#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) -#define SYSTEM_CRYPTO_RSA_RST_V 0x1 -#define SYSTEM_CRYPTO_RSA_RST_S 3 +/*description: .*/ +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_V 0x1 +#define SYSTEM_CRYPTO_RSA_RST_S 3 /* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_V 0x1 -#define SYSTEM_CRYPTO_SHA_RST_S 2 +/*description: .*/ +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_V 0x1 +#define SYSTEM_CRYPTO_SHA_RST_S 2 /* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_AES_RST (BIT(1)) -#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) -#define SYSTEM_CRYPTO_AES_RST_V 0x1 -#define SYSTEM_CRYPTO_AES_RST_S 1 +/*description: .*/ +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_V 0x1 +#define SYSTEM_CRYPTO_AES_RST_S 1 +/* SYSTEM_PERI_BACKUP_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_PERI_BACKUP_RST (BIT(0)) +#define SYSTEM_PERI_BACKUP_RST_M (BIT(0)) +#define SYSTEM_PERI_BACKUP_RST_V 0x1 +#define SYSTEM_PERI_BACKUP_RST_S 0 -#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x05C) +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x48) /* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ -/*description: */ -#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V) << (SYSTEM_BT_LPCK_DIV_NUM_S)) -#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF -#define SYSTEM_BT_LPCK_DIV_NUM_S 0 +/*description: .*/ +#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S)) +#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_NUM_S 0 -#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x060) +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x4C) /* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LPCLK_RTC_EN (BIT(28)) -#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) -#define SYSTEM_LPCLK_RTC_EN_V 0x1 -#define SYSTEM_LPCLK_RTC_EN_S 28 +/*description: .*/ +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_V 0x1 +#define SYSTEM_LPCLK_RTC_EN_S 28 /* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) -#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) -#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 -#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 +/*description: .*/ +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 /* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) -#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) -#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 -#define SYSTEM_LPCLK_SEL_XTAL_S 26 +/*description: .*/ +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL_S 26 /* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_LPCLK_SEL_8M (BIT(25)) -#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) -#define SYSTEM_LPCLK_SEL_8M_V 0x1 -#define SYSTEM_LPCLK_SEL_8M_S 25 +/*description: .*/ +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_V 0x1 +#define SYSTEM_LPCLK_SEL_8M_S 25 /* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) -#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) -#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 -#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 +/*description: .*/ +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 /* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ -/*description: */ -#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V) << (SYSTEM_BT_LPCK_DIV_A_S)) -#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF -#define SYSTEM_BT_LPCK_DIV_A_S 12 +/*description: .*/ +#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S)) +#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_A_S 12 /* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ -/*description: */ -#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V) << (SYSTEM_BT_LPCK_DIV_B_S)) -#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF -#define SYSTEM_BT_LPCK_DIV_B_S 0 +/*description: .*/ +#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S)) +#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_B_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x064) +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x50) /* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 -#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 +/*description: .*/ +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x068) +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x54) /* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 -#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 +/*description: .*/ +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x06C) +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x58) /* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 -#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 +/*description: .*/ +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x070) +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x5C) /* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 -#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 +/*description: .*/ +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 -#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x074) +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x60) /* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) -#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) -#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 -#define SYSTEM_RSA_MEM_FORCE_PD_S 2 +/*description: .*/ +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 /* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) -#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) -#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 -#define SYSTEM_RSA_MEM_FORCE_PU_S 1 +/*description: .*/ +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 /* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_RSA_MEM_PD (BIT(0)) -#define SYSTEM_RSA_MEM_PD_M (BIT(0)) -#define SYSTEM_RSA_MEM_PD_V 0x1 -#define SYSTEM_RSA_MEM_PD_S 0 +/*description: .*/ +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (BIT(0)) +#define SYSTEM_RSA_MEM_PD_V 0x1 +#define SYSTEM_RSA_MEM_PD_S 0 -#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x078) +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x64) /* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_EDMA_RESET (BIT(1)) -#define SYSTEM_EDMA_RESET_M (BIT(1)) -#define SYSTEM_EDMA_RESET_V 0x1 -#define SYSTEM_EDMA_RESET_S 1 +/*description: .*/ +#define SYSTEM_EDMA_RESET (BIT(1)) +#define SYSTEM_EDMA_RESET_M (BIT(1)) +#define SYSTEM_EDMA_RESET_V 0x1 +#define SYSTEM_EDMA_RESET_S 1 /* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_EDMA_CLK_ON (BIT(0)) -#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) -#define SYSTEM_EDMA_CLK_ON_V 0x1 -#define SYSTEM_EDMA_CLK_ON_S 0 +/*description: .*/ +#define SYSTEM_EDMA_CLK_ON (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_V 0x1 +#define SYSTEM_EDMA_CLK_ON_S 0 -#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x07C) +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x68) /* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_DCACHE_RESET (BIT(3)) -#define SYSTEM_DCACHE_RESET_M (BIT(3)) -#define SYSTEM_DCACHE_RESET_V 0x1 -#define SYSTEM_DCACHE_RESET_S 3 +/*description: .*/ +#define SYSTEM_DCACHE_RESET (BIT(3)) +#define SYSTEM_DCACHE_RESET_M (BIT(3)) +#define SYSTEM_DCACHE_RESET_V 0x1 +#define SYSTEM_DCACHE_RESET_S 3 /* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_DCACHE_CLK_ON (BIT(2)) -#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) -#define SYSTEM_DCACHE_CLK_ON_V 0x1 -#define SYSTEM_DCACHE_CLK_ON_S 2 +/*description: .*/ +#define SYSTEM_DCACHE_CLK_ON (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_V 0x1 +#define SYSTEM_DCACHE_CLK_ON_S 2 /* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ICACHE_RESET (BIT(1)) -#define SYSTEM_ICACHE_RESET_M (BIT(1)) -#define SYSTEM_ICACHE_RESET_V 0x1 -#define SYSTEM_ICACHE_RESET_S 1 +/*description: .*/ +#define SYSTEM_ICACHE_RESET (BIT(1)) +#define SYSTEM_ICACHE_RESET_M (BIT(1)) +#define SYSTEM_ICACHE_RESET_V 0x1 +#define SYSTEM_ICACHE_RESET_S 1 /* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_ICACHE_CLK_ON (BIT(0)) -#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) -#define SYSTEM_ICACHE_CLK_ON_V 0x1 -#define SYSTEM_ICACHE_CLK_ON_S 0 +/*description: .*/ +#define SYSTEM_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_V 0x1 +#define SYSTEM_ICACHE_CLK_ON_S 0 -#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x080) +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x6C) /* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 +/*description: .*/ +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 /* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/*description: .*/ +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 /* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/*description: .*/ +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 /* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 +/*description: .*/ +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 -#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x084) +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x70) /* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) -#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) -#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 -#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 /* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF -#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V) << (SYSTEM_RTC_MEM_CRC_LEN_S)) -#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF -#define SYSTEM_RTC_MEM_CRC_LEN_S 20 +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S)) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 /* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF -#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V) << (SYSTEM_RTC_MEM_CRC_ADDR_S)) -#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF -#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S)) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 /* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) -#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) -#define SYSTEM_RTC_MEM_CRC_START_V 0x1 -#define SYSTEM_RTC_MEM_CRC_START_S 8 +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_V 0x1 +#define SYSTEM_RTC_MEM_CRC_START_S 8 -#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x088) +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x74) /* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF -#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V) << (SYSTEM_RTC_MEM_CRC_RES_S)) -#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF -#define SYSTEM_RTC_MEM_CRC_RES_S 0 +/*description: .*/ +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S)) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_S 0 -#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x08C) +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x78) /* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) -#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) -#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 -#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 +/*description: .*/ +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 /* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) -#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) -#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 -#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 +/*description: .*/ +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 -#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x090) +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x7C) /* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_EN (BIT(0)) -#define SYSTEM_CLK_EN_M (BIT(0)) -#define SYSTEM_CLK_EN_V 0x1 -#define SYSTEM_CLK_EN_S 0 +/*description: .*/ +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (BIT(0)) +#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_S 0 -#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x094) +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x80) /* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: */ -#define SYSTEM_CLK_DIV_EN (BIT(19)) -#define SYSTEM_CLK_DIV_EN_M (BIT(19)) -#define SYSTEM_CLK_DIV_EN_V 0x1 -#define SYSTEM_CLK_DIV_EN_S 19 +/*description: .*/ +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (BIT(19)) +#define SYSTEM_CLK_DIV_EN_V 0x1 +#define SYSTEM_CLK_DIV_EN_S 19 /* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ -/*description: */ -#define SYSTEM_CLK_XTAL_FREQ 0x0000007F -#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V) << (SYSTEM_CLK_XTAL_FREQ_S)) -#define SYSTEM_CLK_XTAL_FREQ_V 0x7F -#define SYSTEM_CLK_XTAL_FREQ_S 12 +/*description: .*/ +#define SYSTEM_CLK_XTAL_FREQ 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S)) +#define SYSTEM_CLK_XTAL_FREQ_V 0x7F +#define SYSTEM_CLK_XTAL_FREQ_S 12 /* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: */ -#define SYSTEM_SOC_CLK_SEL 0x00000003 -#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V) << (SYSTEM_SOC_CLK_SEL_S)) -#define SYSTEM_SOC_CLK_SEL_V 0x3 -#define SYSTEM_SOC_CLK_SEL_S 10 +/*description: .*/ +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) +#define SYSTEM_SOC_CLK_SEL_V 0x3 +#define SYSTEM_SOC_CLK_SEL_S 10 /* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ -/*description: */ -#define SYSTEM_PRE_DIV_CNT 0x000003FF -#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V) << (SYSTEM_PRE_DIV_CNT_S)) -#define SYSTEM_PRE_DIV_CNT_V 0x3FF -#define SYSTEM_PRE_DIV_CNT_S 0 +/*description: .*/ +#define SYSTEM_PRE_DIV_CNT 0x000003FF +#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S)) +#define SYSTEM_PRE_DIV_CNT_V 0x3FF +#define SYSTEM_PRE_DIV_CNT_S 0 -#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x098) +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x84) +/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: .*/ +#define SYSTEM_MEM_VT_SEL 0x00000003 +#define SYSTEM_MEM_VT_SEL_M ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S)) +#define SYSTEM_MEM_VT_SEL_V 0x3 +#define SYSTEM_MEM_VT_SEL_S 22 /* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF -#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V) << (SYSTEM_MEM_TIMING_ERR_CNT_S)) -#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF -#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 +/*description: .*/ +#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S)) +#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 /* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) -#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) -#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 -#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 +/*description: .*/ +#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 +#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 /* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) -#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) -#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 -#define SYSTEM_MEM_ERR_CNT_CLR_S 4 +/*description: .*/ +#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 +#define SYSTEM_MEM_ERR_CNT_CLR_S 4 /* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */ -/*description: */ -#define SYSTEM_MEM_PATH_LEN 0x0000000F -#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V) << (SYSTEM_MEM_PATH_LEN_S)) -#define SYSTEM_MEM_PATH_LEN_V 0xF -#define SYSTEM_MEM_PATH_LEN_S 0 +/*description: .*/ +#define SYSTEM_MEM_PATH_LEN 0x0000000F +#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S)) +#define SYSTEM_MEM_PATH_LEN_V 0xF +#define SYSTEM_MEM_PATH_LEN_S 0 -#define SYSTEM_COMB_PVT_REG (DR_REG_SYSTEM_BASE + 0x09C) -/* SYSTEM_COMB_TIMING_ERR_CNT : RO ;bitpos:[22:7] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_M ((SYSTEM_COMB_TIMING_ERR_CNT_V) << (SYSTEM_COMB_TIMING_ERR_CNT_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_S 7 -/* SYSTEM_COMB_PVT_MONITOR_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COMB_PVT_MONITOR_EN (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_M (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_V 0x1 -#define SYSTEM_COMB_PVT_MONITOR_EN_S 6 -/* SYSTEM_COMB_ERR_CNT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COMB_ERR_CNT_CLR (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_M (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_V 0x1 -#define SYSTEM_COMB_ERR_CNT_CLR_S 5 -/* SYSTEM_COMB_PATH_LEN : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ -/*description: */ -#define SYSTEM_COMB_PATH_LEN 0x0000001F -#define SYSTEM_COMB_PATH_LEN_M ((SYSTEM_COMB_PATH_LEN_V) << (SYSTEM_COMB_PATH_LEN_S)) -#define SYSTEM_COMB_PATH_LEN_V 0x1F -#define SYSTEM_COMB_PATH_LEN_S 0 +#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x88) +/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5 +/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: .*/ +#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S)) +#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_LVT_S 0 -#define SYSTEM_RETENTION_BUS_CTRL_REG (DR_REG_SYSTEM_BASE + 0x100) -/* SYSTEM_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ -/*description: */ -#define SYSTEM_RETENTION_LINK_ADDR 0x07FFFFFF -#define SYSTEM_RETENTION_LINK_ADDR_M ((SYSTEM_RETENTION_LINK_ADDR_V) << (SYSTEM_RETENTION_LINK_ADDR_S)) -#define SYSTEM_RETENTION_LINK_ADDR_V 0x7FFFFFF -#define SYSTEM_RETENTION_LINK_ADDR_S 0 +#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x8C) +/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5 +/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: .*/ +#define SYSTEM_COMB_PATH_LEN_NVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S)) +#define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_NVT_S 0 -#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) -/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2002281 ; */ -/*description: */ -#define SYSTEM_DATE 0x0FFFFFFF -#define SYSTEM_DATE_M ((SYSTEM_DATE_V) << (SYSTEM_DATE_S)) -#define SYSTEM_DATE_V 0xFFFFFFF -#define SYSTEM_DATE_S 0 +#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x90) +/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5 +/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: .*/ +#define SYSTEM_COMB_PATH_LEN_HVT 0x0000001F +#define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S)) +#define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F +#define SYSTEM_COMB_PATH_LEN_HVT_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x94) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x98) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x9C) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA0) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA4) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA8) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xAC) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xB0) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xB4) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 + +#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xB8) +/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xBC) +/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 + +#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xC0) +/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: .*/ +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 + +#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012230 ; */ +/*description: .*/ +#define SYSTEM_DATE 0x0FFFFFFF +#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) +#define SYSTEM_DATE_V 0xFFFFFFF +#define SYSTEM_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SYSTEM_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/system_struct.h b/components/soc/esp32s3/include/soc/system_struct.h index 77383353c1..a5d3dd4b4e 100644 --- a/components/soc/esp32s3/include/soc/system_struct.h +++ b/components/soc/esp32s3/include/soc/system_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,363 +11,423 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_SYSTEM_STRUCT_H_ +#define _SOC_SYSTEM_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { union { struct { - uint32_t rom_iram0_clkgate_force_on: 2; - uint32_t rom_iram0_dram0_clkgate_force_on: 1; - uint32_t reserved3: 29; - }; - uint32_t val; - } rom_ctrl_0; - union { - struct { - uint32_t rom_iram0_power_down: 2; - uint32_t rom_iram0_power_up: 2; - uint32_t rom_iram0_dram0_power_down: 1; - uint32_t rom_iram0_dram0_power_up: 1; - uint32_t reserved6: 26; - }; - uint32_t val; - } rom_ctrl_1; - union { - struct { - uint32_t sram_clkgate_force_on: 11; - uint32_t reserved11: 21; - }; - uint32_t val; - } sram_ctrl_0; - union { - struct { - uint32_t sram_power_down: 11; - uint32_t reserved11: 21; - }; - uint32_t val; - } sram_ctrl_1; - union { - struct { - uint32_t sram_power_up: 11; - uint32_t reserved11: 21; - }; - uint32_t val; - } sram_ctrl_2; - union { - struct { - uint32_t control_core_1_runstall: 1; - uint32_t control_core_1_clkgate_en: 1; - uint32_t control_core_1_reseting: 1; - uint32_t reserved3: 29; + uint32_t control_core_1_runstall : 1; + uint32_t control_core_1_clkgate_en : 1; + uint32_t control_core_1_reseting : 1; + uint32_t reserved3 : 29; }; uint32_t val; } core_1_control_0; - uint32_t core_1_control_1; /**/ + uint32_t core_1_control_1; union { struct { - uint32_t reserved0: 6; - uint32_t clk_en_assist_debug: 1; - uint32_t clk_en_dedicated_gpio: 1; - uint32_t reserved8: 24; + uint32_t reserved0 : 6; + uint32_t clk_en_assist_debug : 1; + uint32_t clk_en_dedicated_gpio : 1; + uint32_t reserved8 : 24; }; uint32_t val; } cpu_peri_clk_en; union { struct { - uint32_t reserved0: 6; - uint32_t rst_en_assist_debug: 1; - uint32_t rst_en_dedicated_gpio: 1; - uint32_t reserved8: 24; + uint32_t reserved0 : 6; + uint32_t rst_en_assist_debug : 1; + uint32_t rst_en_dedicated_gpio : 1; + uint32_t reserved8 : 24; }; uint32_t val; } cpu_peri_rst_en; union { struct { - uint32_t cpuperiod_sel: 2; - uint32_t pll_freq_sel: 1; - uint32_t cpu_wait_mode_force_on: 1; - uint32_t cpu_waiti_delay_num: 4; - uint32_t reserved8: 24; + uint32_t cpuperiod_sel : 2; + uint32_t pll_freq_sel : 1; + uint32_t cpu_wait_mode_force_on : 1; + uint32_t cpu_waiti_delay_num : 4; + uint32_t reserved8 : 24; }; uint32_t val; } cpu_per_conf; - uint32_t jtag_ctrl_0; /**/ - uint32_t jtag_ctrl_1; /**/ - uint32_t jtag_ctrl_2; /**/ - uint32_t jtag_ctrl_3; /**/ - uint32_t jtag_ctrl_4; /**/ - uint32_t jtag_ctrl_5; /**/ - uint32_t jtag_ctrl_6; /**/ - uint32_t jtag_ctrl_7; /**/ + uint32_t jtag_ctrl_0; + uint32_t jtag_ctrl_1; + uint32_t jtag_ctrl_2; + uint32_t jtag_ctrl_3; + uint32_t jtag_ctrl_4; + uint32_t jtag_ctrl_5; + uint32_t jtag_ctrl_6; + uint32_t jtag_ctrl_7; union { struct { - uint32_t lslp_mem_pd_mask: 1; - uint32_t reserved1: 31; + uint32_t lslp_mem_pd_mask : 1; + uint32_t reserved1 : 31; }; uint32_t val; } mem_pd_mask; union { struct { - uint32_t timers_clk_en: 1; - uint32_t spi01_clk_en: 1; - uint32_t uart_clk_en: 1; - uint32_t wdg_clk_en: 1; - uint32_t i2s0_clk_en: 1; - uint32_t uart1_clk_en: 1; - uint32_t spi2_clk_en: 1; - uint32_t i2c_ext0_clk_en: 1; - uint32_t uhci0_clk_en: 1; - uint32_t rmt_clk_en: 1; - uint32_t pcnt_clk_en: 1; - uint32_t ledc_clk_en: 1; - uint32_t uhci1_clk_en: 1; - uint32_t timergroup_clk_en: 1; - uint32_t efuse_clk_en: 1; - uint32_t timergroup1_clk_en: 1; - uint32_t spi3_clk_en: 1; - uint32_t pwm0_clk_en: 1; - uint32_t i2c_ext1_clk_en: 1; - uint32_t can_clk_en: 1; - uint32_t pwm1_clk_en: 1; - uint32_t i2s1_clk_en: 1; - uint32_t spi2_dma_clk_en: 1; - uint32_t usb_clk_en: 1; - uint32_t uart_mem_clk_en: 1; - uint32_t pwm2_clk_en: 1; - uint32_t pwm3_clk_en: 1; - uint32_t spi3_dma_clk_en: 1; - uint32_t apb_saradc_clk_en: 1; - uint32_t systimer_clk_en: 1; - uint32_t adc2_arb_clk_en: 1; - uint32_t spi4_clk_en: 1; + uint32_t timers_clk_en : 1; + uint32_t spi01_clk_en : 1; + uint32_t uart_clk_en : 1; + uint32_t wdg_clk_en : 1; + uint32_t i2s0_clk_en : 1; + uint32_t uart1_clk_en : 1; + uint32_t spi2_clk_en : 1; + uint32_t i2c_ext0_clk_en : 1; + uint32_t uhci0_clk_en : 1; + uint32_t rmt_clk_en : 1; + uint32_t pcnt_clk_en : 1; + uint32_t ledc_clk_en : 1; + uint32_t uhci1_clk_en : 1; + uint32_t timergroup_clk_en : 1; + uint32_t efuse_clk_en : 1; + uint32_t timergroup1_clk_en : 1; + uint32_t spi3_clk_en : 1; + uint32_t pwm0_clk_en : 1; + uint32_t i2c_ext1_clk_en : 1; + uint32_t can_clk_en : 1; + uint32_t pwm1_clk_en : 1; + uint32_t i2s1_clk_en : 1; + uint32_t spi2_dma_clk_en : 1; + uint32_t usb_clk_en : 1; + uint32_t uart_mem_clk_en : 1; + uint32_t pwm2_clk_en : 1; + uint32_t pwm3_clk_en : 1; + uint32_t spi3_dma_clk_en : 1; + uint32_t apb_saradc_clk_en : 1; + uint32_t systimer_clk_en : 1; + uint32_t adc2_arb_clk_en : 1; + uint32_t spi4_clk_en : 1; }; uint32_t val; } perip_clk_en0; union { struct { - uint32_t reserved0: 1; - uint32_t crypto_aes_clk_en: 1; - uint32_t crypto_sha_clk_en: 1; - uint32_t crypto_rsa_clk_en: 1; - uint32_t crypto_ds_clk_en: 1; - uint32_t crypto_hmac_clk_en: 1; - uint32_t dma_clk_en: 1; - uint32_t sdio_host_clk_en: 1; - uint32_t lcd_cam_clk_en: 1; - uint32_t uart2_clk_en: 1; - uint32_t reserved10: 22; + uint32_t peri_backup_clk_en : 1; + uint32_t crypto_aes_clk_en : 1; + uint32_t crypto_sha_clk_en : 1; + uint32_t crypto_rsa_clk_en : 1; + uint32_t crypto_ds_clk_en : 1; + uint32_t crypto_hmac_clk_en : 1; + uint32_t dma_clk_en : 1; + uint32_t sdio_host_clk_en : 1; + uint32_t lcd_cam_clk_en : 1; + uint32_t uart2_clk_en : 1; + uint32_t usb_device_clk_en : 1; + uint32_t reserved11 : 21; }; uint32_t val; } perip_clk_en1; union { struct { - uint32_t timers_rst: 1; - uint32_t spi01_rst: 1; - uint32_t uart_rst: 1; - uint32_t wdg_rst: 1; - uint32_t i2s0_rst: 1; - uint32_t uart1_rst: 1; - uint32_t spi2_rst: 1; - uint32_t i2c_ext0_rst: 1; - uint32_t uhci0_rst: 1; - uint32_t rmt_rst: 1; - uint32_t pcnt_rst: 1; - uint32_t ledc_rst: 1; - uint32_t uhci1_rst: 1; - uint32_t timergroup_rst: 1; - uint32_t efuse_rst: 1; - uint32_t timergroup1_rst: 1; - uint32_t spi3_rst: 1; - uint32_t pwm0_rst: 1; - uint32_t i2c_ext1_rst: 1; - uint32_t can_rst: 1; - uint32_t pwm1_rst: 1; - uint32_t i2s1_rst: 1; - uint32_t spi2_dma_rst: 1; - uint32_t usb_rst: 1; - uint32_t uart_mem_rst: 1; - uint32_t pwm2_rst: 1; - uint32_t pwm3_rst: 1; - uint32_t spi3_dma_rst: 1; - uint32_t apb_saradc_rst: 1; - uint32_t systimer_rst: 1; - uint32_t adc2_arb_rst: 1; - uint32_t spi4_rst: 1; + uint32_t timers_rst : 1; + uint32_t spi01_rst : 1; + uint32_t uart_rst : 1; + uint32_t wdg_rst : 1; + uint32_t i2s0_rst : 1; + uint32_t uart1_rst : 1; + uint32_t spi2_rst : 1; + uint32_t i2c_ext0_rst : 1; + uint32_t uhci0_rst : 1; + uint32_t rmt_rst : 1; + uint32_t pcnt_rst : 1; + uint32_t ledc_rst : 1; + uint32_t uhci1_rst : 1; + uint32_t timergroup_rst : 1; + uint32_t efuse_rst : 1; + uint32_t timergroup1_rst : 1; + uint32_t spi3_rst : 1; + uint32_t pwm0_rst : 1; + uint32_t i2c_ext1_rst : 1; + uint32_t can_rst : 1; + uint32_t pwm1_rst : 1; + uint32_t i2s1_rst : 1; + uint32_t spi2_dma_rst : 1; + uint32_t usb_rst : 1; + uint32_t uart_mem_rst : 1; + uint32_t pwm2_rst : 1; + uint32_t pwm3_rst : 1; + uint32_t spi3_dma_rst : 1; + uint32_t apb_saradc_rst : 1; + uint32_t systimer_rst : 1; + uint32_t adc2_arb_rst : 1; + uint32_t spi4_rst : 1; }; uint32_t val; } perip_rst_en0; union { struct { - uint32_t reserved0: 1; - uint32_t crypto_aes_rst: 1; - uint32_t crypto_sha_rst: 1; - uint32_t crypto_rsa_rst: 1; - uint32_t crypto_ds_rst: 1; - uint32_t crypto_hmac_rst: 1; - uint32_t dma_rst: 1; - uint32_t sdio_host_rst: 1; - uint32_t lcd_cam_rst: 1; - uint32_t uart2_rst: 1; - uint32_t reserved10: 22; + uint32_t peri_backup_rst : 1; + uint32_t crypto_aes_rst : 1; + uint32_t crypto_sha_rst : 1; + uint32_t crypto_rsa_rst : 1; + uint32_t crypto_ds_rst : 1; + uint32_t crypto_hmac_rst : 1; + uint32_t dma_rst : 1; + uint32_t sdio_host_rst : 1; + uint32_t lcd_cam_rst : 1; + uint32_t uart2_rst : 1; + uint32_t usb_device_rst : 1; + uint32_t reserved11 : 21; }; uint32_t val; } perip_rst_en1; union { struct { - uint32_t bt_lpck_div_num: 12; - uint32_t reserved12: 20; + uint32_t bt_lpck_div_num : 12; + uint32_t reserved12 : 20; }; uint32_t val; } bt_lpck_div_int; union { struct { - uint32_t bt_lpck_div_b: 12; - uint32_t bt_lpck_div_a: 12; - uint32_t lpclk_sel_rtc_slow: 1; - uint32_t lpclk_sel_8m: 1; - uint32_t lpclk_sel_xtal: 1; - uint32_t lpclk_sel_xtal32k: 1; - uint32_t lpclk_rtc_en: 1; - uint32_t reserved29: 3; + uint32_t bt_lpck_div_b : 12; + uint32_t bt_lpck_div_a : 12; + uint32_t lpclk_sel_rtc_slow : 1; + uint32_t lpclk_sel_8m : 1; + uint32_t lpclk_sel_xtal : 1; + uint32_t lpclk_sel_xtal32k : 1; + uint32_t lpclk_rtc_en : 1; + uint32_t reserved29 : 3; }; uint32_t val; } bt_lpck_div_frac; union { struct { - uint32_t cpu_intr_from_cpu_0: 1; - uint32_t reserved1: 31; + uint32_t cpu_intr_from_cpu_0 : 1; + uint32_t reserved1 : 31; }; uint32_t val; } cpu_intr_from_cpu_0; union { struct { - uint32_t cpu_intr_from_cpu_1: 1; - uint32_t reserved1: 31; + uint32_t cpu_intr_from_cpu_1 : 1; + uint32_t reserved1 : 31; }; uint32_t val; } cpu_intr_from_cpu_1; union { struct { - uint32_t cpu_intr_from_cpu_2: 1; - uint32_t reserved1: 31; + uint32_t cpu_intr_from_cpu_2 : 1; + uint32_t reserved1 : 31; }; uint32_t val; } cpu_intr_from_cpu_2; union { struct { - uint32_t cpu_intr_from_cpu_3: 1; - uint32_t reserved1: 31; + uint32_t cpu_intr_from_cpu_3 : 1; + uint32_t reserved1 : 31; }; uint32_t val; } cpu_intr_from_cpu_3; union { struct { - uint32_t rsa_mem_pd: 1; - uint32_t rsa_mem_force_pu: 1; - uint32_t rsa_mem_force_pd: 1; - uint32_t reserved3: 29; + uint32_t rsa_mem_pd : 1; + uint32_t rsa_mem_force_pu : 1; + uint32_t rsa_mem_force_pd : 1; + uint32_t reserved3 : 29; }; uint32_t val; } rsa_pd_ctrl; union { struct { - uint32_t edma_clk_on: 1; - uint32_t edma_reset: 1; - uint32_t reserved2: 30; + uint32_t edma_clk_on : 1; + uint32_t edma_reset : 1; + uint32_t reserved2 : 30; }; uint32_t val; } edma_ctrl; union { struct { - uint32_t icache_clk_on: 1; - uint32_t icache_reset: 1; - uint32_t dcache_clk_on: 1; - uint32_t dcache_reset: 1; - uint32_t reserved4: 28; + uint32_t icache_clk_on : 1; + uint32_t icache_reset : 1; + uint32_t dcache_clk_on : 1; + uint32_t dcache_reset : 1; + uint32_t reserved4 : 28; }; uint32_t val; } cache_control; union { struct { - uint32_t enable_spi_manual_encrypt: 1; - uint32_t enable_download_db_encrypt: 1; - uint32_t enable_download_g0cb_decrypt: 1; - uint32_t enable_download_manual_encrypt: 1; - uint32_t reserved4: 28; + uint32_t enable_spi_manual_encrypt : 1; + uint32_t enable_download_db_encrypt : 1; + uint32_t enable_download_g0cb_decrypt : 1; + uint32_t enable_download_manual_encrypt: 1; + uint32_t reserved4 : 28; }; uint32_t val; } external_device_encrypt_decrypt_control; union { struct { - uint32_t reserved0: 8; - uint32_t rtc_mem_crc_start: 1; - uint32_t rtc_mem_crc_addr: 11; - uint32_t rtc_mem_crc_len: 11; - uint32_t rtc_mem_crc_finish: 1; + uint32_t reserved0 : 8; + uint32_t rtc_mem_crc_start : 1; + uint32_t rtc_mem_crc_addr : 11; + uint32_t rtc_mem_crc_len : 11; + uint32_t rtc_mem_crc_finish : 1; }; uint32_t val; } rtc_fastmem_config; - uint32_t rtc_fastmem_crc; /**/ + uint32_t rtc_fastmem_crc; union { struct { - uint32_t redundant_eco_drive: 1; - uint32_t redundant_eco_result: 1; - uint32_t reserved2: 30; + uint32_t redundant_eco_drive : 1; + uint32_t redundant_eco_result : 1; + uint32_t reserved2 : 30; }; uint32_t val; } redundant_eco_ctrl; union { struct { - uint32_t clk_en: 1; - uint32_t reserved1: 31; + uint32_t clk_en : 1; + uint32_t reserved1 : 31; }; uint32_t val; } clock_gate; union { struct { - uint32_t pre_div_cnt: 10; - uint32_t soc_clk_sel: 2; - uint32_t clk_xtal_freq: 7; - uint32_t clk_div_en: 1; - uint32_t reserved20: 12; + uint32_t pre_div_cnt : 10; + uint32_t soc_clk_sel : 2; + uint32_t clk_xtal_freq : 7; + uint32_t clk_div_en : 1; + uint32_t reserved20 : 12; }; uint32_t val; } sysclk_conf; union { struct { - uint32_t mem_path_len: 4; - uint32_t mem_err_cnt_clr: 1; - uint32_t mem_pvt_monitor_en: 1; - uint32_t mem_timing_err_cnt: 16; - uint32_t reserved22: 10; + uint32_t mem_path_len : 4; + uint32_t mem_err_cnt_clr : 1; + uint32_t mem_pvt_monitor_en : 1; + uint32_t mem_timing_err_cnt : 16; + uint32_t mem_vt_sel : 2; + uint32_t reserved24 : 8; }; uint32_t val; } mem_pvt; union { struct { - uint32_t comb_path_len: 5; - uint32_t comb_err_cnt_clr: 1; - uint32_t comb_pvt_monitor_en: 1; - uint32_t comb_timing_err_cnt: 16; - uint32_t reserved23: 9; + uint32_t comb_path_len_lvt : 5; + uint32_t comb_err_cnt_clr_lvt : 1; + uint32_t comb_pvt_monitor_en_lvt : 1; + uint32_t reserved7 : 18; + uint32_t reserved25 : 7; }; uint32_t val; - } comb_pvt; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; + } comb_pvt_lvt_conf; + union { + struct { + uint32_t comb_path_len_nvt : 5; + uint32_t comb_err_cnt_clr_nvt : 1; + uint32_t comb_pvt_monitor_en_nvt : 1; + uint32_t reserved7 : 18; + uint32_t reserved25 : 7; + }; + uint32_t val; + } comb_pvt_nvt_conf; + union { + struct { + uint32_t comb_path_len_hvt : 5; + uint32_t comb_err_cnt_clr_hvt : 1; + uint32_t comb_pvt_monitor_en_hvt : 1; + uint32_t reserved7 : 18; + uint32_t reserved25 : 7; + }; + uint32_t val; + } comb_pvt_hvt_conf; + union { + struct { + uint32_t comb_timing_err_cnt_lvt_site0 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_lvt_site0; + union { + struct { + uint32_t comb_timing_err_cnt_nvt_site0 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_nvt_site0; + union { + struct { + uint32_t comb_timing_err_cnt_hvt_site0 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_hvt_site0; + union { + struct { + uint32_t comb_timing_err_cnt_lvt_site1 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_lvt_site1; + union { + struct { + uint32_t comb_timing_err_cnt_nvt_site1 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_nvt_site1; + union { + struct { + uint32_t comb_timing_err_cnt_hvt_site1 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_hvt_site1; + union { + struct { + uint32_t comb_timing_err_cnt_lvt_site2 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_lvt_site2; + union { + struct { + uint32_t comb_timing_err_cnt_nvt_site2 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_nvt_site2; + union { + struct { + uint32_t comb_timing_err_cnt_hvt_site2 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_hvt_site2; + union { + struct { + uint32_t comb_timing_err_cnt_lvt_site3 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_lvt_site3; + union { + struct { + uint32_t comb_timing_err_cnt_nvt_site3 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_nvt_site3; + union { + struct { + uint32_t comb_timing_err_cnt_hvt_site3 : 16; + uint32_t reserved16 : 16; + }; + uint32_t val; + } comb_pvt_err_hvt_site3; uint32_t reserved_c4; uint32_t reserved_c8; uint32_t reserved_cc; @@ -383,13 +443,7 @@ typedef volatile struct { uint32_t reserved_f4; uint32_t reserved_f8; uint32_t reserved_fc; - union { - struct { - uint32_t retention_link_addr: 27; - uint32_t reserved27: 5; - }; - uint32_t val; - } retention_bus_ctrl; + uint32_t reserved_100; uint32_t reserved_104; uint32_t reserved_108; uint32_t reserved_10c; @@ -1350,15 +1404,17 @@ typedef volatile struct { uint32_t reserved_ff8; union { struct { - uint32_t date: 28; - uint32_t reserved28: 4; + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } date; } system_dev_t; - extern system_dev_t SYSTEM; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SYSTEM_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/timer_group_caps.h b/components/soc/esp32s3/include/soc/timer_group_caps.h new file mode 100644 index 0000000000..67d138d9ca --- /dev/null +++ b/components/soc/esp32s3/include/soc/timer_group_caps.h @@ -0,0 +1,17 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_TIMER_GROUP_SUPPORT_XTAL diff --git a/components/soc/esp32s3/include/soc/timer_group_reg.h b/components/soc/esp32s3/include/soc/timer_group_reg.h index 9766a0af55..fcab6a1e14 100644 --- a/components/soc/esp32s3/include/soc/timer_group_reg.h +++ b/components/soc/esp32s3/include/soc/timer_group_reg.h @@ -11,7 +11,9 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_TIMG_REG_H_ +#define _SOC_TIMG_REG_H_ + #ifdef __cplusplus extern "C" { @@ -38,490 +40,495 @@ extern "C" { #define TIMG_WDT_RESET_LENGTH_1600_NS 6 #define TIMG_WDT_RESET_LENGTH_3200_NS 7 -#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) /* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T0_EN (BIT(31)) -#define TIMG_T0_EN_M (BIT(31)) -#define TIMG_T0_EN_V 0x1 -#define TIMG_T0_EN_S 31 +/*description: .*/ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (BIT(31)) +#define TIMG_T0_EN_V 0x1 +#define TIMG_T0_EN_S 31 /* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ -/*description: */ -#define TIMG_T0_INCREASE (BIT(30)) -#define TIMG_T0_INCREASE_M (BIT(30)) -#define TIMG_T0_INCREASE_V 0x1 -#define TIMG_T0_INCREASE_S 30 +/*description: .*/ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (BIT(30)) +#define TIMG_T0_INCREASE_V 0x1 +#define TIMG_T0_INCREASE_S 30 /* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ -/*description: */ -#define TIMG_T0_AUTORELOAD (BIT(29)) -#define TIMG_T0_AUTORELOAD_M (BIT(29)) -#define TIMG_T0_AUTORELOAD_V 0x1 -#define TIMG_T0_AUTORELOAD_S 29 +/*description: .*/ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (BIT(29)) +#define TIMG_T0_AUTORELOAD_V 0x1 +#define TIMG_T0_AUTORELOAD_S 29 /* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ -/*description: */ -#define TIMG_T0_DIVIDER 0x0000FFFF -#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V) << (TIMG_T0_DIVIDER_S)) -#define TIMG_T0_DIVIDER_V 0xFFFF -#define TIMG_T0_DIVIDER_S 13 +/*description: .*/ +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) +#define TIMG_T0_DIVIDER_V 0xFFFF +#define TIMG_T0_DIVIDER_S 13 /* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T0_ALARM_EN (BIT(10)) -#define TIMG_T0_ALARM_EN_M (BIT(10)) -#define TIMG_T0_ALARM_EN_V 0x1 -#define TIMG_T0_ALARM_EN_S 10 +/*description: .*/ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (BIT(10)) +#define TIMG_T0_ALARM_EN_V 0x1 +#define TIMG_T0_ALARM_EN_S 10 /* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define TIMG_T0_USE_XTAL (BIT(9)) -#define TIMG_T0_USE_XTAL_M (BIT(9)) -#define TIMG_T0_USE_XTAL_V 0x1 -#define TIMG_T0_USE_XTAL_S 9 +/*description: .*/ +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (BIT(9)) +#define TIMG_T0_USE_XTAL_V 0x1 +#define TIMG_T0_USE_XTAL_S 9 -#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) /* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_T0_LO 0xFFFFFFFF -#define TIMG_T0_LO_M ((TIMG_T0_LO_V) << (TIMG_T0_LO_S)) -#define TIMG_T0_LO_V 0xFFFFFFFF -#define TIMG_T0_LO_S 0 +/*description: .*/ +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 -#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) /* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define TIMG_T0_HI 0x003FFFFF -#define TIMG_T0_HI_M ((TIMG_T0_HI_V) << (TIMG_T0_HI_S)) -#define TIMG_T0_HI_V 0x3FFFFF -#define TIMG_T0_HI_S 0 +/*description: .*/ +#define TIMG_T0_HI 0x003FFFFF +#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) +#define TIMG_T0_HI_V 0x3FFFFF +#define TIMG_T0_HI_S 0 -#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xC) /* TIMG_T0_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T0_UPDATE (BIT(31)) -#define TIMG_T0_UPDATE_M (BIT(31)) -#define TIMG_T0_UPDATE_V 0x1 -#define TIMG_T0_UPDATE_S 31 +/*description: .*/ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (BIT(31)) +#define TIMG_T0_UPDATE_V 0x1 +#define TIMG_T0_UPDATE_S 31 -#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) /* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_T0_ALARM_LO 0xFFFFFFFF -#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V) << (TIMG_T0_ALARM_LO_S)) -#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF -#define TIMG_T0_ALARM_LO_S 0 +/*description: .*/ +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 -#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) /* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define TIMG_T0_ALARM_HI 0x003FFFFF -#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V) << (TIMG_T0_ALARM_HI_S)) -#define TIMG_T0_ALARM_HI_V 0x3FFFFF -#define TIMG_T0_ALARM_HI_S 0 +/*description: .*/ +#define TIMG_T0_ALARM_HI 0x003FFFFF +#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) +#define TIMG_T0_ALARM_HI_V 0x3FFFFF +#define TIMG_T0_ALARM_HI_S 0 -#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) /* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_T0_LOAD_LO 0xFFFFFFFF -#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V) << (TIMG_T0_LOAD_LO_S)) -#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF -#define TIMG_T0_LOAD_LO_S 0 +/*description: .*/ +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 -#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1C) /* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define TIMG_T0_LOAD_HI 0x003FFFFF -#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V) << (TIMG_T0_LOAD_HI_S)) -#define TIMG_T0_LOAD_HI_V 0x3FFFFF -#define TIMG_T0_LOAD_HI_S 0 +/*description: .*/ +#define TIMG_T0_LOAD_HI 0x003FFFFF +#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) +#define TIMG_T0_LOAD_HI_V 0x3FFFFF +#define TIMG_T0_LOAD_HI_S 0 -#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20) /* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_T0_LOAD 0xFFFFFFFF -#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V) << (TIMG_T0_LOAD_S)) -#define TIMG_T0_LOAD_V 0xFFFFFFFF -#define TIMG_T0_LOAD_S 0 +/*description: .*/ +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 -#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024) +#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24) /* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T1_EN (BIT(31)) -#define TIMG_T1_EN_M (BIT(31)) -#define TIMG_T1_EN_V 0x1 -#define TIMG_T1_EN_S 31 +/*description: .*/ +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (BIT(31)) +#define TIMG_T1_EN_V 0x1 +#define TIMG_T1_EN_S 31 /* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ -/*description: */ -#define TIMG_T1_INCREASE (BIT(30)) -#define TIMG_T1_INCREASE_M (BIT(30)) -#define TIMG_T1_INCREASE_V 0x1 -#define TIMG_T1_INCREASE_S 30 +/*description: .*/ +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (BIT(30)) +#define TIMG_T1_INCREASE_V 0x1 +#define TIMG_T1_INCREASE_S 30 /* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ -/*description: */ -#define TIMG_T1_AUTORELOAD (BIT(29)) -#define TIMG_T1_AUTORELOAD_M (BIT(29)) -#define TIMG_T1_AUTORELOAD_V 0x1 -#define TIMG_T1_AUTORELOAD_S 29 +/*description: .*/ +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (BIT(29)) +#define TIMG_T1_AUTORELOAD_V 0x1 +#define TIMG_T1_AUTORELOAD_S 29 /* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ -/*description: */ -#define TIMG_T1_DIVIDER 0x0000FFFF -#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V) << (TIMG_T1_DIVIDER_S)) -#define TIMG_T1_DIVIDER_V 0xFFFF -#define TIMG_T1_DIVIDER_S 13 +/*description: .*/ +#define TIMG_T1_DIVIDER 0x0000FFFF +#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S)) +#define TIMG_T1_DIVIDER_V 0xFFFF +#define TIMG_T1_DIVIDER_S 13 /* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T1_ALARM_EN (BIT(10)) -#define TIMG_T1_ALARM_EN_M (BIT(10)) -#define TIMG_T1_ALARM_EN_V 0x1 -#define TIMG_T1_ALARM_EN_S 10 +/*description: .*/ +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (BIT(10)) +#define TIMG_T1_ALARM_EN_V 0x1 +#define TIMG_T1_ALARM_EN_S 10 /* TIMG_T1_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define TIMG_T1_USE_XTAL (BIT(9)) -#define TIMG_T1_USE_XTAL_M (BIT(9)) -#define TIMG_T1_USE_XTAL_V 0x1 -#define TIMG_T1_USE_XTAL_S 9 +/*description: .*/ +#define TIMG_T1_USE_XTAL (BIT(9)) +#define TIMG_T1_USE_XTAL_M (BIT(9)) +#define TIMG_T1_USE_XTAL_V 0x1 +#define TIMG_T1_USE_XTAL_S 9 -#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028) +#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28) /* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_T1_LO 0xFFFFFFFF -#define TIMG_T1_LO_M ((TIMG_T1_LO_V) << (TIMG_T1_LO_S)) -#define TIMG_T1_LO_V 0xFFFFFFFF -#define TIMG_T1_LO_S 0 +/*description: .*/ +#define TIMG_T1_LO 0xFFFFFFFF +#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S)) +#define TIMG_T1_LO_V 0xFFFFFFFF +#define TIMG_T1_LO_S 0 -#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c) +#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2C) /* TIMG_T1_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define TIMG_T1_HI 0x003FFFFF -#define TIMG_T1_HI_M ((TIMG_T1_HI_V) << (TIMG_T1_HI_S)) -#define TIMG_T1_HI_V 0x3FFFFF -#define TIMG_T1_HI_S 0 +/*description: .*/ +#define TIMG_T1_HI 0x003FFFFF +#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S)) +#define TIMG_T1_HI_V 0x3FFFFF +#define TIMG_T1_HI_S 0 -#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030) +#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30) /* TIMG_T1_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T1_UPDATE (BIT(31)) -#define TIMG_T1_UPDATE_M (BIT(31)) -#define TIMG_T1_UPDATE_V 0x1 -#define TIMG_T1_UPDATE_S 31 +/*description: .*/ +#define TIMG_T1_UPDATE (BIT(31)) +#define TIMG_T1_UPDATE_M (BIT(31)) +#define TIMG_T1_UPDATE_V 0x1 +#define TIMG_T1_UPDATE_S 31 -#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034) +#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34) /* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_T1_ALARM_LO 0xFFFFFFFF -#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V) << (TIMG_T1_ALARM_LO_S)) -#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF -#define TIMG_T1_ALARM_LO_S 0 +/*description: .*/ +#define TIMG_T1_ALARM_LO 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S)) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_S 0 -#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038) +#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38) /* TIMG_T1_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define TIMG_T1_ALARM_HI 0x003FFFFF -#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V) << (TIMG_T1_ALARM_HI_S)) -#define TIMG_T1_ALARM_HI_V 0x3FFFFF -#define TIMG_T1_ALARM_HI_S 0 +/*description: .*/ +#define TIMG_T1_ALARM_HI 0x003FFFFF +#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S)) +#define TIMG_T1_ALARM_HI_V 0x3FFFFF +#define TIMG_T1_ALARM_HI_S 0 -#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c) +#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3C) /* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_T1_LOAD_LO 0xFFFFFFFF -#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V) << (TIMG_T1_LOAD_LO_S)) -#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF -#define TIMG_T1_LOAD_LO_S 0 +/*description: .*/ +#define TIMG_T1_LOAD_LO 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S)) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_S 0 -#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040) +#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40) /* TIMG_T1_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define TIMG_T1_LOAD_HI 0x003FFFFF -#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V) << (TIMG_T1_LOAD_HI_S)) -#define TIMG_T1_LOAD_HI_V 0x3FFFFF -#define TIMG_T1_LOAD_HI_S 0 +/*description: .*/ +#define TIMG_T1_LOAD_HI 0x003FFFFF +#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S)) +#define TIMG_T1_LOAD_HI_V 0x3FFFFF +#define TIMG_T1_LOAD_HI_S 0 -#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044) +#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44) /* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_T1_LOAD 0xFFFFFFFF -#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V) << (TIMG_T1_LOAD_S)) -#define TIMG_T1_LOAD_V 0xFFFFFFFF -#define TIMG_T1_LOAD_S 0 +/*description: .*/ +#define TIMG_T1_LOAD 0xFFFFFFFF +#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S)) +#define TIMG_T1_LOAD_V 0xFFFFFFFF +#define TIMG_T1_LOAD_S 0 -#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) /* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_WDT_EN (BIT(31)) -#define TIMG_WDT_EN_M (BIT(31)) -#define TIMG_WDT_EN_V 0x1 -#define TIMG_WDT_EN_S 31 +/*description: .*/ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (BIT(31)) +#define TIMG_WDT_EN_V 0x1 +#define TIMG_WDT_EN_S 31 /* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ -/*description: */ -#define TIMG_WDT_STG0 0x00000003 -#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V) << (TIMG_WDT_STG0_S)) -#define TIMG_WDT_STG0_V 0x3 -#define TIMG_WDT_STG0_S 29 +/*description: .*/ +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) +#define TIMG_WDT_STG0_V 0x3 +#define TIMG_WDT_STG0_S 29 /* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ -/*description: */ -#define TIMG_WDT_STG1 0x00000003 -#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V) << (TIMG_WDT_STG1_S)) -#define TIMG_WDT_STG1_V 0x3 -#define TIMG_WDT_STG1_S 27 +/*description: .*/ +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) +#define TIMG_WDT_STG1_V 0x3 +#define TIMG_WDT_STG1_S 27 /* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ -/*description: */ -#define TIMG_WDT_STG2 0x00000003 -#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V) << (TIMG_WDT_STG2_S)) -#define TIMG_WDT_STG2_V 0x3 -#define TIMG_WDT_STG2_S 25 +/*description: .*/ +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) +#define TIMG_WDT_STG2_V 0x3 +#define TIMG_WDT_STG2_S 25 /* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ -/*description: */ -#define TIMG_WDT_STG3 0x00000003 -#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V) << (TIMG_WDT_STG3_S)) -#define TIMG_WDT_STG3_V 0x3 -#define TIMG_WDT_STG3_S 23 +/*description: .*/ +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) +#define TIMG_WDT_STG3_V 0x3 +#define TIMG_WDT_STG3_S 23 /* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ -/*description: */ -#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 -#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V) << (TIMG_WDT_CPU_RESET_LENGTH_S)) -#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 -#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/*description: .*/ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 /* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ -/*description: */ -#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 -#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V) << (TIMG_WDT_SYS_RESET_LENGTH_S)) -#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 -#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/*description: .*/ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 /* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ -/*description: */ -#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) -#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) -#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 -#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/*description: .*/ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 /* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) -#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13)) -#define TIMG_WDT_PROCPU_RESET_EN_V 0x1 -#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/*description: .*/ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x1 +#define TIMG_WDT_PROCPU_RESET_EN_S 13 /* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) -#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12)) -#define TIMG_WDT_APPCPU_RESET_EN_V 0x1 -#define TIMG_WDT_APPCPU_RESET_EN_S 12 +/*description: .*/ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x1 +#define TIMG_WDT_APPCPU_RESET_EN_S 12 -#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4C) /* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ -/*description: */ -#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF -#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V) << (TIMG_WDT_CLK_PRESCALE_S)) -#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF -#define TIMG_WDT_CLK_PRESCALE_S 16 +/*description: .*/ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) +#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF +#define TIMG_WDT_CLK_PRESCALE_S 16 -#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) /* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ -/*description: */ -#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF -#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V) << (TIMG_WDT_STG0_HOLD_S)) -#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF -#define TIMG_WDT_STG0_HOLD_S 0 +/*description: .*/ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 -#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) /* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ -/*description: */ -#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF -#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V) << (TIMG_WDT_STG1_HOLD_S)) -#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF -#define TIMG_WDT_STG1_HOLD_S 0 +/*description: .*/ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 -#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) /* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ -/*description: */ -#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF -#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V) << (TIMG_WDT_STG2_HOLD_S)) -#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF -#define TIMG_WDT_STG2_HOLD_S 0 +/*description: .*/ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 -#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5C) /* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ -/*description: */ -#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF -#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V) << (TIMG_WDT_STG3_HOLD_S)) -#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF -#define TIMG_WDT_STG3_HOLD_S 0 +/*description: .*/ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 -#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60) /* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define TIMG_WDT_FEED 0xFFFFFFFF -#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V) << (TIMG_WDT_FEED_S)) -#define TIMG_WDT_FEED_V 0xFFFFFFFF -#define TIMG_WDT_FEED_S 0 +/*description: .*/ +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 -#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64) /* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ -/*description: */ -#define TIMG_WDT_WKEY 0xFFFFFFFF -#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V) << (TIMG_WDT_WKEY_S)) -#define TIMG_WDT_WKEY_V 0xFFFFFFFF -#define TIMG_WDT_WKEY_S 0 +/*description: .*/ +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 -#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) /* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_RTC_CALI_START (BIT(31)) -#define TIMG_RTC_CALI_START_M (BIT(31)) -#define TIMG_RTC_CALI_START_V 0x1 -#define TIMG_RTC_CALI_START_S 31 +/*description: .*/ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 /* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ -/*description: */ -#define TIMG_RTC_CALI_MAX 0x00007FFF -#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V) << (TIMG_RTC_CALI_MAX_S)) -#define TIMG_RTC_CALI_MAX_V 0x7FFF -#define TIMG_RTC_CALI_MAX_S 16 +/*description: .*/ +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7FFF +#define TIMG_RTC_CALI_MAX_S 16 /* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_RTC_CALI_RDY (BIT(15)) -#define TIMG_RTC_CALI_RDY_M (BIT(15)) -#define TIMG_RTC_CALI_RDY_V 0x1 -#define TIMG_RTC_CALI_RDY_S 15 +/*description: .*/ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 /* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ -/*description: */ -#define TIMG_RTC_CALI_CLK_SEL 0x00000003 -#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V) << (TIMG_RTC_CALI_CLK_SEL_S)) -#define TIMG_RTC_CALI_CLK_SEL_V 0x3 -#define TIMG_RTC_CALI_CLK_SEL_S 13 +/*description: .*/ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 /* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: */ -#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) -#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) -#define TIMG_RTC_CALI_START_CYCLING_V 0x1 -#define TIMG_RTC_CALI_START_CYCLING_S 12 +/*description: .*/ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 -#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6C) /* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ -/*description: */ -#define TIMG_RTC_CALI_VALUE 0x01FFFFFF -#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V) << (TIMG_RTC_CALI_VALUE_S)) -#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF -#define TIMG_RTC_CALI_VALUE_S 7 +/*description: .*/ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 /* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0)) -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1 -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 +/*description: .*/ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1 +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 -#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070) +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70) /* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_WDT_INT_ENA (BIT(2)) -#define TIMG_WDT_INT_ENA_M (BIT(2)) -#define TIMG_WDT_INT_ENA_V 0x1 -#define TIMG_WDT_INT_ENA_S 2 +/*description: .*/ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (BIT(2)) +#define TIMG_WDT_INT_ENA_V 0x1 +#define TIMG_WDT_INT_ENA_S 2 /* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T1_INT_ENA (BIT(1)) -#define TIMG_T1_INT_ENA_M (BIT(1)) -#define TIMG_T1_INT_ENA_V 0x1 -#define TIMG_T1_INT_ENA_S 1 +/*description: .*/ +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (BIT(1)) +#define TIMG_T1_INT_ENA_V 0x1 +#define TIMG_T1_INT_ENA_S 1 /* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T0_INT_ENA (BIT(0)) -#define TIMG_T0_INT_ENA_M (BIT(0)) -#define TIMG_T0_INT_ENA_V 0x1 -#define TIMG_T0_INT_ENA_S 0 +/*description: .*/ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (BIT(0)) +#define TIMG_T0_INT_ENA_V 0x1 +#define TIMG_T0_INT_ENA_S 0 -#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074) +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74) /* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_WDT_INT_RAW (BIT(2)) -#define TIMG_WDT_INT_RAW_M (BIT(2)) -#define TIMG_WDT_INT_RAW_V 0x1 -#define TIMG_WDT_INT_RAW_S 2 +/*description: .*/ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (BIT(2)) +#define TIMG_WDT_INT_RAW_V 0x1 +#define TIMG_WDT_INT_RAW_S 2 /* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T1_INT_RAW (BIT(1)) -#define TIMG_T1_INT_RAW_M (BIT(1)) -#define TIMG_T1_INT_RAW_V 0x1 -#define TIMG_T1_INT_RAW_S 1 +/*description: .*/ +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (BIT(1)) +#define TIMG_T1_INT_RAW_V 0x1 +#define TIMG_T1_INT_RAW_S 1 /* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T0_INT_RAW (BIT(0)) -#define TIMG_T0_INT_RAW_M (BIT(0)) -#define TIMG_T0_INT_RAW_V 0x1 -#define TIMG_T0_INT_RAW_S 0 +/*description: .*/ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (BIT(0)) +#define TIMG_T0_INT_RAW_V 0x1 +#define TIMG_T0_INT_RAW_S 0 -#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078) +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78) /* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_WDT_INT_ST (BIT(2)) -#define TIMG_WDT_INT_ST_M (BIT(2)) -#define TIMG_WDT_INT_ST_V 0x1 -#define TIMG_WDT_INT_ST_S 2 +/*description: .*/ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (BIT(2)) +#define TIMG_WDT_INT_ST_V 0x1 +#define TIMG_WDT_INT_ST_S 2 /* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T1_INT_ST (BIT(1)) -#define TIMG_T1_INT_ST_M (BIT(1)) -#define TIMG_T1_INT_ST_V 0x1 -#define TIMG_T1_INT_ST_S 1 +/*description: .*/ +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (BIT(1)) +#define TIMG_T1_INT_ST_V 0x1 +#define TIMG_T1_INT_ST_S 1 /* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T0_INT_ST (BIT(0)) -#define TIMG_T0_INT_ST_M (BIT(0)) -#define TIMG_T0_INT_ST_V 0x1 -#define TIMG_T0_INT_ST_S 0 +/*description: .*/ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (BIT(0)) +#define TIMG_T0_INT_ST_V 0x1 +#define TIMG_T0_INT_ST_S 0 -#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c) +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7C) /* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_WDT_INT_CLR (BIT(2)) -#define TIMG_WDT_INT_CLR_M (BIT(2)) -#define TIMG_WDT_INT_CLR_V 0x1 -#define TIMG_WDT_INT_CLR_S 2 +/*description: .*/ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (BIT(2)) +#define TIMG_WDT_INT_CLR_V 0x1 +#define TIMG_WDT_INT_CLR_S 2 /* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T1_INT_CLR (BIT(1)) -#define TIMG_T1_INT_CLR_M (BIT(1)) -#define TIMG_T1_INT_CLR_V 0x1 -#define TIMG_T1_INT_CLR_S 1 +/*description: .*/ +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (BIT(1)) +#define TIMG_T1_INT_CLR_V 0x1 +#define TIMG_T1_INT_CLR_S 1 /* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_T0_INT_CLR (BIT(0)) -#define TIMG_T0_INT_CLR_M (BIT(0)) -#define TIMG_T0_INT_CLR_V 0x1 -#define TIMG_T0_INT_CLR_S 0 +/*description: .*/ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (BIT(0)) +#define TIMG_T0_INT_CLR_V 0x1 +#define TIMG_T0_INT_CLR_S 0 -#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080) +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) /* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */ -/*description: timeout if cali value counts over threshold*/ -#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF -#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V) << (TIMG_RTC_CALI_TIMEOUT_THRES_S)) -#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF -#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 +/*description: timeout if cali value counts over threshold.*/ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S)) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 /* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */ -/*description: Cycles that release calibration timeout reset*/ -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V) << (TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)) -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/*description: Cycles that release calibration timeout reset.*/ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 /* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: timeout indicator*/ -#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) -#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0)) -#define TIMG_RTC_CALI_TIMEOUT_V 0x1 -#define TIMG_RTC_CALI_TIMEOUT_S 0 +/*description: timeout indicator.*/ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_V 0x1 +#define TIMG_RTC_CALI_TIMEOUT_S 0 -#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xF8) /* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003071 ; */ -/*description: */ -#define TIMG_NTIMERS_DATE 0x0FFFFFFF -#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V) << (TIMG_NTIMERS_DATE_S)) -#define TIMG_NTIMERS_DATE_V 0xFFFFFFF -#define TIMG_NTIMERS_DATE_S 0 +/*description: .*/ +#define TIMG_NTIMERS_DATE 0x0FFFFFFF +#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) +#define TIMG_NTIMERS_DATE_V 0xFFFFFFF +#define TIMG_NTIMERS_DATE_S 0 -#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) +#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xFC) /* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define TIMG_CLK_EN (BIT(31)) -#define TIMG_CLK_EN_M (BIT(31)) -#define TIMG_CLK_EN_V 0x1 -#define TIMG_CLK_EN_S 31 +/*description: .*/ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (BIT(31)) +#define TIMG_CLK_EN_V 0x1 +#define TIMG_CLK_EN_S 31 + #ifdef __cplusplus } #endif + + + +#endif /*_SOC_TIMG_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/timer_group_struct.h b/components/soc/esp32s3/include/soc/timer_group_struct.h index 3517841934..79ff495dbd 100644 --- a/components/soc/esp32s3/include/soc/timer_group_struct.h +++ b/components/soc/esp32s3/include/soc/timer_group_struct.h @@ -11,8 +11,8 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - +#ifndef _SOC_TIMG_STRUCT_H_ +#define _SOC_TIMG_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif @@ -23,143 +23,143 @@ typedef volatile struct { struct { union { struct { - uint32_t reserved0: 9; - uint32_t use_xtal: 1; - uint32_t alarm_en: 1; - uint32_t reserved11: 1; - uint32_t reserved12: 1; - uint32_t divider: 16; - uint32_t autoreload: 1; - uint32_t increase: 1; - uint32_t enable: 1; + uint32_t reserved0 : 9; + uint32_t use_xtal : 1; + uint32_t alarm_en : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t divider : 16; + uint32_t autoreload : 1; + uint32_t increase : 1; + uint32_t enable : 1; }; uint32_t val; } config; - uint32_t cnt_low; /**/ + uint32_t cnt_low; union { struct { - uint32_t hi: 22; - uint32_t reserved22: 10; + uint32_t hi : 22; + uint32_t reserved22 : 10; }; uint32_t val; } cnt_high; union { struct { - uint32_t reserved0: 31; - uint32_t update: 1; + uint32_t reserved0 : 31; + uint32_t update : 1; }; uint32_t val; } update; - uint32_t alarm_low; /**/ + uint32_t alarm_low; union { struct { - uint32_t alarm_hi: 22; - uint32_t reserved22: 10; + uint32_t alarm_hi : 22; + uint32_t reserved22 : 10; }; uint32_t val; } alarm_high; - uint32_t load_low; /**/ + uint32_t load_low; union { struct { - uint32_t load_hi: 22; - uint32_t reserved22: 10; + uint32_t load_hi : 22; + uint32_t reserved22 : 10; }; uint32_t val; } load_high; - uint32_t reload; /**/ + uint32_t reload; } hw_timer[2]; union { struct { - uint32_t reserved0: 12; - uint32_t appcpu_reset_en: 1; - uint32_t procpu_reset_en: 1; - uint32_t flashboot_mod_en: 1; - uint32_t sys_reset_length: 3; - uint32_t cpu_reset_length: 3; - uint32_t reserved21: 1; - uint32_t reserved22: 1; - uint32_t stg3: 2; - uint32_t stg2: 2; - uint32_t stg1: 2; - uint32_t stg0: 2; - uint32_t en: 1; + uint32_t reserved0 : 12; + uint32_t appcpu_reset_en : 1; + uint32_t procpu_reset_en : 1; + uint32_t flashboot_mod_en : 1; + uint32_t sys_reset_length : 3; + uint32_t cpu_reset_length : 3; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t stg3 : 2; + uint32_t stg2 : 2; + uint32_t stg1 : 2; + uint32_t stg0 : 2; + uint32_t en : 1; }; uint32_t val; } wdt_config0; union { struct { - uint32_t reserved0: 16; - uint32_t clk_prescale: 16; + uint32_t reserved0 : 16; + uint32_t clk_prescale : 16; }; uint32_t val; } wdt_config1; - uint32_t wdt_config2; /**/ - uint32_t wdt_config3; /**/ - uint32_t wdt_config4; /**/ - uint32_t wdt_config5; /**/ - uint32_t wdt_feed; /**/ - uint32_t wdt_wprotect; /**/ + uint32_t wdt_config2; + uint32_t wdt_config3; + uint32_t wdt_config4; + uint32_t wdt_config5; + uint32_t wdt_feed; + uint32_t wdt_wprotect; union { struct { - uint32_t reserved0: 12; - uint32_t start_cycling: 1; - uint32_t clk_sel: 2; - uint32_t rdy: 1; - uint32_t max: 15; - uint32_t start: 1; + uint32_t reserved0 : 12; + uint32_t start_cycling : 1; + uint32_t clk_sel : 2; + uint32_t rdy : 1; + uint32_t max : 15; + uint32_t start : 1; }; uint32_t val; } rtc_cali_cfg; union { struct { - uint32_t cycling_data_vld: 1; - uint32_t reserved1: 6; - uint32_t value: 25; + uint32_t cycling_data_vld : 1; + uint32_t reserved1 : 6; + uint32_t value : 25; }; uint32_t val; } rtc_cali_cfg1; union { struct { - uint32_t t0: 1; - uint32_t t1: 1; - uint32_t wdt: 1; - uint32_t reserved3: 29; + uint32_t t0 : 1; + uint32_t t1 : 1; + uint32_t wdt : 1; + uint32_t reserved3 : 29; }; uint32_t val; } int_ena; union { struct { - uint32_t t0: 1; - uint32_t t1: 1; - uint32_t wdt: 1; - uint32_t reserved3: 29; + uint32_t t0 : 1; + uint32_t t1 : 1; + uint32_t wdt : 1; + uint32_t reserved3 : 29; }; uint32_t val; } int_raw; union { struct { - uint32_t t0: 1; - uint32_t t1: 1; - uint32_t wdt: 1; - uint32_t reserved3: 29; + uint32_t t0 : 1; + uint32_t t1 : 1; + uint32_t wdt : 1; + uint32_t reserved3 : 29; }; uint32_t val; } int_st; union { struct { - uint32_t t0: 1; - uint32_t t1: 1; - uint32_t wdt: 1; - uint32_t reserved3: 29; + uint32_t t0 : 1; + uint32_t t1 : 1; + uint32_t wdt : 1; + uint32_t reserved3 : 29; }; uint32_t val; } int_clr; union { struct { - uint32_t timeout: 1; /*timeout indicator*/ - uint32_t reserved1: 2; - uint32_t timeout_rst_cnt: 4; /*Cycles that release calibration timeout reset*/ - uint32_t timeout_thres: 25; /*timeout if cali value counts over threshold*/ + uint32_t timeout : 1; /*timeout indicator*/ + uint32_t reserved1 : 2; + uint32_t timeout_rst_cnt : 4; /*Cycles that release calibration timeout reset*/ + uint32_t timeout_thres : 25; /*timeout if cali value counts over threshold*/ }; uint32_t val; } rtc_cali_cfg2; @@ -194,23 +194,23 @@ typedef volatile struct { uint32_t reserved_f4; union { struct { - uint32_t date: 28; - uint32_t reserved28: 4; + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } timg_date; union { struct { - uint32_t reserved0: 31; - uint32_t en: 1; + uint32_t reserved0 : 31; + uint32_t clk_en : 1; }; uint32_t val; } clk; } timg_dev_t; - extern timg_dev_t TIMERG0; extern timg_dev_t TIMERG1; - #ifdef __cplusplus } #endif + +#endif /* _SOC_TIMG_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/twai_struct.h b/components/soc/esp32s3/include/soc/twai_struct.h index 58bdc6d1ab..77debe0c43 100644 --- a/components/soc/esp32s3/include/soc/twai_struct.h +++ b/components/soc/esp32s3/include/soc/twai_struct.h @@ -22,7 +22,7 @@ extern "C" { /* ---------------------------- Register Layout ------------------------------ */ -/* The TWAI peripheral's registers are 8bits, however the ESP32-S3 can only access +/* The TWAI peripheral's registers are 8bits, however the ESP32 can only access * peripheral registers every 32bits. Therefore each TWAI register is mapped to * the least significant byte of every 32bits. */ @@ -61,7 +61,7 @@ typedef volatile struct twai_dev_s { uint32_t es: 1; /* SR.6 Error Status */ uint32_t bs: 1; /* SR.7 Bus Status */ uint32_t ms: 1; /* SR.8 Miss Status */ - uint32_t reserved23: 23; /* Internal Reserved */ + uint32_t reserved24: 23; /* Internal Reserved */ }; uint32_t val; } status_reg; /* Address 2 */ diff --git a/components/soc/esp32s3/include/soc/uart_reg.h b/components/soc/esp32s3/include/soc/uart_reg.h index b992b43a02..28b5dcaf6f 100644 --- a/components/soc/esp32s3/include/soc/uart_reg.h +++ b/components/soc/esp32s3/include/soc/uart_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,1170 +11,1252 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_UART_REG_H_ +#define _SOC_UART_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: */ -#define UART_RXFIFO_RD_BYTE 0x000000FF -#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V) << (UART_RXFIFO_RD_BYTE_S)) -#define UART_RXFIFO_RD_BYTE_V 0xFF -#define UART_RXFIFO_RD_BYTE_S 0 +/*description: UART $n accesses FIFO via this register..*/ +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_V 0xFF +#define UART_RXFIFO_RD_BYTE_S 0 -#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) -/* UART_WAKEUP_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define UART_WAKEUP_INT_RAW (BIT(19)) -#define UART_WAKEUP_INT_RAW_M (BIT(19)) -#define UART_WAKEUP_INT_RAW_V 0x1 -#define UART_WAKEUP_INT_RAW_S 19 -/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 -/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_CLASH_INT_RAW (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_V 0x1 -#define UART_RS485_CLASH_INT_RAW_S 17 -/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 -#define UART_RS485_FRM_ERR_INT_RAW_S 16 -/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 -#define UART_RS485_PARITY_ERR_INT_RAW_S 15 -/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_DONE_INT_RAW (BIT(14)) -#define UART_TX_DONE_INT_RAW_M (BIT(14)) -#define UART_TX_DONE_INT_RAW_V 0x1 -#define UART_TX_DONE_INT_RAW_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 -/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_V 0x1 -#define UART_TX_BRK_DONE_INT_RAW_S 12 -/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define UART_GLITCH_DET_INT_RAW (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_V 0x1 -#define UART_GLITCH_DET_INT_RAW_S 11 -/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_XOFF_INT_RAW (BIT(10)) -#define UART_SW_XOFF_INT_RAW_M (BIT(10)) -#define UART_SW_XOFF_INT_RAW_V 0x1 -#define UART_SW_XOFF_INT_RAW_S 10 -/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_XON_INT_RAW (BIT(9)) -#define UART_SW_XON_INT_RAW_M (BIT(9)) -#define UART_SW_XON_INT_RAW_V 0x1 -#define UART_SW_XON_INT_RAW_S 9 -/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 -#define UART_RXFIFO_TOUT_INT_RAW_S 8 -/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define UART_BRK_DET_INT_RAW (BIT(7)) -#define UART_BRK_DET_INT_RAW_M (BIT(7)) -#define UART_BRK_DET_INT_RAW_V 0x1 -#define UART_BRK_DET_INT_RAW_S 7 -/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define UART_CTS_CHG_INT_RAW (BIT(6)) -#define UART_CTS_CHG_INT_RAW_M (BIT(6)) -#define UART_CTS_CHG_INT_RAW_V 0x1 -#define UART_CTS_CHG_INT_RAW_S 6 -/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UART_DSR_CHG_INT_RAW (BIT(5)) -#define UART_DSR_CHG_INT_RAW_M (BIT(5)) -#define UART_DSR_CHG_INT_RAW_V 0x1 -#define UART_DSR_CHG_INT_RAW_S 5 -/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_V 0x1 -#define UART_RXFIFO_OVF_INT_RAW_S 4 -/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UART_FRM_ERR_INT_RAW (BIT(3)) -#define UART_FRM_ERR_INT_RAW_M (BIT(3)) -#define UART_FRM_ERR_INT_RAW_V 0x1 -#define UART_FRM_ERR_INT_RAW_S 3 -/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UART_PARITY_ERR_INT_RAW (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_V 0x1 -#define UART_PARITY_ERR_INT_RAW_S 2 -/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 -#define UART_TXFIFO_EMPTY_INT_RAW_S 1 -/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_V 0x1 -#define UART_RXFIFO_FULL_INT_RAW_S 0 +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when input rxd edge changes more time +s than what reg_active_threshold specifies in light sleeping mode..*/ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (BIT(19)) +#define UART_WAKEUP_INT_RAW_V 0x1 +#define UART_WAKEUP_INT_RAW_S 19 +/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects the configured +at_cmd char..*/ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when detects a clash between transmit +ter and receiver in rs485 mode..*/ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_V 0x1 +#define UART_RS485_CLASH_INT_RAW_S 17 +/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects a data frame er +ror from the echo of transmitter in rs485 mode..*/ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects a parity error +from the echo of transmitter in rs485 mode..*/ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has send out all dat +a in FIFO..*/ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (BIT(14)) +#define UART_TX_DONE_INT_RAW_V 0x1 +#define UART_TX_DONE_INT_RAW_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has kept the shortes +t duration after sending the last data..*/ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter completes sending +NULL characters, after all data in Tx-FIFO are sent..*/ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects a glitch in the + middle of a start bit..*/ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_V 0x1 +#define UART_GLITCH_DET_INT_RAW_S 11 +/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives Xoff char when + uart_sw_flow_con_en is set to 1..*/ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (BIT(10)) +#define UART_SW_XOFF_INT_RAW_V 0x1 +#define UART_SW_XOFF_INT_RAW_S 10 +/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver recevies Xon char when +uart_sw_flow_con_en is set to 1..*/ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (BIT(9)) +#define UART_SW_XON_INT_RAW_V 0x1 +#define UART_SW_XON_INT_RAW_S 9 +/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver takes more time than rx +_tout_thrhd to receive a byte..*/ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects a 0 after the s +top bit..*/ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (BIT(7)) +#define UART_BRK_DET_INT_RAW_V 0x1 +#define UART_BRK_DET_INT_RAW_S 7 +/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects the edge change + of CTSn signal..*/ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (BIT(6)) +#define UART_CTS_CHG_INT_RAW_V 0x1 +#define UART_CTS_CHG_INT_RAW_S 6 +/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects the edge change + of DSRn signal..*/ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (BIT(5)) +#define UART_DSR_CHG_INT_RAW_V 0x1 +#define UART_DSR_CHG_INT_RAW_S 5 +/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives more data than + the FIFO can store..*/ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_V 0x1 +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects a data frame er +ror ..*/ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (BIT(3)) +#define UART_FRM_ERR_INT_RAW_V 0x1 +#define UART_FRM_ERR_INT_RAW_S 3 +/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects a parity error +in the data..*/ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_V 0x1 +#define UART_PARITY_ERR_INT_RAW_S 2 +/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */ +/*description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + less than what txfifo_empty_thrhd specifies ..*/ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives more data than + what rxfifo_full_thrhd specifies..*/ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_V 0x1 +#define UART_RXFIFO_FULL_INT_RAW_S 0 -#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) /* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define UART_WAKEUP_INT_ST (BIT(19)) -#define UART_WAKEUP_INT_ST_M (BIT(19)) -#define UART_WAKEUP_INT_ST_V 0x1 -#define UART_WAKEUP_INT_ST_S 19 +/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set t +o 1..*/ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (BIT(19)) +#define UART_WAKEUP_INT_ST_V 0x1 +#define UART_WAKEUP_INT_ST_S 19 /* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is se +t to 1..*/ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 /* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_CLASH_INT_ST (BIT(17)) -#define UART_RS485_CLASH_INT_ST_M (BIT(17)) -#define UART_RS485_CLASH_INT_ST_V 0x1 -#define UART_RS485_CLASH_INT_ST_S 17 +/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set t +o 1..*/ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (BIT(17)) +#define UART_RS485_CLASH_INT_ST_V 0x1 +#define UART_RS485_CLASH_INT_ST_S 17 /* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_V 0x1 -#define UART_RS485_FRM_ERR_INT_ST_S 16 +/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is se +t to 1..*/ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_V 0x1 +#define UART_RS485_FRM_ERR_INT_ST_S 16 /* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 -#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + set to 1..*/ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 /* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_DONE_INT_ST (BIT(14)) -#define UART_TX_DONE_INT_ST_M (BIT(14)) -#define UART_TX_DONE_INT_ST_V 0x1 -#define UART_TX_DONE_INT_ST_S 14 +/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1..*/ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (BIT(14)) +#define UART_TX_DONE_INT_ST_V 0x1 +#define UART_TX_DONE_INT_ST_S 14 /* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en +a is set to 1..*/ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 /* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_BRK_DONE_INT_ST (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_V 0x1 -#define UART_TX_BRK_DONE_INT_ST_S 12 +/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set t +o 1..*/ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_DONE_INT_ST_S 12 /* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define UART_GLITCH_DET_INT_ST (BIT(11)) -#define UART_GLITCH_DET_INT_ST_M (BIT(11)) -#define UART_GLITCH_DET_INT_ST_V 0x1 -#define UART_GLITCH_DET_INT_ST_S 11 +/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to +1..*/ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (BIT(11)) +#define UART_GLITCH_DET_INT_ST_V 0x1 +#define UART_GLITCH_DET_INT_ST_S 11 /* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_XOFF_INT_ST (BIT(10)) -#define UART_SW_XOFF_INT_ST_M (BIT(10)) -#define UART_SW_XOFF_INT_ST_V 0x1 -#define UART_SW_XOFF_INT_ST_S 10 +/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1..*/ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (BIT(10)) +#define UART_SW_XOFF_INT_ST_V 0x1 +#define UART_SW_XOFF_INT_ST_S 10 /* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_XON_INT_ST (BIT(9)) -#define UART_SW_XON_INT_ST_M (BIT(9)) -#define UART_SW_XON_INT_ST_V 0x1 -#define UART_SW_XON_INT_ST_S 9 +/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1..*/ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (BIT(9)) +#define UART_SW_XON_INT_ST_V 0x1 +#define UART_SW_XON_INT_ST_S 9 /* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_V 0x1 -#define UART_RXFIFO_TOUT_INT_ST_S 8 +/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set t +o 1..*/ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_V 0x1 +#define UART_RXFIFO_TOUT_INT_ST_S 8 /* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define UART_BRK_DET_INT_ST (BIT(7)) -#define UART_BRK_DET_INT_ST_M (BIT(7)) -#define UART_BRK_DET_INT_ST_V 0x1 -#define UART_BRK_DET_INT_ST_S 7 +/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1..*/ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (BIT(7)) +#define UART_BRK_DET_INT_ST_V 0x1 +#define UART_BRK_DET_INT_ST_S 7 /* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define UART_CTS_CHG_INT_ST (BIT(6)) -#define UART_CTS_CHG_INT_ST_M (BIT(6)) -#define UART_CTS_CHG_INT_ST_V 0x1 -#define UART_CTS_CHG_INT_ST_S 6 +/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1..*/ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (BIT(6)) +#define UART_CTS_CHG_INT_ST_V 0x1 +#define UART_CTS_CHG_INT_ST_S 6 /* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UART_DSR_CHG_INT_ST (BIT(5)) -#define UART_DSR_CHG_INT_ST_M (BIT(5)) -#define UART_DSR_CHG_INT_ST_V 0x1 -#define UART_DSR_CHG_INT_ST_S 5 +/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1..*/ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (BIT(5)) +#define UART_DSR_CHG_INT_ST_V 0x1 +#define UART_DSR_CHG_INT_ST_S 5 /* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_OVF_INT_ST (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_V 0x1 -#define UART_RXFIFO_OVF_INT_ST_S 4 +/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to +1..*/ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_V 0x1 +#define UART_RXFIFO_OVF_INT_ST_S 4 /* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UART_FRM_ERR_INT_ST (BIT(3)) -#define UART_FRM_ERR_INT_ST_M (BIT(3)) -#define UART_FRM_ERR_INT_ST_V 0x1 -#define UART_FRM_ERR_INT_ST_S 3 +/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1..*/ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (BIT(3)) +#define UART_FRM_ERR_INT_ST_V 0x1 +#define UART_FRM_ERR_INT_ST_S 3 /* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UART_PARITY_ERR_INT_ST (BIT(2)) -#define UART_PARITY_ERR_INT_ST_M (BIT(2)) -#define UART_PARITY_ERR_INT_ST_V 0x1 -#define UART_PARITY_ERR_INT_ST_S 2 +/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to +1..*/ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (BIT(2)) +#define UART_PARITY_ERR_INT_ST_V 0x1 +#define UART_PARITY_ERR_INT_ST_S 2 /* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 -#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is s +et to 1..*/ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 /* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_FULL_INT_ST (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_V 0x1 -#define UART_RXFIFO_FULL_INT_ST_S 0 +/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set t +o 1..*/ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_V 0x1 +#define UART_RXFIFO_FULL_INT_ST_S 0 -#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) /* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define UART_WAKEUP_INT_ENA (BIT(19)) -#define UART_WAKEUP_INT_ENA_M (BIT(19)) -#define UART_WAKEUP_INT_ENA_V 0x1 -#define UART_WAKEUP_INT_ENA_S 19 +/*description: This is the enable bit for uart_wakeup_int_st register..*/ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (BIT(19)) +#define UART_WAKEUP_INT_ENA_V 0x1 +#define UART_WAKEUP_INT_ENA_S 19 /* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/*description: This is the enable bit for at_cmd_char_det_int_st register..*/ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 /* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_CLASH_INT_ENA (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_V 0x1 -#define UART_RS485_CLASH_INT_ENA_S 17 +/*description: This is the enable bit for rs485_clash_int_st register..*/ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_V 0x1 +#define UART_RS485_CLASH_INT_ENA_S 17 /* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 -#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/*description: This is the enable bit for rs485_parity_err_int_st register..*/ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 /* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 -#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/*description: This is the enable bit for rs485_parity_err_int_st register..*/ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 /* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_DONE_INT_ENA (BIT(14)) -#define UART_TX_DONE_INT_ENA_M (BIT(14)) -#define UART_TX_DONE_INT_ENA_V 0x1 -#define UART_TX_DONE_INT_ENA_S 14 +/*description: This is the enable bit for tx_done_int_st register..*/ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (BIT(14)) +#define UART_TX_DONE_INT_ENA_V 0x1 +#define UART_TX_DONE_INT_ENA_S 14 /* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/*description: This is the enable bit for tx_brk_idle_done_int_st register..*/ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 /* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_V 0x1 -#define UART_TX_BRK_DONE_INT_ENA_S 12 +/*description: This is the enable bit for tx_brk_done_int_st register..*/ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_DONE_INT_ENA_S 12 /* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define UART_GLITCH_DET_INT_ENA (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_V 0x1 -#define UART_GLITCH_DET_INT_ENA_S 11 +/*description: This is the enable bit for glitch_det_int_st register..*/ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_V 0x1 +#define UART_GLITCH_DET_INT_ENA_S 11 /* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_XOFF_INT_ENA (BIT(10)) -#define UART_SW_XOFF_INT_ENA_M (BIT(10)) -#define UART_SW_XOFF_INT_ENA_V 0x1 -#define UART_SW_XOFF_INT_ENA_S 10 +/*description: This is the enable bit for sw_xoff_int_st register..*/ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (BIT(10)) +#define UART_SW_XOFF_INT_ENA_V 0x1 +#define UART_SW_XOFF_INT_ENA_S 10 /* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_XON_INT_ENA (BIT(9)) -#define UART_SW_XON_INT_ENA_M (BIT(9)) -#define UART_SW_XON_INT_ENA_V 0x1 -#define UART_SW_XON_INT_ENA_S 9 +/*description: This is the enable bit for sw_xon_int_st register..*/ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (BIT(9)) +#define UART_SW_XON_INT_ENA_V 0x1 +#define UART_SW_XON_INT_ENA_S 9 /* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 -#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/*description: This is the enable bit for rxfifo_tout_int_st register..*/ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 /* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define UART_BRK_DET_INT_ENA (BIT(7)) -#define UART_BRK_DET_INT_ENA_M (BIT(7)) -#define UART_BRK_DET_INT_ENA_V 0x1 -#define UART_BRK_DET_INT_ENA_S 7 +/*description: This is the enable bit for brk_det_int_st register..*/ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (BIT(7)) +#define UART_BRK_DET_INT_ENA_V 0x1 +#define UART_BRK_DET_INT_ENA_S 7 /* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define UART_CTS_CHG_INT_ENA (BIT(6)) -#define UART_CTS_CHG_INT_ENA_M (BIT(6)) -#define UART_CTS_CHG_INT_ENA_V 0x1 -#define UART_CTS_CHG_INT_ENA_S 6 +/*description: This is the enable bit for cts_chg_int_st register..*/ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (BIT(6)) +#define UART_CTS_CHG_INT_ENA_V 0x1 +#define UART_CTS_CHG_INT_ENA_S 6 /* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UART_DSR_CHG_INT_ENA (BIT(5)) -#define UART_DSR_CHG_INT_ENA_M (BIT(5)) -#define UART_DSR_CHG_INT_ENA_V 0x1 -#define UART_DSR_CHG_INT_ENA_S 5 +/*description: This is the enable bit for dsr_chg_int_st register..*/ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (BIT(5)) +#define UART_DSR_CHG_INT_ENA_V 0x1 +#define UART_DSR_CHG_INT_ENA_S 5 /* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_V 0x1 -#define UART_RXFIFO_OVF_INT_ENA_S 4 +/*description: This is the enable bit for rxfifo_ovf_int_st register..*/ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_V 0x1 +#define UART_RXFIFO_OVF_INT_ENA_S 4 /* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_FRM_ERR_INT_ENA_M (BIT(3)) -#define UART_FRM_ERR_INT_ENA_V 0x1 -#define UART_FRM_ERR_INT_ENA_S 3 +/*description: This is the enable bit for frm_err_int_st register..*/ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (BIT(3)) +#define UART_FRM_ERR_INT_ENA_V 0x1 +#define UART_FRM_ERR_INT_ENA_S 3 /* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_V 0x1 -#define UART_PARITY_ERR_INT_ENA_S 2 +/*description: This is the enable bit for parity_err_int_st register..*/ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_V 0x1 +#define UART_PARITY_ERR_INT_ENA_S 2 /* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 -#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/*description: This is the enable bit for txfifo_empty_int_st register..*/ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 /* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_V 0x1 -#define UART_RXFIFO_FULL_INT_ENA_S 0 +/*description: This is the enable bit for rxfifo_full_int_st register..*/ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_V 0x1 +#define UART_RXFIFO_FULL_INT_ENA_S 0 -#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) -/* UART_WAKEUP_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define UART_WAKEUP_INT_CLR (BIT(19)) -#define UART_WAKEUP_INT_CLR_M (BIT(19)) -#define UART_WAKEUP_INT_CLR_V 0x1 -#define UART_WAKEUP_INT_CLR_S 19 -/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 -/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_CLASH_INT_CLR (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_V 0x1 -#define UART_RS485_CLASH_INT_CLR_S 17 -/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 -#define UART_RS485_FRM_ERR_INT_CLR_S 16 -/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 -#define UART_RS485_PARITY_ERR_INT_CLR_S 15 -/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_DONE_INT_CLR (BIT(14)) -#define UART_TX_DONE_INT_CLR_M (BIT(14)) -#define UART_TX_DONE_INT_CLR_V 0x1 -#define UART_TX_DONE_INT_CLR_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 -/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_V 0x1 -#define UART_TX_BRK_DONE_INT_CLR_S 12 -/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define UART_GLITCH_DET_INT_CLR (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_V 0x1 -#define UART_GLITCH_DET_INT_CLR_S 11 -/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_XOFF_INT_CLR (BIT(10)) -#define UART_SW_XOFF_INT_CLR_M (BIT(10)) -#define UART_SW_XOFF_INT_CLR_V 0x1 -#define UART_SW_XOFF_INT_CLR_S 10 -/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_XON_INT_CLR (BIT(9)) -#define UART_SW_XON_INT_CLR_M (BIT(9)) -#define UART_SW_XON_INT_CLR_V 0x1 -#define UART_SW_XON_INT_CLR_S 9 -/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 -#define UART_RXFIFO_TOUT_INT_CLR_S 8 -/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define UART_BRK_DET_INT_CLR (BIT(7)) -#define UART_BRK_DET_INT_CLR_M (BIT(7)) -#define UART_BRK_DET_INT_CLR_V 0x1 -#define UART_BRK_DET_INT_CLR_S 7 -/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define UART_CTS_CHG_INT_CLR (BIT(6)) -#define UART_CTS_CHG_INT_CLR_M (BIT(6)) -#define UART_CTS_CHG_INT_CLR_V 0x1 -#define UART_CTS_CHG_INT_CLR_S 6 -/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UART_DSR_CHG_INT_CLR (BIT(5)) -#define UART_DSR_CHG_INT_CLR_M (BIT(5)) -#define UART_DSR_CHG_INT_CLR_V 0x1 -#define UART_DSR_CHG_INT_CLR_S 5 -/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_V 0x1 -#define UART_RXFIFO_OVF_INT_CLR_S 4 -/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UART_FRM_ERR_INT_CLR (BIT(3)) -#define UART_FRM_ERR_INT_CLR_M (BIT(3)) -#define UART_FRM_ERR_INT_CLR_V 0x1 -#define UART_FRM_ERR_INT_CLR_S 3 -/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UART_PARITY_ERR_INT_CLR (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_V 0x1 -#define UART_PARITY_ERR_INT_CLR_S 2 -/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 -#define UART_TXFIFO_EMPTY_INT_CLR_S 1 -/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_V 0x1 -#define UART_RXFIFO_FULL_INT_CLR_S 0 +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear the uart_wakeup_int_raw interrupt..*/ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (BIT(19)) +#define UART_WAKEUP_INT_CLR_V 0x1 +#define UART_WAKEUP_INT_CLR_S 19 +/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt..*/ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_clash_int_raw interrupt..*/ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_V 0x1 +#define UART_RS485_CLASH_INT_CLR_S 17 +/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt..*/ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt..*/ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_done_int_raw interrupt..*/ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (BIT(14)) +#define UART_TX_DONE_INT_CLR_V 0x1 +#define UART_TX_DONE_INT_CLR_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt..*/ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_done_int_raw interrupt...*/ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the glitch_det_int_raw interrupt..*/ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_V 0x1 +#define UART_GLITCH_DET_INT_CLR_S 11 +/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xoff_int_raw interrupt..*/ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (BIT(10)) +#define UART_SW_XOFF_INT_CLR_V 0x1 +#define UART_SW_XOFF_INT_CLR_S 10 +/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt..*/ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (BIT(9)) +#define UART_SW_XON_INT_CLR_V 0x1 +#define UART_SW_XON_INT_CLR_S 9 +/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt..*/ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the brk_det_int_raw interrupt..*/ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (BIT(7)) +#define UART_BRK_DET_INT_CLR_V 0x1 +#define UART_BRK_DET_INT_CLR_S 7 +/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the cts_chg_int_raw interrupt..*/ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (BIT(6)) +#define UART_CTS_CHG_INT_CLR_V 0x1 +#define UART_CTS_CHG_INT_CLR_S 6 +/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the dsr_chg_int_raw interrupt..*/ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (BIT(5)) +#define UART_DSR_CHG_INT_CLR_V 0x1 +#define UART_DSR_CHG_INT_CLR_S 5 +/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt..*/ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_V 0x1 +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear frm_err_int_raw interrupt..*/ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (BIT(3)) +#define UART_FRM_ERR_INT_CLR_V 0x1 +#define UART_FRM_ERR_INT_CLR_S 3 +/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear parity_err_int_raw interrupt..*/ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_V 0x1 +#define UART_PARITY_ERR_INT_CLR_S 2 +/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear txfifo_empty_int_raw interrupt..*/ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int_raw interrupt..*/ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_V 0x1 +#define UART_RXFIFO_FULL_INT_CLR_S 0 -#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) /* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: */ -#define UART_CLKDIV_FRAG 0x0000000F -#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V) << (UART_CLKDIV_FRAG_S)) -#define UART_CLKDIV_FRAG_V 0xF -#define UART_CLKDIV_FRAG_S 20 -/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2B6 ; */ -/*description: */ -#define UART_CLKDIV 0x00000FFF -#define UART_CLKDIV_M ((UART_CLKDIV_V) << (UART_CLKDIV_S)) -#define UART_CLKDIV_V 0xFFF -#define UART_CLKDIV_S 0 +/*description: The decimal part of the frequency divider factor..*/ +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_V 0xF +#define UART_CLKDIV_FRAG_S 20 +/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2b6 ; */ +/*description: The integral part of the frequency divider factor..*/ +#define UART_CLKDIV 0x00000FFF +#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) +#define UART_CLKDIV_V 0xFFF +#define UART_CLKDIV_S 0 -#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) /* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define UART_GLITCH_FILT_EN (BIT(8)) -#define UART_GLITCH_FILT_EN_M (BIT(8)) -#define UART_GLITCH_FILT_EN_V 0x1 -#define UART_GLITCH_FILT_EN_S 8 +/*description: Set this bit to enable Rx signal filter..*/ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (BIT(8)) +#define UART_GLITCH_FILT_EN_V 0x1 +#define UART_GLITCH_FILT_EN_S 8 /* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */ -/*description: */ -#define UART_GLITCH_FILT 0x000000FF -#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V) << (UART_GLITCH_FILT_S)) -#define UART_GLITCH_FILT_V 0xFF -#define UART_GLITCH_FILT_S 0 +/*description: when input pulse width is lower than this value, the pulse is ignored..*/ +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_V 0xFF +#define UART_GLITCH_FILT_S 0 -#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) /* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */ -/*description: */ -#define UART_TXD (BIT(31)) -#define UART_TXD_M (BIT(31)) -#define UART_TXD_V 0x1 -#define UART_TXD_S 31 +/*description: This bit represents the level of the internal uart txd signal..*/ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (BIT(31)) +#define UART_TXD_V 0x1 +#define UART_TXD_S 31 /* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define UART_RTSN (BIT(30)) -#define UART_RTSN_M (BIT(30)) -#define UART_RTSN_V 0x1 -#define UART_RTSN_S 30 +/*description: This bit represents the level of the internal uart rts signal..*/ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (BIT(30)) +#define UART_RTSN_V 0x1 +#define UART_RTSN_S 30 /* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define UART_DTRN (BIT(29)) -#define UART_DTRN_M (BIT(29)) -#define UART_DTRN_V 0x1 -#define UART_DTRN_S 29 +/*description: This bit represents the level of the internal uart dtr signal..*/ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (BIT(29)) +#define UART_DTRN_V 0x1 +#define UART_DTRN_S 29 /* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */ -/*description: */ -#define UART_TXFIFO_CNT 0x000003FF -#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V) << (UART_TXFIFO_CNT_S)) -#define UART_TXFIFO_CNT_V 0x3FF -#define UART_TXFIFO_CNT_S 16 +/*description: Stores the byte number of data in Tx-FIFO..*/ +#define UART_TXFIFO_CNT 0x000003FF +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_V 0x3FF +#define UART_TXFIFO_CNT_S 16 /* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */ -/*description: */ -#define UART_RXD (BIT(15)) -#define UART_RXD_M (BIT(15)) -#define UART_RXD_V 0x1 -#define UART_RXD_S 15 +/*description: This register represent the level value of the internal uart rxd signal..*/ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (BIT(15)) +#define UART_RXD_V 0x1 +#define UART_RXD_S 15 /* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define UART_CTSN (BIT(14)) -#define UART_CTSN_M (BIT(14)) -#define UART_CTSN_V 0x1 -#define UART_CTSN_S 14 +/*description: This register represent the level value of the internal uart cts signal..*/ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (BIT(14)) +#define UART_CTSN_V 0x1 +#define UART_CTSN_S 14 /* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define UART_DSRN (BIT(13)) -#define UART_DSRN_M (BIT(13)) -#define UART_DSRN_V 0x1 -#define UART_DSRN_S 13 +/*description: The register represent the level value of the internal uart dsr signal..*/ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (BIT(13)) +#define UART_DSRN_V 0x1 +#define UART_DSRN_S 13 /* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: */ -#define UART_RXFIFO_CNT 0x000003FF -#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V) << (UART_RXFIFO_CNT_S)) -#define UART_RXFIFO_CNT_V 0x3FF -#define UART_RXFIFO_CNT_S 0 +/*description: Stores the byte number of valid data in Rx-FIFO..*/ +#define UART_RXFIFO_CNT 0x000003FF +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_V 0x3FF +#define UART_RXFIFO_CNT_S 0 -#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) /* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */ -/*description: */ -#define UART_MEM_CLK_EN (BIT(28)) -#define UART_MEM_CLK_EN_M (BIT(28)) -#define UART_MEM_CLK_EN_V 0x1 -#define UART_MEM_CLK_EN_S 28 +/*description: UART memory clock gate enable signal..*/ +#define UART_MEM_CLK_EN (BIT(28)) +#define UART_MEM_CLK_EN_M (BIT(28)) +#define UART_MEM_CLK_EN_V 0x1 +#define UART_MEM_CLK_EN_S 28 /* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define UART_AUTOBAUD_EN (BIT(27)) -#define UART_AUTOBAUD_EN_M (BIT(27)) -#define UART_AUTOBAUD_EN_V 0x1 -#define UART_AUTOBAUD_EN_S 27 +/*description: This is the enable bit for detecting baudrate..*/ +#define UART_AUTOBAUD_EN (BIT(27)) +#define UART_AUTOBAUD_EN_M (BIT(27)) +#define UART_AUTOBAUD_EN_V 0x1 +#define UART_AUTOBAUD_EN_S 27 /* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define UART_ERR_WR_MASK (BIT(26)) -#define UART_ERR_WR_MASK_M (BIT(26)) -#define UART_ERR_WR_MASK_V 0x1 -#define UART_ERR_WR_MASK_S 26 +/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver s +tores the data even if the received data is wrong..*/ +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (BIT(26)) +#define UART_ERR_WR_MASK_V 0x1 +#define UART_ERR_WR_MASK_S 26 /* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: */ -#define UART_CLK_EN (BIT(25)) -#define UART_CLK_EN_M (BIT(25)) -#define UART_CLK_EN_V 0x1 -#define UART_CLK_EN_S 25 +/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri +tes registers..*/ +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (BIT(25)) +#define UART_CLK_EN_V 0x1 +#define UART_CLK_EN_S 25 /* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: */ -#define UART_DTR_INV (BIT(24)) -#define UART_DTR_INV_M (BIT(24)) -#define UART_DTR_INV_V 0x1 -#define UART_DTR_INV_S 24 +/*description: Set this bit to inverse the level value of uart dtr signal..*/ +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (BIT(24)) +#define UART_DTR_INV_V 0x1 +#define UART_DTR_INV_S 24 /* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: */ -#define UART_RTS_INV (BIT(23)) -#define UART_RTS_INV_M (BIT(23)) -#define UART_RTS_INV_V 0x1 -#define UART_RTS_INV_S 23 +/*description: Set this bit to inverse the level value of uart rts signal..*/ +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (BIT(23)) +#define UART_RTS_INV_V 0x1 +#define UART_RTS_INV_S 23 /* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: */ -#define UART_TXD_INV (BIT(22)) -#define UART_TXD_INV_M (BIT(22)) -#define UART_TXD_INV_V 0x1 -#define UART_TXD_INV_S 22 +/*description: Set this bit to inverse the level value of uart txd signal..*/ +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (BIT(22)) +#define UART_TXD_INV_V 0x1 +#define UART_TXD_INV_S 22 /* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: */ -#define UART_DSR_INV (BIT(21)) -#define UART_DSR_INV_M (BIT(21)) -#define UART_DSR_INV_V 0x1 -#define UART_DSR_INV_S 21 +/*description: Set this bit to inverse the level value of uart dsr signal..*/ +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (BIT(21)) +#define UART_DSR_INV_V 0x1 +#define UART_DSR_INV_S 21 /* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: */ -#define UART_CTS_INV (BIT(20)) -#define UART_CTS_INV_M (BIT(20)) -#define UART_CTS_INV_V 0x1 -#define UART_CTS_INV_S 20 +/*description: Set this bit to inverse the level value of uart cts signal..*/ +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (BIT(20)) +#define UART_CTS_INV_V 0x1 +#define UART_CTS_INV_S 20 /* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: */ -#define UART_RXD_INV (BIT(19)) -#define UART_RXD_INV_M (BIT(19)) -#define UART_RXD_INV_V 0x1 -#define UART_RXD_INV_S 19 +/*description: Set this bit to inverse the level value of uart rxd signal..*/ +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (BIT(19)) +#define UART_RXD_INV_V 0x1 +#define UART_RXD_INV_S 19 /* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: */ -#define UART_TXFIFO_RST (BIT(18)) -#define UART_TXFIFO_RST_M (BIT(18)) -#define UART_TXFIFO_RST_V 0x1 -#define UART_TXFIFO_RST_S 18 +/*description: Set this bit to reset the uart transmit-FIFO..*/ +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (BIT(18)) +#define UART_TXFIFO_RST_V 0x1 +#define UART_TXFIFO_RST_S 18 /* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: */ -#define UART_RXFIFO_RST (BIT(17)) -#define UART_RXFIFO_RST_M (BIT(17)) -#define UART_RXFIFO_RST_V 0x1 -#define UART_RXFIFO_RST_S 17 +/*description: Set this bit to reset the uart receive-FIFO..*/ +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (BIT(17)) +#define UART_RXFIFO_RST_V 0x1 +#define UART_RXFIFO_RST_S 17 /* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: */ -#define UART_IRDA_EN (BIT(16)) -#define UART_IRDA_EN_M (BIT(16)) -#define UART_IRDA_EN_V 0x1 -#define UART_IRDA_EN_S 16 +/*description: Set this bit to enable IrDA protocol..*/ +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (BIT(16)) +#define UART_IRDA_EN_V 0x1 +#define UART_IRDA_EN_S 16 /* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_FLOW_EN (BIT(15)) -#define UART_TX_FLOW_EN_M (BIT(15)) -#define UART_TX_FLOW_EN_V 0x1 -#define UART_TX_FLOW_EN_S 15 +/*description: Set this bit to enable flow control function for transmitter..*/ +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (BIT(15)) +#define UART_TX_FLOW_EN_V 0x1 +#define UART_TX_FLOW_EN_S 15 /* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define UART_LOOPBACK (BIT(14)) -#define UART_LOOPBACK_M (BIT(14)) -#define UART_LOOPBACK_V 0x1 -#define UART_LOOPBACK_S 14 +/*description: Set this bit to enable uart loopback test mode..*/ +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (BIT(14)) +#define UART_LOOPBACK_V 0x1 +#define UART_LOOPBACK_S 14 /* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define UART_IRDA_RX_INV (BIT(13)) -#define UART_IRDA_RX_INV_M (BIT(13)) -#define UART_IRDA_RX_INV_V 0x1 -#define UART_IRDA_RX_INV_S 13 +/*description: Set this bit to invert the level of IrDA receiver..*/ +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (BIT(13)) +#define UART_IRDA_RX_INV_V 0x1 +#define UART_IRDA_RX_INV_S 13 /* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define UART_IRDA_TX_INV (BIT(12)) -#define UART_IRDA_TX_INV_M (BIT(12)) -#define UART_IRDA_TX_INV_V 0x1 -#define UART_IRDA_TX_INV_S 12 +/*description: Set this bit to invert the level of IrDA transmitter..*/ +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (BIT(12)) +#define UART_IRDA_TX_INV_V 0x1 +#define UART_IRDA_TX_INV_S 12 /* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define UART_IRDA_WCTL (BIT(11)) -#define UART_IRDA_WCTL_M (BIT(11)) -#define UART_IRDA_WCTL_V 0x1 -#define UART_IRDA_WCTL_S 11 +/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA tr +ansmitter's 11th bit to 0..*/ +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (BIT(11)) +#define UART_IRDA_WCTL_V 0x1 +#define UART_IRDA_WCTL_S 11 /* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define UART_IRDA_TX_EN (BIT(10)) -#define UART_IRDA_TX_EN_M (BIT(10)) -#define UART_IRDA_TX_EN_V 0x1 -#define UART_IRDA_TX_EN_S 10 +/*description: This is the start enable bit for IrDA transmitter..*/ +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (BIT(10)) +#define UART_IRDA_TX_EN_V 0x1 +#define UART_IRDA_TX_EN_S 10 /* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define UART_IRDA_DPLX (BIT(9)) -#define UART_IRDA_DPLX_M (BIT(9)) -#define UART_IRDA_DPLX_V 0x1 -#define UART_IRDA_DPLX_S 9 +/*description: Set this bit to enable IrDA loopback mode..*/ +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (BIT(9)) +#define UART_IRDA_DPLX_V 0x1 +#define UART_IRDA_DPLX_S 9 /* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define UART_TXD_BRK (BIT(8)) -#define UART_TXD_BRK_M (BIT(8)) -#define UART_TXD_BRK_V 0x1 -#define UART_TXD_BRK_S 8 +/*description: Set this bit to enbale transmitter to send NULL when the process of sending dat +a is done..*/ +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (BIT(8)) +#define UART_TXD_BRK_V 0x1 +#define UART_TXD_BRK_S 8 /* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_DTR (BIT(7)) -#define UART_SW_DTR_M (BIT(7)) -#define UART_SW_DTR_V 0x1 -#define UART_SW_DTR_S 7 +/*description: This register is used to configure the software dtr signal which is used in soft +ware flow control..*/ +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (BIT(7)) +#define UART_SW_DTR_V 0x1 +#define UART_SW_DTR_S 7 /* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_RTS (BIT(6)) -#define UART_SW_RTS_M (BIT(6)) -#define UART_SW_RTS_V 0x1 -#define UART_SW_RTS_S 6 +/*description: This register is used to configure the software rts signal which is used in soft +ware flow control..*/ +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (BIT(6)) +#define UART_SW_RTS_V 0x1 +#define UART_SW_RTS_S 6 /* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ -/*description: */ -#define UART_STOP_BIT_NUM 0x00000003 -#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V) << (UART_STOP_BIT_NUM_S)) -#define UART_STOP_BIT_NUM_V 0x3 -#define UART_STOP_BIT_NUM_S 4 +/*description: This register is used to set the length of stop bit..*/ +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_V 0x3 +#define UART_STOP_BIT_NUM_S 4 /* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ -/*description: */ -#define UART_BIT_NUM 0x00000003 -#define UART_BIT_NUM_M ((UART_BIT_NUM_V) << (UART_BIT_NUM_S)) -#define UART_BIT_NUM_V 0x3 -#define UART_BIT_NUM_S 2 +/*description: This register is used to set the length of data..*/ +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) +#define UART_BIT_NUM_V 0x3 +#define UART_BIT_NUM_S 2 /* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UART_PARITY_EN (BIT(1)) -#define UART_PARITY_EN_M (BIT(1)) -#define UART_PARITY_EN_V 0x1 -#define UART_PARITY_EN_S 1 +/*description: Set this bit to enable uart parity check..*/ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (BIT(1)) +#define UART_PARITY_EN_V 0x1 +#define UART_PARITY_EN_S 1 /* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UART_PARITY (BIT(0)) -#define UART_PARITY_M (BIT(0)) -#define UART_PARITY_V 0x1 -#define UART_PARITY_S 0 +/*description: This register is used to configure the parity check mode..*/ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (BIT(0)) +#define UART_PARITY_V 0x1 +#define UART_PARITY_S 0 -#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) /* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define UART_RX_TOUT_EN (BIT(21)) -#define UART_RX_TOUT_EN_M (BIT(21)) -#define UART_RX_TOUT_EN_V 0x1 -#define UART_RX_TOUT_EN_S 21 +/*description: This is the enble bit for uart receiver's timeout function..*/ +#define UART_RX_TOUT_EN (BIT(21)) +#define UART_RX_TOUT_EN_M (BIT(21)) +#define UART_RX_TOUT_EN_V 0x1 +#define UART_RX_TOUT_EN_S 21 /* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define UART_RX_FLOW_EN (BIT(20)) -#define UART_RX_FLOW_EN_M (BIT(20)) -#define UART_RX_FLOW_EN_V 0x1 -#define UART_RX_FLOW_EN_S 20 +/*description: This is the flow enable bit for UART receiver..*/ +#define UART_RX_FLOW_EN (BIT(20)) +#define UART_RX_FLOW_EN_M (BIT(20)) +#define UART_RX_FLOW_EN_V 0x1 +#define UART_RX_FLOW_EN_S 20 /* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define UART_RX_TOUT_FLOW_DIS (BIT(19)) -#define UART_RX_TOUT_FLOW_DIS_M (BIT(19)) -#define UART_RX_TOUT_FLOW_DIS_V 0x1 -#define UART_RX_TOUT_FLOW_DIS_S 19 +/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works..*/ +#define UART_RX_TOUT_FLOW_DIS (BIT(19)) +#define UART_RX_TOUT_FLOW_DIS_M (BIT(19)) +#define UART_RX_TOUT_FLOW_DIS_V 0x1 +#define UART_RX_TOUT_FLOW_DIS_S 19 /* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: */ -#define UART_DIS_RX_DAT_OVF (BIT(18)) -#define UART_DIS_RX_DAT_OVF_M (BIT(18)) -#define UART_DIS_RX_DAT_OVF_V 0x1 -#define UART_DIS_RX_DAT_OVF_S 18 +/*description: Disable UART Rx data overflow detect. .*/ +#define UART_DIS_RX_DAT_OVF (BIT(18)) +#define UART_DIS_RX_DAT_OVF_M (BIT(18)) +#define UART_DIS_RX_DAT_OVF_V 0x1 +#define UART_DIS_RX_DAT_OVF_S 18 /* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */ -/*description: */ -#define UART_TXFIFO_EMPTY_THRHD 0x000001FF -#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V) << (UART_TXFIFO_EMPTY_THRHD_S)) -#define UART_TXFIFO_EMPTY_THRHD_V 0x1FF -#define UART_TXFIFO_EMPTY_THRHD_S 9 +/*description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is le +ss than this register value..*/ +#define UART_TXFIFO_EMPTY_THRHD 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_V 0x1FF +#define UART_TXFIFO_EMPTY_THRHD_S 9 /* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */ -/*description: */ -#define UART_RXFIFO_FULL_THRHD 0x000001FF -#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V) << (UART_RXFIFO_FULL_THRHD_S)) -#define UART_RXFIFO_FULL_THRHD_V 0x1FF -#define UART_RXFIFO_FULL_THRHD_S 0 +/*description: It will produce rxfifo_full_int interrupt when receiver receives more data than +this register value..*/ +#define UART_RXFIFO_FULL_THRHD 0x000001FF +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_V 0x1FF +#define UART_RXFIFO_FULL_THRHD_S 0 -#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) -/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: */ -#define UART_LOWPULSE_MIN_CNT 0x00000FFF -#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V) << (UART_LOWPULSE_MIN_CNT_S)) -#define UART_LOWPULSE_MIN_CNT_V 0xFFF -#define UART_LOWPULSE_MIN_CNT_S 0 +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) +/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */ +/*description: This register stores the value of the minimum duration time of the low level pul +se. It is used in baud rate-detect process..*/ +#define UART_LOWPULSE_MIN_CNT 0x00000FFF +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_V 0xFFF +#define UART_LOWPULSE_MIN_CNT_S 0 -#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) -/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: */ -#define UART_HIGHPULSE_MIN_CNT 0x00000FFF -#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V) << (UART_HIGHPULSE_MIN_CNT_S)) -#define UART_HIGHPULSE_MIN_CNT_V 0xFFF -#define UART_HIGHPULSE_MIN_CNT_S 0 +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) +/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */ +/*description: This register stores the value of the maxinum duration time for the high level +pulse. It is used in baud rate-detect process..*/ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFF +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_V 0xFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 -#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) /* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: */ -#define UART_RXD_EDGE_CNT 0x000003FF -#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V) << (UART_RXD_EDGE_CNT_S)) -#define UART_RXD_EDGE_CNT_V 0x3FF -#define UART_RXD_EDGE_CNT_S 0 +/*description: This register stores the count of rxd edge change. It is used in baud rate-detec +t process..*/ +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_V 0x3FF +#define UART_RXD_EDGE_CNT_S 0 -#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) -/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UART_SEND_XOFF (BIT(5)) -#define UART_SEND_XOFF_M (BIT(5)) -#define UART_SEND_XOFF_V 0x1 -#define UART_SEND_XOFF_S 5 -/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UART_SEND_XON (BIT(4)) -#define UART_SEND_XON_M (BIT(4)) -#define UART_SEND_XON_V 0x1 -#define UART_SEND_XON_S 4 +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) +/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to send Xoff char. It is cleared by hardware automatically..*/ +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (BIT(5)) +#define UART_SEND_XOFF_V 0x1 +#define UART_SEND_XOFF_S 5 +/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to send Xon char. It is cleared by hardware automatically..*/ +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (BIT(4)) +#define UART_SEND_XON_V 0x1 +#define UART_SEND_XON_S 4 /* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UART_FORCE_XOFF (BIT(3)) -#define UART_FORCE_XOFF_M (BIT(3)) -#define UART_FORCE_XOFF_V 0x1 -#define UART_FORCE_XOFF_S 3 +/*description: Set this bit to stop the transmitter from sending data..*/ +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (BIT(3)) +#define UART_FORCE_XOFF_V 0x1 +#define UART_FORCE_XOFF_S 3 /* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UART_FORCE_XON (BIT(2)) -#define UART_FORCE_XON_M (BIT(2)) -#define UART_FORCE_XON_V 0x1 -#define UART_FORCE_XON_S 2 +/*description: Set this bit to enable the transmitter to go on sending data..*/ +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (BIT(2)) +#define UART_FORCE_XON_V 0x1 +#define UART_FORCE_XON_S 2 /* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UART_XONOFF_DEL (BIT(1)) -#define UART_XONOFF_DEL_M (BIT(1)) -#define UART_XONOFF_DEL_V 0x1 -#define UART_XONOFF_DEL_S 1 +/*description: Set this bit to remove flow control char from the received data..*/ +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (BIT(1)) +#define UART_XONOFF_DEL_V 0x1 +#define UART_XONOFF_DEL_S 1 /* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UART_SW_FLOW_CON_EN (BIT(0)) -#define UART_SW_FLOW_CON_EN_M (BIT(0)) -#define UART_SW_FLOW_CON_EN_V 0x1 -#define UART_SW_FLOW_CON_EN_S 0 +/*description: Set this bit to enable software flow control. It is used with register sw_xon or + sw_xoff..*/ +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (BIT(0)) +#define UART_SW_FLOW_CON_EN_V 0x1 +#define UART_SW_FLOW_CON_EN_S 0 -#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) /* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ -/*description: */ -#define UART_ACTIVE_THRESHOLD 0x000003FF -#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V) << (UART_ACTIVE_THRESHOLD_S)) -#define UART_ACTIVE_THRESHOLD_V 0x3FF -#define UART_ACTIVE_THRESHOLD_S 0 +/*description: The uart is activated from light sleeping mode when the input rxd edge changes m +ore times than this register value..*/ +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_V 0x3FF +#define UART_ACTIVE_THRESHOLD_S 0 -#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3C) +#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3C) /* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */ -/*description: */ -#define UART_XOFF_CHAR 0x000000FF -#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V) << (UART_XOFF_CHAR_S)) -#define UART_XOFF_CHAR_V 0xFF -#define UART_XOFF_CHAR_S 9 +/*description: This register stores the Xoff flow control char..*/ +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_V 0xFF +#define UART_XOFF_CHAR_S 9 /* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */ -/*description: */ -#define UART_XOFF_THRESHOLD 0x000001FF -#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V) << (UART_XOFF_THRESHOLD_S)) -#define UART_XOFF_THRESHOLD_V 0x1FF -#define UART_XOFF_THRESHOLD_S 0 +/*description: When the data amount in Rx-FIFO is more than this register value with uart_sw_fl +ow_con_en set to 1, it will send a Xoff char..*/ +#define UART_XOFF_THRESHOLD 0x000001FF +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_V 0x1FF +#define UART_XOFF_THRESHOLD_S 0 -#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) /* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */ -/*description: */ -#define UART_XON_CHAR 0x000000FF -#define UART_XON_CHAR_M ((UART_XON_CHAR_V) << (UART_XON_CHAR_S)) -#define UART_XON_CHAR_V 0xFF -#define UART_XON_CHAR_S 9 +/*description: This register stores the Xon flow control char..*/ +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) +#define UART_XON_CHAR_V 0xFF +#define UART_XON_CHAR_S 9 /* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: */ -#define UART_XON_THRESHOLD 0x000001FF -#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V) << (UART_XON_THRESHOLD_S)) -#define UART_XON_THRESHOLD_V 0x1FF -#define UART_XON_THRESHOLD_S 0 +/*description: When the data amount in Rx-FIFO is less than this register value with uart_sw_fl +ow_con_en set to 1, it will send a Xon char..*/ +#define UART_XON_THRESHOLD 0x000001FF +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_V 0x1FF +#define UART_XON_THRESHOLD_S 0 -#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44) +#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44) /* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */ -/*description: */ -#define UART_TX_BRK_NUM 0x000000FF -#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V) << (UART_TX_BRK_NUM_S)) -#define UART_TX_BRK_NUM_V 0xFF -#define UART_TX_BRK_NUM_S 0 +/*description: This register is used to configure the number of 0 to be sent after the process +of sending data is done. It is active when txd_brk is set to 1..*/ +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_V 0xFF +#define UART_TX_BRK_NUM_S 0 -#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48) +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48) /* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ -/*description: */ -#define UART_TX_IDLE_NUM 0x000003FF -#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V) << (UART_TX_IDLE_NUM_S)) -#define UART_TX_IDLE_NUM_V 0x3FF -#define UART_TX_IDLE_NUM_S 10 +/*description: This register is used to configure the duration time between transfers..*/ +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_V 0x3FF +#define UART_TX_IDLE_NUM_S 10 /* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ -/*description: */ -#define UART_RX_IDLE_THRHD 0x000003FF -#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V) << (UART_RX_IDLE_THRHD_S)) -#define UART_RX_IDLE_THRHD_V 0x3FF -#define UART_RX_IDLE_THRHD_S 0 +/*description: It will produce frame end signal when receiver takes more time to receive one by +te data than this register value..*/ +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_V 0x3FF +#define UART_RX_IDLE_THRHD_S 0 -#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4c) +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4C) /* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ -/*description: */ -#define UART_RS485_TX_DLY_NUM 0x0000000F -#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V) << (UART_RS485_TX_DLY_NUM_S)) -#define UART_RS485_TX_DLY_NUM_V 0xF -#define UART_RS485_TX_DLY_NUM_S 6 +/*description: This register is used to delay the transmitter's internal data signal..*/ +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_V 0xF +#define UART_RS485_TX_DLY_NUM_S 6 /* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_RX_DLY_NUM (BIT(5)) -#define UART_RS485_RX_DLY_NUM_M (BIT(5)) -#define UART_RS485_RX_DLY_NUM_V 0x1 -#define UART_RS485_RX_DLY_NUM_S 5 +/*description: This register is used to delay the receiver's internal data signal..*/ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (BIT(5)) +#define UART_RS485_RX_DLY_NUM_V 0x1 +#define UART_RS485_RX_DLY_NUM_S 5 /* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485RXBY_TX_EN (BIT(4)) -#define UART_RS485RXBY_TX_EN_M (BIT(4)) -#define UART_RS485RXBY_TX_EN_V 0x1 -#define UART_RS485RXBY_TX_EN_S 4 +/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. .*/ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (BIT(4)) +#define UART_RS485RXBY_TX_EN_V 0x1 +#define UART_RS485RXBY_TX_EN_S 4 /* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485TX_RX_EN (BIT(3)) -#define UART_RS485TX_RX_EN_M (BIT(3)) -#define UART_RS485TX_RX_EN_V 0x1 -#define UART_RS485TX_RX_EN_S 3 +/*description: Set this bit to enable receiver could receive data when the transmitter is trans +mitting data in rs485 mode. .*/ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (BIT(3)) +#define UART_RS485TX_RX_EN_V 0x1 +#define UART_RS485TX_RX_EN_S 3 /* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UART_DL1_EN (BIT(2)) -#define UART_DL1_EN_M (BIT(2)) -#define UART_DL1_EN_V 0x1 -#define UART_DL1_EN_S 2 +/*description: Set this bit to delay the stop bit by 1 bit..*/ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (BIT(2)) +#define UART_DL1_EN_V 0x1 +#define UART_DL1_EN_S 2 /* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UART_DL0_EN (BIT(1)) -#define UART_DL0_EN_M (BIT(1)) -#define UART_DL0_EN_V 0x1 -#define UART_DL0_EN_S 1 +/*description: Set this bit to delay the stop bit by 1 bit..*/ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (BIT(1)) +#define UART_DL0_EN_V 0x1 +#define UART_DL0_EN_S 1 /* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UART_RS485_EN (BIT(0)) -#define UART_RS485_EN_M (BIT(0)) -#define UART_RS485_EN_V 0x1 -#define UART_RS485_EN_S 0 +/*description: Set this bit to choose the rs485 mode..*/ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (BIT(0)) +#define UART_RS485_EN_V 0x1 +#define UART_RS485_EN_S 0 -#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50) +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50) /* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */ -/*description: */ -#define UART_PRE_IDLE_NUM 0x0000FFFF -#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V) << (UART_PRE_IDLE_NUM_S)) -#define UART_PRE_IDLE_NUM_V 0xFFFF -#define UART_PRE_IDLE_NUM_S 0 +/*description: This register is used to configure the idle duration time before the first at_cm +d is received by receiver. .*/ +#define UART_PRE_IDLE_NUM 0x0000FFFF +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_V 0xFFFF +#define UART_PRE_IDLE_NUM_S 0 -#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54) +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54) /* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */ -/*description: */ -#define UART_POST_IDLE_NUM 0x0000FFFF -#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V) << (UART_POST_IDLE_NUM_S)) -#define UART_POST_IDLE_NUM_V 0xFFFF -#define UART_POST_IDLE_NUM_S 0 +/*description: This register is used to configure the duration time between the last at_cmd and + the next data..*/ +#define UART_POST_IDLE_NUM 0x0000FFFF +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_V 0xFFFF +#define UART_POST_IDLE_NUM_S 0 -#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58) +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58) /* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */ -/*description: */ -#define UART_RX_GAP_TOUT 0x0000FFFF -#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V) << (UART_RX_GAP_TOUT_S)) -#define UART_RX_GAP_TOUT_V 0xFFFF -#define UART_RX_GAP_TOUT_S 0 +/*description: This register is used to configure the duration time between the at_cmd chars..*/ +#define UART_RX_GAP_TOUT 0x0000FFFF +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_V 0xFFFF +#define UART_RX_GAP_TOUT_S 0 -#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c) +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5C) /* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ -/*description: */ -#define UART_CHAR_NUM 0x000000FF -#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V) << (UART_CHAR_NUM_S)) -#define UART_CHAR_NUM_V 0xFF -#define UART_CHAR_NUM_S 8 +/*description: This register is used to configure the num of continuous at_cmd chars received b +y receiver..*/ +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_V 0xFF +#define UART_CHAR_NUM_S 8 /* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ -/*description: */ -#define UART_AT_CMD_CHAR 0x000000FF -#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V) << (UART_AT_CMD_CHAR_S)) -#define UART_AT_CMD_CHAR_V 0xFF -#define UART_AT_CMD_CHAR_S 0 +/*description: This register is used to configure the content of at_cmd char..*/ +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_V 0xFF +#define UART_AT_CMD_CHAR_S 0 -#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) /* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define UART_MEM_FORCE_PU (BIT(27)) -#define UART_MEM_FORCE_PU_M (BIT(27)) -#define UART_MEM_FORCE_PU_V 0x1 -#define UART_MEM_FORCE_PU_S 27 +/*description: Set this bit to force power up UART memory..*/ +#define UART_MEM_FORCE_PU (BIT(27)) +#define UART_MEM_FORCE_PU_M (BIT(27)) +#define UART_MEM_FORCE_PU_V 0x1 +#define UART_MEM_FORCE_PU_S 27 /* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define UART_MEM_FORCE_PD (BIT(26)) -#define UART_MEM_FORCE_PD_M (BIT(26)) -#define UART_MEM_FORCE_PD_V 0x1 -#define UART_MEM_FORCE_PD_S 26 +/*description: Set this bit to force power down UART memory..*/ +#define UART_MEM_FORCE_PD (BIT(26)) +#define UART_MEM_FORCE_PD_M (BIT(26)) +#define UART_MEM_FORCE_PD_V 0x1 +#define UART_MEM_FORCE_PD_S 26 /* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */ -/*description: */ -#define UART_RX_TOUT_THRHD 0x000003FF -#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V) << (UART_RX_TOUT_THRHD_S)) -#define UART_RX_TOUT_THRHD_V 0x3FF -#define UART_RX_TOUT_THRHD_S 16 +/*description: This register is used to configure the threshold time that receiver takes to rec +eive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver t +akes more time to receive one byte with rx_tout_en set to 1..*/ +#define UART_RX_TOUT_THRHD 0x000003FF +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_V 0x3FF +#define UART_RX_TOUT_THRHD_S 16 /* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */ -/*description: */ -#define UART_RX_FLOW_THRHD 0x000001FF -#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V) << (UART_RX_FLOW_THRHD_S)) -#define UART_RX_FLOW_THRHD_V 0x1FF -#define UART_RX_FLOW_THRHD_S 7 +/*description: This register is used to configure the maximum amount of data that can be receiv +ed when hardware flow control works..*/ +#define UART_RX_FLOW_THRHD 0x000001FF +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_V 0x1FF +#define UART_RX_FLOW_THRHD_S 7 /* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */ -/*description: */ -#define UART_TX_SIZE 0x00000007 -#define UART_TX_SIZE_M ((UART_TX_SIZE_V) << (UART_TX_SIZE_S)) -#define UART_TX_SIZE_V 0x7 -#define UART_TX_SIZE_S 4 +/*description: This register is used to configure the amount of mem allocated for transmit-FIFO +. The default number is 128 bytes..*/ +#define UART_TX_SIZE 0x00000007 +#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) +#define UART_TX_SIZE_V 0x7 +#define UART_TX_SIZE_S 4 /* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */ -/*description: */ -#define UART_RX_SIZE 0x00000007 -#define UART_RX_SIZE_M ((UART_RX_SIZE_V) << (UART_RX_SIZE_S)) -#define UART_RX_SIZE_V 0x7 -#define UART_RX_SIZE_S 1 +/*description: This register is used to configure the amount of mem allocated for receive-FIFO. + The default number is 128 bytes..*/ +#define UART_RX_SIZE 0x00000007 +#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) +#define UART_RX_SIZE_V 0x7 +#define UART_RX_SIZE_S 1 -#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) /* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */ -/*description: TXFIFO address for uart tx read data. Default value is 10'h0 - for uart0 10'h80 for uart1 10'h100 for uart2.*/ -#define UART_TX_RADDR 0x000003FF -#define UART_TX_RADDR_M ((UART_TX_RADDR_V) << (UART_TX_RADDR_S)) -#define UART_TX_RADDR_V 0x3FF -#define UART_TX_RADDR_S 11 +/*description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx +-FIFO_Ctrl..*/ +#define UART_TX_RADDR 0x000003FF +#define UART_TX_RADDR_M ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S)) +#define UART_TX_RADDR_V 0x3FF +#define UART_TX_RADDR_S 11 /* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: TXFIFO address write by apb bus or hci. Default value is 10'h0 - for uart0 10'h80 for uart1 10'h100 for uart2.*/ -#define UART_APB_TX_WADDR 0x000003FF -#define UART_APB_TX_WADDR_M ((UART_APB_TX_WADDR_V) << (UART_APB_TX_WADDR_S)) -#define UART_APB_TX_WADDR_V 0x3FF -#define UART_APB_TX_WADDR_S 0 +/*description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO +via APB..*/ +#define UART_APB_TX_WADDR 0x000003FF +#define UART_APB_TX_WADDR_M ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S)) +#define UART_APB_TX_WADDR_V 0x3FF +#define UART_APB_TX_WADDR_S 0 -#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) /* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h200 ; */ -/*description: RXFIFO address for uart rx write data. Default value is 10'h200 - for uart0 10'h280 for uart1 10'h300 for uart2.*/ -#define UART_RX_WADDR 0x000003FF -#define UART_RX_WADDR_M ((UART_RX_WADDR_V) << (UART_RX_WADDR_S)) -#define UART_RX_WADDR_V 0x3FF -#define UART_RX_WADDR_S 11 +/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-F +IFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300..*/ +#define UART_RX_WADDR 0x000003FF +#define UART_RX_WADDR_M ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S)) +#define UART_RX_WADDR_V 0x3FF +#define UART_RX_WADDR_S 11 /* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h200 ; */ -/*description: RXFIFO address read by apb bus or hci. Default value is 10'h200 - for uart0 10'h280 for uart1 10'h300 for uart2.*/ -#define UART_APB_RX_RADDR 0x000003FF -#define UART_APB_RX_RADDR_M ((UART_APB_RX_RADDR_V) << (UART_APB_RX_RADDR_S)) -#define UART_APB_RX_RADDR_V 0x3FF -#define UART_APB_RX_RADDR_S 0 +/*description: This register stores the offset address in RX-FIFO when software reads data from + Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300..*/ +#define UART_APB_RX_RADDR 0x000003FF +#define UART_APB_RX_RADDR_M ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S)) +#define UART_APB_RX_RADDR_V 0x3FF +#define UART_APB_RX_RADDR_S 0 -#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6C) /* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: */ -#define UART_ST_UTX_OUT 0x0000000F -#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V) << (UART_ST_UTX_OUT_S)) -#define UART_ST_UTX_OUT_V 0xF -#define UART_ST_UTX_OUT_S 4 +/*description: This is the status register of transmitter..*/ +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_V 0xF +#define UART_ST_UTX_OUT_S 4 /* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define UART_ST_URX_OUT 0x0000000F -#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V) << (UART_ST_URX_OUT_S)) -#define UART_ST_URX_OUT_V 0xF -#define UART_ST_URX_OUT_S 0 +/*description: This is the status register of receiver..*/ +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_V 0xF +#define UART_ST_URX_OUT_S 0 -#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70) -/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: */ -#define UART_POSEDGE_MIN_CNT 0x00000FFF -#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V) << (UART_POSEDGE_MIN_CNT_S)) -#define UART_POSEDGE_MIN_CNT_V 0xFFF -#define UART_POSEDGE_MIN_CNT_S 0 +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70) +/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */ +/*description: This register stores the minimal input clock count between two positive edges. I +t is used in boudrate-detect process..*/ +#define UART_POSEDGE_MIN_CNT 0x00000FFF +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_V 0xFFF +#define UART_POSEDGE_MIN_CNT_S 0 -#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74) -/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: */ -#define UART_NEGEDGE_MIN_CNT 0x00000FFF -#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V) << (UART_NEGEDGE_MIN_CNT_S)) -#define UART_NEGEDGE_MIN_CNT_V 0xFFF -#define UART_NEGEDGE_MIN_CNT_S 0 +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */ +/*description: This register stores the minimal input clock count between two negative edges. I +t is used in boudrate-detect process..*/ +#define UART_NEGEDGE_MIN_CNT 0x00000FFF +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_V 0xFFF +#define UART_NEGEDGE_MIN_CNT_S 0 -#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78) +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78) /* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define UART_RX_RST_CORE (BIT(27)) -#define UART_RX_RST_CORE_M (BIT(27)) -#define UART_RX_RST_CORE_V 0x1 -#define UART_RX_RST_CORE_S 27 +/*description: Write 1 then write 0 to this bit, reset UART Rx..*/ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (BIT(27)) +#define UART_RX_RST_CORE_V 0x1 +#define UART_RX_RST_CORE_S 27 /* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define UART_TX_RST_CORE (BIT(26)) -#define UART_TX_RST_CORE_M (BIT(26)) -#define UART_TX_RST_CORE_V 0x1 -#define UART_TX_RST_CORE_S 26 +/*description: Write 1 then write 0 to this bit, reset UART Tx..*/ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (BIT(26)) +#define UART_TX_RST_CORE_V 0x1 +#define UART_TX_RST_CORE_S 26 /* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: */ -#define UART_RX_SCLK_EN (BIT(25)) -#define UART_RX_SCLK_EN_M (BIT(25)) -#define UART_RX_SCLK_EN_V 0x1 -#define UART_RX_SCLK_EN_S 25 +/*description: Set this bit to enable UART Rx clock..*/ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (BIT(25)) +#define UART_RX_SCLK_EN_V 0x1 +#define UART_RX_SCLK_EN_S 25 /* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: */ -#define UART_TX_SCLK_EN (BIT(24)) -#define UART_TX_SCLK_EN_M (BIT(24)) -#define UART_TX_SCLK_EN_V 0x1 -#define UART_TX_SCLK_EN_S 24 +/*description: Set this bit to enable UART Tx clock..*/ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (BIT(24)) +#define UART_TX_SCLK_EN_V 0x1 +#define UART_TX_SCLK_EN_S 24 /* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define UART_RST_CORE (BIT(23)) -#define UART_RST_CORE_M (BIT(23)) -#define UART_RST_CORE_V 0x1 -#define UART_RST_CORE_S 23 +/*description: Write 1 then write 0 to this bit, reset UART Tx/Rx..*/ +#define UART_RST_CORE (BIT(23)) +#define UART_RST_CORE_M (BIT(23)) +#define UART_RST_CORE_V 0x1 +#define UART_RST_CORE_S 23 /* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define UART_SCLK_EN (BIT(22)) -#define UART_SCLK_EN_M (BIT(22)) -#define UART_SCLK_EN_V 0x1 -#define UART_SCLK_EN_S 22 +/*description: Set this bit to enable UART Tx/Rx clock..*/ +#define UART_SCLK_EN (BIT(22)) +#define UART_SCLK_EN_M (BIT(22)) +#define UART_SCLK_EN_V 0x1 +#define UART_SCLK_EN_S 22 /* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */ -/*description: */ -#define UART_SCLK_SEL 0x00000003 -#define UART_SCLK_SEL_M ((UART_SCLK_SEL_V) << (UART_SCLK_SEL_S)) -#define UART_SCLK_SEL_V 0x3 -#define UART_SCLK_SEL_S 20 +/*description: UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL..*/ +#define UART_SCLK_SEL 0x00000003 +#define UART_SCLK_SEL_M ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S)) +#define UART_SCLK_SEL_V 0x3 +#define UART_SCLK_SEL_S 20 /* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */ -/*description: */ -#define UART_SCLK_DIV_NUM 0x000000FF -#define UART_SCLK_DIV_NUM_M ((UART_SCLK_DIV_NUM_V) << (UART_SCLK_DIV_NUM_S)) -#define UART_SCLK_DIV_NUM_V 0xFF -#define UART_SCLK_DIV_NUM_S 12 +/*description: The integral part of the frequency divider factor..*/ +#define UART_SCLK_DIV_NUM 0x000000FF +#define UART_SCLK_DIV_NUM_M ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S)) +#define UART_SCLK_DIV_NUM_V 0xFF +#define UART_SCLK_DIV_NUM_S 12 /* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */ -/*description: */ -#define UART_SCLK_DIV_A 0x0000003F -#define UART_SCLK_DIV_A_M ((UART_SCLK_DIV_A_V) << (UART_SCLK_DIV_A_S)) -#define UART_SCLK_DIV_A_V 0x3F -#define UART_SCLK_DIV_A_S 6 +/*description: The numerator of the frequency divider factor..*/ +#define UART_SCLK_DIV_A 0x0000003F +#define UART_SCLK_DIV_A_M ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S)) +#define UART_SCLK_DIV_A_V 0x3F +#define UART_SCLK_DIV_A_S 6 /* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: */ -#define UART_SCLK_DIV_B 0x0000003F -#define UART_SCLK_DIV_B_M ((UART_SCLK_DIV_B_V) << (UART_SCLK_DIV_B_S)) -#define UART_SCLK_DIV_B_V 0x3F -#define UART_SCLK_DIV_B_S 0 +/*description: The denominator of the frequency divider factor..*/ +#define UART_SCLK_DIV_B 0x0000003F +#define UART_SCLK_DIV_B_M ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S)) +#define UART_SCLK_DIV_B_V 0x3F +#define UART_SCLK_DIV_B_S 0 -#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c) -/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2003040 ; */ -/*description: */ -#define UART_DATE 0xFFFFFFFF -#define UART_DATE_M ((UART_DATE_V) << (UART_DATE_S)) -#define UART_DATE_V 0xFFFFFFFF -#define UART_DATE_S 0 +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7C) +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */ +/*description: This is the version register..*/ +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 -#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80) -/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ -/*description: */ -#define UART_ID 0xFFFFFFFF -#define UART_ID_M ((UART_ID_V) << (UART_ID_S)) -#define UART_ID_V 0xFFFFFFFF -#define UART_ID_S 0 +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80) +/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Software write 1 would synchronize registers into UART Core clock domain and wou +ld be cleared by hardware after synchronization is done..*/ +#define UART_UPDATE (BIT(31)) +#define UART_UPDATE_M (BIT(31)) +#define UART_UPDATE_V 0x1 +#define UART_UPDATE_S 31 +/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This bit used to select synchronize mode. 1: Registers are auto synchronized int +o UART Core clock and UART core should be keep the same with APB clock. 0: After + configure registers, software needs to write 1 to UART_REG_UPDATE to synchroniz +e registers. .*/ +#define UART_HIGH_SPEED (BIT(30)) +#define UART_HIGH_SPEED_M (BIT(30)) +#define UART_HIGH_SPEED_V 0x1 +#define UART_HIGH_SPEED_S 30 +/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */ +/*description: This register is used to configure the uart_id..*/ +#define UART_ID 0x3FFFFFFF +#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) +#define UART_ID_V 0x3FFFFFFF +#define UART_ID_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_UART_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/uart_struct.h b/components/soc/esp32s3/include/soc/uart_struct.h index d3564c8a6b..187f58d256 100644 --- a/components/soc/esp32s3/include/soc/uart_struct.h +++ b/components/soc/esp32s3/include/soc/uart_struct.h @@ -11,392 +11,401 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_UART_STRUCT_H_ +#define _SOC_UART_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif -#include - typedef volatile struct { union { struct { - uint32_t rw_byte; + uint32_t rw_byte; /*UART $n accesses FIFO via this register.*/ }; uint32_t val; } ahb_fifo; union { struct { - uint32_t rxfifo_full: 1; - uint32_t txfifo_empty: 1; - uint32_t parity_err: 1; - uint32_t frm_err: 1; - uint32_t rxfifo_ovf: 1; - uint32_t dsr_chg: 1; - uint32_t cts_chg: 1; - uint32_t brk_det: 1; - uint32_t rxfifo_tout: 1; - uint32_t sw_xon: 1; - uint32_t sw_xoff: 1; - uint32_t glitch_det: 1; - uint32_t tx_brk_done: 1; - uint32_t tx_brk_idle_done: 1; - uint32_t tx_done: 1; - uint32_t rs485_parity_err: 1; - uint32_t rs485_frm_err: 1; - uint32_t rs485_clash: 1; - uint32_t at_cmd_char_det: 1; - uint32_t wakeup: 1; - uint32_t reserved20: 12; + uint32_t rxfifo_full : 1; /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/ + uint32_t txfifo_empty : 1; /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/ + uint32_t parity_err : 1; /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/ + uint32_t frm_err : 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/ + uint32_t rxfifo_ovf : 1; /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/ + uint32_t dsr_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/ + uint32_t cts_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/ + uint32_t brk_det : 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/ + uint32_t rxfifo_tout : 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ + uint32_t sw_xon : 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xoff : 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/ + uint32_t glitch_det : 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/ + uint32_t tx_brk_done : 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.*/ + uint32_t tx_brk_idle_done : 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.*/ + uint32_t tx_done : 1; /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/ + uint32_t rs485_parity_err : 1; /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/ + uint32_t rs485_frm_err : 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/ + uint32_t rs485_clash : 1; /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/ + uint32_t at_cmd_char_det : 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/ + uint32_t wakeup : 1; /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/ + uint32_t reserved20 : 12; /*Reserved*/ }; uint32_t val; } int_raw; union { struct { - uint32_t rxfifo_full: 1; - uint32_t txfifo_empty: 1; - uint32_t parity_err: 1; - uint32_t frm_err: 1; - uint32_t rxfifo_ovf: 1; - uint32_t dsr_chg: 1; - uint32_t cts_chg: 1; - uint32_t brk_det: 1; - uint32_t rxfifo_tout: 1; - uint32_t sw_xon: 1; - uint32_t sw_xoff: 1; - uint32_t glitch_det: 1; - uint32_t tx_brk_done: 1; - uint32_t tx_brk_idle_done: 1; - uint32_t tx_done: 1; - uint32_t rs485_parity_err: 1; - uint32_t rs485_frm_err: 1; - uint32_t rs485_clash: 1; - uint32_t at_cmd_char_det: 1; - uint32_t wakeup: 1; - uint32_t reserved20: 12; + uint32_t rxfifo_full : 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ + uint32_t txfifo_empty : 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ + uint32_t parity_err : 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ + uint32_t frm_err : 1; /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/ + uint32_t rxfifo_ovf : 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ + uint32_t dsr_chg : 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ + uint32_t cts_chg : 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ + uint32_t brk_det : 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ + uint32_t rxfifo_tout : 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ + uint32_t sw_xon : 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ + uint32_t sw_xoff : 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ + uint32_t glitch_det : 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ + uint32_t tx_brk_done : 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done : 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_done : 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ + uint32_t rs485_parity_err : 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ + uint32_t rs485_frm_err : 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ + uint32_t rs485_clash : 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ + uint32_t at_cmd_char_det : 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ + uint32_t wakeup : 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/ + uint32_t reserved20 : 12; /*Reserved*/ }; uint32_t val; } int_st; union { struct { - uint32_t rxfifo_full: 1; - uint32_t txfifo_empty: 1; - uint32_t parity_err: 1; - uint32_t frm_err: 1; - uint32_t rxfifo_ovf: 1; - uint32_t dsr_chg: 1; - uint32_t cts_chg: 1; - uint32_t brk_det: 1; - uint32_t rxfifo_tout: 1; - uint32_t sw_xon: 1; - uint32_t sw_xoff: 1; - uint32_t glitch_det: 1; - uint32_t tx_brk_done: 1; - uint32_t tx_brk_idle_done: 1; - uint32_t tx_done: 1; - uint32_t rs485_parity_err: 1; - uint32_t rs485_frm_err: 1; - uint32_t rs485_clash: 1; - uint32_t at_cmd_char_det: 1; - uint32_t wakeup: 1; - uint32_t reserved20: 12; + uint32_t rxfifo_full : 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t txfifo_empty : 1; /*This is the enable bit for txfifo_empty_int_st register.*/ + uint32_t parity_err : 1; /*This is the enable bit for parity_err_int_st register.*/ + uint32_t frm_err : 1; /*This is the enable bit for frm_err_int_st register.*/ + uint32_t rxfifo_ovf : 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ + uint32_t dsr_chg : 1; /*This is the enable bit for dsr_chg_int_st register.*/ + uint32_t cts_chg : 1; /*This is the enable bit for cts_chg_int_st register.*/ + uint32_t brk_det : 1; /*This is the enable bit for brk_det_int_st register.*/ + uint32_t rxfifo_tout : 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ + uint32_t sw_xon : 1; /*This is the enable bit for sw_xon_int_st register.*/ + uint32_t sw_xoff : 1; /*This is the enable bit for sw_xoff_int_st register.*/ + uint32_t glitch_det : 1; /*This is the enable bit for glitch_det_int_st register.*/ + uint32_t tx_brk_done : 1; /*This is the enable bit for tx_brk_done_int_st register.*/ + uint32_t tx_brk_idle_done : 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ + uint32_t tx_done : 1; /*This is the enable bit for tx_done_int_st register.*/ + uint32_t rs485_parity_err : 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_frm_err : 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_clash : 1; /*This is the enable bit for rs485_clash_int_st register.*/ + uint32_t at_cmd_char_det : 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ + uint32_t wakeup : 1; /*This is the enable bit for uart_wakeup_int_st register.*/ + uint32_t reserved20 : 12; /*Reserved*/ }; uint32_t val; } int_ena; union { struct { - uint32_t rxfifo_full: 1; - uint32_t txfifo_empty: 1; - uint32_t parity_err: 1; - uint32_t frm_err: 1; - uint32_t rxfifo_ovf: 1; - uint32_t dsr_chg: 1; - uint32_t cts_chg: 1; - uint32_t brk_det: 1; - uint32_t rxfifo_tout: 1; - uint32_t sw_xon: 1; - uint32_t sw_xoff: 1; - uint32_t glitch_det: 1; - uint32_t tx_brk_done: 1; - uint32_t tx_brk_idle_done: 1; - uint32_t tx_done: 1; - uint32_t rs485_parity_err: 1; - uint32_t rs485_frm_err: 1; - uint32_t rs485_clash: 1; - uint32_t at_cmd_char_det: 1; - uint32_t wakeup: 1; - uint32_t reserved20: 12; + uint32_t rxfifo_full : 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + uint32_t txfifo_empty : 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ + uint32_t parity_err : 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ + uint32_t frm_err : 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ + uint32_t rxfifo_ovf : 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + uint32_t dsr_chg : 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ + uint32_t cts_chg : 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ + uint32_t brk_det : 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ + uint32_t rxfifo_tout : 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + uint32_t sw_xon : 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t sw_xoff : 1; /*Set this bit to clear the sw_xoff_int_raw interrupt.*/ + uint32_t glitch_det : 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ + uint32_t tx_brk_done : 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ + uint32_t tx_brk_idle_done : 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ + uint32_t tx_done : 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ + uint32_t rs485_parity_err : 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ + uint32_t rs485_frm_err : 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + uint32_t rs485_clash : 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ + uint32_t at_cmd_char_det : 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + uint32_t wakeup : 1; /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/ + uint32_t reserved20 : 12; /*Reserved*/ }; uint32_t val; } int_clr; union { struct { - uint32_t div_int: 12; - uint32_t reserved12: 8; - uint32_t div_frag: 4; - uint32_t reserved24: 8; + uint32_t div_int : 12; /*The integral part of the frequency divider factor.*/ + uint32_t reserved12 : 8; + uint32_t div_frag : 4; /*The decimal part of the frequency divider factor.*/ + uint32_t reserved24 : 8; /*Reserved*/ }; uint32_t val; } clk_div; union { struct { - uint32_t glitch_filt: 8; - uint32_t glitch_filt_en: 1; - uint32_t reserved9: 23; + uint32_t glitch_filt : 8; /*when input pulse width is lower than this value, the pulse is ignored.*/ + uint32_t glitch_filt_en : 1; /*Set this bit to enable Rx signal filter.*/ + uint32_t reserved9 : 23; }; uint32_t val; } rx_filt; union { struct { - uint32_t rxfifo_cnt: 10; - uint32_t reserved10: 3; - uint32_t dsrn: 1; - uint32_t ctsn: 1; - uint32_t rxd: 1; - uint32_t txfifo_cnt: 10; - uint32_t reserved26: 3; - uint32_t dtrn: 1; - uint32_t rtsn: 1; - uint32_t txd: 1; + uint32_t rxfifo_cnt : 10; /*Stores the byte number of valid data in Rx-FIFO.*/ + uint32_t reserved10 : 3; + uint32_t dsrn : 1; /*The register represent the level value of the internal uart dsr signal.*/ + uint32_t ctsn : 1; /*This register represent the level value of the internal uart cts signal.*/ + uint32_t rxd : 1; /*This register represent the level value of the internal uart rxd signal.*/ + uint32_t txfifo_cnt : 10; /*Stores the byte number of data in Tx-FIFO.*/ + uint32_t reserved26 : 3; /*Reserved*/ + uint32_t dtrn : 1; /*This bit represents the level of the internal uart dtr signal.*/ + uint32_t rtsn : 1; /*This bit represents the level of the internal uart rts signal.*/ + uint32_t txd : 1; /*This bit represents the level of the internal uart txd signal.*/ }; uint32_t val; } status; union { struct { - uint32_t parity: 1; - uint32_t parity_en: 1; - uint32_t bit_num: 2; - uint32_t stop_bit_num: 2; - uint32_t sw_rts: 1; - uint32_t sw_dtr: 1; - uint32_t txd_brk: 1; - uint32_t irda_dplx: 1; - uint32_t irda_tx_en: 1; - uint32_t irda_wctl: 1; - uint32_t irda_tx_inv: 1; - uint32_t irda_rx_inv: 1; - uint32_t loopback: 1; - uint32_t tx_flow_en: 1; - uint32_t irda_en: 1; - uint32_t rxfifo_rst: 1; - uint32_t txfifo_rst: 1; - uint32_t rxd_inv: 1; - uint32_t cts_inv: 1; - uint32_t dsr_inv: 1; - uint32_t txd_inv: 1; - uint32_t rts_inv: 1; - uint32_t dtr_inv: 1; - uint32_t clk_en: 1; - uint32_t err_wr_mask: 1; - uint32_t en: 1; - uint32_t mem_clk_en: 1; - uint32_t reserved29: 3; + uint32_t parity : 1; /*This register is used to configure the parity check mode.*/ + uint32_t parity_en : 1; /*Set this bit to enable uart parity check.*/ + uint32_t bit_num : 2; /*This register is used to set the length of data.*/ + uint32_t stop_bit_num : 2; /*This register is used to set the length of stop bit.*/ + uint32_t sw_rts : 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ + uint32_t sw_dtr : 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/ + uint32_t txd_brk : 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/ + uint32_t irda_dplx : 1; /*Set this bit to enable IrDA loopback mode.*/ + uint32_t irda_tx_en : 1; /*This is the start enable bit for IrDA transmitter.*/ + uint32_t irda_wctl : 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/ + uint32_t irda_tx_inv : 1; /*Set this bit to invert the level of IrDA transmitter.*/ + uint32_t irda_rx_inv : 1; /*Set this bit to invert the level of IrDA receiver.*/ + uint32_t loopback : 1; /*Set this bit to enable uart loopback test mode.*/ + uint32_t tx_flow_en : 1; /*Set this bit to enable flow control function for transmitter.*/ + uint32_t irda_en : 1; /*Set this bit to enable IrDA protocol.*/ + uint32_t rxfifo_rst : 1; /*Set this bit to reset the uart receive-FIFO.*/ + uint32_t txfifo_rst : 1; /*Set this bit to reset the uart transmit-FIFO.*/ + uint32_t rxd_inv : 1; /*Set this bit to inverse the level value of uart rxd signal.*/ + uint32_t cts_inv : 1; /*Set this bit to inverse the level value of uart cts signal.*/ + uint32_t dsr_inv : 1; /*Set this bit to inverse the level value of uart dsr signal.*/ + uint32_t txd_inv : 1; /*Set this bit to inverse the level value of uart txd signal.*/ + uint32_t rts_inv : 1; /*Set this bit to inverse the level value of uart rts signal.*/ + uint32_t dtr_inv : 1; /*Set this bit to inverse the level value of uart dtr signal.*/ + uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/ + uint32_t err_wr_mask : 1; /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.*/ + uint32_t autobaud_en : 1; /*This is the enable bit for detecting baudrate.*/ + uint32_t mem_clk_en : 1; /*UART memory clock gate enable signal.*/ + uint32_t reserved29 : 3; }; uint32_t val; } conf0; union { struct { - uint32_t rxfifo_full_thrhd: 9; - uint32_t txfifo_empty_thrhd: 9; - uint32_t dis_rx_dat_ovf: 1; - uint32_t rx_tout_flow_dis: 1; - uint32_t rx_flow_en: 1; - uint32_t rx_tout_en: 1; - uint32_t reserved22: 10; + uint32_t rxfifo_full_thrhd : 9; /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/ + uint32_t txfifo_empty_thrhd : 9; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/ + uint32_t dis_rx_dat_ovf : 1; /*Disable UART Rx data overflow detect. */ + uint32_t rx_tout_flow_dis : 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ + uint32_t rx_flow_en : 1; /*This is the flow enable bit for UART receiver.*/ + uint32_t rx_tout_en : 1; /*This is the enble bit for uart receiver's timeout function.*/ + uint32_t reserved22 : 10; }; uint32_t val; } conf1; union { struct { - uint32_t min_cnt: 12; - uint32_t reserved12: 20; + uint32_t min_cnt : 12; /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/ + uint32_t reserved12 : 20; /*Reserved*/ }; uint32_t val; } lowpulse; union { struct { - uint32_t min_cnt: 12; - uint32_t reserved12: 20; + uint32_t min_cnt : 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/ + uint32_t reserved12 : 20; /*Reserved*/ }; uint32_t val; } highpulse; union { struct { - uint32_t edge_cnt: 10; - uint32_t reserved10: 22; + uint32_t edge_cnt : 10; /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/ + uint32_t reserved10 : 22; /*Reserved*/ }; uint32_t val; } rxd_cnt; union { struct { - uint32_t sw_flow_con_en: 1; - uint32_t xonoff_del: 1; - uint32_t force_xon: 1; - uint32_t force_xoff: 1; - uint32_t send_xon: 1; - uint32_t send_xoff: 1; - uint32_t reserved6: 26; + uint32_t sw_flow_con_en : 1; /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/ + uint32_t xonoff_del : 1; /*Set this bit to remove flow control char from the received data.*/ + uint32_t force_xon : 1; /*Set this bit to enable the transmitter to go on sending data.*/ + uint32_t force_xoff : 1; /*Set this bit to stop the transmitter from sending data.*/ + uint32_t send_xon : 1; /*Set this bit to send Xon char. It is cleared by hardware automatically.*/ + uint32_t send_xoff : 1; /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/ + uint32_t reserved6 : 26; /*Reserved*/ }; uint32_t val; } flow_conf; union { struct { - uint32_t active_threshold: 10; - uint32_t reserved10: 22; + uint32_t active_threshold : 10; /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/ + uint32_t reserved10 : 22; /*Reserved*/ }; uint32_t val; } sleep_conf; union { struct { - uint32_t xoff_threshold: 9; - uint32_t xoff_char: 8; - uint32_t reserved17: 15; + uint32_t xoff_threshold : 9; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/ + uint32_t xoff_char : 8; /*This register stores the Xoff flow control char.*/ + uint32_t reserved17 : 15; /*Reserved*/ }; uint32_t val; } swfc_conf0; union { struct { - uint32_t xon_threshold: 9; - uint32_t xon_char: 8; - uint32_t reserved17: 15; + uint32_t xon_threshold : 9; /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/ + uint32_t xon_char : 8; /*This register stores the Xon flow control char.*/ + uint32_t reserved17 : 15; /*Reserved*/ }; uint32_t val; } swfc_conf1; union { struct { - uint32_t tx_brk_num: 8; - uint32_t reserved8: 24; + uint32_t tx_brk_num : 8; /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/ + uint32_t reserved8 : 24; }; uint32_t val; } txbrk_conf; union { struct { - uint32_t rx_idle_thrhd: 10; - uint32_t tx_idle_num: 10; - uint32_t reserved20: 12; + uint32_t rx_idle_thrhd : 10; /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/ + uint32_t tx_idle_num : 10; /*This register is used to configure the duration time between transfers.*/ + uint32_t reserved20 : 12; /*Reserved*/ }; uint32_t val; } idle_conf; union { struct { - uint32_t en: 1; - uint32_t dl0_en: 1; - uint32_t dl1_en: 1; - uint32_t tx_rx_en: 1; - uint32_t rx_busy_tx_en: 1; - uint32_t rx_dly_num: 1; - uint32_t tx_dly_num: 4; - uint32_t reserved10: 22; + uint32_t en : 1; /*Set this bit to choose the rs485 mode.*/ + uint32_t dl0_en : 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t dl1_en : 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t tx_rx_en : 1; /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. */ + uint32_t rx_busy_tx_en : 1; /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. */ + uint32_t rx_dly_num : 1; /*This register is used to delay the receiver's internal data signal.*/ + uint32_t tx_dly_num : 4; /*This register is used to delay the transmitter's internal data signal.*/ + uint32_t reserved10 : 22; /*Reserved*/ }; uint32_t val; } rs485_conf; union { struct { - uint32_t pre_idle_num: 16; - uint32_t reserved16: 16; + uint32_t pre_idle_num : 16; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver. */ + uint32_t reserved16 : 16; /*Reserved*/ }; uint32_t val; } at_cmd_precnt; union { struct { - uint32_t post_idle_num: 16; - uint32_t reserved16: 16; + uint32_t post_idle_num : 16; /*This register is used to configure the duration time between the last at_cmd and the next data.*/ + uint32_t reserved16 : 16; /*Reserved*/ }; uint32_t val; } at_cmd_postcnt; union { struct { - uint32_t rx_gap_tout: 16; - uint32_t reserved16: 16; + uint32_t rx_gap_tout : 16; /*This register is used to configure the duration time between the at_cmd chars.*/ + uint32_t reserved16 : 16; /*Reserved*/ }; uint32_t val; } at_cmd_gaptout; union { struct { - uint32_t data: 8; - uint32_t char_num: 8; - uint32_t reserved16: 16; + uint32_t data : 8; /*This register is used to configure the content of at_cmd char.*/ + uint32_t char_num : 8; /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/ + uint32_t reserved16 : 16; /*Reserved*/ }; uint32_t val; } at_cmd_char; union { struct { - uint32_t reserved0: 1; - uint32_t rx_size: 3; - uint32_t tx_size: 3; - uint32_t rx_flow_thrhd: 9; - uint32_t rx_tout_thrhd: 10; - uint32_t force_pd: 1; - uint32_t force_pu: 1; - uint32_t reserved28: 4; + uint32_t reserved0 : 1; + uint32_t rx_size : 3; /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/ + uint32_t tx_size : 3; /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/ + uint32_t rx_flow_thrhd : 9; /*This register is used to configure the maximum amount of data that can be received when hardware flow control works.*/ + uint32_t rx_tout_thrhd : 10; /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/ + uint32_t force_pd : 1; /*Set this bit to force power down UART memory.*/ + uint32_t force_pu : 1; /*Set this bit to force power up UART memory.*/ + uint32_t reserved28 : 4; }; uint32_t val; } mem_conf; union { struct { - uint32_t apb_tx_waddr: 10; /*TXFIFO address write by apb bus or hci. Default value is 10'h0 for uart0 10'h80 for uart1 10'h100 for uart2.*/ - uint32_t reserved10: 1; - uint32_t tx_raddr: 10; /*TXFIFO address for uart tx read data. Default value is 10'h0 for uart0 10'h80 for uart1 10'h100 for uart2.*/ - uint32_t reserved21: 11; + uint32_t apb_tx_waddr : 10; /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/ + uint32_t reserved10 : 1; /*Reserved*/ + uint32_t tx_raddr : 10; /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/ + uint32_t reserved21 : 11; /*Reserved*/ }; uint32_t val; } mem_tx_status; union { struct { - uint32_t apb_rx_raddr: 10; /*RXFIFO address read by apb bus or hci. Default value is 10'h200 for uart0 10'h280 for uart1 10'h300 for uart2.*/ - uint32_t reserved10: 1; - uint32_t rx_waddr: 10; /*RXFIFO address for uart rx write data. Default value is 10'h200 for uart0 10'h280 for uart1 10'h300 for uart2.*/ - uint32_t reserved21: 11; + uint32_t apb_rx_raddr : 10; /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.*/ + uint32_t reserved10 : 1; /*Reserved*/ + uint32_t rx_waddr : 10; /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.*/ + uint32_t reserved21 : 11; /*Reserved*/ }; uint32_t val; } mem_rx_status; union { struct { - uint32_t st_urx_out: 4; - uint32_t st_utx_out: 4; - uint32_t reserved8: 24; + uint32_t st_urx_out : 4; /*This is the status register of receiver.*/ + uint32_t st_utx_out : 4; /*This is the status register of transmitter.*/ + uint32_t reserved8 : 24; /*Reserved*/ }; uint32_t val; } fsm_status; union { struct { - uint32_t min_cnt: 12; - uint32_t reserved12: 20; + uint32_t min_cnt : 12; /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/ + uint32_t reserved12 : 20; /*Reserved*/ }; uint32_t val; } pospulse; union { struct { - uint32_t min_cnt: 12; - uint32_t reserved12: 20; + uint32_t min_cnt : 12; /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/ + uint32_t reserved12 : 20; /*Reserved*/ }; uint32_t val; } negpulse; union { struct { - uint32_t sclk_div_b: 6; - uint32_t sclk_div_a: 6; - uint32_t sclk_div_num: 8; - uint32_t sclk_sel: 2; - uint32_t sclk_en: 1; - uint32_t rst_core: 1; - uint32_t tx_sclk_en: 1; - uint32_t rx_sclk_en: 1; - uint32_t tx_rst_core: 1; - uint32_t rx_rst_core: 1; - uint32_t reserved28: 4; + uint32_t sclk_div_b : 6; /*The denominator of the frequency divider factor.*/ + uint32_t sclk_div_a : 6; /*The numerator of the frequency divider factor.*/ + uint32_t sclk_div_num : 8; /*The integral part of the frequency divider factor.*/ + uint32_t sclk_sel : 2; /*UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.*/ + uint32_t sclk_en : 1; /*Set this bit to enable UART Tx/Rx clock.*/ + uint32_t rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Tx/Rx.*/ + uint32_t tx_sclk_en : 1; /*Set this bit to enable UART Tx clock.*/ + uint32_t rx_sclk_en : 1; /*Set this bit to enable UART Rx clock.*/ + uint32_t tx_rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Tx.*/ + uint32_t rx_rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Rx.*/ + uint32_t reserved28 : 4; }; uint32_t val; } clk_conf; - uint32_t date; /**/ - uint32_t id; /**/ + uint32_t date; + union { + struct { + uint32_t id : 30; /*This register is used to configure the uart_id.*/ + uint32_t high_speed : 1; /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */ + uint32_t update : 1; /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/ + }; + uint32_t val; + } id; } uart_dev_t; - extern uart_dev_t UART0; extern uart_dev_t UART1; extern uart_dev_t UART2; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_UART_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/uhci_reg.h b/components/soc/esp32s3/include/soc/uhci_reg.h index 440c85cafc..a52010208a 100644 --- a/components/soc/esp32s3/include/soc/uhci_reg.h +++ b/components/soc/esp32s3/include/soc/uhci_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,650 +11,754 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_UHCI_REG_H_ +#define _SOC_UHCI_REG_H_ + #ifdef __cplusplus extern "C" { #endif - #include "soc.h" -#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) +#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) /* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) -#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12)) -#define UHCI_UART_RX_BRK_EOF_EN_V 0x1 -#define UHCI_UART_RX_BRK_EOF_EN_S 12 +/*description: .*/ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x1 +#define UHCI_UART_RX_BRK_EOF_EN_S 12 /* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_CLK_EN (BIT(11)) -#define UHCI_CLK_EN_M (BIT(11)) -#define UHCI_CLK_EN_V 0x1 -#define UHCI_CLK_EN_S 11 +/*description: .*/ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (BIT(11)) +#define UHCI_CLK_EN_V 0x1 +#define UHCI_CLK_EN_S 11 /* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_ENCODE_CRC_EN (BIT(10)) -#define UHCI_ENCODE_CRC_EN_M (BIT(10)) -#define UHCI_ENCODE_CRC_EN_V 0x1 -#define UHCI_ENCODE_CRC_EN_S 10 +/*description: .*/ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (BIT(10)) +#define UHCI_ENCODE_CRC_EN_V 0x1 +#define UHCI_ENCODE_CRC_EN_S 10 /* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_LEN_EOF_EN (BIT(9)) -#define UHCI_LEN_EOF_EN_M (BIT(9)) -#define UHCI_LEN_EOF_EN_V 0x1 -#define UHCI_LEN_EOF_EN_S 9 +/*description: .*/ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (BIT(9)) +#define UHCI_LEN_EOF_EN_V 0x1 +#define UHCI_LEN_EOF_EN_S 9 /* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_UART_IDLE_EOF_EN (BIT(8)) -#define UHCI_UART_IDLE_EOF_EN_M (BIT(8)) -#define UHCI_UART_IDLE_EOF_EN_V 0x1 -#define UHCI_UART_IDLE_EOF_EN_S 8 +/*description: .*/ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_V 0x1 +#define UHCI_UART_IDLE_EOF_EN_S 8 /* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_CRC_REC_EN (BIT(7)) -#define UHCI_CRC_REC_EN_M (BIT(7)) -#define UHCI_CRC_REC_EN_V 0x1 -#define UHCI_CRC_REC_EN_S 7 +/*description: .*/ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (BIT(7)) +#define UHCI_CRC_REC_EN_V 0x1 +#define UHCI_CRC_REC_EN_S 7 /* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_HEAD_EN (BIT(6)) -#define UHCI_HEAD_EN_M (BIT(6)) -#define UHCI_HEAD_EN_V 0x1 -#define UHCI_HEAD_EN_S 6 +/*description: .*/ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (BIT(6)) +#define UHCI_HEAD_EN_V 0x1 +#define UHCI_HEAD_EN_S 6 /* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_SEPER_EN (BIT(5)) -#define UHCI_SEPER_EN_M (BIT(5)) -#define UHCI_SEPER_EN_V 0x1 -#define UHCI_SEPER_EN_S 5 +/*description: .*/ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (BIT(5)) +#define UHCI_SEPER_EN_V 0x1 +#define UHCI_SEPER_EN_S 5 /* UHCI_UART2_CE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_UART2_CE (BIT(4)) -#define UHCI_UART2_CE_M (BIT(4)) -#define UHCI_UART2_CE_V 0x1 -#define UHCI_UART2_CE_S 4 +/*description: .*/ +#define UHCI_UART2_CE (BIT(4)) +#define UHCI_UART2_CE_M (BIT(4)) +#define UHCI_UART2_CE_V 0x1 +#define UHCI_UART2_CE_S 4 /* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_UART1_CE (BIT(3)) -#define UHCI_UART1_CE_M (BIT(3)) -#define UHCI_UART1_CE_V 0x1 -#define UHCI_UART1_CE_S 3 +/*description: .*/ +#define UHCI_UART1_CE (BIT(3)) +#define UHCI_UART1_CE_M (BIT(3)) +#define UHCI_UART1_CE_V 0x1 +#define UHCI_UART1_CE_S 3 /* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: */ -#define UHCI_UART0_CE (BIT(2)) -#define UHCI_UART0_CE_M (BIT(2)) -#define UHCI_UART0_CE_V 0x1 -#define UHCI_UART0_CE_S 2 +/*description: .*/ +#define UHCI_UART0_CE (BIT(2)) +#define UHCI_UART0_CE_M (BIT(2)) +#define UHCI_UART0_CE_V 0x1 +#define UHCI_UART0_CE_S 2 /* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_RST (BIT(1)) -#define UHCI_RX_RST_M (BIT(1)) -#define UHCI_RX_RST_V 0x1 -#define UHCI_RX_RST_S 1 +/*description: .*/ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (BIT(1)) +#define UHCI_RX_RST_V 0x1 +#define UHCI_RX_RST_S 1 /* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define UHCI_TX_RST (BIT(0)) -#define UHCI_TX_RST_M (BIT(0)) -#define UHCI_TX_RST_V 0x1 -#define UHCI_TX_RST_S 0 +/*description: .*/ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (BIT(0)) +#define UHCI_TX_RST_V 0x1 +#define UHCI_TX_RST_S 0 -#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) +#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) +/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_M (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_V 0x1 +#define UHCI_APP_CTRL1_INT_RAW_S 8 +/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_M (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_V 0x1 +#define UHCI_APP_CTRL0_INT_RAW_S 7 +/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 6 /* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SEND_A_Q_INT_RAW (BIT(5)) -#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5)) -#define UHCI_SEND_A_Q_INT_RAW_V 0x1 -#define UHCI_SEND_A_Q_INT_RAW_S 5 +/*description: .*/ +#define UHCI_SEND_A_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_RAW_V 0x1 +#define UHCI_SEND_A_Q_INT_RAW_S 5 /* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SEND_S_Q_INT_RAW (BIT(4)) -#define UHCI_SEND_S_Q_INT_RAW_M (BIT(4)) -#define UHCI_SEND_S_Q_INT_RAW_V 0x1 -#define UHCI_SEND_S_Q_INT_RAW_S 4 +/*description: .*/ +#define UHCI_SEND_S_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_Q_INT_RAW_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_RAW_V 0x1 +#define UHCI_SEND_S_Q_INT_RAW_S 4 /* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_HUNG_INT_RAW (BIT(3)) -#define UHCI_TX_HUNG_INT_RAW_M (BIT(3)) -#define UHCI_TX_HUNG_INT_RAW_V 0x1 -#define UHCI_TX_HUNG_INT_RAW_S 3 +/*description: .*/ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_V 0x1 +#define UHCI_TX_HUNG_INT_RAW_S 3 /* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_HUNG_INT_RAW (BIT(2)) -#define UHCI_RX_HUNG_INT_RAW_M (BIT(2)) -#define UHCI_RX_HUNG_INT_RAW_V 0x1 -#define UHCI_RX_HUNG_INT_RAW_S 2 +/*description: .*/ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_V 0x1 +#define UHCI_RX_HUNG_INT_RAW_S 2 /* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_START_INT_RAW (BIT(1)) -#define UHCI_TX_START_INT_RAW_M (BIT(1)) -#define UHCI_TX_START_INT_RAW_V 0x1 -#define UHCI_TX_START_INT_RAW_S 1 +/*description: .*/ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (BIT(1)) +#define UHCI_TX_START_INT_RAW_V 0x1 +#define UHCI_TX_START_INT_RAW_S 1 /* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_START_INT_RAW (BIT(0)) -#define UHCI_RX_START_INT_RAW_M (BIT(0)) -#define UHCI_RX_START_INT_RAW_V 0x1 -#define UHCI_RX_START_INT_RAW_S 0 +/*description: .*/ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (BIT(0)) +#define UHCI_RX_START_INT_RAW_V 0x1 +#define UHCI_RX_START_INT_RAW_S 0 -#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) +#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) +/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL1_INT_ST (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_M (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_V 0x1 +#define UHCI_APP_CTRL1_INT_ST_S 8 +/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL0_INT_ST (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_M (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_V 0x1 +#define UHCI_APP_CTRL0_INT_ST_S 7 +/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 /* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SEND_A_Q_INT_ST (BIT(5)) -#define UHCI_SEND_A_Q_INT_ST_M (BIT(5)) -#define UHCI_SEND_A_Q_INT_ST_V 0x1 -#define UHCI_SEND_A_Q_INT_ST_S 5 +/*description: .*/ +#define UHCI_SEND_A_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_Q_INT_ST_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_ST_V 0x1 +#define UHCI_SEND_A_Q_INT_ST_S 5 /* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SEND_S_Q_INT_ST (BIT(4)) -#define UHCI_SEND_S_Q_INT_ST_M (BIT(4)) -#define UHCI_SEND_S_Q_INT_ST_V 0x1 -#define UHCI_SEND_S_Q_INT_ST_S 4 +/*description: .*/ +#define UHCI_SEND_S_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_Q_INT_ST_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_ST_V 0x1 +#define UHCI_SEND_S_Q_INT_ST_S 4 /* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_HUNG_INT_ST (BIT(3)) -#define UHCI_TX_HUNG_INT_ST_M (BIT(3)) -#define UHCI_TX_HUNG_INT_ST_V 0x1 -#define UHCI_TX_HUNG_INT_ST_S 3 +/*description: .*/ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_V 0x1 +#define UHCI_TX_HUNG_INT_ST_S 3 /* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_HUNG_INT_ST (BIT(2)) -#define UHCI_RX_HUNG_INT_ST_M (BIT(2)) -#define UHCI_RX_HUNG_INT_ST_V 0x1 -#define UHCI_RX_HUNG_INT_ST_S 2 +/*description: .*/ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_V 0x1 +#define UHCI_RX_HUNG_INT_ST_S 2 /* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_START_INT_ST (BIT(1)) -#define UHCI_TX_START_INT_ST_M (BIT(1)) -#define UHCI_TX_START_INT_ST_V 0x1 -#define UHCI_TX_START_INT_ST_S 1 +/*description: .*/ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (BIT(1)) +#define UHCI_TX_START_INT_ST_V 0x1 +#define UHCI_TX_START_INT_ST_S 1 /* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_START_INT_ST (BIT(0)) -#define UHCI_RX_START_INT_ST_M (BIT(0)) -#define UHCI_RX_START_INT_ST_V 0x1 -#define UHCI_RX_START_INT_ST_S 0 +/*description: .*/ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (BIT(0)) +#define UHCI_RX_START_INT_ST_V 0x1 +#define UHCI_RX_START_INT_ST_S 0 -#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC) +#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC) +/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_M (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_V 0x1 +#define UHCI_APP_CTRL1_INT_ENA_S 8 +/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_M (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_V 0x1 +#define UHCI_APP_CTRL0_INT_ENA_S 7 +/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 /* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SEND_A_Q_INT_ENA (BIT(5)) -#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5)) -#define UHCI_SEND_A_Q_INT_ENA_V 0x1 -#define UHCI_SEND_A_Q_INT_ENA_S 5 +/*description: .*/ +#define UHCI_SEND_A_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_ENA_V 0x1 +#define UHCI_SEND_A_Q_INT_ENA_S 5 /* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SEND_S_Q_INT_ENA (BIT(4)) -#define UHCI_SEND_S_Q_INT_ENA_M (BIT(4)) -#define UHCI_SEND_S_Q_INT_ENA_V 0x1 -#define UHCI_SEND_S_Q_INT_ENA_S 4 +/*description: .*/ +#define UHCI_SEND_S_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_Q_INT_ENA_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_ENA_V 0x1 +#define UHCI_SEND_S_Q_INT_ENA_S 4 /* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_HUNG_INT_ENA (BIT(3)) -#define UHCI_TX_HUNG_INT_ENA_M (BIT(3)) -#define UHCI_TX_HUNG_INT_ENA_V 0x1 -#define UHCI_TX_HUNG_INT_ENA_S 3 +/*description: .*/ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_V 0x1 +#define UHCI_TX_HUNG_INT_ENA_S 3 /* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_HUNG_INT_ENA (BIT(2)) -#define UHCI_RX_HUNG_INT_ENA_M (BIT(2)) -#define UHCI_RX_HUNG_INT_ENA_V 0x1 -#define UHCI_RX_HUNG_INT_ENA_S 2 +/*description: .*/ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_V 0x1 +#define UHCI_RX_HUNG_INT_ENA_S 2 /* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_START_INT_ENA (BIT(1)) -#define UHCI_TX_START_INT_ENA_M (BIT(1)) -#define UHCI_TX_START_INT_ENA_V 0x1 -#define UHCI_TX_START_INT_ENA_S 1 +/*description: .*/ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (BIT(1)) +#define UHCI_TX_START_INT_ENA_V 0x1 +#define UHCI_TX_START_INT_ENA_S 1 /* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_START_INT_ENA (BIT(0)) -#define UHCI_RX_START_INT_ENA_M (BIT(0)) -#define UHCI_RX_START_INT_ENA_V 0x1 -#define UHCI_RX_START_INT_ENA_S 0 +/*description: .*/ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (BIT(0)) +#define UHCI_RX_START_INT_ENA_V 0x1 +#define UHCI_RX_START_INT_ENA_S 0 -#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) +#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) +/* UHCI_APP_CTRL1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_M (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_V 0x1 +#define UHCI_APP_CTRL1_INT_CLR_S 8 +/* UHCI_APP_CTRL0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_M (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_V 0x1 +#define UHCI_APP_CTRL0_INT_CLR_S 7 +/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1 +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 /* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SEND_A_Q_INT_CLR (BIT(5)) -#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5)) -#define UHCI_SEND_A_Q_INT_CLR_V 0x1 -#define UHCI_SEND_A_Q_INT_CLR_S 5 +/*description: .*/ +#define UHCI_SEND_A_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_CLR_V 0x1 +#define UHCI_SEND_A_Q_INT_CLR_S 5 /* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SEND_S_Q_INT_CLR (BIT(4)) -#define UHCI_SEND_S_Q_INT_CLR_M (BIT(4)) -#define UHCI_SEND_S_Q_INT_CLR_V 0x1 -#define UHCI_SEND_S_Q_INT_CLR_S 4 +/*description: .*/ +#define UHCI_SEND_S_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_Q_INT_CLR_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_CLR_V 0x1 +#define UHCI_SEND_S_Q_INT_CLR_S 4 /* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_HUNG_INT_CLR (BIT(3)) -#define UHCI_TX_HUNG_INT_CLR_M (BIT(3)) -#define UHCI_TX_HUNG_INT_CLR_V 0x1 -#define UHCI_TX_HUNG_INT_CLR_S 3 +/*description: .*/ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_V 0x1 +#define UHCI_TX_HUNG_INT_CLR_S 3 /* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_HUNG_INT_CLR (BIT(2)) -#define UHCI_RX_HUNG_INT_CLR_M (BIT(2)) -#define UHCI_RX_HUNG_INT_CLR_V 0x1 -#define UHCI_RX_HUNG_INT_CLR_S 2 +/*description: .*/ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_V 0x1 +#define UHCI_RX_HUNG_INT_CLR_S 2 /* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_START_INT_CLR (BIT(1)) -#define UHCI_TX_START_INT_CLR_M (BIT(1)) -#define UHCI_TX_START_INT_CLR_V 0x1 -#define UHCI_TX_START_INT_CLR_S 1 +/*description: .*/ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (BIT(1)) +#define UHCI_TX_START_INT_CLR_V 0x1 +#define UHCI_TX_START_INT_CLR_S 1 /* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_START_INT_CLR (BIT(0)) -#define UHCI_RX_START_INT_CLR_M (BIT(0)) -#define UHCI_RX_START_INT_CLR_V 0x1 -#define UHCI_RX_START_INT_CLR_S 0 +/*description: .*/ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (BIT(0)) +#define UHCI_RX_START_INT_CLR_V 0x1 +#define UHCI_RX_START_INT_CLR_S 0 -#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14) +#define UHCI_APP_INT_SET_REG(i) (REG_UHCI_BASE(i) + 0x14) +/* UHCI_APP_CTRL1_INT_SET : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL1_INT_SET (BIT(1)) +#define UHCI_APP_CTRL1_INT_SET_M (BIT(1)) +#define UHCI_APP_CTRL1_INT_SET_V 0x1 +#define UHCI_APP_CTRL1_INT_SET_S 1 +/* UHCI_APP_CTRL0_INT_SET : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define UHCI_APP_CTRL0_INT_SET (BIT(0)) +#define UHCI_APP_CTRL0_INT_SET_M (BIT(0)) +#define UHCI_APP_CTRL0_INT_SET_V 0x1 +#define UHCI_APP_CTRL0_INT_SET_S 0 + +#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x18) /* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SW_START (BIT(8)) -#define UHCI_SW_START_M (BIT(8)) -#define UHCI_SW_START_V 0x1 -#define UHCI_SW_START_S 8 +/*description: .*/ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (BIT(8)) +#define UHCI_SW_START_V 0x1 +#define UHCI_SW_START_S 8 /* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_WAIT_SW_START (BIT(7)) -#define UHCI_WAIT_SW_START_M (BIT(7)) -#define UHCI_WAIT_SW_START_V 0x1 -#define UHCI_WAIT_SW_START_S 7 +/*description: .*/ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (BIT(7)) +#define UHCI_WAIT_SW_START_V 0x1 +#define UHCI_WAIT_SW_START_S 7 /* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_TX_ACK_NUM_RE (BIT(5)) -#define UHCI_TX_ACK_NUM_RE_M (BIT(5)) -#define UHCI_TX_ACK_NUM_RE_V 0x1 -#define UHCI_TX_ACK_NUM_RE_S 5 +/*description: .*/ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_V 0x1 +#define UHCI_TX_ACK_NUM_RE_S 5 /* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_TX_CHECK_SUM_RE (BIT(4)) -#define UHCI_TX_CHECK_SUM_RE_M (BIT(4)) -#define UHCI_TX_CHECK_SUM_RE_V 0x1 -#define UHCI_TX_CHECK_SUM_RE_S 4 +/*description: .*/ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_V 0x1 +#define UHCI_TX_CHECK_SUM_RE_S 4 /* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SAVE_HEAD (BIT(3)) -#define UHCI_SAVE_HEAD_M (BIT(3)) -#define UHCI_SAVE_HEAD_V 0x1 -#define UHCI_SAVE_HEAD_S 3 +/*description: .*/ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (BIT(3)) +#define UHCI_SAVE_HEAD_V 0x1 +#define UHCI_SAVE_HEAD_S 3 /* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_CRC_DISABLE (BIT(2)) -#define UHCI_CRC_DISABLE_M (BIT(2)) -#define UHCI_CRC_DISABLE_V 0x1 -#define UHCI_CRC_DISABLE_S 2 +/*description: .*/ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (BIT(2)) +#define UHCI_CRC_DISABLE_V 0x1 +#define UHCI_CRC_DISABLE_S 2 /* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_CHECK_SEQ_EN (BIT(1)) -#define UHCI_CHECK_SEQ_EN_M (BIT(1)) -#define UHCI_CHECK_SEQ_EN_V 0x1 -#define UHCI_CHECK_SEQ_EN_S 1 +/*description: .*/ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (BIT(1)) +#define UHCI_CHECK_SEQ_EN_V 0x1 +#define UHCI_CHECK_SEQ_EN_S 1 /* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_CHECK_SUM_EN (BIT(0)) -#define UHCI_CHECK_SUM_EN_M (BIT(0)) -#define UHCI_CHECK_SUM_EN_V 0x1 -#define UHCI_CHECK_SUM_EN_S 0 +/*description: .*/ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (BIT(0)) +#define UHCI_CHECK_SUM_EN_V 0x1 +#define UHCI_CHECK_SUM_EN_S 0 -#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18) +#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x1C) /* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: */ -#define UHCI_DECODE_STATE 0x00000007 -#define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V) << (UHCI_DECODE_STATE_S)) -#define UHCI_DECODE_STATE_V 0x7 -#define UHCI_DECODE_STATE_S 3 +/*description: .*/ +#define UHCI_DECODE_STATE 0x00000007 +#define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S)) +#define UHCI_DECODE_STATE_V 0x7 +#define UHCI_DECODE_STATE_S 3 /* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define UHCI_RX_ERR_CAUSE 0x00000007 -#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V) << (UHCI_RX_ERR_CAUSE_S)) -#define UHCI_RX_ERR_CAUSE_V 0x7 -#define UHCI_RX_ERR_CAUSE_S 0 +/*description: .*/ +#define UHCI_RX_ERR_CAUSE 0x00000007 +#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S)) +#define UHCI_RX_ERR_CAUSE_V 0x7 +#define UHCI_RX_ERR_CAUSE_S 0 -#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1C) +#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x20) /* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define UHCI_ENCODE_STATE 0x00000007 -#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V) << (UHCI_ENCODE_STATE_S)) -#define UHCI_ENCODE_STATE_V 0x7 -#define UHCI_ENCODE_STATE_S 0 +/*description: .*/ +#define UHCI_ENCODE_STATE 0x00000007 +#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S)) +#define UHCI_ENCODE_STATE_V 0x7 +#define UHCI_ENCODE_STATE_S 0 -#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20) +#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24) /* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_13_ESC_EN (BIT(7)) -#define UHCI_RX_13_ESC_EN_M (BIT(7)) -#define UHCI_RX_13_ESC_EN_V 0x1 -#define UHCI_RX_13_ESC_EN_S 7 +/*description: .*/ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (BIT(7)) +#define UHCI_RX_13_ESC_EN_V 0x1 +#define UHCI_RX_13_ESC_EN_S 7 /* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_RX_11_ESC_EN (BIT(6)) -#define UHCI_RX_11_ESC_EN_M (BIT(6)) -#define UHCI_RX_11_ESC_EN_V 0x1 -#define UHCI_RX_11_ESC_EN_S 6 +/*description: .*/ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (BIT(6)) +#define UHCI_RX_11_ESC_EN_V 0x1 +#define UHCI_RX_11_ESC_EN_S 6 /* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_RX_DB_ESC_EN (BIT(5)) -#define UHCI_RX_DB_ESC_EN_M (BIT(5)) -#define UHCI_RX_DB_ESC_EN_V 0x1 -#define UHCI_RX_DB_ESC_EN_S 5 +/*description: .*/ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (BIT(5)) +#define UHCI_RX_DB_ESC_EN_V 0x1 +#define UHCI_RX_DB_ESC_EN_S 5 /* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_RX_C0_ESC_EN (BIT(4)) -#define UHCI_RX_C0_ESC_EN_M (BIT(4)) -#define UHCI_RX_C0_ESC_EN_V 0x1 -#define UHCI_RX_C0_ESC_EN_S 4 +/*description: .*/ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (BIT(4)) +#define UHCI_RX_C0_ESC_EN_V 0x1 +#define UHCI_RX_C0_ESC_EN_S 4 /* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_13_ESC_EN (BIT(3)) -#define UHCI_TX_13_ESC_EN_M (BIT(3)) -#define UHCI_TX_13_ESC_EN_V 0x1 -#define UHCI_TX_13_ESC_EN_S 3 +/*description: .*/ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (BIT(3)) +#define UHCI_TX_13_ESC_EN_V 0x1 +#define UHCI_TX_13_ESC_EN_S 3 /* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_TX_11_ESC_EN (BIT(2)) -#define UHCI_TX_11_ESC_EN_M (BIT(2)) -#define UHCI_TX_11_ESC_EN_V 0x1 -#define UHCI_TX_11_ESC_EN_S 2 +/*description: .*/ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (BIT(2)) +#define UHCI_TX_11_ESC_EN_V 0x1 +#define UHCI_TX_11_ESC_EN_S 2 /* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_TX_DB_ESC_EN (BIT(1)) -#define UHCI_TX_DB_ESC_EN_M (BIT(1)) -#define UHCI_TX_DB_ESC_EN_V 0x1 -#define UHCI_TX_DB_ESC_EN_S 1 +/*description: .*/ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (BIT(1)) +#define UHCI_TX_DB_ESC_EN_V 0x1 +#define UHCI_TX_DB_ESC_EN_S 1 /* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_TX_C0_ESC_EN (BIT(0)) -#define UHCI_TX_C0_ESC_EN_M (BIT(0)) -#define UHCI_TX_C0_ESC_EN_V 0x1 -#define UHCI_TX_C0_ESC_EN_S 0 +/*description: .*/ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (BIT(0)) +#define UHCI_TX_C0_ESC_EN_V 0x1 +#define UHCI_TX_C0_ESC_EN_S 0 -#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24) +#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x28) /* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) -#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23)) -#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1 -#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 +/*description: .*/ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 /* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: */ -#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 -#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V) << (UHCI_RXFIFO_TIMEOUT_SHIFT_S)) -#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7 -#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/*description: .*/ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 /* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */ -/*description: */ -#define UHCI_RXFIFO_TIMEOUT 0x000000FF -#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V) << (UHCI_RXFIFO_TIMEOUT_S)) -#define UHCI_RXFIFO_TIMEOUT_V 0xFF -#define UHCI_RXFIFO_TIMEOUT_S 12 +/*description: .*/ +#define UHCI_RXFIFO_TIMEOUT 0x000000FF +#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S)) +#define UHCI_RXFIFO_TIMEOUT_V 0xFF +#define UHCI_RXFIFO_TIMEOUT_S 12 /* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) -#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11)) -#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1 -#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/*description: .*/ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 /* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: */ -#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 -#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V) << (UHCI_TXFIFO_TIMEOUT_SHIFT_S)) -#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7 -#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/*description: .*/ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 /* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ -/*description: */ -#define UHCI_TXFIFO_TIMEOUT 0x000000FF -#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V) << (UHCI_TXFIFO_TIMEOUT_S)) -#define UHCI_TXFIFO_TIMEOUT_V 0xFF -#define UHCI_TXFIFO_TIMEOUT_S 0 +/*description: .*/ +#define UHCI_TXFIFO_TIMEOUT 0x000000FF +#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S)) +#define UHCI_TXFIFO_TIMEOUT_V 0xFF +#define UHCI_TXFIFO_TIMEOUT_S 0 -#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28) +#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x2C) +/* UHCI_ACK_NUM_LOAD : WO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define UHCI_ACK_NUM_LOAD (BIT(3)) +#define UHCI_ACK_NUM_LOAD_M (BIT(3)) +#define UHCI_ACK_NUM_LOAD_V 0x1 +#define UHCI_ACK_NUM_LOAD_S 3 +/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: .*/ +#define UHCI_ACK_NUM 0x00000007 +#define UHCI_ACK_NUM_M ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S)) +#define UHCI_ACK_NUM_V 0x7 +#define UHCI_ACK_NUM_S 0 -#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2C) +#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x30) /* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_RX_HEAD 0xFFFFFFFF -#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V) << (UHCI_RX_HEAD_S)) -#define UHCI_RX_HEAD_V 0xFFFFFFFF -#define UHCI_RX_HEAD_S 0 +/*description: .*/ +#define UHCI_RX_HEAD 0xFFFFFFFF +#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S)) +#define UHCI_RX_HEAD_V 0xFFFFFFFF +#define UHCI_RX_HEAD_S 0 -#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30) +#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x34) /* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_ALWAYS_SEND_EN (BIT(7)) -#define UHCI_ALWAYS_SEND_EN_M (BIT(7)) -#define UHCI_ALWAYS_SEND_EN_V 0x1 -#define UHCI_ALWAYS_SEND_EN_S 7 +/*description: .*/ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_V 0x1 +#define UHCI_ALWAYS_SEND_EN_S 7 /* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: */ -#define UHCI_ALWAYS_SEND_NUM 0x00000007 -#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V) << (UHCI_ALWAYS_SEND_NUM_S)) -#define UHCI_ALWAYS_SEND_NUM_V 0x7 -#define UHCI_ALWAYS_SEND_NUM_S 4 +/*description: .*/ +#define UHCI_ALWAYS_SEND_NUM 0x00000007 +#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S)) +#define UHCI_ALWAYS_SEND_NUM_V 0x7 +#define UHCI_ALWAYS_SEND_NUM_S 4 /* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define UHCI_SINGLE_SEND_EN (BIT(3)) -#define UHCI_SINGLE_SEND_EN_M (BIT(3)) -#define UHCI_SINGLE_SEND_EN_V 0x1 -#define UHCI_SINGLE_SEND_EN_S 3 +/*description: .*/ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (BIT(3)) +#define UHCI_SINGLE_SEND_EN_V 0x1 +#define UHCI_SINGLE_SEND_EN_S 3 /* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: */ -#define UHCI_SINGLE_SEND_NUM 0x00000007 -#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V) << (UHCI_SINGLE_SEND_NUM_S)) -#define UHCI_SINGLE_SEND_NUM_V 0x7 -#define UHCI_SINGLE_SEND_NUM_S 0 +/*description: .*/ +#define UHCI_SINGLE_SEND_NUM 0x00000007 +#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S)) +#define UHCI_SINGLE_SEND_NUM_V 0x7 +#define UHCI_SINGLE_SEND_NUM_S 0 -#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34) +#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x38) /* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V) << (UHCI_SEND_Q0_WORD0_S)) -#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q0_WORD0_S 0 +/*description: .*/ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S)) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_S 0 -#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38) +#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x3C) /* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V) << (UHCI_SEND_Q0_WORD1_S)) -#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q0_WORD1_S 0 +/*description: .*/ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S)) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_S 0 -#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3C) +#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x40) /* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V) << (UHCI_SEND_Q1_WORD0_S)) -#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q1_WORD0_S 0 +/*description: .*/ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S)) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_S 0 -#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40) +#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x44) /* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V) << (UHCI_SEND_Q1_WORD1_S)) -#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q1_WORD1_S 0 +/*description: .*/ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S)) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_S 0 -#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44) +#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x48) /* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V) << (UHCI_SEND_Q2_WORD0_S)) -#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q2_WORD0_S 0 +/*description: .*/ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S)) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_S 0 -#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48) +#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x4C) /* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V) << (UHCI_SEND_Q2_WORD1_S)) -#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q2_WORD1_S 0 +/*description: .*/ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S)) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_S 0 -#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4C) +#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x50) /* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V) << (UHCI_SEND_Q3_WORD0_S)) -#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q3_WORD0_S 0 +/*description: .*/ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S)) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_S 0 -#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50) +#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x54) /* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V) << (UHCI_SEND_Q3_WORD1_S)) -#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q3_WORD1_S 0 +/*description: .*/ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S)) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_S 0 -#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54) +#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x58) /* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V) << (UHCI_SEND_Q4_WORD0_S)) -#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q4_WORD0_S 0 +/*description: .*/ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S)) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_S 0 -#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58) +#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x5C) /* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V) << (UHCI_SEND_Q4_WORD1_S)) -#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q4_WORD1_S 0 +/*description: .*/ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S)) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_S 0 -#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5C) +#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x60) /* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V) << (UHCI_SEND_Q5_WORD0_S)) -#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q5_WORD0_S 0 +/*description: .*/ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S)) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_S 0 -#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60) +#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x64) /* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V) << (UHCI_SEND_Q5_WORD1_S)) -#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q5_WORD1_S 0 +/*description: .*/ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S)) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_S 0 -#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64) +#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x68) /* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V) << (UHCI_SEND_Q6_WORD0_S)) -#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q6_WORD0_S 0 +/*description: .*/ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S)) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_S 0 -#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68) +#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x6C) /* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V) << (UHCI_SEND_Q6_WORD1_S)) -#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q6_WORD1_S 0 +/*description: .*/ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S)) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_S 0 -#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6C) +#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x70) /* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */ -/*description: */ -#define UHCI_SEPER_ESC_CHAR1 0x000000FF -#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V) << (UHCI_SEPER_ESC_CHAR1_S)) -#define UHCI_SEPER_ESC_CHAR1_V 0xFF -#define UHCI_SEPER_ESC_CHAR1_S 16 +/*description: .*/ +#define UHCI_SEPER_ESC_CHAR1 0x000000FF +#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S)) +#define UHCI_SEPER_ESC_CHAR1_V 0xFF +#define UHCI_SEPER_ESC_CHAR1_S 16 /* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ -/*description: */ -#define UHCI_SEPER_ESC_CHAR0 0x000000FF -#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V) << (UHCI_SEPER_ESC_CHAR0_S)) -#define UHCI_SEPER_ESC_CHAR0_V 0xFF -#define UHCI_SEPER_ESC_CHAR0_S 8 +/*description: .*/ +#define UHCI_SEPER_ESC_CHAR0 0x000000FF +#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S)) +#define UHCI_SEPER_ESC_CHAR0_V 0xFF +#define UHCI_SEPER_ESC_CHAR0_S 8 /* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ -/*description: */ -#define UHCI_SEPER_CHAR 0x000000FF -#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V) << (UHCI_SEPER_CHAR_S)) -#define UHCI_SEPER_CHAR_V 0xFF -#define UHCI_SEPER_CHAR_S 0 +/*description: .*/ +#define UHCI_SEPER_CHAR 0x000000FF +#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S)) +#define UHCI_SEPER_CHAR_V 0xFF +#define UHCI_SEPER_CHAR_S 0 -#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70) +#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x74) /* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */ -/*description: */ -#define UHCI_ESC_SEQ0_CHAR1 0x000000FF -#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V) << (UHCI_ESC_SEQ0_CHAR1_S)) -#define UHCI_ESC_SEQ0_CHAR1_V 0xFF -#define UHCI_ESC_SEQ0_CHAR1_S 16 +/*description: .*/ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FF +#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S)) +#define UHCI_ESC_SEQ0_CHAR1_V 0xFF +#define UHCI_ESC_SEQ0_CHAR1_S 16 /* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ -/*description: */ -#define UHCI_ESC_SEQ0_CHAR0 0x000000FF -#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V) << (UHCI_ESC_SEQ0_CHAR0_S)) -#define UHCI_ESC_SEQ0_CHAR0_V 0xFF -#define UHCI_ESC_SEQ0_CHAR0_S 8 +/*description: .*/ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FF +#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S)) +#define UHCI_ESC_SEQ0_CHAR0_V 0xFF +#define UHCI_ESC_SEQ0_CHAR0_S 8 /* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */ -/*description: */ -#define UHCI_ESC_SEQ0 0x000000FF -#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V) << (UHCI_ESC_SEQ0_S)) -#define UHCI_ESC_SEQ0_V 0xFF -#define UHCI_ESC_SEQ0_S 0 +/*description: .*/ +#define UHCI_ESC_SEQ0 0x000000FF +#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S)) +#define UHCI_ESC_SEQ0_V 0xFF +#define UHCI_ESC_SEQ0_S 0 -#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74) +#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x78) /* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */ -/*description: */ -#define UHCI_ESC_SEQ1_CHAR1 0x000000FF -#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V) << (UHCI_ESC_SEQ1_CHAR1_S)) -#define UHCI_ESC_SEQ1_CHAR1_V 0xFF -#define UHCI_ESC_SEQ1_CHAR1_S 16 +/*description: .*/ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FF +#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S)) +#define UHCI_ESC_SEQ1_CHAR1_V 0xFF +#define UHCI_ESC_SEQ1_CHAR1_S 16 /* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ -/*description: */ -#define UHCI_ESC_SEQ1_CHAR0 0x000000FF -#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V) << (UHCI_ESC_SEQ1_CHAR0_S)) -#define UHCI_ESC_SEQ1_CHAR0_V 0xFF -#define UHCI_ESC_SEQ1_CHAR0_S 8 +/*description: .*/ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FF +#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S)) +#define UHCI_ESC_SEQ1_CHAR0_V 0xFF +#define UHCI_ESC_SEQ1_CHAR0_S 8 /* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */ -/*description: */ -#define UHCI_ESC_SEQ1 0x000000FF -#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V) << (UHCI_ESC_SEQ1_S)) -#define UHCI_ESC_SEQ1_V 0xFF -#define UHCI_ESC_SEQ1_S 0 +/*description: .*/ +#define UHCI_ESC_SEQ1 0x000000FF +#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S)) +#define UHCI_ESC_SEQ1_V 0xFF +#define UHCI_ESC_SEQ1_S 0 -#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78) +#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x7C) /* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */ -/*description: */ -#define UHCI_ESC_SEQ2_CHAR1 0x000000FF -#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V) << (UHCI_ESC_SEQ2_CHAR1_S)) -#define UHCI_ESC_SEQ2_CHAR1_V 0xFF -#define UHCI_ESC_SEQ2_CHAR1_S 16 +/*description: .*/ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FF +#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S)) +#define UHCI_ESC_SEQ2_CHAR1_V 0xFF +#define UHCI_ESC_SEQ2_CHAR1_S 16 /* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ -/*description: */ -#define UHCI_ESC_SEQ2_CHAR0 0x000000FF -#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V) << (UHCI_ESC_SEQ2_CHAR0_S)) -#define UHCI_ESC_SEQ2_CHAR0_V 0xFF -#define UHCI_ESC_SEQ2_CHAR0_S 8 +/*description: .*/ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FF +#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S)) +#define UHCI_ESC_SEQ2_CHAR0_V 0xFF +#define UHCI_ESC_SEQ2_CHAR0_S 8 /* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */ -/*description: */ -#define UHCI_ESC_SEQ2 0x000000FF -#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V) << (UHCI_ESC_SEQ2_S)) -#define UHCI_ESC_SEQ2_V 0xFF -#define UHCI_ESC_SEQ2_S 0 +/*description: .*/ +#define UHCI_ESC_SEQ2 0x000000FF +#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S)) +#define UHCI_ESC_SEQ2_V 0xFF +#define UHCI_ESC_SEQ2_S 0 -#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7C) +#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x80) /* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */ -/*description: */ -#define UHCI_PKT_THRS 0x00001FFF -#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V) << (UHCI_PKT_THRS_S)) -#define UHCI_PKT_THRS_V 0x1FFF -#define UHCI_PKT_THRS_S 0 +/*description: .*/ +#define UHCI_PKT_THRS 0x00001FFF +#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S)) +#define UHCI_PKT_THRS_V 0x1FFF +#define UHCI_PKT_THRS_S 0 + +#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x84) +/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2010090 ; */ +/*description: .*/ +#define UHCI_DATE 0xFFFFFFFF +#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S)) +#define UHCI_DATE_V 0xFFFFFFFF +#define UHCI_DATE_S 0 -#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80) -/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2001182 ; */ -/*description: */ -#define UHCI_DATE 0xFFFFFFFF -#define UHCI_DATE_M ((UHCI_DATE_V) << (UHCI_DATE_S)) -#define UHCI_DATE_V 0xFFFFFFFF -#define UHCI_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_UHCI_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/uhci_struct.h b/components/soc/esp32s3/include/soc/uhci_struct.h index 36fe3d78b4..90e2ad6fe3 100644 --- a/components/soc/esp32s3/include/soc/uhci_struct.h +++ b/components/soc/esp32s3/include/soc/uhci_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,203 +11,233 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _SOC_UHCI_STRUCT_H_ +#define _SOC_UHCI_STRUCT_H_ + #ifdef __cplusplus extern "C" { #endif - -#include +#include "soc.h" typedef volatile struct { union { struct { - uint32_t tx_rst: 1; - uint32_t rx_rst: 1; - uint32_t uart0_ce: 1; - uint32_t uart1_ce: 1; - uint32_t uart2_ce: 1; - uint32_t seper_en: 1; - uint32_t head_en: 1; - uint32_t crc_rec_en: 1; - uint32_t uart_idle_eof_en: 1; - uint32_t len_eof_en: 1; - uint32_t encode_crc_en: 1; - uint32_t clk_en: 1; - uint32_t uart_rx_brk_eof_en: 1; - uint32_t reserved13: 19; + uint32_t tx_rst : 1; + uint32_t rx_rst : 1; + uint32_t uart0_ce : 1; + uint32_t uart1_ce : 1; + uint32_t uart2_ce : 1; + uint32_t seper_en : 1; + uint32_t head_en : 1; + uint32_t crc_rec_en : 1; + uint32_t uart_idle_eof_en : 1; + uint32_t len_eof_en : 1; + uint32_t encode_crc_en : 1; + uint32_t clk_en : 1; + uint32_t uart_rx_brk_eof_en : 1; + uint32_t reserved13 : 19; }; uint32_t val; } conf0; union { struct { - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_hung: 1; - uint32_t tx_hung: 1; - uint32_t send_s_q: 1; - uint32_t send_a_q: 1; - uint32_t reserved6: 26; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_hung : 1; + uint32_t tx_hung : 1; + uint32_t send_s_q : 1; + uint32_t send_a_q : 1; + uint32_t outlink_eof_err : 1; + uint32_t app_ctrl0 : 1; + uint32_t app_ctrl1 : 1; + uint32_t reserved9 : 23; }; uint32_t val; } int_raw; union { struct { - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_hung: 1; - uint32_t tx_hung: 1; - uint32_t send_s_q: 1; - uint32_t send_a_q: 1; - uint32_t reserved6: 26; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_hung : 1; + uint32_t tx_hung : 1; + uint32_t send_s_q : 1; + uint32_t send_a_q : 1; + uint32_t outlink_eof_err : 1; + uint32_t app_ctrl0 : 1; + uint32_t app_ctrl1 : 1; + uint32_t reserved9 : 23; }; uint32_t val; } int_st; union { struct { - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_hung: 1; - uint32_t tx_hung: 1; - uint32_t send_s_q: 1; - uint32_t send_a_q: 1; - uint32_t reserved6: 26; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_hung : 1; + uint32_t tx_hung : 1; + uint32_t send_s_q : 1; + uint32_t send_a_q : 1; + uint32_t outlink_eof_err : 1; + uint32_t app_ctrl0 : 1; + uint32_t app_ctrl1 : 1; + uint32_t reserved9 : 23; }; uint32_t val; } int_ena; union { struct { - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_hung: 1; - uint32_t tx_hung: 1; - uint32_t send_s_q: 1; - uint32_t send_a_q: 1; - uint32_t reserved6: 26; + uint32_t rx_start : 1; + uint32_t tx_start : 1; + uint32_t rx_hung : 1; + uint32_t tx_hung : 1; + uint32_t send_s_q : 1; + uint32_t send_a_q : 1; + uint32_t outlink_eof_err : 1; + uint32_t app_ctrl0 : 1; + uint32_t app_ctrl1 : 1; + uint32_t reserved9 : 23; }; uint32_t val; } int_clr; union { struct { - uint32_t check_sum_en: 1; - uint32_t check_seq_en: 1; - uint32_t crc_disable: 1; - uint32_t save_head: 1; - uint32_t tx_check_sum_re: 1; - uint32_t tx_ack_num_re: 1; - uint32_t reserved6: 1; - uint32_t wait_sw_start: 1; - uint32_t sw_start: 1; - uint32_t reserved9: 12; - uint32_t reserved21: 11; + uint32_t app_ctrl0_int_set : 1; + uint32_t app_ctrl1_int_set : 1; + uint32_t reserved2 : 30; + }; + uint32_t val; + } app_int_set; + union { + struct { + uint32_t check_sum_en : 1; + uint32_t check_seq_en : 1; + uint32_t crc_disable : 1; + uint32_t save_head : 1; + uint32_t tx_check_sum_re : 1; + uint32_t tx_ack_num_re : 1; + uint32_t reserved6 : 1; + uint32_t wait_sw_start : 1; + uint32_t sw_start : 1; + uint32_t reserved9 : 12; + uint32_t reserved21 : 11; }; uint32_t val; } conf1; union { struct { - uint32_t rx_err_cause: 3; - uint32_t decode_state: 3; - uint32_t reserved6: 26; + uint32_t rx_err_cause : 3; + uint32_t decode_state : 3; + uint32_t reserved6 : 26; }; uint32_t val; } state0; union { struct { - uint32_t encode_state: 3; - uint32_t reserved3: 29; + uint32_t encode_state : 3; + uint32_t reserved3 : 29; }; uint32_t val; } state1; union { struct { - uint32_t tx_c0_esc_en: 1; - uint32_t tx_db_esc_en: 1; - uint32_t tx_11_esc_en: 1; - uint32_t tx_13_esc_en: 1; - uint32_t rx_c0_esc_en: 1; - uint32_t rx_db_esc_en: 1; - uint32_t rx_11_esc_en: 1; - uint32_t rx_13_esc_en: 1; - uint32_t reserved8: 24; + uint32_t tx_c0_esc_en : 1; + uint32_t tx_db_esc_en : 1; + uint32_t tx_11_esc_en : 1; + uint32_t tx_13_esc_en : 1; + uint32_t rx_c0_esc_en : 1; + uint32_t rx_db_esc_en : 1; + uint32_t rx_11_esc_en : 1; + uint32_t rx_13_esc_en : 1; + uint32_t reserved8 : 24; }; uint32_t val; } escape_conf; union { struct { - uint32_t txfifo_timeout: 8; - uint32_t txfifo_timeout_shift: 3; - uint32_t txfifo_timeout_ena: 1; - uint32_t rxfifo_timeout: 8; - uint32_t rxfifo_timeout_shift: 3; - uint32_t rxfifo_timeout_ena: 1; - uint32_t reserved24: 8; + uint32_t txfifo_timeout : 8; + uint32_t txfifo_timeout_shift : 3; + uint32_t txfifo_timeout_ena : 1; + uint32_t rxfifo_timeout : 8; + uint32_t rxfifo_timeout_shift : 3; + uint32_t rxfifo_timeout_ena : 1; + uint32_t reserved24 : 8; }; uint32_t val; } hung_conf; - uint32_t ack_num; /**/ - uint32_t rx_head; /**/ union { struct { - uint32_t single_send_num: 3; - uint32_t single_send_en: 1; - uint32_t always_send_num: 3; - uint32_t always_send_en: 1; - uint32_t reserved8: 24; + uint32_t ack_num : 3; + uint32_t ack_num_load : 1; + uint32_t reserved4 : 28; + }; + uint32_t val; + } ack_num; + uint32_t rx_head; + union { + struct { + uint32_t single_send_num : 3; + uint32_t single_send_en : 1; + uint32_t always_send_num : 3; + uint32_t always_send_en : 1; + uint32_t reserved8 : 24; }; uint32_t val; } quick_sent; struct { - uint32_t w_data[2]; /**/ + uint32_t word[2]; } q_data[7]; union { struct { - uint32_t seper_char: 8; - uint32_t seper_esc_char0: 8; - uint32_t seper_esc_char1: 8; - uint32_t reserved24: 8; + uint32_t seper_char : 8; + uint32_t seper_esc_char0 : 8; + uint32_t seper_esc_char1 : 8; + uint32_t reserved24 : 8; }; uint32_t val; } esc_conf0; union { struct { - uint32_t seq0: 8; - uint32_t seq0_char0: 8; - uint32_t seq0_char1: 8; - uint32_t reserved24: 8; + uint32_t seq0 : 8; + uint32_t seq0_char0 : 8; + uint32_t seq0_char1 : 8; + uint32_t reserved24 : 8; }; uint32_t val; } esc_conf1; union { struct { - uint32_t seq1: 8; - uint32_t seq1_char0: 8; - uint32_t seq1_char1: 8; - uint32_t reserved24: 8; + uint32_t seq1 : 8; + uint32_t seq1_char0 : 8; + uint32_t seq1_char1 : 8; + uint32_t reserved24 : 8; }; uint32_t val; } esc_conf2; union { struct { - uint32_t seq2: 8; - uint32_t seq2_char0: 8; - uint32_t seq2_char1: 8; - uint32_t reserved24: 8; + uint32_t seq2 : 8; + uint32_t seq2_char0 : 8; + uint32_t seq2_char1 : 8; + uint32_t reserved24 : 8; }; uint32_t val; } esc_conf3; union { struct { - uint32_t thrs: 13; - uint32_t reserved13: 19; + uint32_t thrs : 13; + uint32_t reserved13 : 19; }; uint32_t val; } pkt_thres; - uint32_t date; /**/ + uint32_t date; } uhci_dev_t; - extern uhci_dev_t UHCI0; extern uhci_dev_t UHCI1; - #ifdef __cplusplus } #endif + + + +#endif /*_SOC_UHCI_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/usb_caps.h b/components/soc/esp32s3/include/soc/usb_caps.h new file mode 100644 index 0000000000..820e98a4dd --- /dev/null +++ b/components/soc/esp32s3/include/soc/usb_caps.h @@ -0,0 +1,17 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_USB_PERIPH_NUM 1 diff --git a/components/soc/esp32s3/include/soc/usb_device_reg.h b/components/soc/esp32s3/include/soc/usb_device_reg.h new file mode 100644 index 0000000000..3ffe3a260a --- /dev/null +++ b/components/soc/esp32s3/include/soc/usb_device_reg.h @@ -0,0 +1,737 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_USB_DEVICE_REG_H_ +#define _SOC_USB_DEVICE_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) +/* USB_DEVICE_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE +VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into +UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB +_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is rece +ived, then read data from UART Rx FIFO..*/ +#define USB_DEVICE_RDWR_BYTE 0x000000FF +#define USB_DEVICE_RDWR_BYTE_M ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S)) +#define USB_DEVICE_RDWR_BYTE_V 0xFF +#define USB_DEVICE_RDWR_BYTE_S 0 + +#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) +/* USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1'b1: Indicate there is data in UART Rx FIFO..*/ +#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_M (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_V 0x1 +#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_S 2 +/* USB_DEVICE_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin +g USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by +USB Host..*/ +#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_M (BIT(1)) +#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_V 0x1 +#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_S 1 +/* USB_DEVICE_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done..*/ +#define USB_DEVICE_WR_DONE (BIT(0)) +#define USB_DEVICE_WR_DONE_M (BIT(0)) +#define USB_DEVICE_WR_DONE_V 0x1 +#define USB_DEVICE_WR_DONE_S 0 + +#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) +/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi +th zero palyload..*/ +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (BIT(11)) +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x1 +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet wi +th zero palyload..*/ +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (BIT(10)) +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x1 +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/* USB_DEVICE_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when usb bus reset is detected..*/ +#define USB_DEVICE_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_DEVICE_USB_BUS_RESET_INT_RAW_M (BIT(9)) +#define USB_DEVICE_USB_BUS_RESET_INT_RAW_V 0x1 +#define USB_DEVICE_USB_BUS_RESET_INT_RAW_S 9 +/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is rec +eived..*/ +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_M (BIT(8)) +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x1 +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/* USB_DEVICE_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when stuff error is detected..*/ +#define USB_DEVICE_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_DEVICE_STUFF_ERR_INT_RAW_M (BIT(7)) +#define USB_DEVICE_STUFF_ERR_INT_RAW_V 0x1 +#define USB_DEVICE_STUFF_ERR_INT_RAW_S 7 +/* USB_DEVICE_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when CRC16 error is detected..*/ +#define USB_DEVICE_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_DEVICE_CRC16_ERR_INT_RAW_M (BIT(6)) +#define USB_DEVICE_CRC16_ERR_INT_RAW_V 0x1 +#define USB_DEVICE_CRC16_ERR_INT_RAW_S 6 +/* USB_DEVICE_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when CRC5 error is detected..*/ +#define USB_DEVICE_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_DEVICE_CRC5_ERR_INT_RAW_M (BIT(5)) +#define USB_DEVICE_CRC5_ERR_INT_RAW_V 0x1 +#define USB_DEVICE_CRC5_ERR_INT_RAW_S 5 +/* USB_DEVICE_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when pid error is detected..*/ +#define USB_DEVICE_PID_ERR_INT_RAW (BIT(4)) +#define USB_DEVICE_PID_ERR_INT_RAW_M (BIT(4)) +#define USB_DEVICE_PID_ERR_INT_RAW_V 0x1 +#define USB_DEVICE_PID_ERR_INT_RAW_S 4 +/* USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */ +/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty..*/ +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_M (BIT(3)) +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_V 0x1 +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_S 3 +/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + one packet..*/ +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_M (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x1 +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/* USB_DEVICE_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when SOF frame is received..*/ +#define USB_DEVICE_SOF_INT_RAW (BIT(1)) +#define USB_DEVICE_SOF_INT_RAW_M (BIT(1)) +#define USB_DEVICE_SOF_INT_RAW_V 0x1 +#define USB_DEVICE_SOF_INT_RAW_S 1 +/* USB_DEVICE_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp +oint 2 of JTAG..*/ +#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_M (BIT(0)) +#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_V 0x1 +#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_S 0 + +#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xC) +/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interru +pt..*/ +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (BIT(11)) +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x1 +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interru +pt..*/ +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (BIT(10)) +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x1 +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/* USB_DEVICE_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/ +#define USB_DEVICE_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_DEVICE_USB_BUS_RESET_INT_ST_M (BIT(9)) +#define USB_DEVICE_USB_BUS_RESET_INT_ST_V 0x1 +#define USB_DEVICE_USB_BUS_RESET_INT_ST_S 9 +/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrup +t..*/ +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8)) +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x1 +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/* USB_DEVICE_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt..*/ +#define USB_DEVICE_STUFF_ERR_INT_ST (BIT(7)) +#define USB_DEVICE_STUFF_ERR_INT_ST_M (BIT(7)) +#define USB_DEVICE_STUFF_ERR_INT_ST_V 0x1 +#define USB_DEVICE_STUFF_ERR_INT_ST_S 7 +/* USB_DEVICE_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt..*/ +#define USB_DEVICE_CRC16_ERR_INT_ST (BIT(6)) +#define USB_DEVICE_CRC16_ERR_INT_ST_M (BIT(6)) +#define USB_DEVICE_CRC16_ERR_INT_ST_V 0x1 +#define USB_DEVICE_CRC16_ERR_INT_ST_S 6 +/* USB_DEVICE_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt..*/ +#define USB_DEVICE_CRC5_ERR_INT_ST (BIT(5)) +#define USB_DEVICE_CRC5_ERR_INT_ST_M (BIT(5)) +#define USB_DEVICE_CRC5_ERR_INT_ST_V 0x1 +#define USB_DEVICE_CRC5_ERR_INT_ST_S 5 +/* USB_DEVICE_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt..*/ +#define USB_DEVICE_PID_ERR_INT_ST (BIT(4)) +#define USB_DEVICE_PID_ERR_INT_ST_M (BIT(4)) +#define USB_DEVICE_PID_ERR_INT_ST_V 0x1 +#define USB_DEVICE_PID_ERR_INT_ST_S 4 +/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/ +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_M (BIT(3)) +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_V 0x1 +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_S 3 +/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrup +t..*/ +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_V 0x1 +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/* USB_DEVICE_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt..*/ +#define USB_DEVICE_SOF_INT_ST (BIT(1)) +#define USB_DEVICE_SOF_INT_ST_M (BIT(1)) +#define USB_DEVICE_SOF_INT_ST_V 0x1 +#define USB_DEVICE_SOF_INT_ST_S 1 +/* USB_DEVICE_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/ +#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_M (BIT(0)) +#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_V 0x1 +#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_S 0 + +#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) +/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/ +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (BIT(11)) +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x1 +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/ +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (BIT(10)) +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x1 +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/* USB_DEVICE_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/ +#define USB_DEVICE_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_DEVICE_USB_BUS_RESET_INT_ENA_M (BIT(9)) +#define USB_DEVICE_USB_BUS_RESET_INT_ENA_V 0x1 +#define USB_DEVICE_USB_BUS_RESET_INT_ENA_S 9 +/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt..*/ +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_M (BIT(8)) +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x1 +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/* USB_DEVICE_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt..*/ +#define USB_DEVICE_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_DEVICE_STUFF_ERR_INT_ENA_M (BIT(7)) +#define USB_DEVICE_STUFF_ERR_INT_ENA_V 0x1 +#define USB_DEVICE_STUFF_ERR_INT_ENA_S 7 +/* USB_DEVICE_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt..*/ +#define USB_DEVICE_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_DEVICE_CRC16_ERR_INT_ENA_M (BIT(6)) +#define USB_DEVICE_CRC16_ERR_INT_ENA_V 0x1 +#define USB_DEVICE_CRC16_ERR_INT_ENA_S 6 +/* USB_DEVICE_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt..*/ +#define USB_DEVICE_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_DEVICE_CRC5_ERR_INT_ENA_M (BIT(5)) +#define USB_DEVICE_CRC5_ERR_INT_ENA_V 0x1 +#define USB_DEVICE_CRC5_ERR_INT_ENA_S 5 +/* USB_DEVICE_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt..*/ +#define USB_DEVICE_PID_ERR_INT_ENA (BIT(4)) +#define USB_DEVICE_PID_ERR_INT_ENA_M (BIT(4)) +#define USB_DEVICE_PID_ERR_INT_ENA_V 0x1 +#define USB_DEVICE_PID_ERR_INT_ENA_S 4 +/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/ +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_M (BIT(3)) +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_V 0x1 +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_S 3 +/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt..*/ +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_M (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x1 +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/* USB_DEVICE_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt..*/ +#define USB_DEVICE_SOF_INT_ENA (BIT(1)) +#define USB_DEVICE_SOF_INT_ENA_M (BIT(1)) +#define USB_DEVICE_SOF_INT_ENA_V 0x1 +#define USB_DEVICE_SOF_INT_ENA_S 1 +/* USB_DEVICE_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/ +#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_M (BIT(0)) +#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_V 0x1 +#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_S 0 + +#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) +/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/ +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (BIT(11)) +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x1 +#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/ +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (BIT(10)) +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x1 +#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/* USB_DEVICE_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/ +#define USB_DEVICE_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_DEVICE_USB_BUS_RESET_INT_CLR_M (BIT(9)) +#define USB_DEVICE_USB_BUS_RESET_INT_CLR_V 0x1 +#define USB_DEVICE_USB_BUS_RESET_INT_CLR_S 9 +/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt..*/ +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_M (BIT(8)) +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x1 +#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/* USB_DEVICE_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt..*/ +#define USB_DEVICE_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_DEVICE_STUFF_ERR_INT_CLR_M (BIT(7)) +#define USB_DEVICE_STUFF_ERR_INT_CLR_V 0x1 +#define USB_DEVICE_STUFF_ERR_INT_CLR_S 7 +/* USB_DEVICE_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt..*/ +#define USB_DEVICE_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_DEVICE_CRC16_ERR_INT_CLR_M (BIT(6)) +#define USB_DEVICE_CRC16_ERR_INT_CLR_V 0x1 +#define USB_DEVICE_CRC16_ERR_INT_CLR_S 6 +/* USB_DEVICE_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt..*/ +#define USB_DEVICE_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_DEVICE_CRC5_ERR_INT_CLR_M (BIT(5)) +#define USB_DEVICE_CRC5_ERR_INT_CLR_V 0x1 +#define USB_DEVICE_CRC5_ERR_INT_CLR_S 5 +/* USB_DEVICE_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt..*/ +#define USB_DEVICE_PID_ERR_INT_CLR (BIT(4)) +#define USB_DEVICE_PID_ERR_INT_CLR_M (BIT(4)) +#define USB_DEVICE_PID_ERR_INT_CLR_V 0x1 +#define USB_DEVICE_PID_ERR_INT_CLR_S 4 +/* USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/ +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_M (BIT(3)) +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_V 0x1 +#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_S 3 +/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt..*/ +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_M (BIT(2)) +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x1 +#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/* USB_DEVICE_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt..*/ +#define USB_DEVICE_SOF_INT_CLR (BIT(1)) +#define USB_DEVICE_SOF_INT_CLR_M (BIT(1)) +#define USB_DEVICE_SOF_INT_CLR_V 0x1 +#define USB_DEVICE_SOF_INT_CLR_S 1 +/* USB_DEVICE_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/ +#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_M (BIT(0)) +#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_V 0x1 +#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_S 0 + +#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) +/* USB_DEVICE_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 0: TX output at clock negedge. 1: Tx output at clock posedge..*/ +#define USB_DEVICE_PHY_TX_EDGE_SEL (BIT(15)) +#define USB_DEVICE_PHY_TX_EDGE_SEL_M (BIT(15)) +#define USB_DEVICE_PHY_TX_EDGE_SEL_V 0x1 +#define USB_DEVICE_PHY_TX_EDGE_SEL_S 15 +/* USB_DEVICE_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: Enable USB pad function..*/ +#define USB_DEVICE_USB_PAD_ENABLE (BIT(14)) +#define USB_DEVICE_USB_PAD_ENABLE_M (BIT(14)) +#define USB_DEVICE_USB_PAD_ENABLE_V 0x1 +#define USB_DEVICE_USB_PAD_ENABLE_S 14 +/* USB_DEVICE_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Control pull up value..*/ +#define USB_DEVICE_PULLUP_VALUE (BIT(13)) +#define USB_DEVICE_PULLUP_VALUE_M (BIT(13)) +#define USB_DEVICE_PULLUP_VALUE_V 0x1 +#define USB_DEVICE_PULLUP_VALUE_S 13 +/* USB_DEVICE_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Control USB D- pull down..*/ +#define USB_DEVICE_DM_PULLDOWN (BIT(12)) +#define USB_DEVICE_DM_PULLDOWN_M (BIT(12)) +#define USB_DEVICE_DM_PULLDOWN_V 0x1 +#define USB_DEVICE_DM_PULLDOWN_S 12 +/* USB_DEVICE_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Control USB D- pull up..*/ +#define USB_DEVICE_DM_PULLUP (BIT(11)) +#define USB_DEVICE_DM_PULLUP_M (BIT(11)) +#define USB_DEVICE_DM_PULLUP_V 0x1 +#define USB_DEVICE_DM_PULLUP_S 11 +/* USB_DEVICE_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Control USB D+ pull down..*/ +#define USB_DEVICE_DP_PULLDOWN (BIT(10)) +#define USB_DEVICE_DP_PULLDOWN_M (BIT(10)) +#define USB_DEVICE_DP_PULLDOWN_V 0x1 +#define USB_DEVICE_DP_PULLDOWN_S 10 +/* USB_DEVICE_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: Control USB D+ pull up..*/ +#define USB_DEVICE_DP_PULLUP (BIT(9)) +#define USB_DEVICE_DP_PULLUP_M (BIT(9)) +#define USB_DEVICE_DP_PULLUP_V 0x1 +#define USB_DEVICE_DP_PULLUP_S 9 +/* USB_DEVICE_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Enable software control USB D+ D- pullup pulldown.*/ +#define USB_DEVICE_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_DEVICE_PAD_PULL_OVERRIDE_M (BIT(8)) +#define USB_DEVICE_PAD_PULL_OVERRIDE_V 0x1 +#define USB_DEVICE_PAD_PULL_OVERRIDE_S 8 +/* USB_DEVICE_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Enable software control input threshold.*/ +#define USB_DEVICE_VREF_OVERRIDE (BIT(7)) +#define USB_DEVICE_VREF_OVERRIDE_M (BIT(7)) +#define USB_DEVICE_VREF_OVERRIDE_V 0x1 +#define USB_DEVICE_VREF_OVERRIDE_S 7 +/* USB_DEVICE_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ +/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/ +#define USB_DEVICE_VREFL 0x00000003 +#define USB_DEVICE_VREFL_M ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S)) +#define USB_DEVICE_VREFL_V 0x3 +#define USB_DEVICE_VREFL_S 5 +/* USB_DEVICE_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/ +#define USB_DEVICE_VREFH 0x00000003 +#define USB_DEVICE_VREFH_M ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S)) +#define USB_DEVICE_VREFH_V 0x3 +#define USB_DEVICE_VREFH_S 3 +/* USB_DEVICE_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: USB D+ D- exchange.*/ +#define USB_DEVICE_EXCHG_PINS (BIT(2)) +#define USB_DEVICE_EXCHG_PINS_M (BIT(2)) +#define USB_DEVICE_EXCHG_PINS_V 0x1 +#define USB_DEVICE_EXCHG_PINS_S 2 +/* USB_DEVICE_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Enable software control USB D+ D- exchange.*/ +#define USB_DEVICE_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_DEVICE_EXCHG_PINS_OVERRIDE_M (BIT(1)) +#define USB_DEVICE_EXCHG_PINS_OVERRIDE_V 0x1 +#define USB_DEVICE_EXCHG_PINS_OVERRIDE_S 1 +/* USB_DEVICE_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Select internal/external PHY.*/ +#define USB_DEVICE_PHY_SEL (BIT(0)) +#define USB_DEVICE_PHY_SEL_M (BIT(0)) +#define USB_DEVICE_PHY_SEL_V 0x1 +#define USB_DEVICE_PHY_SEL_S 0 + +#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1C) +/* USB_DEVICE_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: USB D- rx value in test.*/ +#define USB_DEVICE_TEST_RX_DM (BIT(6)) +#define USB_DEVICE_TEST_RX_DM_M (BIT(6)) +#define USB_DEVICE_TEST_RX_DM_V 0x1 +#define USB_DEVICE_TEST_RX_DM_S 6 +/* USB_DEVICE_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: USB D+ rx value in test.*/ +#define USB_DEVICE_TEST_RX_DP (BIT(5)) +#define USB_DEVICE_TEST_RX_DP_M (BIT(5)) +#define USB_DEVICE_TEST_RX_DP_V 0x1 +#define USB_DEVICE_TEST_RX_DP_S 5 +/* USB_DEVICE_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: USB differential rx value in test.*/ +#define USB_DEVICE_TEST_RX_RCV (BIT(4)) +#define USB_DEVICE_TEST_RX_RCV_M (BIT(4)) +#define USB_DEVICE_TEST_RX_RCV_V 0x1 +#define USB_DEVICE_TEST_RX_RCV_S 4 +/* USB_DEVICE_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: USB D- tx value in test.*/ +#define USB_DEVICE_TEST_TX_DM (BIT(3)) +#define USB_DEVICE_TEST_TX_DM_M (BIT(3)) +#define USB_DEVICE_TEST_TX_DM_V 0x1 +#define USB_DEVICE_TEST_TX_DM_S 3 +/* USB_DEVICE_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: USB D+ tx value in test.*/ +#define USB_DEVICE_TEST_TX_DP (BIT(2)) +#define USB_DEVICE_TEST_TX_DP_M (BIT(2)) +#define USB_DEVICE_TEST_TX_DP_V 0x1 +#define USB_DEVICE_TEST_TX_DP_S 2 +/* USB_DEVICE_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: USB pad oen in test.*/ +#define USB_DEVICE_TEST_USB_OE (BIT(1)) +#define USB_DEVICE_TEST_USB_OE_M (BIT(1)) +#define USB_DEVICE_TEST_USB_OE_V 0x1 +#define USB_DEVICE_TEST_USB_OE_S 1 +/* USB_DEVICE_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Enable test of the USB pad.*/ +#define USB_DEVICE_TEST_ENABLE (BIT(0)) +#define USB_DEVICE_TEST_ENABLE_M (BIT(0)) +#define USB_DEVICE_TEST_ENABLE_V 0x1 +#define USB_DEVICE_TEST_ENABLE_S 0 + +#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) +/* USB_DEVICE_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Write 1 to reset JTAG out fifo..*/ +#define USB_DEVICE_OUT_FIFO_RESET (BIT(9)) +#define USB_DEVICE_OUT_FIFO_RESET_M (BIT(9)) +#define USB_DEVICE_OUT_FIFO_RESET_V 0x1 +#define USB_DEVICE_OUT_FIFO_RESET_S 9 +/* USB_DEVICE_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Write 1 to reset JTAG in fifo..*/ +#define USB_DEVICE_IN_FIFO_RESET (BIT(8)) +#define USB_DEVICE_IN_FIFO_RESET_M (BIT(8)) +#define USB_DEVICE_IN_FIFO_RESET_V 0x1 +#define USB_DEVICE_IN_FIFO_RESET_S 8 +/* USB_DEVICE_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 1: JTAG out fifo is full..*/ +#define USB_DEVICE_OUT_FIFO_FULL (BIT(7)) +#define USB_DEVICE_OUT_FIFO_FULL_M (BIT(7)) +#define USB_DEVICE_OUT_FIFO_FULL_V 0x1 +#define USB_DEVICE_OUT_FIFO_FULL_S 7 +/* USB_DEVICE_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */ +/*description: 1: JTAG out fifo is empty..*/ +#define USB_DEVICE_OUT_FIFO_EMPTY (BIT(6)) +#define USB_DEVICE_OUT_FIFO_EMPTY_M (BIT(6)) +#define USB_DEVICE_OUT_FIFO_EMPTY_V 0x1 +#define USB_DEVICE_OUT_FIFO_EMPTY_S 6 +/* USB_DEVICE_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: JTAT out fifo counter..*/ +#define USB_DEVICE_OUT_FIFO_CNT 0x00000003 +#define USB_DEVICE_OUT_FIFO_CNT_M ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S)) +#define USB_DEVICE_OUT_FIFO_CNT_V 0x3 +#define USB_DEVICE_OUT_FIFO_CNT_S 4 +/* USB_DEVICE_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: JTAG in fifo is full..*/ +#define USB_DEVICE_IN_FIFO_FULL (BIT(3)) +#define USB_DEVICE_IN_FIFO_FULL_M (BIT(3)) +#define USB_DEVICE_IN_FIFO_FULL_V 0x1 +#define USB_DEVICE_IN_FIFO_FULL_S 3 +/* USB_DEVICE_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */ +/*description: 1: JTAG in fifo is empty..*/ +#define USB_DEVICE_IN_FIFO_EMPTY (BIT(2)) +#define USB_DEVICE_IN_FIFO_EMPTY_M (BIT(2)) +#define USB_DEVICE_IN_FIFO_EMPTY_V 0x1 +#define USB_DEVICE_IN_FIFO_EMPTY_S 2 +/* USB_DEVICE_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: JTAT in fifo counter..*/ +#define USB_DEVICE_IN_FIFO_CNT 0x00000003 +#define USB_DEVICE_IN_FIFO_CNT_M ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S)) +#define USB_DEVICE_IN_FIFO_CNT_V 0x3 +#define USB_DEVICE_IN_FIFO_CNT_S 0 + +#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) +/* USB_DEVICE_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */ +/*description: Frame index of received SOF frame..*/ +#define USB_DEVICE_SOF_FRAME_INDEX 0x000007FF +#define USB_DEVICE_SOF_FRAME_INDEX_M ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S)) +#define USB_DEVICE_SOF_FRAME_INDEX_V 0x7FF +#define USB_DEVICE_SOF_FRAME_INDEX_S 0 + +#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) +/* USB_DEVICE_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ +/*description: Read data address of IN endpoint 0..*/ +#define USB_DEVICE_IN_EP0_RD_ADDR 0x0000007F +#define USB_DEVICE_IN_EP0_RD_ADDR_M ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S)) +#define USB_DEVICE_IN_EP0_RD_ADDR_V 0x7F +#define USB_DEVICE_IN_EP0_RD_ADDR_S 9 +/* USB_DEVICE_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ +/*description: Write data address of IN endpoint 0..*/ +#define USB_DEVICE_IN_EP0_WR_ADDR 0x0000007F +#define USB_DEVICE_IN_EP0_WR_ADDR_M ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S)) +#define USB_DEVICE_IN_EP0_WR_ADDR_V 0x7F +#define USB_DEVICE_IN_EP0_WR_ADDR_S 2 +/* USB_DEVICE_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: State of IN Endpoint 0..*/ +#define USB_DEVICE_IN_EP0_STATE 0x00000003 +#define USB_DEVICE_IN_EP0_STATE_M ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S)) +#define USB_DEVICE_IN_EP0_STATE_V 0x3 +#define USB_DEVICE_IN_EP0_STATE_S 0 + +#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2C) +/* USB_DEVICE_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ +/*description: Read data address of IN endpoint 1..*/ +#define USB_DEVICE_IN_EP1_RD_ADDR 0x0000007F +#define USB_DEVICE_IN_EP1_RD_ADDR_M ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S)) +#define USB_DEVICE_IN_EP1_RD_ADDR_V 0x7F +#define USB_DEVICE_IN_EP1_RD_ADDR_S 9 +/* USB_DEVICE_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ +/*description: Write data address of IN endpoint 1..*/ +#define USB_DEVICE_IN_EP1_WR_ADDR 0x0000007F +#define USB_DEVICE_IN_EP1_WR_ADDR_M ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S)) +#define USB_DEVICE_IN_EP1_WR_ADDR_V 0x7F +#define USB_DEVICE_IN_EP1_WR_ADDR_S 2 +/* USB_DEVICE_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: State of IN Endpoint 1..*/ +#define USB_DEVICE_IN_EP1_STATE 0x00000003 +#define USB_DEVICE_IN_EP1_STATE_M ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S)) +#define USB_DEVICE_IN_EP1_STATE_V 0x3 +#define USB_DEVICE_IN_EP1_STATE_S 0 + +#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) +/* USB_DEVICE_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ +/*description: Read data address of IN endpoint 2..*/ +#define USB_DEVICE_IN_EP2_RD_ADDR 0x0000007F +#define USB_DEVICE_IN_EP2_RD_ADDR_M ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S)) +#define USB_DEVICE_IN_EP2_RD_ADDR_V 0x7F +#define USB_DEVICE_IN_EP2_RD_ADDR_S 9 +/* USB_DEVICE_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ +/*description: Write data address of IN endpoint 2..*/ +#define USB_DEVICE_IN_EP2_WR_ADDR 0x0000007F +#define USB_DEVICE_IN_EP2_WR_ADDR_M ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S)) +#define USB_DEVICE_IN_EP2_WR_ADDR_V 0x7F +#define USB_DEVICE_IN_EP2_WR_ADDR_S 2 +/* USB_DEVICE_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: State of IN Endpoint 2..*/ +#define USB_DEVICE_IN_EP2_STATE 0x00000003 +#define USB_DEVICE_IN_EP2_STATE_M ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S)) +#define USB_DEVICE_IN_EP2_STATE_V 0x3 +#define USB_DEVICE_IN_EP2_STATE_S 0 + +#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) +/* USB_DEVICE_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ +/*description: Read data address of IN endpoint 3..*/ +#define USB_DEVICE_IN_EP3_RD_ADDR 0x0000007F +#define USB_DEVICE_IN_EP3_RD_ADDR_M ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S)) +#define USB_DEVICE_IN_EP3_RD_ADDR_V 0x7F +#define USB_DEVICE_IN_EP3_RD_ADDR_S 9 +/* USB_DEVICE_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ +/*description: Write data address of IN endpoint 3..*/ +#define USB_DEVICE_IN_EP3_WR_ADDR 0x0000007F +#define USB_DEVICE_IN_EP3_WR_ADDR_M ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S)) +#define USB_DEVICE_IN_EP3_WR_ADDR_V 0x7F +#define USB_DEVICE_IN_EP3_WR_ADDR_S 2 +/* USB_DEVICE_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */ +/*description: State of IN Endpoint 3..*/ +#define USB_DEVICE_IN_EP3_STATE 0x00000003 +#define USB_DEVICE_IN_EP3_STATE_M ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S)) +#define USB_DEVICE_IN_EP3_STATE_V 0x3 +#define USB_DEVICE_IN_EP3_STATE_S 0 + +#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) +/* USB_DEVICE_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ +/*description: Read data address of OUT endpoint 0..*/ +#define USB_DEVICE_OUT_EP0_RD_ADDR 0x0000007F +#define USB_DEVICE_OUT_EP0_RD_ADDR_M ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S)) +#define USB_DEVICE_OUT_EP0_RD_ADDR_V 0x7F +#define USB_DEVICE_OUT_EP0_RD_ADDR_S 9 +/* USB_DEVICE_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ +/*description: Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0..*/ +#define USB_DEVICE_OUT_EP0_WR_ADDR 0x0000007F +#define USB_DEVICE_OUT_EP0_WR_ADDR_M ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S)) +#define USB_DEVICE_OUT_EP0_WR_ADDR_V 0x7F +#define USB_DEVICE_OUT_EP0_WR_ADDR_S 2 +/* USB_DEVICE_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: State of OUT Endpoint 0..*/ +#define USB_DEVICE_OUT_EP0_STATE 0x00000003 +#define USB_DEVICE_OUT_EP0_STATE_M ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S)) +#define USB_DEVICE_OUT_EP0_STATE_V 0x3 +#define USB_DEVICE_OUT_EP0_STATE_S 0 + +#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3C) +/* USB_DEVICE_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */ +/*description: Data count in OUT endpoint 1 when one packet is received..*/ +#define USB_DEVICE_OUT_EP1_REC_DATA_CNT 0x0000007F +#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_M ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S)) +#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_V 0x7F +#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_S 16 +/* USB_DEVICE_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ +/*description: Read data address of OUT endpoint 1..*/ +#define USB_DEVICE_OUT_EP1_RD_ADDR 0x0000007F +#define USB_DEVICE_OUT_EP1_RD_ADDR_M ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S)) +#define USB_DEVICE_OUT_EP1_RD_ADDR_V 0x7F +#define USB_DEVICE_OUT_EP1_RD_ADDR_S 9 +/* USB_DEVICE_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ +/*description: Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/ +#define USB_DEVICE_OUT_EP1_WR_ADDR 0x0000007F +#define USB_DEVICE_OUT_EP1_WR_ADDR_M ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S)) +#define USB_DEVICE_OUT_EP1_WR_ADDR_V 0x7F +#define USB_DEVICE_OUT_EP1_WR_ADDR_S 2 +/* USB_DEVICE_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: State of OUT Endpoint 1..*/ +#define USB_DEVICE_OUT_EP1_STATE 0x00000003 +#define USB_DEVICE_OUT_EP1_STATE_M ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S)) +#define USB_DEVICE_OUT_EP1_STATE_V 0x3 +#define USB_DEVICE_OUT_EP1_STATE_S 0 + +#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) +/* USB_DEVICE_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */ +/*description: Read data address of OUT endpoint 2..*/ +#define USB_DEVICE_OUT_EP2_RD_ADDR 0x0000007F +#define USB_DEVICE_OUT_EP2_RD_ADDR_M ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S)) +#define USB_DEVICE_OUT_EP2_RD_ADDR_V 0x7F +#define USB_DEVICE_OUT_EP2_RD_ADDR_S 9 +/* USB_DEVICE_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */ +/*description: Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is + detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/ +#define USB_DEVICE_OUT_EP2_WR_ADDR 0x0000007F +#define USB_DEVICE_OUT_EP2_WR_ADDR_M ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S)) +#define USB_DEVICE_OUT_EP2_WR_ADDR_V 0x7F +#define USB_DEVICE_OUT_EP2_WR_ADDR_S 2 +/* USB_DEVICE_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: State of OUT Endpoint 2..*/ +#define USB_DEVICE_OUT_EP2_STATE 0x00000003 +#define USB_DEVICE_OUT_EP2_STATE_M ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S)) +#define USB_DEVICE_OUT_EP2_STATE_V 0x3 +#define USB_DEVICE_OUT_EP2_STATE_S 0 + +#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) +/* USB_DEVICE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri +tes registers..*/ +#define USB_DEVICE_CLK_EN (BIT(0)) +#define USB_DEVICE_CLK_EN_M (BIT(0)) +#define USB_DEVICE_CLK_EN_V 0x1 +#define USB_DEVICE_CLK_EN_S 0 + +#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) +/* USB_DEVICE_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: 1: Force clock on for usb memory..*/ +#define USB_DEVICE_USB_MEM_CLK_EN (BIT(1)) +#define USB_DEVICE_USB_MEM_CLK_EN_M (BIT(1)) +#define USB_DEVICE_USB_MEM_CLK_EN_V 0x1 +#define USB_DEVICE_USB_MEM_CLK_EN_S 1 +/* USB_DEVICE_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: power down usb memory..*/ +#define USB_DEVICE_USB_MEM_PD (BIT(0)) +#define USB_DEVICE_USB_MEM_PD_M (BIT(0)) +#define USB_DEVICE_USB_MEM_PD_V 0x1 +#define USB_DEVICE_USB_MEM_PD_S 0 + +#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80) +/* USB_DEVICE_DATE : R/W ;bitpos:[31:0] ;default: 32'h2011190 ; */ +/*description: register version..*/ +#define USB_DEVICE_DATE 0xFFFFFFFF +#define USB_DEVICE_DATE_M ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S)) +#define USB_DEVICE_DATE_V 0xFFFFFFFF +#define USB_DEVICE_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_USB_DEVICE_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/usb_pins.h b/components/soc/esp32s3/include/soc/usb_pins.h new file mode 100644 index 0000000000..c8ad806e08 --- /dev/null +++ b/components/soc/esp32s3/include/soc/usb_pins.h @@ -0,0 +1,27 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/* GPIOs used to connect an external USB PHY */ +#define USBPHY_VP_NUM 33 +#define USBPHY_VM_NUM 34 +#define USBPHY_RCV_NUM 35 +#define USBPHY_OEN_NUM 36 +#define USBPHY_VPO_NUM 37 +#define USBPHY_VMO_NUM 38 + +/* GPIOs corresponding to the pads of the internal USB PHY */ +#define USBPHY_DP_NUM 20 +#define USBPHY_DM_NUM 19 diff --git a/components/soc/esp32s3/include/soc/usb_reg.h b/components/soc/esp32s3/include/soc/usb_reg.h new file mode 100644 index 0000000000..361144e0c1 --- /dev/null +++ b/components/soc/esp32s3/include/soc/usb_reg.h @@ -0,0 +1,10459 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** Control/Status registers */ +/** USB_GOTGCTL_REG register + * OTG Control and Status Register + */ +#define USB_GOTGCTL_REG (SOC_DPORT_USB_BASE + 0x0) +/** USB_SESREQSCS : RO; bitpos: [0]; default: 0; + * Session Request Success.The core sets this bit when a session request initiation is + * successful + */ +#define USB_SESREQSCS (BIT(0)) +#define USB_SESREQSCS_M (USB_SESREQSCS_V << USB_SESREQSCS_S) +#define USB_SESREQSCS_V 0x00000001 +#define USB_SESREQSCS_S 0 +/** USB_SESREQ : R/W; bitpos: [1]; default: 0; + * Session Request.The application sets this bit to initiate a session request on the + * USB. The application can clear this bit by writing a 0 when the Host Negotiation + * Success Status Change bit in the OTG Interrupt register + * (GOTGINT_REG.USB_HSTNEGSUCSTSCHNG) is SET. The core clears this bit when the + * USB_HSTNEGSUCSTSCHNG bit is cleared + */ +#define USB_SESREQ (BIT(1)) +#define USB_SESREQ_M (USB_SESREQ_V << USB_SESREQ_S) +#define USB_SESREQ_V 0x00000001 +#define USB_SESREQ_S 1 +/** USB_VBVALIDOVEN : R/W; bitpos: [2]; default: 0; + * VBUS Valid Override Enable + * 1'b1 : Internally Bvalid received from the PHY is overridden with + * GOTGCTL_REG.REG_VBVALIDOVVAl + * 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is + * used internally by the controller + */ +#define USB_VBVALIDOVEN (BIT(2)) +#define USB_VBVALIDOVEN_M (USB_VBVALIDOVEN_V << USB_VBVALIDOVEN_S) +#define USB_VBVALIDOVEN_V 0x00000001 +#define USB_VBVALIDOVEN_S 2 +/** USB_VBVALIDOVVAL : R/W; bitpos: [3]; default: 0; + * VBUS Valid OverrideValue + * 1'b0 : vbusvalid value is 1'b0 when GOTGCTL_REG.USB_VBVALIDOVEN =1 + * 1'b1 : vbusvalid value is 1'b1 when GOTGCTL_REG.USB_VBVALIDOVEN =1 + */ +#define USB_VBVALIDOVVAL (BIT(3)) +#define USB_VBVALIDOVVAL_M (USB_VBVALIDOVVAL_V << USB_VBVALIDOVVAL_S) +#define USB_VBVALIDOVVAL_V 0x00000001 +#define USB_VBVALIDOVVAL_S 3 +/** USB_AVALIDOVEN : R/W; bitpos: [4]; default: 0; + * This bit is used to enable/disable the software to override the Avalid signal using + * the GOTGCTL.AVALIDOVVAL + * 1'b1: Internally Avalid received from the PHY is overridden with + * GOTGCTL_REG.REG_AVALIDOVVAL + * 1'b0: Override is disabled and avalid signal from the respective PHY selected is + * used internally by the core + */ +#define USB_AVALIDOVEN (BIT(4)) +#define USB_AVALIDOVEN_M (USB_AVALIDOVEN_V << USB_AVALIDOVEN_S) +#define USB_AVALIDOVEN_V 0x00000001 +#define USB_AVALIDOVEN_S 4 +/** USB_AVALIDOVVAL : R/W; bitpos: [5]; default: 0; + * A-Peripheral Session Valid OverrideValue + * 1'b0 : Avalid value is 1'b0 when GOTGCTL_REG.USB_AVALIDOVEN =1 + * 1'b1 : Avalid value is 1'b1 when GOTGCTL_REG.USB_AVALIDOVEN =1 + */ +#define USB_AVALIDOVVAL (BIT(5)) +#define USB_AVALIDOVVAL_M (USB_AVALIDOVVAL_V << USB_AVALIDOVVAL_S) +#define USB_AVALIDOVVAL_V 0x00000001 +#define USB_AVALIDOVVAL_S 5 +/** USB_BVALIDOVEN : R/W; bitpos: [6]; default: 0; + * This bit is used to enable/disable the software to override the Bvalid signal using + * the GOTGCTLREG.BVALIDOVVAL + * 1'b1 : Internally Bvalid received from the PHY is overridden with + * GOTGCTL_REG.USB_BVALIDOVVAL + * 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is + * used internally by the force + */ +#define USB_BVALIDOVEN (BIT(6)) +#define USB_BVALIDOVEN_M (USB_BVALIDOVEN_V << USB_BVALIDOVEN_S) +#define USB_BVALIDOVEN_V 0x00000001 +#define USB_BVALIDOVEN_S 6 +/** USB_BVALIDOVVAL : R/W; bitpos: [7]; default: 0; + * B-Peripheral Session Valid OverrideValue + * 1'b0 : Bvalid value is 1'b0 when GOTGCTL_REG.USB_BVALIDOVEN =1 + * 1'b1 : Bvalid value is 1'b1 when GOTGCTL_REG.USB_BVALIDOVEN =1 + */ +#define USB_BVALIDOVVAL (BIT(7)) +#define USB_BVALIDOVVAL_M (USB_BVALIDOVVAL_V << USB_BVALIDOVVAL_S) +#define USB_BVALIDOVVAL_V 0x00000001 +#define USB_BVALIDOVVAL_S 7 +/** USB_HSTNEGSCS : RO; bitpos: [8]; default: 0; + * Host Negotiation Success.The controller sets this bit when host negotiation is + * successful. The controller clears this bit when the HNP Request (HNPReq) bit in + * this register is set. + */ +#define USB_HSTNEGSCS (BIT(8)) +#define USB_HSTNEGSCS_M (USB_HSTNEGSCS_V << USB_HSTNEGSCS_S) +#define USB_HSTNEGSCS_V 0x00000001 +#define USB_HSTNEGSCS_S 8 +/** USB_HNPREQ : R/W; bitpos: [9]; default: 0; + * HNP Request .The application sets this bit to initiate an HNP request to the + * Connected USB host. The application can clear this bit by writing a 0 when the Host + * Negotiation Success Status Change bit in the OTG Interrupt register + * (GOTGINT_REG.HSTNEGSUCSTSCHNG) is SET. The controller clears this bit when the + * HSTNEGSUCSTSCHNG bit is cleared. + */ +#define USB_HNPREQ (BIT(9)) +#define USB_HNPREQ_M (USB_HNPREQ_V << USB_HNPREQ_S) +#define USB_HNPREQ_V 0x00000001 +#define USB_HNPREQ_S 9 +/** USB_HSTSETHNPEN : R/W; bitpos: [10]; default: 0; + * Host Set HNP Enable.The application sets this bit when it has successfully enabled + * HNP (using the SetFeature.SetHNPEnable command) on the connected device + * 1'b0: Host Set HNP is not enabled + * 1'b1: Host Set HNP is enabled + */ +#define USB_HSTSETHNPEN (BIT(10)) +#define USB_HSTSETHNPEN_M (USB_HSTSETHNPEN_V << USB_HSTSETHNPEN_S) +#define USB_HSTSETHNPEN_V 0x00000001 +#define USB_HSTSETHNPEN_S 10 +/** USB_DEVHNPEN : R/W; bitpos: [11]; default: 0; + * Device HNP Enabled.The application sets this bit when it successfully receives a + * SetFeature.SetHNPEnable command from the connected USB host + * 1'b0: HNP is not enabled in the application + * 1'b1: HNP is enabled in the application + */ +#define USB_DEVHNPEN (BIT(11)) +#define USB_DEVHNPEN_M (USB_DEVHNPEN_V << USB_DEVHNPEN_S) +#define USB_DEVHNPEN_V 0x00000001 +#define USB_DEVHNPEN_S 11 +/** USB_EHEN : R/W; bitpos: [12]; default: 0; + * Embedded Host Enable.It is used to select between OTG A Device state Machine and + * Embedded Host state machine + * 1'b0: OTG A Device state machine is selected + * 1'b1: Embedded Host State Machine is selected + */ +#define USB_EHEN (BIT(12)) +#define USB_EHEN_M (USB_EHEN_V << USB_EHEN_S) +#define USB_EHEN_V 0x00000001 +#define USB_EHEN_S 12 +/** USB_DBNCEFLTRBYPASS : R/W; bitpos: [15]; default: 0; + * Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when + * enabled + * 1'b0: Disabled + * 1'b1: Enabled + */ +#define USB_DBNCEFLTRBYPASS (BIT(15)) +#define USB_DBNCEFLTRBYPASS_M (USB_DBNCEFLTRBYPASS_V << USB_DBNCEFLTRBYPASS_S) +#define USB_DBNCEFLTRBYPASS_V 0x00000001 +#define USB_DBNCEFLTRBYPASS_S 15 +/** USB_CONIDSTS : RO; bitpos: [16]; default: 0; + * Connector ID Status. Indicates the connector ID status on a connect event + * 1'b0: The core is in A-Device mode + * 1'b1: The core is in B-Device mode + */ +#define USB_CONIDSTS (BIT(16)) +#define USB_CONIDSTS_M (USB_CONIDSTS_V << USB_CONIDSTS_S) +#define USB_CONIDSTS_V 0x00000001 +#define USB_CONIDSTS_S 16 +/** USB_DBNCTIME : RO; bitpos: [17]; default: 0; + * Long/Short Debounce Time. Indicates the debounce time of a detected connection + * 1'b0: Long debounce time, used for physical connections (100ms + 2.5 micro-sec) + * 1'b1: Short debounce time, used for soft connections (2.5 micro-sec) + */ +#define USB_DBNCTIME (BIT(17)) +#define USB_DBNCTIME_M (USB_DBNCTIME_V << USB_DBNCTIME_S) +#define USB_DBNCTIME_V 0x00000001 +#define USB_DBNCTIME_S 17 +/** USB_ASESVLD : RO; bitpos: [18]; default: 0; + * A-Session Valid. Indicates the Host mode transceiver status + * 1'b0: A-session is not valid + * 1'b1: A-session is valid + */ +#define USB_ASESVLD (BIT(18)) +#define USB_ASESVLD_M (USB_ASESVLD_V << USB_ASESVLD_S) +#define USB_ASESVLD_V 0x00000001 +#define USB_ASESVLD_S 18 +/** USB_BSESVLD : RO; bitpos: [19]; default: 0; + * B-Session Valid.Indicates the Device mode transceiver status + * 1'b0: B-session is not valid + * 1'b1: B-session is valid + */ +#define USB_BSESVLD (BIT(19)) +#define USB_BSESVLD_M (USB_BSESVLD_V << USB_BSESVLD_S) +#define USB_BSESVLD_V 0x00000001 +#define USB_BSESVLD_S 19 +/** USB_OTGVER : R/W; bitpos: [20]; default: 0; + * OTG Version + * 1'b0:Supports OTG Version 1.3 + * 1'b1:Supports OTG Version 2.0 + */ +#define USB_OTGVER (BIT(20)) +#define USB_OTGVER_M (USB_OTGVER_V << USB_OTGVER_S) +#define USB_OTGVER_V 0x00000001 +#define USB_OTGVER_S 20 +/** USB_CURMOD : RO; bitpos: [21]; default: 0; + * Current Mode of Operation + * 1'b0: Device mode + * 1'b1:Host mode + */ +#define USB_CURMOD (BIT(21)) +#define USB_CURMOD_M (USB_CURMOD_V << USB_CURMOD_S) +#define USB_CURMOD_V 0x00000001 +#define USB_CURMOD_S 21 + + +/** USB_GDFIFOCFG_REG register + * Global DFIFO Configuration Register + */ +#define USB_GDFIFOCFG_REG (SOC_DPORT_USB_BASE + 0x5c) +/** USB_GDFIFOCFG : R/W; bitpos: [16:0]; default: 0; + * GDFIFOCfg + */ +#define USB_GDFIFOCFG 0x0000FFFF +#define USB_GDFIFOCFG_M (USB_GDFIFOCFG_V << USB_GDFIFOCFG_S) +#define USB_GDFIFOCFG_V 0x0000FFFF +#define USB_GDFIFOCFG_S 0 +/** USB_EPINFOBASEADDR : R/W; bitpos: [32:16]; default: 0; + * EPInfoBaseAddr + */ +#define USB_EPINFOBASEADDR 0x0000FFFF +#define USB_EPINFOBASEADDR_M (USB_EPINFOBASEADDR_V << USB_EPINFOBASEADDR_S) +#define USB_EPINFOBASEADDR_V 0x0000FFFF +#define USB_EPINFOBASEADDR_S 16 + + +/** USB_HPTXFSIZ_REG register + * Host Periodic Transmit FIFO Size Register + */ +#define USB_HPTXFSIZ_REG (SOC_DPORT_USB_BASE + 0x100) +/** USB_PTXFSTADDR : R/W; bitpos: [16:0]; default: 512; + * Host Periodic TxFIFO Start Address. + */ +#define USB_PTXFSTADDR 0x0000FFFF +#define USB_PTXFSTADDR_M (USB_PTXFSTADDR_V << USB_PTXFSTADDR_S) +#define USB_PTXFSTADDR_V 0x0000FFFF +#define USB_PTXFSTADDR_S 0 +/** USB_PTXFSIZE : R/W; bitpos: [32:16]; default: 4096; + * Host Periodic TxFIFO Depth,This value is in terms of 32-bit words.. + */ +#define USB_PTXFSIZE 0x0000FFFF +#define USB_PTXFSIZE_M (USB_PTXFSIZE_V << USB_PTXFSIZE_S) +#define USB_PTXFSIZE_V 0x0000FFFF +#define USB_PTXFSIZE_S 16 + + +/** USB_DIEPTXF1_REG register + * Device IN Endpoint Transmit FIFO Size Register + */ +#define USB_DIEPTXF1_REG (SOC_DPORT_USB_BASE + 0x104) +/** USB_INEP1TXFSTADDR : R/W; bitpos: [16:0]; default: 512; + * IN Endpoint FIFOn Transmit RAM Start Address. + */ +#define USB_INEP1TXFSTADDR 0x0000FFFF +#define USB_INEP1TXFSTADDR_M (USB_INEP1TXFSTADDR_V << USB_INEP1TXFSTADDR_S) +#define USB_INEP1TXFSTADDR_V 0x0000FFFF +#define USB_INEP1TXFSTADDR_S 0 +/** USB_INEP1TXFDEP : R/W; bitpos: [32:16]; default: 4096; + * IN Endpoint TxFIFO Depth + */ +#define USB_INEP1TXFDEP 0x0000FFFF +#define USB_INEP1TXFDEP_M (USB_INEP1TXFDEP_V << USB_INEP1TXFDEP_S) +#define USB_INEP1TXFDEP_V 0x0000FFFF +#define USB_INEP1TXFDEP_S 16 + + +/** USB_DIEPTXF2_REG register + * Device IN Endpoint Transmit FIFO Size Register + */ +#define USB_DIEPTXF2_REG (SOC_DPORT_USB_BASE + 0x108) +/** USB_INEP2TXFSTADDR : R/W; bitpos: [16:0]; default: 512; + * IN Endpoint FIFOn Transmit RAM Start Address. + */ +#define USB_INEP2TXFSTADDR 0x0000FFFF +#define USB_INEP2TXFSTADDR_M (USB_INEP2TXFSTADDR_V << USB_INEP2TXFSTADDR_S) +#define USB_INEP2TXFSTADDR_V 0x0000FFFF +#define USB_INEP2TXFSTADDR_S 0 +/** USB_INEP2TXFDEP : R/W; bitpos: [32:16]; default: 4096; + * IN Endpoint TxFIFO Depth + */ +#define USB_INEP2TXFDEP 0x0000FFFF +#define USB_INEP2TXFDEP_M (USB_INEP2TXFDEP_V << USB_INEP2TXFDEP_S) +#define USB_INEP2TXFDEP_V 0x0000FFFF +#define USB_INEP2TXFDEP_S 16 + + +/** USB_DIEPTXF3_REG register + * Device IN Endpoint Transmit FIFO Size Register + */ +#define USB_DIEPTXF3_REG (SOC_DPORT_USB_BASE + 0x10c) +/** USB_INEP3TXFSTADDR : R/W; bitpos: [16:0]; default: 512; + * IN Endpoint FIFOn Transmit RAM Start Address. + */ +#define USB_INEP3TXFSTADDR 0x0000FFFF +#define USB_INEP3TXFSTADDR_M (USB_INEP3TXFSTADDR_V << USB_INEP3TXFSTADDR_S) +#define USB_INEP3TXFSTADDR_V 0x0000FFFF +#define USB_INEP3TXFSTADDR_S 0 +/** USB_INEP3TXFDEP : R/W; bitpos: [32:16]; default: 4096; + * IN Endpoint TxFIFO Depth + */ +#define USB_INEP3TXFDEP 0x0000FFFF +#define USB_INEP3TXFDEP_M (USB_INEP3TXFDEP_V << USB_INEP3TXFDEP_S) +#define USB_INEP3TXFDEP_V 0x0000FFFF +#define USB_INEP3TXFDEP_S 16 + + +/** USB_DIEPTXF4_REG register + * Device IN Endpoint Transmit FIFO Size Register + */ +#define USB_DIEPTXF4_REG (SOC_DPORT_USB_BASE + 0x110) +/** USB_INEP4TXFSTADDR : R/W; bitpos: [16:0]; default: 512; + * IN Endpoint FIFOn Transmit RAM Start Address. + */ +#define USB_INEP4TXFSTADDR 0x0000FFFF +#define USB_INEP4TXFSTADDR_M (USB_INEP4TXFSTADDR_V << USB_INEP4TXFSTADDR_S) +#define USB_INEP4TXFSTADDR_V 0x0000FFFF +#define USB_INEP4TXFSTADDR_S 0 +/** USB_INEP4TXFDEP : R/W; bitpos: [32:16]; default: 4096; + * IN Endpoint TxFIFO Depth + */ +#define USB_INEP4TXFDEP 0x0000FFFF +#define USB_INEP4TXFDEP_M (USB_INEP4TXFDEP_V << USB_INEP4TXFDEP_S) +#define USB_INEP4TXFDEP_V 0x0000FFFF +#define USB_INEP4TXFDEP_S 16 + + +/** USB_HCFG_REG register + * Host Configuration Register + */ +#define USB_HCFG_REG (SOC_DPORT_USB_BASE + 0x400) +/** USB_H_FSLSPCLKSEL : R/W; bitpos: [2:0]; default: 0; + * 0x0 : PHY clock is running at 30/60 MHz + * 0x1 : PHY clock is running at 48 MHz + * 0x2 : PHY clock is running at 6 MHz + */ +#define USB_H_FSLSPCLKSEL 0x00000003 +#define USB_H_FSLSPCLKSEL_M (USB_H_FSLSPCLKSEL_V << USB_H_FSLSPCLKSEL_S) +#define USB_H_FSLSPCLKSEL_V 0x00000003 +#define USB_H_FSLSPCLKSEL_S 0 +/** USB_H_FSLSSUPP : R/W; bitpos: [2]; default: 0; + * FS- and LS-Only Support + * 1'b0: HS/FS/LS, based on the maximum speed supported by the connected device + * 1'b1: FS/LS-only, even If the connected device can support HS + */ +#define USB_H_FSLSSUPP (BIT(2)) +#define USB_H_FSLSSUPP_M (USB_H_FSLSSUPP_V << USB_H_FSLSSUPP_S) +#define USB_H_FSLSSUPP_V 0x00000001 +#define USB_H_FSLSSUPP_S 2 +/** USB_H_ENA32KHZS : R/W; bitpos: [7]; default: 0; + * 1'b0:32 KHz Suspend mode disabled + * 1'b1:32 KHz Suspend mode enabled + */ +#define USB_H_ENA32KHZS (BIT(7)) +#define USB_H_ENA32KHZS_M (USB_H_ENA32KHZS_V << USB_H_ENA32KHZS_S) +#define USB_H_ENA32KHZS_V 0x00000001 +#define USB_H_ENA32KHZS_S 7 +/** USB_H_DESCDMA : R/W; bitpos: [23]; default: 0; + * GAHBCFG_REG.USB_DMAEN=0,HCFG_REG.USB_DESCDMA=0 => Slave mode + * GAHBCFG_REG.USB_DMAEN=0,HCFG_REG.USB_DESCDMA=1 => Invalid + * GAHBCFG_REG.USB_DMAEN=1,HCFG_REG.USB_DESCDMA=0 => Buffered DMA + * GAHBCFG_REG.USB_DMAEN=1,HCFG_REG.USB_DESCDMA=1 => Scatter/Gather DMA mode + */ +#define USB_H_DESCDMA (BIT(23)) +#define USB_H_DESCDMA_M (USB_H_DESCDMA_V << USB_H_DESCDMA_S) +#define USB_H_DESCDMA_V 0x00000001 +#define USB_H_DESCDMA_S 23 +/** USB_H_FRLISTEN : R/W; bitpos: [26:24]; default: 0; + * Frame List Entries + * 2'b00: 8 Entries + * 2'b01: 16 Entries + * 2'b10: 32 Entries + * 2'b11: 64 Entries + */ +#define USB_H_FRLISTEN 0x00000003 +#define USB_H_FRLISTEN_M (USB_H_FRLISTEN_V << USB_H_FRLISTEN_S) +#define USB_H_FRLISTEN_V 0x00000003 +#define USB_H_FRLISTEN_S 24 +/** USB_H_PERSCHEDENA : R/W; bitpos: [26]; default: 0; + * 0x0 (DISABLED): Disables periodic scheduling within the core + * 0x1 (ENABLED): Enables periodic scheduling within the core + */ +#define USB_H_PERSCHEDENA (BIT(26)) +#define USB_H_PERSCHEDENA_M (USB_H_PERSCHEDENA_V << USB_H_PERSCHEDENA_S) +#define USB_H_PERSCHEDENA_V 0x00000001 +#define USB_H_PERSCHEDENA_S 26 +/** USB_H_MODECHTIMEN : R/W; bitpos: [31]; default: 0; + * Mode Change Ready Timer Enable, + * 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at + * the end of resume to the change the opmode from 2'b10 to 2'b00. + * 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume to + * change the opmode from 2'b10 to 2'b00. + */ +#define USB_H_MODECHTIMEN (BIT(31)) +#define USB_H_MODECHTIMEN_M (USB_H_MODECHTIMEN_V << USB_H_MODECHTIMEN_S) +#define USB_H_MODECHTIMEN_V 0x00000001 +#define USB_H_MODECHTIMEN_S 31 + + +/** USB_HFIR_REG register + * Host Frame Interval Register + */ +#define USB_HFIR_REG (SOC_DPORT_USB_BASE + 0x404) +/** USB_FRINT : R/W; bitpos: [16:0]; default: 6103; + * Frame Interval . 1 ms * (PHY clock frequency for FS/LS) + */ +#define USB_FRINT 0x0000FFFF +#define USB_FRINT_M (USB_FRINT_V << USB_FRINT_S) +#define USB_FRINT_V 0x0000FFFF +#define USB_FRINT_S 0 +/** USB_HFIRRLDCTRL : R/W; bitpos: [16]; default: 0; + * Reload Control + * 1'b0 : The HFIR cannot be reloaded dynamically + * 1'b1: the HFIR can be dynamically reloaded during runtime + */ +#define USB_HFIRRLDCTRL (BIT(16)) +#define USB_HFIRRLDCTRL_M (USB_HFIRRLDCTRL_V << USB_HFIRRLDCTRL_S) +#define USB_HFIRRLDCTRL_V 0x00000001 +#define USB_HFIRRLDCTRL_S 16 + + +/** USB_HFLBADDR_REG register + * Host Frame List Base Address Register + */ +#define USB_HFLBADDR_REG (SOC_DPORT_USB_BASE + 0x41c) +/** USB_HFLBADDR : R/W; bitpos: [32:0]; default: 0; + * The starting address of the Frame list. This register is used only for Isochronous + * and Interrupt Channels. + */ +#define USB_HFLBADDR 0xFFFFFFFF +#define USB_HFLBADDR_M (USB_HFLBADDR_V << USB_HFLBADDR_S) +#define USB_HFLBADDR_V 0xFFFFFFFF +#define USB_HFLBADDR_S 0 + + +/** USB_HPRT_REG register + * Host Port Control and Status Register + */ +#define USB_HPRT_REG (SOC_DPORT_USB_BASE + 0x440) +/** USB_PRTCONNSTS : RO; bitpos: [0]; default: 0; + * Port Connect Status + * 0x0: No device is attached to the port + * 0x1: A device is attached to the port + */ +#define USB_PRTCONNSTS (BIT(0)) +#define USB_PRTCONNSTS_M (USB_PRTCONNSTS_V << USB_PRTCONNSTS_S) +#define USB_PRTCONNSTS_V 0x00000001 +#define USB_PRTCONNSTS_S 0 +/** USB_PRTCONNDET : R/W; bitpos: [1]; default: 0; + * Port Connect Detected. + * 0x1 : Device connection detected. + * 0x0 : No device connection detected. + */ +#define USB_PRTCONNDET (BIT(1)) +#define USB_PRTCONNDET_M (USB_PRTCONNDET_V << USB_PRTCONNDET_S) +#define USB_PRTCONNDET_V 0x00000001 +#define USB_PRTCONNDET_S 1 +/** USB_PRTENA : R/W; bitpos: [2]; default: 0; + * Port Enable + * 1'b0: Port disabled + * 1'b1: Port enabled + */ +#define USB_PRTENA (BIT(2)) +#define USB_PRTENA_M (USB_PRTENA_V << USB_PRTENA_S) +#define USB_PRTENA_V 0x00000001 +#define USB_PRTENA_S 2 +/** USB_PRTENCHNG : R/W; bitpos: [3]; default: 0; + * Port Enable/Disable Change + * 0x0 : Port Enable bit 2 has not changed + * 0x1 : Port Enable bit 2 changed + */ +#define USB_PRTENCHNG (BIT(3)) +#define USB_PRTENCHNG_M (USB_PRTENCHNG_V << USB_PRTENCHNG_S) +#define USB_PRTENCHNG_V 0x00000001 +#define USB_PRTENCHNG_S 3 +/** USB_PRTOVRCURRACT : RO; bitpos: [4]; default: 0; + * Port Overcurrent Active + * 1'b0: No overcurrent condition + * 1'b1: Overcurrent condition + */ +#define USB_PRTOVRCURRACT (BIT(4)) +#define USB_PRTOVRCURRACT_M (USB_PRTOVRCURRACT_V << USB_PRTOVRCURRACT_S) +#define USB_PRTOVRCURRACT_V 0x00000001 +#define USB_PRTOVRCURRACT_S 4 +/** USB_PRTOVRCURRCHNG : R/W; bitpos: [5]; default: 0; + * Port Overcurrent Change + * 0x0: Status of port overcurrent status is not changed + * 0x1: Status of port overcurrent changed + */ +#define USB_PRTOVRCURRCHNG (BIT(5)) +#define USB_PRTOVRCURRCHNG_M (USB_PRTOVRCURRCHNG_V << USB_PRTOVRCURRCHNG_S) +#define USB_PRTOVRCURRCHNG_V 0x00000001 +#define USB_PRTOVRCURRCHNG_S 5 +/** USB_PRTRES : R/W; bitpos: [6]; default: 0; + * Port Resume + * 1'b0: No resume driven + * 1'b1: Resume driven + */ +#define USB_PRTRES (BIT(6)) +#define USB_PRTRES_M (USB_PRTRES_V << USB_PRTRES_S) +#define USB_PRTRES_V 0x00000001 +#define USB_PRTRES_S 6 +/** USB_PRTSUSP : R/W; bitpos: [7]; default: 0; + * Port Suspend + * 1'b0: Port not in Suspend mode + * 1'b1: Port in Suspend mode + */ +#define USB_PRTSUSP (BIT(7)) +#define USB_PRTSUSP_M (USB_PRTSUSP_V << USB_PRTSUSP_S) +#define USB_PRTSUSP_V 0x00000001 +#define USB_PRTSUSP_S 7 +/** USB_PRTRST : R/W; bitpos: [8]; default: 0; + * Port Reset. + * 1'b0: Port not in reset + * 1'b1: Port in reset + */ +#define USB_PRTRST (BIT(8)) +#define USB_PRTRST_M (USB_PRTRST_V << USB_PRTRST_S) +#define USB_PRTRST_V 0x00000001 +#define USB_PRTRST_S 8 +/** USB_PRTLNSTS : RO; bitpos: [12:10]; default: 0; + * Port Line Status + * Bit [10]: Logic level of D+ + * Bit [11]: Logic level of D- + */ +#define USB_PRTLNSTS 0x00000003 +#define USB_PRTLNSTS_M (USB_PRTLNSTS_V << USB_PRTLNSTS_S) +#define USB_PRTLNSTS_V 0x00000003 +#define USB_PRTLNSTS_S 10 +/** USB_PRTPWR : R/W; bitpos: [12]; default: 0; + * Port Power + * 1'b0: Power off + * 1'b1: Power on + */ +#define USB_PRTPWR (BIT(12)) +#define USB_PRTPWR_M (USB_PRTPWR_V << USB_PRTPWR_S) +#define USB_PRTPWR_V 0x00000001 +#define USB_PRTPWR_S 12 +/** USB_PRTTSTCTL : R/W; bitpos: [17:13]; default: 0; + * Port Test Control + * 4'b0000: Test mode disabled + * 4'b0001: Test_J mode + * 4'b0010: Test_K mode + * 4'b0011: Test_SE0_NAK mode + * 4'b0100: Test_Packet mode + * 4'b0101: Test_Force_Enable + * Others: Reserved + */ +#define USB_PRTTSTCTL 0x0000000F +#define USB_PRTTSTCTL_M (USB_PRTTSTCTL_V << USB_PRTTSTCTL_S) +#define USB_PRTTSTCTL_V 0x0000000F +#define USB_PRTTSTCTL_S 13 +/** USB_PRTSPD : RO; bitpos: [19:17]; default: 0; + * Port Speed + * 2'b00: High speed + * 2'b01: Full speed + * 2'b10: Low speed + * 2'b11: Reserved + */ +#define USB_PRTSPD 0x00000003 +#define USB_PRTSPD_M (USB_PRTSPD_V << USB_PRTSPD_S) +#define USB_PRTSPD_V 0x00000003 +#define USB_PRTSPD_S 17 + + +/** USB_HCCHAR0_REG register + * Host Channel 0 Characteristics Register + */ +#define USB_HCCHAR0_REG (SOC_DPORT_USB_BASE + 0x500) +/** USB_H_MPS0 : R/W; bitpos: [11:0]; default: 0; + * Maximum Packet Size. + */ +#define USB_H_MPS0 0x000007FF +#define USB_H_MPS0_M (USB_H_MPS0_V << USB_H_MPS0_S) +#define USB_H_MPS0_V 0x000007FF +#define USB_H_MPS0_S 0 +/** USB_H_EPNUM0 : R/W; bitpos: [15:11]; default: 0; + * Endpoint Number. + */ +#define USB_H_EPNUM0 0x0000000F +#define USB_H_EPNUM0_M (USB_H_EPNUM0_V << USB_H_EPNUM0_S) +#define USB_H_EPNUM0_V 0x0000000F +#define USB_H_EPNUM0_S 11 +/** USB_H_EPDIR0 : R/W; bitpos: [15]; default: 0; + * 1'b0: OUT + * 1'b1: IN + */ +#define USB_H_EPDIR0 (BIT(15)) +#define USB_H_EPDIR0_M (USB_H_EPDIR0_V << USB_H_EPDIR0_S) +#define USB_H_EPDIR0_V 0x00000001 +#define USB_H_EPDIR0_S 15 +/** USB_H_LSPDDEV0 : R/W; bitpos: [17]; default: 0; + * 0x0: Not Communicating with low speed device + * 0x1: Communicating with low speed device + */ +#define USB_H_LSPDDEV0 (BIT(17)) +#define USB_H_LSPDDEV0_M (USB_H_LSPDDEV0_V << USB_H_LSPDDEV0_S) +#define USB_H_LSPDDEV0_V 0x00000001 +#define USB_H_LSPDDEV0_S 17 +/** USB_H_EPTYPE0 : R/W; bitpos: [20:18]; default: 0; + * 0x0 (CTRL): Contro + * 0x1 (ISOC): Isochronous + * 0x2 (BULK): Bulk + * 0x3 (INTERR): Interrupt + */ +#define USB_H_EPTYPE0 0x00000003 +#define USB_H_EPTYPE0_M (USB_H_EPTYPE0_V << USB_H_EPTYPE0_S) +#define USB_H_EPTYPE0_V 0x00000003 +#define USB_H_EPTYPE0_S 18 +/** USB_H_EC0 : R/W; bitpos: [21]; default: 0; + * Multi Count (MC) / Error Count(EC) + * 0x0 (RESERVED): Reserved. This field yields undefined result + * 0x1 (TRANSONE): 1 transaction + * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe + * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe + */ +#define USB_H_EC0 (BIT(21)) +#define USB_H_EC0_M (USB_H_EC0_V << USB_H_EC0_S) +#define USB_H_EC0_V 0x00000001 +#define USB_H_EC0_S 21 +/** USB_H_DEVADDR0 : R/W; bitpos: [29:22]; default: 0; + * Device Address . This field selects the specific device serving as the data + * source or sink. + */ +#define USB_H_DEVADDR0 0x0000007F +#define USB_H_DEVADDR0_M (USB_H_DEVADDR0_V << USB_H_DEVADDR0_S) +#define USB_H_DEVADDR0_V 0x0000007F +#define USB_H_DEVADDR0_S 22 +/** USB_H_ODDFRM0 : R/W; bitpos: [29]; default: 0; + * Odd Frame + * 1'b0: Even (micro)Frame + * 1'b1: Odd (micro)Frame + */ +#define USB_H_ODDFRM0 (BIT(29)) +#define USB_H_ODDFRM0_M (USB_H_ODDFRM0_V << USB_H_ODDFRM0_S) +#define USB_H_ODDFRM0_V 0x00000001 +#define USB_H_ODDFRM0_S 29 +/** USB_H_CHDIS0 : R/W; bitpos: [30]; default: 0; + * Channel Disable + * 0x0 : Transmit/Recieve norma + * 0x1 : Stop transmitting/receiving data on channel + */ +#define USB_H_CHDIS0 (BIT(30)) +#define USB_H_CHDIS0_M (USB_H_CHDIS0_V << USB_H_CHDIS0_S) +#define USB_H_CHDIS0_V 0x00000001 +#define USB_H_CHDIS0_S 30 +/** USB_H_CHENA0 : R/W; bitpos: [31]; default: 0; + * Channel Enable + * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is + * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is + * disabled + * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure + * and data buffer with data is set up and this channel can access the descriptor. If + * Scatter/Gather mode is disabled, indicates that the channel is enabled + */ +#define USB_H_CHENA0 (BIT(31)) +#define USB_H_CHENA0_M (USB_H_CHENA0_V << USB_H_CHENA0_S) +#define USB_H_CHENA0_V 0x00000001 +#define USB_H_CHENA0_S 31 + + +/** USB_HCDMA0_REG register + * Host Channel 0 DMA Address Register + */ +#define USB_HCDMA0_REG (SOC_DPORT_USB_BASE + 0x514) +/** USB_H_DMAADDR0 : R/W; bitpos: [32:0]; default: 0; + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * [31:9]: DMA Address + * [8:3]: Current Transfer Desc + * [2:0]: Reserved + */ +#define USB_H_DMAADDR0 0xFFFFFFFF +#define USB_H_DMAADDR0_M (USB_H_DMAADDR0_V << USB_H_DMAADDR0_S) +#define USB_H_DMAADDR0_V 0xFFFFFFFF +#define USB_H_DMAADDR0_S 0 + + +/** USB_HCCHAR1_REG register + * Host Channel 1 Characteristics Register + */ +#define USB_HCCHAR1_REG (SOC_DPORT_USB_BASE + 0x520) +/** USB_H_MPS1 : R/W; bitpos: [11:0]; default: 0; + * Maximum Packet Size. + */ +#define USB_H_MPS1 0x000007FF +#define USB_H_MPS1_M (USB_H_MPS1_V << USB_H_MPS1_S) +#define USB_H_MPS1_V 0x000007FF +#define USB_H_MPS1_S 0 +/** USB_H_EPNUM1 : R/W; bitpos: [15:11]; default: 0; + * Endpoint Number. + */ +#define USB_H_EPNUM1 0x0000000F +#define USB_H_EPNUM1_M (USB_H_EPNUM1_V << USB_H_EPNUM1_S) +#define USB_H_EPNUM1_V 0x0000000F +#define USB_H_EPNUM1_S 11 +/** USB_H_EPDIR1 : R/W; bitpos: [15]; default: 0; + * 1'b0: OUT + * 1'b1: IN + */ +#define USB_H_EPDIR1 (BIT(15)) +#define USB_H_EPDIR1_M (USB_H_EPDIR1_V << USB_H_EPDIR1_S) +#define USB_H_EPDIR1_V 0x00000001 +#define USB_H_EPDIR1_S 15 +/** USB_H_LSPDDEV1 : R/W; bitpos: [17]; default: 0; + * 0x0: Not Communicating with low speed device + * 0x1: Communicating with low speed device + */ +#define USB_H_LSPDDEV1 (BIT(17)) +#define USB_H_LSPDDEV1_M (USB_H_LSPDDEV1_V << USB_H_LSPDDEV1_S) +#define USB_H_LSPDDEV1_V 0x00000001 +#define USB_H_LSPDDEV1_S 17 +/** USB_H_EPTYPE1 : R/W; bitpos: [20:18]; default: 0; + * 0x0 (CTRL): Contro + * 0x1 (ISOC): Isochronous + * 0x2 (BULK): Bulk + * 0x3 (INTERR): Interrupt + */ +#define USB_H_EPTYPE1 0x00000003 +#define USB_H_EPTYPE1_M (USB_H_EPTYPE1_V << USB_H_EPTYPE1_S) +#define USB_H_EPTYPE1_V 0x00000003 +#define USB_H_EPTYPE1_S 18 +/** USB_H_EC1 : R/W; bitpos: [21]; default: 0; + * Multi Count (MC) / Error Count(EC) + * 0x0 (RESERVED): Reserved. This field yields undefined result + * 0x1 (TRANSONE): 1 transaction + * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe + * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe + */ +#define USB_H_EC1 (BIT(21)) +#define USB_H_EC1_M (USB_H_EC1_V << USB_H_EC1_S) +#define USB_H_EC1_V 0x00000001 +#define USB_H_EC1_S 21 +/** USB_H_DEVADDR1 : R/W; bitpos: [29:22]; default: 0; + * Device Address . This field selects the specific device serving as the data + * source or sink. + */ +#define USB_H_DEVADDR1 0x0000007F +#define USB_H_DEVADDR1_M (USB_H_DEVADDR1_V << USB_H_DEVADDR1_S) +#define USB_H_DEVADDR1_V 0x0000007F +#define USB_H_DEVADDR1_S 22 +/** USB_H_ODDFRM1 : R/W; bitpos: [29]; default: 0; + * Odd Frame + * 1'b0: Even (micro)Frame + * 1'b1: Odd (micro)Frame + */ +#define USB_H_ODDFRM1 (BIT(29)) +#define USB_H_ODDFRM1_M (USB_H_ODDFRM1_V << USB_H_ODDFRM1_S) +#define USB_H_ODDFRM1_V 0x00000001 +#define USB_H_ODDFRM1_S 29 +/** USB_H_CHDIS1 : R/W; bitpos: [30]; default: 0; + * Channel Disable + * 0x0 : Transmit/Recieve norma + * 0x1 : Stop transmitting/receiving data on channel + */ +#define USB_H_CHDIS1 (BIT(30)) +#define USB_H_CHDIS1_M (USB_H_CHDIS1_V << USB_H_CHDIS1_S) +#define USB_H_CHDIS1_V 0x00000001 +#define USB_H_CHDIS1_S 30 +/** USB_H_CHENA1 : R/W; bitpos: [31]; default: 0; + * Channel Enable + * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is + * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is + * disabled + * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure + * and data buffer with data is set up and this channel can access the descriptor. If + * Scatter/Gather mode is disabled, indicates that the channel is enabled + */ +#define USB_H_CHENA1 (BIT(31)) +#define USB_H_CHENA1_M (USB_H_CHENA1_V << USB_H_CHENA1_S) +#define USB_H_CHENA1_V 0x00000001 +#define USB_H_CHENA1_S 31 + + +/** USB_HCDMA1_REG register + * Host Channel 1 DMA Address Register + */ +#define USB_HCDMA1_REG (SOC_DPORT_USB_BASE + 0x534) +/** USB_H_DMAADDR1 : R/W; bitpos: [32:0]; default: 0; + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * [31:9]: DMA Address + * [8:3]: Current Transfer Desc + * [2:0]: Reserved + */ +#define USB_H_DMAADDR1 0xFFFFFFFF +#define USB_H_DMAADDR1_M (USB_H_DMAADDR1_V << USB_H_DMAADDR1_S) +#define USB_H_DMAADDR1_V 0xFFFFFFFF +#define USB_H_DMAADDR1_S 0 + + +/** USB_HCCHAR2_REG register + * Host Channel 2 Characteristics Register + */ +#define USB_HCCHAR2_REG (SOC_DPORT_USB_BASE + 0x540) +/** USB_H_MPS2 : R/W; bitpos: [11:0]; default: 0; + * Maximum Packet Size. + */ +#define USB_H_MPS2 0x000007FF +#define USB_H_MPS2_M (USB_H_MPS2_V << USB_H_MPS2_S) +#define USB_H_MPS2_V 0x000007FF +#define USB_H_MPS2_S 0 +/** USB_H_EPNUM2 : R/W; bitpos: [15:11]; default: 0; + * Endpoint Number. + */ +#define USB_H_EPNUM2 0x0000000F +#define USB_H_EPNUM2_M (USB_H_EPNUM2_V << USB_H_EPNUM2_S) +#define USB_H_EPNUM2_V 0x0000000F +#define USB_H_EPNUM2_S 11 +/** USB_H_EPDIR2 : R/W; bitpos: [15]; default: 0; + * 1'b0: OUT + * 1'b1: IN + */ +#define USB_H_EPDIR2 (BIT(15)) +#define USB_H_EPDIR2_M (USB_H_EPDIR2_V << USB_H_EPDIR2_S) +#define USB_H_EPDIR2_V 0x00000001 +#define USB_H_EPDIR2_S 15 +/** USB_H_LSPDDEV2 : R/W; bitpos: [17]; default: 0; + * 0x0: Not Communicating with low speed device + * 0x1: Communicating with low speed device + */ +#define USB_H_LSPDDEV2 (BIT(17)) +#define USB_H_LSPDDEV2_M (USB_H_LSPDDEV2_V << USB_H_LSPDDEV2_S) +#define USB_H_LSPDDEV2_V 0x00000001 +#define USB_H_LSPDDEV2_S 17 +/** USB_H_EPTYPE2 : R/W; bitpos: [20:18]; default: 0; + * 0x0 (CTRL): Contro + * 0x1 (ISOC): Isochronous + * 0x2 (BULK): Bulk + * 0x3 (INTERR): Interrupt + */ +#define USB_H_EPTYPE2 0x00000003 +#define USB_H_EPTYPE2_M (USB_H_EPTYPE2_V << USB_H_EPTYPE2_S) +#define USB_H_EPTYPE2_V 0x00000003 +#define USB_H_EPTYPE2_S 18 +/** USB_H_EC2 : R/W; bitpos: [21]; default: 0; + * Multi Count (MC) / Error Count(EC) + * 0x0 (RESERVED): Reserved. This field yields undefined result + * 0x1 (TRANSONE): 1 transaction + * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe + * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe + */ +#define USB_H_EC2 (BIT(21)) +#define USB_H_EC2_M (USB_H_EC2_V << USB_H_EC2_S) +#define USB_H_EC2_V 0x00000001 +#define USB_H_EC2_S 21 +/** USB_H_DEVADDR2 : R/W; bitpos: [29:22]; default: 0; + * Device Address . This field selects the specific device serving as the data + * source or sink. + */ +#define USB_H_DEVADDR2 0x0000007F +#define USB_H_DEVADDR2_M (USB_H_DEVADDR2_V << USB_H_DEVADDR2_S) +#define USB_H_DEVADDR2_V 0x0000007F +#define USB_H_DEVADDR2_S 22 +/** USB_H_ODDFRM2 : R/W; bitpos: [29]; default: 0; + * Odd Frame + * 1'b0: Even (micro)Frame + * 1'b1: Odd (micro)Frame + */ +#define USB_H_ODDFRM2 (BIT(29)) +#define USB_H_ODDFRM2_M (USB_H_ODDFRM2_V << USB_H_ODDFRM2_S) +#define USB_H_ODDFRM2_V 0x00000001 +#define USB_H_ODDFRM2_S 29 +/** USB_H_CHDIS2 : R/W; bitpos: [30]; default: 0; + * Channel Disable + * 0x0 : Transmit/Recieve norma + * 0x1 : Stop transmitting/receiving data on channel + */ +#define USB_H_CHDIS2 (BIT(30)) +#define USB_H_CHDIS2_M (USB_H_CHDIS2_V << USB_H_CHDIS2_S) +#define USB_H_CHDIS2_V 0x00000001 +#define USB_H_CHDIS2_S 30 +/** USB_H_CHENA2 : R/W; bitpos: [31]; default: 0; + * Channel Enable + * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is + * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is + * disabled + * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure + * and data buffer with data is set up and this channel can access the descriptor. If + * Scatter/Gather mode is disabled, indicates that the channel is enabled + */ +#define USB_H_CHENA2 (BIT(31)) +#define USB_H_CHENA2_M (USB_H_CHENA2_V << USB_H_CHENA2_S) +#define USB_H_CHENA2_V 0x00000001 +#define USB_H_CHENA2_S 31 + + +/** USB_HCDMA2_REG register + * Host Channel 2 DMA Address Register + */ +#define USB_HCDMA2_REG (SOC_DPORT_USB_BASE + 0x554) +/** USB_H_DMAADDR2 : R/W; bitpos: [32:0]; default: 0; + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * [31:9]: DMA Address + * [8:3]: Current Transfer Desc + * [2:0]: Reserved + */ +#define USB_H_DMAADDR2 0xFFFFFFFF +#define USB_H_DMAADDR2_M (USB_H_DMAADDR2_V << USB_H_DMAADDR2_S) +#define USB_H_DMAADDR2_V 0xFFFFFFFF +#define USB_H_DMAADDR2_S 0 + + +/** USB_HCCHAR3_REG register + * Host Channel 3 Characteristics Register + */ +#define USB_HCCHAR3_REG (SOC_DPORT_USB_BASE + 0x560) +/** USB_H_MPS3 : R/W; bitpos: [11:0]; default: 0; + * Maximum Packet Size. + */ +#define USB_H_MPS3 0x000007FF +#define USB_H_MPS3_M (USB_H_MPS3_V << USB_H_MPS3_S) +#define USB_H_MPS3_V 0x000007FF +#define USB_H_MPS3_S 0 +/** USB_H_EPNUM3 : R/W; bitpos: [15:11]; default: 0; + * Endpoint Number. + */ +#define USB_H_EPNUM3 0x0000000F +#define USB_H_EPNUM3_M (USB_H_EPNUM3_V << USB_H_EPNUM3_S) +#define USB_H_EPNUM3_V 0x0000000F +#define USB_H_EPNUM3_S 11 +/** USB_H_EPDIR3 : R/W; bitpos: [15]; default: 0; + * 1'b0: OUT + * 1'b1: IN + */ +#define USB_H_EPDIR3 (BIT(15)) +#define USB_H_EPDIR3_M (USB_H_EPDIR3_V << USB_H_EPDIR3_S) +#define USB_H_EPDIR3_V 0x00000001 +#define USB_H_EPDIR3_S 15 +/** USB_H_LSPDDEV3 : R/W; bitpos: [17]; default: 0; + * 0x0: Not Communicating with low speed device + * 0x1: Communicating with low speed device + */ +#define USB_H_LSPDDEV3 (BIT(17)) +#define USB_H_LSPDDEV3_M (USB_H_LSPDDEV3_V << USB_H_LSPDDEV3_S) +#define USB_H_LSPDDEV3_V 0x00000001 +#define USB_H_LSPDDEV3_S 17 +/** USB_H_EPTYPE3 : R/W; bitpos: [20:18]; default: 0; + * 0x0 (CTRL): Contro + * 0x1 (ISOC): Isochronous + * 0x2 (BULK): Bulk + * 0x3 (INTERR): Interrupt + */ +#define USB_H_EPTYPE3 0x00000003 +#define USB_H_EPTYPE3_M (USB_H_EPTYPE3_V << USB_H_EPTYPE3_S) +#define USB_H_EPTYPE3_V 0x00000003 +#define USB_H_EPTYPE3_S 18 +/** USB_H_EC3 : R/W; bitpos: [21]; default: 0; + * Multi Count (MC) / Error Count(EC) + * 0x0 (RESERVED): Reserved. This field yields undefined result + * 0x1 (TRANSONE): 1 transaction + * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe + * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe + */ +#define USB_H_EC3 (BIT(21)) +#define USB_H_EC3_M (USB_H_EC3_V << USB_H_EC3_S) +#define USB_H_EC3_V 0x00000001 +#define USB_H_EC3_S 21 +/** USB_H_DEVADDR3 : R/W; bitpos: [29:22]; default: 0; + * Device Address . This field selects the specific device serving as the data + * source or sink. + */ +#define USB_H_DEVADDR3 0x0000007F +#define USB_H_DEVADDR3_M (USB_H_DEVADDR3_V << USB_H_DEVADDR3_S) +#define USB_H_DEVADDR3_V 0x0000007F +#define USB_H_DEVADDR3_S 22 +/** USB_H_ODDFRM3 : R/W; bitpos: [29]; default: 0; + * Odd Frame + * 1'b0: Even (micro)Frame + * 1'b1: Odd (micro)Frame + */ +#define USB_H_ODDFRM3 (BIT(29)) +#define USB_H_ODDFRM3_M (USB_H_ODDFRM3_V << USB_H_ODDFRM3_S) +#define USB_H_ODDFRM3_V 0x00000001 +#define USB_H_ODDFRM3_S 29 +/** USB_H_CHDIS3 : R/W; bitpos: [30]; default: 0; + * Channel Disable + * 0x0 : Transmit/Recieve norma + * 0x1 : Stop transmitting/receiving data on channel + */ +#define USB_H_CHDIS3 (BIT(30)) +#define USB_H_CHDIS3_M (USB_H_CHDIS3_V << USB_H_CHDIS3_S) +#define USB_H_CHDIS3_V 0x00000001 +#define USB_H_CHDIS3_S 30 +/** USB_H_CHENA3 : R/W; bitpos: [31]; default: 0; + * Channel Enable + * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is + * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is + * disabled + * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure + * and data buffer with data is set up and this channel can access the descriptor. If + * Scatter/Gather mode is disabled, indicates that the channel is enabled + */ +#define USB_H_CHENA3 (BIT(31)) +#define USB_H_CHENA3_M (USB_H_CHENA3_V << USB_H_CHENA3_S) +#define USB_H_CHENA3_V 0x00000001 +#define USB_H_CHENA3_S 31 + + +/** USB_HCDMA3_REG register + * Host Channel 3 DMA Address Register + */ +#define USB_HCDMA3_REG (SOC_DPORT_USB_BASE + 0x574) +/** USB_H_DMAADDR3 : R/W; bitpos: [32:0]; default: 0; + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * [31:9]: DMA Address + * [8:3]: Current Transfer Desc + * [2:0]: Reserved + */ +#define USB_H_DMAADDR3 0xFFFFFFFF +#define USB_H_DMAADDR3_M (USB_H_DMAADDR3_V << USB_H_DMAADDR3_S) +#define USB_H_DMAADDR3_V 0xFFFFFFFF +#define USB_H_DMAADDR3_S 0 + + +/** USB_HCCHAR4_REG register + * Host Channel 4 Characteristics Register + */ +#define USB_HCCHAR4_REG (SOC_DPORT_USB_BASE + 0x580) +/** USB_H_MPS4 : R/W; bitpos: [11:0]; default: 0; + * Maximum Packet Size. + */ +#define USB_H_MPS4 0x000007FF +#define USB_H_MPS4_M (USB_H_MPS4_V << USB_H_MPS4_S) +#define USB_H_MPS4_V 0x000007FF +#define USB_H_MPS4_S 0 +/** USB_H_EPNUM4 : R/W; bitpos: [15:11]; default: 0; + * Endpoint Number. + */ +#define USB_H_EPNUM4 0x0000000F +#define USB_H_EPNUM4_M (USB_H_EPNUM4_V << USB_H_EPNUM4_S) +#define USB_H_EPNUM4_V 0x0000000F +#define USB_H_EPNUM4_S 11 +/** USB_H_EPDIR4 : R/W; bitpos: [15]; default: 0; + * 1'b0: OUT + * 1'b1: IN + */ +#define USB_H_EPDIR4 (BIT(15)) +#define USB_H_EPDIR4_M (USB_H_EPDIR4_V << USB_H_EPDIR4_S) +#define USB_H_EPDIR4_V 0x00000001 +#define USB_H_EPDIR4_S 15 +/** USB_H_LSPDDEV4 : R/W; bitpos: [17]; default: 0; + * 0x0: Not Communicating with low speed device + * 0x1: Communicating with low speed device + */ +#define USB_H_LSPDDEV4 (BIT(17)) +#define USB_H_LSPDDEV4_M (USB_H_LSPDDEV4_V << USB_H_LSPDDEV4_S) +#define USB_H_LSPDDEV4_V 0x00000001 +#define USB_H_LSPDDEV4_S 17 +/** USB_H_EPTYPE4 : R/W; bitpos: [20:18]; default: 0; + * 0x0 (CTRL): Contro + * 0x1 (ISOC): Isochronous + * 0x2 (BULK): Bulk + * 0x3 (INTERR): Interrupt + */ +#define USB_H_EPTYPE4 0x00000003 +#define USB_H_EPTYPE4_M (USB_H_EPTYPE4_V << USB_H_EPTYPE4_S) +#define USB_H_EPTYPE4_V 0x00000003 +#define USB_H_EPTYPE4_S 18 +/** USB_H_EC4 : R/W; bitpos: [21]; default: 0; + * Multi Count (MC) / Error Count(EC) + * 0x0 (RESERVED): Reserved. This field yields undefined result + * 0x1 (TRANSONE): 1 transaction + * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe + * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe + */ +#define USB_H_EC4 (BIT(21)) +#define USB_H_EC4_M (USB_H_EC4_V << USB_H_EC4_S) +#define USB_H_EC4_V 0x00000001 +#define USB_H_EC4_S 21 +/** USB_H_DEVADDR4 : R/W; bitpos: [29:22]; default: 0; + * Device Address . This field selects the specific device serving as the data + * source or sink. + */ +#define USB_H_DEVADDR4 0x0000007F +#define USB_H_DEVADDR4_M (USB_H_DEVADDR4_V << USB_H_DEVADDR4_S) +#define USB_H_DEVADDR4_V 0x0000007F +#define USB_H_DEVADDR4_S 22 +/** USB_H_ODDFRM4 : R/W; bitpos: [29]; default: 0; + * Odd Frame + * 1'b0: Even (micro)Frame + * 1'b1: Odd (micro)Frame + */ +#define USB_H_ODDFRM4 (BIT(29)) +#define USB_H_ODDFRM4_M (USB_H_ODDFRM4_V << USB_H_ODDFRM4_S) +#define USB_H_ODDFRM4_V 0x00000001 +#define USB_H_ODDFRM4_S 29 +/** USB_H_CHDIS4 : R/W; bitpos: [30]; default: 0; + * Channel Disable + * 0x0 : Transmit/Recieve norma + * 0x1 : Stop transmitting/receiving data on channel + */ +#define USB_H_CHDIS4 (BIT(30)) +#define USB_H_CHDIS4_M (USB_H_CHDIS4_V << USB_H_CHDIS4_S) +#define USB_H_CHDIS4_V 0x00000001 +#define USB_H_CHDIS4_S 30 +/** USB_H_CHENA4 : R/W; bitpos: [31]; default: 0; + * Channel Enable + * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is + * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is + * disabled + * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure + * and data buffer with data is set up and this channel can access the descriptor. If + * Scatter/Gather mode is disabled, indicates that the channel is enabled + */ +#define USB_H_CHENA4 (BIT(31)) +#define USB_H_CHENA4_M (USB_H_CHENA4_V << USB_H_CHENA4_S) +#define USB_H_CHENA4_V 0x00000001 +#define USB_H_CHENA4_S 31 + + +/** USB_HCDMA4_REG register + * Host Channel 4 DMA Address Register + */ +#define USB_HCDMA4_REG (SOC_DPORT_USB_BASE + 0x594) +/** USB_H_DMAADDR4 : R/W; bitpos: [32:0]; default: 0; + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * [31:9]: DMA Address + * [8:3]: Current Transfer Desc + * [2:0]: Reserved + */ +#define USB_H_DMAADDR4 0xFFFFFFFF +#define USB_H_DMAADDR4_M (USB_H_DMAADDR4_V << USB_H_DMAADDR4_S) +#define USB_H_DMAADDR4_V 0xFFFFFFFF +#define USB_H_DMAADDR4_S 0 + + +/** USB_HCCHAR5_REG register + * Host Channel 5 Characteristics Register + */ +#define USB_HCCHAR5_REG (SOC_DPORT_USB_BASE + 0x5a0) +/** USB_H_MPS5 : R/W; bitpos: [11:0]; default: 0; + * Maximum Packet Size. + */ +#define USB_H_MPS5 0x000007FF +#define USB_H_MPS5_M (USB_H_MPS5_V << USB_H_MPS5_S) +#define USB_H_MPS5_V 0x000007FF +#define USB_H_MPS5_S 0 +/** USB_H_EPNUM5 : R/W; bitpos: [15:11]; default: 0; + * Endpoint Number. + */ +#define USB_H_EPNUM5 0x0000000F +#define USB_H_EPNUM5_M (USB_H_EPNUM5_V << USB_H_EPNUM5_S) +#define USB_H_EPNUM5_V 0x0000000F +#define USB_H_EPNUM5_S 11 +/** USB_H_EPDIR5 : R/W; bitpos: [15]; default: 0; + * 1'b0: OUT + * 1'b1: IN + */ +#define USB_H_EPDIR5 (BIT(15)) +#define USB_H_EPDIR5_M (USB_H_EPDIR5_V << USB_H_EPDIR5_S) +#define USB_H_EPDIR5_V 0x00000001 +#define USB_H_EPDIR5_S 15 +/** USB_H_LSPDDEV5 : R/W; bitpos: [17]; default: 0; + * 0x0: Not Communicating with low speed device + * 0x1: Communicating with low speed device + */ +#define USB_H_LSPDDEV5 (BIT(17)) +#define USB_H_LSPDDEV5_M (USB_H_LSPDDEV5_V << USB_H_LSPDDEV5_S) +#define USB_H_LSPDDEV5_V 0x00000001 +#define USB_H_LSPDDEV5_S 17 +/** USB_H_EPTYPE5 : R/W; bitpos: [20:18]; default: 0; + * 0x0 (CTRL): Contro + * 0x1 (ISOC): Isochronous + * 0x2 (BULK): Bulk + * 0x3 (INTERR): Interrupt + */ +#define USB_H_EPTYPE5 0x00000003 +#define USB_H_EPTYPE5_M (USB_H_EPTYPE5_V << USB_H_EPTYPE5_S) +#define USB_H_EPTYPE5_V 0x00000003 +#define USB_H_EPTYPE5_S 18 +/** USB_H_EC5 : R/W; bitpos: [21]; default: 0; + * Multi Count (MC) / Error Count(EC) + * 0x0 (RESERVED): Reserved. This field yields undefined result + * 0x1 (TRANSONE): 1 transaction + * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe + * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe + */ +#define USB_H_EC5 (BIT(21)) +#define USB_H_EC5_M (USB_H_EC5_V << USB_H_EC5_S) +#define USB_H_EC5_V 0x00000001 +#define USB_H_EC5_S 21 +/** USB_H_DEVADDR5 : R/W; bitpos: [29:22]; default: 0; + * Device Address . This field selects the specific device serving as the data + * source or sink. + */ +#define USB_H_DEVADDR5 0x0000007F +#define USB_H_DEVADDR5_M (USB_H_DEVADDR5_V << USB_H_DEVADDR5_S) +#define USB_H_DEVADDR5_V 0x0000007F +#define USB_H_DEVADDR5_S 22 +/** USB_H_ODDFRM5 : R/W; bitpos: [29]; default: 0; + * Odd Frame + * 1'b0: Even (micro)Frame + * 1'b1: Odd (micro)Frame + */ +#define USB_H_ODDFRM5 (BIT(29)) +#define USB_H_ODDFRM5_M (USB_H_ODDFRM5_V << USB_H_ODDFRM5_S) +#define USB_H_ODDFRM5_V 0x00000001 +#define USB_H_ODDFRM5_S 29 +/** USB_H_CHDIS5 : R/W; bitpos: [30]; default: 0; + * Channel Disable + * 0x0 : Transmit/Recieve norma + * 0x1 : Stop transmitting/receiving data on channel + */ +#define USB_H_CHDIS5 (BIT(30)) +#define USB_H_CHDIS5_M (USB_H_CHDIS5_V << USB_H_CHDIS5_S) +#define USB_H_CHDIS5_V 0x00000001 +#define USB_H_CHDIS5_S 30 +/** USB_H_CHENA5 : R/W; bitpos: [31]; default: 0; + * Channel Enable + * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is + * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is + * disabled + * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure + * and data buffer with data is set up and this channel can access the descriptor. If + * Scatter/Gather mode is disabled, indicates that the channel is enabled + */ +#define USB_H_CHENA5 (BIT(31)) +#define USB_H_CHENA5_M (USB_H_CHENA5_V << USB_H_CHENA5_S) +#define USB_H_CHENA5_V 0x00000001 +#define USB_H_CHENA5_S 31 + + +/** USB_HCDMA5_REG register + * Host Channel 5 DMA Address Register + */ +#define USB_HCDMA5_REG (SOC_DPORT_USB_BASE + 0x5b4) +/** USB_H_DMAADDR5 : R/W; bitpos: [32:0]; default: 0; + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * [31:9]: DMA Address + * [8:3]: Current Transfer Desc + * [2:0]: Reserved + */ +#define USB_H_DMAADDR5 0xFFFFFFFF +#define USB_H_DMAADDR5_M (USB_H_DMAADDR5_V << USB_H_DMAADDR5_S) +#define USB_H_DMAADDR5_V 0xFFFFFFFF +#define USB_H_DMAADDR5_S 0 + + +/** USB_HCCHAR6_REG register + * Host Channel 6 Characteristics Register + */ +#define USB_HCCHAR6_REG (SOC_DPORT_USB_BASE + 0x5c0) +/** USB_H_MPS6 : R/W; bitpos: [11:0]; default: 0; + * Maximum Packet Size. + */ +#define USB_H_MPS6 0x000007FF +#define USB_H_MPS6_M (USB_H_MPS6_V << USB_H_MPS6_S) +#define USB_H_MPS6_V 0x000007FF +#define USB_H_MPS6_S 0 +/** USB_H_EPNUM6 : R/W; bitpos: [15:11]; default: 0; + * Endpoint Number. + */ +#define USB_H_EPNUM6 0x0000000F +#define USB_H_EPNUM6_M (USB_H_EPNUM6_V << USB_H_EPNUM6_S) +#define USB_H_EPNUM6_V 0x0000000F +#define USB_H_EPNUM6_S 11 +/** USB_H_EPDIR6 : R/W; bitpos: [15]; default: 0; + * 1'b0: OUT + * 1'b1: IN + */ +#define USB_H_EPDIR6 (BIT(15)) +#define USB_H_EPDIR6_M (USB_H_EPDIR6_V << USB_H_EPDIR6_S) +#define USB_H_EPDIR6_V 0x00000001 +#define USB_H_EPDIR6_S 15 +/** USB_H_LSPDDEV6 : R/W; bitpos: [17]; default: 0; + * 0x0: Not Communicating with low speed device + * 0x1: Communicating with low speed device + */ +#define USB_H_LSPDDEV6 (BIT(17)) +#define USB_H_LSPDDEV6_M (USB_H_LSPDDEV6_V << USB_H_LSPDDEV6_S) +#define USB_H_LSPDDEV6_V 0x00000001 +#define USB_H_LSPDDEV6_S 17 +/** USB_H_EPTYPE6 : R/W; bitpos: [20:18]; default: 0; + * 0x0 (CTRL): Contro + * 0x1 (ISOC): Isochronous + * 0x2 (BULK): Bulk + * 0x3 (INTERR): Interrupt + */ +#define USB_H_EPTYPE6 0x00000003 +#define USB_H_EPTYPE6_M (USB_H_EPTYPE6_V << USB_H_EPTYPE6_S) +#define USB_H_EPTYPE6_V 0x00000003 +#define USB_H_EPTYPE6_S 18 +/** USB_H_EC6 : R/W; bitpos: [21]; default: 0; + * Multi Count (MC) / Error Count(EC) + * 0x0 (RESERVED): Reserved. This field yields undefined result + * 0x1 (TRANSONE): 1 transaction + * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe + * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe + */ +#define USB_H_EC6 (BIT(21)) +#define USB_H_EC6_M (USB_H_EC6_V << USB_H_EC6_S) +#define USB_H_EC6_V 0x00000001 +#define USB_H_EC6_S 21 +/** USB_H_DEVADDR6 : R/W; bitpos: [29:22]; default: 0; + * Device Address . This field selects the specific device serving as the data + * source or sink. + */ +#define USB_H_DEVADDR6 0x0000007F +#define USB_H_DEVADDR6_M (USB_H_DEVADDR6_V << USB_H_DEVADDR6_S) +#define USB_H_DEVADDR6_V 0x0000007F +#define USB_H_DEVADDR6_S 22 +/** USB_H_ODDFRM6 : R/W; bitpos: [29]; default: 0; + * Odd Frame + * 1'b0: Even (micro)Frame + * 1'b1: Odd (micro)Frame + */ +#define USB_H_ODDFRM6 (BIT(29)) +#define USB_H_ODDFRM6_M (USB_H_ODDFRM6_V << USB_H_ODDFRM6_S) +#define USB_H_ODDFRM6_V 0x00000001 +#define USB_H_ODDFRM6_S 29 +/** USB_H_CHDIS6 : R/W; bitpos: [30]; default: 0; + * Channel Disable + * 0x0 : Transmit/Recieve norma + * 0x1 : Stop transmitting/receiving data on channel + */ +#define USB_H_CHDIS6 (BIT(30)) +#define USB_H_CHDIS6_M (USB_H_CHDIS6_V << USB_H_CHDIS6_S) +#define USB_H_CHDIS6_V 0x00000001 +#define USB_H_CHDIS6_S 30 +/** USB_H_CHENA6 : R/W; bitpos: [31]; default: 0; + * Channel Enable + * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is + * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is + * disabled + * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure + * and data buffer with data is set up and this channel can access the descriptor. If + * Scatter/Gather mode is disabled, indicates that the channel is enabled + */ +#define USB_H_CHENA6 (BIT(31)) +#define USB_H_CHENA6_M (USB_H_CHENA6_V << USB_H_CHENA6_S) +#define USB_H_CHENA6_V 0x00000001 +#define USB_H_CHENA6_S 31 + + +/** USB_HCDMA6_REG register + * Host Channel 6 DMA Address Register + */ +#define USB_HCDMA6_REG (SOC_DPORT_USB_BASE + 0x5d4) +/** USB_H_DMAADDR6 : R/W; bitpos: [32:0]; default: 0; + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * [31:9]: DMA Address + * [8:3]: Current Transfer Desc + * [2:0]: Reserved + */ +#define USB_H_DMAADDR6 0xFFFFFFFF +#define USB_H_DMAADDR6_M (USB_H_DMAADDR6_V << USB_H_DMAADDR6_S) +#define USB_H_DMAADDR6_V 0xFFFFFFFF +#define USB_H_DMAADDR6_S 0 + + +/** USB_HCCHAR7_REG register + * Host Channel 7 Characteristics Register + */ +#define USB_HCCHAR7_REG (SOC_DPORT_USB_BASE + 0x5e0) +/** USB_H_MPS7 : R/W; bitpos: [11:0]; default: 0; + * Maximum Packet Size. + */ +#define USB_H_MPS7 0x000007FF +#define USB_H_MPS7_M (USB_H_MPS7_V << USB_H_MPS7_S) +#define USB_H_MPS7_V 0x000007FF +#define USB_H_MPS7_S 0 +/** USB_H_EPNUM7 : R/W; bitpos: [15:11]; default: 0; + * Endpoint Number. + */ +#define USB_H_EPNUM7 0x0000000F +#define USB_H_EPNUM7_M (USB_H_EPNUM7_V << USB_H_EPNUM7_S) +#define USB_H_EPNUM7_V 0x0000000F +#define USB_H_EPNUM7_S 11 +/** USB_H_EPDIR7 : R/W; bitpos: [15]; default: 0; + * 1'b0: OUT + * 1'b1: IN + */ +#define USB_H_EPDIR7 (BIT(15)) +#define USB_H_EPDIR7_M (USB_H_EPDIR7_V << USB_H_EPDIR7_S) +#define USB_H_EPDIR7_V 0x00000001 +#define USB_H_EPDIR7_S 15 +/** USB_H_LSPDDEV7 : R/W; bitpos: [17]; default: 0; + * 0x0: Not Communicating with low speed device + * 0x1: Communicating with low speed device + */ +#define USB_H_LSPDDEV7 (BIT(17)) +#define USB_H_LSPDDEV7_M (USB_H_LSPDDEV7_V << USB_H_LSPDDEV7_S) +#define USB_H_LSPDDEV7_V 0x00000001 +#define USB_H_LSPDDEV7_S 17 +/** USB_H_EPTYPE7 : R/W; bitpos: [20:18]; default: 0; + * 0x0 (CTRL): Contro + * 0x1 (ISOC): Isochronous + * 0x2 (BULK): Bulk + * 0x3 (INTERR): Interrupt + */ +#define USB_H_EPTYPE7 0x00000003 +#define USB_H_EPTYPE7_M (USB_H_EPTYPE7_V << USB_H_EPTYPE7_S) +#define USB_H_EPTYPE7_V 0x00000003 +#define USB_H_EPTYPE7_S 18 +/** USB_H_EC7 : R/W; bitpos: [21]; default: 0; + * Multi Count (MC) / Error Count(EC) + * 0x0 (RESERVED): Reserved. This field yields undefined result + * 0x1 (TRANSONE): 1 transaction + * 0x2 (TRANSTWO):2 transactions to be issued for this endpoint per microframe + * 0x3 (TRANSTHREE): 3 transactions to be issued for this endpoint per microframe + */ +#define USB_H_EC7 (BIT(21)) +#define USB_H_EC7_M (USB_H_EC7_V << USB_H_EC7_S) +#define USB_H_EC7_V 0x00000001 +#define USB_H_EC7_S 21 +/** USB_H_DEVADDR7 : R/W; bitpos: [29:22]; default: 0; + * Device Address . This field selects the specific device serving as the data + * source or sink. + */ +#define USB_H_DEVADDR7 0x0000007F +#define USB_H_DEVADDR7_M (USB_H_DEVADDR7_V << USB_H_DEVADDR7_S) +#define USB_H_DEVADDR7_V 0x0000007F +#define USB_H_DEVADDR7_S 22 +/** USB_H_ODDFRM7 : R/W; bitpos: [29]; default: 0; + * Odd Frame + * 1'b0: Even (micro)Frame + * 1'b1: Odd (micro)Frame + */ +#define USB_H_ODDFRM7 (BIT(29)) +#define USB_H_ODDFRM7_M (USB_H_ODDFRM7_V << USB_H_ODDFRM7_S) +#define USB_H_ODDFRM7_V 0x00000001 +#define USB_H_ODDFRM7_S 29 +/** USB_H_CHDIS7 : R/W; bitpos: [30]; default: 0; + * Channel Disable + * 0x0 : Transmit/Recieve norma + * 0x1 : Stop transmitting/receiving data on channel + */ +#define USB_H_CHDIS7 (BIT(30)) +#define USB_H_CHDIS7_M (USB_H_CHDIS7_V << USB_H_CHDIS7_S) +#define USB_H_CHDIS7_V 0x00000001 +#define USB_H_CHDIS7_S 30 +/** USB_H_CHENA7 : R/W; bitpos: [31]; default: 0; + * Channel Enable + * 0x0 :If Scatter/Gather mode is enabled, indicates that the descriptor structure is + * not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is + * disabled + * 0x1 : If Scatter/Gather mode is enabled, indicates that the descriptor structure + * and data buffer with data is set up and this channel can access the descriptor. If + * Scatter/Gather mode is disabled, indicates that the channel is enabled + */ +#define USB_H_CHENA7 (BIT(31)) +#define USB_H_CHENA7_M (USB_H_CHENA7_V << USB_H_CHENA7_S) +#define USB_H_CHENA7_V 0x00000001 +#define USB_H_CHENA7_S 31 + + +/** USB_HCDMA7_REG register + * Host Channel 7 DMA Address Register + */ +#define USB_HCDMA7_REG (SOC_DPORT_USB_BASE + 0x5f4) +/** USB_H_DMAADDR7 : R/W; bitpos: [32:0]; default: 0; + * In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: + * [31:9]: DMA Address + * [8:3]: Current Transfer Desc + * [2:0]: Reserved + */ +#define USB_H_DMAADDR7 0xFFFFFFFF +#define USB_H_DMAADDR7_M (USB_H_DMAADDR7_V << USB_H_DMAADDR7_S) +#define USB_H_DMAADDR7_V 0xFFFFFFFF +#define USB_H_DMAADDR7_S 0 + + +/** USB_DCFG_REG register + * Device Configuration Register + */ +#define USB_DCFG_REG (SOC_DPORT_USB_BASE + 0x800) +/** USB_NZSTSOUTHSHK : R/W; bitpos: [2]; default: 0; + * 1'b0: Send the received OUT packet to the application (zero-length or non-zero + * length) and send a handshake based on NAK and STALL bits for the endpoint in the + * Devce Endpoint Control Register + * 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not + * send the received OUT packet to the application + */ +#define USB_NZSTSOUTHSHK (BIT(2)) +#define USB_NZSTSOUTHSHK_M (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S) +#define USB_NZSTSOUTHSHK_V 0x00000001 +#define USB_NZSTSOUTHSHK_S 2 +/** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0; + * Device Address. + */ +#define USB_DEVADDR 0x0000007F +#define USB_DEVADDR_M (USB_DEVADDR_V << USB_DEVADDR_S) +#define USB_DEVADDR_V 0x0000007F +#define USB_DEVADDR_S 4 +/** USB_PERFRLINT : R/W; bitpos: [13:11]; default: 0; + * 0x0 (EOPF80): 80% of the (micro)Frame interval + * 0x1 (EOPF85): 85% of the (micro)Frame interval + * 0x2 (EOPF90): 90% of the (micro)Frame interval + * 0x3 (EOPF95): 95% of the (micro)Frame interval + */ +#define USB_PERFRLINT 0x00000003 +#define USB_PERFRLINT_M (USB_PERFRLINT_V << USB_PERFRLINT_S) +#define USB_PERFRLINT_V 0x00000003 +#define USB_PERFRLINT_S 11 +/** USB_ENDEVOUTNAK : R/W; bitpos: [13]; default: 0; + * 1'b0:The core does not set NAK after Bulk OUT transfer complete + * 1'b1: The core sets NAK after Bulk OUT transfer complete + */ +#define USB_ENDEVOUTNAK (BIT(13)) +#define USB_ENDEVOUTNAK_M (USB_ENDEVOUTNAK_V << USB_ENDEVOUTNAK_S) +#define USB_ENDEVOUTNAK_V 0x00000001 +#define USB_ENDEVOUTNAK_S 13 +/** USB_XCVRDLY : R/W; bitpos: [14]; default: 0; + * 0x0 : No delay between xcvr_sel and txvalid during Device chirp + * 0x1 : Enable delay between xcvr_sel and txvalid during Device chirp + */ +#define USB_XCVRDLY (BIT(14)) +#define USB_XCVRDLY_M (USB_XCVRDLY_V << USB_XCVRDLY_S) +#define USB_XCVRDLY_V 0x00000001 +#define USB_XCVRDLY_S 14 +/** USB_ERRATICINTMSK : R/W; bitpos: [15]; default: 0; + * 0x0 : Early suspend interrupt is generated on erratic error + * 0x1: Mask early suspend interrupt on erratic error + */ +#define USB_ERRATICINTMSK (BIT(15)) +#define USB_ERRATICINTMSK_M (USB_ERRATICINTMSK_V << USB_ERRATICINTMSK_S) +#define USB_ERRATICINTMSK_V 0x00000001 +#define USB_ERRATICINTMSK_S 15 +/** USB_EPMISCNT : R/W; bitpos: [23:18]; default: 4; + * IN Endpoint Mismatch Count. + */ +#define USB_EPMISCNT 0x0000001F +#define USB_EPMISCNT_M (USB_EPMISCNT_V << USB_EPMISCNT_S) +#define USB_EPMISCNT_V 0x0000001F +#define USB_EPMISCNT_S 18 +/** USB_DESCDMA : R/W; bitpos: [23]; default: 0; + * 1'b0: Disable Scatter/Gather DMA + * 1'b1: Enable Scatter/Gather DMA + */ +#define USB_DESCDMA (BIT(23)) +#define USB_DESCDMA_M (USB_DESCDMA_V << USB_DESCDMA_S) +#define USB_DESCDMA_V 0x00000001 +#define USB_DESCDMA_S 23 +/** USB_PERSCHINTVL : R/W; bitpos: [26:24]; default: 0; + * Periodic Scheduling Interval + * 0x0 (MF25): 25% of (micro)Frame + * 0x1 (MF50): 50% of (micro)Frame + * 0x2 (MF75): 75% of (micro)Frame + * 0x3 (RESERVED): Reserved + */ +#define USB_PERSCHINTVL 0x00000003 +#define USB_PERSCHINTVL_M (USB_PERSCHINTVL_V << USB_PERSCHINTVL_S) +#define USB_PERSCHINTVL_V 0x00000003 +#define USB_PERSCHINTVL_S 24 +/** USB_RESVALID : R/W; bitpos: [32:26]; default: 2; + * This field is effective only when DCFG.Ena32KHzSusp is set. It controls the resume + * period when the core resumes from suspend. + * The core counts for ResValid number of clock cycles to detect a valid resume when + * this bit is set + */ +#define USB_RESVALID 0x0000003F +#define USB_RESVALID_M (USB_RESVALID_V << USB_RESVALID_S) +#define USB_RESVALID_V 0x0000003F +#define USB_RESVALID_S 26 + + +/** USB_DCTL_REG register + * Device Control Register + */ +#define USB_DCTL_REG (SOC_DPORT_USB_BASE + 0x804) +/** USB_RMTWKUPSIG : R/W; bitpos: [0]; default: 0; + * 0x0 : Core does not send Remote Wakeup Signaling + * 0x1 : Core sends Remote Wakeup Signalin + */ +#define USB_RMTWKUPSIG (BIT(0)) +#define USB_RMTWKUPSIG_M (USB_RMTWKUPSIG_V << USB_RMTWKUPSIG_S) +#define USB_RMTWKUPSIG_V 0x00000001 +#define USB_RMTWKUPSIG_S 0 +/** USB_SFTDISCON : R/W; bitpos: [1]; default: 0; + * 1'b0: Normal operation. When this bit is cleared after a soft disconnect, the core + * drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device + * connect event to the USB host. When the device is reconnected, the USB host + * restarts device enumeration + * 1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which + * generates a device disconnect event to the USB host + */ +#define USB_SFTDISCON (BIT(1)) +#define USB_SFTDISCON_M (USB_SFTDISCON_V << USB_SFTDISCON_S) +#define USB_SFTDISCON_V 0x00000001 +#define USB_SFTDISCON_S 1 +/** USB_GNPINNAKSTS : RO; bitpos: [2]; default: 0; + * 0x0 : A handshake is sent out based on the data availability in the transmit FIFO + * 0x1 : A NAK handshake is sent out on all non-periodic IN endpoints, irrespective + * of the data availability in the transmit FIFO + */ +#define USB_GNPINNAKSTS (BIT(2)) +#define USB_GNPINNAKSTS_M (USB_GNPINNAKSTS_V << USB_GNPINNAKSTS_S) +#define USB_GNPINNAKSTS_V 0x00000001 +#define USB_GNPINNAKSTS_S 2 +/** USB_GOUTNAKSTS : RO; bitpos: [3]; default: 0; + * 0x0 : A handshake is sent based on the FIFO Status and the NAK and STALL bit + * settings + * 0x1 : No data is written to the RxFIFO, irrespective of space availability. Sends + * a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT + * packets are dropped + */ +#define USB_GOUTNAKSTS (BIT(3)) +#define USB_GOUTNAKSTS_M (USB_GOUTNAKSTS_V << USB_GOUTNAKSTS_S) +#define USB_GOUTNAKSTS_V 0x00000001 +#define USB_GOUTNAKSTS_S 3 +/** USB_TSTCTL : R/W; bitpos: [7:4]; default: 0; + * 0x0: Test mode disabled + * 0x1: Test_J mode + * 0x2 : Test_K mode + * 0x3 : Test_SE0_NAK mode + * 0x4 : Test_Packet mode + * 0x5 : Test_force_Enable + */ +#define USB_TSTCTL 0x00000007 +#define USB_TSTCTL_M (USB_TSTCTL_V << USB_TSTCTL_S) +#define USB_TSTCTL_V 0x00000007 +#define USB_TSTCTL_S 4 +/** USB_SGNPINNAK : WO; bitpos: [7]; default: 0; + * Set Global Non-periodic IN NAK. A write to this field sets the Global Non-periodic + * IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN + * endpoints. The core can also Set this bit when a timeout condition is detected on a + * non-periodic endpoint in shared FIFO operation. The application must Set this bit + * only after making sure that the Global IN NAK Effective bit in the Core Interrupt + * Register (GINTSTS.GINNakEff) is cleared + */ +#define USB_SGNPINNAK (BIT(7)) +#define USB_SGNPINNAK_M (USB_SGNPINNAK_V << USB_SGNPINNAK_S) +#define USB_SGNPINNAK_V 0x00000001 +#define USB_SGNPINNAK_S 7 +/** USB_CGNPINNAK : WO; bitpos: [8]; default: 0; + * Clear Global Non-periodic IN NAK. A write to this field clears the Global + * Non-periodic IN NAK. + */ +#define USB_CGNPINNAK (BIT(8)) +#define USB_CGNPINNAK_M (USB_CGNPINNAK_V << USB_CGNPINNAK_S) +#define USB_CGNPINNAK_V 0x00000001 +#define USB_CGNPINNAK_S 8 +/** USB_SGOUTNAK : WO; bitpos: [9]; default: 0; + * Set Global OUT NAK. A write to this field sets the Global OUT NAK. The application + * uses this bit to send a NAK handshake on all OUT endpoints. The application must + * set the this bit only after making sure that the Global OUT NAK Effective bit in + * the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared. + */ +#define USB_SGOUTNAK (BIT(9)) +#define USB_SGOUTNAK_M (USB_SGOUTNAK_V << USB_SGOUTNAK_S) +#define USB_SGOUTNAK_V 0x00000001 +#define USB_SGOUTNAK_S 9 +/** USB_CGOUTNAK : WO; bitpos: [10]; default: 0; + * Clear Global OUT NAK. A write to this field clears the Global OUT NAK. + */ +#define USB_CGOUTNAK (BIT(10)) +#define USB_CGOUTNAK_M (USB_CGOUTNAK_V << USB_CGOUTNAK_S) +#define USB_CGOUTNAK_V 0x00000001 +#define USB_CGOUTNAK_S 10 +/** USB_PWRONPRGDONE : R/W; bitpos: [11]; default: 0; + * 1'b0: Power-On Programming not done + * 1'b1: Power-On Programming Done + */ +#define USB_PWRONPRGDONE (BIT(11)) +#define USB_PWRONPRGDONE_M (USB_PWRONPRGDONE_V << USB_PWRONPRGDONE_S) +#define USB_PWRONPRGDONE_V 0x00000001 +#define USB_PWRONPRGDONE_S 11 +/** USB_GMC : R/W; bitpos: [15:13]; default: 1; + * Global Multi Count. applicable only for Scatter/Gather DMA mode + * 0x0 : Invalid + * 0x1 : 1 packet + * 0x2 : 2 packets + * 0x3 : 3 packets + */ +#define USB_GMC 0x00000003 +#define USB_GMC_M (USB_GMC_V << USB_GMC_S) +#define USB_GMC_V 0x00000003 +#define USB_GMC_S 13 +/** USB_IGNRFRMNUM : R/W; bitpos: [15]; default: 0; + * 0: The core transmits the packets only in the frame number in which they are + * intended to be transmitted + * 1: The core ignores the frame number, sending packets immediately as the packets + * are ready + */ +#define USB_IGNRFRMNUM (BIT(15)) +#define USB_IGNRFRMNUM_M (USB_IGNRFRMNUM_V << USB_IGNRFRMNUM_S) +#define USB_IGNRFRMNUM_V 0x00000001 +#define USB_IGNRFRMNUM_S 15 +/** USB_NAKONBBLE : R/W; bitpos: [16]; default: 0; + * 1'b0: Disable NAK on Babble Error + * 1'b1: NAK on Babble Error + */ +#define USB_NAKONBBLE (BIT(16)) +#define USB_NAKONBBLE_M (USB_NAKONBBLE_V << USB_NAKONBBLE_S) +#define USB_NAKONBBLE_V 0x00000001 +#define USB_NAKONBBLE_S 16 +/** USB_ENCOUNTONBNA : R/W; bitpos: [17]; default: 0; + * 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the + * endpoint is re-enabled by the application,the core starts processing from the + * DOEPDMA descriptor + * 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the + * endpoint is re-enabled by the application, the core starts processing from the + * descriptor that received the BNA interrupt + */ +#define USB_ENCOUNTONBNA (BIT(17)) +#define USB_ENCOUNTONBNA_M (USB_ENCOUNTONBNA_V << USB_ENCOUNTONBNA_S) +#define USB_ENCOUNTONBNA_V 0x00000001 +#define USB_ENCOUNTONBNA_S 17 +/** USB_DEEPSLEEPBESLREJECT : R/W; bitpos: [18]; default: 0; + * 1'b0: Deep Sleep BESL Reject feature is disabled + * 1'b1: Deep Sleep BESL Reject feature is enabled + */ +#define USB_DEEPSLEEPBESLREJECT (BIT(18)) +#define USB_DEEPSLEEPBESLREJECT_M (USB_DEEPSLEEPBESLREJECT_V << USB_DEEPSLEEPBESLREJECT_S) +#define USB_DEEPSLEEPBESLREJECT_V 0x00000001 +#define USB_DEEPSLEEPBESLREJECT_S 18 + + +/** USB_DVBUSDIS_REG register + * Device VBUS Discharge Time Register + */ +#define USB_DVBUSDIS_REG (SOC_DPORT_USB_BASE + 0x828) +/** USB_DVBUSDIS : R/W; bitpos: [16:0]; default: 6103; + * Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals + * (VBUS discharge time in PHY clocks) / 1, 024. The value you use depends whether the + * PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width). + * Depending on your VBUS load, this value can need adjustment. + */ +#define USB_DVBUSDIS 0x0000FFFF +#define USB_DVBUSDIS_M (USB_DVBUSDIS_V << USB_DVBUSDIS_S) +#define USB_DVBUSDIS_V 0x0000FFFF +#define USB_DVBUSDIS_S 0 + + +/** USB_DVBUSPULSE_REG register + * Device VBUS Pulsing Time Register + */ +#define USB_DVBUSPULSE_REG (SOC_DPORT_USB_BASE + 0x82c) +/** USB_DVBUSPULSE : R/W; bitpos: [12:0]; default: 1464; + * Specifies the VBUS pulsing time during SRP. This value equals (VBUS pulsing time in + * PHY clocks) / 1, 024 The value you use depends whether the PHY is operating at + * 30MHz (16-bit data width) or 60 MHz (8-bit data width). + */ +#define USB_DVBUSPULSE 0x00000FFF +#define USB_DVBUSPULSE_M (USB_DVBUSPULSE_V << USB_DVBUSPULSE_S) +#define USB_DVBUSPULSE_V 0x00000FFF +#define USB_DVBUSPULSE_S 0 + + +/** USB_DTHRCTL_REG register + * Device Threshold Control Register + */ +#define USB_DTHRCTL_REG (SOC_DPORT_USB_BASE + 0x830) +/** USB_NONISOTHREN : R/W; bitpos: [0]; default: 0; + * Non-ISO IN Endpoints Threshold Enable + * 0x0 : No thresholding + * 0x1 : Enable thresholding for non-isochronous IN endpoints + */ +#define USB_NONISOTHREN (BIT(0)) +#define USB_NONISOTHREN_M (USB_NONISOTHREN_V << USB_NONISOTHREN_S) +#define USB_NONISOTHREN_V 0x00000001 +#define USB_NONISOTHREN_S 0 +/** USB_ISOTHREN : R/W; bitpos: [1]; default: 0; + * ISO IN Endpoints Threshold Enable + * 0x0 : No thresholding + * 0x1 : Enables thresholding for isochronous IN endpoints + */ +#define USB_ISOTHREN (BIT(1)) +#define USB_ISOTHREN_M (USB_ISOTHREN_V << USB_ISOTHREN_S) +#define USB_ISOTHREN_V 0x00000001 +#define USB_ISOTHREN_S 1 +/** USB_TXTHRLEN : R/W; bitpos: [11:2]; default: 8; + * This field specifies Transmit thresholding size in DWORDS. This also forms the MAC + * threshold and specifies the amount of data in bytes to be in the corresponding + * endpoint transmit FIFO, before the core can start transmit on the USB. The + * threshold length has to be at least eight DWORDS when the value of AHBThrRatio is + * 2'h00. In case the AHBThrRatio is non zero the application needs to ensure that the + * AHB Threshold value does not go below the recommended eight DWORD. This field + * controls both isochronous and non-isochronous IN endpoint thresholds. The + * recommended value for ThrLen is to be the same as the programmed AHB Burst Length + * (GAHBCFG.HBstLen). + */ +#define USB_TXTHRLEN 0x000001FF +#define USB_TXTHRLEN_M (USB_TXTHRLEN_V << USB_TXTHRLEN_S) +#define USB_TXTHRLEN_V 0x000001FF +#define USB_TXTHRLEN_S 2 +/** USB_AHBTHRRATIO : R/W; bitpos: [13:11]; default: 0; + * 2'b00: AHB threshold = MAC threshold + * 2'b01: AHB threshold = MAC threshold/2 + * 2'b10: AHB threshold = MAC threshold/4 + * 2'b11: AHB threshold = MAC threshold/8 + */ +#define USB_AHBTHRRATIO 0x00000003 +#define USB_AHBTHRRATIO_M (USB_AHBTHRRATIO_V << USB_AHBTHRRATIO_S) +#define USB_AHBTHRRATIO_V 0x00000003 +#define USB_AHBTHRRATIO_S 11 +/** USB_RXTHREN : R/W; bitpos: [16]; default: 0; + * 0x0 : Disable thresholding + * 0x1 : Enable thresholding in the receive direction + */ +#define USB_RXTHREN (BIT(16)) +#define USB_RXTHREN_M (USB_RXTHREN_V << USB_RXTHREN_S) +#define USB_RXTHREN_V 0x00000001 +#define USB_RXTHREN_S 16 +/** USB_RXTHRLEN : R/W; bitpos: [26:17]; default: 1; + * Receive Threshold Length. This field specifies Receive thresholding size in + * DWORDS. This field also specifies the amount of data received on the USB before the + * core can start transmitting on the AHB. The threshold length has to be at least + * eight DWORDS. The recommended value for ThrLen is to be the same as the programmed + * AHB Burst Length(GAHBCFG.HBstLen). + */ +#define USB_RXTHRLEN 0x000001FF +#define USB_RXTHRLEN_M (USB_RXTHRLEN_V << USB_RXTHRLEN_S) +#define USB_RXTHRLEN_V 0x000001FF +#define USB_RXTHRLEN_S 17 +/** USB_ARBPRKEN : R/W; bitpos: [27]; default: 1; + * 0x0 : Disable DMA arbiter parking + * 0x1 : Enable DMA arbiter parking for IN endpoints + */ +#define USB_ARBPRKEN (BIT(27)) +#define USB_ARBPRKEN_M (USB_ARBPRKEN_V << USB_ARBPRKEN_S) +#define USB_ARBPRKEN_V 0x00000001 +#define USB_ARBPRKEN_S 27 + + +/** USB_DIEPCTL0_REG register + * Device Control IN Endpoint $n Control Register + */ +#define USB_DIEPCTL0_REG (SOC_DPORT_USB_BASE + 0x900) +/** USB_D_MPS0 : R/W; bitpos: [2:0]; default: 0; + * Maximum Packet Size + * 0x0 : 64 bytes + * 0x1 : 32 bytes + * 0x2 : 16 bytes + * 0x3 : 8 bytes + */ +#define USB_D_MPS0 0x00000003 +#define USB_D_MPS0_M (USB_D_MPS0_V << USB_D_MPS0_S) +#define USB_D_MPS0_V 0x00000003 +#define USB_D_MPS0_S 0 +/** USB_D_USBACTEP0 : RO; bitpos: [15]; default: 1; + * USB Active Endpoint + * 0x1 : Control endpoint is always active + */ +#define USB_D_USBACTEP0 (BIT(15)) +#define USB_D_USBACTEP0_M (USB_D_USBACTEP0_V << USB_D_USBACTEP0_S) +#define USB_D_USBACTEP0_V 0x00000001 +#define USB_D_USBACTEP0_S 15 +/** USB_D_NAKSTS0 : RO; bitpos: [17]; default: 0; + * NAK Status + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status + * 0x1 : The core is transmitting NAK handshakes on this endpoint + */ +#define USB_D_NAKSTS0 (BIT(17)) +#define USB_D_NAKSTS0_M (USB_D_NAKSTS0_V << USB_D_NAKSTS0_S) +#define USB_D_NAKSTS0_V 0x00000001 +#define USB_D_NAKSTS0_S 17 +/** USB_D_EPTYPE0 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 0 + */ +#define USB_D_EPTYPE0 0x00000003 +#define USB_D_EPTYPE0_M (USB_D_EPTYPE0_V << USB_D_EPTYPE0_S) +#define USB_D_EPTYPE0_V 0x00000003 +#define USB_D_EPTYPE0_S 18 +/** USB_D_STALL0 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it + * 0x0 : No Stall + * 0x1 : Stall Handshake + */ +#define USB_D_STALL0 (BIT(21)) +#define USB_D_STALL0_M (USB_D_STALL0_V << USB_D_STALL0_S) +#define USB_D_STALL0_V 0x00000001 +#define USB_D_STALL0_S 21 +/** USB_D_TXFNUM0 : R/W; bitpos: [26:22]; default: 0; + * TxFIFO Number. + */ +#define USB_D_TXFNUM0 0x0000000F +#define USB_D_TXFNUM0_M (USB_D_TXFNUM0_V << USB_D_TXFNUM0_S) +#define USB_D_TXFNUM0_V 0x0000000F +#define USB_D_TXFNUM0_S 22 +/** USB_D_CNAK0 : WO; bitpos: [26]; default: 0; + * A write to this bit clears the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_D_CNAK0 (BIT(26)) +#define USB_D_CNAK0_M (USB_D_CNAK0_V << USB_D_CNAK0_S) +#define USB_D_CNAK0_V 0x00000001 +#define USB_D_CNAK0_S 26 +/** USB_DI_SNAK0 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DI_SNAK0 (BIT(27)) +#define USB_DI_SNAK0_M (USB_DI_SNAK0_V << USB_DI_SNAK0_S) +#define USB_DI_SNAK0_V 0x00000001 +#define USB_DI_SNAK0_S 27 +/** USB_D_EPDIS0 : R/W; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No action + * 0x1 : Disabled Endpoint + */ +#define USB_D_EPDIS0 (BIT(30)) +#define USB_D_EPDIS0_M (USB_D_EPDIS0_V << USB_D_EPDIS0_S) +#define USB_D_EPDIS0_V 0x00000001 +#define USB_D_EPDIS0_S 30 +/** USB_D_EPENA0 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_D_EPENA0 (BIT(31)) +#define USB_D_EPENA0_M (USB_D_EPENA0_V << USB_D_EPENA0_S) +#define USB_D_EPENA0_V 0x00000001 +#define USB_D_EPENA0_S 31 + + +/** USB_DIEPTSIZ0_REG register + * Device IN Endpoint 0 Transfer Size Register + */ +#define USB_DIEPTSIZ0_REG (SOC_DPORT_USB_BASE + 0x910) +/** USB_D_XFERSIZE0 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size + * IN Endpoints: The core decrements this field every time a packet from the external + * memory is written to the TxFIFO + * OUT Endpoints: The core decrements this field every time a packet is read from the + * RxFIFO and written to the external memory + */ +#define USB_D_XFERSIZE0 0x0000007F +#define USB_D_XFERSIZE0_M (USB_D_XFERSIZE0_V << USB_D_XFERSIZE0_S) +#define USB_D_XFERSIZE0_V 0x0000007F +#define USB_D_XFERSIZE0_S 0 +/** USB_D_PKTCNT0 : R/W; bitpos: [21:19]; default: 0; + * Packet Count + * IN Endpoints : This field is decremented every time a packet (maximum size or short + * packet) is read from the TxFIFO + * OUT Endpoints: This field is decremented every time a packet (maximum size or short + * packet) is written to the RxFIFO + */ +#define USB_D_PKTCNT0 0x00000003 +#define USB_D_PKTCNT0_M (USB_D_PKTCNT0_V << USB_D_PKTCNT0_S) +#define USB_D_PKTCNT0_V 0x00000003 +#define USB_D_PKTCNT0_S 19 + + +/** USB_DIEPDMA0_REG register + * Device IN Endpoint 0 DMA Address Register + */ +#define USB_DIEPDMA0_REG (SOC_DPORT_USB_BASE + 0x914) +/** USB_D_DMAADDR0 : R/W; bitpos: [32:0]; default: 0; + * This field holds the start address of the external memory for storing or fetching + * endpoint data. + */ +#define USB_D_DMAADDR0 0xFFFFFFFF +#define USB_D_DMAADDR0_M (USB_D_DMAADDR0_V << USB_D_DMAADDR0_S) +#define USB_D_DMAADDR0_V 0xFFFFFFFF +#define USB_D_DMAADDR0_S 0 + + +/** USB_DIEPCTL1_REG register + * Device Control IN Endpoint $n Control Register + */ +#define USB_DIEPCTL1_REG (SOC_DPORT_USB_BASE + 0x920) +/** USB_D_MPS1 : R/W; bitpos: [2:0]; default: 0; + * Maximum Packet Size + * 0x0 : 64 bytes + * 0x1 : 32 bytes + * 0x2 : 16 bytes + * 0x3 : 8 bytes + */ +#define USB_D_MPS1 0x00000003 +#define USB_D_MPS1_M (USB_D_MPS1_V << USB_D_MPS1_S) +#define USB_D_MPS1_V 0x00000003 +#define USB_D_MPS1_S 0 +/** USB_D_USBACTEP1 : RO; bitpos: [15]; default: 1; + * USB Active Endpoint + * 0x1 : Control endpoint is always active + */ +#define USB_D_USBACTEP1 (BIT(15)) +#define USB_D_USBACTEP1_M (USB_D_USBACTEP1_V << USB_D_USBACTEP1_S) +#define USB_D_USBACTEP1_V 0x00000001 +#define USB_D_USBACTEP1_S 15 +/** USB_D_NAKSTS1 : RO; bitpos: [17]; default: 0; + * NAK Status + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status + * 0x1 : The core is transmitting NAK handshakes on this endpoint + */ +#define USB_D_NAKSTS1 (BIT(17)) +#define USB_D_NAKSTS1_M (USB_D_NAKSTS1_V << USB_D_NAKSTS1_S) +#define USB_D_NAKSTS1_V 0x00000001 +#define USB_D_NAKSTS1_S 17 +/** USB_D_EPTYPE1 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 0 + */ +#define USB_D_EPTYPE1 0x00000003 +#define USB_D_EPTYPE1_M (USB_D_EPTYPE1_V << USB_D_EPTYPE1_S) +#define USB_D_EPTYPE1_V 0x00000003 +#define USB_D_EPTYPE1_S 18 +/** USB_D_STALL1 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it + * 0x0 : No Stall + * 0x1 : Stall Handshake + */ +#define USB_D_STALL1 (BIT(21)) +#define USB_D_STALL1_M (USB_D_STALL1_V << USB_D_STALL1_S) +#define USB_D_STALL1_V 0x00000001 +#define USB_D_STALL1_S 21 +/** USB_D_TXFNUM1 : R/W; bitpos: [26:22]; default: 0; + * TxFIFO Number. + */ +#define USB_D_TXFNUM1 0x0000000F +#define USB_D_TXFNUM1_M (USB_D_TXFNUM1_V << USB_D_TXFNUM1_S) +#define USB_D_TXFNUM1_V 0x0000000F +#define USB_D_TXFNUM1_S 22 +/** USB_D_CNAK1 : WO; bitpos: [26]; default: 0; + * A write to this bit clears the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_D_CNAK1 (BIT(26)) +#define USB_D_CNAK1_M (USB_D_CNAK1_V << USB_D_CNAK1_S) +#define USB_D_CNAK1_V 0x00000001 +#define USB_D_CNAK1_S 26 +/** USB_DI_SNAK1 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DI_SNAK1 (BIT(27)) +#define USB_DI_SNAK1_M (USB_DI_SNAK1_V << USB_DI_SNAK1_S) +#define USB_DI_SNAK1_V 0x00000001 +#define USB_DI_SNAK1_S 27 +/** USB_DI_SETD0PID1 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DI_SETD0PID1 (BIT(28)) +#define USB_DI_SETD0PID1_M (USB_DI_SETD0PID1_V << USB_DI_SETD0PID1_S) +#define USB_DI_SETD0PID1_V 0x00000001 +#define USB_DI_SETD0PID1_S 28 +/** USB_DI_SETD1PID1 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DI_SETD1PID1 (BIT(29)) +#define USB_DI_SETD1PID1_M (USB_DI_SETD1PID1_V << USB_DI_SETD1PID1_S) +#define USB_DI_SETD1PID1_V 0x00000001 +#define USB_DI_SETD1PID1_S 29 +/** USB_D_EPDIS1 : R/W; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No action + * 0x1 : Disabled Endpoint + */ +#define USB_D_EPDIS1 (BIT(30)) +#define USB_D_EPDIS1_M (USB_D_EPDIS1_V << USB_D_EPDIS1_S) +#define USB_D_EPDIS1_V 0x00000001 +#define USB_D_EPDIS1_S 30 +/** USB_D_EPENA1 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_D_EPENA1 (BIT(31)) +#define USB_D_EPENA1_M (USB_D_EPENA1_V << USB_D_EPENA1_S) +#define USB_D_EPENA1_V 0x00000001 +#define USB_D_EPENA1_S 31 + + +/** USB_DIEPTSIZ1_REG register + * Device IN Endpoint 1 Transfer Size Register + */ +#define USB_DIEPTSIZ1_REG (SOC_DPORT_USB_BASE + 0x930) +/** USB_D_XFERSIZE1 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size + * IN Endpoints: The core decrements this field every time a packet from the external + * memory is written to the TxFIFO + * OUT Endpoints: The core decrements this field every time a packet is read from the + * RxFIFO and written to the external memory + */ +#define USB_D_XFERSIZE1 0x0000007F +#define USB_D_XFERSIZE1_M (USB_D_XFERSIZE1_V << USB_D_XFERSIZE1_S) +#define USB_D_XFERSIZE1_V 0x0000007F +#define USB_D_XFERSIZE1_S 0 +/** USB_D_PKTCNT1 : R/W; bitpos: [21:19]; default: 0; + * Packet Count + * IN Endpoints : This field is decremented every time a packet (maximum size or short + * packet) is read from the TxFIFO + * OUT Endpoints: This field is decremented every time a packet (maximum size or short + * packet) is written to the RxFIFO + */ +#define USB_D_PKTCNT1 0x00000003 +#define USB_D_PKTCNT1_M (USB_D_PKTCNT1_V << USB_D_PKTCNT1_S) +#define USB_D_PKTCNT1_V 0x00000003 +#define USB_D_PKTCNT1_S 19 + + +/** USB_DIEPDMA1_REG register + * Device IN Endpoint 1 DMA Address Register + */ +#define USB_DIEPDMA1_REG (SOC_DPORT_USB_BASE + 0x934) +/** USB_D_DMAADDR1 : R/W; bitpos: [32:0]; default: 0; + * This field holds the start address of the external memory for storing or fetching + * endpoint data. + */ +#define USB_D_DMAADDR1 0xFFFFFFFF +#define USB_D_DMAADDR1_M (USB_D_DMAADDR1_V << USB_D_DMAADDR1_S) +#define USB_D_DMAADDR1_V 0xFFFFFFFF +#define USB_D_DMAADDR1_S 0 + + +/** USB_DIEPCTL2_REG register + * Device Control IN Endpoint 2 Control Register + */ +#define USB_DIEPCTL2_REG (SOC_DPORT_USB_BASE + 0x940) +/** USB_D_MPS2 : R/W; bitpos: [2:0]; default: 0; + * Maximum Packet Size + * 0x0 : 64 bytes + * 0x1 : 32 bytes + * 0x2 : 16 bytes + * 0x3 : 8 bytes + */ +#define USB_D_MPS2 0x00000003 +#define USB_D_MPS2_M (USB_D_MPS2_V << USB_D_MPS2_S) +#define USB_D_MPS2_V 0x00000003 +#define USB_D_MPS2_S 0 +/** USB_D_USBACTEP2 : RO; bitpos: [15]; default: 1; + * USB Active Endpoint + * 0x1 : Control endpoint is always active + */ +#define USB_D_USBACTEP2 (BIT(15)) +#define USB_D_USBACTEP2_M (USB_D_USBACTEP2_V << USB_D_USBACTEP2_S) +#define USB_D_USBACTEP2_V 0x00000001 +#define USB_D_USBACTEP2_S 15 +/** USB_D_NAKSTS2 : RO; bitpos: [17]; default: 0; + * NAK Status + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status + * 0x1 : The core is transmitting NAK handshakes on this endpoint + */ +#define USB_D_NAKSTS2 (BIT(17)) +#define USB_D_NAKSTS2_M (USB_D_NAKSTS2_V << USB_D_NAKSTS2_S) +#define USB_D_NAKSTS2_V 0x00000001 +#define USB_D_NAKSTS2_S 17 +/** USB_D_EPTYPE2 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 0 + */ +#define USB_D_EPTYPE2 0x00000003 +#define USB_D_EPTYPE2_M (USB_D_EPTYPE2_V << USB_D_EPTYPE2_S) +#define USB_D_EPTYPE2_V 0x00000003 +#define USB_D_EPTYPE2_S 18 +/** USB_D_STALL2 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it + * 0x0 : No Stall + * 0x1 : Stall Handshake + */ +#define USB_D_STALL2 (BIT(21)) +#define USB_D_STALL2_M (USB_D_STALL2_V << USB_D_STALL2_S) +#define USB_D_STALL2_V 0x00000001 +#define USB_D_STALL2_S 21 +/** USB_D_TXFNUM2 : R/W; bitpos: [26:22]; default: 0; + * TxFIFO Number. + */ +#define USB_D_TXFNUM2 0x0000000F +#define USB_D_TXFNUM2_M (USB_D_TXFNUM2_V << USB_D_TXFNUM2_S) +#define USB_D_TXFNUM2_V 0x0000000F +#define USB_D_TXFNUM2_S 22 +/** USB_D_CNAK2 : WO; bitpos: [26]; default: 0; + * A write to this bit clears the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_D_CNAK2 (BIT(26)) +#define USB_D_CNAK2_M (USB_D_CNAK2_V << USB_D_CNAK2_S) +#define USB_D_CNAK2_V 0x00000001 +#define USB_D_CNAK2_S 26 +/** USB_DI_SNAK2 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DI_SNAK2 (BIT(27)) +#define USB_DI_SNAK2_M (USB_DI_SNAK2_V << USB_DI_SNAK2_S) +#define USB_DI_SNAK2_V 0x00000001 +#define USB_DI_SNAK2_S 27 +/** USB_DI_SETD0PID2 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DI_SETD0PID2 (BIT(28)) +#define USB_DI_SETD0PID2_M (USB_DI_SETD0PID2_V << USB_DI_SETD0PID2_S) +#define USB_DI_SETD0PID2_V 0x00000001 +#define USB_DI_SETD0PID2_S 28 +/** USB_DI_SETD1PID2 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DI_SETD1PID2 (BIT(29)) +#define USB_DI_SETD1PID2_M (USB_DI_SETD1PID2_V << USB_DI_SETD1PID2_S) +#define USB_DI_SETD1PID2_V 0x00000001 +#define USB_DI_SETD1PID2_S 29 +/** USB_D_EPDIS2 : R/W; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No action + * 0x1 : Disabled Endpoint + */ +#define USB_D_EPDIS2 (BIT(30)) +#define USB_D_EPDIS2_M (USB_D_EPDIS2_V << USB_D_EPDIS2_S) +#define USB_D_EPDIS2_V 0x00000001 +#define USB_D_EPDIS2_S 30 +/** USB_D_EPENA2 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_D_EPENA2 (BIT(31)) +#define USB_D_EPENA2_M (USB_D_EPENA2_V << USB_D_EPENA2_S) +#define USB_D_EPENA2_V 0x00000001 +#define USB_D_EPENA2_S 31 + + +/** USB_DIEPTSIZ2_REG register + * Device IN Endpoint 2 Transfer Size Register + */ +#define USB_DIEPTSIZ2_REG (SOC_DPORT_USB_BASE + 0x950) +/** USB_D_XFERSIZE2 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size + * IN Endpoints: The core decrements this field every time a packet from the external + * memory is written to the TxFIFO + * OUT Endpoints: The core decrements this field every time a packet is read from the + * RxFIFO and written to the external memory + */ +#define USB_D_XFERSIZE2 0x0000007F +#define USB_D_XFERSIZE2_M (USB_D_XFERSIZE2_V << USB_D_XFERSIZE2_S) +#define USB_D_XFERSIZE2_V 0x0000007F +#define USB_D_XFERSIZE2_S 0 +/** USB_D_PKTCNT2 : R/W; bitpos: [21:19]; default: 0; + * Packet Count + * IN Endpoints : This field is decremented every time a packet (maximum size or short + * packet) is read from the TxFIFO + * OUT Endpoints: This field is decremented every time a packet (maximum size or short + * packet) is written to the RxFIFO + */ +#define USB_D_PKTCNT2 0x00000003 +#define USB_D_PKTCNT2_M (USB_D_PKTCNT2_V << USB_D_PKTCNT2_S) +#define USB_D_PKTCNT2_V 0x00000003 +#define USB_D_PKTCNT2_S 19 + + +/** USB_DIEPDMA2_REG register + * Device IN Endpoint 2 DMA Address Register + */ +#define USB_DIEPDMA2_REG (SOC_DPORT_USB_BASE + 0x954) +/** USB_D_DMAADDR2 : R/W; bitpos: [32:0]; default: 0; + * This field holds the start address of the external memory for storing or fetching + * endpoint data. + */ +#define USB_D_DMAADDR2 0xFFFFFFFF +#define USB_D_DMAADDR2_M (USB_D_DMAADDR2_V << USB_D_DMAADDR2_S) +#define USB_D_DMAADDR2_V 0xFFFFFFFF +#define USB_D_DMAADDR2_S 0 + + +/** USB_DIEPCTL3_REG register + * Device Control IN Endpoint $n Control Register + */ +#define USB_DIEPCTL3_REG (SOC_DPORT_USB_BASE + 0x960) +/** USB_DI_MPS3 : R/W; bitpos: [2:0]; default: 0; + * Maximum Packet Size + * 0x0 : 64 bytes + * 0x1 : 32 bytes + * 0x2 : 16 bytes + * 0x3 : 8 bytes + */ +#define USB_DI_MPS3 0x00000003 +#define USB_DI_MPS3_M (USB_DI_MPS3_V << USB_DI_MPS3_S) +#define USB_DI_MPS3_V 0x00000003 +#define USB_DI_MPS3_S 0 +/** USB_DI_USBACTEP3 : RO; bitpos: [15]; default: 1; + * USB Active Endpoint + * 0x1 : Control endpoint is always active + */ +#define USB_DI_USBACTEP3 (BIT(15)) +#define USB_DI_USBACTEP3_M (USB_DI_USBACTEP3_V << USB_DI_USBACTEP3_S) +#define USB_DI_USBACTEP3_V 0x00000001 +#define USB_DI_USBACTEP3_S 15 +/** USB_DI_NAKSTS3 : RO; bitpos: [17]; default: 0; + * NAK Status + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status + * 0x1 : The core is transmitting NAK handshakes on this endpoint + */ +#define USB_DI_NAKSTS3 (BIT(17)) +#define USB_DI_NAKSTS3_M (USB_DI_NAKSTS3_V << USB_DI_NAKSTS3_S) +#define USB_DI_NAKSTS3_V 0x00000001 +#define USB_DI_NAKSTS3_S 17 +/** USB_DI_EPTYPE3 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 0 + */ +#define USB_DI_EPTYPE3 0x00000003 +#define USB_DI_EPTYPE3_M (USB_DI_EPTYPE3_V << USB_DI_EPTYPE3_S) +#define USB_DI_EPTYPE3_V 0x00000003 +#define USB_DI_EPTYPE3_S 18 +/** USB_DI_STALL3 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it + * 0x0 : No Stall + * 0x1 : Stall Handshake + */ +#define USB_DI_STALL3 (BIT(21)) +#define USB_DI_STALL3_M (USB_DI_STALL3_V << USB_DI_STALL3_S) +#define USB_DI_STALL3_V 0x00000001 +#define USB_DI_STALL3_S 21 +/** USB_DI_TXFNUM3 : R/W; bitpos: [26:22]; default: 0; + * TxFIFO Number. + */ +#define USB_DI_TXFNUM3 0x0000000F +#define USB_DI_TXFNUM3_M (USB_DI_TXFNUM3_V << USB_DI_TXFNUM3_S) +#define USB_DI_TXFNUM3_V 0x0000000F +#define USB_DI_TXFNUM3_S 22 +/** USB_DI_CNAK3 : WO; bitpos: [26]; default: 0; + * A write to this bit clears the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_DI_CNAK3 (BIT(26)) +#define USB_DI_CNAK3_M (USB_DI_CNAK3_V << USB_DI_CNAK3_S) +#define USB_DI_CNAK3_V 0x00000001 +#define USB_DI_CNAK3_S 26 +/** USB_DI_SNAK3 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DI_SNAK3 (BIT(27)) +#define USB_DI_SNAK3_M (USB_DI_SNAK3_V << USB_DI_SNAK3_S) +#define USB_DI_SNAK3_V 0x00000001 +#define USB_DI_SNAK3_S 27 +/** USB_DI_SETD0PID3 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DI_SETD0PID3 (BIT(28)) +#define USB_DI_SETD0PID3_M (USB_DI_SETD0PID3_V << USB_DI_SETD0PID3_S) +#define USB_DI_SETD0PID3_V 0x00000001 +#define USB_DI_SETD0PID3_S 28 +/** USB_DI_SETD1PID3 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DI_SETD1PID3 (BIT(29)) +#define USB_DI_SETD1PID3_M (USB_DI_SETD1PID3_V << USB_DI_SETD1PID3_S) +#define USB_DI_SETD1PID3_V 0x00000001 +#define USB_DI_SETD1PID3_S 29 +/** USB_DI_EPDIS3 : R/W; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No action + * 0x1 : Disabled Endpoint + */ +#define USB_DI_EPDIS3 (BIT(30)) +#define USB_DI_EPDIS3_M (USB_DI_EPDIS3_V << USB_DI_EPDIS3_S) +#define USB_DI_EPDIS3_V 0x00000001 +#define USB_DI_EPDIS3_S 30 +/** USB_DI_EPENA3 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_DI_EPENA3 (BIT(31)) +#define USB_DI_EPENA3_M (USB_DI_EPENA3_V << USB_DI_EPENA3_S) +#define USB_DI_EPENA3_V 0x00000001 +#define USB_DI_EPENA3_S 31 + + +/** USB_DIEPTSIZ3_REG register + * Device IN Endpoint 3 Transfer Size Register + */ +#define USB_DIEPTSIZ3_REG (SOC_DPORT_USB_BASE + 0x970) +/** USB_D_XFERSIZE3 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size + * IN Endpoints: The core decrements this field every time a packet from the external + * memory is written to the TxFIFO + * OUT Endpoints: The core decrements this field every time a packet is read from the + * RxFIFO and written to the external memory + */ +#define USB_D_XFERSIZE3 0x0000007F +#define USB_D_XFERSIZE3_M (USB_D_XFERSIZE3_V << USB_D_XFERSIZE3_S) +#define USB_D_XFERSIZE3_V 0x0000007F +#define USB_D_XFERSIZE3_S 0 +/** USB_D_PKTCNT3 : R/W; bitpos: [21:19]; default: 0; + * Packet Count + * IN Endpoints : This field is decremented every time a packet (maximum size or short + * packet) is read from the TxFIFO + * OUT Endpoints: This field is decremented every time a packet (maximum size or short + * packet) is written to the RxFIFO + */ +#define USB_D_PKTCNT3 0x00000003 +#define USB_D_PKTCNT3_M (USB_D_PKTCNT3_V << USB_D_PKTCNT3_S) +#define USB_D_PKTCNT3_V 0x00000003 +#define USB_D_PKTCNT3_S 19 + + +/** USB_DIEPDMA3_REG register + * Device IN Endpoint 3 DMA Address Register + */ +#define USB_DIEPDMA3_REG (SOC_DPORT_USB_BASE + 0x974) +/** USB_D_DMAADDR3 : R/W; bitpos: [32:0]; default: 0; + * This field holds the start address of the external memory for storing or fetching + * endpoint data. + */ +#define USB_D_DMAADDR3 0xFFFFFFFF +#define USB_D_DMAADDR3_M (USB_D_DMAADDR3_V << USB_D_DMAADDR3_S) +#define USB_D_DMAADDR3_V 0xFFFFFFFF +#define USB_D_DMAADDR3_S 0 + + +/** USB_DIEPCTL4_REG register + * Device Control IN Endpoint $n Control Register + */ +#define USB_DIEPCTL4_REG (SOC_DPORT_USB_BASE + 0x980) +/** USB_D_MPS4 : R/W; bitpos: [2:0]; default: 0; + * Maximum Packet Size + * 0x0 : 64 bytes + * 0x1 : 32 bytes + * 0x2 : 16 bytes + * 0x3 : 8 bytes + */ +#define USB_D_MPS4 0x00000003 +#define USB_D_MPS4_M (USB_D_MPS4_V << USB_D_MPS4_S) +#define USB_D_MPS4_V 0x00000003 +#define USB_D_MPS4_S 0 +/** USB_D_USBACTEP4 : RO; bitpos: [15]; default: 1; + * USB Active Endpoint + * 0x1 : Control endpoint is always active + */ +#define USB_D_USBACTEP4 (BIT(15)) +#define USB_D_USBACTEP4_M (USB_D_USBACTEP4_V << USB_D_USBACTEP4_S) +#define USB_D_USBACTEP4_V 0x00000001 +#define USB_D_USBACTEP4_S 15 +/** USB_D_NAKSTS4 : RO; bitpos: [17]; default: 0; + * NAK Status + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status + * 0x1 : The core is transmitting NAK handshakes on this endpoint + */ +#define USB_D_NAKSTS4 (BIT(17)) +#define USB_D_NAKSTS4_M (USB_D_NAKSTS4_V << USB_D_NAKSTS4_S) +#define USB_D_NAKSTS4_V 0x00000001 +#define USB_D_NAKSTS4_S 17 +/** USB_D_EPTYPE4 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 0 + */ +#define USB_D_EPTYPE4 0x00000003 +#define USB_D_EPTYPE4_M (USB_D_EPTYPE4_V << USB_D_EPTYPE4_S) +#define USB_D_EPTYPE4_V 0x00000003 +#define USB_D_EPTYPE4_S 18 +/** USB_D_STALL4 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it + * 0x0 : No Stall + * 0x1 : Stall Handshake + */ +#define USB_D_STALL4 (BIT(21)) +#define USB_D_STALL4_M (USB_D_STALL4_V << USB_D_STALL4_S) +#define USB_D_STALL4_V 0x00000001 +#define USB_D_STALL4_S 21 +/** USB_D_TXFNUM4 : R/W; bitpos: [26:22]; default: 0; + * TxFIFO Number. + */ +#define USB_D_TXFNUM4 0x0000000F +#define USB_D_TXFNUM4_M (USB_D_TXFNUM4_V << USB_D_TXFNUM4_S) +#define USB_D_TXFNUM4_V 0x0000000F +#define USB_D_TXFNUM4_S 22 +/** USB_D_CNAK4 : WO; bitpos: [26]; default: 0; + * A write to this bit clears the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_D_CNAK4 (BIT(26)) +#define USB_D_CNAK4_M (USB_D_CNAK4_V << USB_D_CNAK4_S) +#define USB_D_CNAK4_V 0x00000001 +#define USB_D_CNAK4_S 26 +/** USB_DI_SNAK4 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DI_SNAK4 (BIT(27)) +#define USB_DI_SNAK4_M (USB_DI_SNAK4_V << USB_DI_SNAK4_S) +#define USB_DI_SNAK4_V 0x00000001 +#define USB_DI_SNAK4_S 27 +/** USB_DI_SETD0PID4 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DI_SETD0PID4 (BIT(28)) +#define USB_DI_SETD0PID4_M (USB_DI_SETD0PID4_V << USB_DI_SETD0PID4_S) +#define USB_DI_SETD0PID4_V 0x00000001 +#define USB_DI_SETD0PID4_S 28 +/** USB_DI_SETD1PID4 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DI_SETD1PID4 (BIT(29)) +#define USB_DI_SETD1PID4_M (USB_DI_SETD1PID4_V << USB_DI_SETD1PID4_S) +#define USB_DI_SETD1PID4_V 0x00000001 +#define USB_DI_SETD1PID4_S 29 +/** USB_D_EPDIS4 : R/W; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No action + * 0x1 : Disabled Endpoint + */ +#define USB_D_EPDIS4 (BIT(30)) +#define USB_D_EPDIS4_M (USB_D_EPDIS4_V << USB_D_EPDIS4_S) +#define USB_D_EPDIS4_V 0x00000001 +#define USB_D_EPDIS4_S 30 +/** USB_D_EPENA4 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_D_EPENA4 (BIT(31)) +#define USB_D_EPENA4_M (USB_D_EPENA4_V << USB_D_EPENA4_S) +#define USB_D_EPENA4_V 0x00000001 +#define USB_D_EPENA4_S 31 + + +/** USB_DIEPTSIZ4_REG register + * Device IN Endpoint 4 Transfer Size Register + */ +#define USB_DIEPTSIZ4_REG (SOC_DPORT_USB_BASE + 0x990) +/** USB_D_XFERSIZE4 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size + * IN Endpoints: The core decrements this field every time a packet from the external + * memory is written to the TxFIFO + * OUT Endpoints: The core decrements this field every time a packet is read from the + * RxFIFO and written to the external memory + */ +#define USB_D_XFERSIZE4 0x0000007F +#define USB_D_XFERSIZE4_M (USB_D_XFERSIZE4_V << USB_D_XFERSIZE4_S) +#define USB_D_XFERSIZE4_V 0x0000007F +#define USB_D_XFERSIZE4_S 0 +/** USB_D_PKTCNT4 : R/W; bitpos: [21:19]; default: 0; + * Packet Count + * IN Endpoints : This field is decremented every time a packet (maximum size or short + * packet) is read from the TxFIFO + * OUT Endpoints: This field is decremented every time a packet (maximum size or short + * packet) is written to the RxFIFO + */ +#define USB_D_PKTCNT4 0x00000003 +#define USB_D_PKTCNT4_M (USB_D_PKTCNT4_V << USB_D_PKTCNT4_S) +#define USB_D_PKTCNT4_V 0x00000003 +#define USB_D_PKTCNT4_S 19 + + +/** USB_DIEPDMA4_REG register + * Device IN Endpoint 4 DMA Address Register + */ +#define USB_DIEPDMA4_REG (SOC_DPORT_USB_BASE + 0x994) +/** USB_D_DMAADDR4 : R/W; bitpos: [32:0]; default: 0; + * This field holds the start address of the external memory for storing or fetching + * endpoint data. + */ +#define USB_D_DMAADDR4 0xFFFFFFFF +#define USB_D_DMAADDR4_M (USB_D_DMAADDR4_V << USB_D_DMAADDR4_S) +#define USB_D_DMAADDR4_V 0xFFFFFFFF +#define USB_D_DMAADDR4_S 0 + + +/** USB_DIEPCTL5_REG register + * Device Control IN Endpoint $n Control Register + */ +#define USB_DIEPCTL5_REG (SOC_DPORT_USB_BASE + 0x9a0) +/** USB_DI_MPS5 : R/W; bitpos: [2:0]; default: 0; + * Maximum Packet Size + * 0x0 : 64 bytes + * 0x1 : 32 bytes + * 0x2 : 16 bytes + * 0x3 : 8 bytes + */ +#define USB_DI_MPS5 0x00000003 +#define USB_DI_MPS5_M (USB_DI_MPS5_V << USB_DI_MPS5_S) +#define USB_DI_MPS5_V 0x00000003 +#define USB_DI_MPS5_S 0 +/** USB_DI_USBACTEP5 : RO; bitpos: [15]; default: 1; + * USB Active Endpoint + * 0x1 : Control endpoint is always active + */ +#define USB_DI_USBACTEP5 (BIT(15)) +#define USB_DI_USBACTEP5_M (USB_DI_USBACTEP5_V << USB_DI_USBACTEP5_S) +#define USB_DI_USBACTEP5_V 0x00000001 +#define USB_DI_USBACTEP5_S 15 +/** USB_DI_NAKSTS5 : RO; bitpos: [17]; default: 0; + * NAK Status + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status + * 0x1 : The core is transmitting NAK handshakes on this endpoint + */ +#define USB_DI_NAKSTS5 (BIT(17)) +#define USB_DI_NAKSTS5_M (USB_DI_NAKSTS5_V << USB_DI_NAKSTS5_S) +#define USB_DI_NAKSTS5_V 0x00000001 +#define USB_DI_NAKSTS5_S 17 +/** USB_DI_EPTYPE5 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 0 + */ +#define USB_DI_EPTYPE5 0x00000003 +#define USB_DI_EPTYPE5_M (USB_DI_EPTYPE5_V << USB_DI_EPTYPE5_S) +#define USB_DI_EPTYPE5_V 0x00000003 +#define USB_DI_EPTYPE5_S 18 +/** USB_DI_STALL5 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it + * 0x0 : No Stall + * 0x1 : Stall Handshake + */ +#define USB_DI_STALL5 (BIT(21)) +#define USB_DI_STALL5_M (USB_DI_STALL5_V << USB_DI_STALL5_S) +#define USB_DI_STALL5_V 0x00000001 +#define USB_DI_STALL5_S 21 +/** USB_DI_TXFNUM5 : R/W; bitpos: [26:22]; default: 0; + * TxFIFO Number. + */ +#define USB_DI_TXFNUM5 0x0000000F +#define USB_DI_TXFNUM5_M (USB_DI_TXFNUM5_V << USB_DI_TXFNUM5_S) +#define USB_DI_TXFNUM5_V 0x0000000F +#define USB_DI_TXFNUM5_S 22 +/** USB_DI_CNAK5 : WO; bitpos: [26]; default: 0; + * A write to this bit clears the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_DI_CNAK5 (BIT(26)) +#define USB_DI_CNAK5_M (USB_DI_CNAK5_V << USB_DI_CNAK5_S) +#define USB_DI_CNAK5_V 0x00000001 +#define USB_DI_CNAK5_S 26 +/** USB_DI_SNAK5 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DI_SNAK5 (BIT(27)) +#define USB_DI_SNAK5_M (USB_DI_SNAK5_V << USB_DI_SNAK5_S) +#define USB_DI_SNAK5_V 0x00000001 +#define USB_DI_SNAK5_S 27 +/** USB_DI_SETD0PID5 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DI_SETD0PID5 (BIT(28)) +#define USB_DI_SETD0PID5_M (USB_DI_SETD0PID5_V << USB_DI_SETD0PID5_S) +#define USB_DI_SETD0PID5_V 0x00000001 +#define USB_DI_SETD0PID5_S 28 +/** USB_DI_SETD1PID5 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DI_SETD1PID5 (BIT(29)) +#define USB_DI_SETD1PID5_M (USB_DI_SETD1PID5_V << USB_DI_SETD1PID5_S) +#define USB_DI_SETD1PID5_V 0x00000001 +#define USB_DI_SETD1PID5_S 29 +/** USB_DI_EPDIS5 : R/W; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No action + * 0x1 : Disabled Endpoint + */ +#define USB_DI_EPDIS5 (BIT(30)) +#define USB_DI_EPDIS5_M (USB_DI_EPDIS5_V << USB_DI_EPDIS5_S) +#define USB_DI_EPDIS5_V 0x00000001 +#define USB_DI_EPDIS5_S 30 +/** USB_DI_EPENA5 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_DI_EPENA5 (BIT(31)) +#define USB_DI_EPENA5_M (USB_DI_EPENA5_V << USB_DI_EPENA5_S) +#define USB_DI_EPENA5_V 0x00000001 +#define USB_DI_EPENA5_S 31 + + +/** USB_DIEPTSIZ5_REG register + * Device IN Endpoint 5 Transfer Size Register + */ +#define USB_DIEPTSIZ5_REG (SOC_DPORT_USB_BASE + 0x9b0) +/** USB_D_XFERSIZE5 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size + * IN Endpoints: The core decrements this field every time a packet from the external + * memory is written to the TxFIFO + * OUT Endpoints: The core decrements this field every time a packet is read from the + * RxFIFO and written to the external memory + */ +#define USB_D_XFERSIZE5 0x0000007F +#define USB_D_XFERSIZE5_M (USB_D_XFERSIZE5_V << USB_D_XFERSIZE5_S) +#define USB_D_XFERSIZE5_V 0x0000007F +#define USB_D_XFERSIZE5_S 0 +/** USB_D_PKTCNT5 : R/W; bitpos: [21:19]; default: 0; + * Packet Count + * IN Endpoints : This field is decremented every time a packet (maximum size or short + * packet) is read from the TxFIFO + * OUT Endpoints: This field is decremented every time a packet (maximum size or short + * packet) is written to the RxFIFO + */ +#define USB_D_PKTCNT5 0x00000003 +#define USB_D_PKTCNT5_M (USB_D_PKTCNT5_V << USB_D_PKTCNT5_S) +#define USB_D_PKTCNT5_V 0x00000003 +#define USB_D_PKTCNT5_S 19 + + +/** USB_DIEPDMA5_REG register + * Device IN Endpoint 5 DMA Address Register + */ +#define USB_DIEPDMA5_REG (SOC_DPORT_USB_BASE + 0x9b4) +/** USB_D_DMAADDR5 : R/W; bitpos: [32:0]; default: 0; + * This field holds the start address of the external memory for storing or fetching + * endpoint data. + */ +#define USB_D_DMAADDR5 0xFFFFFFFF +#define USB_D_DMAADDR5_M (USB_D_DMAADDR5_V << USB_D_DMAADDR5_S) +#define USB_D_DMAADDR5_V 0xFFFFFFFF +#define USB_D_DMAADDR5_S 0 + + +/** USB_DIEPCTL6_REG register + * Device Control IN Endpoint $n Control Register + */ +#define USB_DIEPCTL6_REG (SOC_DPORT_USB_BASE + 0x9c0) +/** USB_D_MPS6 : R/W; bitpos: [2:0]; default: 0; + * Maximum Packet Size + * 0x0 : 64 bytes + * 0x1 : 32 bytes + * 0x2 : 16 bytes + * 0x3 : 8 bytes + */ +#define USB_D_MPS6 0x00000003 +#define USB_D_MPS6_M (USB_D_MPS6_V << USB_D_MPS6_S) +#define USB_D_MPS6_V 0x00000003 +#define USB_D_MPS6_S 0 +/** USB_D_USBACTEP6 : RO; bitpos: [15]; default: 1; + * USB Active Endpoint + * 0x1 : Control endpoint is always active + */ +#define USB_D_USBACTEP6 (BIT(15)) +#define USB_D_USBACTEP6_M (USB_D_USBACTEP6_V << USB_D_USBACTEP6_S) +#define USB_D_USBACTEP6_V 0x00000001 +#define USB_D_USBACTEP6_S 15 +/** USB_D_NAKSTS6 : RO; bitpos: [17]; default: 0; + * NAK Status + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO Status + * 0x1 : The core is transmitting NAK handshakes on this endpoint + */ +#define USB_D_NAKSTS6 (BIT(17)) +#define USB_D_NAKSTS6_M (USB_D_NAKSTS6_V << USB_D_NAKSTS6_S) +#define USB_D_NAKSTS6_V 0x00000001 +#define USB_D_NAKSTS6_S 17 +/** USB_D_EPTYPE6 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 0 + */ +#define USB_D_EPTYPE6 0x00000003 +#define USB_D_EPTYPE6_M (USB_D_EPTYPE6_V << USB_D_EPTYPE6_S) +#define USB_D_EPTYPE6_V 0x00000003 +#define USB_D_EPTYPE6_S 18 +/** USB_D_STALL6 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it + * 0x0 : No Stall + * 0x1 : Stall Handshake + */ +#define USB_D_STALL6 (BIT(21)) +#define USB_D_STALL6_M (USB_D_STALL6_V << USB_D_STALL6_S) +#define USB_D_STALL6_V 0x00000001 +#define USB_D_STALL6_S 21 +/** USB_D_TXFNUM6 : R/W; bitpos: [26:22]; default: 0; + * TxFIFO Number. + */ +#define USB_D_TXFNUM6 0x0000000F +#define USB_D_TXFNUM6_M (USB_D_TXFNUM6_V << USB_D_TXFNUM6_S) +#define USB_D_TXFNUM6_V 0x0000000F +#define USB_D_TXFNUM6_S 22 +/** USB_D_CNAK6 : WO; bitpos: [26]; default: 0; + * A write to this bit clears the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_D_CNAK6 (BIT(26)) +#define USB_D_CNAK6_M (USB_D_CNAK6_V << USB_D_CNAK6_S) +#define USB_D_CNAK6_V 0x00000001 +#define USB_D_CNAK6_S 26 +/** USB_DI_SNAK6 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DI_SNAK6 (BIT(27)) +#define USB_DI_SNAK6_M (USB_DI_SNAK6_V << USB_DI_SNAK6_S) +#define USB_DI_SNAK6_V 0x00000001 +#define USB_DI_SNAK6_S 27 +/** USB_DI_SETD0PID6 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DI_SETD0PID6 (BIT(28)) +#define USB_DI_SETD0PID6_M (USB_DI_SETD0PID6_V << USB_DI_SETD0PID6_S) +#define USB_DI_SETD0PID6_V 0x00000001 +#define USB_DI_SETD0PID6_S 28 +/** USB_DI_SETD1PID6 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DI_SETD1PID6 (BIT(29)) +#define USB_DI_SETD1PID6_M (USB_DI_SETD1PID6_V << USB_DI_SETD1PID6_S) +#define USB_DI_SETD1PID6_V 0x00000001 +#define USB_DI_SETD1PID6_S 29 +/** USB_D_EPDIS6 : R/W; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No action + * 0x1 : Disabled Endpoint + */ +#define USB_D_EPDIS6 (BIT(30)) +#define USB_D_EPDIS6_M (USB_D_EPDIS6_V << USB_D_EPDIS6_S) +#define USB_D_EPDIS6_V 0x00000001 +#define USB_D_EPDIS6_S 30 +/** USB_D_EPENA6 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_D_EPENA6 (BIT(31)) +#define USB_D_EPENA6_M (USB_D_EPENA6_V << USB_D_EPENA6_S) +#define USB_D_EPENA6_V 0x00000001 +#define USB_D_EPENA6_S 31 + + +/** USB_DIEPTSIZ6_REG register + * Device IN Endpoint 6 Transfer Size Register + */ +#define USB_DIEPTSIZ6_REG (SOC_DPORT_USB_BASE + 0x9d0) +/** USB_D_XFERSIZE6 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size + * IN Endpoints: The core decrements this field every time a packet from the external + * memory is written to the TxFIFO + * OUT Endpoints: The core decrements this field every time a packet is read from the + * RxFIFO and written to the external memory + */ +#define USB_D_XFERSIZE6 0x0000007F +#define USB_D_XFERSIZE6_M (USB_D_XFERSIZE6_V << USB_D_XFERSIZE6_S) +#define USB_D_XFERSIZE6_V 0x0000007F +#define USB_D_XFERSIZE6_S 0 +/** USB_D_PKTCNT6 : R/W; bitpos: [21:19]; default: 0; + * Packet Count + * IN Endpoints : This field is decremented every time a packet (maximum size or short + * packet) is read from the TxFIFO + * OUT Endpoints: This field is decremented every time a packet (maximum size or short + * packet) is written to the RxFIFO + */ +#define USB_D_PKTCNT6 0x00000003 +#define USB_D_PKTCNT6_M (USB_D_PKTCNT6_V << USB_D_PKTCNT6_S) +#define USB_D_PKTCNT6_V 0x00000003 +#define USB_D_PKTCNT6_S 19 + + +/** USB_DIEPDMA6_REG register + * Device IN Endpoint 6 DMA Address Register + */ +#define USB_DIEPDMA6_REG (SOC_DPORT_USB_BASE + 0x9d4) +/** USB_D_DMAADDR6 : R/W; bitpos: [32:0]; default: 0; + * This field holds the start address of the external memory for storing or fetching + * endpoint data. + */ +#define USB_D_DMAADDR6 0xFFFFFFFF +#define USB_D_DMAADDR6_M (USB_D_DMAADDR6_V << USB_D_DMAADDR6_S) +#define USB_D_DMAADDR6_V 0xFFFFFFFF +#define USB_D_DMAADDR6_S 0 + + +/** USB_DOEPCTL0_REG register + * Device Control OUT Endpoint $n Control Register + */ +#define USB_DOEPCTL0_REG (SOC_DPORT_USB_BASE + 0xb00) +/** USB_MPS0 : RO; bitpos: [2:0]; default: 0; + * Maximum Packet Size + * 0x0 : 64 bytes + * 0x1 : 32 bytes + * 0x2 : 16 bytes + * 0x3 : 8 bytes + */ +#define USB_MPS0 0x00000003 +#define USB_MPS0_M (USB_MPS0_V << USB_MPS0_S) +#define USB_MPS0_V 0x00000003 +#define USB_MPS0_S 0 +/** USB_USBACTEP0 : RO; bitpos: [15]; default: 1; + * 0x1: USB Active Endpoint 0 + */ +#define USB_USBACTEP0 (BIT(15)) +#define USB_USBACTEP0_M (USB_USBACTEP0_V << USB_USBACTEP0_S) +#define USB_USBACTEP0_V 0x00000001 +#define USB_USBACTEP0_S 15 +/** USB_NAKSTS0 : RO; bitpos: [17]; default: 0; + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status + * 0x1 :The core is transmitting NAK handshakes on this endpoint + */ +#define USB_NAKSTS0 (BIT(17)) +#define USB_NAKSTS0_M (USB_NAKSTS0_V << USB_NAKSTS0_S) +#define USB_NAKSTS0_V 0x00000001 +#define USB_NAKSTS0_S 17 +/** USB_EPTYPE0 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control $n + */ +#define USB_EPTYPE0 0x00000003 +#define USB_EPTYPE0_M (USB_EPTYPE0_V << USB_EPTYPE0_S) +#define USB_EPTYPE0_V 0x00000003 +#define USB_EPTYPE0_S 18 +/** USB_SNP0 : R/W; bitpos: [20]; default: 0; + * 0x0 : Reserved 0 + * 0x1 : Reserved 1 + */ +#define USB_SNP0 (BIT(20)) +#define USB_SNP0_M (USB_SNP0_V << USB_SNP0_S) +#define USB_SNP0_V 0x00000001 +#define USB_SNP0_S 20 +/** USB_STALL0 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it, when a SETUP token + * is received for this endpoint + * 0x0 (INACTIVE): No Stall + * 0x1 (ACTIVE): Stall Handshake + */ +#define USB_STALL0 (BIT(21)) +#define USB_STALL0_M (USB_STALL0_V << USB_STALL0_S) +#define USB_STALL0_V 0x00000001 +#define USB_STALL0_S 21 +/** USB_CNAK0 : WO; bitpos: [26]; default: 0; + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_CNAK0 (BIT(26)) +#define USB_CNAK0_M (USB_CNAK0_V << USB_CNAK0_S) +#define USB_CNAK0_V 0x00000001 +#define USB_CNAK0_S 26 +/** USB_DO_SNAK0 : WO; bitpos: [27]; default: 0; + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DO_SNAK0 (BIT(27)) +#define USB_DO_SNAK0_M (USB_DO_SNAK0_V << USB_DO_SNAK0_S) +#define USB_DO_SNAK0_V 0x00000001 +#define USB_DO_SNAK0_S 27 +/** USB_EPDIS0 : RO; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No Endpoint disable + */ +#define USB_EPDIS0 (BIT(30)) +#define USB_EPDIS0_M (USB_EPDIS0_V << USB_EPDIS0_S) +#define USB_EPDIS0_V 0x00000001 +#define USB_EPDIS0_S 30 +/** USB_EPENA0 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_EPENA0 (BIT(31)) +#define USB_EPENA0_M (USB_EPENA0_V << USB_EPENA0_S) +#define USB_EPENA0_V 0x00000001 +#define USB_EPENA0_S 31 + + +/** USB_DOEPTSIZ0_REG register + * Device OUT Endpoint 0 Transfer Size Register + */ +#define USB_DOEPTSIZ0_REG (SOC_DPORT_USB_BASE + 0xb10) +/** USB_XFERSIZE0 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size.Indicates the transfer size in bytes for ENDPOINT0 + */ +#define USB_XFERSIZE0 0x0000007F +#define USB_XFERSIZE0_M (USB_XFERSIZE0_V << USB_XFERSIZE0_S) +#define USB_XFERSIZE0_V 0x0000007F +#define USB_XFERSIZE0_S 0 +/** USB_PKTCNT0 : R/W; bitpos: [19]; default: 0; + * Packet Count (PktCnt).This field is decremented to zero after a packet is written + * into the RxFIFO. + */ +#define USB_PKTCNT0 (BIT(19)) +#define USB_PKTCNT0_M (USB_PKTCNT0_V << USB_PKTCNT0_S) +#define USB_PKTCNT0_V 0x00000001 +#define USB_PKTCNT0_S 19 +/** USB_SUPCNT0 : R/W; bitpos: [31:29]; default: 0; + * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP + * data packets the endpoint can receive + * 2'b01: 1 packet + * 2'b10: 2 packets + * 2'b11: 3 packets + */ +#define USB_SUPCNT0 0x00000003 +#define USB_SUPCNT0_M (USB_SUPCNT0_V << USB_SUPCNT0_S) +#define USB_SUPCNT0_V 0x00000003 +#define USB_SUPCNT0_S 29 + + +/** USB_DOEPDMA0_REG register + * Device OUT Endpoint 0 DMA Address Register + */ +#define USB_DOEPDMA0_REG (SOC_DPORT_USB_BASE + 0xb14) +/** USB_DMAADDR0 : R/W; bitpos: [32:0]; default: 0; + * Holds the start address of the external memory for storing or fetching endpoint + * data. + */ +#define USB_DMAADDR0 0xFFFFFFFF +#define USB_DMAADDR0_M (USB_DMAADDR0_V << USB_DMAADDR0_S) +#define USB_DMAADDR0_V 0xFFFFFFFF +#define USB_DMAADDR0_S 0 + + +/** USB_DOEPDMAB0_REG register + * Device OUT Endpoint 16 Buffer Address Register + */ +#define USB_DOEPDMAB0_REG (SOC_DPORT_USB_BASE + 0xb1c) +/** USB_DMABUFFERADDR0 : R/W; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_DMABUFFERADDR0 0xFFFFFFFF +#define USB_DMABUFFERADDR0_M (USB_DMABUFFERADDR0_V << USB_DMABUFFERADDR0_S) +#define USB_DMABUFFERADDR0_V 0xFFFFFFFF +#define USB_DMABUFFERADDR0_S 0 + + +/** USB_DOEPCTL1_REG register + * Device Control OUT Endpoint 1 Control Register + */ +#define USB_DOEPCTL1_REG (SOC_DPORT_USB_BASE + 0xb20) +/** USB_MPS1 : RO; bitpos: [11:0]; default: 0; + * Maximum Packet Size in bytes + */ +#define USB_MPS1 0x000007FF +#define USB_MPS1_M (USB_MPS1_V << USB_MPS1_S) +#define USB_MPS1_V 0x000007FF +#define USB_MPS1_S 0 +/** USB_USBACTEP1 : RO; bitpos: [15]; default: 1; + * 0x1: USB Active Endpoint 0 + */ +#define USB_USBACTEP1 (BIT(15)) +#define USB_USBACTEP1_M (USB_USBACTEP1_V << USB_USBACTEP1_S) +#define USB_USBACTEP1_V 0x00000001 +#define USB_USBACTEP1_S 15 +/** USB_NAKSTS1 : RO; bitpos: [17]; default: 0; + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status + * 0x1 :The core is transmitting NAK handshakes on this endpoint + */ +#define USB_NAKSTS1 (BIT(17)) +#define USB_NAKSTS1_M (USB_NAKSTS1_V << USB_NAKSTS1_S) +#define USB_NAKSTS1_V 0x00000001 +#define USB_NAKSTS1_S 17 +/** USB_EPTYPE1 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 1 + */ +#define USB_EPTYPE1 0x00000003 +#define USB_EPTYPE1_M (USB_EPTYPE1_V << USB_EPTYPE1_S) +#define USB_EPTYPE1_V 0x00000003 +#define USB_EPTYPE1_S 18 +/** USB_SNP1 : R/W; bitpos: [20]; default: 0; + * 0x0 : Reserved 0 + * 0x1 : Reserved 1 + */ +#define USB_SNP1 (BIT(20)) +#define USB_SNP1_M (USB_SNP1_V << USB_SNP1_S) +#define USB_SNP1_V 0x00000001 +#define USB_SNP1_S 20 +/** USB_STALL1 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it, when a SETUP token + * is received for this endpoint + * 0x0 (INACTIVE): No Stall + * 0x1 (ACTIVE): Stall Handshake + */ +#define USB_STALL1 (BIT(21)) +#define USB_STALL1_M (USB_STALL1_V << USB_STALL1_S) +#define USB_STALL1_V 0x00000001 +#define USB_STALL1_S 21 +/** USB_CNAK1 : WO; bitpos: [26]; default: 0; + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_CNAK1 (BIT(26)) +#define USB_CNAK1_M (USB_CNAK1_V << USB_CNAK1_S) +#define USB_CNAK1_V 0x00000001 +#define USB_CNAK1_S 26 +/** USB_DO_SNAK1 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DO_SNAK1 (BIT(27)) +#define USB_DO_SNAK1_M (USB_DO_SNAK1_V << USB_DO_SNAK1_S) +#define USB_DO_SNAK1_V 0x00000001 +#define USB_DO_SNAK1_S 27 +/** USB_DO_SETD0PID1 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DO_SETD0PID1 (BIT(28)) +#define USB_DO_SETD0PID1_M (USB_DO_SETD0PID1_V << USB_DO_SETD0PID1_S) +#define USB_DO_SETD0PID1_V 0x00000001 +#define USB_DO_SETD0PID1_S 28 +/** USB_DO_SETD1PID1 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DO_SETD1PID1 (BIT(29)) +#define USB_DO_SETD1PID1_M (USB_DO_SETD1PID1_V << USB_DO_SETD1PID1_S) +#define USB_DO_SETD1PID1_V 0x00000001 +#define USB_DO_SETD1PID1_S 29 +/** USB_EPDIS1 : RO; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No Endpoint disable + */ +#define USB_EPDIS1 (BIT(30)) +#define USB_EPDIS1_M (USB_EPDIS1_V << USB_EPDIS1_S) +#define USB_EPDIS1_V 0x00000001 +#define USB_EPDIS1_S 30 +/** USB_EPENA1 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_EPENA1 (BIT(31)) +#define USB_EPENA1_M (USB_EPENA1_V << USB_EPENA1_S) +#define USB_EPENA1_V 0x00000001 +#define USB_EPENA1_S 31 + + +/** USB_DOEPTSIZ1_REG register + * Device OUT Endpoint 1 Transfer Size Register + */ +#define USB_DOEPTSIZ1_REG (SOC_DPORT_USB_BASE + 0xb30) +/** USB_XFERSIZE1 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size.Indicates the transfer size in bytes for ENDPOINT1 + */ +#define USB_XFERSIZE1 0x0000007F +#define USB_XFERSIZE1_M (USB_XFERSIZE1_V << USB_XFERSIZE1_S) +#define USB_XFERSIZE1_V 0x0000007F +#define USB_XFERSIZE1_S 0 +/** USB_PKTCNT1 : R/W; bitpos: [19]; default: 0; + * Packet Count (PktCnt).This field is decremented to zero after a packet is written + * into the RxFIFO. + */ +#define USB_PKTCNT1 (BIT(19)) +#define USB_PKTCNT1_M (USB_PKTCNT1_V << USB_PKTCNT1_S) +#define USB_PKTCNT1_V 0x00000001 +#define USB_PKTCNT1_S 19 +/** USB_SUPCNT1 : R/W; bitpos: [31:29]; default: 0; + * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP + * data packets the endpoint can receive + * 2'b01: 1 packet + * 2'b10: 2 packets + * 2'b11: 3 packets + */ +#define USB_SUPCNT1 0x00000003 +#define USB_SUPCNT1_M (USB_SUPCNT1_V << USB_SUPCNT1_S) +#define USB_SUPCNT1_V 0x00000003 +#define USB_SUPCNT1_S 29 + + +/** USB_DOEPDMA1_REG register + * Device OUT Endpoint 1 DMA Address Register + */ +#define USB_DOEPDMA1_REG (SOC_DPORT_USB_BASE + 0xb34) +/** USB_DMAADDR1 : R/W; bitpos: [32:0]; default: 0; + * Holds the start address of the external memory for storing or fetching endpoint + * data. + */ +#define USB_DMAADDR1 0xFFFFFFFF +#define USB_DMAADDR1_M (USB_DMAADDR1_V << USB_DMAADDR1_S) +#define USB_DMAADDR1_V 0xFFFFFFFF +#define USB_DMAADDR1_S 0 + + +/** USB_DOEPDMAB1_REG register + * Device OUT Endpoint 16 Buffer Address Register + */ +#define USB_DOEPDMAB1_REG (SOC_DPORT_USB_BASE + 0xb3c) +/** USB_DMABUFFERADDR1 : R/W; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_DMABUFFERADDR1 0xFFFFFFFF +#define USB_DMABUFFERADDR1_M (USB_DMABUFFERADDR1_V << USB_DMABUFFERADDR1_S) +#define USB_DMABUFFERADDR1_V 0xFFFFFFFF +#define USB_DMABUFFERADDR1_S 0 + + +/** USB_DOEPCTL2_REG register + * Device Control OUT Endpoint 2 Control Register + */ +#define USB_DOEPCTL2_REG (SOC_DPORT_USB_BASE + 0xb40) +/** USB_MPS2 : RO; bitpos: [11:0]; default: 0; + * Maximum Packet Size in bytes + */ +#define USB_MPS2 0x000007FF +#define USB_MPS2_M (USB_MPS2_V << USB_MPS2_S) +#define USB_MPS2_V 0x000007FF +#define USB_MPS2_S 0 +/** USB_USBACTEP2 : RO; bitpos: [15]; default: 1; + * 0x1: USB Active Endpoint 0 + */ +#define USB_USBACTEP2 (BIT(15)) +#define USB_USBACTEP2_M (USB_USBACTEP2_V << USB_USBACTEP2_S) +#define USB_USBACTEP2_V 0x00000001 +#define USB_USBACTEP2_S 15 +/** USB_NAKSTS2 : RO; bitpos: [17]; default: 0; + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status + * 0x1 :The core is transmitting NAK handshakes on this endpoint + */ +#define USB_NAKSTS2 (BIT(17)) +#define USB_NAKSTS2_M (USB_NAKSTS2_V << USB_NAKSTS2_S) +#define USB_NAKSTS2_V 0x00000001 +#define USB_NAKSTS2_S 17 +/** USB_EPTYPE2 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 2 + */ +#define USB_EPTYPE2 0x00000003 +#define USB_EPTYPE2_M (USB_EPTYPE2_V << USB_EPTYPE2_S) +#define USB_EPTYPE2_V 0x00000003 +#define USB_EPTYPE2_S 18 +/** USB_SNP2 : R/W; bitpos: [20]; default: 0; + * 0x0 : Reserved 0 + * 0x1 : Reserved 1 + */ +#define USB_SNP2 (BIT(20)) +#define USB_SNP2_M (USB_SNP2_V << USB_SNP2_S) +#define USB_SNP2_V 0x00000001 +#define USB_SNP2_S 20 +/** USB_STALL2 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it, when a SETUP token + * is received for this endpoint + * 0x0 (INACTIVE): No Stall + * 0x1 (ACTIVE): Stall Handshake + */ +#define USB_STALL2 (BIT(21)) +#define USB_STALL2_M (USB_STALL2_V << USB_STALL2_S) +#define USB_STALL2_V 0x00000001 +#define USB_STALL2_S 21 +/** USB_CNAK2 : WO; bitpos: [26]; default: 0; + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_CNAK2 (BIT(26)) +#define USB_CNAK2_M (USB_CNAK2_V << USB_CNAK2_S) +#define USB_CNAK2_V 0x00000001 +#define USB_CNAK2_S 26 +/** USB_DO_SNAK2 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DO_SNAK2 (BIT(27)) +#define USB_DO_SNAK2_M (USB_DO_SNAK2_V << USB_DO_SNAK2_S) +#define USB_DO_SNAK2_V 0x00000001 +#define USB_DO_SNAK2_S 27 +/** USB_DO_SETD0PID2 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DO_SETD0PID2 (BIT(28)) +#define USB_DO_SETD0PID2_M (USB_DO_SETD0PID2_V << USB_DO_SETD0PID2_S) +#define USB_DO_SETD0PID2_V 0x00000001 +#define USB_DO_SETD0PID2_S 28 +/** USB_DO_SETD1PID2 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DO_SETD1PID2 (BIT(29)) +#define USB_DO_SETD1PID2_M (USB_DO_SETD1PID2_V << USB_DO_SETD1PID2_S) +#define USB_DO_SETD1PID2_V 0x00000001 +#define USB_DO_SETD1PID2_S 29 +/** USB_EPDIS2 : RO; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No Endpoint disable + */ +#define USB_EPDIS2 (BIT(30)) +#define USB_EPDIS2_M (USB_EPDIS2_V << USB_EPDIS2_S) +#define USB_EPDIS2_V 0x00000001 +#define USB_EPDIS2_S 30 +/** USB_EPENA2 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_EPENA2 (BIT(31)) +#define USB_EPENA2_M (USB_EPENA2_V << USB_EPENA2_S) +#define USB_EPENA2_V 0x00000001 +#define USB_EPENA2_S 31 + + +/** USB_DOEPTSIZ2_REG register + * Device OUT Endpoint 2 Transfer Size Register + */ +#define USB_DOEPTSIZ2_REG (SOC_DPORT_USB_BASE + 0xb50) +/** USB_XFERSIZE2 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size.Indicates the transfer size in bytes for ENDPOINT2 + */ +#define USB_XFERSIZE2 0x0000007F +#define USB_XFERSIZE2_M (USB_XFERSIZE2_V << USB_XFERSIZE2_S) +#define USB_XFERSIZE2_V 0x0000007F +#define USB_XFERSIZE2_S 0 +/** USB_PKTCNT2 : R/W; bitpos: [19]; default: 0; + * Packet Count (PktCnt).This field is decremented to zero after a packet is written + * into the RxFIFO. + */ +#define USB_PKTCNT2 (BIT(19)) +#define USB_PKTCNT2_M (USB_PKTCNT2_V << USB_PKTCNT2_S) +#define USB_PKTCNT2_V 0x00000001 +#define USB_PKTCNT2_S 19 +/** USB_SUPCNT2 : R/W; bitpos: [31:29]; default: 0; + * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP + * data packets the endpoint can receive + * 2'b01: 1 packet + * 2'b10: 2 packets + * 2'b11: 3 packets + */ +#define USB_SUPCNT2 0x00000003 +#define USB_SUPCNT2_M (USB_SUPCNT2_V << USB_SUPCNT2_S) +#define USB_SUPCNT2_V 0x00000003 +#define USB_SUPCNT2_S 29 + + +/** USB_DOEPDMA2_REG register + * Device OUT Endpoint 2 DMA Address Register + */ +#define USB_DOEPDMA2_REG (SOC_DPORT_USB_BASE + 0xb54) +/** USB_DMAADDR2 : R/W; bitpos: [32:0]; default: 0; + * Holds the start address of the external memory for storing or fetching endpoint + * data. + */ +#define USB_DMAADDR2 0xFFFFFFFF +#define USB_DMAADDR2_M (USB_DMAADDR2_V << USB_DMAADDR2_S) +#define USB_DMAADDR2_V 0xFFFFFFFF +#define USB_DMAADDR2_S 0 + + +/** USB_DOEPDMAB2_REG register + * Device OUT Endpoint 16 Buffer Address Register + */ +#define USB_DOEPDMAB2_REG (SOC_DPORT_USB_BASE + 0xb5c) +/** USB_DMABUFFERADDR2 : R/W; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_DMABUFFERADDR2 0xFFFFFFFF +#define USB_DMABUFFERADDR2_M (USB_DMABUFFERADDR2_V << USB_DMABUFFERADDR2_S) +#define USB_DMABUFFERADDR2_V 0xFFFFFFFF +#define USB_DMABUFFERADDR2_S 0 + + +/** USB_DOEPCTL3_REG register + * Device Control OUT Endpoint 3 Control Register + */ +#define USB_DOEPCTL3_REG (SOC_DPORT_USB_BASE + 0xb60) +/** USB_MPS3 : RO; bitpos: [11:0]; default: 0; + * Maximum Packet Size in bytes + */ +#define USB_MPS3 0x000007FF +#define USB_MPS3_M (USB_MPS3_V << USB_MPS3_S) +#define USB_MPS3_V 0x000007FF +#define USB_MPS3_S 0 +/** USB_USBACTEP3 : RO; bitpos: [15]; default: 1; + * 0x1: USB Active Endpoint 0 + */ +#define USB_USBACTEP3 (BIT(15)) +#define USB_USBACTEP3_M (USB_USBACTEP3_V << USB_USBACTEP3_S) +#define USB_USBACTEP3_V 0x00000001 +#define USB_USBACTEP3_S 15 +/** USB_NAKSTS3 : RO; bitpos: [17]; default: 0; + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status + * 0x1 :The core is transmitting NAK handshakes on this endpoint + */ +#define USB_NAKSTS3 (BIT(17)) +#define USB_NAKSTS3_M (USB_NAKSTS3_V << USB_NAKSTS3_S) +#define USB_NAKSTS3_V 0x00000001 +#define USB_NAKSTS3_S 17 +/** USB_EPTYPE3 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 3 + */ +#define USB_EPTYPE3 0x00000003 +#define USB_EPTYPE3_M (USB_EPTYPE3_V << USB_EPTYPE3_S) +#define USB_EPTYPE3_V 0x00000003 +#define USB_EPTYPE3_S 18 +/** USB_SNP3 : R/W; bitpos: [20]; default: 0; + * 0x0 : Reserved 0 + * 0x1 : Reserved 1 + */ +#define USB_SNP3 (BIT(20)) +#define USB_SNP3_M (USB_SNP3_V << USB_SNP3_S) +#define USB_SNP3_V 0x00000001 +#define USB_SNP3_S 20 +/** USB_STALL3 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it, when a SETUP token + * is received for this endpoint + * 0x0 (INACTIVE): No Stall + * 0x1 (ACTIVE): Stall Handshake + */ +#define USB_STALL3 (BIT(21)) +#define USB_STALL3_M (USB_STALL3_V << USB_STALL3_S) +#define USB_STALL3_V 0x00000001 +#define USB_STALL3_S 21 +/** USB_CNAK3 : WO; bitpos: [26]; default: 0; + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_CNAK3 (BIT(26)) +#define USB_CNAK3_M (USB_CNAK3_V << USB_CNAK3_S) +#define USB_CNAK3_V 0x00000001 +#define USB_CNAK3_S 26 +/** USB_DO_SNAK3 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DO_SNAK3 (BIT(27)) +#define USB_DO_SNAK3_M (USB_DO_SNAK3_V << USB_DO_SNAK3_S) +#define USB_DO_SNAK3_V 0x00000001 +#define USB_DO_SNAK3_S 27 +/** USB_DO_SETD0PID3 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DO_SETD0PID3 (BIT(28)) +#define USB_DO_SETD0PID3_M (USB_DO_SETD0PID3_V << USB_DO_SETD0PID3_S) +#define USB_DO_SETD0PID3_V 0x00000001 +#define USB_DO_SETD0PID3_S 28 +/** USB_DO_SETD1PID3 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DO_SETD1PID3 (BIT(29)) +#define USB_DO_SETD1PID3_M (USB_DO_SETD1PID3_V << USB_DO_SETD1PID3_S) +#define USB_DO_SETD1PID3_V 0x00000001 +#define USB_DO_SETD1PID3_S 29 +/** USB_EPDIS3 : RO; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No Endpoint disable + */ +#define USB_EPDIS3 (BIT(30)) +#define USB_EPDIS3_M (USB_EPDIS3_V << USB_EPDIS3_S) +#define USB_EPDIS3_V 0x00000001 +#define USB_EPDIS3_S 30 +/** USB_EPENA3 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_EPENA3 (BIT(31)) +#define USB_EPENA3_M (USB_EPENA3_V << USB_EPENA3_S) +#define USB_EPENA3_V 0x00000001 +#define USB_EPENA3_S 31 + + +/** USB_DOEPTSIZ3_REG register + * Device OUT Endpoint 3 Transfer Size Register + */ +#define USB_DOEPTSIZ3_REG (SOC_DPORT_USB_BASE + 0xb70) +/** USB_XFERSIZE3 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size.Indicates the transfer size in bytes for ENDPOINT3 + */ +#define USB_XFERSIZE3 0x0000007F +#define USB_XFERSIZE3_M (USB_XFERSIZE3_V << USB_XFERSIZE3_S) +#define USB_XFERSIZE3_V 0x0000007F +#define USB_XFERSIZE3_S 0 +/** USB_PKTCNT3 : R/W; bitpos: [19]; default: 0; + * Packet Count (PktCnt).This field is decremented to zero after a packet is written + * into the RxFIFO. + */ +#define USB_PKTCNT3 (BIT(19)) +#define USB_PKTCNT3_M (USB_PKTCNT3_V << USB_PKTCNT3_S) +#define USB_PKTCNT3_V 0x00000001 +#define USB_PKTCNT3_S 19 +/** USB_SUPCNT3 : R/W; bitpos: [31:29]; default: 0; + * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP + * data packets the endpoint can receive + * 2'b01: 1 packet + * 2'b10: 2 packets + * 2'b11: 3 packets + */ +#define USB_SUPCNT3 0x00000003 +#define USB_SUPCNT3_M (USB_SUPCNT3_V << USB_SUPCNT3_S) +#define USB_SUPCNT3_V 0x00000003 +#define USB_SUPCNT3_S 29 + + +/** USB_DOEPDMA3_REG register + * Device OUT Endpoint 3 DMA Address Register + */ +#define USB_DOEPDMA3_REG (SOC_DPORT_USB_BASE + 0xb74) +/** USB_DMAADDR3 : R/W; bitpos: [32:0]; default: 0; + * Holds the start address of the external memory for storing or fetching endpoint + * data. + */ +#define USB_DMAADDR3 0xFFFFFFFF +#define USB_DMAADDR3_M (USB_DMAADDR3_V << USB_DMAADDR3_S) +#define USB_DMAADDR3_V 0xFFFFFFFF +#define USB_DMAADDR3_S 0 + + +/** USB_DOEPDMAB3_REG register + * Device OUT Endpoint 16 Buffer Address Register + */ +#define USB_DOEPDMAB3_REG (SOC_DPORT_USB_BASE + 0xb7c) +/** USB_DMABUFFERADDR3 : R/W; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_DMABUFFERADDR3 0xFFFFFFFF +#define USB_DMABUFFERADDR3_M (USB_DMABUFFERADDR3_V << USB_DMABUFFERADDR3_S) +#define USB_DMABUFFERADDR3_V 0xFFFFFFFF +#define USB_DMABUFFERADDR3_S 0 + + +/** USB_DOEPCTL4_REG register + * Device Control OUT Endpoint 4 Control Register + */ +#define USB_DOEPCTL4_REG (SOC_DPORT_USB_BASE + 0xb80) +/** USB_MPS4 : RO; bitpos: [11:0]; default: 0; + * Maximum Packet Size in bytes + */ +#define USB_MPS4 0x000007FF +#define USB_MPS4_M (USB_MPS4_V << USB_MPS4_S) +#define USB_MPS4_V 0x000007FF +#define USB_MPS4_S 0 +/** USB_USBACTEP4 : RO; bitpos: [15]; default: 1; + * 0x1: USB Active Endpoint 0 + */ +#define USB_USBACTEP4 (BIT(15)) +#define USB_USBACTEP4_M (USB_USBACTEP4_V << USB_USBACTEP4_S) +#define USB_USBACTEP4_V 0x00000001 +#define USB_USBACTEP4_S 15 +/** USB_NAKSTS4 : RO; bitpos: [17]; default: 0; + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status + * 0x1 :The core is transmitting NAK handshakes on this endpoint + */ +#define USB_NAKSTS4 (BIT(17)) +#define USB_NAKSTS4_M (USB_NAKSTS4_V << USB_NAKSTS4_S) +#define USB_NAKSTS4_V 0x00000001 +#define USB_NAKSTS4_S 17 +/** USB_EPTYPE4 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 4 + */ +#define USB_EPTYPE4 0x00000003 +#define USB_EPTYPE4_M (USB_EPTYPE4_V << USB_EPTYPE4_S) +#define USB_EPTYPE4_V 0x00000003 +#define USB_EPTYPE4_S 18 +/** USB_SNP4 : R/W; bitpos: [20]; default: 0; + * 0x0 : Reserved 0 + * 0x1 : Reserved 1 + */ +#define USB_SNP4 (BIT(20)) +#define USB_SNP4_M (USB_SNP4_V << USB_SNP4_S) +#define USB_SNP4_V 0x00000001 +#define USB_SNP4_S 20 +/** USB_STALL4 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it, when a SETUP token + * is received for this endpoint + * 0x0 (INACTIVE): No Stall + * 0x1 (ACTIVE): Stall Handshake + */ +#define USB_STALL4 (BIT(21)) +#define USB_STALL4_M (USB_STALL4_V << USB_STALL4_S) +#define USB_STALL4_V 0x00000001 +#define USB_STALL4_S 21 +/** USB_CNAK4 : WO; bitpos: [26]; default: 0; + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_CNAK4 (BIT(26)) +#define USB_CNAK4_M (USB_CNAK4_V << USB_CNAK4_S) +#define USB_CNAK4_V 0x00000001 +#define USB_CNAK4_S 26 +/** USB_DO_SNAK4 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DO_SNAK4 (BIT(27)) +#define USB_DO_SNAK4_M (USB_DO_SNAK4_V << USB_DO_SNAK4_S) +#define USB_DO_SNAK4_V 0x00000001 +#define USB_DO_SNAK4_S 27 +/** USB_DO_SETD0PID4 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DO_SETD0PID4 (BIT(28)) +#define USB_DO_SETD0PID4_M (USB_DO_SETD0PID4_V << USB_DO_SETD0PID4_S) +#define USB_DO_SETD0PID4_V 0x00000001 +#define USB_DO_SETD0PID4_S 28 +/** USB_DO_SETD1PID4 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DO_SETD1PID4 (BIT(29)) +#define USB_DO_SETD1PID4_M (USB_DO_SETD1PID4_V << USB_DO_SETD1PID4_S) +#define USB_DO_SETD1PID4_V 0x00000001 +#define USB_DO_SETD1PID4_S 29 +/** USB_EPDIS4 : RO; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No Endpoint disable + */ +#define USB_EPDIS4 (BIT(30)) +#define USB_EPDIS4_M (USB_EPDIS4_V << USB_EPDIS4_S) +#define USB_EPDIS4_V 0x00000001 +#define USB_EPDIS4_S 30 +/** USB_EPENA4 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_EPENA4 (BIT(31)) +#define USB_EPENA4_M (USB_EPENA4_V << USB_EPENA4_S) +#define USB_EPENA4_V 0x00000001 +#define USB_EPENA4_S 31 + + +/** USB_DOEPTSIZ4_REG register + * Device OUT Endpoint 4 Transfer Size Register + */ +#define USB_DOEPTSIZ4_REG (SOC_DPORT_USB_BASE + 0xb90) +/** USB_XFERSIZE4 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size.Indicates the transfer size in bytes for ENDPOINT4 + */ +#define USB_XFERSIZE4 0x0000007F +#define USB_XFERSIZE4_M (USB_XFERSIZE4_V << USB_XFERSIZE4_S) +#define USB_XFERSIZE4_V 0x0000007F +#define USB_XFERSIZE4_S 0 +/** USB_PKTCNT4 : R/W; bitpos: [19]; default: 0; + * Packet Count (PktCnt).This field is decremented to zero after a packet is written + * into the RxFIFO. + */ +#define USB_PKTCNT4 (BIT(19)) +#define USB_PKTCNT4_M (USB_PKTCNT4_V << USB_PKTCNT4_S) +#define USB_PKTCNT4_V 0x00000001 +#define USB_PKTCNT4_S 19 +/** USB_SUPCNT4 : R/W; bitpos: [31:29]; default: 0; + * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP + * data packets the endpoint can receive + * 2'b01: 1 packet + * 2'b10: 2 packets + * 2'b11: 3 packets + */ +#define USB_SUPCNT4 0x00000003 +#define USB_SUPCNT4_M (USB_SUPCNT4_V << USB_SUPCNT4_S) +#define USB_SUPCNT4_V 0x00000003 +#define USB_SUPCNT4_S 29 + + +/** USB_DOEPDMA4_REG register + * Device OUT Endpoint 4 DMA Address Register + */ +#define USB_DOEPDMA4_REG (SOC_DPORT_USB_BASE + 0xb94) +/** USB_DMAADDR4 : R/W; bitpos: [32:0]; default: 0; + * Holds the start address of the external memory for storing or fetching endpoint + * data. + */ +#define USB_DMAADDR4 0xFFFFFFFF +#define USB_DMAADDR4_M (USB_DMAADDR4_V << USB_DMAADDR4_S) +#define USB_DMAADDR4_V 0xFFFFFFFF +#define USB_DMAADDR4_S 0 + + +/** USB_DOEPDMAB4_REG register + * Device OUT Endpoint 16 Buffer Address Register + */ +#define USB_DOEPDMAB4_REG (SOC_DPORT_USB_BASE + 0xb9c) +/** USB_DMABUFFERADDR4 : R/W; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_DMABUFFERADDR4 0xFFFFFFFF +#define USB_DMABUFFERADDR4_M (USB_DMABUFFERADDR4_V << USB_DMABUFFERADDR4_S) +#define USB_DMABUFFERADDR4_V 0xFFFFFFFF +#define USB_DMABUFFERADDR4_S 0 + + +/** USB_DOEPCTL5_REG register + * Device Control OUT Endpoint 5 Control Register + */ +#define USB_DOEPCTL5_REG (SOC_DPORT_USB_BASE + 0xba0) +/** USB_MPS5 : RO; bitpos: [11:0]; default: 0; + * Maximum Packet Size in bytes + */ +#define USB_MPS5 0x000007FF +#define USB_MPS5_M (USB_MPS5_V << USB_MPS5_S) +#define USB_MPS5_V 0x000007FF +#define USB_MPS5_S 0 +/** USB_USBACTEP5 : RO; bitpos: [15]; default: 1; + * 0x1: USB Active Endpoint 0 + */ +#define USB_USBACTEP5 (BIT(15)) +#define USB_USBACTEP5_M (USB_USBACTEP5_V << USB_USBACTEP5_S) +#define USB_USBACTEP5_V 0x00000001 +#define USB_USBACTEP5_S 15 +/** USB_NAKSTS5 : RO; bitpos: [17]; default: 0; + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status + * 0x1 :The core is transmitting NAK handshakes on this endpoint + */ +#define USB_NAKSTS5 (BIT(17)) +#define USB_NAKSTS5_M (USB_NAKSTS5_V << USB_NAKSTS5_S) +#define USB_NAKSTS5_V 0x00000001 +#define USB_NAKSTS5_S 17 +/** USB_EPTYPE5 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 5 + */ +#define USB_EPTYPE5 0x00000003 +#define USB_EPTYPE5_M (USB_EPTYPE5_V << USB_EPTYPE5_S) +#define USB_EPTYPE5_V 0x00000003 +#define USB_EPTYPE5_S 18 +/** USB_SNP5 : R/W; bitpos: [20]; default: 0; + * 0x0 : Reserved 0 + * 0x1 : Reserved 1 + */ +#define USB_SNP5 (BIT(20)) +#define USB_SNP5_M (USB_SNP5_V << USB_SNP5_S) +#define USB_SNP5_V 0x00000001 +#define USB_SNP5_S 20 +/** USB_STALL5 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it, when a SETUP token + * is received for this endpoint + * 0x0 (INACTIVE): No Stall + * 0x1 (ACTIVE): Stall Handshake + */ +#define USB_STALL5 (BIT(21)) +#define USB_STALL5_M (USB_STALL5_V << USB_STALL5_S) +#define USB_STALL5_V 0x00000001 +#define USB_STALL5_S 21 +/** USB_CNAK5 : WO; bitpos: [26]; default: 0; + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_CNAK5 (BIT(26)) +#define USB_CNAK5_M (USB_CNAK5_V << USB_CNAK5_S) +#define USB_CNAK5_V 0x00000001 +#define USB_CNAK5_S 26 +/** USB_DO_SNAK5 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DO_SNAK5 (BIT(27)) +#define USB_DO_SNAK5_M (USB_DO_SNAK5_V << USB_DO_SNAK5_S) +#define USB_DO_SNAK5_V 0x00000001 +#define USB_DO_SNAK5_S 27 +/** USB_DO_SETD0PID5 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DO_SETD0PID5 (BIT(28)) +#define USB_DO_SETD0PID5_M (USB_DO_SETD0PID5_V << USB_DO_SETD0PID5_S) +#define USB_DO_SETD0PID5_V 0x00000001 +#define USB_DO_SETD0PID5_S 28 +/** USB_DO_SETD1PID5 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DO_SETD1PID5 (BIT(29)) +#define USB_DO_SETD1PID5_M (USB_DO_SETD1PID5_V << USB_DO_SETD1PID5_S) +#define USB_DO_SETD1PID5_V 0x00000001 +#define USB_DO_SETD1PID5_S 29 +/** USB_EPDIS5 : RO; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No Endpoint disable + */ +#define USB_EPDIS5 (BIT(30)) +#define USB_EPDIS5_M (USB_EPDIS5_V << USB_EPDIS5_S) +#define USB_EPDIS5_V 0x00000001 +#define USB_EPDIS5_S 30 +/** USB_EPENA5 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_EPENA5 (BIT(31)) +#define USB_EPENA5_M (USB_EPENA5_V << USB_EPENA5_S) +#define USB_EPENA5_V 0x00000001 +#define USB_EPENA5_S 31 + + +/** USB_DOEPTSIZ5_REG register + * Device OUT Endpoint 5 Transfer Size Register + */ +#define USB_DOEPTSIZ5_REG (SOC_DPORT_USB_BASE + 0xbb0) +/** USB_XFERSIZE5 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size.Indicates the transfer size in bytes for ENDPOINT5 + */ +#define USB_XFERSIZE5 0x0000007F +#define USB_XFERSIZE5_M (USB_XFERSIZE5_V << USB_XFERSIZE5_S) +#define USB_XFERSIZE5_V 0x0000007F +#define USB_XFERSIZE5_S 0 +/** USB_PKTCNT5 : R/W; bitpos: [19]; default: 0; + * Packet Count (PktCnt).This field is decremented to zero after a packet is written + * into the RxFIFO. + */ +#define USB_PKTCNT5 (BIT(19)) +#define USB_PKTCNT5_M (USB_PKTCNT5_V << USB_PKTCNT5_S) +#define USB_PKTCNT5_V 0x00000001 +#define USB_PKTCNT5_S 19 +/** USB_SUPCNT5 : R/W; bitpos: [31:29]; default: 0; + * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP + * data packets the endpoint can receive + * 2'b01: 1 packet + * 2'b10: 2 packets + * 2'b11: 3 packets + */ +#define USB_SUPCNT5 0x00000003 +#define USB_SUPCNT5_M (USB_SUPCNT5_V << USB_SUPCNT5_S) +#define USB_SUPCNT5_V 0x00000003 +#define USB_SUPCNT5_S 29 + + +/** USB_DOEPDMA5_REG register + * Device OUT Endpoint 5 DMA Address Register + */ +#define USB_DOEPDMA5_REG (SOC_DPORT_USB_BASE + 0xbb4) +/** USB_DMAADDR5 : R/W; bitpos: [32:0]; default: 0; + * Holds the start address of the external memory for storing or fetching endpoint + * data. + */ +#define USB_DMAADDR5 0xFFFFFFFF +#define USB_DMAADDR5_M (USB_DMAADDR5_V << USB_DMAADDR5_S) +#define USB_DMAADDR5_V 0xFFFFFFFF +#define USB_DMAADDR5_S 0 + + +/** USB_DOEPDMAB5_REG register + * Device OUT Endpoint 16 Buffer Address Register + */ +#define USB_DOEPDMAB5_REG (SOC_DPORT_USB_BASE + 0xbbc) +/** USB_DMABUFFERADDR5 : R/W; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_DMABUFFERADDR5 0xFFFFFFFF +#define USB_DMABUFFERADDR5_M (USB_DMABUFFERADDR5_V << USB_DMABUFFERADDR5_S) +#define USB_DMABUFFERADDR5_V 0xFFFFFFFF +#define USB_DMABUFFERADDR5_S 0 + + +/** USB_DOEPCTL6_REG register + * Device Control OUT Endpoint 6 Control Register + */ +#define USB_DOEPCTL6_REG (SOC_DPORT_USB_BASE + 0xbc0) +/** USB_MPS6 : RO; bitpos: [11:0]; default: 0; + * Maximum Packet Size in bytes + */ +#define USB_MPS6 0x000007FF +#define USB_MPS6_M (USB_MPS6_V << USB_MPS6_S) +#define USB_MPS6_V 0x000007FF +#define USB_MPS6_S 0 +/** USB_USBACTEP6 : RO; bitpos: [15]; default: 1; + * 0x1: USB Active Endpoint 0 + */ +#define USB_USBACTEP6 (BIT(15)) +#define USB_USBACTEP6_M (USB_USBACTEP6_V << USB_USBACTEP6_S) +#define USB_USBACTEP6_V 0x00000001 +#define USB_USBACTEP6_S 15 +/** USB_NAKSTS6 : RO; bitpos: [17]; default: 0; + * 0x0 : The core is transmitting non-NAK handshakes based on the FIFO status + * 0x1 :The core is transmitting NAK handshakes on this endpoint + */ +#define USB_NAKSTS6 (BIT(17)) +#define USB_NAKSTS6_M (USB_NAKSTS6_V << USB_NAKSTS6_S) +#define USB_NAKSTS6_V 0x00000001 +#define USB_NAKSTS6_S 17 +/** USB_EPTYPE6 : RO; bitpos: [20:18]; default: 0; + * Endpoint Type + * 0x0 : Endpoint Control 6 + */ +#define USB_EPTYPE6 0x00000003 +#define USB_EPTYPE6_M (USB_EPTYPE6_V << USB_EPTYPE6_S) +#define USB_EPTYPE6_V 0x00000003 +#define USB_EPTYPE6_S 18 +/** USB_SNP6 : R/W; bitpos: [20]; default: 0; + * 0x0 : Reserved 0 + * 0x1 : Reserved 1 + */ +#define USB_SNP6 (BIT(20)) +#define USB_SNP6_M (USB_SNP6_V << USB_SNP6_S) +#define USB_SNP6_V 0x00000001 +#define USB_SNP6_S 20 +/** USB_STALL6 : R/W; bitpos: [21]; default: 0; + * The application can only set this bit, and the core clears it, when a SETUP token + * is received for this endpoint + * 0x0 (INACTIVE): No Stall + * 0x1 (ACTIVE): Stall Handshake + */ +#define USB_STALL6 (BIT(21)) +#define USB_STALL6_M (USB_STALL6_V << USB_STALL6_S) +#define USB_STALL6_V 0x00000001 +#define USB_STALL6_S 21 +/** USB_CNAK6 : WO; bitpos: [26]; default: 0; + * 0x0 : No action + * 0x1 : Clear NAK + */ +#define USB_CNAK6 (BIT(26)) +#define USB_CNAK6_M (USB_CNAK6_V << USB_CNAK6_S) +#define USB_CNAK6_V 0x00000001 +#define USB_CNAK6_S 26 +/** USB_DO_SNAK6 : WO; bitpos: [27]; default: 0; + * A write to this bit sets the NAK bit for the endpoint + * 0x0 : No action + * 0x1 : Set NAK + */ +#define USB_DO_SNAK6 (BIT(27)) +#define USB_DO_SNAK6_M (USB_DO_SNAK6_V << USB_DO_SNAK6_S) +#define USB_DO_SNAK6_V 0x00000001 +#define USB_DO_SNAK6_S 27 +/** USB_DO_SETD0PID6 : WO; bitpos: [28]; default: 0; + * Set DATA0 PID + */ +#define USB_DO_SETD0PID6 (BIT(28)) +#define USB_DO_SETD0PID6_M (USB_DO_SETD0PID6_V << USB_DO_SETD0PID6_S) +#define USB_DO_SETD0PID6_V 0x00000001 +#define USB_DO_SETD0PID6_S 28 +/** USB_DO_SETD1PID6 : WO; bitpos: [29]; default: 0; + * Set DATA1 PID + */ +#define USB_DO_SETD1PID6 (BIT(29)) +#define USB_DO_SETD1PID6_M (USB_DO_SETD1PID6_V << USB_DO_SETD1PID6_S) +#define USB_DO_SETD1PID6_V 0x00000001 +#define USB_DO_SETD1PID6_S 29 +/** USB_EPDIS6 : RO; bitpos: [30]; default: 0; + * Endpoint Disable + * 0x0 : No Endpoint disable + */ +#define USB_EPDIS6 (BIT(30)) +#define USB_EPDIS6_M (USB_EPDIS6_V << USB_EPDIS6_S) +#define USB_EPDIS6_V 0x00000001 +#define USB_EPDIS6_S 30 +/** USB_EPENA6 : R/W; bitpos: [31]; default: 0; + * Endpoint Enable + * 0x0 : No action + * 0x1 : Enable Endpoint + */ +#define USB_EPENA6 (BIT(31)) +#define USB_EPENA6_M (USB_EPENA6_V << USB_EPENA6_S) +#define USB_EPENA6_V 0x00000001 +#define USB_EPENA6_S 31 + + +/** USB_DOEPTSIZ6_REG register + * Device OUT Endpoint 6 Transfer Size Register + */ +#define USB_DOEPTSIZ6_REG (SOC_DPORT_USB_BASE + 0xbd0) +/** USB_XFERSIZE6 : R/W; bitpos: [7:0]; default: 0; + * Transfer Size.Indicates the transfer size in bytes for ENDPOINT6 + */ +#define USB_XFERSIZE6 0x0000007F +#define USB_XFERSIZE6_M (USB_XFERSIZE6_V << USB_XFERSIZE6_S) +#define USB_XFERSIZE6_V 0x0000007F +#define USB_XFERSIZE6_S 0 +/** USB_PKTCNT6 : R/W; bitpos: [19]; default: 0; + * Packet Count (PktCnt).This field is decremented to zero after a packet is written + * into the RxFIFO. + */ +#define USB_PKTCNT6 (BIT(19)) +#define USB_PKTCNT6_M (USB_PKTCNT6_V << USB_PKTCNT6_S) +#define USB_PKTCNT6_V 0x00000001 +#define USB_PKTCNT6_S 19 +/** USB_SUPCNT6 : R/W; bitpos: [31:29]; default: 0; + * SETUP Packet Count (SUPCnt).This field specifies the number of back-to-back SETUP + * data packets the endpoint can receive + * 2'b01: 1 packet + * 2'b10: 2 packets + * 2'b11: 3 packets + */ +#define USB_SUPCNT6 0x00000003 +#define USB_SUPCNT6_M (USB_SUPCNT6_V << USB_SUPCNT6_S) +#define USB_SUPCNT6_V 0x00000003 +#define USB_SUPCNT6_S 29 + + +/** USB_DOEPDMA6_REG register + * Device OUT Endpoint 6 DMA Address Register + */ +#define USB_DOEPDMA6_REG (SOC_DPORT_USB_BASE + 0xbd4) +/** USB_DMAADDR6 : R/W; bitpos: [32:0]; default: 0; + * Holds the start address of the external memory for storing or fetching endpoint + * data. + */ +#define USB_DMAADDR6 0xFFFFFFFF +#define USB_DMAADDR6_M (USB_DMAADDR6_V << USB_DMAADDR6_S) +#define USB_DMAADDR6_V 0xFFFFFFFF +#define USB_DMAADDR6_S 0 + + +/** USB_DOEPDMAB6_REG register + * Device OUT Endpoint 16 Buffer Address Register + */ +#define USB_DOEPDMAB6_REG (SOC_DPORT_USB_BASE + 0xbdc) +/** USB_DMABUFFERADDR6 : R/W; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_DMABUFFERADDR6 0xFFFFFFFF +#define USB_DMABUFFERADDR6_M (USB_DMABUFFERADDR6_V << USB_DMABUFFERADDR6_S) +#define USB_DMABUFFERADDR6_V 0xFFFFFFFF +#define USB_DMABUFFERADDR6_S 0 + + +/** USB_PCGCCTL_REG register + * Power and Clock Gating Control Register + */ +#define USB_PCGCCTL_REG (SOC_DPORT_USB_BASE + 0xe00) +/** USB_STOPPCLK : R/W; bitpos: [0]; default: 0; + * 0x0 : Disable Stop Pclk + * 0x1 : Enable Stop Pclk + */ +#define USB_STOPPCLK (BIT(0)) +#define USB_STOPPCLK_M (USB_STOPPCLK_V << USB_STOPPCLK_S) +#define USB_STOPPCLK_V 0x00000001 +#define USB_STOPPCLK_S 0 +/** USB_GATEHCLK : R/W; bitpos: [1]; default: 0; + * gate hclk + * 0x0:clears this bit when USB is resumed or a new session starts + * 0x1:set this bit to gate hclk to modules, when the USB is suspended or the session + * is not valid + */ +#define USB_GATEHCLK (BIT(1)) +#define USB_GATEHCLK_M (USB_GATEHCLK_V << USB_GATEHCLK_S) +#define USB_GATEHCLK_V 0x00000001 +#define USB_GATEHCLK_S 1 +/** USB_PWRCLMP : R/W; bitpos: [2]; default: 0; + * 0x0:Clears this bit to disable the clamping before the power is turned on + * 0x1:In only Partial Power-Down mode, sets this bit to clamp the signals between the + * power-on modules and the power-off modules before the power is turned off + */ +#define USB_PWRCLMP (BIT(2)) +#define USB_PWRCLMP_M (USB_PWRCLMP_V << USB_PWRCLMP_S) +#define USB_PWRCLMP_V 0x00000001 +#define USB_PWRCLMP_S 2 +/** USB_RSTPDWNMODULE : R/W; bitpos: [3]; default: 0; + * Reset Power-Down Modules. + * 0x0 : Power is turned on + * 0x1 : Power is turned off + */ +#define USB_RSTPDWNMODULE (BIT(3)) +#define USB_RSTPDWNMODULE_M (USB_RSTPDWNMODULE_V << USB_RSTPDWNMODULE_S) +#define USB_RSTPDWNMODULE_V 0x00000001 +#define USB_RSTPDWNMODULE_S 3 +/** USB_PHYSLEEP : RO; bitpos: [6]; default: 0; + * 0x0 : Phy not in Sleep state + * 0x1 : Phy in Sleep state + */ +#define USB_PHYSLEEP (BIT(6)) +#define USB_PHYSLEEP_M (USB_PHYSLEEP_V << USB_PHYSLEEP_S) +#define USB_PHYSLEEP_V 0x00000001 +#define USB_PHYSLEEP_S 6 +/** USB_L1SUSPENDED : RO; bitpos: [7]; default: 0; + * L1 Deep Sleep + * 0x0 : Non Deep Sleep + * 0x1 : Deep Sleep + */ +#define USB_L1SUSPENDED (BIT(7)) +#define USB_L1SUSPENDED_M (USB_L1SUSPENDED_V << USB_L1SUSPENDED_S) +#define USB_L1SUSPENDED_V 0x00000001 +#define USB_L1SUSPENDED_S 7 +/** USB_RESETAFTERSUSP : R/W; bitpos: [8]; default: 0; + * Reset after suspend + * 0x0 : In Host-only mode, host issues Resume after Suspend + * 0x1 : In Host-only mode, host sets this bit before clamp is removed if the host + * needs to issue Reset after Suspend + */ +#define USB_RESETAFTERSUSP (BIT(8)) +#define USB_RESETAFTERSUSP_M (USB_RESETAFTERSUSP_V << USB_RESETAFTERSUSP_S) +#define USB_RESETAFTERSUSP_V 0x00000001 +#define USB_RESETAFTERSUSP_S 8 + + + + +/** Interrupt registers */ +/** USB_GOTGINT_REG register + * OTG Interrupt Register + */ +#define USB_GOTGINT_REG (SOC_DPORT_USB_BASE + 0x4) +/** USB_SESENDDET : R/W1C; bitpos: [2]; default: 0; + * Session End Detected.The controller sets this bit when the utmiotg_bvalid signal is + * deasserted. This bit can be set only by the core and the application should write 1 + * to clear it + */ +#define USB_SESENDDET (BIT(2)) +#define USB_SESENDDET_M (USB_SESENDDET_V << USB_SESENDDET_S) +#define USB_SESENDDET_V 0x00000001 +#define USB_SESENDDET_S 2 +/** USB_SESREQSUCSTSCHNG : R/W1C; bitpos: [8]; default: 0; + * Session Request Success Status Change.The core sets this bit on the success or + * failure of a session request.The application must read the Session Request Success + * bit in the OTG Control and Status register (GOTGCTL_REG.USB_SESREQSCS) to check for + * success or failure. This bit can be set only by the core and the application should + * write 1 to clear it. + */ +#define USB_SESREQSUCSTSCHNG (BIT(8)) +#define USB_SESREQSUCSTSCHNG_M (USB_SESREQSUCSTSCHNG_V << USB_SESREQSUCSTSCHNG_S) +#define USB_SESREQSUCSTSCHNG_V 0x00000001 +#define USB_SESREQSUCSTSCHNG_S 8 +/** USB_HSTNEGSUCSTSCHNG : R/W1C; bitpos: [9]; default: 0; + * Host Negotiation Success Status Change. The core sets this bit on the success or + * failure of a USB host negotiation request. The application must read the Host + * Negotiation Success bit of the OTG Control and Status register + * (GOTGCTL_REG.USB_HSTNEGSCS) to check for success or failure. This bit can be set + * only by the core and the application should write 1 to clear it + */ +#define USB_HSTNEGSUCSTSCHNG (BIT(9)) +#define USB_HSTNEGSUCSTSCHNG_M (USB_HSTNEGSUCSTSCHNG_V << USB_HSTNEGSUCSTSCHNG_S) +#define USB_HSTNEGSUCSTSCHNG_V 0x00000001 +#define USB_HSTNEGSUCSTSCHNG_S 9 +/** USB_HSTNEGDET : R/W1C; bitpos: [17]; default: 0; + * Host Negotiation Detected.The core sets this bit when it detects a host negotiation + * request on the USB. This bit can be set only by the core and the application should + * write 1 to clear it. + */ +#define USB_HSTNEGDET (BIT(17)) +#define USB_HSTNEGDET_M (USB_HSTNEGDET_V << USB_HSTNEGDET_S) +#define USB_HSTNEGDET_V 0x00000001 +#define USB_HSTNEGDET_S 17 +/** USB_ADEVTOUTCHG : R/W1C; bitpos: [18]; default: 0; + * A-Device Timeout Change. The core sets this bit to indicate that the A-device has + * timed out while waiting for the B-device to connect.This bit can be set only by the + * core and the application should write 1 to clear it + */ +#define USB_ADEVTOUTCHG (BIT(18)) +#define USB_ADEVTOUTCHG_M (USB_ADEVTOUTCHG_V << USB_ADEVTOUTCHG_S) +#define USB_ADEVTOUTCHG_V 0x00000001 +#define USB_ADEVTOUTCHG_S 18 +/** USB_DBNCEDONE : R/W1C; bitpos: [19]; default: 0; + * Debounce Done. The core sets this bit when the debounce is completed after the + * device connect. The application can start driving USB reset after seeing this + * interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET in + * the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, + * respectively). This bit can be set only by the core and the application should + * write 1 to clear it + */ +#define USB_DBNCEDONE (BIT(19)) +#define USB_DBNCEDONE_M (USB_DBNCEDONE_V << USB_DBNCEDONE_S) +#define USB_DBNCEDONE_V 0x00000001 +#define USB_DBNCEDONE_S 19 + + +/** USB_GINTSTS_REG register + * Interrupt Register + */ +#define USB_GINTSTS_REG (SOC_DPORT_USB_BASE + 0x14) +/** USB_CURMOD_INT : RO; bitpos: [0]; default: 0; + * Current Mode of Operation + * 1'b0: Device mode + * 1'b1: Host mode + */ +#define USB_CURMOD_INT (BIT(0)) +#define USB_CURMOD_INT_M (USB_CURMOD_INT_V << USB_CURMOD_INT_S) +#define USB_CURMOD_INT_V 0x00000001 +#define USB_CURMOD_INT_S 0 +/** USB_MODEMIS : R/W1C; bitpos: [1]; default: 0; + * Mode Mismatch Interrupt.The core sets this bit when the application is trying to + * access:A Host mode register, when the controller is operating in Device mode + */ +#define USB_MODEMIS (BIT(1)) +#define USB_MODEMIS_M (USB_MODEMIS_V << USB_MODEMIS_S) +#define USB_MODEMIS_V 0x00000001 +#define USB_MODEMIS_S 1 +/** USB_OTGINT : RO; bitpos: [2]; default: 0; + * OTG Interrupt.The controller sets this bit to indicate an OTG protocol event. The + * application must read the OTG Interrupt Status (GOTGINT_REG) register to determine + * the exact event that caused this interrupt. The application must clear the + * appropriate status bit in the GOTGINT_REG register to clear this bit. + */ +#define USB_OTGINT (BIT(2)) +#define USB_OTGINT_M (USB_OTGINT_V << USB_OTGINT_S) +#define USB_OTGINT_V 0x00000001 +#define USB_OTGINT_S 2 +/** USB_SOF : R/W1C; bitpos: [3]; default: 0; + * Start of (micro)Frame (Sof) + * In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS), + * or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to + * this bit to clear the interrupt + * In Device mode, the controller sets this bit to indicate that an SOF token has been + * received on the USB. The application can read the Device Status register to get the + * current (micro)Frame number. This Interrupt is seen only when the core is operating + * at either HS or FS. This bit can be set only by the core and the application must + * write 1 to clear it + */ +#define USB_SOF (BIT(3)) +#define USB_SOF_M (USB_SOF_V << USB_SOF_S) +#define USB_SOF_V 0x00000001 +#define USB_SOF_S 3 +/** USB_RXFLVI : RO; bitpos: [4]; default: 0; + * RxFIFO Non-Empty.Indicates that there is at least one packet pending to be read + * from the RxFIFO + * 1'b0: Rx Fifo is empty + * 1'b1: Rx Fifo is not empty + */ +#define USB_RXFLVI (BIT(4)) +#define USB_RXFLVI_M (USB_RXFLVI_V << USB_RXFLVI_S) +#define USB_RXFLVI_V 0x00000001 +#define USB_RXFLVI_S 4 +/** USB_NPTXFEMP : RO; bitpos: [5]; default: 0; + * Non-periodic TxFIFO Empty.This interrupt is asserted when the Non-periodic TxFIFO + * is either half or completely empty, and there is space for at least one Entry to be + * written to the Non-periodic Transmit Request Queue. The half or completely empty + * status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB + * Configuration register (GAHBCFG_REG.USB_NPTXFEMPLVL). + */ +#define USB_NPTXFEMP (BIT(5)) +#define USB_NPTXFEMP_M (USB_NPTXFEMP_V << USB_NPTXFEMP_S) +#define USB_NPTXFEMP_V 0x00000001 +#define USB_NPTXFEMP_S 5 +/** USB_GINNAKEFF : RO; bitpos: [6]; default: 0; + * Device only.Global IN Non-periodic NAK Effective.Indicates that the Set Global + * Non-periodic IN NAK bit in the Device Control register (DCTL.SGNPInNak) set by the + * application, has taken effect in the core. That is, the core has sampled the Global + * IN NAK bit Set by the application. This bit can be cleared by clearing the Clear + * Global Non-periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak). + * This interrupt does not necessarily mean that a NAK handshake is sent out on the + * USB. The STALL bit takes precedence over the NAK bit. + */ +#define USB_GINNAKEFF (BIT(6)) +#define USB_GINNAKEFF_M (USB_GINNAKEFF_V << USB_GINNAKEFF_S) +#define USB_GINNAKEFF_V 0x00000001 +#define USB_GINNAKEFF_S 6 +/** USB_GOUTNAKEFF : RO; bitpos: [7]; default: 0; + * Device only.Global OUT NAK Effective.Indicates that the Set Global OUT NAK bit in + * the Device Control register (DCTL_REG.USB_SGOUTNAK), Set by the application, has + * taken effect in the core. This bit can be cleared by writing the Clear Global OUT + * NAK bit in the Device Control register (DCTL_REG.REG_CGOUTNAK). + */ +#define USB_GOUTNAKEFF (BIT(7)) +#define USB_GOUTNAKEFF_M (USB_GOUTNAKEFF_V << USB_GOUTNAKEFF_S) +#define USB_GOUTNAKEFF_V 0x00000001 +#define USB_GOUTNAKEFF_S 7 +/** USB_ERLYSUSP : R/W1C; bitpos: [10]; default: 0; + * Device only.Early Suspend.The controller sets this bit to indicate that an Idle + * state has been detected on the USB for 3 ms. + */ +#define USB_ERLYSUSP (BIT(10)) +#define USB_ERLYSUSP_M (USB_ERLYSUSP_V << USB_ERLYSUSP_S) +#define USB_ERLYSUSP_V 0x00000001 +#define USB_ERLYSUSP_S 10 +/** USB_USBSUSP : R/W1C; bitpos: [11]; default: 0; + * Device only.USB Suspend.The controller sets this bit to indicate that a suspend was + * detected on the USB. The controller enters the Suspended state when there is no + * activity on the linestate signal for an extended period of time. + */ +#define USB_USBSUSP (BIT(11)) +#define USB_USBSUSP_M (USB_USBSUSP_V << USB_USBSUSP_S) +#define USB_USBSUSP_V 0x00000001 +#define USB_USBSUSP_S 11 +/** USB_USBRST : R/W1C; bitpos: [12]; default: 0; + * Device only.USB Reset.The controller sets this bit to indicate that a reset is + * detected on the USB + */ +#define USB_USBRST (BIT(12)) +#define USB_USBRST_M (USB_USBRST_V << USB_USBRST_S) +#define USB_USBRST_V 0x00000001 +#define USB_USBRST_S 12 +/** USB_ENUMDONE : R/W1C; bitpos: [13]; default: 0; + * Device only.Enumeration Done.The core sets this bit to indicate that speed + * enumeration is complete. The application must read the Device Status (DSTS_REG) + * register to obtain the enumerated speed. + */ +#define USB_ENUMDONE (BIT(13)) +#define USB_ENUMDONE_M (USB_ENUMDONE_V << USB_ENUMDONE_S) +#define USB_ENUMDONE_V 0x00000001 +#define USB_ENUMDONE_S 13 +/** USB_ISOOUTDROP : R/W1C; bitpos: [14]; default: 0; + * Device only.Isochronous OUT Packet Dropped Interrupt.The controller sets this bit + * when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO + * does not have enough space to accommodate a maximum packet size packet for the + * isochronous OUT endpoint. + */ +#define USB_ISOOUTDROP (BIT(14)) +#define USB_ISOOUTDROP_M (USB_ISOOUTDROP_V << USB_ISOOUTDROP_S) +#define USB_ISOOUTDROP_V 0x00000001 +#define USB_ISOOUTDROP_S 14 +/** USB_EOPF : R/W1C; bitpos: [15]; default: 0; + * Device only.End of Periodic Frame Interrupt.Indicates that the period specified in + * the Periodic Frame Interval field of the Device Configuration register + * (DCFG_REG.REG_PERFRINT) has been reached in the current microframe. + */ +#define USB_EOPF (BIT(15)) +#define USB_EOPF_M (USB_EOPF_V << USB_EOPF_S) +#define USB_EOPF_V 0x00000001 +#define USB_EOPF_S 15 +/** USB_EPMIS : R/W1C; bitpos: [17]; default: 0; + * Device only.Endpoint Mismatch Interrupt.This interrupt is valid only in shared FIFO + * operation.Indicates that an IN token has been received for a non-periodic endpoint, + * but the data for another endpoint is present in the top of the Non-periodic + * Transmit FIFO and the IN endpoint mismatch count programmed by the application has + * expired. + */ +#define USB_EPMIS (BIT(17)) +#define USB_EPMIS_M (USB_EPMIS_V << USB_EPMIS_S) +#define USB_EPMIS_V 0x00000001 +#define USB_EPMIS_S 17 +/** USB_IEPINT : RO; bitpos: [18]; default: 0; + * Device only.IN Endpoints Interrupt.The core sets this bit to indicate that an + * interrupt is pending on one of the IN endpoints of the core (in Device mode). The + * application must read the Device All Endpoints Interrupt (DAINT) register to + * determine the exact number of the IN endpoint on Device IN Endpoint-n Interrupt + * (DIEPINTn) register to determine the exact cause of the interrupt. The application + * must clear the appropriate status bit in the corresponding DIEPINTn register to + * clear this bit. + */ +#define USB_IEPINT (BIT(18)) +#define USB_IEPINT_M (USB_IEPINT_V << USB_IEPINT_S) +#define USB_IEPINT_V 0x00000001 +#define USB_IEPINT_S 18 +/** USB_OEPINT : RO; bitpos: [19]; default: 0; + * Device only.OUT Endpoints Interrupt.The controller sets this bit to indicate that + * an interrupt is pending on one of the OUT endpoints of the core (in Device mode). + * The application must read the Device All Endpoints Interrupt (DAINT) register to + * determine the exact number of the OUT endpoint on which the interrupt occurred, and + * then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to + * determine the exact cause of the interrupt. The application must clear the + * appropriate status bit in the corresponding DOEPINTn register to clear this bit. + */ +#define USB_OEPINT (BIT(19)) +#define USB_OEPINT_M (USB_OEPINT_V << USB_OEPINT_S) +#define USB_OEPINT_V 0x00000001 +#define USB_OEPINT_S 19 +/** USB_INCOMPISOIN : R/W1C; bitpos: [20]; default: 0; + * Device only.Incomplete Isochronous IN Transfer.The core sets this interrupt to + * indicate that there is at least one isochronous IN endpoint on which the transfer + * is not completed in the current microframe. This interrupt is asserted along with + * the End of Periodic Frame Interrupt (EOPF) bit in this register. + */ +#define USB_INCOMPISOIN (BIT(20)) +#define USB_INCOMPISOIN_M (USB_INCOMPISOIN_V << USB_INCOMPISOIN_S) +#define USB_INCOMPISOIN_V 0x00000001 +#define USB_INCOMPISOIN_S 20 +/** USB_INCOMPIP : R/W1C; bitpos: [21]; default: 0; + * In Host mode, the core sets this interrupt bit when there are incomplete periodic + * transactions still pending which are scheduled for the current microframe.The + * Device mode, the core sets this interrupt to indicate that thereis at least one + * isochronous OUT endpoint on which the transfer is not completed in the current + * microframe. This interrupt is asserted along with the End of Periodic Frame + * Interrupt (EOPF) bit in this register. + */ +#define USB_INCOMPIP (BIT(21)) +#define USB_INCOMPIP_M (USB_INCOMPIP_V << USB_INCOMPIP_S) +#define USB_INCOMPIP_V 0x00000001 +#define USB_INCOMPIP_S 21 +/** USB_FETSUSP : R/W1C; bitpos: [22]; default: 0; + * Device only.Data Fetch Suspended.This interrupt is valid only in DMA mode. This + * interrupt indicates that the core has stopped fetching data. For IN endpoints due + * to the unavailability of TxFIFO space or Request Queue space. This interrupt is + * used by the application for an endpoint mismatch algorithm + */ +#define USB_FETSUSP (BIT(22)) +#define USB_FETSUSP_M (USB_FETSUSP_V << USB_FETSUSP_S) +#define USB_FETSUSP_V 0x00000001 +#define USB_FETSUSP_S 22 +/** USB_RESETDET : R/W1C; bitpos: [23]; default: 0; + * Reset detected Interrupt + * In Device mode, this interrupt is asserted when a reset is detected on the USB in + * partial power-down mode when the device is in Suspend + * In Host mode, this interrupt is not asserted + */ +#define USB_RESETDET (BIT(23)) +#define USB_RESETDET_M (USB_RESETDET_V << USB_RESETDET_S) +#define USB_RESETDET_V 0x00000001 +#define USB_RESETDET_S 23 +/** USB_PRTLNT : RO; bitpos: [24]; default: 0; + * Host only.Host Port Interrupt.The core sets this bit to indicate a change in port + * status of one of the controller ports in Host mode. The application must read the + * Host Port Control and Status (HPRT) register to determine the exact event that + * caused this interrupt. The application must clear the appropriate status bit in the + * Host Port Control and Status register to clear this bit. + */ +#define USB_PRTLNT (BIT(24)) +#define USB_PRTLNT_M (USB_PRTLNT_V << USB_PRTLNT_S) +#define USB_PRTLNT_V 0x00000001 +#define USB_PRTLNT_S 24 +/** USB_HCHLNT : RO; bitpos: [25]; default: 0; + * Host only.Host Channels Interrupt.The core sets this bit to indicate that an + * interrupt is pending on one of the channels of the core (in Host mode). The + * application must read the Host All Channels Interrupt (HAINT) register to determine + * the exact number of the channel on which the interrupt occurred,and Then read the + * corresponding Host Channel-n Interrupt (HCINTn) register to determine the exact + * cause of the interrupt.The application must clear the appropriate status bit in the + * HCINTn register to clear this bit. + */ +#define USB_HCHLNT (BIT(25)) +#define USB_HCHLNT_M (USB_HCHLNT_V << USB_HCHLNT_S) +#define USB_HCHLNT_V 0x00000001 +#define USB_HCHLNT_S 25 +/** USB_PTXFEMP : RO; bitpos: [26]; default: 0; + * Host only.Periodic TxFIFO Empty.This interrupt is asserted when the Periodic + * Transmit FIFO is either half or completely empty and there is space for at least + * one entry to be written in the Periodic Request Queue. The half or completelyempty + * status is determined by the Periodic TxFIFO Empty Level bit in the Core AHB + * Configuration register (GAHBCFG.PTxFEmpLvl) + */ +#define USB_PTXFEMP (BIT(26)) +#define USB_PTXFEMP_M (USB_PTXFEMP_V << USB_PTXFEMP_S) +#define USB_PTXFEMP_V 0x00000001 +#define USB_PTXFEMP_S 26 +/** USB_CONIDSTSCHNG : R/W1C; bitpos: [28]; default: 0; + * Connector ID Status Change + * 1'b0:Not active + * 1'b1:Connector ID Status Change + */ +#define USB_CONIDSTSCHNG (BIT(28)) +#define USB_CONIDSTSCHNG_M (USB_CONIDSTSCHNG_V << USB_CONIDSTSCHNG_S) +#define USB_CONIDSTSCHNG_V 0x00000001 +#define USB_CONIDSTSCHNG_S 28 +/** USB_DISCONNINT : R/W1C; bitpos: [29]; default: 0; + * Disconnect Detected Interrupt + * 1'b0:Not active + * 1'b1:Disconnect Detected Interrupt + */ +#define USB_DISCONNINT (BIT(29)) +#define USB_DISCONNINT_M (USB_DISCONNINT_V << USB_DISCONNINT_S) +#define USB_DISCONNINT_V 0x00000001 +#define USB_DISCONNINT_S 29 +/** USB_SESSREQINT : R/W1C; bitpos: [30]; default: 0; + * 1'b0:Not active + * 1'b1:Session Request New Session Detected + */ +#define USB_SESSREQINT (BIT(30)) +#define USB_SESSREQINT_M (USB_SESSREQINT_V << USB_SESSREQINT_S) +#define USB_SESSREQINT_V 0x00000001 +#define USB_SESSREQINT_S 30 +/** USB_WKUPINT : R/W1C; bitpos: [31]; default: 0; + * Resume/Remote Wakeup Detected Interrupt + * 1'b0:Not active + * 1'b1:Resume or Remote Wakeup Detected Interrupt + */ +#define USB_WKUPINT (BIT(31)) +#define USB_WKUPINT_M (USB_WKUPINT_V << USB_WKUPINT_S) +#define USB_WKUPINT_V 0x00000001 +#define USB_WKUPINT_S 31 + + +/** USB_GINTMSK_REG register + * Interrupt Mask Register + */ +#define USB_GINTMSK_REG (SOC_DPORT_USB_BASE + 0x18) +/** USB_MODEMISMSK : R/W; bitpos: [1]; default: 0; + * 1'b0:Mode Mismatch Interrupt Mask + * 1'b1:No Mode Mismatch Interrupt Mask + */ +#define USB_MODEMISMSK (BIT(1)) +#define USB_MODEMISMSK_M (USB_MODEMISMSK_V << USB_MODEMISMSK_S) +#define USB_MODEMISMSK_V 0x00000001 +#define USB_MODEMISMSK_S 1 +/** USB_OTGINTMSK : R/W; bitpos: [2]; default: 0; + * 1'b0:OTG Interrupt Mask + * 1'b1:No OTG Interrupt Mask + */ +#define USB_OTGINTMSK (BIT(2)) +#define USB_OTGINTMSK_M (USB_OTGINTMSK_V << USB_OTGINTMSK_S) +#define USB_OTGINTMSK_V 0x00000001 +#define USB_OTGINTMSK_S 2 +/** USB_SOFMSK : R/W; bitpos: [3]; default: 0; + * 1'b0:Start of (micro)Frame Mask + * 1'b1:No Start of (micro)Frame Mask + */ +#define USB_SOFMSK (BIT(3)) +#define USB_SOFMSK_M (USB_SOFMSK_V << USB_SOFMSK_S) +#define USB_SOFMSK_V 0x00000001 +#define USB_SOFMSK_S 3 +/** USB_RXFLVIMSK : R/W; bitpos: [4]; default: 0; + * 1'b0:Receive FIFO Non-Empty Mask + * 1'b1:No Receive FIFO Non-Empty Mask + */ +#define USB_RXFLVIMSK (BIT(4)) +#define USB_RXFLVIMSK_M (USB_RXFLVIMSK_V << USB_RXFLVIMSK_S) +#define USB_RXFLVIMSK_V 0x00000001 +#define USB_RXFLVIMSK_S 4 +/** USB_NPTXFEMPMSK : R/W; bitpos: [5]; default: 0; + * 1'b0:Non-periodic TxFIFO Empty Mask + * 1'b1:No Non-periodic TxFIFO Empty Mask + */ +#define USB_NPTXFEMPMSK (BIT(5)) +#define USB_NPTXFEMPMSK_M (USB_NPTXFEMPMSK_V << USB_NPTXFEMPMSK_S) +#define USB_NPTXFEMPMSK_V 0x00000001 +#define USB_NPTXFEMPMSK_S 5 +/** USB_GINNAKEFFMSK : R/W; bitpos: [6]; default: 0; + * 1'b0:Global Non-periodic IN NAK Effective Mask + * 1'b1:No Global Non-periodic IN NAK Effective Mask + */ +#define USB_GINNAKEFFMSK (BIT(6)) +#define USB_GINNAKEFFMSK_M (USB_GINNAKEFFMSK_V << USB_GINNAKEFFMSK_S) +#define USB_GINNAKEFFMSK_V 0x00000001 +#define USB_GINNAKEFFMSK_S 6 +/** USB_GOUTNACKEFFMSK : R/W; bitpos: [7]; default: 0; + * 1'b0:Global OUT NAK Effective Mask + * 1'b1:No Global OUT NAK Effective Mask + */ +#define USB_GOUTNACKEFFMSK (BIT(7)) +#define USB_GOUTNACKEFFMSK_M (USB_GOUTNACKEFFMSK_V << USB_GOUTNACKEFFMSK_S) +#define USB_GOUTNACKEFFMSK_V 0x00000001 +#define USB_GOUTNACKEFFMSK_S 7 +/** USB_ERLYSUSPMSK : R/W; bitpos: [10]; default: 0; + * 1'b0:Early Suspend Mask + * 1'b1:No Early Suspend Mask + */ +#define USB_ERLYSUSPMSK (BIT(10)) +#define USB_ERLYSUSPMSK_M (USB_ERLYSUSPMSK_V << USB_ERLYSUSPMSK_S) +#define USB_ERLYSUSPMSK_V 0x00000001 +#define USB_ERLYSUSPMSK_S 10 +/** USB_USBSUSPMSK : R/W; bitpos: [11]; default: 0; + * 1'b0:USB Suspend Mask + * 1'b1:No USB Suspend Mask + */ +#define USB_USBSUSPMSK (BIT(11)) +#define USB_USBSUSPMSK_M (USB_USBSUSPMSK_V << USB_USBSUSPMSK_S) +#define USB_USBSUSPMSK_V 0x00000001 +#define USB_USBSUSPMSK_S 11 +/** USB_USBRSTMSK : R/W; bitpos: [12]; default: 0; + * 1'b0:USB Reset Mask + * 1'b1:No USB Reset Mask + */ +#define USB_USBRSTMSK (BIT(12)) +#define USB_USBRSTMSK_M (USB_USBRSTMSK_V << USB_USBRSTMSK_S) +#define USB_USBRSTMSK_V 0x00000001 +#define USB_USBRSTMSK_S 12 +/** USB_ENUMDONEMSK : R/W; bitpos: [13]; default: 0; + * 1'b0: Enumeration Done Mask + * 1'b1: No Enumeration Done Mask + */ +#define USB_ENUMDONEMSK (BIT(13)) +#define USB_ENUMDONEMSK_M (USB_ENUMDONEMSK_V << USB_ENUMDONEMSK_S) +#define USB_ENUMDONEMSK_V 0x00000001 +#define USB_ENUMDONEMSK_S 13 +/** USB_ISOOUTDROPMSK : R/W; bitpos: [14]; default: 0; + * 1'b0: Isochronous OUT Packet Dropped Interrupt Mask + * 1'b1: No Isochronous OUT Packet Dropped Interrupt Mask + */ +#define USB_ISOOUTDROPMSK (BIT(14)) +#define USB_ISOOUTDROPMSK_M (USB_ISOOUTDROPMSK_V << USB_ISOOUTDROPMSK_S) +#define USB_ISOOUTDROPMSK_V 0x00000001 +#define USB_ISOOUTDROPMSK_S 14 +/** USB_EOPFMSK : R/W; bitpos: [15]; default: 0; + * 1'b0: End of Periodic Frame Interrupt Mask + * 1'b1: No End of Periodic Frame Interrupt Mask + */ +#define USB_EOPFMSK (BIT(15)) +#define USB_EOPFMSK_M (USB_EOPFMSK_V << USB_EOPFMSK_S) +#define USB_EOPFMSK_V 0x00000001 +#define USB_EOPFMSK_S 15 +/** USB_EPMISMSK : R/W; bitpos: [17]; default: 0; + * 1'b0: Endpoint Mismatch Interrupt Mask + * 1'b1: No Endpoint Mismatch Interrupt Mask + */ +#define USB_EPMISMSK (BIT(17)) +#define USB_EPMISMSK_M (USB_EPMISMSK_V << USB_EPMISMSK_S) +#define USB_EPMISMSK_V 0x00000001 +#define USB_EPMISMSK_S 17 +/** USB_IEPINTMSK : R/W; bitpos: [18]; default: 0; + * 1'b0: IN Endpoints Interrupt Mask + * 1'b1: No IN Endpoints Interrupt Mask + */ +#define USB_IEPINTMSK (BIT(18)) +#define USB_IEPINTMSK_M (USB_IEPINTMSK_V << USB_IEPINTMSK_S) +#define USB_IEPINTMSK_V 0x00000001 +#define USB_IEPINTMSK_S 18 +/** USB_OEPINTMSK : R/W; bitpos: [19]; default: 0; + * 1'b0: OUT Endpoints Interrupt Mask + * 1'b1: No OUT Endpoints Interrupt Mask + */ +#define USB_OEPINTMSK (BIT(19)) +#define USB_OEPINTMSK_M (USB_OEPINTMSK_V << USB_OEPINTMSK_S) +#define USB_OEPINTMSK_V 0x00000001 +#define USB_OEPINTMSK_S 19 +/** USB_INCOMPISOINMSK : R/W; bitpos: [20]; default: 0; + * 1'b0: Incomplete Isochronous IN Transfer Mask + * 1'b1: No Incomplete Isochronous IN Transfer Mask + */ +#define USB_INCOMPISOINMSK (BIT(20)) +#define USB_INCOMPISOINMSK_M (USB_INCOMPISOINMSK_V << USB_INCOMPISOINMSK_S) +#define USB_INCOMPISOINMSK_V 0x00000001 +#define USB_INCOMPISOINMSK_S 20 +/** USB_INCOMPIPMSK : R/W; bitpos: [21]; default: 0; + * 1'b0: Host mode: Incomplete Periodic Transfer Mask Device mode: Incomplete + * Isochronous OUT Transfer Mask + * 1'b1: Host mode: No Incomplete Periodic Transfer Mask Device mode: No Incomplete + * Isochronous OUT Transfer Mask + */ +#define USB_INCOMPIPMSK (BIT(21)) +#define USB_INCOMPIPMSK_M (USB_INCOMPIPMSK_V << USB_INCOMPIPMSK_S) +#define USB_INCOMPIPMSK_V 0x00000001 +#define USB_INCOMPIPMSK_S 21 +/** USB_FETSUSPMSK : R/W; bitpos: [22]; default: 0; + * 1'b0: Data Fetch Suspended Mask + * 1'b1: No Data Fetch Suspended Mask + */ +#define USB_FETSUSPMSK (BIT(22)) +#define USB_FETSUSPMSK_M (USB_FETSUSPMSK_V << USB_FETSUSPMSK_S) +#define USB_FETSUSPMSK_V 0x00000001 +#define USB_FETSUSPMSK_S 22 +/** USB_RESETDETMSK : R/W; bitpos: [23]; default: 0; + * 1'b0: Reset detected Interrupt Mask + * 1'b1: No Reset detected Interrupt Mask + */ +#define USB_RESETDETMSK (BIT(23)) +#define USB_RESETDETMSK_M (USB_RESETDETMSK_V << USB_RESETDETMSK_S) +#define USB_RESETDETMSK_V 0x00000001 +#define USB_RESETDETMSK_S 23 +/** USB_PRTLNTMSK : R/W; bitpos: [24]; default: 0; + * 1'b0: Host Port Interrupt Mask + * 1'b1: No Host Port Interrupt Mask + */ +#define USB_PRTLNTMSK (BIT(24)) +#define USB_PRTLNTMSK_M (USB_PRTLNTMSK_V << USB_PRTLNTMSK_S) +#define USB_PRTLNTMSK_V 0x00000001 +#define USB_PRTLNTMSK_S 24 +/** USB_HCHINTMSK : R/W; bitpos: [25]; default: 0; + * 1'b0: Host Channels Interrupt Mask + * 1'b1: No Host Channels Interrupt Mask + */ +#define USB_HCHINTMSK (BIT(25)) +#define USB_HCHINTMSK_M (USB_HCHINTMSK_V << USB_HCHINTMSK_S) +#define USB_HCHINTMSK_V 0x00000001 +#define USB_HCHINTMSK_S 25 +/** USB_PTXFEMPMSK : R/W; bitpos: [26]; default: 0; + * 1'b0: Periodic TxFIFO Empty Mask + * 1'b1: No Periodic TxFIFO Empty Mask + */ +#define USB_PTXFEMPMSK (BIT(26)) +#define USB_PTXFEMPMSK_M (USB_PTXFEMPMSK_V << USB_PTXFEMPMSK_S) +#define USB_PTXFEMPMSK_V 0x00000001 +#define USB_PTXFEMPMSK_S 26 +/** USB_CONIDSTSCHNGMSK : R/W; bitpos: [28]; default: 0; + * 1'b0: Connector ID Status Change Mask + * 1'b1: No Connector ID Status Change Mask + */ +#define USB_CONIDSTSCHNGMSK (BIT(28)) +#define USB_CONIDSTSCHNGMSK_M (USB_CONIDSTSCHNGMSK_V << USB_CONIDSTSCHNGMSK_S) +#define USB_CONIDSTSCHNGMSK_V 0x00000001 +#define USB_CONIDSTSCHNGMSK_S 28 +/** USB_DISCONNINTMSK : R/W; bitpos: [29]; default: 0; + * 1'b0: Disconnect Detected Interrupt Mask + * 1'b1: No Disconnect Detected Interrupt Mask + */ +#define USB_DISCONNINTMSK (BIT(29)) +#define USB_DISCONNINTMSK_M (USB_DISCONNINTMSK_V << USB_DISCONNINTMSK_S) +#define USB_DISCONNINTMSK_V 0x00000001 +#define USB_DISCONNINTMSK_S 29 +/** USB_SESSREQINTMSK : R/W; bitpos: [30]; default: 0; + * 1'b0: Session Request or New Session Detected Interrupt Mask + * 1'b1: No Session Request or New Session Detected Interrupt Mask + */ +#define USB_SESSREQINTMSK (BIT(30)) +#define USB_SESSREQINTMSK_M (USB_SESSREQINTMSK_V << USB_SESSREQINTMSK_S) +#define USB_SESSREQINTMSK_V 0x00000001 +#define USB_SESSREQINTMSK_S 30 +/** USB_WKUPINTMSK : R/W; bitpos: [31]; default: 0; + * 1'b0 : Resume or Remote Wakeup Detected Interrupt Mask + * 1'b1 : Unmask Resume Remote Wakeup Detected Interrupt + */ +#define USB_WKUPINTMSK (BIT(31)) +#define USB_WKUPINTMSK_M (USB_WKUPINTMSK_V << USB_WKUPINTMSK_S) +#define USB_WKUPINTMSK_V 0x00000001 +#define USB_WKUPINTMSK_S 31 + + +/** USB_HAINT_REG register + * Host All Channels Interrupt Register + */ +#define USB_HAINT_REG (SOC_DPORT_USB_BASE + 0x414) +/** USB_HAINT : RO; bitpos: [8:0]; default: 0; + * Channel Interrupt for channel no. + */ +#define USB_HAINT 0x000000FF +#define USB_HAINT_M (USB_HAINT_V << USB_HAINT_S) +#define USB_HAINT_V 0x000000FF +#define USB_HAINT_S 0 + + +/** USB_HAINTMSK_REG register + * Host All Channels Interrupt Mask Register + */ +#define USB_HAINTMSK_REG (SOC_DPORT_USB_BASE + 0x418) +/** USB_HAINTMSK : R/W; bitpos: [8:0]; default: 0; + * Channel Interrupt Mask (HAINTMSK_REG) One bit per channel: Bit 0 for channel 0, bit + * 15 for channel 15. + */ +#define USB_HAINTMSK 0x000000FF +#define USB_HAINTMSK_M (USB_HAINTMSK_V << USB_HAINTMSK_S) +#define USB_HAINTMSK_V 0x000000FF +#define USB_HAINTMSK_S 0 + + +/** USB_HCINT0_REG register + * Host Channel 0 Interrupt Register + */ +#define USB_HCINT0_REG (SOC_DPORT_USB_BASE + 0x508) +/** USB_H_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0; + * 1'b0: Transfer in progress or No Active Transfer + * 1'b1: Transfer completed normally without any errors + */ +#define USB_H_XFERCOMPL0 (BIT(0)) +#define USB_H_XFERCOMPL0_M (USB_H_XFERCOMPL0_V << USB_H_XFERCOMPL0_S) +#define USB_H_XFERCOMPL0_V 0x00000001 +#define USB_H_XFERCOMPL0_S 0 +/** USB_H_CHHLTD0 : R/W1C; bitpos: [1]; default: 0; + * 1'b0: Channel not halted + * 1'b1: Channel Halted + */ +#define USB_H_CHHLTD0 (BIT(1)) +#define USB_H_CHHLTD0_M (USB_H_CHHLTD0_V << USB_H_CHHLTD0_S) +#define USB_H_CHHLTD0_V 0x00000001 +#define USB_H_CHHLTD0_S 1 +/** USB_H_AHBERR0 : R/W1C; bitpos: [2]; default: 0; + * 1'b0: No AHB error + * 1'b1: AHB error during AHB read/write + */ +#define USB_H_AHBERR0 (BIT(2)) +#define USB_H_AHBERR0_M (USB_H_AHBERR0_V << USB_H_AHBERR0_S) +#define USB_H_AHBERR0_V 0x00000001 +#define USB_H_AHBERR0_S 2 +/** USB_H_STALL0 : R/W1C; bitpos: [3]; default: 0; + * 1'b0: No Stall Response Received Interrupt + * 1'b1: Stall Response Received Interrupt + */ +#define USB_H_STALL0 (BIT(3)) +#define USB_H_STALL0_M (USB_H_STALL0_V << USB_H_STALL0_S) +#define USB_H_STALL0_V 0x00000001 +#define USB_H_STALL0_S 3 +/** USB_H_NACK0 : R/W1C; bitpos: [4]; default: 0; + * 1'b0: No NAK Response Received Interrupt + * 1'b1: NAK Response Received Interrupt + */ +#define USB_H_NACK0 (BIT(4)) +#define USB_H_NACK0_M (USB_H_NACK0_V << USB_H_NACK0_S) +#define USB_H_NACK0_V 0x00000001 +#define USB_H_NACK0_S 4 +/** USB_H_ACK0 : R/W1C; bitpos: [5]; default: 0; + * 1'b0: No ACK Response Received or Transmitted Interrupt + * 1'b1: ACK Response Received or Transmitted Interrup + */ +#define USB_H_ACK0 (BIT(5)) +#define USB_H_ACK0_M (USB_H_ACK0_V << USB_H_ACK0_S) +#define USB_H_ACK0_V 0x00000001 +#define USB_H_ACK0_S 5 +/** USB_H_NYET0 : R/W1C; bitpos: [6]; default: 0; + * 1'b0: No NYET Response Received Interrupt + * 1'b1: NYET Response Received Interrupt + */ +#define USB_H_NYET0 (BIT(6)) +#define USB_H_NYET0_M (USB_H_NYET0_V << USB_H_NYET0_S) +#define USB_H_NYET0_V 0x00000001 +#define USB_H_NYET0_S 6 +/** USB_H_XACTERR0 : R/W1C; bitpos: [7]; default: 0; + * Indicates one of the following errors occurred on the USB: + * CRC check failure + * Timeout + * Bit stuff error + * False EOP + */ +#define USB_H_XACTERR0 (BIT(7)) +#define USB_H_XACTERR0_M (USB_H_XACTERR0_V << USB_H_XACTERR0_S) +#define USB_H_XACTERR0_V 0x00000001 +#define USB_H_XACTERR0_S 7 +/** USB_H_BBLERR0 : R/W1C; bitpos: [8]; default: 0; + * 1'b0: No Babble Error + * 1'b1: Babble Error + */ +#define USB_H_BBLERR0 (BIT(8)) +#define USB_H_BBLERR0_M (USB_H_BBLERR0_V << USB_H_BBLERR0_S) +#define USB_H_BBLERR0_V 0x00000001 +#define USB_H_BBLERR0_S 8 +/** USB_H_FRMOVRUN0 : R/W1C; bitpos: [9]; default: 0; + * 1'b0: No Frame Overrun + * 1'b1: Frame Overrun + */ +#define USB_H_FRMOVRUN0 (BIT(9)) +#define USB_H_FRMOVRUN0_M (USB_H_FRMOVRUN0_V << USB_H_FRMOVRUN0_S) +#define USB_H_FRMOVRUN0_V 0x00000001 +#define USB_H_FRMOVRUN0_S 9 +/** USB_H_DATATGLERR0 : R/W1C; bitpos: [10]; default: 0; + * 1'b0: No Data Toggle Error + * 1'b1: Data Toggle Error + */ +#define USB_H_DATATGLERR0 (BIT(10)) +#define USB_H_DATATGLERR0_M (USB_H_DATATGLERR0_V << USB_H_DATATGLERR0_S) +#define USB_H_DATATGLERR0_V 0x00000001 +#define USB_H_DATATGLERR0_S 10 +/** USB_H_BNAINTR0 : R/W1C; bitpos: [11]; default: 0; + * 1'b0: No BNA Interrupt + * 1'b1: BNA Interrupt + */ +#define USB_H_BNAINTR0 (BIT(11)) +#define USB_H_BNAINTR0_M (USB_H_BNAINTR0_V << USB_H_BNAINTR0_S) +#define USB_H_BNAINTR0_V 0x00000001 +#define USB_H_BNAINTR0_S 11 +/** USB_H_XCS_XACT_ERR0 : R/W1C; bitpos: [12]; default: 0; + * 1'b0: No Excessive Transaction Error + * 1'b1: Excessive Transaction Error + */ +#define USB_H_XCS_XACT_ERR0 (BIT(12)) +#define USB_H_XCS_XACT_ERR0_M (USB_H_XCS_XACT_ERR0_V << USB_H_XCS_XACT_ERR0_S) +#define USB_H_XCS_XACT_ERR0_V 0x00000001 +#define USB_H_XCS_XACT_ERR0_S 12 +/** USB_H_DESC_LST_ROLLINTR0 : R/W1C; bitpos: [13]; default: 0; + * 1'b0: No Descriptor rollover interrupt + * 1'b1: Descriptor rollover interrupt + */ +#define USB_H_DESC_LST_ROLLINTR0 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTR0_M (USB_H_DESC_LST_ROLLINTR0_V << USB_H_DESC_LST_ROLLINTR0_S) +#define USB_H_DESC_LST_ROLLINTR0_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTR0_S 13 + + +/** USB_HCINTMSK0_REG register + * Host Channel 0 Interrupt Mask Register + */ +#define USB_HCINTMSK0_REG (SOC_DPORT_USB_BASE + 0x50c) +/** USB_H_XFERCOMPLMSK0 : R/W; bitpos: [0]; default: 0; + * 1'b0: Transfer Completed Mask + * 1'b1: No Transfer Completed Mask + */ +#define USB_H_XFERCOMPLMSK0 (BIT(0)) +#define USB_H_XFERCOMPLMSK0_M (USB_H_XFERCOMPLMSK0_V << USB_H_XFERCOMPLMSK0_S) +#define USB_H_XFERCOMPLMSK0_V 0x00000001 +#define USB_H_XFERCOMPLMSK0_S 0 +/** USB_H_CHHLTDMSK0 : R/W; bitpos: [1]; default: 0; + * 1'b0: Channel Halted Mask + * 1'b1: No Channel Halted Mask + */ +#define USB_H_CHHLTDMSK0 (BIT(1)) +#define USB_H_CHHLTDMSK0_M (USB_H_CHHLTDMSK0_V << USB_H_CHHLTDMSK0_S) +#define USB_H_CHHLTDMSK0_V 0x00000001 +#define USB_H_CHHLTDMSK0_S 1 +/** USB_H_AHBERRMSK0 : R/W; bitpos: [2]; default: 0; + * 1'b0: AHB Error Mask + * 1'b1: No AHB Error Mask + */ +#define USB_H_AHBERRMSK0 (BIT(2)) +#define USB_H_AHBERRMSK0_M (USB_H_AHBERRMSK0_V << USB_H_AHBERRMSK0_S) +#define USB_H_AHBERRMSK0_V 0x00000001 +#define USB_H_AHBERRMSK0_S 2 +/** USB_H_STALLMSK0 : R/W; bitpos: [3]; default: 0; + * 1'b0: Mask STALL Response Received Interrupt + * 1'b1: No STALL Response Received Interrupt Mask + */ +#define USB_H_STALLMSK0 (BIT(3)) +#define USB_H_STALLMSK0_M (USB_H_STALLMSK0_V << USB_H_STALLMSK0_S) +#define USB_H_STALLMSK0_V 0x00000001 +#define USB_H_STALLMSK0_S 3 +/** USB_H_NAKMSK0 : R/W; bitpos: [4]; default: 0; + * 1'b0: Mask NAK Response Received Interrupt + * 1'b1: No NAK Response Received Interrupt Mask + */ +#define USB_H_NAKMSK0 (BIT(4)) +#define USB_H_NAKMSK0_M (USB_H_NAKMSK0_V << USB_H_NAKMSK0_S) +#define USB_H_NAKMSK0_V 0x00000001 +#define USB_H_NAKMSK0_S 4 +/** USB_H_ACKMSK0 : R/W; bitpos: [5]; default: 0; + * 1'b0: Mask ACK Response Received/Transmitted Interrupt + * 1'b1: No ACK Response Received/Transmitted Interrupt Mask + */ +#define USB_H_ACKMSK0 (BIT(5)) +#define USB_H_ACKMSK0_M (USB_H_ACKMSK0_V << USB_H_ACKMSK0_S) +#define USB_H_ACKMSK0_V 0x00000001 +#define USB_H_ACKMSK0_S 5 +/** USB_H_NYETMSK0 : R/W; bitpos: [6]; default: 0; + * 1'b0: Mask NYET Response Received Interrupt + * 1'b1: No NYET Response Received Interrupt Mask + */ +#define USB_H_NYETMSK0 (BIT(6)) +#define USB_H_NYETMSK0_M (USB_H_NYETMSK0_V << USB_H_NYETMSK0_S) +#define USB_H_NYETMSK0_V 0x00000001 +#define USB_H_NYETMSK0_S 6 +/** USB_H_XACTERRMSK0 : R/W; bitpos: [7]; default: 0; + * 1'b0: Mask Transaction Error + * 1'b1: No Transaction Error Mask + */ +#define USB_H_XACTERRMSK0 (BIT(7)) +#define USB_H_XACTERRMSK0_M (USB_H_XACTERRMSK0_V << USB_H_XACTERRMSK0_S) +#define USB_H_XACTERRMSK0_V 0x00000001 +#define USB_H_XACTERRMSK0_S 7 +/** USB_H_BBLERRMSK0 : R/W; bitpos: [8]; default: 0; + * Babble Error Mask + * 1'b0: Mask Babble Error + * 1'b1: No Babble Error Mask + */ +#define USB_H_BBLERRMSK0 (BIT(8)) +#define USB_H_BBLERRMSK0_M (USB_H_BBLERRMSK0_V << USB_H_BBLERRMSK0_S) +#define USB_H_BBLERRMSK0_V 0x00000001 +#define USB_H_BBLERRMSK0_S 8 +/** USB_H_FRMOVRUNMSK0 : R/W; bitpos: [9]; default: 0; + * Frame Overrun Mask + * 0x0 (MASK): Mask Overrun Mask + * 0x1 (NOMASK): No Frame Overrun Mask + */ +#define USB_H_FRMOVRUNMSK0 (BIT(9)) +#define USB_H_FRMOVRUNMSK0_M (USB_H_FRMOVRUNMSK0_V << USB_H_FRMOVRUNMSK0_S) +#define USB_H_FRMOVRUNMSK0_V 0x00000001 +#define USB_H_FRMOVRUNMSK0_S 9 +/** USB_H_DATATGLERRMSK0 : R/W; bitpos: [10]; default: 0; + * Data Toggle Error Mask n scatter/gather DMA mode for host + * 1'b0: Mask Data Toggle Error + * 1'b1: No Data Toggle Error Mask + */ +#define USB_H_DATATGLERRMSK0 (BIT(10)) +#define USB_H_DATATGLERRMSK0_M (USB_H_DATATGLERRMSK0_V << USB_H_DATATGLERRMSK0_S) +#define USB_H_DATATGLERRMSK0_V 0x00000001 +#define USB_H_DATATGLERRMSK0_S 10 +/** USB_H_BNAINTRMSK0 : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt mask register + * 1'b0: BNA Interrupt Masked + * 1'b1: BNA Interrupt not masked + */ +#define USB_H_BNAINTRMSK0 (BIT(11)) +#define USB_H_BNAINTRMSK0_M (USB_H_BNAINTRMSK0_V << USB_H_BNAINTRMSK0_S) +#define USB_H_BNAINTRMSK0_V 0x00000001 +#define USB_H_BNAINTRMSK0_S 11 +/** USB_H_DESC_LST_ROLLINTRMSK0 : R/W; bitpos: [13]; default: 0; + * Descriptor List rollover interrupt Mask + * 1'b0: Descriptor Rollover Interrupt Mask + * 1'b1: Descriptor Rollover Interrupt not masked + */ +#define USB_H_DESC_LST_ROLLINTRMSK0 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTRMSK0_M (USB_H_DESC_LST_ROLLINTRMSK0_V << USB_H_DESC_LST_ROLLINTRMSK0_S) +#define USB_H_DESC_LST_ROLLINTRMSK0_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTRMSK0_S 13 + + +/** USB_HCINT1_REG register + * Host Channel 1 Interrupt Register + */ +#define USB_HCINT1_REG (SOC_DPORT_USB_BASE + 0x528) +/** USB_H_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0; + * 1'b0: Transfer in progress or No Active Transfer + * 1'b1: Transfer completed normally without any errors + */ +#define USB_H_XFERCOMPL1 (BIT(0)) +#define USB_H_XFERCOMPL1_M (USB_H_XFERCOMPL1_V << USB_H_XFERCOMPL1_S) +#define USB_H_XFERCOMPL1_V 0x00000001 +#define USB_H_XFERCOMPL1_S 0 +/** USB_H_CHHLTD1 : R/W1C; bitpos: [1]; default: 0; + * 1'b0: Channel not halted + * 1'b1: Channel Halted + */ +#define USB_H_CHHLTD1 (BIT(1)) +#define USB_H_CHHLTD1_M (USB_H_CHHLTD1_V << USB_H_CHHLTD1_S) +#define USB_H_CHHLTD1_V 0x00000001 +#define USB_H_CHHLTD1_S 1 +/** USB_H_AHBERR1 : R/W1C; bitpos: [2]; default: 0; + * 1'b0: No AHB error + * 1'b1: AHB error during AHB read/write + */ +#define USB_H_AHBERR1 (BIT(2)) +#define USB_H_AHBERR1_M (USB_H_AHBERR1_V << USB_H_AHBERR1_S) +#define USB_H_AHBERR1_V 0x00000001 +#define USB_H_AHBERR1_S 2 +/** USB_H_STALL1 : R/W1C; bitpos: [3]; default: 0; + * 1'b0: No Stall Response Received Interrupt + * 1'b1: Stall Response Received Interrupt + */ +#define USB_H_STALL1 (BIT(3)) +#define USB_H_STALL1_M (USB_H_STALL1_V << USB_H_STALL1_S) +#define USB_H_STALL1_V 0x00000001 +#define USB_H_STALL1_S 3 +/** USB_H_NACK1 : R/W1C; bitpos: [4]; default: 0; + * 1'b0: No NAK Response Received Interrupt + * 1'b1: NAK Response Received Interrupt + */ +#define USB_H_NACK1 (BIT(4)) +#define USB_H_NACK1_M (USB_H_NACK1_V << USB_H_NACK1_S) +#define USB_H_NACK1_V 0x00000001 +#define USB_H_NACK1_S 4 +/** USB_H_ACK1 : R/W1C; bitpos: [5]; default: 0; + * 1'b0: No ACK Response Received or Transmitted Interrupt + * 1'b1: ACK Response Received or Transmitted Interrup + */ +#define USB_H_ACK1 (BIT(5)) +#define USB_H_ACK1_M (USB_H_ACK1_V << USB_H_ACK1_S) +#define USB_H_ACK1_V 0x00000001 +#define USB_H_ACK1_S 5 +/** USB_H_NYET1 : R/W1C; bitpos: [6]; default: 0; + * 1'b0: No NYET Response Received Interrupt + * 1'b1: NYET Response Received Interrupt + */ +#define USB_H_NYET1 (BIT(6)) +#define USB_H_NYET1_M (USB_H_NYET1_V << USB_H_NYET1_S) +#define USB_H_NYET1_V 0x00000001 +#define USB_H_NYET1_S 6 +/** USB_H_XACTERR1 : R/W1C; bitpos: [7]; default: 0; + * Indicates one of the following errors occurred on the USB: + * CRC check failure + * Timeout + * Bit stuff error + * False EOP + */ +#define USB_H_XACTERR1 (BIT(7)) +#define USB_H_XACTERR1_M (USB_H_XACTERR1_V << USB_H_XACTERR1_S) +#define USB_H_XACTERR1_V 0x00000001 +#define USB_H_XACTERR1_S 7 +/** USB_H_BBLERR1 : R/W1C; bitpos: [8]; default: 0; + * 1'b0: No Babble Error + * 1'b1: Babble Error + */ +#define USB_H_BBLERR1 (BIT(8)) +#define USB_H_BBLERR1_M (USB_H_BBLERR1_V << USB_H_BBLERR1_S) +#define USB_H_BBLERR1_V 0x00000001 +#define USB_H_BBLERR1_S 8 +/** USB_H_FRMOVRUN1 : R/W1C; bitpos: [9]; default: 0; + * 1'b0: No Frame Overrun + * 1'b1: Frame Overrun + */ +#define USB_H_FRMOVRUN1 (BIT(9)) +#define USB_H_FRMOVRUN1_M (USB_H_FRMOVRUN1_V << USB_H_FRMOVRUN1_S) +#define USB_H_FRMOVRUN1_V 0x00000001 +#define USB_H_FRMOVRUN1_S 9 +/** USB_H_DATATGLERR1 : R/W1C; bitpos: [10]; default: 0; + * 1'b0: No Data Toggle Error + * 1'b1: Data Toggle Error + */ +#define USB_H_DATATGLERR1 (BIT(10)) +#define USB_H_DATATGLERR1_M (USB_H_DATATGLERR1_V << USB_H_DATATGLERR1_S) +#define USB_H_DATATGLERR1_V 0x00000001 +#define USB_H_DATATGLERR1_S 10 +/** USB_H_BNAINTR1 : R/W1C; bitpos: [11]; default: 0; + * 1'b0: No BNA Interrupt + * 1'b1: BNA Interrupt + */ +#define USB_H_BNAINTR1 (BIT(11)) +#define USB_H_BNAINTR1_M (USB_H_BNAINTR1_V << USB_H_BNAINTR1_S) +#define USB_H_BNAINTR1_V 0x00000001 +#define USB_H_BNAINTR1_S 11 +/** USB_H_XCS_XACT_ERR1 : R/W1C; bitpos: [12]; default: 0; + * 1'b0: No Excessive Transaction Error + * 1'b1: Excessive Transaction Error + */ +#define USB_H_XCS_XACT_ERR1 (BIT(12)) +#define USB_H_XCS_XACT_ERR1_M (USB_H_XCS_XACT_ERR1_V << USB_H_XCS_XACT_ERR1_S) +#define USB_H_XCS_XACT_ERR1_V 0x00000001 +#define USB_H_XCS_XACT_ERR1_S 12 +/** USB_H_DESC_LST_ROLLINTR1 : R/W1C; bitpos: [13]; default: 0; + * 1'b0: No Descriptor rollover interrupt + * 1'b1: Descriptor rollover interrupt + */ +#define USB_H_DESC_LST_ROLLINTR1 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTR1_M (USB_H_DESC_LST_ROLLINTR1_V << USB_H_DESC_LST_ROLLINTR1_S) +#define USB_H_DESC_LST_ROLLINTR1_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTR1_S 13 + + +/** USB_HCINTMSK1_REG register + * Host Channel 1 Interrupt Mask Register + */ +#define USB_HCINTMSK1_REG (SOC_DPORT_USB_BASE + 0x52c) +/** USB_H_XFERCOMPLMSK1 : R/W; bitpos: [0]; default: 0; + * 1'b0: Transfer Completed Mask + * 1'b1: No Transfer Completed Mask + */ +#define USB_H_XFERCOMPLMSK1 (BIT(0)) +#define USB_H_XFERCOMPLMSK1_M (USB_H_XFERCOMPLMSK1_V << USB_H_XFERCOMPLMSK1_S) +#define USB_H_XFERCOMPLMSK1_V 0x00000001 +#define USB_H_XFERCOMPLMSK1_S 0 +/** USB_H_CHHLTDMSK1 : R/W; bitpos: [1]; default: 0; + * 1'b0: Channel Halted Mask + * 1'b1: No Channel Halted Mask + */ +#define USB_H_CHHLTDMSK1 (BIT(1)) +#define USB_H_CHHLTDMSK1_M (USB_H_CHHLTDMSK1_V << USB_H_CHHLTDMSK1_S) +#define USB_H_CHHLTDMSK1_V 0x00000001 +#define USB_H_CHHLTDMSK1_S 1 +/** USB_H_AHBERRMSK1 : R/W; bitpos: [2]; default: 0; + * 1'b0: AHB Error Mask + * 1'b1: No AHB Error Mask + */ +#define USB_H_AHBERRMSK1 (BIT(2)) +#define USB_H_AHBERRMSK1_M (USB_H_AHBERRMSK1_V << USB_H_AHBERRMSK1_S) +#define USB_H_AHBERRMSK1_V 0x00000001 +#define USB_H_AHBERRMSK1_S 2 +/** USB_H_STALLMSK1 : R/W; bitpos: [3]; default: 0; + * 1'b0: Mask STALL Response Received Interrupt + * 1'b1: No STALL Response Received Interrupt Mask + */ +#define USB_H_STALLMSK1 (BIT(3)) +#define USB_H_STALLMSK1_M (USB_H_STALLMSK1_V << USB_H_STALLMSK1_S) +#define USB_H_STALLMSK1_V 0x00000001 +#define USB_H_STALLMSK1_S 3 +/** USB_H_NAKMSK1 : R/W; bitpos: [4]; default: 0; + * 1'b0: Mask NAK Response Received Interrupt + * 1'b1: No NAK Response Received Interrupt Mask + */ +#define USB_H_NAKMSK1 (BIT(4)) +#define USB_H_NAKMSK1_M (USB_H_NAKMSK1_V << USB_H_NAKMSK1_S) +#define USB_H_NAKMSK1_V 0x00000001 +#define USB_H_NAKMSK1_S 4 +/** USB_H_ACKMSK1 : R/W; bitpos: [5]; default: 0; + * 1'b0: Mask ACK Response Received/Transmitted Interrupt + * 1'b1: No ACK Response Received/Transmitted Interrupt Mask + */ +#define USB_H_ACKMSK1 (BIT(5)) +#define USB_H_ACKMSK1_M (USB_H_ACKMSK1_V << USB_H_ACKMSK1_S) +#define USB_H_ACKMSK1_V 0x00000001 +#define USB_H_ACKMSK1_S 5 +/** USB_H_NYETMSK1 : R/W; bitpos: [6]; default: 0; + * 1'b0: Mask NYET Response Received Interrupt + * 1'b1: No NYET Response Received Interrupt Mask + */ +#define USB_H_NYETMSK1 (BIT(6)) +#define USB_H_NYETMSK1_M (USB_H_NYETMSK1_V << USB_H_NYETMSK1_S) +#define USB_H_NYETMSK1_V 0x00000001 +#define USB_H_NYETMSK1_S 6 +/** USB_H_XACTERRMSK1 : R/W; bitpos: [7]; default: 0; + * 1'b0: Mask Transaction Error + * 1'b1: No Transaction Error Mask + */ +#define USB_H_XACTERRMSK1 (BIT(7)) +#define USB_H_XACTERRMSK1_M (USB_H_XACTERRMSK1_V << USB_H_XACTERRMSK1_S) +#define USB_H_XACTERRMSK1_V 0x00000001 +#define USB_H_XACTERRMSK1_S 7 +/** USB_H_BBLERRMSK1 : R/W; bitpos: [8]; default: 0; + * Babble Error Mask + * 1'b0: Mask Babble Error + * 1'b1: No Babble Error Mask + */ +#define USB_H_BBLERRMSK1 (BIT(8)) +#define USB_H_BBLERRMSK1_M (USB_H_BBLERRMSK1_V << USB_H_BBLERRMSK1_S) +#define USB_H_BBLERRMSK1_V 0x00000001 +#define USB_H_BBLERRMSK1_S 8 +/** USB_H_FRMOVRUNMSK1 : R/W; bitpos: [9]; default: 0; + * Frame Overrun Mask + * 0x0 (MASK): Mask Overrun Mask + * 0x1 (NOMASK): No Frame Overrun Mask + */ +#define USB_H_FRMOVRUNMSK1 (BIT(9)) +#define USB_H_FRMOVRUNMSK1_M (USB_H_FRMOVRUNMSK1_V << USB_H_FRMOVRUNMSK1_S) +#define USB_H_FRMOVRUNMSK1_V 0x00000001 +#define USB_H_FRMOVRUNMSK1_S 9 +/** USB_H_DATATGLERRMSK1 : R/W; bitpos: [10]; default: 0; + * Data Toggle Error Mask n scatter/gather DMA mode for host + * 1'b0: Mask Data Toggle Error + * 1'b1: No Data Toggle Error Mask + */ +#define USB_H_DATATGLERRMSK1 (BIT(10)) +#define USB_H_DATATGLERRMSK1_M (USB_H_DATATGLERRMSK1_V << USB_H_DATATGLERRMSK1_S) +#define USB_H_DATATGLERRMSK1_V 0x00000001 +#define USB_H_DATATGLERRMSK1_S 10 +/** USB_H_BNAINTRMSK1 : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt mask register + * 1'b0: BNA Interrupt Masked + * 1'b1: BNA Interrupt not masked + */ +#define USB_H_BNAINTRMSK1 (BIT(11)) +#define USB_H_BNAINTRMSK1_M (USB_H_BNAINTRMSK1_V << USB_H_BNAINTRMSK1_S) +#define USB_H_BNAINTRMSK1_V 0x00000001 +#define USB_H_BNAINTRMSK1_S 11 +/** USB_H_DESC_LST_ROLLINTRMSK1 : R/W; bitpos: [13]; default: 0; + * Descriptor List rollover interrupt Mask + * 1'b0: Descriptor Rollover Interrupt Mask + * 1'b1: Descriptor Rollover Interrupt not masked + */ +#define USB_H_DESC_LST_ROLLINTRMSK1 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTRMSK1_M (USB_H_DESC_LST_ROLLINTRMSK1_V << USB_H_DESC_LST_ROLLINTRMSK1_S) +#define USB_H_DESC_LST_ROLLINTRMSK1_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTRMSK1_S 13 + + +/** USB_HCINT2_REG register + * Host Channel 2 Interrupt Register + */ +#define USB_HCINT2_REG (SOC_DPORT_USB_BASE + 0x548) +/** USB_H_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0; + * 1'b0: Transfer in progress or No Active Transfer + * 1'b1: Transfer completed normally without any errors + */ +#define USB_H_XFERCOMPL2 (BIT(0)) +#define USB_H_XFERCOMPL2_M (USB_H_XFERCOMPL2_V << USB_H_XFERCOMPL2_S) +#define USB_H_XFERCOMPL2_V 0x00000001 +#define USB_H_XFERCOMPL2_S 0 +/** USB_H_CHHLTD2 : R/W1C; bitpos: [1]; default: 0; + * 1'b0: Channel not halted + * 1'b1: Channel Halted + */ +#define USB_H_CHHLTD2 (BIT(1)) +#define USB_H_CHHLTD2_M (USB_H_CHHLTD2_V << USB_H_CHHLTD2_S) +#define USB_H_CHHLTD2_V 0x00000001 +#define USB_H_CHHLTD2_S 1 +/** USB_H_AHBERR2 : R/W1C; bitpos: [2]; default: 0; + * 1'b0: No AHB error + * 1'b1: AHB error during AHB read/write + */ +#define USB_H_AHBERR2 (BIT(2)) +#define USB_H_AHBERR2_M (USB_H_AHBERR2_V << USB_H_AHBERR2_S) +#define USB_H_AHBERR2_V 0x00000001 +#define USB_H_AHBERR2_S 2 +/** USB_H_STALL2 : R/W1C; bitpos: [3]; default: 0; + * 1'b0: No Stall Response Received Interrupt + * 1'b1: Stall Response Received Interrupt + */ +#define USB_H_STALL2 (BIT(3)) +#define USB_H_STALL2_M (USB_H_STALL2_V << USB_H_STALL2_S) +#define USB_H_STALL2_V 0x00000001 +#define USB_H_STALL2_S 3 +/** USB_H_NACK2 : R/W1C; bitpos: [4]; default: 0; + * 1'b0: No NAK Response Received Interrupt + * 1'b1: NAK Response Received Interrupt + */ +#define USB_H_NACK2 (BIT(4)) +#define USB_H_NACK2_M (USB_H_NACK2_V << USB_H_NACK2_S) +#define USB_H_NACK2_V 0x00000001 +#define USB_H_NACK2_S 4 +/** USB_H_ACK2 : R/W1C; bitpos: [5]; default: 0; + * 1'b0: No ACK Response Received or Transmitted Interrupt + * 1'b1: ACK Response Received or Transmitted Interrup + */ +#define USB_H_ACK2 (BIT(5)) +#define USB_H_ACK2_M (USB_H_ACK2_V << USB_H_ACK2_S) +#define USB_H_ACK2_V 0x00000001 +#define USB_H_ACK2_S 5 +/** USB_H_NYET2 : R/W1C; bitpos: [6]; default: 0; + * 1'b0: No NYET Response Received Interrupt + * 1'b1: NYET Response Received Interrupt + */ +#define USB_H_NYET2 (BIT(6)) +#define USB_H_NYET2_M (USB_H_NYET2_V << USB_H_NYET2_S) +#define USB_H_NYET2_V 0x00000001 +#define USB_H_NYET2_S 6 +/** USB_H_XACTERR2 : R/W1C; bitpos: [7]; default: 0; + * Indicates one of the following errors occurred on the USB: + * CRC check failure + * Timeout + * Bit stuff error + * False EOP + */ +#define USB_H_XACTERR2 (BIT(7)) +#define USB_H_XACTERR2_M (USB_H_XACTERR2_V << USB_H_XACTERR2_S) +#define USB_H_XACTERR2_V 0x00000001 +#define USB_H_XACTERR2_S 7 +/** USB_H_BBLERR2 : R/W1C; bitpos: [8]; default: 0; + * 1'b0: No Babble Error + * 1'b1: Babble Error + */ +#define USB_H_BBLERR2 (BIT(8)) +#define USB_H_BBLERR2_M (USB_H_BBLERR2_V << USB_H_BBLERR2_S) +#define USB_H_BBLERR2_V 0x00000001 +#define USB_H_BBLERR2_S 8 +/** USB_H_FRMOVRUN2 : R/W1C; bitpos: [9]; default: 0; + * 1'b0: No Frame Overrun + * 1'b1: Frame Overrun + */ +#define USB_H_FRMOVRUN2 (BIT(9)) +#define USB_H_FRMOVRUN2_M (USB_H_FRMOVRUN2_V << USB_H_FRMOVRUN2_S) +#define USB_H_FRMOVRUN2_V 0x00000001 +#define USB_H_FRMOVRUN2_S 9 +/** USB_H_DATATGLERR2 : R/W1C; bitpos: [10]; default: 0; + * 1'b0: No Data Toggle Error + * 1'b1: Data Toggle Error + */ +#define USB_H_DATATGLERR2 (BIT(10)) +#define USB_H_DATATGLERR2_M (USB_H_DATATGLERR2_V << USB_H_DATATGLERR2_S) +#define USB_H_DATATGLERR2_V 0x00000001 +#define USB_H_DATATGLERR2_S 10 +/** USB_H_BNAINTR2 : R/W1C; bitpos: [11]; default: 0; + * 1'b0: No BNA Interrupt + * 1'b1: BNA Interrupt + */ +#define USB_H_BNAINTR2 (BIT(11)) +#define USB_H_BNAINTR2_M (USB_H_BNAINTR2_V << USB_H_BNAINTR2_S) +#define USB_H_BNAINTR2_V 0x00000001 +#define USB_H_BNAINTR2_S 11 +/** USB_H_XCS_XACT_ERR2 : R/W1C; bitpos: [12]; default: 0; + * 1'b0: No Excessive Transaction Error + * 1'b1: Excessive Transaction Error + */ +#define USB_H_XCS_XACT_ERR2 (BIT(12)) +#define USB_H_XCS_XACT_ERR2_M (USB_H_XCS_XACT_ERR2_V << USB_H_XCS_XACT_ERR2_S) +#define USB_H_XCS_XACT_ERR2_V 0x00000001 +#define USB_H_XCS_XACT_ERR2_S 12 +/** USB_H_DESC_LST_ROLLINTR2 : R/W1C; bitpos: [13]; default: 0; + * 1'b0: No Descriptor rollover interrupt + * 1'b1: Descriptor rollover interrupt + */ +#define USB_H_DESC_LST_ROLLINTR2 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTR2_M (USB_H_DESC_LST_ROLLINTR2_V << USB_H_DESC_LST_ROLLINTR2_S) +#define USB_H_DESC_LST_ROLLINTR2_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTR2_S 13 + + +/** USB_HCINTMSK2_REG register + * Host Channel 2 Interrupt Mask Register + */ +#define USB_HCINTMSK2_REG (SOC_DPORT_USB_BASE + 0x54c) +/** USB_H_XFERCOMPLMSK2 : R/W; bitpos: [0]; default: 0; + * 1'b0: Transfer Completed Mask + * 1'b1: No Transfer Completed Mask + */ +#define USB_H_XFERCOMPLMSK2 (BIT(0)) +#define USB_H_XFERCOMPLMSK2_M (USB_H_XFERCOMPLMSK2_V << USB_H_XFERCOMPLMSK2_S) +#define USB_H_XFERCOMPLMSK2_V 0x00000001 +#define USB_H_XFERCOMPLMSK2_S 0 +/** USB_H_CHHLTDMSK2 : R/W; bitpos: [1]; default: 0; + * 1'b0: Channel Halted Mask + * 1'b1: No Channel Halted Mask + */ +#define USB_H_CHHLTDMSK2 (BIT(1)) +#define USB_H_CHHLTDMSK2_M (USB_H_CHHLTDMSK2_V << USB_H_CHHLTDMSK2_S) +#define USB_H_CHHLTDMSK2_V 0x00000001 +#define USB_H_CHHLTDMSK2_S 1 +/** USB_H_AHBERRMSK2 : R/W; bitpos: [2]; default: 0; + * 1'b0: AHB Error Mask + * 1'b1: No AHB Error Mask + */ +#define USB_H_AHBERRMSK2 (BIT(2)) +#define USB_H_AHBERRMSK2_M (USB_H_AHBERRMSK2_V << USB_H_AHBERRMSK2_S) +#define USB_H_AHBERRMSK2_V 0x00000001 +#define USB_H_AHBERRMSK2_S 2 +/** USB_H_STALLMSK2 : R/W; bitpos: [3]; default: 0; + * 1'b0: Mask STALL Response Received Interrupt + * 1'b1: No STALL Response Received Interrupt Mask + */ +#define USB_H_STALLMSK2 (BIT(3)) +#define USB_H_STALLMSK2_M (USB_H_STALLMSK2_V << USB_H_STALLMSK2_S) +#define USB_H_STALLMSK2_V 0x00000001 +#define USB_H_STALLMSK2_S 3 +/** USB_H_NAKMSK2 : R/W; bitpos: [4]; default: 0; + * 1'b0: Mask NAK Response Received Interrupt + * 1'b1: No NAK Response Received Interrupt Mask + */ +#define USB_H_NAKMSK2 (BIT(4)) +#define USB_H_NAKMSK2_M (USB_H_NAKMSK2_V << USB_H_NAKMSK2_S) +#define USB_H_NAKMSK2_V 0x00000001 +#define USB_H_NAKMSK2_S 4 +/** USB_H_ACKMSK2 : R/W; bitpos: [5]; default: 0; + * 1'b0: Mask ACK Response Received/Transmitted Interrupt + * 1'b1: No ACK Response Received/Transmitted Interrupt Mask + */ +#define USB_H_ACKMSK2 (BIT(5)) +#define USB_H_ACKMSK2_M (USB_H_ACKMSK2_V << USB_H_ACKMSK2_S) +#define USB_H_ACKMSK2_V 0x00000001 +#define USB_H_ACKMSK2_S 5 +/** USB_H_NYETMSK2 : R/W; bitpos: [6]; default: 0; + * 1'b0: Mask NYET Response Received Interrupt + * 1'b1: No NYET Response Received Interrupt Mask + */ +#define USB_H_NYETMSK2 (BIT(6)) +#define USB_H_NYETMSK2_M (USB_H_NYETMSK2_V << USB_H_NYETMSK2_S) +#define USB_H_NYETMSK2_V 0x00000001 +#define USB_H_NYETMSK2_S 6 +/** USB_H_XACTERRMSK2 : R/W; bitpos: [7]; default: 0; + * 1'b0: Mask Transaction Error + * 1'b1: No Transaction Error Mask + */ +#define USB_H_XACTERRMSK2 (BIT(7)) +#define USB_H_XACTERRMSK2_M (USB_H_XACTERRMSK2_V << USB_H_XACTERRMSK2_S) +#define USB_H_XACTERRMSK2_V 0x00000001 +#define USB_H_XACTERRMSK2_S 7 +/** USB_H_BBLERRMSK2 : R/W; bitpos: [8]; default: 0; + * Babble Error Mask + * 1'b0: Mask Babble Error + * 1'b1: No Babble Error Mask + */ +#define USB_H_BBLERRMSK2 (BIT(8)) +#define USB_H_BBLERRMSK2_M (USB_H_BBLERRMSK2_V << USB_H_BBLERRMSK2_S) +#define USB_H_BBLERRMSK2_V 0x00000001 +#define USB_H_BBLERRMSK2_S 8 +/** USB_H_FRMOVRUNMSK2 : R/W; bitpos: [9]; default: 0; + * Frame Overrun Mask + * 0x0 (MASK): Mask Overrun Mask + * 0x1 (NOMASK): No Frame Overrun Mask + */ +#define USB_H_FRMOVRUNMSK2 (BIT(9)) +#define USB_H_FRMOVRUNMSK2_M (USB_H_FRMOVRUNMSK2_V << USB_H_FRMOVRUNMSK2_S) +#define USB_H_FRMOVRUNMSK2_V 0x00000001 +#define USB_H_FRMOVRUNMSK2_S 9 +/** USB_H_DATATGLERRMSK2 : R/W; bitpos: [10]; default: 0; + * Data Toggle Error Mask n scatter/gather DMA mode for host + * 1'b0: Mask Data Toggle Error + * 1'b1: No Data Toggle Error Mask + */ +#define USB_H_DATATGLERRMSK2 (BIT(10)) +#define USB_H_DATATGLERRMSK2_M (USB_H_DATATGLERRMSK2_V << USB_H_DATATGLERRMSK2_S) +#define USB_H_DATATGLERRMSK2_V 0x00000001 +#define USB_H_DATATGLERRMSK2_S 10 +/** USB_H_BNAINTRMSK2 : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt mask register + * 1'b0: BNA Interrupt Masked + * 1'b1: BNA Interrupt not masked + */ +#define USB_H_BNAINTRMSK2 (BIT(11)) +#define USB_H_BNAINTRMSK2_M (USB_H_BNAINTRMSK2_V << USB_H_BNAINTRMSK2_S) +#define USB_H_BNAINTRMSK2_V 0x00000001 +#define USB_H_BNAINTRMSK2_S 11 +/** USB_H_DESC_LST_ROLLINTRMSK2 : R/W; bitpos: [13]; default: 0; + * Descriptor List rollover interrupt Mask + * 1'b0: Descriptor Rollover Interrupt Mask + * 1'b1: Descriptor Rollover Interrupt not masked + */ +#define USB_H_DESC_LST_ROLLINTRMSK2 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTRMSK2_M (USB_H_DESC_LST_ROLLINTRMSK2_V << USB_H_DESC_LST_ROLLINTRMSK2_S) +#define USB_H_DESC_LST_ROLLINTRMSK2_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTRMSK2_S 13 + + +/** USB_HCINT3_REG register + * Host Channel 3 Interrupt Register + */ +#define USB_HCINT3_REG (SOC_DPORT_USB_BASE + 0x568) +/** USB_H_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0; + * 1'b0: Transfer in progress or No Active Transfer + * 1'b1: Transfer completed normally without any errors + */ +#define USB_H_XFERCOMPL3 (BIT(0)) +#define USB_H_XFERCOMPL3_M (USB_H_XFERCOMPL3_V << USB_H_XFERCOMPL3_S) +#define USB_H_XFERCOMPL3_V 0x00000001 +#define USB_H_XFERCOMPL3_S 0 +/** USB_H_CHHLTD3 : R/W1C; bitpos: [1]; default: 0; + * 1'b0: Channel not halted + * 1'b1: Channel Halted + */ +#define USB_H_CHHLTD3 (BIT(1)) +#define USB_H_CHHLTD3_M (USB_H_CHHLTD3_V << USB_H_CHHLTD3_S) +#define USB_H_CHHLTD3_V 0x00000001 +#define USB_H_CHHLTD3_S 1 +/** USB_H_AHBERR3 : R/W1C; bitpos: [2]; default: 0; + * 1'b0: No AHB error + * 1'b1: AHB error during AHB read/write + */ +#define USB_H_AHBERR3 (BIT(2)) +#define USB_H_AHBERR3_M (USB_H_AHBERR3_V << USB_H_AHBERR3_S) +#define USB_H_AHBERR3_V 0x00000001 +#define USB_H_AHBERR3_S 2 +/** USB_H_STALL3 : R/W1C; bitpos: [3]; default: 0; + * 1'b0: No Stall Response Received Interrupt + * 1'b1: Stall Response Received Interrupt + */ +#define USB_H_STALL3 (BIT(3)) +#define USB_H_STALL3_M (USB_H_STALL3_V << USB_H_STALL3_S) +#define USB_H_STALL3_V 0x00000001 +#define USB_H_STALL3_S 3 +/** USB_H_NACK3 : R/W1C; bitpos: [4]; default: 0; + * 1'b0: No NAK Response Received Interrupt + * 1'b1: NAK Response Received Interrupt + */ +#define USB_H_NACK3 (BIT(4)) +#define USB_H_NACK3_M (USB_H_NACK3_V << USB_H_NACK3_S) +#define USB_H_NACK3_V 0x00000001 +#define USB_H_NACK3_S 4 +/** USB_H_ACK3 : R/W1C; bitpos: [5]; default: 0; + * 1'b0: No ACK Response Received or Transmitted Interrupt + * 1'b1: ACK Response Received or Transmitted Interrup + */ +#define USB_H_ACK3 (BIT(5)) +#define USB_H_ACK3_M (USB_H_ACK3_V << USB_H_ACK3_S) +#define USB_H_ACK3_V 0x00000001 +#define USB_H_ACK3_S 5 +/** USB_H_NYET3 : R/W1C; bitpos: [6]; default: 0; + * 1'b0: No NYET Response Received Interrupt + * 1'b1: NYET Response Received Interrupt + */ +#define USB_H_NYET3 (BIT(6)) +#define USB_H_NYET3_M (USB_H_NYET3_V << USB_H_NYET3_S) +#define USB_H_NYET3_V 0x00000001 +#define USB_H_NYET3_S 6 +/** USB_H_XACTERR3 : R/W1C; bitpos: [7]; default: 0; + * Indicates one of the following errors occurred on the USB: + * CRC check failure + * Timeout + * Bit stuff error + * False EOP + */ +#define USB_H_XACTERR3 (BIT(7)) +#define USB_H_XACTERR3_M (USB_H_XACTERR3_V << USB_H_XACTERR3_S) +#define USB_H_XACTERR3_V 0x00000001 +#define USB_H_XACTERR3_S 7 +/** USB_H_BBLERR3 : R/W1C; bitpos: [8]; default: 0; + * 1'b0: No Babble Error + * 1'b1: Babble Error + */ +#define USB_H_BBLERR3 (BIT(8)) +#define USB_H_BBLERR3_M (USB_H_BBLERR3_V << USB_H_BBLERR3_S) +#define USB_H_BBLERR3_V 0x00000001 +#define USB_H_BBLERR3_S 8 +/** USB_H_FRMOVRUN3 : R/W1C; bitpos: [9]; default: 0; + * 1'b0: No Frame Overrun + * 1'b1: Frame Overrun + */ +#define USB_H_FRMOVRUN3 (BIT(9)) +#define USB_H_FRMOVRUN3_M (USB_H_FRMOVRUN3_V << USB_H_FRMOVRUN3_S) +#define USB_H_FRMOVRUN3_V 0x00000001 +#define USB_H_FRMOVRUN3_S 9 +/** USB_H_DATATGLERR3 : R/W1C; bitpos: [10]; default: 0; + * 1'b0: No Data Toggle Error + * 1'b1: Data Toggle Error + */ +#define USB_H_DATATGLERR3 (BIT(10)) +#define USB_H_DATATGLERR3_M (USB_H_DATATGLERR3_V << USB_H_DATATGLERR3_S) +#define USB_H_DATATGLERR3_V 0x00000001 +#define USB_H_DATATGLERR3_S 10 +/** USB_H_BNAINTR3 : R/W1C; bitpos: [11]; default: 0; + * 1'b0: No BNA Interrupt + * 1'b1: BNA Interrupt + */ +#define USB_H_BNAINTR3 (BIT(11)) +#define USB_H_BNAINTR3_M (USB_H_BNAINTR3_V << USB_H_BNAINTR3_S) +#define USB_H_BNAINTR3_V 0x00000001 +#define USB_H_BNAINTR3_S 11 +/** USB_H_XCS_XACT_ERR3 : R/W1C; bitpos: [12]; default: 0; + * 1'b0: No Excessive Transaction Error + * 1'b1: Excessive Transaction Error + */ +#define USB_H_XCS_XACT_ERR3 (BIT(12)) +#define USB_H_XCS_XACT_ERR3_M (USB_H_XCS_XACT_ERR3_V << USB_H_XCS_XACT_ERR3_S) +#define USB_H_XCS_XACT_ERR3_V 0x00000001 +#define USB_H_XCS_XACT_ERR3_S 12 +/** USB_H_DESC_LST_ROLLINTR3 : R/W1C; bitpos: [13]; default: 0; + * 1'b0: No Descriptor rollover interrupt + * 1'b1: Descriptor rollover interrupt + */ +#define USB_H_DESC_LST_ROLLINTR3 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTR3_M (USB_H_DESC_LST_ROLLINTR3_V << USB_H_DESC_LST_ROLLINTR3_S) +#define USB_H_DESC_LST_ROLLINTR3_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTR3_S 13 + + +/** USB_HCINTMSK3_REG register + * Host Channel 3 Interrupt Mask Register + */ +#define USB_HCINTMSK3_REG (SOC_DPORT_USB_BASE + 0x56c) +/** USB_H_XFERCOMPLMSK3 : R/W; bitpos: [0]; default: 0; + * 1'b0: Transfer Completed Mask + * 1'b1: No Transfer Completed Mask + */ +#define USB_H_XFERCOMPLMSK3 (BIT(0)) +#define USB_H_XFERCOMPLMSK3_M (USB_H_XFERCOMPLMSK3_V << USB_H_XFERCOMPLMSK3_S) +#define USB_H_XFERCOMPLMSK3_V 0x00000001 +#define USB_H_XFERCOMPLMSK3_S 0 +/** USB_H_CHHLTDMSK3 : R/W; bitpos: [1]; default: 0; + * 1'b0: Channel Halted Mask + * 1'b1: No Channel Halted Mask + */ +#define USB_H_CHHLTDMSK3 (BIT(1)) +#define USB_H_CHHLTDMSK3_M (USB_H_CHHLTDMSK3_V << USB_H_CHHLTDMSK3_S) +#define USB_H_CHHLTDMSK3_V 0x00000001 +#define USB_H_CHHLTDMSK3_S 1 +/** USB_H_AHBERRMSK3 : R/W; bitpos: [2]; default: 0; + * 1'b0: AHB Error Mask + * 1'b1: No AHB Error Mask + */ +#define USB_H_AHBERRMSK3 (BIT(2)) +#define USB_H_AHBERRMSK3_M (USB_H_AHBERRMSK3_V << USB_H_AHBERRMSK3_S) +#define USB_H_AHBERRMSK3_V 0x00000001 +#define USB_H_AHBERRMSK3_S 2 +/** USB_H_STALLMSK3 : R/W; bitpos: [3]; default: 0; + * 1'b0: Mask STALL Response Received Interrupt + * 1'b1: No STALL Response Received Interrupt Mask + */ +#define USB_H_STALLMSK3 (BIT(3)) +#define USB_H_STALLMSK3_M (USB_H_STALLMSK3_V << USB_H_STALLMSK3_S) +#define USB_H_STALLMSK3_V 0x00000001 +#define USB_H_STALLMSK3_S 3 +/** USB_H_NAKMSK3 : R/W; bitpos: [4]; default: 0; + * 1'b0: Mask NAK Response Received Interrupt + * 1'b1: No NAK Response Received Interrupt Mask + */ +#define USB_H_NAKMSK3 (BIT(4)) +#define USB_H_NAKMSK3_M (USB_H_NAKMSK3_V << USB_H_NAKMSK3_S) +#define USB_H_NAKMSK3_V 0x00000001 +#define USB_H_NAKMSK3_S 4 +/** USB_H_ACKMSK3 : R/W; bitpos: [5]; default: 0; + * 1'b0: Mask ACK Response Received/Transmitted Interrupt + * 1'b1: No ACK Response Received/Transmitted Interrupt Mask + */ +#define USB_H_ACKMSK3 (BIT(5)) +#define USB_H_ACKMSK3_M (USB_H_ACKMSK3_V << USB_H_ACKMSK3_S) +#define USB_H_ACKMSK3_V 0x00000001 +#define USB_H_ACKMSK3_S 5 +/** USB_H_NYETMSK3 : R/W; bitpos: [6]; default: 0; + * 1'b0: Mask NYET Response Received Interrupt + * 1'b1: No NYET Response Received Interrupt Mask + */ +#define USB_H_NYETMSK3 (BIT(6)) +#define USB_H_NYETMSK3_M (USB_H_NYETMSK3_V << USB_H_NYETMSK3_S) +#define USB_H_NYETMSK3_V 0x00000001 +#define USB_H_NYETMSK3_S 6 +/** USB_H_XACTERRMSK3 : R/W; bitpos: [7]; default: 0; + * 1'b0: Mask Transaction Error + * 1'b1: No Transaction Error Mask + */ +#define USB_H_XACTERRMSK3 (BIT(7)) +#define USB_H_XACTERRMSK3_M (USB_H_XACTERRMSK3_V << USB_H_XACTERRMSK3_S) +#define USB_H_XACTERRMSK3_V 0x00000001 +#define USB_H_XACTERRMSK3_S 7 +/** USB_H_BBLERRMSK3 : R/W; bitpos: [8]; default: 0; + * Babble Error Mask + * 1'b0: Mask Babble Error + * 1'b1: No Babble Error Mask + */ +#define USB_H_BBLERRMSK3 (BIT(8)) +#define USB_H_BBLERRMSK3_M (USB_H_BBLERRMSK3_V << USB_H_BBLERRMSK3_S) +#define USB_H_BBLERRMSK3_V 0x00000001 +#define USB_H_BBLERRMSK3_S 8 +/** USB_H_FRMOVRUNMSK3 : R/W; bitpos: [9]; default: 0; + * Frame Overrun Mask + * 0x0 (MASK): Mask Overrun Mask + * 0x1 (NOMASK): No Frame Overrun Mask + */ +#define USB_H_FRMOVRUNMSK3 (BIT(9)) +#define USB_H_FRMOVRUNMSK3_M (USB_H_FRMOVRUNMSK3_V << USB_H_FRMOVRUNMSK3_S) +#define USB_H_FRMOVRUNMSK3_V 0x00000001 +#define USB_H_FRMOVRUNMSK3_S 9 +/** USB_H_DATATGLERRMSK3 : R/W; bitpos: [10]; default: 0; + * Data Toggle Error Mask n scatter/gather DMA mode for host + * 1'b0: Mask Data Toggle Error + * 1'b1: No Data Toggle Error Mask + */ +#define USB_H_DATATGLERRMSK3 (BIT(10)) +#define USB_H_DATATGLERRMSK3_M (USB_H_DATATGLERRMSK3_V << USB_H_DATATGLERRMSK3_S) +#define USB_H_DATATGLERRMSK3_V 0x00000001 +#define USB_H_DATATGLERRMSK3_S 10 +/** USB_H_BNAINTRMSK3 : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt mask register + * 1'b0: BNA Interrupt Masked + * 1'b1: BNA Interrupt not masked + */ +#define USB_H_BNAINTRMSK3 (BIT(11)) +#define USB_H_BNAINTRMSK3_M (USB_H_BNAINTRMSK3_V << USB_H_BNAINTRMSK3_S) +#define USB_H_BNAINTRMSK3_V 0x00000001 +#define USB_H_BNAINTRMSK3_S 11 +/** USB_H_DESC_LST_ROLLINTRMSK3 : R/W; bitpos: [13]; default: 0; + * Descriptor List rollover interrupt Mask + * 1'b0: Descriptor Rollover Interrupt Mask + * 1'b1: Descriptor Rollover Interrupt not masked + */ +#define USB_H_DESC_LST_ROLLINTRMSK3 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTRMSK3_M (USB_H_DESC_LST_ROLLINTRMSK3_V << USB_H_DESC_LST_ROLLINTRMSK3_S) +#define USB_H_DESC_LST_ROLLINTRMSK3_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTRMSK3_S 13 + + +/** USB_HCINT4_REG register + * Host Channel 4 Interrupt Register + */ +#define USB_HCINT4_REG (SOC_DPORT_USB_BASE + 0x588) +/** USB_H_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0; + * 1'b0: Transfer in progress or No Active Transfer + * 1'b1: Transfer completed normally without any errors + */ +#define USB_H_XFERCOMPL4 (BIT(0)) +#define USB_H_XFERCOMPL4_M (USB_H_XFERCOMPL4_V << USB_H_XFERCOMPL4_S) +#define USB_H_XFERCOMPL4_V 0x00000001 +#define USB_H_XFERCOMPL4_S 0 +/** USB_H_CHHLTD4 : R/W1C; bitpos: [1]; default: 0; + * 1'b0: Channel not halted + * 1'b1: Channel Halted + */ +#define USB_H_CHHLTD4 (BIT(1)) +#define USB_H_CHHLTD4_M (USB_H_CHHLTD4_V << USB_H_CHHLTD4_S) +#define USB_H_CHHLTD4_V 0x00000001 +#define USB_H_CHHLTD4_S 1 +/** USB_H_AHBERR4 : R/W1C; bitpos: [2]; default: 0; + * 1'b0: No AHB error + * 1'b1: AHB error during AHB read/write + */ +#define USB_H_AHBERR4 (BIT(2)) +#define USB_H_AHBERR4_M (USB_H_AHBERR4_V << USB_H_AHBERR4_S) +#define USB_H_AHBERR4_V 0x00000001 +#define USB_H_AHBERR4_S 2 +/** USB_H_STALL4 : R/W1C; bitpos: [3]; default: 0; + * 1'b0: No Stall Response Received Interrupt + * 1'b1: Stall Response Received Interrupt + */ +#define USB_H_STALL4 (BIT(3)) +#define USB_H_STALL4_M (USB_H_STALL4_V << USB_H_STALL4_S) +#define USB_H_STALL4_V 0x00000001 +#define USB_H_STALL4_S 3 +/** USB_H_NACK4 : R/W1C; bitpos: [4]; default: 0; + * 1'b0: No NAK Response Received Interrupt + * 1'b1: NAK Response Received Interrupt + */ +#define USB_H_NACK4 (BIT(4)) +#define USB_H_NACK4_M (USB_H_NACK4_V << USB_H_NACK4_S) +#define USB_H_NACK4_V 0x00000001 +#define USB_H_NACK4_S 4 +/** USB_H_ACK4 : R/W1C; bitpos: [5]; default: 0; + * 1'b0: No ACK Response Received or Transmitted Interrupt + * 1'b1: ACK Response Received or Transmitted Interrup + */ +#define USB_H_ACK4 (BIT(5)) +#define USB_H_ACK4_M (USB_H_ACK4_V << USB_H_ACK4_S) +#define USB_H_ACK4_V 0x00000001 +#define USB_H_ACK4_S 5 +/** USB_H_NYET4 : R/W1C; bitpos: [6]; default: 0; + * 1'b0: No NYET Response Received Interrupt + * 1'b1: NYET Response Received Interrupt + */ +#define USB_H_NYET4 (BIT(6)) +#define USB_H_NYET4_M (USB_H_NYET4_V << USB_H_NYET4_S) +#define USB_H_NYET4_V 0x00000001 +#define USB_H_NYET4_S 6 +/** USB_H_XACTERR4 : R/W1C; bitpos: [7]; default: 0; + * Indicates one of the following errors occurred on the USB: + * CRC check failure + * Timeout + * Bit stuff error + * False EOP + */ +#define USB_H_XACTERR4 (BIT(7)) +#define USB_H_XACTERR4_M (USB_H_XACTERR4_V << USB_H_XACTERR4_S) +#define USB_H_XACTERR4_V 0x00000001 +#define USB_H_XACTERR4_S 7 +/** USB_H_BBLERR4 : R/W1C; bitpos: [8]; default: 0; + * 1'b0: No Babble Error + * 1'b1: Babble Error + */ +#define USB_H_BBLERR4 (BIT(8)) +#define USB_H_BBLERR4_M (USB_H_BBLERR4_V << USB_H_BBLERR4_S) +#define USB_H_BBLERR4_V 0x00000001 +#define USB_H_BBLERR4_S 8 +/** USB_H_FRMOVRUN4 : R/W1C; bitpos: [9]; default: 0; + * 1'b0: No Frame Overrun + * 1'b1: Frame Overrun + */ +#define USB_H_FRMOVRUN4 (BIT(9)) +#define USB_H_FRMOVRUN4_M (USB_H_FRMOVRUN4_V << USB_H_FRMOVRUN4_S) +#define USB_H_FRMOVRUN4_V 0x00000001 +#define USB_H_FRMOVRUN4_S 9 +/** USB_H_DATATGLERR4 : R/W1C; bitpos: [10]; default: 0; + * 1'b0: No Data Toggle Error + * 1'b1: Data Toggle Error + */ +#define USB_H_DATATGLERR4 (BIT(10)) +#define USB_H_DATATGLERR4_M (USB_H_DATATGLERR4_V << USB_H_DATATGLERR4_S) +#define USB_H_DATATGLERR4_V 0x00000001 +#define USB_H_DATATGLERR4_S 10 +/** USB_H_BNAINTR4 : R/W1C; bitpos: [11]; default: 0; + * 1'b0: No BNA Interrupt + * 1'b1: BNA Interrupt + */ +#define USB_H_BNAINTR4 (BIT(11)) +#define USB_H_BNAINTR4_M (USB_H_BNAINTR4_V << USB_H_BNAINTR4_S) +#define USB_H_BNAINTR4_V 0x00000001 +#define USB_H_BNAINTR4_S 11 +/** USB_H_XCS_XACT_ERR4 : R/W1C; bitpos: [12]; default: 0; + * 1'b0: No Excessive Transaction Error + * 1'b1: Excessive Transaction Error + */ +#define USB_H_XCS_XACT_ERR4 (BIT(12)) +#define USB_H_XCS_XACT_ERR4_M (USB_H_XCS_XACT_ERR4_V << USB_H_XCS_XACT_ERR4_S) +#define USB_H_XCS_XACT_ERR4_V 0x00000001 +#define USB_H_XCS_XACT_ERR4_S 12 +/** USB_H_DESC_LST_ROLLINTR4 : R/W1C; bitpos: [13]; default: 0; + * 1'b0: No Descriptor rollover interrupt + * 1'b1: Descriptor rollover interrupt + */ +#define USB_H_DESC_LST_ROLLINTR4 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTR4_M (USB_H_DESC_LST_ROLLINTR4_V << USB_H_DESC_LST_ROLLINTR4_S) +#define USB_H_DESC_LST_ROLLINTR4_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTR4_S 13 + + +/** USB_HCINTMSK4_REG register + * Host Channel 4 Interrupt Mask Register + */ +#define USB_HCINTMSK4_REG (SOC_DPORT_USB_BASE + 0x58c) +/** USB_H_XFERCOMPLMSK4 : R/W; bitpos: [0]; default: 0; + * 1'b0: Transfer Completed Mask + * 1'b1: No Transfer Completed Mask + */ +#define USB_H_XFERCOMPLMSK4 (BIT(0)) +#define USB_H_XFERCOMPLMSK4_M (USB_H_XFERCOMPLMSK4_V << USB_H_XFERCOMPLMSK4_S) +#define USB_H_XFERCOMPLMSK4_V 0x00000001 +#define USB_H_XFERCOMPLMSK4_S 0 +/** USB_H_CHHLTDMSK4 : R/W; bitpos: [1]; default: 0; + * 1'b0: Channel Halted Mask + * 1'b1: No Channel Halted Mask + */ +#define USB_H_CHHLTDMSK4 (BIT(1)) +#define USB_H_CHHLTDMSK4_M (USB_H_CHHLTDMSK4_V << USB_H_CHHLTDMSK4_S) +#define USB_H_CHHLTDMSK4_V 0x00000001 +#define USB_H_CHHLTDMSK4_S 1 +/** USB_H_AHBERRMSK4 : R/W; bitpos: [2]; default: 0; + * 1'b0: AHB Error Mask + * 1'b1: No AHB Error Mask + */ +#define USB_H_AHBERRMSK4 (BIT(2)) +#define USB_H_AHBERRMSK4_M (USB_H_AHBERRMSK4_V << USB_H_AHBERRMSK4_S) +#define USB_H_AHBERRMSK4_V 0x00000001 +#define USB_H_AHBERRMSK4_S 2 +/** USB_H_STALLMSK4 : R/W; bitpos: [3]; default: 0; + * 1'b0: Mask STALL Response Received Interrupt + * 1'b1: No STALL Response Received Interrupt Mask + */ +#define USB_H_STALLMSK4 (BIT(3)) +#define USB_H_STALLMSK4_M (USB_H_STALLMSK4_V << USB_H_STALLMSK4_S) +#define USB_H_STALLMSK4_V 0x00000001 +#define USB_H_STALLMSK4_S 3 +/** USB_H_NAKMSK4 : R/W; bitpos: [4]; default: 0; + * 1'b0: Mask NAK Response Received Interrupt + * 1'b1: No NAK Response Received Interrupt Mask + */ +#define USB_H_NAKMSK4 (BIT(4)) +#define USB_H_NAKMSK4_M (USB_H_NAKMSK4_V << USB_H_NAKMSK4_S) +#define USB_H_NAKMSK4_V 0x00000001 +#define USB_H_NAKMSK4_S 4 +/** USB_H_ACKMSK4 : R/W; bitpos: [5]; default: 0; + * 1'b0: Mask ACK Response Received/Transmitted Interrupt + * 1'b1: No ACK Response Received/Transmitted Interrupt Mask + */ +#define USB_H_ACKMSK4 (BIT(5)) +#define USB_H_ACKMSK4_M (USB_H_ACKMSK4_V << USB_H_ACKMSK4_S) +#define USB_H_ACKMSK4_V 0x00000001 +#define USB_H_ACKMSK4_S 5 +/** USB_H_NYETMSK4 : R/W; bitpos: [6]; default: 0; + * 1'b0: Mask NYET Response Received Interrupt + * 1'b1: No NYET Response Received Interrupt Mask + */ +#define USB_H_NYETMSK4 (BIT(6)) +#define USB_H_NYETMSK4_M (USB_H_NYETMSK4_V << USB_H_NYETMSK4_S) +#define USB_H_NYETMSK4_V 0x00000001 +#define USB_H_NYETMSK4_S 6 +/** USB_H_XACTERRMSK4 : R/W; bitpos: [7]; default: 0; + * 1'b0: Mask Transaction Error + * 1'b1: No Transaction Error Mask + */ +#define USB_H_XACTERRMSK4 (BIT(7)) +#define USB_H_XACTERRMSK4_M (USB_H_XACTERRMSK4_V << USB_H_XACTERRMSK4_S) +#define USB_H_XACTERRMSK4_V 0x00000001 +#define USB_H_XACTERRMSK4_S 7 +/** USB_H_BBLERRMSK4 : R/W; bitpos: [8]; default: 0; + * Babble Error Mask + * 1'b0: Mask Babble Error + * 1'b1: No Babble Error Mask + */ +#define USB_H_BBLERRMSK4 (BIT(8)) +#define USB_H_BBLERRMSK4_M (USB_H_BBLERRMSK4_V << USB_H_BBLERRMSK4_S) +#define USB_H_BBLERRMSK4_V 0x00000001 +#define USB_H_BBLERRMSK4_S 8 +/** USB_H_FRMOVRUNMSK4 : R/W; bitpos: [9]; default: 0; + * Frame Overrun Mask + * 0x0 (MASK): Mask Overrun Mask + * 0x1 (NOMASK): No Frame Overrun Mask + */ +#define USB_H_FRMOVRUNMSK4 (BIT(9)) +#define USB_H_FRMOVRUNMSK4_M (USB_H_FRMOVRUNMSK4_V << USB_H_FRMOVRUNMSK4_S) +#define USB_H_FRMOVRUNMSK4_V 0x00000001 +#define USB_H_FRMOVRUNMSK4_S 9 +/** USB_H_DATATGLERRMSK4 : R/W; bitpos: [10]; default: 0; + * Data Toggle Error Mask n scatter/gather DMA mode for host + * 1'b0: Mask Data Toggle Error + * 1'b1: No Data Toggle Error Mask + */ +#define USB_H_DATATGLERRMSK4 (BIT(10)) +#define USB_H_DATATGLERRMSK4_M (USB_H_DATATGLERRMSK4_V << USB_H_DATATGLERRMSK4_S) +#define USB_H_DATATGLERRMSK4_V 0x00000001 +#define USB_H_DATATGLERRMSK4_S 10 +/** USB_H_BNAINTRMSK4 : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt mask register + * 1'b0: BNA Interrupt Masked + * 1'b1: BNA Interrupt not masked + */ +#define USB_H_BNAINTRMSK4 (BIT(11)) +#define USB_H_BNAINTRMSK4_M (USB_H_BNAINTRMSK4_V << USB_H_BNAINTRMSK4_S) +#define USB_H_BNAINTRMSK4_V 0x00000001 +#define USB_H_BNAINTRMSK4_S 11 +/** USB_H_DESC_LST_ROLLINTRMSK4 : R/W; bitpos: [13]; default: 0; + * Descriptor List rollover interrupt Mask + * 1'b0: Descriptor Rollover Interrupt Mask + * 1'b1: Descriptor Rollover Interrupt not masked + */ +#define USB_H_DESC_LST_ROLLINTRMSK4 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTRMSK4_M (USB_H_DESC_LST_ROLLINTRMSK4_V << USB_H_DESC_LST_ROLLINTRMSK4_S) +#define USB_H_DESC_LST_ROLLINTRMSK4_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTRMSK4_S 13 + + +/** USB_HCINT5_REG register + * Host Channel 5 Interrupt Register + */ +#define USB_HCINT5_REG (SOC_DPORT_USB_BASE + 0x5a8) +/** USB_H_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0; + * 1'b0: Transfer in progress or No Active Transfer + * 1'b1: Transfer completed normally without any errors + */ +#define USB_H_XFERCOMPL5 (BIT(0)) +#define USB_H_XFERCOMPL5_M (USB_H_XFERCOMPL5_V << USB_H_XFERCOMPL5_S) +#define USB_H_XFERCOMPL5_V 0x00000001 +#define USB_H_XFERCOMPL5_S 0 +/** USB_H_CHHLTD5 : R/W1C; bitpos: [1]; default: 0; + * 1'b0: Channel not halted + * 1'b1: Channel Halted + */ +#define USB_H_CHHLTD5 (BIT(1)) +#define USB_H_CHHLTD5_M (USB_H_CHHLTD5_V << USB_H_CHHLTD5_S) +#define USB_H_CHHLTD5_V 0x00000001 +#define USB_H_CHHLTD5_S 1 +/** USB_H_AHBERR5 : R/W1C; bitpos: [2]; default: 0; + * 1'b0: No AHB error + * 1'b1: AHB error during AHB read/write + */ +#define USB_H_AHBERR5 (BIT(2)) +#define USB_H_AHBERR5_M (USB_H_AHBERR5_V << USB_H_AHBERR5_S) +#define USB_H_AHBERR5_V 0x00000001 +#define USB_H_AHBERR5_S 2 +/** USB_H_STALL5 : R/W1C; bitpos: [3]; default: 0; + * 1'b0: No Stall Response Received Interrupt + * 1'b1: Stall Response Received Interrupt + */ +#define USB_H_STALL5 (BIT(3)) +#define USB_H_STALL5_M (USB_H_STALL5_V << USB_H_STALL5_S) +#define USB_H_STALL5_V 0x00000001 +#define USB_H_STALL5_S 3 +/** USB_H_NACK5 : R/W1C; bitpos: [4]; default: 0; + * 1'b0: No NAK Response Received Interrupt + * 1'b1: NAK Response Received Interrupt + */ +#define USB_H_NACK5 (BIT(4)) +#define USB_H_NACK5_M (USB_H_NACK5_V << USB_H_NACK5_S) +#define USB_H_NACK5_V 0x00000001 +#define USB_H_NACK5_S 4 +/** USB_H_ACK5 : R/W1C; bitpos: [5]; default: 0; + * 1'b0: No ACK Response Received or Transmitted Interrupt + * 1'b1: ACK Response Received or Transmitted Interrup + */ +#define USB_H_ACK5 (BIT(5)) +#define USB_H_ACK5_M (USB_H_ACK5_V << USB_H_ACK5_S) +#define USB_H_ACK5_V 0x00000001 +#define USB_H_ACK5_S 5 +/** USB_H_NYET5 : R/W1C; bitpos: [6]; default: 0; + * 1'b0: No NYET Response Received Interrupt + * 1'b1: NYET Response Received Interrupt + */ +#define USB_H_NYET5 (BIT(6)) +#define USB_H_NYET5_M (USB_H_NYET5_V << USB_H_NYET5_S) +#define USB_H_NYET5_V 0x00000001 +#define USB_H_NYET5_S 6 +/** USB_H_XACTERR5 : R/W1C; bitpos: [7]; default: 0; + * Indicates one of the following errors occurred on the USB: + * CRC check failure + * Timeout + * Bit stuff error + * False EOP + */ +#define USB_H_XACTERR5 (BIT(7)) +#define USB_H_XACTERR5_M (USB_H_XACTERR5_V << USB_H_XACTERR5_S) +#define USB_H_XACTERR5_V 0x00000001 +#define USB_H_XACTERR5_S 7 +/** USB_H_BBLERR5 : R/W1C; bitpos: [8]; default: 0; + * 1'b0: No Babble Error + * 1'b1: Babble Error + */ +#define USB_H_BBLERR5 (BIT(8)) +#define USB_H_BBLERR5_M (USB_H_BBLERR5_V << USB_H_BBLERR5_S) +#define USB_H_BBLERR5_V 0x00000001 +#define USB_H_BBLERR5_S 8 +/** USB_H_FRMOVRUN5 : R/W1C; bitpos: [9]; default: 0; + * 1'b0: No Frame Overrun + * 1'b1: Frame Overrun + */ +#define USB_H_FRMOVRUN5 (BIT(9)) +#define USB_H_FRMOVRUN5_M (USB_H_FRMOVRUN5_V << USB_H_FRMOVRUN5_S) +#define USB_H_FRMOVRUN5_V 0x00000001 +#define USB_H_FRMOVRUN5_S 9 +/** USB_H_DATATGLERR5 : R/W1C; bitpos: [10]; default: 0; + * 1'b0: No Data Toggle Error + * 1'b1: Data Toggle Error + */ +#define USB_H_DATATGLERR5 (BIT(10)) +#define USB_H_DATATGLERR5_M (USB_H_DATATGLERR5_V << USB_H_DATATGLERR5_S) +#define USB_H_DATATGLERR5_V 0x00000001 +#define USB_H_DATATGLERR5_S 10 +/** USB_H_BNAINTR5 : R/W1C; bitpos: [11]; default: 0; + * 1'b0: No BNA Interrupt + * 1'b1: BNA Interrupt + */ +#define USB_H_BNAINTR5 (BIT(11)) +#define USB_H_BNAINTR5_M (USB_H_BNAINTR5_V << USB_H_BNAINTR5_S) +#define USB_H_BNAINTR5_V 0x00000001 +#define USB_H_BNAINTR5_S 11 +/** USB_H_XCS_XACT_ERR5 : R/W1C; bitpos: [12]; default: 0; + * 1'b0: No Excessive Transaction Error + * 1'b1: Excessive Transaction Error + */ +#define USB_H_XCS_XACT_ERR5 (BIT(12)) +#define USB_H_XCS_XACT_ERR5_M (USB_H_XCS_XACT_ERR5_V << USB_H_XCS_XACT_ERR5_S) +#define USB_H_XCS_XACT_ERR5_V 0x00000001 +#define USB_H_XCS_XACT_ERR5_S 12 +/** USB_H_DESC_LST_ROLLINTR5 : R/W1C; bitpos: [13]; default: 0; + * 1'b0: No Descriptor rollover interrupt + * 1'b1: Descriptor rollover interrupt + */ +#define USB_H_DESC_LST_ROLLINTR5 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTR5_M (USB_H_DESC_LST_ROLLINTR5_V << USB_H_DESC_LST_ROLLINTR5_S) +#define USB_H_DESC_LST_ROLLINTR5_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTR5_S 13 + + +/** USB_HCINTMSK5_REG register + * Host Channel 5 Interrupt Mask Register + */ +#define USB_HCINTMSK5_REG (SOC_DPORT_USB_BASE + 0x5ac) +/** USB_H_XFERCOMPLMSK5 : R/W; bitpos: [0]; default: 0; + * 1'b0: Transfer Completed Mask + * 1'b1: No Transfer Completed Mask + */ +#define USB_H_XFERCOMPLMSK5 (BIT(0)) +#define USB_H_XFERCOMPLMSK5_M (USB_H_XFERCOMPLMSK5_V << USB_H_XFERCOMPLMSK5_S) +#define USB_H_XFERCOMPLMSK5_V 0x00000001 +#define USB_H_XFERCOMPLMSK5_S 0 +/** USB_H_CHHLTDMSK5 : R/W; bitpos: [1]; default: 0; + * 1'b0: Channel Halted Mask + * 1'b1: No Channel Halted Mask + */ +#define USB_H_CHHLTDMSK5 (BIT(1)) +#define USB_H_CHHLTDMSK5_M (USB_H_CHHLTDMSK5_V << USB_H_CHHLTDMSK5_S) +#define USB_H_CHHLTDMSK5_V 0x00000001 +#define USB_H_CHHLTDMSK5_S 1 +/** USB_H_AHBERRMSK5 : R/W; bitpos: [2]; default: 0; + * 1'b0: AHB Error Mask + * 1'b1: No AHB Error Mask + */ +#define USB_H_AHBERRMSK5 (BIT(2)) +#define USB_H_AHBERRMSK5_M (USB_H_AHBERRMSK5_V << USB_H_AHBERRMSK5_S) +#define USB_H_AHBERRMSK5_V 0x00000001 +#define USB_H_AHBERRMSK5_S 2 +/** USB_H_STALLMSK5 : R/W; bitpos: [3]; default: 0; + * 1'b0: Mask STALL Response Received Interrupt + * 1'b1: No STALL Response Received Interrupt Mask + */ +#define USB_H_STALLMSK5 (BIT(3)) +#define USB_H_STALLMSK5_M (USB_H_STALLMSK5_V << USB_H_STALLMSK5_S) +#define USB_H_STALLMSK5_V 0x00000001 +#define USB_H_STALLMSK5_S 3 +/** USB_H_NAKMSK5 : R/W; bitpos: [4]; default: 0; + * 1'b0: Mask NAK Response Received Interrupt + * 1'b1: No NAK Response Received Interrupt Mask + */ +#define USB_H_NAKMSK5 (BIT(4)) +#define USB_H_NAKMSK5_M (USB_H_NAKMSK5_V << USB_H_NAKMSK5_S) +#define USB_H_NAKMSK5_V 0x00000001 +#define USB_H_NAKMSK5_S 4 +/** USB_H_ACKMSK5 : R/W; bitpos: [5]; default: 0; + * 1'b0: Mask ACK Response Received/Transmitted Interrupt + * 1'b1: No ACK Response Received/Transmitted Interrupt Mask + */ +#define USB_H_ACKMSK5 (BIT(5)) +#define USB_H_ACKMSK5_M (USB_H_ACKMSK5_V << USB_H_ACKMSK5_S) +#define USB_H_ACKMSK5_V 0x00000001 +#define USB_H_ACKMSK5_S 5 +/** USB_H_NYETMSK5 : R/W; bitpos: [6]; default: 0; + * 1'b0: Mask NYET Response Received Interrupt + * 1'b1: No NYET Response Received Interrupt Mask + */ +#define USB_H_NYETMSK5 (BIT(6)) +#define USB_H_NYETMSK5_M (USB_H_NYETMSK5_V << USB_H_NYETMSK5_S) +#define USB_H_NYETMSK5_V 0x00000001 +#define USB_H_NYETMSK5_S 6 +/** USB_H_XACTERRMSK5 : R/W; bitpos: [7]; default: 0; + * 1'b0: Mask Transaction Error + * 1'b1: No Transaction Error Mask + */ +#define USB_H_XACTERRMSK5 (BIT(7)) +#define USB_H_XACTERRMSK5_M (USB_H_XACTERRMSK5_V << USB_H_XACTERRMSK5_S) +#define USB_H_XACTERRMSK5_V 0x00000001 +#define USB_H_XACTERRMSK5_S 7 +/** USB_H_BBLERRMSK5 : R/W; bitpos: [8]; default: 0; + * Babble Error Mask + * 1'b0: Mask Babble Error + * 1'b1: No Babble Error Mask + */ +#define USB_H_BBLERRMSK5 (BIT(8)) +#define USB_H_BBLERRMSK5_M (USB_H_BBLERRMSK5_V << USB_H_BBLERRMSK5_S) +#define USB_H_BBLERRMSK5_V 0x00000001 +#define USB_H_BBLERRMSK5_S 8 +/** USB_H_FRMOVRUNMSK5 : R/W; bitpos: [9]; default: 0; + * Frame Overrun Mask + * 0x0 (MASK): Mask Overrun Mask + * 0x1 (NOMASK): No Frame Overrun Mask + */ +#define USB_H_FRMOVRUNMSK5 (BIT(9)) +#define USB_H_FRMOVRUNMSK5_M (USB_H_FRMOVRUNMSK5_V << USB_H_FRMOVRUNMSK5_S) +#define USB_H_FRMOVRUNMSK5_V 0x00000001 +#define USB_H_FRMOVRUNMSK5_S 9 +/** USB_H_DATATGLERRMSK5 : R/W; bitpos: [10]; default: 0; + * Data Toggle Error Mask n scatter/gather DMA mode for host + * 1'b0: Mask Data Toggle Error + * 1'b1: No Data Toggle Error Mask + */ +#define USB_H_DATATGLERRMSK5 (BIT(10)) +#define USB_H_DATATGLERRMSK5_M (USB_H_DATATGLERRMSK5_V << USB_H_DATATGLERRMSK5_S) +#define USB_H_DATATGLERRMSK5_V 0x00000001 +#define USB_H_DATATGLERRMSK5_S 10 +/** USB_H_BNAINTRMSK5 : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt mask register + * 1'b0: BNA Interrupt Masked + * 1'b1: BNA Interrupt not masked + */ +#define USB_H_BNAINTRMSK5 (BIT(11)) +#define USB_H_BNAINTRMSK5_M (USB_H_BNAINTRMSK5_V << USB_H_BNAINTRMSK5_S) +#define USB_H_BNAINTRMSK5_V 0x00000001 +#define USB_H_BNAINTRMSK5_S 11 +/** USB_H_DESC_LST_ROLLINTRMSK5 : R/W; bitpos: [13]; default: 0; + * Descriptor List rollover interrupt Mask + * 1'b0: Descriptor Rollover Interrupt Mask + * 1'b1: Descriptor Rollover Interrupt not masked + */ +#define USB_H_DESC_LST_ROLLINTRMSK5 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTRMSK5_M (USB_H_DESC_LST_ROLLINTRMSK5_V << USB_H_DESC_LST_ROLLINTRMSK5_S) +#define USB_H_DESC_LST_ROLLINTRMSK5_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTRMSK5_S 13 + + +/** USB_HCINT6_REG register + * Host Channel 6 Interrupt Register + */ +#define USB_HCINT6_REG (SOC_DPORT_USB_BASE + 0x5c8) +/** USB_H_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0; + * 1'b0: Transfer in progress or No Active Transfer + * 1'b1: Transfer completed normally without any errors + */ +#define USB_H_XFERCOMPL6 (BIT(0)) +#define USB_H_XFERCOMPL6_M (USB_H_XFERCOMPL6_V << USB_H_XFERCOMPL6_S) +#define USB_H_XFERCOMPL6_V 0x00000001 +#define USB_H_XFERCOMPL6_S 0 +/** USB_H_CHHLTD6 : R/W1C; bitpos: [1]; default: 0; + * 1'b0: Channel not halted + * 1'b1: Channel Halted + */ +#define USB_H_CHHLTD6 (BIT(1)) +#define USB_H_CHHLTD6_M (USB_H_CHHLTD6_V << USB_H_CHHLTD6_S) +#define USB_H_CHHLTD6_V 0x00000001 +#define USB_H_CHHLTD6_S 1 +/** USB_H_AHBERR6 : R/W1C; bitpos: [2]; default: 0; + * 1'b0: No AHB error + * 1'b1: AHB error during AHB read/write + */ +#define USB_H_AHBERR6 (BIT(2)) +#define USB_H_AHBERR6_M (USB_H_AHBERR6_V << USB_H_AHBERR6_S) +#define USB_H_AHBERR6_V 0x00000001 +#define USB_H_AHBERR6_S 2 +/** USB_H_STALL6 : R/W1C; bitpos: [3]; default: 0; + * 1'b0: No Stall Response Received Interrupt + * 1'b1: Stall Response Received Interrupt + */ +#define USB_H_STALL6 (BIT(3)) +#define USB_H_STALL6_M (USB_H_STALL6_V << USB_H_STALL6_S) +#define USB_H_STALL6_V 0x00000001 +#define USB_H_STALL6_S 3 +/** USB_H_NACK6 : R/W1C; bitpos: [4]; default: 0; + * 1'b0: No NAK Response Received Interrupt + * 1'b1: NAK Response Received Interrupt + */ +#define USB_H_NACK6 (BIT(4)) +#define USB_H_NACK6_M (USB_H_NACK6_V << USB_H_NACK6_S) +#define USB_H_NACK6_V 0x00000001 +#define USB_H_NACK6_S 4 +/** USB_H_ACK6 : R/W1C; bitpos: [5]; default: 0; + * 1'b0: No ACK Response Received or Transmitted Interrupt + * 1'b1: ACK Response Received or Transmitted Interrup + */ +#define USB_H_ACK6 (BIT(5)) +#define USB_H_ACK6_M (USB_H_ACK6_V << USB_H_ACK6_S) +#define USB_H_ACK6_V 0x00000001 +#define USB_H_ACK6_S 5 +/** USB_H_NYET6 : R/W1C; bitpos: [6]; default: 0; + * 1'b0: No NYET Response Received Interrupt + * 1'b1: NYET Response Received Interrupt + */ +#define USB_H_NYET6 (BIT(6)) +#define USB_H_NYET6_M (USB_H_NYET6_V << USB_H_NYET6_S) +#define USB_H_NYET6_V 0x00000001 +#define USB_H_NYET6_S 6 +/** USB_H_XACTERR6 : R/W1C; bitpos: [7]; default: 0; + * Indicates one of the following errors occurred on the USB: + * CRC check failure + * Timeout + * Bit stuff error + * False EOP + */ +#define USB_H_XACTERR6 (BIT(7)) +#define USB_H_XACTERR6_M (USB_H_XACTERR6_V << USB_H_XACTERR6_S) +#define USB_H_XACTERR6_V 0x00000001 +#define USB_H_XACTERR6_S 7 +/** USB_H_BBLERR6 : R/W1C; bitpos: [8]; default: 0; + * 1'b0: No Babble Error + * 1'b1: Babble Error + */ +#define USB_H_BBLERR6 (BIT(8)) +#define USB_H_BBLERR6_M (USB_H_BBLERR6_V << USB_H_BBLERR6_S) +#define USB_H_BBLERR6_V 0x00000001 +#define USB_H_BBLERR6_S 8 +/** USB_H_FRMOVRUN6 : R/W1C; bitpos: [9]; default: 0; + * 1'b0: No Frame Overrun + * 1'b1: Frame Overrun + */ +#define USB_H_FRMOVRUN6 (BIT(9)) +#define USB_H_FRMOVRUN6_M (USB_H_FRMOVRUN6_V << USB_H_FRMOVRUN6_S) +#define USB_H_FRMOVRUN6_V 0x00000001 +#define USB_H_FRMOVRUN6_S 9 +/** USB_H_DATATGLERR6 : R/W1C; bitpos: [10]; default: 0; + * 1'b0: No Data Toggle Error + * 1'b1: Data Toggle Error + */ +#define USB_H_DATATGLERR6 (BIT(10)) +#define USB_H_DATATGLERR6_M (USB_H_DATATGLERR6_V << USB_H_DATATGLERR6_S) +#define USB_H_DATATGLERR6_V 0x00000001 +#define USB_H_DATATGLERR6_S 10 +/** USB_H_BNAINTR6 : R/W1C; bitpos: [11]; default: 0; + * 1'b0: No BNA Interrupt + * 1'b1: BNA Interrupt + */ +#define USB_H_BNAINTR6 (BIT(11)) +#define USB_H_BNAINTR6_M (USB_H_BNAINTR6_V << USB_H_BNAINTR6_S) +#define USB_H_BNAINTR6_V 0x00000001 +#define USB_H_BNAINTR6_S 11 +/** USB_H_XCS_XACT_ERR6 : R/W1C; bitpos: [12]; default: 0; + * 1'b0: No Excessive Transaction Error + * 1'b1: Excessive Transaction Error + */ +#define USB_H_XCS_XACT_ERR6 (BIT(12)) +#define USB_H_XCS_XACT_ERR6_M (USB_H_XCS_XACT_ERR6_V << USB_H_XCS_XACT_ERR6_S) +#define USB_H_XCS_XACT_ERR6_V 0x00000001 +#define USB_H_XCS_XACT_ERR6_S 12 +/** USB_H_DESC_LST_ROLLINTR6 : R/W1C; bitpos: [13]; default: 0; + * 1'b0: No Descriptor rollover interrupt + * 1'b1: Descriptor rollover interrupt + */ +#define USB_H_DESC_LST_ROLLINTR6 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTR6_M (USB_H_DESC_LST_ROLLINTR6_V << USB_H_DESC_LST_ROLLINTR6_S) +#define USB_H_DESC_LST_ROLLINTR6_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTR6_S 13 + + +/** USB_HCINTMSK6_REG register + * Host Channel 6 Interrupt Mask Register + */ +#define USB_HCINTMSK6_REG (SOC_DPORT_USB_BASE + 0x5cc) +/** USB_H_XFERCOMPLMSK6 : R/W; bitpos: [0]; default: 0; + * 1'b0: Transfer Completed Mask + * 1'b1: No Transfer Completed Mask + */ +#define USB_H_XFERCOMPLMSK6 (BIT(0)) +#define USB_H_XFERCOMPLMSK6_M (USB_H_XFERCOMPLMSK6_V << USB_H_XFERCOMPLMSK6_S) +#define USB_H_XFERCOMPLMSK6_V 0x00000001 +#define USB_H_XFERCOMPLMSK6_S 0 +/** USB_H_CHHLTDMSK6 : R/W; bitpos: [1]; default: 0; + * 1'b0: Channel Halted Mask + * 1'b1: No Channel Halted Mask + */ +#define USB_H_CHHLTDMSK6 (BIT(1)) +#define USB_H_CHHLTDMSK6_M (USB_H_CHHLTDMSK6_V << USB_H_CHHLTDMSK6_S) +#define USB_H_CHHLTDMSK6_V 0x00000001 +#define USB_H_CHHLTDMSK6_S 1 +/** USB_H_AHBERRMSK6 : R/W; bitpos: [2]; default: 0; + * 1'b0: AHB Error Mask + * 1'b1: No AHB Error Mask + */ +#define USB_H_AHBERRMSK6 (BIT(2)) +#define USB_H_AHBERRMSK6_M (USB_H_AHBERRMSK6_V << USB_H_AHBERRMSK6_S) +#define USB_H_AHBERRMSK6_V 0x00000001 +#define USB_H_AHBERRMSK6_S 2 +/** USB_H_STALLMSK6 : R/W; bitpos: [3]; default: 0; + * 1'b0: Mask STALL Response Received Interrupt + * 1'b1: No STALL Response Received Interrupt Mask + */ +#define USB_H_STALLMSK6 (BIT(3)) +#define USB_H_STALLMSK6_M (USB_H_STALLMSK6_V << USB_H_STALLMSK6_S) +#define USB_H_STALLMSK6_V 0x00000001 +#define USB_H_STALLMSK6_S 3 +/** USB_H_NAKMSK6 : R/W; bitpos: [4]; default: 0; + * 1'b0: Mask NAK Response Received Interrupt + * 1'b1: No NAK Response Received Interrupt Mask + */ +#define USB_H_NAKMSK6 (BIT(4)) +#define USB_H_NAKMSK6_M (USB_H_NAKMSK6_V << USB_H_NAKMSK6_S) +#define USB_H_NAKMSK6_V 0x00000001 +#define USB_H_NAKMSK6_S 4 +/** USB_H_ACKMSK6 : R/W; bitpos: [5]; default: 0; + * 1'b0: Mask ACK Response Received/Transmitted Interrupt + * 1'b1: No ACK Response Received/Transmitted Interrupt Mask + */ +#define USB_H_ACKMSK6 (BIT(5)) +#define USB_H_ACKMSK6_M (USB_H_ACKMSK6_V << USB_H_ACKMSK6_S) +#define USB_H_ACKMSK6_V 0x00000001 +#define USB_H_ACKMSK6_S 5 +/** USB_H_NYETMSK6 : R/W; bitpos: [6]; default: 0; + * 1'b0: Mask NYET Response Received Interrupt + * 1'b1: No NYET Response Received Interrupt Mask + */ +#define USB_H_NYETMSK6 (BIT(6)) +#define USB_H_NYETMSK6_M (USB_H_NYETMSK6_V << USB_H_NYETMSK6_S) +#define USB_H_NYETMSK6_V 0x00000001 +#define USB_H_NYETMSK6_S 6 +/** USB_H_XACTERRMSK6 : R/W; bitpos: [7]; default: 0; + * 1'b0: Mask Transaction Error + * 1'b1: No Transaction Error Mask + */ +#define USB_H_XACTERRMSK6 (BIT(7)) +#define USB_H_XACTERRMSK6_M (USB_H_XACTERRMSK6_V << USB_H_XACTERRMSK6_S) +#define USB_H_XACTERRMSK6_V 0x00000001 +#define USB_H_XACTERRMSK6_S 7 +/** USB_H_BBLERRMSK6 : R/W; bitpos: [8]; default: 0; + * Babble Error Mask + * 1'b0: Mask Babble Error + * 1'b1: No Babble Error Mask + */ +#define USB_H_BBLERRMSK6 (BIT(8)) +#define USB_H_BBLERRMSK6_M (USB_H_BBLERRMSK6_V << USB_H_BBLERRMSK6_S) +#define USB_H_BBLERRMSK6_V 0x00000001 +#define USB_H_BBLERRMSK6_S 8 +/** USB_H_FRMOVRUNMSK6 : R/W; bitpos: [9]; default: 0; + * Frame Overrun Mask + * 0x0 (MASK): Mask Overrun Mask + * 0x1 (NOMASK): No Frame Overrun Mask + */ +#define USB_H_FRMOVRUNMSK6 (BIT(9)) +#define USB_H_FRMOVRUNMSK6_M (USB_H_FRMOVRUNMSK6_V << USB_H_FRMOVRUNMSK6_S) +#define USB_H_FRMOVRUNMSK6_V 0x00000001 +#define USB_H_FRMOVRUNMSK6_S 9 +/** USB_H_DATATGLERRMSK6 : R/W; bitpos: [10]; default: 0; + * Data Toggle Error Mask n scatter/gather DMA mode for host + * 1'b0: Mask Data Toggle Error + * 1'b1: No Data Toggle Error Mask + */ +#define USB_H_DATATGLERRMSK6 (BIT(10)) +#define USB_H_DATATGLERRMSK6_M (USB_H_DATATGLERRMSK6_V << USB_H_DATATGLERRMSK6_S) +#define USB_H_DATATGLERRMSK6_V 0x00000001 +#define USB_H_DATATGLERRMSK6_S 10 +/** USB_H_BNAINTRMSK6 : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt mask register + * 1'b0: BNA Interrupt Masked + * 1'b1: BNA Interrupt not masked + */ +#define USB_H_BNAINTRMSK6 (BIT(11)) +#define USB_H_BNAINTRMSK6_M (USB_H_BNAINTRMSK6_V << USB_H_BNAINTRMSK6_S) +#define USB_H_BNAINTRMSK6_V 0x00000001 +#define USB_H_BNAINTRMSK6_S 11 +/** USB_H_DESC_LST_ROLLINTRMSK6 : R/W; bitpos: [13]; default: 0; + * Descriptor List rollover interrupt Mask + * 1'b0: Descriptor Rollover Interrupt Mask + * 1'b1: Descriptor Rollover Interrupt not masked + */ +#define USB_H_DESC_LST_ROLLINTRMSK6 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTRMSK6_M (USB_H_DESC_LST_ROLLINTRMSK6_V << USB_H_DESC_LST_ROLLINTRMSK6_S) +#define USB_H_DESC_LST_ROLLINTRMSK6_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTRMSK6_S 13 + + +/** USB_HCINT7_REG register + * Host Channel 7 Interrupt Register + */ +#define USB_HCINT7_REG (SOC_DPORT_USB_BASE + 0x5e8) +/** USB_H_XFERCOMPL7 : R/W1C; bitpos: [0]; default: 0; + * 1'b0: Transfer in progress or No Active Transfer + * 1'b1: Transfer completed normally without any errors + */ +#define USB_H_XFERCOMPL7 (BIT(0)) +#define USB_H_XFERCOMPL7_M (USB_H_XFERCOMPL7_V << USB_H_XFERCOMPL7_S) +#define USB_H_XFERCOMPL7_V 0x00000001 +#define USB_H_XFERCOMPL7_S 0 +/** USB_H_CHHLTD7 : R/W1C; bitpos: [1]; default: 0; + * 1'b0: Channel not halted + * 1'b1: Channel Halted + */ +#define USB_H_CHHLTD7 (BIT(1)) +#define USB_H_CHHLTD7_M (USB_H_CHHLTD7_V << USB_H_CHHLTD7_S) +#define USB_H_CHHLTD7_V 0x00000001 +#define USB_H_CHHLTD7_S 1 +/** USB_H_AHBERR7 : R/W1C; bitpos: [2]; default: 0; + * 1'b0: No AHB error + * 1'b1: AHB error during AHB read/write + */ +#define USB_H_AHBERR7 (BIT(2)) +#define USB_H_AHBERR7_M (USB_H_AHBERR7_V << USB_H_AHBERR7_S) +#define USB_H_AHBERR7_V 0x00000001 +#define USB_H_AHBERR7_S 2 +/** USB_H_STALL7 : R/W1C; bitpos: [3]; default: 0; + * 1'b0: No Stall Response Received Interrupt + * 1'b1: Stall Response Received Interrupt + */ +#define USB_H_STALL7 (BIT(3)) +#define USB_H_STALL7_M (USB_H_STALL7_V << USB_H_STALL7_S) +#define USB_H_STALL7_V 0x00000001 +#define USB_H_STALL7_S 3 +/** USB_H_NACK7 : R/W1C; bitpos: [4]; default: 0; + * 1'b0: No NAK Response Received Interrupt + * 1'b1: NAK Response Received Interrupt + */ +#define USB_H_NACK7 (BIT(4)) +#define USB_H_NACK7_M (USB_H_NACK7_V << USB_H_NACK7_S) +#define USB_H_NACK7_V 0x00000001 +#define USB_H_NACK7_S 4 +/** USB_H_ACK7 : R/W1C; bitpos: [5]; default: 0; + * 1'b0: No ACK Response Received or Transmitted Interrupt + * 1'b1: ACK Response Received or Transmitted Interrup + */ +#define USB_H_ACK7 (BIT(5)) +#define USB_H_ACK7_M (USB_H_ACK7_V << USB_H_ACK7_S) +#define USB_H_ACK7_V 0x00000001 +#define USB_H_ACK7_S 5 +/** USB_H_NYET7 : R/W1C; bitpos: [6]; default: 0; + * 1'b0: No NYET Response Received Interrupt + * 1'b1: NYET Response Received Interrupt + */ +#define USB_H_NYET7 (BIT(6)) +#define USB_H_NYET7_M (USB_H_NYET7_V << USB_H_NYET7_S) +#define USB_H_NYET7_V 0x00000001 +#define USB_H_NYET7_S 6 +/** USB_H_XACTERR7 : R/W1C; bitpos: [7]; default: 0; + * Indicates one of the following errors occurred on the USB: + * CRC check failure + * Timeout + * Bit stuff error + * False EOP + */ +#define USB_H_XACTERR7 (BIT(7)) +#define USB_H_XACTERR7_M (USB_H_XACTERR7_V << USB_H_XACTERR7_S) +#define USB_H_XACTERR7_V 0x00000001 +#define USB_H_XACTERR7_S 7 +/** USB_H_BBLERR7 : R/W1C; bitpos: [8]; default: 0; + * 1'b0: No Babble Error + * 1'b1: Babble Error + */ +#define USB_H_BBLERR7 (BIT(8)) +#define USB_H_BBLERR7_M (USB_H_BBLERR7_V << USB_H_BBLERR7_S) +#define USB_H_BBLERR7_V 0x00000001 +#define USB_H_BBLERR7_S 8 +/** USB_H_FRMOVRUN7 : R/W1C; bitpos: [9]; default: 0; + * 1'b0: No Frame Overrun + * 1'b1: Frame Overrun + */ +#define USB_H_FRMOVRUN7 (BIT(9)) +#define USB_H_FRMOVRUN7_M (USB_H_FRMOVRUN7_V << USB_H_FRMOVRUN7_S) +#define USB_H_FRMOVRUN7_V 0x00000001 +#define USB_H_FRMOVRUN7_S 9 +/** USB_H_DATATGLERR7 : R/W1C; bitpos: [10]; default: 0; + * 1'b0: No Data Toggle Error + * 1'b1: Data Toggle Error + */ +#define USB_H_DATATGLERR7 (BIT(10)) +#define USB_H_DATATGLERR7_M (USB_H_DATATGLERR7_V << USB_H_DATATGLERR7_S) +#define USB_H_DATATGLERR7_V 0x00000001 +#define USB_H_DATATGLERR7_S 10 +/** USB_H_BNAINTR7 : R/W1C; bitpos: [11]; default: 0; + * 1'b0: No BNA Interrupt + * 1'b1: BNA Interrupt + */ +#define USB_H_BNAINTR7 (BIT(11)) +#define USB_H_BNAINTR7_M (USB_H_BNAINTR7_V << USB_H_BNAINTR7_S) +#define USB_H_BNAINTR7_V 0x00000001 +#define USB_H_BNAINTR7_S 11 +/** USB_H_XCS_XACT_ERR7 : R/W1C; bitpos: [12]; default: 0; + * 1'b0: No Excessive Transaction Error + * 1'b1: Excessive Transaction Error + */ +#define USB_H_XCS_XACT_ERR7 (BIT(12)) +#define USB_H_XCS_XACT_ERR7_M (USB_H_XCS_XACT_ERR7_V << USB_H_XCS_XACT_ERR7_S) +#define USB_H_XCS_XACT_ERR7_V 0x00000001 +#define USB_H_XCS_XACT_ERR7_S 12 +/** USB_H_DESC_LST_ROLLINTR7 : R/W1C; bitpos: [13]; default: 0; + * 1'b0: No Descriptor rollover interrupt + * 1'b1: Descriptor rollover interrupt + */ +#define USB_H_DESC_LST_ROLLINTR7 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTR7_M (USB_H_DESC_LST_ROLLINTR7_V << USB_H_DESC_LST_ROLLINTR7_S) +#define USB_H_DESC_LST_ROLLINTR7_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTR7_S 13 + + +/** USB_HCINTMSK7_REG register + * Host Channel 7 Interrupt Mask Register + */ +#define USB_HCINTMSK7_REG (SOC_DPORT_USB_BASE + 0x5ec) +/** USB_H_XFERCOMPLMSK7 : R/W; bitpos: [0]; default: 0; + * 1'b0: Transfer Completed Mask + * 1'b1: No Transfer Completed Mask + */ +#define USB_H_XFERCOMPLMSK7 (BIT(0)) +#define USB_H_XFERCOMPLMSK7_M (USB_H_XFERCOMPLMSK7_V << USB_H_XFERCOMPLMSK7_S) +#define USB_H_XFERCOMPLMSK7_V 0x00000001 +#define USB_H_XFERCOMPLMSK7_S 0 +/** USB_H_CHHLTDMSK7 : R/W; bitpos: [1]; default: 0; + * 1'b0: Channel Halted Mask + * 1'b1: No Channel Halted Mask + */ +#define USB_H_CHHLTDMSK7 (BIT(1)) +#define USB_H_CHHLTDMSK7_M (USB_H_CHHLTDMSK7_V << USB_H_CHHLTDMSK7_S) +#define USB_H_CHHLTDMSK7_V 0x00000001 +#define USB_H_CHHLTDMSK7_S 1 +/** USB_H_AHBERRMSK7 : R/W; bitpos: [2]; default: 0; + * 1'b0: AHB Error Mask + * 1'b1: No AHB Error Mask + */ +#define USB_H_AHBERRMSK7 (BIT(2)) +#define USB_H_AHBERRMSK7_M (USB_H_AHBERRMSK7_V << USB_H_AHBERRMSK7_S) +#define USB_H_AHBERRMSK7_V 0x00000001 +#define USB_H_AHBERRMSK7_S 2 +/** USB_H_STALLMSK7 : R/W; bitpos: [3]; default: 0; + * 1'b0: Mask STALL Response Received Interrupt + * 1'b1: No STALL Response Received Interrupt Mask + */ +#define USB_H_STALLMSK7 (BIT(3)) +#define USB_H_STALLMSK7_M (USB_H_STALLMSK7_V << USB_H_STALLMSK7_S) +#define USB_H_STALLMSK7_V 0x00000001 +#define USB_H_STALLMSK7_S 3 +/** USB_H_NAKMSK7 : R/W; bitpos: [4]; default: 0; + * 1'b0: Mask NAK Response Received Interrupt + * 1'b1: No NAK Response Received Interrupt Mask + */ +#define USB_H_NAKMSK7 (BIT(4)) +#define USB_H_NAKMSK7_M (USB_H_NAKMSK7_V << USB_H_NAKMSK7_S) +#define USB_H_NAKMSK7_V 0x00000001 +#define USB_H_NAKMSK7_S 4 +/** USB_H_ACKMSK7 : R/W; bitpos: [5]; default: 0; + * 1'b0: Mask ACK Response Received/Transmitted Interrupt + * 1'b1: No ACK Response Received/Transmitted Interrupt Mask + */ +#define USB_H_ACKMSK7 (BIT(5)) +#define USB_H_ACKMSK7_M (USB_H_ACKMSK7_V << USB_H_ACKMSK7_S) +#define USB_H_ACKMSK7_V 0x00000001 +#define USB_H_ACKMSK7_S 5 +/** USB_H_NYETMSK7 : R/W; bitpos: [6]; default: 0; + * 1'b0: Mask NYET Response Received Interrupt + * 1'b1: No NYET Response Received Interrupt Mask + */ +#define USB_H_NYETMSK7 (BIT(6)) +#define USB_H_NYETMSK7_M (USB_H_NYETMSK7_V << USB_H_NYETMSK7_S) +#define USB_H_NYETMSK7_V 0x00000001 +#define USB_H_NYETMSK7_S 6 +/** USB_H_XACTERRMSK7 : R/W; bitpos: [7]; default: 0; + * 1'b0: Mask Transaction Error + * 1'b1: No Transaction Error Mask + */ +#define USB_H_XACTERRMSK7 (BIT(7)) +#define USB_H_XACTERRMSK7_M (USB_H_XACTERRMSK7_V << USB_H_XACTERRMSK7_S) +#define USB_H_XACTERRMSK7_V 0x00000001 +#define USB_H_XACTERRMSK7_S 7 +/** USB_H_BBLERRMSK7 : R/W; bitpos: [8]; default: 0; + * Babble Error Mask + * 1'b0: Mask Babble Error + * 1'b1: No Babble Error Mask + */ +#define USB_H_BBLERRMSK7 (BIT(8)) +#define USB_H_BBLERRMSK7_M (USB_H_BBLERRMSK7_V << USB_H_BBLERRMSK7_S) +#define USB_H_BBLERRMSK7_V 0x00000001 +#define USB_H_BBLERRMSK7_S 8 +/** USB_H_FRMOVRUNMSK7 : R/W; bitpos: [9]; default: 0; + * Frame Overrun Mask + * 0x0 (MASK): Mask Overrun Mask + * 0x1 (NOMASK): No Frame Overrun Mask + */ +#define USB_H_FRMOVRUNMSK7 (BIT(9)) +#define USB_H_FRMOVRUNMSK7_M (USB_H_FRMOVRUNMSK7_V << USB_H_FRMOVRUNMSK7_S) +#define USB_H_FRMOVRUNMSK7_V 0x00000001 +#define USB_H_FRMOVRUNMSK7_S 9 +/** USB_H_DATATGLERRMSK7 : R/W; bitpos: [10]; default: 0; + * Data Toggle Error Mask n scatter/gather DMA mode for host + * 1'b0: Mask Data Toggle Error + * 1'b1: No Data Toggle Error Mask + */ +#define USB_H_DATATGLERRMSK7 (BIT(10)) +#define USB_H_DATATGLERRMSK7_M (USB_H_DATATGLERRMSK7_V << USB_H_DATATGLERRMSK7_S) +#define USB_H_DATATGLERRMSK7_V 0x00000001 +#define USB_H_DATATGLERRMSK7_S 10 +/** USB_H_BNAINTRMSK7 : R/W; bitpos: [11]; default: 0; + * BNA (Buffer Not Available) Interrupt mask register + * 1'b0: BNA Interrupt Masked + * 1'b1: BNA Interrupt not masked + */ +#define USB_H_BNAINTRMSK7 (BIT(11)) +#define USB_H_BNAINTRMSK7_M (USB_H_BNAINTRMSK7_V << USB_H_BNAINTRMSK7_S) +#define USB_H_BNAINTRMSK7_V 0x00000001 +#define USB_H_BNAINTRMSK7_S 11 +/** USB_H_DESC_LST_ROLLINTRMSK7 : R/W; bitpos: [13]; default: 0; + * Descriptor List rollover interrupt Mask + * 1'b0: Descriptor Rollover Interrupt Mask + * 1'b1: Descriptor Rollover Interrupt not masked + */ +#define USB_H_DESC_LST_ROLLINTRMSK7 (BIT(13)) +#define USB_H_DESC_LST_ROLLINTRMSK7_M (USB_H_DESC_LST_ROLLINTRMSK7_V << USB_H_DESC_LST_ROLLINTRMSK7_S) +#define USB_H_DESC_LST_ROLLINTRMSK7_V 0x00000001 +#define USB_H_DESC_LST_ROLLINTRMSK7_S 13 + + +/** USB_DIEPMSK_REG register + * Device IN Endpoint Common Interrupt Mask Register + */ +#define USB_DIEPMSK_REG (SOC_DPORT_USB_BASE + 0x810) +/** USB_DI_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * 0x0 : Mask Transfer Completed Interrupt + * 0x1 : No Transfer Completed Interrupt Mask + */ +#define USB_DI_XFERCOMPLMSK (BIT(0)) +#define USB_DI_XFERCOMPLMSK_M (USB_DI_XFERCOMPLMSK_V << USB_DI_XFERCOMPLMSK_S) +#define USB_DI_XFERCOMPLMSK_V 0x00000001 +#define USB_DI_XFERCOMPLMSK_S 0 +/** USB_DI_EPDISBLDMSK : R/W; bitpos: [1]; default: 0; + * 0x0 : Mask Endpoint Disabled Interrupt + * 0x1 : No Endpoint Disabled Interrupt Mask + */ +#define USB_DI_EPDISBLDMSK (BIT(1)) +#define USB_DI_EPDISBLDMSK_M (USB_DI_EPDISBLDMSK_V << USB_DI_EPDISBLDMSK_S) +#define USB_DI_EPDISBLDMSK_V 0x00000001 +#define USB_DI_EPDISBLDMSK_S 1 +/** USB_DI_AHBERMSK : R/W; bitpos: [2]; default: 0; + * 0x0 : Mask AHB Error Interrupt + * 0x1 : No AHB Error Interrupt Mask + */ +#define USB_DI_AHBERMSK (BIT(2)) +#define USB_DI_AHBERMSK_M (USB_DI_AHBERMSK_V << USB_DI_AHBERMSK_S) +#define USB_DI_AHBERMSK_V 0x00000001 +#define USB_DI_AHBERMSK_S 2 +/** USB_TIMEOUTMSK : R/W; bitpos: [3]; default: 0; + * 0x0 : Mask Timeout Condition Interrupt + * 0x1 : No Timeout Condition Interrupt Mask + */ +#define USB_TIMEOUTMSK (BIT(3)) +#define USB_TIMEOUTMSK_M (USB_TIMEOUTMSK_V << USB_TIMEOUTMSK_S) +#define USB_TIMEOUTMSK_V 0x00000001 +#define USB_TIMEOUTMSK_S 3 +/** USB_INTKNTXFEMPMSK : R/W; bitpos: [4]; default: 0; + * 0x0 : Mask IN Token Received When TxFIFO Empty Interrupt + * 0x1 : No IN Token Received When TxFIFO Empty Interrupt + */ +#define USB_INTKNTXFEMPMSK (BIT(4)) +#define USB_INTKNTXFEMPMSK_M (USB_INTKNTXFEMPMSK_V << USB_INTKNTXFEMPMSK_S) +#define USB_INTKNTXFEMPMSK_V 0x00000001 +#define USB_INTKNTXFEMPMSK_S 4 +/** USB_INTKNEPMISMSK : R/W; bitpos: [5]; default: 0; + * 0x0 : Mask IN Token received with EP Mismatch Interrupt + * 0x1 : No Mask IN Token received with EP Mismatch Interrupt + */ +#define USB_INTKNEPMISMSK (BIT(5)) +#define USB_INTKNEPMISMSK_M (USB_INTKNEPMISMSK_V << USB_INTKNEPMISMSK_S) +#define USB_INTKNEPMISMSK_V 0x00000001 +#define USB_INTKNEPMISMSK_S 5 +/** USB_INEPNAKEFFMSK : R/W; bitpos: [6]; default: 0; + * 0x0 : Mask IN Endpoint NAK Effective Interrupt + * 0x1 : No IN Endpoint NAK Effective Interrupt Mask + */ +#define USB_INEPNAKEFFMSK (BIT(6)) +#define USB_INEPNAKEFFMSK_M (USB_INEPNAKEFFMSK_V << USB_INEPNAKEFFMSK_S) +#define USB_INEPNAKEFFMSK_V 0x00000001 +#define USB_INEPNAKEFFMSK_S 6 +/** USB_TXFIFOUNDRNMSK : R/W; bitpos: [8]; default: 0; + * 0x0 : Mask Fifo Underrun Interrupt + * 0x1 : No Fifo Underrun Interrupt Mask + */ +#define USB_TXFIFOUNDRNMSK (BIT(8)) +#define USB_TXFIFOUNDRNMSK_M (USB_TXFIFOUNDRNMSK_V << USB_TXFIFOUNDRNMSK_S) +#define USB_TXFIFOUNDRNMSK_V 0x00000001 +#define USB_TXFIFOUNDRNMSK_S 8 +/** USB_BNAININTRMSK : R/W; bitpos: [9]; default: 0; + * 0x0 : Mask BNA Interrupt + * 0x1 : No BNA Interrupt Mask + */ +#define USB_BNAININTRMSK (BIT(9)) +#define USB_BNAININTRMSK_M (USB_BNAININTRMSK_V << USB_BNAININTRMSK_S) +#define USB_BNAININTRMSK_V 0x00000001 +#define USB_BNAININTRMSK_S 9 +/** USB_DI_NAKMSK : R/W; bitpos: [13]; default: 0; + * 0x0 : Mask NAK Interrupt + * 0x1 : No Mask NAK Interrupt + */ +#define USB_DI_NAKMSK (BIT(13)) +#define USB_DI_NAKMSK_M (USB_DI_NAKMSK_V << USB_DI_NAKMSK_S) +#define USB_DI_NAKMSK_V 0x00000001 +#define USB_DI_NAKMSK_S 13 + + +/** USB_DOEPMSK_REG register + * Device OUT Endpoint Common Interrupt Mask Register + */ +#define USB_DOEPMSK_REG (SOC_DPORT_USB_BASE + 0x814) +/** USB_XFERCOMPLMSK : R/W; bitpos: [0]; default: 0; + * 0x0 : Mask Transfer Completed Interrupt + * 0x1 : No Transfer Completed Interrupt Mask + */ +#define USB_XFERCOMPLMSK (BIT(0)) +#define USB_XFERCOMPLMSK_M (USB_XFERCOMPLMSK_V << USB_XFERCOMPLMSK_S) +#define USB_XFERCOMPLMSK_V 0x00000001 +#define USB_XFERCOMPLMSK_S 0 +/** USB_EPDISBLDMSK : R/W; bitpos: [1]; default: 0; + * 0x0 : Mask Endpoint Disabled Interrupt + * 0x1 : No Endpoint Disabled Interrupt Mask + */ +#define USB_EPDISBLDMSK (BIT(1)) +#define USB_EPDISBLDMSK_M (USB_EPDISBLDMSK_V << USB_EPDISBLDMSK_S) +#define USB_EPDISBLDMSK_V 0x00000001 +#define USB_EPDISBLDMSK_S 1 +/** USB_AHBERMSK : R/W; bitpos: [2]; default: 0; + * 0x0 : Mask AHB Error Interrupt + * 0x1 : No AHB Error Interrupt Mask + */ +#define USB_AHBERMSK (BIT(2)) +#define USB_AHBERMSK_M (USB_AHBERMSK_V << USB_AHBERMSK_S) +#define USB_AHBERMSK_V 0x00000001 +#define USB_AHBERMSK_S 2 +/** USB_SETUPMSK : R/W; bitpos: [3]; default: 0; + * 0x0 : Mask SETUP Phase Done Interrupt + * 0x1 : No SETUP Phase Done Interrupt Mask + */ +#define USB_SETUPMSK (BIT(3)) +#define USB_SETUPMSK_M (USB_SETUPMSK_V << USB_SETUPMSK_S) +#define USB_SETUPMSK_V 0x00000001 +#define USB_SETUPMSK_S 3 +/** USB_OUTTKNEPDISMSK : R/W; bitpos: [4]; default: 0; + * 0x0 : Mask OUT Token Received when Endpoint Disabled Interrupt + * 0x1 : No OUT Token Received when Endpoint Disabled Interrupt Mask + */ +#define USB_OUTTKNEPDISMSK (BIT(4)) +#define USB_OUTTKNEPDISMSK_M (USB_OUTTKNEPDISMSK_V << USB_OUTTKNEPDISMSK_S) +#define USB_OUTTKNEPDISMSK_V 0x00000001 +#define USB_OUTTKNEPDISMSK_S 4 +/** USB_STSPHSERCVDMSK : R/W; bitpos: [5]; default: 0; + * 0x0 : Status Phase Received Mask + * 0x1 : No Status Phase Received Mask + */ +#define USB_STSPHSERCVDMSK (BIT(5)) +#define USB_STSPHSERCVDMSK_M (USB_STSPHSERCVDMSK_V << USB_STSPHSERCVDMSK_S) +#define USB_STSPHSERCVDMSK_V 0x00000001 +#define USB_STSPHSERCVDMSK_S 5 +/** USB_BACK2BACKSETUP : R/W; bitpos: [6]; default: 0; + * 0x0 : Mask Back-to-Back SETUP Packets Received Interrupt + * 0x1 : No Back-to-Back SETUP Packets Received Interrupt Mask + */ +#define USB_BACK2BACKSETUP (BIT(6)) +#define USB_BACK2BACKSETUP_M (USB_BACK2BACKSETUP_V << USB_BACK2BACKSETUP_S) +#define USB_BACK2BACKSETUP_V 0x00000001 +#define USB_BACK2BACKSETUP_S 6 +/** USB_OUTPKTERRMSK : R/W; bitpos: [8]; default: 0; + * 0x0 : Mask OUT Packet Error Interrupt + * 0x1 : No OUT Packet Error Interrupt Mask + */ +#define USB_OUTPKTERRMSK (BIT(8)) +#define USB_OUTPKTERRMSK_M (USB_OUTPKTERRMSK_V << USB_OUTPKTERRMSK_S) +#define USB_OUTPKTERRMSK_V 0x00000001 +#define USB_OUTPKTERRMSK_S 8 +/** USB_BNAOUTINTRMSK : R/W; bitpos: [9]; default: 0; + * 0x0 : Mask BNA Interrupt + * 0x1 : No BNA Interrupt Mask + */ +#define USB_BNAOUTINTRMSK (BIT(9)) +#define USB_BNAOUTINTRMSK_M (USB_BNAOUTINTRMSK_V << USB_BNAOUTINTRMSK_S) +#define USB_BNAOUTINTRMSK_V 0x00000001 +#define USB_BNAOUTINTRMSK_S 9 +/** USB_BBLEERRMSK : R/W; bitpos: [12]; default: 0; + * 0x0 : Mask Babble Error Interrupt + * 0x1 : No Babble Error Interrupt Mask + */ +#define USB_BBLEERRMSK (BIT(12)) +#define USB_BBLEERRMSK_M (USB_BBLEERRMSK_V << USB_BBLEERRMSK_S) +#define USB_BBLEERRMSK_V 0x00000001 +#define USB_BBLEERRMSK_S 12 +/** USB_NAKMSK : R/W; bitpos: [13]; default: 0; + * 0x0 : Mask NAK Interrupt + * 0x1 : No NAK Interrupt Mask + */ +#define USB_NAKMSK (BIT(13)) +#define USB_NAKMSK_M (USB_NAKMSK_V << USB_NAKMSK_S) +#define USB_NAKMSK_V 0x00000001 +#define USB_NAKMSK_S 13 +/** USB_NYETMSK : R/W; bitpos: [14]; default: 0; + * NYET interrupt Mask + * 0x0 : Mask NYET Interrupt + * 0x1 : No NYET Interrupt Mask + */ +#define USB_NYETMSK (BIT(14)) +#define USB_NYETMSK_M (USB_NYETMSK_V << USB_NYETMSK_S) +#define USB_NYETMSK_V 0x00000001 +#define USB_NYETMSK_S 14 + + +/** USB_DAINT_REG register + * Device All Endpoints Interrupt Register + */ +#define USB_DAINT_REG (SOC_DPORT_USB_BASE + 0x818) +/** USB_INEPINT0 : RO; bitpos: [0]; default: 0; + * IN Endpoint 0 Interrupt Bit. + */ +#define USB_INEPINT0 (BIT(0)) +#define USB_INEPINT0_M (USB_INEPINT0_V << USB_INEPINT0_S) +#define USB_INEPINT0_V 0x00000001 +#define USB_INEPINT0_S 0 +/** USB_INEPINT1 : RO; bitpos: [1]; default: 0; + * IN Endpoint 1 Interrupt Bit. + */ +#define USB_INEPINT1 (BIT(1)) +#define USB_INEPINT1_M (USB_INEPINT1_V << USB_INEPINT1_S) +#define USB_INEPINT1_V 0x00000001 +#define USB_INEPINT1_S 1 +/** USB_INEPINT2 : RO; bitpos: [2]; default: 0; + * IN Endpoint 2 Interrupt Bit. + */ +#define USB_INEPINT2 (BIT(2)) +#define USB_INEPINT2_M (USB_INEPINT2_V << USB_INEPINT2_S) +#define USB_INEPINT2_V 0x00000001 +#define USB_INEPINT2_S 2 +/** USB_INEPINT3 : RO; bitpos: [3]; default: 0; + * IN Endpoint 3 Interrupt Bit. + */ +#define USB_INEPINT3 (BIT(3)) +#define USB_INEPINT3_M (USB_INEPINT3_V << USB_INEPINT3_S) +#define USB_INEPINT3_V 0x00000001 +#define USB_INEPINT3_S 3 +/** USB_INEPINT4 : RO; bitpos: [4]; default: 0; + * IN Endpoint 4 Interrupt Bit. + */ +#define USB_INEPINT4 (BIT(4)) +#define USB_INEPINT4_M (USB_INEPINT4_V << USB_INEPINT4_S) +#define USB_INEPINT4_V 0x00000001 +#define USB_INEPINT4_S 4 +/** USB_INEPINT5 : RO; bitpos: [5]; default: 0; + * IN Endpoint 5 Interrupt Bit. + */ +#define USB_INEPINT5 (BIT(5)) +#define USB_INEPINT5_M (USB_INEPINT5_V << USB_INEPINT5_S) +#define USB_INEPINT5_V 0x00000001 +#define USB_INEPINT5_S 5 +/** USB_INEPINT6 : RO; bitpos: [6]; default: 0; + * IN Endpoint 6 Interrupt Bit. + */ +#define USB_INEPINT6 (BIT(6)) +#define USB_INEPINT6_M (USB_INEPINT6_V << USB_INEPINT6_S) +#define USB_INEPINT6_V 0x00000001 +#define USB_INEPINT6_S 6 +/** USB_OUTEPINT0 : RO; bitpos: [16]; default: 0; + * OUT Endpoint 0 Interrupt Bit. + */ +#define USB_OUTEPINT0 (BIT(16)) +#define USB_OUTEPINT0_M (USB_OUTEPINT0_V << USB_OUTEPINT0_S) +#define USB_OUTEPINT0_V 0x00000001 +#define USB_OUTEPINT0_S 16 +/** USB_OUTEPINT1 : RO; bitpos: [17]; default: 0; + * OUT Endpoint 1 Interrupt Bit. + */ +#define USB_OUTEPINT1 (BIT(17)) +#define USB_OUTEPINT1_M (USB_OUTEPINT1_V << USB_OUTEPINT1_S) +#define USB_OUTEPINT1_V 0x00000001 +#define USB_OUTEPINT1_S 17 +/** USB_OUTEPINT2 : RO; bitpos: [18]; default: 0; + * OUT Endpoint 2 Interrupt Bit. + */ +#define USB_OUTEPINT2 (BIT(18)) +#define USB_OUTEPINT2_M (USB_OUTEPINT2_V << USB_OUTEPINT2_S) +#define USB_OUTEPINT2_V 0x00000001 +#define USB_OUTEPINT2_S 18 +/** USB_OUTEPINT3 : RO; bitpos: [19]; default: 0; + * OUT Endpoint 3 Interrupt Bit. + */ +#define USB_OUTEPINT3 (BIT(19)) +#define USB_OUTEPINT3_M (USB_OUTEPINT3_V << USB_OUTEPINT3_S) +#define USB_OUTEPINT3_V 0x00000001 +#define USB_OUTEPINT3_S 19 +/** USB_OUTEPINT4 : RO; bitpos: [20]; default: 0; + * OUT Endpoint 4 Interrupt Bit. + */ +#define USB_OUTEPINT4 (BIT(20)) +#define USB_OUTEPINT4_M (USB_OUTEPINT4_V << USB_OUTEPINT4_S) +#define USB_OUTEPINT4_V 0x00000001 +#define USB_OUTEPINT4_S 20 +/** USB_OUTEPINT5 : RO; bitpos: [21]; default: 0; + * OUT Endpoint 5 Interrupt Bit. + */ +#define USB_OUTEPINT5 (BIT(21)) +#define USB_OUTEPINT5_M (USB_OUTEPINT5_V << USB_OUTEPINT5_S) +#define USB_OUTEPINT5_V 0x00000001 +#define USB_OUTEPINT5_S 21 +/** USB_OUTEPINT6 : RO; bitpos: [22]; default: 0; + * OUT Endpoint 6 Interrupt Bit. + */ +#define USB_OUTEPINT6 (BIT(22)) +#define USB_OUTEPINT6_M (USB_OUTEPINT6_V << USB_OUTEPINT6_S) +#define USB_OUTEPINT6_V 0x00000001 +#define USB_OUTEPINT6_S 22 + + +/** USB_DAINTMSK_REG register + * Device All Endpoints Interrupt Mask Register + */ +#define USB_DAINTMSK_REG (SOC_DPORT_USB_BASE + 0x81c) +/** USB_INEPMSK0 : R/W; bitpos: [0]; default: 0; + * IN Endpoint 0 Interrupt mask Bit. + */ +#define USB_INEPMSK0 (BIT(0)) +#define USB_INEPMSK0_M (USB_INEPMSK0_V << USB_INEPMSK0_S) +#define USB_INEPMSK0_V 0x00000001 +#define USB_INEPMSK0_S 0 +/** USB_INEPMSK1 : R/W; bitpos: [1]; default: 0; + * IN Endpoint 1 Interrupt mask Bit. + */ +#define USB_INEPMSK1 (BIT(1)) +#define USB_INEPMSK1_M (USB_INEPMSK1_V << USB_INEPMSK1_S) +#define USB_INEPMSK1_V 0x00000001 +#define USB_INEPMSK1_S 1 +/** USB_INEPMSK2 : R/W; bitpos: [2]; default: 0; + * IN Endpoint 2 Interrupt mask Bit. + */ +#define USB_INEPMSK2 (BIT(2)) +#define USB_INEPMSK2_M (USB_INEPMSK2_V << USB_INEPMSK2_S) +#define USB_INEPMSK2_V 0x00000001 +#define USB_INEPMSK2_S 2 +/** USB_INEPMSK3 : R/W; bitpos: [3]; default: 0; + * IN Endpoint 3 Interrupt mask Bit. + */ +#define USB_INEPMSK3 (BIT(3)) +#define USB_INEPMSK3_M (USB_INEPMSK3_V << USB_INEPMSK3_S) +#define USB_INEPMSK3_V 0x00000001 +#define USB_INEPMSK3_S 3 +/** USB_INEPMSK4 : R/W; bitpos: [4]; default: 0; + * IN Endpoint 4 Interrupt mask Bit. + */ +#define USB_INEPMSK4 (BIT(4)) +#define USB_INEPMSK4_M (USB_INEPMSK4_V << USB_INEPMSK4_S) +#define USB_INEPMSK4_V 0x00000001 +#define USB_INEPMSK4_S 4 +/** USB_INEPMSK5 : R/W; bitpos: [5]; default: 0; + * IN Endpoint 5 Interrupt mask Bit. + */ +#define USB_INEPMSK5 (BIT(5)) +#define USB_INEPMSK5_M (USB_INEPMSK5_V << USB_INEPMSK5_S) +#define USB_INEPMSK5_V 0x00000001 +#define USB_INEPMSK5_S 5 +/** USB_INEPMSK6 : R/W; bitpos: [6]; default: 0; + * IN Endpoint 6 Interrupt mask Bit. + */ +#define USB_INEPMSK6 (BIT(6)) +#define USB_INEPMSK6_M (USB_INEPMSK6_V << USB_INEPMSK6_S) +#define USB_INEPMSK6_V 0x00000001 +#define USB_INEPMSK6_S 6 +/** USB_OUTEPMSK0 : R/W; bitpos: [16]; default: 0; + * OUT Endpoint 0 Interrupt mask Bit. + */ +#define USB_OUTEPMSK0 (BIT(16)) +#define USB_OUTEPMSK0_M (USB_OUTEPMSK0_V << USB_OUTEPMSK0_S) +#define USB_OUTEPMSK0_V 0x00000001 +#define USB_OUTEPMSK0_S 16 +/** USB_OUTEPMSK1 : R/W; bitpos: [17]; default: 0; + * OUT Endpoint 1 Interrupt mask Bit. + */ +#define USB_OUTEPMSK1 (BIT(17)) +#define USB_OUTEPMSK1_M (USB_OUTEPMSK1_V << USB_OUTEPMSK1_S) +#define USB_OUTEPMSK1_V 0x00000001 +#define USB_OUTEPMSK1_S 17 +/** USB_OUTEPMSK2 : R/W; bitpos: [18]; default: 0; + * OUT Endpoint 2 Interrupt mask Bit. + */ +#define USB_OUTEPMSK2 (BIT(18)) +#define USB_OUTEPMSK2_M (USB_OUTEPMSK2_V << USB_OUTEPMSK2_S) +#define USB_OUTEPMSK2_V 0x00000001 +#define USB_OUTEPMSK2_S 18 +/** USB_OUTEPMSK3 : R/W; bitpos: [19]; default: 0; + * OUT Endpoint 3 Interrupt mask Bit. + */ +#define USB_OUTEPMSK3 (BIT(19)) +#define USB_OUTEPMSK3_M (USB_OUTEPMSK3_V << USB_OUTEPMSK3_S) +#define USB_OUTEPMSK3_V 0x00000001 +#define USB_OUTEPMSK3_S 19 +/** USB_OUTEPMSK4 : R/W; bitpos: [20]; default: 0; + * OUT Endpoint 4 Interrupt mask Bit. + */ +#define USB_OUTEPMSK4 (BIT(20)) +#define USB_OUTEPMSK4_M (USB_OUTEPMSK4_V << USB_OUTEPMSK4_S) +#define USB_OUTEPMSK4_V 0x00000001 +#define USB_OUTEPMSK4_S 20 +/** USB_OUTEPMSK5 : R/W; bitpos: [21]; default: 0; + * OUT Endpoint 5 Interrupt mask Bit. + */ +#define USB_OUTEPMSK5 (BIT(21)) +#define USB_OUTEPMSK5_M (USB_OUTEPMSK5_V << USB_OUTEPMSK5_S) +#define USB_OUTEPMSK5_V 0x00000001 +#define USB_OUTEPMSK5_S 21 +/** USB_OUTEPMSK6 : R/W; bitpos: [22]; default: 0; + * OUT Endpoint 6 Interrupt mask Bit. + */ +#define USB_OUTEPMSK6 (BIT(22)) +#define USB_OUTEPMSK6_M (USB_OUTEPMSK6_V << USB_OUTEPMSK6_S) +#define USB_OUTEPMSK6_V 0x00000001 +#define USB_OUTEPMSK6_S 22 + + +/** USB_DIEPEMPMSK_REG register + * Device IN Endpoint FIFO Empty Interrupt Mask Register + */ +#define USB_DIEPEMPMSK_REG (SOC_DPORT_USB_BASE + 0x834) +/** USB_D_INEPTXFEMPMSK : R/W; bitpos: [16:0]; default: 0; + * IN EP Tx FIFO Empty Interrupt Mask Bits + * 0x1 (EP0_MASK): Mask IN EP0 Tx FIFO Empty Interrupt + * 0x2 (EP1_MASK): Mask IN EP1 Tx FIFO Empty Interrupt + * 0x4 (EP2_MASK): Mask IN EP2 Tx FIFO Empty Interrupt + * 0x8 (EP3_MASK): Mask IN EP3 Tx FIFO Empty Interrupt + * 0x10 (EP4_MASK): Mask IN EP4 Tx FIFO Empty Interrupt + * 0x20 (EP5_MASK): Mask IN EP5 Tx FIFO Empty Interrupt + * 0x40 (EP6_MASK): Mask IN EP6 Tx FIFO Empty Interrupt + * 0x80 (EP7_MASK): Mask IN EP7 Tx FIFO Empty Interrupt + * 0x100 (EP8_MASK): Mask IN EP8 Tx FIFO Empty Interrupt + * 0x200 (EP9_MASK): Mask IN EP9 Tx FIFO Empty Interrupt + * 0x400 (EP10_MASK): Mask IN EP10 Tx FIFO Empty Interrupt + * 0x800 (EP11_MASK): Mask IN EP11 Tx FIFO Empty Interrupt + * 0x1000 (EP12_MASK): Mask IN EP12 Tx FIFO Empty Interrupt + * 0x2000 (EP13_MASK): Mask IN EP13 Tx FIFO Empty Interrupt + * 0x4000 (EP14_MASK): Mask IN EP14 Tx FIFO Empty Interrupt + * 0x8000 (EP15_MASK): Mask IN EP15 Tx FIFO Empty Interrupt + */ +#define USB_D_INEPTXFEMPMSK 0x0000FFFF +#define USB_D_INEPTXFEMPMSK_M (USB_D_INEPTXFEMPMSK_V << USB_D_INEPTXFEMPMSK_S) +#define USB_D_INEPTXFEMPMSK_V 0x0000FFFF +#define USB_D_INEPTXFEMPMSK_S 0 + + +/** USB_DIEPINT0_REG register + * Device IN Endpoint 0 Interrupt Register + */ +#define USB_DIEPINT0_REG (SOC_DPORT_USB_BASE + 0x908) +/** USB_D_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0; + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Completed Interrupt + */ +#define USB_D_XFERCOMPL0 (BIT(0)) +#define USB_D_XFERCOMPL0_M (USB_D_XFERCOMPL0_V << USB_D_XFERCOMPL0_S) +#define USB_D_XFERCOMPL0_V 0x00000001 +#define USB_D_XFERCOMPL0_S 0 +/** USB_D_EPDISBLD0 : R/W1C; bitpos: [1]; default: 0; + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_D_EPDISBLD0 (BIT(1)) +#define USB_D_EPDISBLD0_M (USB_D_EPDISBLD0_V << USB_D_EPDISBLD0_S) +#define USB_D_EPDISBLD0_V 0x00000001 +#define USB_D_EPDISBLD0_S 1 +/** USB_D_AHBERR0 : R/W1C; bitpos: [2]; default: 0; + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_D_AHBERR0 (BIT(2)) +#define USB_D_AHBERR0_M (USB_D_AHBERR0_V << USB_D_AHBERR0_S) +#define USB_D_AHBERR0_V 0x00000001 +#define USB_D_AHBERR0_S 2 +/** USB_D_TIMEOUT0 : R/W1C; bitpos: [3]; default: 0; + * 0x0 : No Timeout interrupt + * 0x1 : Timeout interrupt + */ +#define USB_D_TIMEOUT0 (BIT(3)) +#define USB_D_TIMEOUT0_M (USB_D_TIMEOUT0_V << USB_D_TIMEOUT0_S) +#define USB_D_TIMEOUT0_V 0x00000001 +#define USB_D_TIMEOUT0_S 3 +/** USB_D_INTKNTXFEMP0 : R/W1C; bitpos: [4]; default: 0; + * 0x0 : No IN Token Received when TxFIFO Empty Interrupt + * 0x1 : IN Token Received when TxFIFO Empty Interrupt + */ +#define USB_D_INTKNTXFEMP0 (BIT(4)) +#define USB_D_INTKNTXFEMP0_M (USB_D_INTKNTXFEMP0_V << USB_D_INTKNTXFEMP0_S) +#define USB_D_INTKNTXFEMP0_V 0x00000001 +#define USB_D_INTKNTXFEMP0_S 4 +/** USB_D_INTKNEPMIS0 : R/W1C; bitpos: [5]; default: 0; + * 0x0 : No IN Token Received with EP Mismatch Interrupt + * 0x1 : IN Token Received with EP Mismatch interrupt + */ +#define USB_D_INTKNEPMIS0 (BIT(5)) +#define USB_D_INTKNEPMIS0_M (USB_D_INTKNEPMIS0_V << USB_D_INTKNEPMIS0_S) +#define USB_D_INTKNEPMIS0_V 0x00000001 +#define USB_D_INTKNEPMIS0_S 5 +/** USB_D_INEPNAKEFF0 : R/W1C; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective + * 0x0 : No IN Endpoint NAK Effective interrupt + * 0x1 : IN Endpoint NAK Effective interrupt + */ +#define USB_D_INEPNAKEFF0 (BIT(6)) +#define USB_D_INEPNAKEFF0_M (USB_D_INEPNAKEFF0_V << USB_D_INEPNAKEFF0_S) +#define USB_D_INEPNAKEFF0_V 0x00000001 +#define USB_D_INEPNAKEFF0_S 6 +/** USB_D_TXFEMP0 : RO; bitpos: [7]; default: 0; + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty + * 0x0 : No Transmit FIFO Empty interrupt + * 0x1 : Transmit FIFO Empty interrupt + */ +#define USB_D_TXFEMP0 (BIT(7)) +#define USB_D_TXFEMP0_M (USB_D_TXFEMP0_V << USB_D_TXFEMP0_S) +#define USB_D_TXFEMP0_V 0x00000001 +#define USB_D_TXFEMP0_S 7 +/** USB_D_TXFIFOUNDRN0 : R/W1C; bitpos: [8]; default: 0; + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint + * 0x0 : No Fifo Underrun interrupt + * 0x1 : Fifo Underrun interrupt + */ +#define USB_D_TXFIFOUNDRN0 (BIT(8)) +#define USB_D_TXFIFOUNDRN0_M (USB_D_TXFIFOUNDRN0_V << USB_D_TXFIFOUNDRN0_S) +#define USB_D_TXFIFOUNDRN0_V 0x00000001 +#define USB_D_TXFIFOUNDRN0_S 8 +/** USB_D_BNAINTR0 : R/W1C; bitpos: [9]; default: 0; + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_D_BNAINTR0 (BIT(9)) +#define USB_D_BNAINTR0_M (USB_D_BNAINTR0_V << USB_D_BNAINTR0_S) +#define USB_D_BNAINTR0_V 0x00000001 +#define USB_D_BNAINTR0_S 9 +/** USB_D_PKTDRPSTS0 : R/W1C; bitpos: [11]; default: 0; + * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet + * has been dropped. This bit does not have an associated mask bit and does not + * generate an interrupt + * 0x0 : No interrupt + * 0x1 : Packet Drop Status + */ +#define USB_D_PKTDRPSTS0 (BIT(11)) +#define USB_D_PKTDRPSTS0_M (USB_D_PKTDRPSTS0_V << USB_D_PKTDRPSTS0_S) +#define USB_D_PKTDRPSTS0_V 0x00000001 +#define USB_D_PKTDRPSTS0_S 11 +/** USB_D_BBLEERR0 : R/W1C; bitpos: [12]; default: 0; + * The core generates this interrupt when babble is received for the endpoint + * 0x0 : No interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_D_BBLEERR0 (BIT(12)) +#define USB_D_BBLEERR0_M (USB_D_BBLEERR0_V << USB_D_BBLEERR0_S) +#define USB_D_BBLEERR0_V 0x00000001 +#define USB_D_BBLEERR0_S 12 +/** USB_D_NAKINTRPT0 : R/W1C; bitpos: [13]; default: 0; + * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or + * received by the device + * 0x0 : No interrupt + * 0x1 : NAK Interrupt + */ +#define USB_D_NAKINTRPT0 (BIT(13)) +#define USB_D_NAKINTRPT0_M (USB_D_NAKINTRPT0_V << USB_D_NAKINTRPT0_S) +#define USB_D_NAKINTRPT0_V 0x00000001 +#define USB_D_NAKINTRPT0_S 13 +/** USB_D_NYETINTRPT0 : R/W1C; bitpos: [14]; default: 0; + * NYET Interrupt. The core generates this interrupt when a NYET response is + * transmitted for a non isochronous OUT endpoint + * 0x0 : No interrupt + * 0x1 : NYET Interrupt + */ +#define USB_D_NYETINTRPT0 (BIT(14)) +#define USB_D_NYETINTRPT0_M (USB_D_NYETINTRPT0_V << USB_D_NYETINTRPT0_S) +#define USB_D_NYETINTRPT0_V 0x00000001 +#define USB_D_NYETINTRPT0_S 14 + + +/** USB_DIEPINT1_REG register + * Device IN Endpoint 1 Interrupt Register + */ +#define USB_DIEPINT1_REG (SOC_DPORT_USB_BASE + 0x928) +/** USB_D_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0; + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Completed Interrupt + */ +#define USB_D_XFERCOMPL1 (BIT(0)) +#define USB_D_XFERCOMPL1_M (USB_D_XFERCOMPL1_V << USB_D_XFERCOMPL1_S) +#define USB_D_XFERCOMPL1_V 0x00000001 +#define USB_D_XFERCOMPL1_S 0 +/** USB_D_EPDISBLD1 : R/W1C; bitpos: [1]; default: 0; + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_D_EPDISBLD1 (BIT(1)) +#define USB_D_EPDISBLD1_M (USB_D_EPDISBLD1_V << USB_D_EPDISBLD1_S) +#define USB_D_EPDISBLD1_V 0x00000001 +#define USB_D_EPDISBLD1_S 1 +/** USB_D_AHBERR1 : R/W1C; bitpos: [2]; default: 0; + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_D_AHBERR1 (BIT(2)) +#define USB_D_AHBERR1_M (USB_D_AHBERR1_V << USB_D_AHBERR1_S) +#define USB_D_AHBERR1_V 0x00000001 +#define USB_D_AHBERR1_S 2 +/** USB_D_TIMEOUT1 : R/W1C; bitpos: [3]; default: 0; + * 0x0 : No Timeout interrupt + * 0x1 : Timeout interrupt + */ +#define USB_D_TIMEOUT1 (BIT(3)) +#define USB_D_TIMEOUT1_M (USB_D_TIMEOUT1_V << USB_D_TIMEOUT1_S) +#define USB_D_TIMEOUT1_V 0x00000001 +#define USB_D_TIMEOUT1_S 3 +/** USB_D_INTKNTXFEMP1 : R/W1C; bitpos: [4]; default: 0; + * 0x0 : No IN Token Received when TxFIFO Empty Interrupt + * 0x1 : IN Token Received when TxFIFO Empty Interrupt + */ +#define USB_D_INTKNTXFEMP1 (BIT(4)) +#define USB_D_INTKNTXFEMP1_M (USB_D_INTKNTXFEMP1_V << USB_D_INTKNTXFEMP1_S) +#define USB_D_INTKNTXFEMP1_V 0x00000001 +#define USB_D_INTKNTXFEMP1_S 4 +/** USB_D_INTKNEPMIS1 : R/W1C; bitpos: [5]; default: 0; + * 0x0 : No IN Token Received with EP Mismatch Interrupt + * 0x1 : IN Token Received with EP Mismatch interrupt + */ +#define USB_D_INTKNEPMIS1 (BIT(5)) +#define USB_D_INTKNEPMIS1_M (USB_D_INTKNEPMIS1_V << USB_D_INTKNEPMIS1_S) +#define USB_D_INTKNEPMIS1_V 0x00000001 +#define USB_D_INTKNEPMIS1_S 5 +/** USB_D_INEPNAKEFF1 : R/W1C; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective + * 0x0 : No IN Endpoint NAK Effective interrupt + * 0x1 : IN Endpoint NAK Effective interrupt + */ +#define USB_D_INEPNAKEFF1 (BIT(6)) +#define USB_D_INEPNAKEFF1_M (USB_D_INEPNAKEFF1_V << USB_D_INEPNAKEFF1_S) +#define USB_D_INEPNAKEFF1_V 0x00000001 +#define USB_D_INEPNAKEFF1_S 6 +/** USB_D_TXFEMP1 : RO; bitpos: [7]; default: 0; + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty + * 0x0 : No Transmit FIFO Empty interrupt + * 0x1 : Transmit FIFO Empty interrupt + */ +#define USB_D_TXFEMP1 (BIT(7)) +#define USB_D_TXFEMP1_M (USB_D_TXFEMP1_V << USB_D_TXFEMP1_S) +#define USB_D_TXFEMP1_V 0x00000001 +#define USB_D_TXFEMP1_S 7 +/** USB_D_TXFIFOUNDRN1 : R/W1C; bitpos: [8]; default: 0; + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint + * 0x0 : No Fifo Underrun interrupt + * 0x1 : Fifo Underrun interrupt + */ +#define USB_D_TXFIFOUNDRN1 (BIT(8)) +#define USB_D_TXFIFOUNDRN1_M (USB_D_TXFIFOUNDRN1_V << USB_D_TXFIFOUNDRN1_S) +#define USB_D_TXFIFOUNDRN1_V 0x00000001 +#define USB_D_TXFIFOUNDRN1_S 8 +/** USB_D_BNAINTR1 : R/W1C; bitpos: [9]; default: 0; + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_D_BNAINTR1 (BIT(9)) +#define USB_D_BNAINTR1_M (USB_D_BNAINTR1_V << USB_D_BNAINTR1_S) +#define USB_D_BNAINTR1_V 0x00000001 +#define USB_D_BNAINTR1_S 9 +/** USB_D_PKTDRPSTS1 : R/W1C; bitpos: [11]; default: 0; + * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet + * has been dropped. This bit does not have an associated mask bit and does not + * generate an interrupt + * 0x0 : No interrupt + * 0x1 : Packet Drop Status + */ +#define USB_D_PKTDRPSTS1 (BIT(11)) +#define USB_D_PKTDRPSTS1_M (USB_D_PKTDRPSTS1_V << USB_D_PKTDRPSTS1_S) +#define USB_D_PKTDRPSTS1_V 0x00000001 +#define USB_D_PKTDRPSTS1_S 11 +/** USB_D_BBLEERR1 : R/W1C; bitpos: [12]; default: 0; + * The core generates this interrupt when babble is received for the endpoint + * 0x0 : No interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_D_BBLEERR1 (BIT(12)) +#define USB_D_BBLEERR1_M (USB_D_BBLEERR1_V << USB_D_BBLEERR1_S) +#define USB_D_BBLEERR1_V 0x00000001 +#define USB_D_BBLEERR1_S 12 +/** USB_D_NAKINTRPT1 : R/W1C; bitpos: [13]; default: 0; + * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or + * received by the device + * 0x0 : No interrupt + * 0x1 : NAK Interrupt + */ +#define USB_D_NAKINTRPT1 (BIT(13)) +#define USB_D_NAKINTRPT1_M (USB_D_NAKINTRPT1_V << USB_D_NAKINTRPT1_S) +#define USB_D_NAKINTRPT1_V 0x00000001 +#define USB_D_NAKINTRPT1_S 13 +/** USB_D_NYETINTRPT1 : R/W1C; bitpos: [14]; default: 0; + * NYET Interrupt. The core generates this interrupt when a NYET response is + * transmitted for a non isochronous OUT endpoint + * 0x0 : No interrupt + * 0x1 : NYET Interrupt + */ +#define USB_D_NYETINTRPT1 (BIT(14)) +#define USB_D_NYETINTRPT1_M (USB_D_NYETINTRPT1_V << USB_D_NYETINTRPT1_S) +#define USB_D_NYETINTRPT1_V 0x00000001 +#define USB_D_NYETINTRPT1_S 14 + + +/** USB_DIEPINT2_REG register + * Device IN Endpoint 2 Interrupt Register + */ +#define USB_DIEPINT2_REG (SOC_DPORT_USB_BASE + 0x948) +/** USB_D_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0; + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Completed Interrupt + */ +#define USB_D_XFERCOMPL2 (BIT(0)) +#define USB_D_XFERCOMPL2_M (USB_D_XFERCOMPL2_V << USB_D_XFERCOMPL2_S) +#define USB_D_XFERCOMPL2_V 0x00000001 +#define USB_D_XFERCOMPL2_S 0 +/** USB_D_EPDISBLD2 : R/W1C; bitpos: [1]; default: 0; + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_D_EPDISBLD2 (BIT(1)) +#define USB_D_EPDISBLD2_M (USB_D_EPDISBLD2_V << USB_D_EPDISBLD2_S) +#define USB_D_EPDISBLD2_V 0x00000001 +#define USB_D_EPDISBLD2_S 1 +/** USB_D_AHBERR2 : R/W1C; bitpos: [2]; default: 0; + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_D_AHBERR2 (BIT(2)) +#define USB_D_AHBERR2_M (USB_D_AHBERR2_V << USB_D_AHBERR2_S) +#define USB_D_AHBERR2_V 0x00000001 +#define USB_D_AHBERR2_S 2 +/** USB_D_TIMEOUT2 : R/W1C; bitpos: [3]; default: 0; + * 0x0 : No Timeout interrupt + * 0x1 : Timeout interrupt + */ +#define USB_D_TIMEOUT2 (BIT(3)) +#define USB_D_TIMEOUT2_M (USB_D_TIMEOUT2_V << USB_D_TIMEOUT2_S) +#define USB_D_TIMEOUT2_V 0x00000001 +#define USB_D_TIMEOUT2_S 3 +/** USB_D_INTKNTXFEMP2 : R/W1C; bitpos: [4]; default: 0; + * 0x0 : No IN Token Received when TxFIFO Empty Interrupt + * 0x1 : IN Token Received when TxFIFO Empty Interrupt + */ +#define USB_D_INTKNTXFEMP2 (BIT(4)) +#define USB_D_INTKNTXFEMP2_M (USB_D_INTKNTXFEMP2_V << USB_D_INTKNTXFEMP2_S) +#define USB_D_INTKNTXFEMP2_V 0x00000001 +#define USB_D_INTKNTXFEMP2_S 4 +/** USB_D_INTKNEPMIS2 : R/W1C; bitpos: [5]; default: 0; + * 0x0 : No IN Token Received with EP Mismatch Interrupt + * 0x1 : IN Token Received with EP Mismatch interrupt + */ +#define USB_D_INTKNEPMIS2 (BIT(5)) +#define USB_D_INTKNEPMIS2_M (USB_D_INTKNEPMIS2_V << USB_D_INTKNEPMIS2_S) +#define USB_D_INTKNEPMIS2_V 0x00000001 +#define USB_D_INTKNEPMIS2_S 5 +/** USB_D_INEPNAKEFF2 : R/W1C; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective + * 0x0 : No IN Endpoint NAK Effective interrupt + * 0x1 : IN Endpoint NAK Effective interrupt + */ +#define USB_D_INEPNAKEFF2 (BIT(6)) +#define USB_D_INEPNAKEFF2_M (USB_D_INEPNAKEFF2_V << USB_D_INEPNAKEFF2_S) +#define USB_D_INEPNAKEFF2_V 0x00000001 +#define USB_D_INEPNAKEFF2_S 6 +/** USB_D_TXFEMP2 : RO; bitpos: [7]; default: 0; + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty + * 0x0 : No Transmit FIFO Empty interrupt + * 0x1 : Transmit FIFO Empty interrupt + */ +#define USB_D_TXFEMP2 (BIT(7)) +#define USB_D_TXFEMP2_M (USB_D_TXFEMP2_V << USB_D_TXFEMP2_S) +#define USB_D_TXFEMP2_V 0x00000001 +#define USB_D_TXFEMP2_S 7 +/** USB_D_TXFIFOUNDRN2 : R/W1C; bitpos: [8]; default: 0; + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint + * 0x0 : No Fifo Underrun interrupt + * 0x1 : Fifo Underrun interrupt + */ +#define USB_D_TXFIFOUNDRN2 (BIT(8)) +#define USB_D_TXFIFOUNDRN2_M (USB_D_TXFIFOUNDRN2_V << USB_D_TXFIFOUNDRN2_S) +#define USB_D_TXFIFOUNDRN2_V 0x00000001 +#define USB_D_TXFIFOUNDRN2_S 8 +/** USB_D_BNAINTR2 : R/W1C; bitpos: [9]; default: 0; + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_D_BNAINTR2 (BIT(9)) +#define USB_D_BNAINTR2_M (USB_D_BNAINTR2_V << USB_D_BNAINTR2_S) +#define USB_D_BNAINTR2_V 0x00000001 +#define USB_D_BNAINTR2_S 9 +/** USB_D_PKTDRPSTS2 : R/W1C; bitpos: [11]; default: 0; + * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet + * has been dropped. This bit does not have an associated mask bit and does not + * generate an interrupt + * 0x0 : No interrupt + * 0x1 : Packet Drop Status + */ +#define USB_D_PKTDRPSTS2 (BIT(11)) +#define USB_D_PKTDRPSTS2_M (USB_D_PKTDRPSTS2_V << USB_D_PKTDRPSTS2_S) +#define USB_D_PKTDRPSTS2_V 0x00000001 +#define USB_D_PKTDRPSTS2_S 11 +/** USB_D_BBLEERR2 : R/W1C; bitpos: [12]; default: 0; + * The core generates this interrupt when babble is received for the endpoint + * 0x0 : No interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_D_BBLEERR2 (BIT(12)) +#define USB_D_BBLEERR2_M (USB_D_BBLEERR2_V << USB_D_BBLEERR2_S) +#define USB_D_BBLEERR2_V 0x00000001 +#define USB_D_BBLEERR2_S 12 +/** USB_D_NAKINTRPT2 : R/W1C; bitpos: [13]; default: 0; + * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or + * received by the device + * 0x0 : No interrupt + * 0x1 : NAK Interrupt + */ +#define USB_D_NAKINTRPT2 (BIT(13)) +#define USB_D_NAKINTRPT2_M (USB_D_NAKINTRPT2_V << USB_D_NAKINTRPT2_S) +#define USB_D_NAKINTRPT2_V 0x00000001 +#define USB_D_NAKINTRPT2_S 13 +/** USB_D_NYETINTRPT2 : R/W1C; bitpos: [14]; default: 0; + * NYET Interrupt. The core generates this interrupt when a NYET response is + * transmitted for a non isochronous OUT endpoint + * 0x0 : No interrupt + * 0x1 : NYET Interrupt + */ +#define USB_D_NYETINTRPT2 (BIT(14)) +#define USB_D_NYETINTRPT2_M (USB_D_NYETINTRPT2_V << USB_D_NYETINTRPT2_S) +#define USB_D_NYETINTRPT2_V 0x00000001 +#define USB_D_NYETINTRPT2_S 14 + + +/** USB_DIEPINT3_REG register + * Device IN Endpoint 3 Interrupt Register + */ +#define USB_DIEPINT3_REG (SOC_DPORT_USB_BASE + 0x968) +/** USB_D_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0; + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Completed Interrupt + */ +#define USB_D_XFERCOMPL3 (BIT(0)) +#define USB_D_XFERCOMPL3_M (USB_D_XFERCOMPL3_V << USB_D_XFERCOMPL3_S) +#define USB_D_XFERCOMPL3_V 0x00000001 +#define USB_D_XFERCOMPL3_S 0 +/** USB_D_EPDISBLD3 : R/W1C; bitpos: [1]; default: 0; + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_D_EPDISBLD3 (BIT(1)) +#define USB_D_EPDISBLD3_M (USB_D_EPDISBLD3_V << USB_D_EPDISBLD3_S) +#define USB_D_EPDISBLD3_V 0x00000001 +#define USB_D_EPDISBLD3_S 1 +/** USB_D_AHBERR3 : R/W1C; bitpos: [2]; default: 0; + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_D_AHBERR3 (BIT(2)) +#define USB_D_AHBERR3_M (USB_D_AHBERR3_V << USB_D_AHBERR3_S) +#define USB_D_AHBERR3_V 0x00000001 +#define USB_D_AHBERR3_S 2 +/** USB_D_TIMEOUT3 : R/W1C; bitpos: [3]; default: 0; + * 0x0 : No Timeout interrupt + * 0x1 : Timeout interrupt + */ +#define USB_D_TIMEOUT3 (BIT(3)) +#define USB_D_TIMEOUT3_M (USB_D_TIMEOUT3_V << USB_D_TIMEOUT3_S) +#define USB_D_TIMEOUT3_V 0x00000001 +#define USB_D_TIMEOUT3_S 3 +/** USB_D_INTKNTXFEMP3 : R/W1C; bitpos: [4]; default: 0; + * 0x0 : No IN Token Received when TxFIFO Empty Interrupt + * 0x1 : IN Token Received when TxFIFO Empty Interrupt + */ +#define USB_D_INTKNTXFEMP3 (BIT(4)) +#define USB_D_INTKNTXFEMP3_M (USB_D_INTKNTXFEMP3_V << USB_D_INTKNTXFEMP3_S) +#define USB_D_INTKNTXFEMP3_V 0x00000001 +#define USB_D_INTKNTXFEMP3_S 4 +/** USB_D_INTKNEPMIS3 : R/W1C; bitpos: [5]; default: 0; + * 0x0 : No IN Token Received with EP Mismatch Interrupt + * 0x1 : IN Token Received with EP Mismatch interrupt + */ +#define USB_D_INTKNEPMIS3 (BIT(5)) +#define USB_D_INTKNEPMIS3_M (USB_D_INTKNEPMIS3_V << USB_D_INTKNEPMIS3_S) +#define USB_D_INTKNEPMIS3_V 0x00000001 +#define USB_D_INTKNEPMIS3_S 5 +/** USB_D_INEPNAKEFF3 : R/W1C; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective + * 0x0 : No IN Endpoint NAK Effective interrupt + * 0x1 : IN Endpoint NAK Effective interrupt + */ +#define USB_D_INEPNAKEFF3 (BIT(6)) +#define USB_D_INEPNAKEFF3_M (USB_D_INEPNAKEFF3_V << USB_D_INEPNAKEFF3_S) +#define USB_D_INEPNAKEFF3_V 0x00000001 +#define USB_D_INEPNAKEFF3_S 6 +/** USB_D_TXFEMP3 : RO; bitpos: [7]; default: 0; + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty + * 0x0 : No Transmit FIFO Empty interrupt + * 0x1 : Transmit FIFO Empty interrupt + */ +#define USB_D_TXFEMP3 (BIT(7)) +#define USB_D_TXFEMP3_M (USB_D_TXFEMP3_V << USB_D_TXFEMP3_S) +#define USB_D_TXFEMP3_V 0x00000001 +#define USB_D_TXFEMP3_S 7 +/** USB_D_TXFIFOUNDRN3 : R/W1C; bitpos: [8]; default: 0; + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint + * 0x0 : No Fifo Underrun interrupt + * 0x1 : Fifo Underrun interrupt + */ +#define USB_D_TXFIFOUNDRN3 (BIT(8)) +#define USB_D_TXFIFOUNDRN3_M (USB_D_TXFIFOUNDRN3_V << USB_D_TXFIFOUNDRN3_S) +#define USB_D_TXFIFOUNDRN3_V 0x00000001 +#define USB_D_TXFIFOUNDRN3_S 8 +/** USB_D_BNAINTR3 : R/W1C; bitpos: [9]; default: 0; + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_D_BNAINTR3 (BIT(9)) +#define USB_D_BNAINTR3_M (USB_D_BNAINTR3_V << USB_D_BNAINTR3_S) +#define USB_D_BNAINTR3_V 0x00000001 +#define USB_D_BNAINTR3_S 9 +/** USB_D_PKTDRPSTS3 : R/W1C; bitpos: [11]; default: 0; + * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet + * has been dropped. This bit does not have an associated mask bit and does not + * generate an interrupt + * 0x0 : No interrupt + * 0x1 : Packet Drop Status + */ +#define USB_D_PKTDRPSTS3 (BIT(11)) +#define USB_D_PKTDRPSTS3_M (USB_D_PKTDRPSTS3_V << USB_D_PKTDRPSTS3_S) +#define USB_D_PKTDRPSTS3_V 0x00000001 +#define USB_D_PKTDRPSTS3_S 11 +/** USB_D_BBLEERR3 : R/W1C; bitpos: [12]; default: 0; + * The core generates this interrupt when babble is received for the endpoint + * 0x0 : No interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_D_BBLEERR3 (BIT(12)) +#define USB_D_BBLEERR3_M (USB_D_BBLEERR3_V << USB_D_BBLEERR3_S) +#define USB_D_BBLEERR3_V 0x00000001 +#define USB_D_BBLEERR3_S 12 +/** USB_D_NAKINTRPT3 : R/W1C; bitpos: [13]; default: 0; + * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or + * received by the device + * 0x0 : No interrupt + * 0x1 : NAK Interrupt + */ +#define USB_D_NAKINTRPT3 (BIT(13)) +#define USB_D_NAKINTRPT3_M (USB_D_NAKINTRPT3_V << USB_D_NAKINTRPT3_S) +#define USB_D_NAKINTRPT3_V 0x00000001 +#define USB_D_NAKINTRPT3_S 13 +/** USB_D_NYETINTRPT3 : R/W1C; bitpos: [14]; default: 0; + * NYET Interrupt. The core generates this interrupt when a NYET response is + * transmitted for a non isochronous OUT endpoint + * 0x0 : No interrupt + * 0x1 : NYET Interrupt + */ +#define USB_D_NYETINTRPT3 (BIT(14)) +#define USB_D_NYETINTRPT3_M (USB_D_NYETINTRPT3_V << USB_D_NYETINTRPT3_S) +#define USB_D_NYETINTRPT3_V 0x00000001 +#define USB_D_NYETINTRPT3_S 14 + + +/** USB_DIEPINT4_REG register + * Device IN Endpoint 4 Interrupt Register + */ +#define USB_DIEPINT4_REG (SOC_DPORT_USB_BASE + 0x988) +/** USB_D_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0; + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Completed Interrupt + */ +#define USB_D_XFERCOMPL4 (BIT(0)) +#define USB_D_XFERCOMPL4_M (USB_D_XFERCOMPL4_V << USB_D_XFERCOMPL4_S) +#define USB_D_XFERCOMPL4_V 0x00000001 +#define USB_D_XFERCOMPL4_S 0 +/** USB_D_EPDISBLD4 : R/W1C; bitpos: [1]; default: 0; + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_D_EPDISBLD4 (BIT(1)) +#define USB_D_EPDISBLD4_M (USB_D_EPDISBLD4_V << USB_D_EPDISBLD4_S) +#define USB_D_EPDISBLD4_V 0x00000001 +#define USB_D_EPDISBLD4_S 1 +/** USB_D_AHBERR4 : R/W1C; bitpos: [2]; default: 0; + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_D_AHBERR4 (BIT(2)) +#define USB_D_AHBERR4_M (USB_D_AHBERR4_V << USB_D_AHBERR4_S) +#define USB_D_AHBERR4_V 0x00000001 +#define USB_D_AHBERR4_S 2 +/** USB_D_TIMEOUT4 : R/W1C; bitpos: [3]; default: 0; + * 0x0 : No Timeout interrupt + * 0x1 : Timeout interrupt + */ +#define USB_D_TIMEOUT4 (BIT(3)) +#define USB_D_TIMEOUT4_M (USB_D_TIMEOUT4_V << USB_D_TIMEOUT4_S) +#define USB_D_TIMEOUT4_V 0x00000001 +#define USB_D_TIMEOUT4_S 3 +/** USB_D_INTKNTXFEMP4 : R/W1C; bitpos: [4]; default: 0; + * 0x0 : No IN Token Received when TxFIFO Empty Interrupt + * 0x1 : IN Token Received when TxFIFO Empty Interrupt + */ +#define USB_D_INTKNTXFEMP4 (BIT(4)) +#define USB_D_INTKNTXFEMP4_M (USB_D_INTKNTXFEMP4_V << USB_D_INTKNTXFEMP4_S) +#define USB_D_INTKNTXFEMP4_V 0x00000001 +#define USB_D_INTKNTXFEMP4_S 4 +/** USB_D_INTKNEPMIS4 : R/W1C; bitpos: [5]; default: 0; + * 0x0 : No IN Token Received with EP Mismatch Interrupt + * 0x1 : IN Token Received with EP Mismatch interrupt + */ +#define USB_D_INTKNEPMIS4 (BIT(5)) +#define USB_D_INTKNEPMIS4_M (USB_D_INTKNEPMIS4_V << USB_D_INTKNEPMIS4_S) +#define USB_D_INTKNEPMIS4_V 0x00000001 +#define USB_D_INTKNEPMIS4_S 5 +/** USB_D_INEPNAKEFF4 : R/W1C; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective + * 0x0 : No IN Endpoint NAK Effective interrupt + * 0x1 : IN Endpoint NAK Effective interrupt + */ +#define USB_D_INEPNAKEFF4 (BIT(6)) +#define USB_D_INEPNAKEFF4_M (USB_D_INEPNAKEFF4_V << USB_D_INEPNAKEFF4_S) +#define USB_D_INEPNAKEFF4_V 0x00000001 +#define USB_D_INEPNAKEFF4_S 6 +/** USB_D_TXFEMP4 : RO; bitpos: [7]; default: 0; + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty + * 0x0 : No Transmit FIFO Empty interrupt + * 0x1 : Transmit FIFO Empty interrupt + */ +#define USB_D_TXFEMP4 (BIT(7)) +#define USB_D_TXFEMP4_M (USB_D_TXFEMP4_V << USB_D_TXFEMP4_S) +#define USB_D_TXFEMP4_V 0x00000001 +#define USB_D_TXFEMP4_S 7 +/** USB_D_TXFIFOUNDRN4 : R/W1C; bitpos: [8]; default: 0; + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint + * 0x0 : No Fifo Underrun interrupt + * 0x1 : Fifo Underrun interrupt + */ +#define USB_D_TXFIFOUNDRN4 (BIT(8)) +#define USB_D_TXFIFOUNDRN4_M (USB_D_TXFIFOUNDRN4_V << USB_D_TXFIFOUNDRN4_S) +#define USB_D_TXFIFOUNDRN4_V 0x00000001 +#define USB_D_TXFIFOUNDRN4_S 8 +/** USB_D_BNAINTR4 : R/W1C; bitpos: [9]; default: 0; + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_D_BNAINTR4 (BIT(9)) +#define USB_D_BNAINTR4_M (USB_D_BNAINTR4_V << USB_D_BNAINTR4_S) +#define USB_D_BNAINTR4_V 0x00000001 +#define USB_D_BNAINTR4_S 9 +/** USB_D_PKTDRPSTS4 : R/W1C; bitpos: [11]; default: 0; + * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet + * has been dropped. This bit does not have an associated mask bit and does not + * generate an interrupt + * 0x0 : No interrupt + * 0x1 : Packet Drop Status + */ +#define USB_D_PKTDRPSTS4 (BIT(11)) +#define USB_D_PKTDRPSTS4_M (USB_D_PKTDRPSTS4_V << USB_D_PKTDRPSTS4_S) +#define USB_D_PKTDRPSTS4_V 0x00000001 +#define USB_D_PKTDRPSTS4_S 11 +/** USB_D_BBLEERR4 : R/W1C; bitpos: [12]; default: 0; + * The core generates this interrupt when babble is received for the endpoint + * 0x0 : No interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_D_BBLEERR4 (BIT(12)) +#define USB_D_BBLEERR4_M (USB_D_BBLEERR4_V << USB_D_BBLEERR4_S) +#define USB_D_BBLEERR4_V 0x00000001 +#define USB_D_BBLEERR4_S 12 +/** USB_D_NAKINTRPT4 : R/W1C; bitpos: [13]; default: 0; + * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or + * received by the device + * 0x0 : No interrupt + * 0x1 : NAK Interrupt + */ +#define USB_D_NAKINTRPT4 (BIT(13)) +#define USB_D_NAKINTRPT4_M (USB_D_NAKINTRPT4_V << USB_D_NAKINTRPT4_S) +#define USB_D_NAKINTRPT4_V 0x00000001 +#define USB_D_NAKINTRPT4_S 13 +/** USB_D_NYETINTRPT4 : R/W1C; bitpos: [14]; default: 0; + * NYET Interrupt. The core generates this interrupt when a NYET response is + * transmitted for a non isochronous OUT endpoint + * 0x0 : No interrupt + * 0x1 : NYET Interrupt + */ +#define USB_D_NYETINTRPT4 (BIT(14)) +#define USB_D_NYETINTRPT4_M (USB_D_NYETINTRPT4_V << USB_D_NYETINTRPT4_S) +#define USB_D_NYETINTRPT4_V 0x00000001 +#define USB_D_NYETINTRPT4_S 14 + + +/** USB_DIEPINT5_REG register + * Device IN Endpoint 5 Interrupt Register + */ +#define USB_DIEPINT5_REG (SOC_DPORT_USB_BASE + 0x9a8) +/** USB_D_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0; + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Completed Interrupt + */ +#define USB_D_XFERCOMPL5 (BIT(0)) +#define USB_D_XFERCOMPL5_M (USB_D_XFERCOMPL5_V << USB_D_XFERCOMPL5_S) +#define USB_D_XFERCOMPL5_V 0x00000001 +#define USB_D_XFERCOMPL5_S 0 +/** USB_D_EPDISBLD5 : R/W1C; bitpos: [1]; default: 0; + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_D_EPDISBLD5 (BIT(1)) +#define USB_D_EPDISBLD5_M (USB_D_EPDISBLD5_V << USB_D_EPDISBLD5_S) +#define USB_D_EPDISBLD5_V 0x00000001 +#define USB_D_EPDISBLD5_S 1 +/** USB_D_AHBERR5 : R/W1C; bitpos: [2]; default: 0; + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_D_AHBERR5 (BIT(2)) +#define USB_D_AHBERR5_M (USB_D_AHBERR5_V << USB_D_AHBERR5_S) +#define USB_D_AHBERR5_V 0x00000001 +#define USB_D_AHBERR5_S 2 +/** USB_D_TIMEOUT5 : R/W1C; bitpos: [3]; default: 0; + * 0x0 : No Timeout interrupt + * 0x1 : Timeout interrupt + */ +#define USB_D_TIMEOUT5 (BIT(3)) +#define USB_D_TIMEOUT5_M (USB_D_TIMEOUT5_V << USB_D_TIMEOUT5_S) +#define USB_D_TIMEOUT5_V 0x00000001 +#define USB_D_TIMEOUT5_S 3 +/** USB_D_INTKNTXFEMP5 : R/W1C; bitpos: [4]; default: 0; + * 0x0 : No IN Token Received when TxFIFO Empty Interrupt + * 0x1 : IN Token Received when TxFIFO Empty Interrupt + */ +#define USB_D_INTKNTXFEMP5 (BIT(4)) +#define USB_D_INTKNTXFEMP5_M (USB_D_INTKNTXFEMP5_V << USB_D_INTKNTXFEMP5_S) +#define USB_D_INTKNTXFEMP5_V 0x00000001 +#define USB_D_INTKNTXFEMP5_S 4 +/** USB_D_INTKNEPMIS5 : R/W1C; bitpos: [5]; default: 0; + * 0x0 : No IN Token Received with EP Mismatch Interrupt + * 0x1 : IN Token Received with EP Mismatch interrupt + */ +#define USB_D_INTKNEPMIS5 (BIT(5)) +#define USB_D_INTKNEPMIS5_M (USB_D_INTKNEPMIS5_V << USB_D_INTKNEPMIS5_S) +#define USB_D_INTKNEPMIS5_V 0x00000001 +#define USB_D_INTKNEPMIS5_S 5 +/** USB_D_INEPNAKEFF5 : R/W1C; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective + * 0x0 : No IN Endpoint NAK Effective interrupt + * 0x1 : IN Endpoint NAK Effective interrupt + */ +#define USB_D_INEPNAKEFF5 (BIT(6)) +#define USB_D_INEPNAKEFF5_M (USB_D_INEPNAKEFF5_V << USB_D_INEPNAKEFF5_S) +#define USB_D_INEPNAKEFF5_V 0x00000001 +#define USB_D_INEPNAKEFF5_S 6 +/** USB_D_TXFEMP5 : RO; bitpos: [7]; default: 0; + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty + * 0x0 : No Transmit FIFO Empty interrupt + * 0x1 : Transmit FIFO Empty interrupt + */ +#define USB_D_TXFEMP5 (BIT(7)) +#define USB_D_TXFEMP5_M (USB_D_TXFEMP5_V << USB_D_TXFEMP5_S) +#define USB_D_TXFEMP5_V 0x00000001 +#define USB_D_TXFEMP5_S 7 +/** USB_D_TXFIFOUNDRN5 : R/W1C; bitpos: [8]; default: 0; + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint + * 0x0 : No Fifo Underrun interrupt + * 0x1 : Fifo Underrun interrupt + */ +#define USB_D_TXFIFOUNDRN5 (BIT(8)) +#define USB_D_TXFIFOUNDRN5_M (USB_D_TXFIFOUNDRN5_V << USB_D_TXFIFOUNDRN5_S) +#define USB_D_TXFIFOUNDRN5_V 0x00000001 +#define USB_D_TXFIFOUNDRN5_S 8 +/** USB_D_BNAINTR5 : R/W1C; bitpos: [9]; default: 0; + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_D_BNAINTR5 (BIT(9)) +#define USB_D_BNAINTR5_M (USB_D_BNAINTR5_V << USB_D_BNAINTR5_S) +#define USB_D_BNAINTR5_V 0x00000001 +#define USB_D_BNAINTR5_S 9 +/** USB_D_PKTDRPSTS5 : R/W1C; bitpos: [11]; default: 0; + * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet + * has been dropped. This bit does not have an associated mask bit and does not + * generate an interrupt + * 0x0 : No interrupt + * 0x1 : Packet Drop Status + */ +#define USB_D_PKTDRPSTS5 (BIT(11)) +#define USB_D_PKTDRPSTS5_M (USB_D_PKTDRPSTS5_V << USB_D_PKTDRPSTS5_S) +#define USB_D_PKTDRPSTS5_V 0x00000001 +#define USB_D_PKTDRPSTS5_S 11 +/** USB_D_BBLEERR5 : R/W1C; bitpos: [12]; default: 0; + * The core generates this interrupt when babble is received for the endpoint + * 0x0 : No interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_D_BBLEERR5 (BIT(12)) +#define USB_D_BBLEERR5_M (USB_D_BBLEERR5_V << USB_D_BBLEERR5_S) +#define USB_D_BBLEERR5_V 0x00000001 +#define USB_D_BBLEERR5_S 12 +/** USB_D_NAKINTRPT5 : R/W1C; bitpos: [13]; default: 0; + * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or + * received by the device + * 0x0 : No interrupt + * 0x1 : NAK Interrupt + */ +#define USB_D_NAKINTRPT5 (BIT(13)) +#define USB_D_NAKINTRPT5_M (USB_D_NAKINTRPT5_V << USB_D_NAKINTRPT5_S) +#define USB_D_NAKINTRPT5_V 0x00000001 +#define USB_D_NAKINTRPT5_S 13 +/** USB_D_NYETINTRPT5 : R/W1C; bitpos: [14]; default: 0; + * NYET Interrupt. The core generates this interrupt when a NYET response is + * transmitted for a non isochronous OUT endpoint + * 0x0 : No interrupt + * 0x1 : NYET Interrupt + */ +#define USB_D_NYETINTRPT5 (BIT(14)) +#define USB_D_NYETINTRPT5_M (USB_D_NYETINTRPT5_V << USB_D_NYETINTRPT5_S) +#define USB_D_NYETINTRPT5_V 0x00000001 +#define USB_D_NYETINTRPT5_S 14 + + +/** USB_DIEPINT6_REG register + * Device IN Endpoint 6 Interrupt Register + */ +#define USB_DIEPINT6_REG (SOC_DPORT_USB_BASE + 0x9c8) +/** USB_D_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0; + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Completed Interrupt + */ +#define USB_D_XFERCOMPL6 (BIT(0)) +#define USB_D_XFERCOMPL6_M (USB_D_XFERCOMPL6_V << USB_D_XFERCOMPL6_S) +#define USB_D_XFERCOMPL6_V 0x00000001 +#define USB_D_XFERCOMPL6_S 0 +/** USB_D_EPDISBLD6 : R/W1C; bitpos: [1]; default: 0; + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_D_EPDISBLD6 (BIT(1)) +#define USB_D_EPDISBLD6_M (USB_D_EPDISBLD6_V << USB_D_EPDISBLD6_S) +#define USB_D_EPDISBLD6_V 0x00000001 +#define USB_D_EPDISBLD6_S 1 +/** USB_D_AHBERR6 : R/W1C; bitpos: [2]; default: 0; + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_D_AHBERR6 (BIT(2)) +#define USB_D_AHBERR6_M (USB_D_AHBERR6_V << USB_D_AHBERR6_S) +#define USB_D_AHBERR6_V 0x00000001 +#define USB_D_AHBERR6_S 2 +/** USB_D_TIMEOUT6 : R/W1C; bitpos: [3]; default: 0; + * 0x0 : No Timeout interrupt + * 0x1 : Timeout interrupt + */ +#define USB_D_TIMEOUT6 (BIT(3)) +#define USB_D_TIMEOUT6_M (USB_D_TIMEOUT6_V << USB_D_TIMEOUT6_S) +#define USB_D_TIMEOUT6_V 0x00000001 +#define USB_D_TIMEOUT6_S 3 +/** USB_D_INTKNTXFEMP6 : R/W1C; bitpos: [4]; default: 0; + * 0x0 : No IN Token Received when TxFIFO Empty Interrupt + * 0x1 : IN Token Received when TxFIFO Empty Interrupt + */ +#define USB_D_INTKNTXFEMP6 (BIT(4)) +#define USB_D_INTKNTXFEMP6_M (USB_D_INTKNTXFEMP6_V << USB_D_INTKNTXFEMP6_S) +#define USB_D_INTKNTXFEMP6_V 0x00000001 +#define USB_D_INTKNTXFEMP6_S 4 +/** USB_D_INTKNEPMIS6 : R/W1C; bitpos: [5]; default: 0; + * 0x0 : No IN Token Received with EP Mismatch Interrupt + * 0x1 : IN Token Received with EP Mismatch interrupt + */ +#define USB_D_INTKNEPMIS6 (BIT(5)) +#define USB_D_INTKNEPMIS6_M (USB_D_INTKNEPMIS6_V << USB_D_INTKNEPMIS6_S) +#define USB_D_INTKNEPMIS6_V 0x00000001 +#define USB_D_INTKNEPMIS6_S 5 +/** USB_D_INEPNAKEFF6 : R/W1C; bitpos: [6]; default: 0; + * IN Endpoint NAK Effective + * 0x0 : No IN Endpoint NAK Effective interrupt + * 0x1 : IN Endpoint NAK Effective interrupt + */ +#define USB_D_INEPNAKEFF6 (BIT(6)) +#define USB_D_INEPNAKEFF6_M (USB_D_INEPNAKEFF6_V << USB_D_INEPNAKEFF6_S) +#define USB_D_INEPNAKEFF6_V 0x00000001 +#define USB_D_INEPNAKEFF6_S 6 +/** USB_D_TXFEMP6 : RO; bitpos: [7]; default: 0; + * This interrupt is asserted when the TxFIFO for this endpoint is either half or + * completely empty + * 0x0 : No Transmit FIFO Empty interrupt + * 0x1 : Transmit FIFO Empty interrupt + */ +#define USB_D_TXFEMP6 (BIT(7)) +#define USB_D_TXFEMP6_M (USB_D_TXFEMP6_V << USB_D_TXFEMP6_S) +#define USB_D_TXFEMP6_V 0x00000001 +#define USB_D_TXFEMP6_S 7 +/** USB_D_TXFIFOUNDRN6 : R/W1C; bitpos: [8]; default: 0; + * The core generates this interrupt when it detects a transmit FIFO underrun + * condition in threshold mode for this endpoint + * 0x0 : No Fifo Underrun interrupt + * 0x1 : Fifo Underrun interrupt + */ +#define USB_D_TXFIFOUNDRN6 (BIT(8)) +#define USB_D_TXFIFOUNDRN6_M (USB_D_TXFIFOUNDRN6_V << USB_D_TXFIFOUNDRN6_S) +#define USB_D_TXFIFOUNDRN6_V 0x00000001 +#define USB_D_TXFIFOUNDRN6_S 8 +/** USB_D_BNAINTR6 : R/W1C; bitpos: [9]; default: 0; + * This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates + * this interrupt when the descriptor accessed is not ready for the Core to process, + * such as Host busy or DMA done + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_D_BNAINTR6 (BIT(9)) +#define USB_D_BNAINTR6_M (USB_D_BNAINTR6_V << USB_D_BNAINTR6_S) +#define USB_D_BNAINTR6_V 0x00000001 +#define USB_D_BNAINTR6_S 9 +/** USB_D_PKTDRPSTS6 : R/W1C; bitpos: [11]; default: 0; + * Packet Drop Status. This bit indicates to the application that an ISOC OUT packet + * has been dropped. This bit does not have an associated mask bit and does not + * generate an interrupt + * 0x0 : No interrupt + * 0x1 : Packet Drop Status + */ +#define USB_D_PKTDRPSTS6 (BIT(11)) +#define USB_D_PKTDRPSTS6_M (USB_D_PKTDRPSTS6_V << USB_D_PKTDRPSTS6_S) +#define USB_D_PKTDRPSTS6_V 0x00000001 +#define USB_D_PKTDRPSTS6_S 11 +/** USB_D_BBLEERR6 : R/W1C; bitpos: [12]; default: 0; + * The core generates this interrupt when babble is received for the endpoint + * 0x0 : No interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_D_BBLEERR6 (BIT(12)) +#define USB_D_BBLEERR6_M (USB_D_BBLEERR6_V << USB_D_BBLEERR6_S) +#define USB_D_BBLEERR6_V 0x00000001 +#define USB_D_BBLEERR6_S 12 +/** USB_D_NAKINTRPT6 : R/W1C; bitpos: [13]; default: 0; + * NAK Interrupt. The core generates this interrupt when a NAK is transmitted or + * received by the device + * 0x0 : No interrupt + * 0x1 : NAK Interrupt + */ +#define USB_D_NAKINTRPT6 (BIT(13)) +#define USB_D_NAKINTRPT6_M (USB_D_NAKINTRPT6_V << USB_D_NAKINTRPT6_S) +#define USB_D_NAKINTRPT6_V 0x00000001 +#define USB_D_NAKINTRPT6_S 13 +/** USB_D_NYETINTRPT6 : R/W1C; bitpos: [14]; default: 0; + * NYET Interrupt. The core generates this interrupt when a NYET response is + * transmitted for a non isochronous OUT endpoint + * 0x0 : No interrupt + * 0x1 : NYET Interrupt + */ +#define USB_D_NYETINTRPT6 (BIT(14)) +#define USB_D_NYETINTRPT6_M (USB_D_NYETINTRPT6_V << USB_D_NYETINTRPT6_S) +#define USB_D_NYETINTRPT6_V 0x00000001 +#define USB_D_NYETINTRPT6_S 14 + + +/** USB_DOEPINT0_REG register + * Device OUT Endpoint 0 Interrupt Register + */ +#define USB_DOEPINT0_REG (SOC_DPORT_USB_BASE + 0xb08) +/** USB_XFERCOMPL0 : R/W1C; bitpos: [0]; default: 0; + * Transfer Completed Interrupt + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Complete Interrupt + */ +#define USB_XFERCOMPL0 (BIT(0)) +#define USB_XFERCOMPL0_M (USB_XFERCOMPL0_V << USB_XFERCOMPL0_S) +#define USB_XFERCOMPL0_V 0x00000001 +#define USB_XFERCOMPL0_S 0 +/** USB_EPDISBLD0 : R/W1C; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_EPDISBLD0 (BIT(1)) +#define USB_EPDISBLD0_M (USB_EPDISBLD0_V << USB_EPDISBLD0_S) +#define USB_EPDISBLD0_V 0x00000001 +#define USB_EPDISBLD0_S 1 +/** USB_AHBERR0 : R/W1C; bitpos: [2]; default: 0; + * AHB Error + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_AHBERR0 (BIT(2)) +#define USB_AHBERR0_M (USB_AHBERR0_V << USB_AHBERR0_S) +#define USB_AHBERR0_V 0x00000001 +#define USB_AHBERR0_S 2 +/** USB_SETUP0 : R/W1C; bitpos: [3]; default: 0; + * SETUP Phase Done + * 0x0 : No SETUP Phase Done + * 0x1 : SETUP Phase Done + */ +#define USB_SETUP0 (BIT(3)) +#define USB_SETUP0_M (USB_SETUP0_V << USB_SETUP0_S) +#define USB_SETUP0_V 0x00000001 +#define USB_SETUP0_S 3 +/** USB_OUTTKNEPDIS0 : R/W1C; bitpos: [4]; default: 0; + * OUT Token Received When Endpoint Disabled + * 0x0 : No OUT Token Received When Endpoint Disabled + * 0x1 : OUT Token Received When Endpoint Disabled + */ +#define USB_OUTTKNEPDIS0 (BIT(4)) +#define USB_OUTTKNEPDIS0_M (USB_OUTTKNEPDIS0_V << USB_OUTTKNEPDIS0_S) +#define USB_OUTTKNEPDIS0_V 0x00000001 +#define USB_OUTTKNEPDIS0_S 4 +/** USB_STSPHSERCVD0 : R/W1C; bitpos: [5]; default: 0; + * Status Phase Received for Control Write + * 0x0 : No Status Phase Received for Control Write + * 0x1 : Status Phase Received for Control Write + */ +#define USB_STSPHSERCVD0 (BIT(5)) +#define USB_STSPHSERCVD0_M (USB_STSPHSERCVD0_V << USB_STSPHSERCVD0_S) +#define USB_STSPHSERCVD0_V 0x00000001 +#define USB_STSPHSERCVD0_S 5 +/** USB_BACK2BACKSETUP0 : R/W1C; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received + * 0x0 : No Back-to-Back SETUP Packets Received + * 0x1 : Back-to-Back SETUP Packets Received + */ +#define USB_BACK2BACKSETUP0 (BIT(6)) +#define USB_BACK2BACKSETUP0_M (USB_BACK2BACKSETUP0_V << USB_BACK2BACKSETUP0_S) +#define USB_BACK2BACKSETUP0_V 0x00000001 +#define USB_BACK2BACKSETUP0_S 6 +/** USB_OUTPKTERR0 : R/W1C; bitpos: [8]; default: 0; + * OUT Packet Error + * 0x0 : No OUT Packet Error + * 0x1 : OUT Packet Error + */ +#define USB_OUTPKTERR0 (BIT(8)) +#define USB_OUTPKTERR0_M (USB_OUTPKTERR0_V << USB_OUTPKTERR0_S) +#define USB_OUTPKTERR0_V 0x00000001 +#define USB_OUTPKTERR0_S 8 +/** USB_BNAINTR0 : R/W1C; bitpos: [9]; default: 0; + * Buffer Not Available Interrupt + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_BNAINTR0 (BIT(9)) +#define USB_BNAINTR0_M (USB_BNAINTR0_V << USB_BNAINTR0_S) +#define USB_BNAINTR0_V 0x00000001 +#define USB_BNAINTR0_S 9 +/** USB_PKTDRPSTS0 : R/W1C; bitpos: [11]; default: 0; + * 0x0 : No interrupt + * 0x1 : Packet Drop Status interrupt + */ +#define USB_PKTDRPSTS0 (BIT(11)) +#define USB_PKTDRPSTS0_M (USB_PKTDRPSTS0_V << USB_PKTDRPSTS0_S) +#define USB_PKTDRPSTS0_V 0x00000001 +#define USB_PKTDRPSTS0_S 11 +/** USB_BBLEERR0 : R/W1C; bitpos: [12]; default: 0; + * 0x0 : No BbleErr interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_BBLEERR0 (BIT(12)) +#define USB_BBLEERR0_M (USB_BBLEERR0_V << USB_BBLEERR0_S) +#define USB_BBLEERR0_V 0x00000001 +#define USB_BBLEERR0_S 12 +/** USB_NAKINTRPT0 : R/W1C; bitpos: [13]; default: 0; + * 0x0 : No NAK interrupt + * 0x1 : NAK Interrupt + */ +#define USB_NAKINTRPT0 (BIT(13)) +#define USB_NAKINTRPT0_M (USB_NAKINTRPT0_V << USB_NAKINTRPT0_S) +#define USB_NAKINTRPT0_V 0x00000001 +#define USB_NAKINTRPT0_S 13 +/** USB_NYEPINTRPT0 : R/W1C; bitpos: [14]; default: 0; + * 0x0 : No NYET interrupt + * 0x1 : NYET Interrupt + */ +#define USB_NYEPINTRPT0 (BIT(14)) +#define USB_NYEPINTRPT0_M (USB_NYEPINTRPT0_V << USB_NYEPINTRPT0_S) +#define USB_NYEPINTRPT0_V 0x00000001 +#define USB_NYEPINTRPT0_S 14 +/** USB_STUPPKTRCVD0 : R/W1C; bitpos: [15]; default: 0; + * 0x0 : No Setup packet received + * 0x1 : Setup packet received + */ +#define USB_STUPPKTRCVD0 (BIT(15)) +#define USB_STUPPKTRCVD0_M (USB_STUPPKTRCVD0_V << USB_STUPPKTRCVD0_S) +#define USB_STUPPKTRCVD0_V 0x00000001 +#define USB_STUPPKTRCVD0_S 15 + + +/** USB_DOEPINT1_REG register + * Device OUT Endpoint 1 Interrupt Register + */ +#define USB_DOEPINT1_REG (SOC_DPORT_USB_BASE + 0xb28) +/** USB_XFERCOMPL1 : R/W1C; bitpos: [0]; default: 0; + * Transfer Completed Interrupt + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Complete Interrupt + */ +#define USB_XFERCOMPL1 (BIT(0)) +#define USB_XFERCOMPL1_M (USB_XFERCOMPL1_V << USB_XFERCOMPL1_S) +#define USB_XFERCOMPL1_V 0x00000001 +#define USB_XFERCOMPL1_S 0 +/** USB_EPDISBLD1 : R/W1C; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_EPDISBLD1 (BIT(1)) +#define USB_EPDISBLD1_M (USB_EPDISBLD1_V << USB_EPDISBLD1_S) +#define USB_EPDISBLD1_V 0x00000001 +#define USB_EPDISBLD1_S 1 +/** USB_AHBERR1 : R/W1C; bitpos: [2]; default: 0; + * AHB Error + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_AHBERR1 (BIT(2)) +#define USB_AHBERR1_M (USB_AHBERR1_V << USB_AHBERR1_S) +#define USB_AHBERR1_V 0x00000001 +#define USB_AHBERR1_S 2 +/** USB_SETUP1 : R/W1C; bitpos: [3]; default: 0; + * SETUP Phase Done + * 0x0 : No SETUP Phase Done + * 0x1 : SETUP Phase Done + */ +#define USB_SETUP1 (BIT(3)) +#define USB_SETUP1_M (USB_SETUP1_V << USB_SETUP1_S) +#define USB_SETUP1_V 0x00000001 +#define USB_SETUP1_S 3 +/** USB_OUTTKNEPDIS1 : R/W1C; bitpos: [4]; default: 0; + * OUT Token Received When Endpoint Disabled + * 0x0 : No OUT Token Received When Endpoint Disabled + * 0x1 : OUT Token Received When Endpoint Disabled + */ +#define USB_OUTTKNEPDIS1 (BIT(4)) +#define USB_OUTTKNEPDIS1_M (USB_OUTTKNEPDIS1_V << USB_OUTTKNEPDIS1_S) +#define USB_OUTTKNEPDIS1_V 0x00000001 +#define USB_OUTTKNEPDIS1_S 4 +/** USB_STSPHSERCVD1 : R/W1C; bitpos: [5]; default: 0; + * Status Phase Received for Control Write + * 0x0 : No Status Phase Received for Control Write + * 0x1 : Status Phase Received for Control Write + */ +#define USB_STSPHSERCVD1 (BIT(5)) +#define USB_STSPHSERCVD1_M (USB_STSPHSERCVD1_V << USB_STSPHSERCVD1_S) +#define USB_STSPHSERCVD1_V 0x00000001 +#define USB_STSPHSERCVD1_S 5 +/** USB_BACK2BACKSETUP1 : R/W1C; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received + * 0x0 : No Back-to-Back SETUP Packets Received + * 0x1 : Back-to-Back SETUP Packets Received + */ +#define USB_BACK2BACKSETUP1 (BIT(6)) +#define USB_BACK2BACKSETUP1_M (USB_BACK2BACKSETUP1_V << USB_BACK2BACKSETUP1_S) +#define USB_BACK2BACKSETUP1_V 0x00000001 +#define USB_BACK2BACKSETUP1_S 6 +/** USB_OUTPKTERR1 : R/W1C; bitpos: [8]; default: 0; + * OUT Packet Error + * 0x0 : No OUT Packet Error + * 0x1 : OUT Packet Error + */ +#define USB_OUTPKTERR1 (BIT(8)) +#define USB_OUTPKTERR1_M (USB_OUTPKTERR1_V << USB_OUTPKTERR1_S) +#define USB_OUTPKTERR1_V 0x00000001 +#define USB_OUTPKTERR1_S 8 +/** USB_BNAINTR1 : R/W1C; bitpos: [9]; default: 0; + * Buffer Not Available Interrupt + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_BNAINTR1 (BIT(9)) +#define USB_BNAINTR1_M (USB_BNAINTR1_V << USB_BNAINTR1_S) +#define USB_BNAINTR1_V 0x00000001 +#define USB_BNAINTR1_S 9 +/** USB_PKTDRPSTS1 : R/W1C; bitpos: [11]; default: 0; + * 0x0 : No interrupt + * 0x1 : Packet Drop Status interrupt + */ +#define USB_PKTDRPSTS1 (BIT(11)) +#define USB_PKTDRPSTS1_M (USB_PKTDRPSTS1_V << USB_PKTDRPSTS1_S) +#define USB_PKTDRPSTS1_V 0x00000001 +#define USB_PKTDRPSTS1_S 11 +/** USB_BBLEERR1 : R/W1C; bitpos: [12]; default: 0; + * 0x0 : No BbleErr interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_BBLEERR1 (BIT(12)) +#define USB_BBLEERR1_M (USB_BBLEERR1_V << USB_BBLEERR1_S) +#define USB_BBLEERR1_V 0x00000001 +#define USB_BBLEERR1_S 12 +/** USB_NAKINTRPT1 : R/W1C; bitpos: [13]; default: 0; + * 0x0 : No NAK interrupt + * 0x1 : NAK Interrupt + */ +#define USB_NAKINTRPT1 (BIT(13)) +#define USB_NAKINTRPT1_M (USB_NAKINTRPT1_V << USB_NAKINTRPT1_S) +#define USB_NAKINTRPT1_V 0x00000001 +#define USB_NAKINTRPT1_S 13 +/** USB_NYEPINTRPT1 : R/W1C; bitpos: [14]; default: 0; + * 0x0 : No NYET interrupt + * 0x1 : NYET Interrupt + */ +#define USB_NYEPINTRPT1 (BIT(14)) +#define USB_NYEPINTRPT1_M (USB_NYEPINTRPT1_V << USB_NYEPINTRPT1_S) +#define USB_NYEPINTRPT1_V 0x00000001 +#define USB_NYEPINTRPT1_S 14 +/** USB_STUPPKTRCVD1 : R/W1C; bitpos: [15]; default: 0; + * 0x0 : No Setup packet received + * 0x1 : Setup packet received + */ +#define USB_STUPPKTRCVD1 (BIT(15)) +#define USB_STUPPKTRCVD1_M (USB_STUPPKTRCVD1_V << USB_STUPPKTRCVD1_S) +#define USB_STUPPKTRCVD1_V 0x00000001 +#define USB_STUPPKTRCVD1_S 15 + + +/** USB_DOEPINT2_REG register + * Device OUT Endpoint 2 Interrupt Register + */ +#define USB_DOEPINT2_REG (SOC_DPORT_USB_BASE + 0xb48) +/** USB_XFERCOMPL2 : R/W1C; bitpos: [0]; default: 0; + * Transfer Completed Interrupt + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Complete Interrupt + */ +#define USB_XFERCOMPL2 (BIT(0)) +#define USB_XFERCOMPL2_M (USB_XFERCOMPL2_V << USB_XFERCOMPL2_S) +#define USB_XFERCOMPL2_V 0x00000001 +#define USB_XFERCOMPL2_S 0 +/** USB_EPDISBLD2 : R/W1C; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_EPDISBLD2 (BIT(1)) +#define USB_EPDISBLD2_M (USB_EPDISBLD2_V << USB_EPDISBLD2_S) +#define USB_EPDISBLD2_V 0x00000001 +#define USB_EPDISBLD2_S 1 +/** USB_AHBERR2 : R/W1C; bitpos: [2]; default: 0; + * AHB Error + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_AHBERR2 (BIT(2)) +#define USB_AHBERR2_M (USB_AHBERR2_V << USB_AHBERR2_S) +#define USB_AHBERR2_V 0x00000001 +#define USB_AHBERR2_S 2 +/** USB_SETUP2 : R/W1C; bitpos: [3]; default: 0; + * SETUP Phase Done + * 0x0 : No SETUP Phase Done + * 0x1 : SETUP Phase Done + */ +#define USB_SETUP2 (BIT(3)) +#define USB_SETUP2_M (USB_SETUP2_V << USB_SETUP2_S) +#define USB_SETUP2_V 0x00000001 +#define USB_SETUP2_S 3 +/** USB_OUTTKNEPDIS2 : R/W1C; bitpos: [4]; default: 0; + * OUT Token Received When Endpoint Disabled + * 0x0 : No OUT Token Received When Endpoint Disabled + * 0x1 : OUT Token Received When Endpoint Disabled + */ +#define USB_OUTTKNEPDIS2 (BIT(4)) +#define USB_OUTTKNEPDIS2_M (USB_OUTTKNEPDIS2_V << USB_OUTTKNEPDIS2_S) +#define USB_OUTTKNEPDIS2_V 0x00000001 +#define USB_OUTTKNEPDIS2_S 4 +/** USB_STSPHSERCVD2 : R/W1C; bitpos: [5]; default: 0; + * Status Phase Received for Control Write + * 0x0 : No Status Phase Received for Control Write + * 0x1 : Status Phase Received for Control Write + */ +#define USB_STSPHSERCVD2 (BIT(5)) +#define USB_STSPHSERCVD2_M (USB_STSPHSERCVD2_V << USB_STSPHSERCVD2_S) +#define USB_STSPHSERCVD2_V 0x00000001 +#define USB_STSPHSERCVD2_S 5 +/** USB_BACK2BACKSETUP2 : R/W1C; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received + * 0x0 : No Back-to-Back SETUP Packets Received + * 0x1 : Back-to-Back SETUP Packets Received + */ +#define USB_BACK2BACKSETUP2 (BIT(6)) +#define USB_BACK2BACKSETUP2_M (USB_BACK2BACKSETUP2_V << USB_BACK2BACKSETUP2_S) +#define USB_BACK2BACKSETUP2_V 0x00000001 +#define USB_BACK2BACKSETUP2_S 6 +/** USB_OUTPKTERR2 : R/W1C; bitpos: [8]; default: 0; + * OUT Packet Error + * 0x0 : No OUT Packet Error + * 0x1 : OUT Packet Error + */ +#define USB_OUTPKTERR2 (BIT(8)) +#define USB_OUTPKTERR2_M (USB_OUTPKTERR2_V << USB_OUTPKTERR2_S) +#define USB_OUTPKTERR2_V 0x00000001 +#define USB_OUTPKTERR2_S 8 +/** USB_BNAINTR2 : R/W1C; bitpos: [9]; default: 0; + * Buffer Not Available Interrupt + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_BNAINTR2 (BIT(9)) +#define USB_BNAINTR2_M (USB_BNAINTR2_V << USB_BNAINTR2_S) +#define USB_BNAINTR2_V 0x00000001 +#define USB_BNAINTR2_S 9 +/** USB_PKTDRPSTS2 : R/W1C; bitpos: [11]; default: 0; + * 0x0 : No interrupt + * 0x1 : Packet Drop Status interrupt + */ +#define USB_PKTDRPSTS2 (BIT(11)) +#define USB_PKTDRPSTS2_M (USB_PKTDRPSTS2_V << USB_PKTDRPSTS2_S) +#define USB_PKTDRPSTS2_V 0x00000001 +#define USB_PKTDRPSTS2_S 11 +/** USB_BBLEERR2 : R/W1C; bitpos: [12]; default: 0; + * 0x0 : No BbleErr interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_BBLEERR2 (BIT(12)) +#define USB_BBLEERR2_M (USB_BBLEERR2_V << USB_BBLEERR2_S) +#define USB_BBLEERR2_V 0x00000001 +#define USB_BBLEERR2_S 12 +/** USB_NAKINTRPT2 : R/W1C; bitpos: [13]; default: 0; + * 0x0 : No NAK interrupt + * 0x1 : NAK Interrupt + */ +#define USB_NAKINTRPT2 (BIT(13)) +#define USB_NAKINTRPT2_M (USB_NAKINTRPT2_V << USB_NAKINTRPT2_S) +#define USB_NAKINTRPT2_V 0x00000001 +#define USB_NAKINTRPT2_S 13 +/** USB_NYEPINTRPT2 : R/W1C; bitpos: [14]; default: 0; + * 0x0 : No NYET interrupt + * 0x1 : NYET Interrupt + */ +#define USB_NYEPINTRPT2 (BIT(14)) +#define USB_NYEPINTRPT2_M (USB_NYEPINTRPT2_V << USB_NYEPINTRPT2_S) +#define USB_NYEPINTRPT2_V 0x00000001 +#define USB_NYEPINTRPT2_S 14 +/** USB_STUPPKTRCVD2 : R/W1C; bitpos: [15]; default: 0; + * 0x0 : No Setup packet received + * 0x1 : Setup packet received + */ +#define USB_STUPPKTRCVD2 (BIT(15)) +#define USB_STUPPKTRCVD2_M (USB_STUPPKTRCVD2_V << USB_STUPPKTRCVD2_S) +#define USB_STUPPKTRCVD2_V 0x00000001 +#define USB_STUPPKTRCVD2_S 15 + + +/** USB_DOEPINT3_REG register + * Device OUT Endpoint 3 Interrupt Register + */ +#define USB_DOEPINT3_REG (SOC_DPORT_USB_BASE + 0xb68) +/** USB_XFERCOMPL3 : R/W1C; bitpos: [0]; default: 0; + * Transfer Completed Interrupt + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Complete Interrupt + */ +#define USB_XFERCOMPL3 (BIT(0)) +#define USB_XFERCOMPL3_M (USB_XFERCOMPL3_V << USB_XFERCOMPL3_S) +#define USB_XFERCOMPL3_V 0x00000001 +#define USB_XFERCOMPL3_S 0 +/** USB_EPDISBLD3 : R/W1C; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_EPDISBLD3 (BIT(1)) +#define USB_EPDISBLD3_M (USB_EPDISBLD3_V << USB_EPDISBLD3_S) +#define USB_EPDISBLD3_V 0x00000001 +#define USB_EPDISBLD3_S 1 +/** USB_AHBERR3 : R/W1C; bitpos: [2]; default: 0; + * AHB Error + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_AHBERR3 (BIT(2)) +#define USB_AHBERR3_M (USB_AHBERR3_V << USB_AHBERR3_S) +#define USB_AHBERR3_V 0x00000001 +#define USB_AHBERR3_S 2 +/** USB_SETUP3 : R/W1C; bitpos: [3]; default: 0; + * SETUP Phase Done + * 0x0 : No SETUP Phase Done + * 0x1 : SETUP Phase Done + */ +#define USB_SETUP3 (BIT(3)) +#define USB_SETUP3_M (USB_SETUP3_V << USB_SETUP3_S) +#define USB_SETUP3_V 0x00000001 +#define USB_SETUP3_S 3 +/** USB_OUTTKNEPDIS3 : R/W1C; bitpos: [4]; default: 0; + * OUT Token Received When Endpoint Disabled + * 0x0 : No OUT Token Received When Endpoint Disabled + * 0x1 : OUT Token Received When Endpoint Disabled + */ +#define USB_OUTTKNEPDIS3 (BIT(4)) +#define USB_OUTTKNEPDIS3_M (USB_OUTTKNEPDIS3_V << USB_OUTTKNEPDIS3_S) +#define USB_OUTTKNEPDIS3_V 0x00000001 +#define USB_OUTTKNEPDIS3_S 4 +/** USB_STSPHSERCVD3 : R/W1C; bitpos: [5]; default: 0; + * Status Phase Received for Control Write + * 0x0 : No Status Phase Received for Control Write + * 0x1 : Status Phase Received for Control Write + */ +#define USB_STSPHSERCVD3 (BIT(5)) +#define USB_STSPHSERCVD3_M (USB_STSPHSERCVD3_V << USB_STSPHSERCVD3_S) +#define USB_STSPHSERCVD3_V 0x00000001 +#define USB_STSPHSERCVD3_S 5 +/** USB_BACK2BACKSETUP3 : R/W1C; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received + * 0x0 : No Back-to-Back SETUP Packets Received + * 0x1 : Back-to-Back SETUP Packets Received + */ +#define USB_BACK2BACKSETUP3 (BIT(6)) +#define USB_BACK2BACKSETUP3_M (USB_BACK2BACKSETUP3_V << USB_BACK2BACKSETUP3_S) +#define USB_BACK2BACKSETUP3_V 0x00000001 +#define USB_BACK2BACKSETUP3_S 6 +/** USB_OUTPKTERR3 : R/W1C; bitpos: [8]; default: 0; + * OUT Packet Error + * 0x0 : No OUT Packet Error + * 0x1 : OUT Packet Error + */ +#define USB_OUTPKTERR3 (BIT(8)) +#define USB_OUTPKTERR3_M (USB_OUTPKTERR3_V << USB_OUTPKTERR3_S) +#define USB_OUTPKTERR3_V 0x00000001 +#define USB_OUTPKTERR3_S 8 +/** USB_BNAINTR3 : R/W1C; bitpos: [9]; default: 0; + * Buffer Not Available Interrupt + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_BNAINTR3 (BIT(9)) +#define USB_BNAINTR3_M (USB_BNAINTR3_V << USB_BNAINTR3_S) +#define USB_BNAINTR3_V 0x00000001 +#define USB_BNAINTR3_S 9 +/** USB_PKTDRPSTS3 : R/W1C; bitpos: [11]; default: 0; + * 0x0 : No interrupt + * 0x1 : Packet Drop Status interrupt + */ +#define USB_PKTDRPSTS3 (BIT(11)) +#define USB_PKTDRPSTS3_M (USB_PKTDRPSTS3_V << USB_PKTDRPSTS3_S) +#define USB_PKTDRPSTS3_V 0x00000001 +#define USB_PKTDRPSTS3_S 11 +/** USB_BBLEERR3 : R/W1C; bitpos: [12]; default: 0; + * 0x0 : No BbleErr interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_BBLEERR3 (BIT(12)) +#define USB_BBLEERR3_M (USB_BBLEERR3_V << USB_BBLEERR3_S) +#define USB_BBLEERR3_V 0x00000001 +#define USB_BBLEERR3_S 12 +/** USB_NAKINTRPT3 : R/W1C; bitpos: [13]; default: 0; + * 0x0 : No NAK interrupt + * 0x1 : NAK Interrupt + */ +#define USB_NAKINTRPT3 (BIT(13)) +#define USB_NAKINTRPT3_M (USB_NAKINTRPT3_V << USB_NAKINTRPT3_S) +#define USB_NAKINTRPT3_V 0x00000001 +#define USB_NAKINTRPT3_S 13 +/** USB_NYEPINTRPT3 : R/W1C; bitpos: [14]; default: 0; + * 0x0 : No NYET interrupt + * 0x1 : NYET Interrupt + */ +#define USB_NYEPINTRPT3 (BIT(14)) +#define USB_NYEPINTRPT3_M (USB_NYEPINTRPT3_V << USB_NYEPINTRPT3_S) +#define USB_NYEPINTRPT3_V 0x00000001 +#define USB_NYEPINTRPT3_S 14 +/** USB_STUPPKTRCVD3 : R/W1C; bitpos: [15]; default: 0; + * 0x0 : No Setup packet received + * 0x1 : Setup packet received + */ +#define USB_STUPPKTRCVD3 (BIT(15)) +#define USB_STUPPKTRCVD3_M (USB_STUPPKTRCVD3_V << USB_STUPPKTRCVD3_S) +#define USB_STUPPKTRCVD3_V 0x00000001 +#define USB_STUPPKTRCVD3_S 15 + + +/** USB_DOEPINT4_REG register + * Device OUT Endpoint 4 Interrupt Register + */ +#define USB_DOEPINT4_REG (SOC_DPORT_USB_BASE + 0xb88) +/** USB_XFERCOMPL4 : R/W1C; bitpos: [0]; default: 0; + * Transfer Completed Interrupt + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Complete Interrupt + */ +#define USB_XFERCOMPL4 (BIT(0)) +#define USB_XFERCOMPL4_M (USB_XFERCOMPL4_V << USB_XFERCOMPL4_S) +#define USB_XFERCOMPL4_V 0x00000001 +#define USB_XFERCOMPL4_S 0 +/** USB_EPDISBLD4 : R/W1C; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_EPDISBLD4 (BIT(1)) +#define USB_EPDISBLD4_M (USB_EPDISBLD4_V << USB_EPDISBLD4_S) +#define USB_EPDISBLD4_V 0x00000001 +#define USB_EPDISBLD4_S 1 +/** USB_AHBERR4 : R/W1C; bitpos: [2]; default: 0; + * AHB Error + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_AHBERR4 (BIT(2)) +#define USB_AHBERR4_M (USB_AHBERR4_V << USB_AHBERR4_S) +#define USB_AHBERR4_V 0x00000001 +#define USB_AHBERR4_S 2 +/** USB_SETUP4 : R/W1C; bitpos: [3]; default: 0; + * SETUP Phase Done + * 0x0 : No SETUP Phase Done + * 0x1 : SETUP Phase Done + */ +#define USB_SETUP4 (BIT(3)) +#define USB_SETUP4_M (USB_SETUP4_V << USB_SETUP4_S) +#define USB_SETUP4_V 0x00000001 +#define USB_SETUP4_S 3 +/** USB_OUTTKNEPDIS4 : R/W1C; bitpos: [4]; default: 0; + * OUT Token Received When Endpoint Disabled + * 0x0 : No OUT Token Received When Endpoint Disabled + * 0x1 : OUT Token Received When Endpoint Disabled + */ +#define USB_OUTTKNEPDIS4 (BIT(4)) +#define USB_OUTTKNEPDIS4_M (USB_OUTTKNEPDIS4_V << USB_OUTTKNEPDIS4_S) +#define USB_OUTTKNEPDIS4_V 0x00000001 +#define USB_OUTTKNEPDIS4_S 4 +/** USB_STSPHSERCVD4 : R/W1C; bitpos: [5]; default: 0; + * Status Phase Received for Control Write + * 0x0 : No Status Phase Received for Control Write + * 0x1 : Status Phase Received for Control Write + */ +#define USB_STSPHSERCVD4 (BIT(5)) +#define USB_STSPHSERCVD4_M (USB_STSPHSERCVD4_V << USB_STSPHSERCVD4_S) +#define USB_STSPHSERCVD4_V 0x00000001 +#define USB_STSPHSERCVD4_S 5 +/** USB_BACK2BACKSETUP4 : R/W1C; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received + * 0x0 : No Back-to-Back SETUP Packets Received + * 0x1 : Back-to-Back SETUP Packets Received + */ +#define USB_BACK2BACKSETUP4 (BIT(6)) +#define USB_BACK2BACKSETUP4_M (USB_BACK2BACKSETUP4_V << USB_BACK2BACKSETUP4_S) +#define USB_BACK2BACKSETUP4_V 0x00000001 +#define USB_BACK2BACKSETUP4_S 6 +/** USB_OUTPKTERR4 : R/W1C; bitpos: [8]; default: 0; + * OUT Packet Error + * 0x0 : No OUT Packet Error + * 0x1 : OUT Packet Error + */ +#define USB_OUTPKTERR4 (BIT(8)) +#define USB_OUTPKTERR4_M (USB_OUTPKTERR4_V << USB_OUTPKTERR4_S) +#define USB_OUTPKTERR4_V 0x00000001 +#define USB_OUTPKTERR4_S 8 +/** USB_BNAINTR4 : R/W1C; bitpos: [9]; default: 0; + * Buffer Not Available Interrupt + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_BNAINTR4 (BIT(9)) +#define USB_BNAINTR4_M (USB_BNAINTR4_V << USB_BNAINTR4_S) +#define USB_BNAINTR4_V 0x00000001 +#define USB_BNAINTR4_S 9 +/** USB_PKTDRPSTS4 : R/W1C; bitpos: [11]; default: 0; + * 0x0 : No interrupt + * 0x1 : Packet Drop Status interrupt + */ +#define USB_PKTDRPSTS4 (BIT(11)) +#define USB_PKTDRPSTS4_M (USB_PKTDRPSTS4_V << USB_PKTDRPSTS4_S) +#define USB_PKTDRPSTS4_V 0x00000001 +#define USB_PKTDRPSTS4_S 11 +/** USB_BBLEERR4 : R/W1C; bitpos: [12]; default: 0; + * 0x0 : No BbleErr interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_BBLEERR4 (BIT(12)) +#define USB_BBLEERR4_M (USB_BBLEERR4_V << USB_BBLEERR4_S) +#define USB_BBLEERR4_V 0x00000001 +#define USB_BBLEERR4_S 12 +/** USB_NAKINTRPT4 : R/W1C; bitpos: [13]; default: 0; + * 0x0 : No NAK interrupt + * 0x1 : NAK Interrupt + */ +#define USB_NAKINTRPT4 (BIT(13)) +#define USB_NAKINTRPT4_M (USB_NAKINTRPT4_V << USB_NAKINTRPT4_S) +#define USB_NAKINTRPT4_V 0x00000001 +#define USB_NAKINTRPT4_S 13 +/** USB_NYEPINTRPT4 : R/W1C; bitpos: [14]; default: 0; + * 0x0 : No NYET interrupt + * 0x1 : NYET Interrupt + */ +#define USB_NYEPINTRPT4 (BIT(14)) +#define USB_NYEPINTRPT4_M (USB_NYEPINTRPT4_V << USB_NYEPINTRPT4_S) +#define USB_NYEPINTRPT4_V 0x00000001 +#define USB_NYEPINTRPT4_S 14 +/** USB_STUPPKTRCVD4 : R/W1C; bitpos: [15]; default: 0; + * 0x0 : No Setup packet received + * 0x1 : Setup packet received + */ +#define USB_STUPPKTRCVD4 (BIT(15)) +#define USB_STUPPKTRCVD4_M (USB_STUPPKTRCVD4_V << USB_STUPPKTRCVD4_S) +#define USB_STUPPKTRCVD4_V 0x00000001 +#define USB_STUPPKTRCVD4_S 15 + + +/** USB_DOEPINT5_REG register + * Device OUT Endpoint 5 Interrupt Register + */ +#define USB_DOEPINT5_REG (SOC_DPORT_USB_BASE + 0xba8) +/** USB_XFERCOMPL5 : R/W1C; bitpos: [0]; default: 0; + * Transfer Completed Interrupt + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Complete Interrupt + */ +#define USB_XFERCOMPL5 (BIT(0)) +#define USB_XFERCOMPL5_M (USB_XFERCOMPL5_V << USB_XFERCOMPL5_S) +#define USB_XFERCOMPL5_V 0x00000001 +#define USB_XFERCOMPL5_S 0 +/** USB_EPDISBLD5 : R/W1C; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_EPDISBLD5 (BIT(1)) +#define USB_EPDISBLD5_M (USB_EPDISBLD5_V << USB_EPDISBLD5_S) +#define USB_EPDISBLD5_V 0x00000001 +#define USB_EPDISBLD5_S 1 +/** USB_AHBERR5 : R/W1C; bitpos: [2]; default: 0; + * AHB Error + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_AHBERR5 (BIT(2)) +#define USB_AHBERR5_M (USB_AHBERR5_V << USB_AHBERR5_S) +#define USB_AHBERR5_V 0x00000001 +#define USB_AHBERR5_S 2 +/** USB_SETUP5 : R/W1C; bitpos: [3]; default: 0; + * SETUP Phase Done + * 0x0 : No SETUP Phase Done + * 0x1 : SETUP Phase Done + */ +#define USB_SETUP5 (BIT(3)) +#define USB_SETUP5_M (USB_SETUP5_V << USB_SETUP5_S) +#define USB_SETUP5_V 0x00000001 +#define USB_SETUP5_S 3 +/** USB_OUTTKNEPDIS5 : R/W1C; bitpos: [4]; default: 0; + * OUT Token Received When Endpoint Disabled + * 0x0 : No OUT Token Received When Endpoint Disabled + * 0x1 : OUT Token Received When Endpoint Disabled + */ +#define USB_OUTTKNEPDIS5 (BIT(4)) +#define USB_OUTTKNEPDIS5_M (USB_OUTTKNEPDIS5_V << USB_OUTTKNEPDIS5_S) +#define USB_OUTTKNEPDIS5_V 0x00000001 +#define USB_OUTTKNEPDIS5_S 4 +/** USB_STSPHSERCVD5 : R/W1C; bitpos: [5]; default: 0; + * Status Phase Received for Control Write + * 0x0 : No Status Phase Received for Control Write + * 0x1 : Status Phase Received for Control Write + */ +#define USB_STSPHSERCVD5 (BIT(5)) +#define USB_STSPHSERCVD5_M (USB_STSPHSERCVD5_V << USB_STSPHSERCVD5_S) +#define USB_STSPHSERCVD5_V 0x00000001 +#define USB_STSPHSERCVD5_S 5 +/** USB_BACK2BACKSETUP5 : R/W1C; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received + * 0x0 : No Back-to-Back SETUP Packets Received + * 0x1 : Back-to-Back SETUP Packets Received + */ +#define USB_BACK2BACKSETUP5 (BIT(6)) +#define USB_BACK2BACKSETUP5_M (USB_BACK2BACKSETUP5_V << USB_BACK2BACKSETUP5_S) +#define USB_BACK2BACKSETUP5_V 0x00000001 +#define USB_BACK2BACKSETUP5_S 6 +/** USB_OUTPKTERR5 : R/W1C; bitpos: [8]; default: 0; + * OUT Packet Error + * 0x0 : No OUT Packet Error + * 0x1 : OUT Packet Error + */ +#define USB_OUTPKTERR5 (BIT(8)) +#define USB_OUTPKTERR5_M (USB_OUTPKTERR5_V << USB_OUTPKTERR5_S) +#define USB_OUTPKTERR5_V 0x00000001 +#define USB_OUTPKTERR5_S 8 +/** USB_BNAINTR5 : R/W1C; bitpos: [9]; default: 0; + * Buffer Not Available Interrupt + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_BNAINTR5 (BIT(9)) +#define USB_BNAINTR5_M (USB_BNAINTR5_V << USB_BNAINTR5_S) +#define USB_BNAINTR5_V 0x00000001 +#define USB_BNAINTR5_S 9 +/** USB_PKTDRPSTS5 : R/W1C; bitpos: [11]; default: 0; + * 0x0 : No interrupt + * 0x1 : Packet Drop Status interrupt + */ +#define USB_PKTDRPSTS5 (BIT(11)) +#define USB_PKTDRPSTS5_M (USB_PKTDRPSTS5_V << USB_PKTDRPSTS5_S) +#define USB_PKTDRPSTS5_V 0x00000001 +#define USB_PKTDRPSTS5_S 11 +/** USB_BBLEERR5 : R/W1C; bitpos: [12]; default: 0; + * 0x0 : No BbleErr interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_BBLEERR5 (BIT(12)) +#define USB_BBLEERR5_M (USB_BBLEERR5_V << USB_BBLEERR5_S) +#define USB_BBLEERR5_V 0x00000001 +#define USB_BBLEERR5_S 12 +/** USB_NAKINTRPT5 : R/W1C; bitpos: [13]; default: 0; + * 0x0 : No NAK interrupt + * 0x1 : NAK Interrupt + */ +#define USB_NAKINTRPT5 (BIT(13)) +#define USB_NAKINTRPT5_M (USB_NAKINTRPT5_V << USB_NAKINTRPT5_S) +#define USB_NAKINTRPT5_V 0x00000001 +#define USB_NAKINTRPT5_S 13 +/** USB_NYEPINTRPT5 : R/W1C; bitpos: [14]; default: 0; + * 0x0 : No NYET interrupt + * 0x1 : NYET Interrupt + */ +#define USB_NYEPINTRPT5 (BIT(14)) +#define USB_NYEPINTRPT5_M (USB_NYEPINTRPT5_V << USB_NYEPINTRPT5_S) +#define USB_NYEPINTRPT5_V 0x00000001 +#define USB_NYEPINTRPT5_S 14 +/** USB_STUPPKTRCVD5 : R/W1C; bitpos: [15]; default: 0; + * 0x0 : No Setup packet received + * 0x1 : Setup packet received + */ +#define USB_STUPPKTRCVD5 (BIT(15)) +#define USB_STUPPKTRCVD5_M (USB_STUPPKTRCVD5_V << USB_STUPPKTRCVD5_S) +#define USB_STUPPKTRCVD5_V 0x00000001 +#define USB_STUPPKTRCVD5_S 15 + + +/** USB_DOEPINT6_REG register + * Device OUT Endpoint 6 Interrupt Register + */ +#define USB_DOEPINT6_REG (SOC_DPORT_USB_BASE + 0xbc8) +/** USB_XFERCOMPL6 : R/W1C; bitpos: [0]; default: 0; + * Transfer Completed Interrupt + * 0x0 : No Transfer Complete Interrupt + * 0x1 : Transfer Complete Interrupt + */ +#define USB_XFERCOMPL6 (BIT(0)) +#define USB_XFERCOMPL6_M (USB_XFERCOMPL6_V << USB_XFERCOMPL6_S) +#define USB_XFERCOMPL6_V 0x00000001 +#define USB_XFERCOMPL6_S 0 +/** USB_EPDISBLD6 : R/W1C; bitpos: [1]; default: 0; + * Endpoint Disabled Interrupt + * 0x0 : No Endpoint Disabled Interrupt + * 0x1 : Endpoint Disabled Interrupt + */ +#define USB_EPDISBLD6 (BIT(1)) +#define USB_EPDISBLD6_M (USB_EPDISBLD6_V << USB_EPDISBLD6_S) +#define USB_EPDISBLD6_V 0x00000001 +#define USB_EPDISBLD6_S 1 +/** USB_AHBERR6 : R/W1C; bitpos: [2]; default: 0; + * AHB Error + * 0x0 : No AHB Error Interrupt + * 0x1 : AHB Error interrupt + */ +#define USB_AHBERR6 (BIT(2)) +#define USB_AHBERR6_M (USB_AHBERR6_V << USB_AHBERR6_S) +#define USB_AHBERR6_V 0x00000001 +#define USB_AHBERR6_S 2 +/** USB_SETUP6 : R/W1C; bitpos: [3]; default: 0; + * SETUP Phase Done + * 0x0 : No SETUP Phase Done + * 0x1 : SETUP Phase Done + */ +#define USB_SETUP6 (BIT(3)) +#define USB_SETUP6_M (USB_SETUP6_V << USB_SETUP6_S) +#define USB_SETUP6_V 0x00000001 +#define USB_SETUP6_S 3 +/** USB_OUTTKNEPDIS6 : R/W1C; bitpos: [4]; default: 0; + * OUT Token Received When Endpoint Disabled + * 0x0 : No OUT Token Received When Endpoint Disabled + * 0x1 : OUT Token Received When Endpoint Disabled + */ +#define USB_OUTTKNEPDIS6 (BIT(4)) +#define USB_OUTTKNEPDIS6_M (USB_OUTTKNEPDIS6_V << USB_OUTTKNEPDIS6_S) +#define USB_OUTTKNEPDIS6_V 0x00000001 +#define USB_OUTTKNEPDIS6_S 4 +/** USB_STSPHSERCVD6 : R/W1C; bitpos: [5]; default: 0; + * Status Phase Received for Control Write + * 0x0 : No Status Phase Received for Control Write + * 0x1 : Status Phase Received for Control Write + */ +#define USB_STSPHSERCVD6 (BIT(5)) +#define USB_STSPHSERCVD6_M (USB_STSPHSERCVD6_V << USB_STSPHSERCVD6_S) +#define USB_STSPHSERCVD6_V 0x00000001 +#define USB_STSPHSERCVD6_S 5 +/** USB_BACK2BACKSETUP6 : R/W1C; bitpos: [6]; default: 0; + * Back-to-Back SETUP Packets Received + * 0x0 : No Back-to-Back SETUP Packets Received + * 0x1 : Back-to-Back SETUP Packets Received + */ +#define USB_BACK2BACKSETUP6 (BIT(6)) +#define USB_BACK2BACKSETUP6_M (USB_BACK2BACKSETUP6_V << USB_BACK2BACKSETUP6_S) +#define USB_BACK2BACKSETUP6_V 0x00000001 +#define USB_BACK2BACKSETUP6_S 6 +/** USB_OUTPKTERR6 : R/W1C; bitpos: [8]; default: 0; + * OUT Packet Error + * 0x0 : No OUT Packet Error + * 0x1 : OUT Packet Error + */ +#define USB_OUTPKTERR6 (BIT(8)) +#define USB_OUTPKTERR6_M (USB_OUTPKTERR6_V << USB_OUTPKTERR6_S) +#define USB_OUTPKTERR6_V 0x00000001 +#define USB_OUTPKTERR6_S 8 +/** USB_BNAINTR6 : R/W1C; bitpos: [9]; default: 0; + * Buffer Not Available Interrupt + * 0x0 : No BNA interrupt + * 0x1 : BNA interrupt + */ +#define USB_BNAINTR6 (BIT(9)) +#define USB_BNAINTR6_M (USB_BNAINTR6_V << USB_BNAINTR6_S) +#define USB_BNAINTR6_V 0x00000001 +#define USB_BNAINTR6_S 9 +/** USB_PKTDRPSTS6 : R/W1C; bitpos: [11]; default: 0; + * 0x0 : No interrupt + * 0x1 : Packet Drop Status interrupt + */ +#define USB_PKTDRPSTS6 (BIT(11)) +#define USB_PKTDRPSTS6_M (USB_PKTDRPSTS6_V << USB_PKTDRPSTS6_S) +#define USB_PKTDRPSTS6_V 0x00000001 +#define USB_PKTDRPSTS6_S 11 +/** USB_BBLEERR6 : R/W1C; bitpos: [12]; default: 0; + * 0x0 : No BbleErr interrupt + * 0x1 : BbleErr interrupt + */ +#define USB_BBLEERR6 (BIT(12)) +#define USB_BBLEERR6_M (USB_BBLEERR6_V << USB_BBLEERR6_S) +#define USB_BBLEERR6_V 0x00000001 +#define USB_BBLEERR6_S 12 +/** USB_NAKINTRPT6 : R/W1C; bitpos: [13]; default: 0; + * 0x0 : No NAK interrupt + * 0x1 : NAK Interrupt + */ +#define USB_NAKINTRPT6 (BIT(13)) +#define USB_NAKINTRPT6_M (USB_NAKINTRPT6_V << USB_NAKINTRPT6_S) +#define USB_NAKINTRPT6_V 0x00000001 +#define USB_NAKINTRPT6_S 13 +/** USB_NYEPINTRPT6 : R/W1C; bitpos: [14]; default: 0; + * 0x0 : No NYET interrupt + * 0x1 : NYET Interrupt + */ +#define USB_NYEPINTRPT6 (BIT(14)) +#define USB_NYEPINTRPT6_M (USB_NYEPINTRPT6_V << USB_NYEPINTRPT6_S) +#define USB_NYEPINTRPT6_V 0x00000001 +#define USB_NYEPINTRPT6_S 14 +/** USB_STUPPKTRCVD6 : R/W1C; bitpos: [15]; default: 0; + * 0x0 : No Setup packet received + * 0x1 : Setup packet received + */ +#define USB_STUPPKTRCVD6 (BIT(15)) +#define USB_STUPPKTRCVD6_M (USB_STUPPKTRCVD6_V << USB_STUPPKTRCVD6_S) +#define USB_STUPPKTRCVD6_V 0x00000001 +#define USB_STUPPKTRCVD6_S 15 + + + + +/** configuration registers */ +/** USB_GAHBCFG_REG register + * AHB Configuration Register + */ +#define USB_GAHBCFG_REG (SOC_DPORT_USB_BASE + 0x8) +/** USB_GLBLLNTRMSK : R/W; bitpos: [0]; default: 0; + * 1'b0: Mask the interrupt assertion to the application. + * 1'b1: Unmask the interrupt assertion to the application + */ +#define USB_GLBLLNTRMSK (BIT(0)) +#define USB_GLBLLNTRMSK_M (USB_GLBLLNTRMSK_V << USB_GLBLLNTRMSK_S) +#define USB_GLBLLNTRMSK_V 0x00000001 +#define USB_GLBLLNTRMSK_S 0 +/** USB_HBSTLEN : R/W; bitpos: [5:1]; default: 0; + * this field is used in Internal DMA modes + * 4'b0000 Single + * 4'b0001: INCR + * 4'b0011 INCR4 + * 4'b0101 INCR8 + * 4'b0111 INCR16 + * Others: Reserved + */ +#define USB_HBSTLEN 0x0000000F +#define USB_HBSTLEN_M (USB_HBSTLEN_V << USB_HBSTLEN_S) +#define USB_HBSTLEN_V 0x0000000F +#define USB_HBSTLEN_S 1 +/** USB_DMAEN : R/W; bitpos: [5]; default: 0; + * This bit is always 0 when Slave-Only mode has been selected + * 1'b0:Core operates in Slave mode + * 1'b1:Core operates in a DMA mode + */ +#define USB_DMAEN (BIT(5)) +#define USB_DMAEN_M (USB_DMAEN_V << USB_DMAEN_S) +#define USB_DMAEN_V 0x00000001 +#define USB_DMAEN_S 5 +/** USB_NPTXFEMPLVL : R/W; bitpos: [7]; default: 0; + * Non-Periodic TxFIFO Empty Level + * 1'b0: DIEPINTn_REG.REG_TXFEMP interrupt indicates that the Non-Periodic TxFIFO is + * half empty or that the IN Endpoint TxFIFO is half empty + * 1'b1: GINTSTS_REG.USB_NPTXFEMP interrupt indicates that the Non-Periodic TxFIFO is + * completely empty or that the IN Endpoint TxFIFO is completely empty + */ +#define USB_NPTXFEMPLVL (BIT(7)) +#define USB_NPTXFEMPLVL_M (USB_NPTXFEMPLVL_V << USB_NPTXFEMPLVL_S) +#define USB_NPTXFEMPLVL_V 0x00000001 +#define USB_NPTXFEMPLVL_S 7 +/** USB_PTXFEMPLVL : R/W; bitpos: [8]; default: 0; + * Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt + * register (GINTSTS_REG.USB_PTXFEMP) is triggered. This bit is used only in Slave + * mode + * 1'b0: GINTSTS_REG.USB_PTXFEMP interrupt indicates that the Periodic TxFIFO is half + * empty + * 1'b1: GINTSTS_REG.USB_PTXFEMP interrupt indicates that the Periodic TxFIFO is + * completely empty + */ +#define USB_PTXFEMPLVL (BIT(8)) +#define USB_PTXFEMPLVL_M (USB_PTXFEMPLVL_V << USB_PTXFEMPLVL_S) +#define USB_PTXFEMPLVL_V 0x00000001 +#define USB_PTXFEMPLVL_S 8 +/** USB_REMMEMSUPP : R/W; bitpos: [21]; default: 0; + * Remote Memory Support (RemMemSupp) This bit is programmed to enable the + * functionality to wait for thesystem DMA Done Signal for the DMA Write Transfers + * 1'b0:Remote Memory Support Feature disabled + * 1'b1:Remote Memory Support Feature enabled + */ +#define USB_REMMEMSUPP (BIT(21)) +#define USB_REMMEMSUPP_M (USB_REMMEMSUPP_V << USB_REMMEMSUPP_S) +#define USB_REMMEMSUPP_V 0x00000001 +#define USB_REMMEMSUPP_S 21 +/** USB_NOTIALLDMAWRIT : R/W; bitpos: [22]; default: 0; + * Notify All DMA Write Transactions (NotiAllDmaWrit) This bit is programmed to enable + * the System DMA Done functionality for all the DMA write Transactions corresponding + * to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1 + */ +#define USB_NOTIALLDMAWRIT (BIT(22)) +#define USB_NOTIALLDMAWRIT_M (USB_NOTIALLDMAWRIT_V << USB_NOTIALLDMAWRIT_S) +#define USB_NOTIALLDMAWRIT_V 0x00000001 +#define USB_NOTIALLDMAWRIT_S 22 +/** USB_AHBSINGLE : R/W; bitpos: [23]; default: 0; + * AHB Single Support (AHBSingle) This bit when programmed supports Single transfers + * for the remaining data in a transfer when the core is operating in DMA mode + * 1'b0: The remaining data in the transfer is sent using INCR burst size + * 1'b1: The remaining data in the transfer is sent using Single burst size + */ +#define USB_AHBSINGLE (BIT(23)) +#define USB_AHBSINGLE_M (USB_AHBSINGLE_V << USB_AHBSINGLE_S) +#define USB_AHBSINGLE_V 0x00000001 +#define USB_AHBSINGLE_S 23 +/** USB_INVDESCENDIANESS : R/W; bitpos: [24]; default: 0; + * Invert Descriptor Endianess + * 1'b0: Descriptor Endianness is same as AHB Master Endianness + * 1'b1:Invert Descriptor Endianess according to AHB Master endianness + */ +#define USB_INVDESCENDIANESS (BIT(24)) +#define USB_INVDESCENDIANESS_M (USB_INVDESCENDIANESS_V << USB_INVDESCENDIANESS_S) +#define USB_INVDESCENDIANESS_V 0x00000001 +#define USB_INVDESCENDIANESS_S 24 + + +/** USB_GUSBCFG_REG register + * USB Configuration Register + */ +#define USB_GUSBCFG_REG (SOC_DPORT_USB_BASE + 0xc) +/** USB_TOUTCAL : R/W; bitpos: [3:0]; default: 0; + * FS Timeout Calibration + */ +#define USB_TOUTCAL 0x00000007 +#define USB_TOUTCAL_M (USB_TOUTCAL_V << USB_TOUTCAL_S) +#define USB_TOUTCAL_V 0x00000007 +#define USB_TOUTCAL_S 0 +/** USB_PHYIF : R/W; bitpos: [3]; default: 0; + * The application uses this bit to configure the core to support a + * UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is + * chosen, this must be Set to 8-bit mode + * 1'b0: 8 bits + * 1'b1: 16 bits + */ +#define USB_PHYIF (BIT(3)) +#define USB_PHYIF_M (USB_PHYIF_V << USB_PHYIF_S) +#define USB_PHYIF_V 0x00000001 +#define USB_PHYIF_S 3 +/** USB_ULPI_UTMI_SEL : RO; bitpos: [4]; default: 0; + * 1'b0: UTMI+ Interface + * 1'b1: ULPI Interface + */ +#define USB_ULPI_UTMI_SEL (BIT(4)) +#define USB_ULPI_UTMI_SEL_M (USB_ULPI_UTMI_SEL_V << USB_ULPI_UTMI_SEL_S) +#define USB_ULPI_UTMI_SEL_V 0x00000001 +#define USB_ULPI_UTMI_SEL_S 4 +/** USB_FSINTF : R/W; bitpos: [5]; default: 0; + * 1'b0: 6-pin unidirectional full-speed serial interface + * 1'b1: 3-pin bidirectional full-speed serial interface + */ +#define USB_FSINTF (BIT(5)) +#define USB_FSINTF_M (USB_FSINTF_V << USB_FSINTF_S) +#define USB_FSINTF_V 0x00000001 +#define USB_FSINTF_S 5 +/** USB_PHYSEL : RO; bitpos: [6]; default: 1; + * 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY + * 1'b1: USB 1.1 full-speed serial transceiver + */ +#define USB_PHYSEL (BIT(6)) +#define USB_PHYSEL_M (USB_PHYSEL_V << USB_PHYSEL_S) +#define USB_PHYSEL_V 0x00000001 +#define USB_PHYSEL_S 6 +/** USB_SRPCAP : R/W; bitpos: [8]; default: 0; + * 1'b0: SRP capability is not enabled + * 1'b1: SRP capability is enabled + */ +#define USB_SRPCAP (BIT(8)) +#define USB_SRPCAP_M (USB_SRPCAP_V << USB_SRPCAP_S) +#define USB_SRPCAP_V 0x00000001 +#define USB_SRPCAP_S 8 +/** USB_HNPCAP : R/W; bitpos: [9]; default: 0; + * 1'b0: HNP capability is not enabled + * 1'b1: HNP capability is enabled + */ +#define USB_HNPCAP (BIT(9)) +#define USB_HNPCAP_M (USB_HNPCAP_V << USB_HNPCAP_S) +#define USB_HNPCAP_V 0x00000001 +#define USB_HNPCAP_S 9 +/** USB_USBTRDTIM : R/W; bitpos: [14:10]; default: 5; + * 4'h5: When the MAC interface is 16-bit UTMI+ + * 4'h9: When the MAC interface is 8-bit UTMI+ + */ +#define USB_USBTRDTIM 0x0000000F +#define USB_USBTRDTIM_M (USB_USBTRDTIM_V << USB_USBTRDTIM_S) +#define USB_USBTRDTIM_V 0x0000000F +#define USB_USBTRDTIM_S 10 +/** USB_TERMSELDLPULSE : R/W; bitpos: [22]; default: 0; + * TermSel DLine Pulsing Selection + * 1'b0: Data line pulsing using utmi_txvalid (Default) + * 1'b1: Data line pulsing using utmi_termsel + */ +#define USB_TERMSELDLPULSE (BIT(22)) +#define USB_TERMSELDLPULSE_M (USB_TERMSELDLPULSE_V << USB_TERMSELDLPULSE_S) +#define USB_TERMSELDLPULSE_V 0x00000001 +#define USB_TERMSELDLPULSE_S 22 +/** USB_TXENDDELAY : R/W; bitpos: [28]; default: 0; + * 1'b0 : Normal Mode + * 1'b1 : Tx End delay + */ +#define USB_TXENDDELAY (BIT(28)) +#define USB_TXENDDELAY_M (USB_TXENDDELAY_V << USB_TXENDDELAY_S) +#define USB_TXENDDELAY_V 0x00000001 +#define USB_TXENDDELAY_S 28 +/** USB_FORCEHSTMODE : R/W; bitpos: [29]; default: 0; + * 1'b0 : Normal Mode + * 1'b1 : Force Host Mode + */ +#define USB_FORCEHSTMODE (BIT(29)) +#define USB_FORCEHSTMODE_M (USB_FORCEHSTMODE_V << USB_FORCEHSTMODE_S) +#define USB_FORCEHSTMODE_V 0x00000001 +#define USB_FORCEHSTMODE_S 29 +/** USB_FORCEDEVMODE : R/W; bitpos: [30]; default: 0; + * 1'b0 : Normal Mode + * 1'b1 : Force Device Mode + */ +#define USB_FORCEDEVMODE (BIT(30)) +#define USB_FORCEDEVMODE_M (USB_FORCEDEVMODE_V << USB_FORCEDEVMODE_S) +#define USB_FORCEDEVMODE_V 0x00000001 +#define USB_FORCEDEVMODE_S 30 +/** USB_CORRUPTTXPKT : R/W; bitpos: [31]; default: 0; + * This bit is for debug purposes only. Never Set this bit to 1. The application + * should always write 1'b0 to this bit + * 1'b0:Normal Mode + * 1'b1:Debug Mode + */ +#define USB_CORRUPTTXPKT (BIT(31)) +#define USB_CORRUPTTXPKT_M (USB_CORRUPTTXPKT_V << USB_CORRUPTTXPKT_S) +#define USB_CORRUPTTXPKT_V 0x00000001 +#define USB_CORRUPTTXPKT_S 31 + + +/** USB_GRSTCTL_REG register + * Reset Register + */ +#define USB_GRSTCTL_REG (SOC_DPORT_USB_BASE + 0x10) +/** USB_CSFTRST : R_WS_SC; bitpos: [0]; default: 0; + * Core Soft Reset + */ +#define USB_CSFTRST (BIT(0)) +#define USB_CSFTRST_M (USB_CSFTRST_V << USB_CSFTRST_S) +#define USB_CSFTRST_V 0x00000001 +#define USB_CSFTRST_S 0 +/** USB_PIUFSSFTRST : R_WS_SC; bitpos: [1]; default: 0; + * 1'b0: No Reset + * 1'b1:PIU FS Dedicated Controller Soft Reset + */ +#define USB_PIUFSSFTRST (BIT(1)) +#define USB_PIUFSSFTRST_M (USB_PIUFSSFTRST_V << USB_PIUFSSFTRST_S) +#define USB_PIUFSSFTRST_V 0x00000001 +#define USB_PIUFSSFTRST_S 1 +/** USB_FRMCNTRRST : R/W1S; bitpos: [2]; default: 0; + * Host only. Host Frame Counter Reset.The application writes this bit to reset the + * (micro)Frame number counter inside the core. When the (micro)Frame counter is + * reset, the subsequent SOF sent out by the core has a (micro)Frame number of 0 + */ +#define USB_FRMCNTRRST (BIT(2)) +#define USB_FRMCNTRRST_M (USB_FRMCNTRRST_V << USB_FRMCNTRRST_S) +#define USB_FRMCNTRRST_V 0x00000001 +#define USB_FRMCNTRRST_S 2 +/** USB_RXFFLSH : R/W1S; bitpos: [4]; default: 0; + * RxFIFO Flush. The application can flush the entire RxFIFO using this bit, but must + * first ensure that the core is not in the middle of a transaction.The application + * must only write to this bit after checking that the controller is neither reading + * from the RxFIFO nor writing to the RxFIFO + * 1'b0:Does not flush the entire RxFIFO + * 1'b1:flushes the entire RxFIFO + */ +#define USB_RXFFLSH (BIT(4)) +#define USB_RXFFLSH_M (USB_RXFFLSH_V << USB_RXFFLSH_S) +#define USB_RXFFLSH_V 0x00000001 +#define USB_RXFFLSH_S 4 +/** USB_TXFFLSH : R/W1S; bitpos: [5]; default: 0; + * TxFIFO Flush.This bit selectively flushes a single or all transmit FIFOs, but + * cannot do so If the core is in the midst of a transaction.The application must + * write this bit only after checking that the core is neither writing to the TxFIFO + * nor reading from the TxFIFO. + */ +#define USB_TXFFLSH (BIT(5)) +#define USB_TXFFLSH_M (USB_TXFFLSH_V << USB_TXFFLSH_S) +#define USB_TXFFLSH_V 0x00000001 +#define USB_TXFFLSH_S 5 +/** USB_TXFNUM : R/W; bitpos: [11:6]; default: 0; + * TxFIFO Number.This is the FIFO number that must be flushed using the TxFIFO Flush + * bit. This field must not be changed until the core clears the TxFIFO Flush bit + */ +#define USB_TXFNUM 0x0000001F +#define USB_TXFNUM_M (USB_TXFNUM_V << USB_TXFNUM_S) +#define USB_TXFNUM_V 0x0000001F +#define USB_TXFNUM_S 6 +/** USB_DMAREQ : RO; bitpos: [30]; default: 0; + * DMA Request Signal + * 1'b0:No DMA request + * 1'b1:DMA request is in progress + */ +#define USB_DMAREQ (BIT(30)) +#define USB_DMAREQ_M (USB_DMAREQ_V << USB_DMAREQ_S) +#define USB_DMAREQ_V 0x00000001 +#define USB_DMAREQ_S 30 +/** USB_AHBIDLE : RO; bitpos: [31]; default: 0; + * AHB Master Idle + * 1'b0:Not Idle + * 1'b1:AHB Master Idle + */ +#define USB_AHBIDLE (BIT(31)) +#define USB_AHBIDLE_M (USB_AHBIDLE_V << USB_AHBIDLE_S) +#define USB_AHBIDLE_V 0x00000001 +#define USB_AHBIDLE_S 31 + + +/** USB_GRXFSIZ_REG register + * Receive FIFO Size Register + */ +#define USB_GRXFSIZ_REG (SOC_DPORT_USB_BASE + 0x24) +/** USB_RXFDEP : R/W; bitpos: [16:0]; default: 256; + * RxFIFO Depth.This value is in terms of 32-bit words.Minimum value is 16,Maximum + * value is 32,768 + */ +#define USB_RXFDEP 0x0000FFFF +#define USB_RXFDEP_M (USB_RXFDEP_V << USB_RXFDEP_S) +#define USB_RXFDEP_V 0x0000FFFF +#define USB_RXFDEP_S 0 + + +/** USB_GNPTXFSIZ_REG register + * Non-periodic Transmit FIFO Size Register + */ +#define USB_GNPTXFSIZ_REG (SOC_DPORT_USB_BASE + 0x28) +/** USB_NPTXFSTADDR : R/W; bitpos: [16:0]; default: 256; + * The NPTxFStAddr field description is valid only for host mode.This field contains + * the memory start address for Non-periodic Transmit FIFO RAM. + */ +#define USB_NPTXFSTADDR 0x0000FFFF +#define USB_NPTXFSTADDR_M (USB_NPTXFSTADDR_V << USB_NPTXFSTADDR_S) +#define USB_NPTXFSTADDR_V 0x0000FFFF +#define USB_NPTXFSTADDR_S 0 +/** USB_NPTXFDEP : R/W; bitpos: [32:16]; default: 256; + * The NPTxFDep field description is valid only for host mode or device mode when + * OTG_EN_DED_TX_FIFO=0.Minimum value is 16,Maximum value is 32,768. + */ +#define USB_NPTXFDEP 0x0000FFFF +#define USB_NPTXFDEP_M (USB_NPTXFDEP_V << USB_NPTXFDEP_S) +#define USB_NPTXFDEP_V 0x0000FFFF +#define USB_NPTXFDEP_S 16 + + +/** USB_GNPTXSTS_REG register + * Non-periodic Transmit FIFO/Queue Status Register + */ +#define USB_GNPTXSTS_REG (SOC_DPORT_USB_BASE + 0x2c) +/** USB_NPTXFSPCAVAIL : RO; bitpos: [16:0]; default: 256; + * Non-periodic TxFIFO Space Avail.Indicates the amount of free space available in the + * Non-periodic TxFIFO.Values are in terms of 32-bit words. + */ +#define USB_NPTXFSPCAVAIL 0x0000FFFF +#define USB_NPTXFSPCAVAIL_M (USB_NPTXFSPCAVAIL_V << USB_NPTXFSPCAVAIL_S) +#define USB_NPTXFSPCAVAIL_V 0x0000FFFF +#define USB_NPTXFSPCAVAIL_S 0 +/** USB_NPTXQSPCAVAIL : RO; bitpos: [20:16]; default: 4; + * Non-periodic Transmit Request Queue Space Available.Indicates the amount of free + * space available in the Non-periodic Transmit Request Queue. This queue holds both + * IN and OUT requests in Host mode. Device mode has only IN requests. + */ +#define USB_NPTXQSPCAVAIL 0x0000000F +#define USB_NPTXQSPCAVAIL_M (USB_NPTXQSPCAVAIL_V << USB_NPTXQSPCAVAIL_S) +#define USB_NPTXQSPCAVAIL_V 0x0000000F +#define USB_NPTXQSPCAVAIL_S 16 +/** USB_NPTXQTOP : RO; bitpos: [31:24]; default: 0; + * Top of the Non-periodic Transmit Request Queue. + * Bits [30:27]: Channel/endpoint number. + * Bits [26:25]: 2'b00: IN/OUT token 2'b01: Zero-length transmit packet (device + * IN/host OUT) 2'b10: PING/CSPLIT token 2'b11: Channel halt command. + * Bit [24]: Terminate (last Entry for selected channel/endpoint). + */ +#define USB_NPTXQTOP 0x0000007F +#define USB_NPTXQTOP_M (USB_NPTXQTOP_V << USB_NPTXQTOP_S) +#define USB_NPTXQTOP_V 0x0000007F +#define USB_NPTXQTOP_S 24 + + +/** USB_HCTSIZ0_REG register + * Host Channel 0Transfer Size Register + */ +#define USB_HCTSIZ0_REG (SOC_DPORT_USB_BASE + 0x510) +/** USB_H_XFERSIZE0 : R/W; bitpos: [19:0]; default: 0; + * Non-Scatter/Gather DMA Mode: Transfer Size. + * Scatter/Gather DMA Mode: + * [18:16]: Reserved + * [15:8]: NTD (Number of Transfer Descriptors) + */ +#define USB_H_XFERSIZE0 0x0007FFFF +#define USB_H_XFERSIZE0_M (USB_H_XFERSIZE0_V << USB_H_XFERSIZE0_S) +#define USB_H_XFERSIZE0_V 0x0007FFFF +#define USB_H_XFERSIZE0_S 0 +/** USB_H_PKTCNT0 : R/W; bitpos: [29:19]; default: 0; + * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the + * application with the expected number of packets to be transmitted (OUT) or received + * (IN). + * Scatter/Gather DMA Mode: Reserved. + */ +#define USB_H_PKTCNT0 0x000003FF +#define USB_H_PKTCNT0_M (USB_H_PKTCNT0_V << USB_H_PKTCNT0_S) +#define USB_H_PKTCNT0_V 0x000003FF +#define USB_H_PKTCNT0_S 19 +/** USB_H_PID0 : R/W; bitpos: [31:29]; default: 0; + * 2'b00: DATA0 + * 2'b01: DATA2 + * 2'b10: DATA1 + * 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_H_PID0 0x00000003 +#define USB_H_PID0_M (USB_H_PID0_V << USB_H_PID0_S) +#define USB_H_PID0_V 0x00000003 +#define USB_H_PID0_S 29 +/** USB_H_DOPNG0 : R/W; bitpos: [31]; default: 0; + * This bit is used only for OUT transfers. Setting this field to 1 directs the host + * to do PING protocol + * 1'b0: No ping protocol + * 1'b1: Ping protocol + */ +#define USB_H_DOPNG0 (BIT(31)) +#define USB_H_DOPNG0_M (USB_H_DOPNG0_V << USB_H_DOPNG0_S) +#define USB_H_DOPNG0_V 0x00000001 +#define USB_H_DOPNG0_S 31 + + +/** USB_HCTSIZ1_REG register + * Host Channel 1Transfer Size Register + */ +#define USB_HCTSIZ1_REG (SOC_DPORT_USB_BASE + 0x530) +/** USB_H_XFERSIZE1 : R/W; bitpos: [19:0]; default: 0; + * Non-Scatter/Gather DMA Mode: Transfer Size. + * Scatter/Gather DMA Mode: + * [18:16]: Reserved + * [15:8]: NTD (Number of Transfer Descriptors) + */ +#define USB_H_XFERSIZE1 0x0007FFFF +#define USB_H_XFERSIZE1_M (USB_H_XFERSIZE1_V << USB_H_XFERSIZE1_S) +#define USB_H_XFERSIZE1_V 0x0007FFFF +#define USB_H_XFERSIZE1_S 0 +/** USB_H_PKTCNT1 : R/W; bitpos: [29:19]; default: 0; + * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the + * application with the expected number of packets to be transmitted (OUT) or received + * (IN). + * Scatter/Gather DMA Mode: Reserved. + */ +#define USB_H_PKTCNT1 0x000003FF +#define USB_H_PKTCNT1_M (USB_H_PKTCNT1_V << USB_H_PKTCNT1_S) +#define USB_H_PKTCNT1_V 0x000003FF +#define USB_H_PKTCNT1_S 19 +/** USB_H_PID1 : R/W; bitpos: [31:29]; default: 0; + * 2'b00: DATA0 + * 2'b01: DATA2 + * 2'b10: DATA1 + * 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_H_PID1 0x00000003 +#define USB_H_PID1_M (USB_H_PID1_V << USB_H_PID1_S) +#define USB_H_PID1_V 0x00000003 +#define USB_H_PID1_S 29 +/** USB_H_DOPNG1 : R/W; bitpos: [31]; default: 0; + * This bit is used only for OUT transfers. Setting this field to 1 directs the host + * to do PING protocol + * 1'b0: No ping protocol + * 1'b1: Ping protocol + */ +#define USB_H_DOPNG1 (BIT(31)) +#define USB_H_DOPNG1_M (USB_H_DOPNG1_V << USB_H_DOPNG1_S) +#define USB_H_DOPNG1_V 0x00000001 +#define USB_H_DOPNG1_S 31 + + +/** USB_HCTSIZ2_REG register + * Host Channel 2Transfer Size Register + */ +#define USB_HCTSIZ2_REG (SOC_DPORT_USB_BASE + 0x550) +/** USB_H_XFERSIZE2 : R/W; bitpos: [19:0]; default: 0; + * Non-Scatter/Gather DMA Mode: Transfer Size. + * Scatter/Gather DMA Mode: + * [18:16]: Reserved + * [15:8]: NTD (Number of Transfer Descriptors) + */ +#define USB_H_XFERSIZE2 0x0007FFFF +#define USB_H_XFERSIZE2_M (USB_H_XFERSIZE2_V << USB_H_XFERSIZE2_S) +#define USB_H_XFERSIZE2_V 0x0007FFFF +#define USB_H_XFERSIZE2_S 0 +/** USB_H_PKTCNT2 : R/W; bitpos: [29:19]; default: 0; + * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the + * application with the expected number of packets to be transmitted (OUT) or received + * (IN). + * Scatter/Gather DMA Mode: Reserved. + */ +#define USB_H_PKTCNT2 0x000003FF +#define USB_H_PKTCNT2_M (USB_H_PKTCNT2_V << USB_H_PKTCNT2_S) +#define USB_H_PKTCNT2_V 0x000003FF +#define USB_H_PKTCNT2_S 19 +/** USB_H_PID2 : R/W; bitpos: [31:29]; default: 0; + * 2'b00: DATA0 + * 2'b01: DATA2 + * 2'b10: DATA1 + * 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_H_PID2 0x00000003 +#define USB_H_PID2_M (USB_H_PID2_V << USB_H_PID2_S) +#define USB_H_PID2_V 0x00000003 +#define USB_H_PID2_S 29 +/** USB_H_DOPNG2 : R/W; bitpos: [31]; default: 0; + * This bit is used only for OUT transfers. Setting this field to 1 directs the host + * to do PING protocol + * 1'b0: No ping protocol + * 1'b1: Ping protocol + */ +#define USB_H_DOPNG2 (BIT(31)) +#define USB_H_DOPNG2_M (USB_H_DOPNG2_V << USB_H_DOPNG2_S) +#define USB_H_DOPNG2_V 0x00000001 +#define USB_H_DOPNG2_S 31 + + +/** USB_HCTSIZ3_REG register + * Host Channel 3Transfer Size Register + */ +#define USB_HCTSIZ3_REG (SOC_DPORT_USB_BASE + 0x570) +/** USB_H_XFERSIZE3 : R/W; bitpos: [19:0]; default: 0; + * Non-Scatter/Gather DMA Mode: Transfer Size. + * Scatter/Gather DMA Mode: + * [18:16]: Reserved + * [15:8]: NTD (Number of Transfer Descriptors) + */ +#define USB_H_XFERSIZE3 0x0007FFFF +#define USB_H_XFERSIZE3_M (USB_H_XFERSIZE3_V << USB_H_XFERSIZE3_S) +#define USB_H_XFERSIZE3_V 0x0007FFFF +#define USB_H_XFERSIZE3_S 0 +/** USB_H_PKTCNT3 : R/W; bitpos: [29:19]; default: 0; + * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the + * application with the expected number of packets to be transmitted (OUT) or received + * (IN). + * Scatter/Gather DMA Mode: Reserved. + */ +#define USB_H_PKTCNT3 0x000003FF +#define USB_H_PKTCNT3_M (USB_H_PKTCNT3_V << USB_H_PKTCNT3_S) +#define USB_H_PKTCNT3_V 0x000003FF +#define USB_H_PKTCNT3_S 19 +/** USB_H_PID3 : R/W; bitpos: [31:29]; default: 0; + * 2'b00: DATA0 + * 2'b01: DATA2 + * 2'b10: DATA1 + * 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_H_PID3 0x00000003 +#define USB_H_PID3_M (USB_H_PID3_V << USB_H_PID3_S) +#define USB_H_PID3_V 0x00000003 +#define USB_H_PID3_S 29 +/** USB_H_DOPNG3 : R/W; bitpos: [31]; default: 0; + * This bit is used only for OUT transfers. Setting this field to 1 directs the host + * to do PING protocol + * 1'b0: No ping protocol + * 1'b1: Ping protocol + */ +#define USB_H_DOPNG3 (BIT(31)) +#define USB_H_DOPNG3_M (USB_H_DOPNG3_V << USB_H_DOPNG3_S) +#define USB_H_DOPNG3_V 0x00000001 +#define USB_H_DOPNG3_S 31 + + +/** USB_HCTSIZ4_REG register + * Host Channel 4Transfer Size Register + */ +#define USB_HCTSIZ4_REG (SOC_DPORT_USB_BASE + 0x590) +/** USB_H_XFERSIZE4 : R/W; bitpos: [19:0]; default: 0; + * Non-Scatter/Gather DMA Mode: Transfer Size. + * Scatter/Gather DMA Mode: + * [18:16]: Reserved + * [15:8]: NTD (Number of Transfer Descriptors) + */ +#define USB_H_XFERSIZE4 0x0007FFFF +#define USB_H_XFERSIZE4_M (USB_H_XFERSIZE4_V << USB_H_XFERSIZE4_S) +#define USB_H_XFERSIZE4_V 0x0007FFFF +#define USB_H_XFERSIZE4_S 0 +/** USB_H_PKTCNT4 : R/W; bitpos: [29:19]; default: 0; + * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the + * application with the expected number of packets to be transmitted (OUT) or received + * (IN). + * Scatter/Gather DMA Mode: Reserved. + */ +#define USB_H_PKTCNT4 0x000003FF +#define USB_H_PKTCNT4_M (USB_H_PKTCNT4_V << USB_H_PKTCNT4_S) +#define USB_H_PKTCNT4_V 0x000003FF +#define USB_H_PKTCNT4_S 19 +/** USB_H_PID4 : R/W; bitpos: [31:29]; default: 0; + * 2'b00: DATA0 + * 2'b01: DATA2 + * 2'b10: DATA1 + * 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_H_PID4 0x00000003 +#define USB_H_PID4_M (USB_H_PID4_V << USB_H_PID4_S) +#define USB_H_PID4_V 0x00000003 +#define USB_H_PID4_S 29 +/** USB_H_DOPNG4 : R/W; bitpos: [31]; default: 0; + * This bit is used only for OUT transfers. Setting this field to 1 directs the host + * to do PING protocol + * 1'b0: No ping protocol + * 1'b1: Ping protocol + */ +#define USB_H_DOPNG4 (BIT(31)) +#define USB_H_DOPNG4_M (USB_H_DOPNG4_V << USB_H_DOPNG4_S) +#define USB_H_DOPNG4_V 0x00000001 +#define USB_H_DOPNG4_S 31 + + +/** USB_HCTSIZ5_REG register + * Host Channel 5Transfer Size Register + */ +#define USB_HCTSIZ5_REG (SOC_DPORT_USB_BASE + 0x5b0) +/** USB_H_XFERSIZE5 : R/W; bitpos: [19:0]; default: 0; + * Non-Scatter/Gather DMA Mode: Transfer Size. + * Scatter/Gather DMA Mode: + * [18:16]: Reserved + * [15:8]: NTD (Number of Transfer Descriptors) + */ +#define USB_H_XFERSIZE5 0x0007FFFF +#define USB_H_XFERSIZE5_M (USB_H_XFERSIZE5_V << USB_H_XFERSIZE5_S) +#define USB_H_XFERSIZE5_V 0x0007FFFF +#define USB_H_XFERSIZE5_S 0 +/** USB_H_PKTCNT5 : R/W; bitpos: [29:19]; default: 0; + * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the + * application with the expected number of packets to be transmitted (OUT) or received + * (IN). + * Scatter/Gather DMA Mode: Reserved. + */ +#define USB_H_PKTCNT5 0x000003FF +#define USB_H_PKTCNT5_M (USB_H_PKTCNT5_V << USB_H_PKTCNT5_S) +#define USB_H_PKTCNT5_V 0x000003FF +#define USB_H_PKTCNT5_S 19 +/** USB_H_PID5 : R/W; bitpos: [31:29]; default: 0; + * 2'b00: DATA0 + * 2'b01: DATA2 + * 2'b10: DATA1 + * 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_H_PID5 0x00000003 +#define USB_H_PID5_M (USB_H_PID5_V << USB_H_PID5_S) +#define USB_H_PID5_V 0x00000003 +#define USB_H_PID5_S 29 +/** USB_H_DOPNG5 : R/W; bitpos: [31]; default: 0; + * This bit is used only for OUT transfers. Setting this field to 1 directs the host + * to do PING protocol + * 1'b0: No ping protocol + * 1'b1: Ping protocol + */ +#define USB_H_DOPNG5 (BIT(31)) +#define USB_H_DOPNG5_M (USB_H_DOPNG5_V << USB_H_DOPNG5_S) +#define USB_H_DOPNG5_V 0x00000001 +#define USB_H_DOPNG5_S 31 + + +/** USB_HCTSIZ6_REG register + * Host Channel 6Transfer Size Register + */ +#define USB_HCTSIZ6_REG (SOC_DPORT_USB_BASE + 0x5d0) +/** USB_H_XFERSIZE6 : R/W; bitpos: [19:0]; default: 0; + * Non-Scatter/Gather DMA Mode: Transfer Size. + * Scatter/Gather DMA Mode: + * [18:16]: Reserved + * [15:8]: NTD (Number of Transfer Descriptors) + */ +#define USB_H_XFERSIZE6 0x0007FFFF +#define USB_H_XFERSIZE6_M (USB_H_XFERSIZE6_V << USB_H_XFERSIZE6_S) +#define USB_H_XFERSIZE6_V 0x0007FFFF +#define USB_H_XFERSIZE6_S 0 +/** USB_H_PKTCNT6 : R/W; bitpos: [29:19]; default: 0; + * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the + * application with the expected number of packets to be transmitted (OUT) or received + * (IN). + * Scatter/Gather DMA Mode: Reserved. + */ +#define USB_H_PKTCNT6 0x000003FF +#define USB_H_PKTCNT6_M (USB_H_PKTCNT6_V << USB_H_PKTCNT6_S) +#define USB_H_PKTCNT6_V 0x000003FF +#define USB_H_PKTCNT6_S 19 +/** USB_H_PID6 : R/W; bitpos: [31:29]; default: 0; + * 2'b00: DATA0 + * 2'b01: DATA2 + * 2'b10: DATA1 + * 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_H_PID6 0x00000003 +#define USB_H_PID6_M (USB_H_PID6_V << USB_H_PID6_S) +#define USB_H_PID6_V 0x00000003 +#define USB_H_PID6_S 29 +/** USB_H_DOPNG6 : R/W; bitpos: [31]; default: 0; + * This bit is used only for OUT transfers. Setting this field to 1 directs the host + * to do PING protocol + * 1'b0: No ping protocol + * 1'b1: Ping protocol + */ +#define USB_H_DOPNG6 (BIT(31)) +#define USB_H_DOPNG6_M (USB_H_DOPNG6_V << USB_H_DOPNG6_S) +#define USB_H_DOPNG6_V 0x00000001 +#define USB_H_DOPNG6_S 31 + + +/** USB_HCTSIZ7_REG register + * Host Channel 7Transfer Size Register + */ +#define USB_HCTSIZ7_REG (SOC_DPORT_USB_BASE + 0x5f0) +/** USB_H_XFERSIZE7 : R/W; bitpos: [19:0]; default: 0; + * Non-Scatter/Gather DMA Mode: Transfer Size. + * Scatter/Gather DMA Mode: + * [18:16]: Reserved + * [15:8]: NTD (Number of Transfer Descriptors) + */ +#define USB_H_XFERSIZE7 0x0007FFFF +#define USB_H_XFERSIZE7_M (USB_H_XFERSIZE7_V << USB_H_XFERSIZE7_S) +#define USB_H_XFERSIZE7_V 0x0007FFFF +#define USB_H_XFERSIZE7_S 0 +/** USB_H_PKTCNT7 : R/W; bitpos: [29:19]; default: 0; + * when in Non-Scatter/Gather DMA mode: Packet Count . This field is programmed by the + * application with the expected number of packets to be transmitted (OUT) or received + * (IN). + * Scatter/Gather DMA Mode: Reserved. + */ +#define USB_H_PKTCNT7 0x000003FF +#define USB_H_PKTCNT7_M (USB_H_PKTCNT7_V << USB_H_PKTCNT7_S) +#define USB_H_PKTCNT7_V 0x000003FF +#define USB_H_PKTCNT7_S 19 +/** USB_H_PID7 : R/W; bitpos: [31:29]; default: 0; + * 2'b00: DATA0 + * 2'b01: DATA2 + * 2'b10: DATA1 + * 2'b11: MDATA (non-control)/SETUP (control) + */ +#define USB_H_PID7 0x00000003 +#define USB_H_PID7_M (USB_H_PID7_V << USB_H_PID7_S) +#define USB_H_PID7_V 0x00000003 +#define USB_H_PID7_S 29 +/** USB_H_DOPNG7 : R/W; bitpos: [31]; default: 0; + * This bit is used only for OUT transfers. Setting this field to 1 directs the host + * to do PING protocol + * 1'b0: No ping protocol + * 1'b1: Ping protocol + */ +#define USB_H_DOPNG7 (BIT(31)) +#define USB_H_DOPNG7_M (USB_H_DOPNG7_V << USB_H_DOPNG7_S) +#define USB_H_DOPNG7_V 0x00000001 +#define USB_H_DOPNG7_S 31 + + + + +/** Status registers */ +/** USB_GRXSTSR_REG register + * Receive Status Debug Read Register + */ +#define USB_GRXSTSR_REG (SOC_DPORT_USB_BASE + 0x1c) +/** USB_G_CHNUM : RO; bitpos: [4:0]; default: 0; + * Channel Number: Host only. Indicates the channel number to which the current + * received packet belongs. + * Endpoint Number: Device only Indicates the endpoint number to which the current + * received packet belongs + */ +#define USB_G_CHNUM 0x0000000F +#define USB_G_CHNUM_M (USB_G_CHNUM_V << USB_G_CHNUM_S) +#define USB_G_CHNUM_V 0x0000000F +#define USB_G_CHNUM_S 0 +/** USB_G_BCNT : RO; bitpos: [15:4]; default: 0; + * In host mode, indicates the byte count of the received IN data Packet + * In device mode, indicates the byte count of the received data packet + */ +#define USB_G_BCNT 0x000007FF +#define USB_G_BCNT_M (USB_G_BCNT_V << USB_G_BCNT_S) +#define USB_G_BCNT_V 0x000007FF +#define USB_G_BCNT_S 4 +/** USB_G_DPID : RO; bitpos: [17:15]; default: 0; + * Data PID + * 0x0 (DATA0): DATA0 + * 0x2 (DATA1): DATA1 + * 0x1 (DATA2): DATA2 + * 0x3 (MDATA): MDATA + */ +#define USB_G_DPID 0x00000003 +#define USB_G_DPID_M (USB_G_DPID_V << USB_G_DPID_S) +#define USB_G_DPID_V 0x00000003 +#define USB_G_DPID_S 15 +/** USB_G_PKTSTS : RO; bitpos: [21:17]; default: 0; + * 0x1 (OUTNAK): Global OUT NAK in device mode (triggers an Interrupt) + * 0x2 (INOUTDPRX): IN data packet received in host mode and OUT data received in + * device mode + * 0x3 (INOUTTRCOM): IN or OUT transfer completed in both host and device (triggers + * an interrupt) + * 0x4 (DSETUPCOM): SETUP transaction completed in device mode (triggers an interrupt) + * 0x5 (DTTOG): Data toggle error (triggers an interrupt) in host Mode + * 0x6 (DSETUPRX): SETUP data packet received in device mode + * 0x7 (CHHALT): Channel halted in host mode (triggers an interrupt) + */ +#define USB_G_PKTSTS 0x0000000F +#define USB_G_PKTSTS_M (USB_G_PKTSTS_V << USB_G_PKTSTS_S) +#define USB_G_PKTSTS_V 0x0000000F +#define USB_G_PKTSTS_S 17 +/** USB_G_FN : RO; bitpos: [25:21]; default: 0; + * This is the least significant 4 bits of the (micro)Frame number in which the packet + * is received on the USB. This field is supported only when isochronous OUT endpoints + * are supported + */ +#define USB_G_FN 0x0000000F +#define USB_G_FN_M (USB_G_FN_V << USB_G_FN_S) +#define USB_G_FN_V 0x0000000F +#define USB_G_FN_S 21 + + +/** USB_GRXSTSP_REG register + * Receive Status Read/Pop Register + */ +#define USB_GRXSTSP_REG (SOC_DPORT_USB_BASE + 0x20) +/** USB_CHNUM : RO; bitpos: [4:0]; default: 0; + * Channel Number: Host only. Indicates the channel number to which the current + * received packet belongs. + * Endpoint Number: Device only Indicates the endpoint number to which the current + * received packet belongs + */ +#define USB_CHNUM 0x0000000F +#define USB_CHNUM_M (USB_CHNUM_V << USB_CHNUM_S) +#define USB_CHNUM_V 0x0000000F +#define USB_CHNUM_S 0 +/** USB_BCNT : RO; bitpos: [15:4]; default: 0; + * In host mode, indicates the byte count of the received IN data Packet + * In device mode, indicates the byte count of the received data packet + */ +#define USB_BCNT 0x000007FF +#define USB_BCNT_M (USB_BCNT_V << USB_BCNT_S) +#define USB_BCNT_V 0x000007FF +#define USB_BCNT_S 4 +/** USB_DPID : RO; bitpos: [17:15]; default: 0; + * Data PID + * 0x0 (DATA0): DATA0 + * 0x2 (DATA1): DATA1 + * 0x1 (DATA2): DATA2 + * 0x3 (MDATA): MDATA + */ +#define USB_DPID 0x00000003 +#define USB_DPID_M (USB_DPID_V << USB_DPID_S) +#define USB_DPID_V 0x00000003 +#define USB_DPID_S 15 +/** USB_PKTSTS : RO; bitpos: [21:17]; default: 0; + * 0x1 (OUTNAK): Global OUT NAK in device mode (triggers an Interrupt) + * 0x2 (INOUTDPRX): IN data packet received in host mode and OUT data packet received + * in device mode + * 0x3 (INOUTTRCOM): IN or OUT transfer completed in both host and device mode + * (triggers an interrupt) + * 0x4 (DSETUPCOM): SETUP transaction completed in device mode (triggers an interrupt) + * 0x5 (DTTOG): Data toggle error (triggers an interrupt) in host Mode + * 0x6 (DSETUPRX): SETUP data packet received in device mode + * 0x7 (CHHALT): Channel halted in host mode (triggers an interrupt) + */ +#define USB_PKTSTS 0x0000000F +#define USB_PKTSTS_M (USB_PKTSTS_V << USB_PKTSTS_S) +#define USB_PKTSTS_V 0x0000000F +#define USB_PKTSTS_S 17 +/** USB_FN : RO; bitpos: [25:21]; default: 0; + * This is the least significant 4 bits of the (micro)Frame number in which the packet + * is received on the USB. This field is supported only when isochronous OUT endpoints + * are supported + */ +#define USB_FN 0x0000000F +#define USB_FN_M (USB_FN_V << USB_FN_S) +#define USB_FN_V 0x0000000F +#define USB_FN_S 21 + + +/** USB_GSNPSID_REG register + * Synopsys ID Register + */ +#define USB_GSNPSID_REG (SOC_DPORT_USB_BASE + 0x40) +/** USB_SYNOPSYSID : RO; bitpos: [32:0]; default: 1330921482; + * ID register + */ +#define USB_SYNOPSYSID 0xFFFFFFFF +#define USB_SYNOPSYSID_M (USB_SYNOPSYSID_V << USB_SYNOPSYSID_S) +#define USB_SYNOPSYSID_V 0xFFFFFFFF +#define USB_SYNOPSYSID_S 0 + + +/** USB_GHWCFG1_REG register + * User Hardware Configuration 1 Register + */ +#define USB_GHWCFG1_REG (SOC_DPORT_USB_BASE + 0x44) +/** USB_EPDIR : RO; bitpos: [32:0]; default: 0; + * This 32-bit field uses two bits per endpoint to determine the endpoint direction. + * Bits [31:30]: Endpoint 15 direction + * Bits [29:28]: Endpoint 14 direction + * ... + * Direction: + * 2'b00: BIDIR (IN and OUT) endpoint + * 2'b01: IN endpoint + * 2'b10: OUT endpoint + * 2'b11: Reserved + */ +#define USB_EPDIR 0xFFFFFFFF +#define USB_EPDIR_M (USB_EPDIR_V << USB_EPDIR_S) +#define USB_EPDIR_V 0xFFFFFFFF +#define USB_EPDIR_S 0 + + +/** USB_GHWCFG2_REG register + * User Hardware Configuration 2 Register + */ +#define USB_GHWCFG2_REG (SOC_DPORT_USB_BASE + 0x48) +/** USB_OTGMODE : RO; bitpos: [3:0]; default: 0; + * 3'b000: HNP- and SRP-Capable OTG (Host Device) + */ +#define USB_OTGMODE 0x00000007 +#define USB_OTGMODE_M (USB_OTGMODE_V << USB_OTGMODE_S) +#define USB_OTGMODE_V 0x00000007 +#define USB_OTGMODE_S 0 +/** USB_OTGARCH : RO; bitpos: [5:3]; default: 2; + * 2'b10: Internal DMA + */ +#define USB_OTGARCH 0x00000003 +#define USB_OTGARCH_M (USB_OTGARCH_V << USB_OTGARCH_S) +#define USB_OTGARCH_V 0x00000003 +#define USB_OTGARCH_S 3 +/** USB_SINGPNT : RO; bitpos: [5]; default: 1; + * Point-to-Point + * 1'b1: Single-point application (no hub and split support). + */ +#define USB_SINGPNT (BIT(5)) +#define USB_SINGPNT_M (USB_SINGPNT_V << USB_SINGPNT_S) +#define USB_SINGPNT_V 0x00000001 +#define USB_SINGPNT_S 5 +/** USB_HSPHYTYPE : RO; bitpos: [8:6]; default: 0; + * High-Speed PHY Interface Type + * 2'b00: High-Speed interface not supported + */ +#define USB_HSPHYTYPE 0x00000003 +#define USB_HSPHYTYPE_M (USB_HSPHYTYPE_V << USB_HSPHYTYPE_S) +#define USB_HSPHYTYPE_V 0x00000003 +#define USB_HSPHYTYPE_S 6 +/** USB_FSPHYTYPE : RO; bitpos: [10:8]; default: 1; + * Full-Speed PHY Interface Type. + */ +#define USB_FSPHYTYPE 0x00000003 +#define USB_FSPHYTYPE_M (USB_FSPHYTYPE_V << USB_FSPHYTYPE_S) +#define USB_FSPHYTYPE_V 0x00000003 +#define USB_FSPHYTYPE_S 8 +/** USB_NUMDEVEPS : RO; bitpos: [14:10]; default: 6; + * Number of Device Endpoints. + */ +#define USB_NUMDEVEPS 0x0000000F +#define USB_NUMDEVEPS_M (USB_NUMDEVEPS_V << USB_NUMDEVEPS_S) +#define USB_NUMDEVEPS_V 0x0000000F +#define USB_NUMDEVEPS_S 10 +/** USB_NUMHSTCHNL : RO; bitpos: [18:14]; default: 7; + * Number of Host Channels. + */ +#define USB_NUMHSTCHNL 0x0000000F +#define USB_NUMHSTCHNL_M (USB_NUMHSTCHNL_V << USB_NUMHSTCHNL_S) +#define USB_NUMHSTCHNL_V 0x0000000F +#define USB_NUMHSTCHNL_S 14 +/** USB_PERIOSUPPORT : RO; bitpos: [18]; default: 1; + * 1'b0:Periodic OUT Channels is not Supported in Host Mode + * 1'b1:Periodic OUT Channels Supported in Host Mode + */ +#define USB_PERIOSUPPORT (BIT(18)) +#define USB_PERIOSUPPORT_M (USB_PERIOSUPPORT_V << USB_PERIOSUPPORT_S) +#define USB_PERIOSUPPORT_V 0x00000001 +#define USB_PERIOSUPPORT_S 18 +/** USB_DYNFIFOSIZING : RO; bitpos: [19]; default: 1; + * 1'b0:Dynamic FIFO Sizing Disabled + * 1'b1:Dynamic FIFO Sizing Enabled + */ +#define USB_DYNFIFOSIZING (BIT(19)) +#define USB_DYNFIFOSIZING_M (USB_DYNFIFOSIZING_V << USB_DYNFIFOSIZING_S) +#define USB_DYNFIFOSIZING_V 0x00000001 +#define USB_DYNFIFOSIZING_S 19 +/** USB_MULTIPROCINTRPT : RO; bitpos: [20]; default: 0; + * 1'b0: No Multi Processor Interrupt Enabled + * 1'b1:Multi Processor Interrupt Enabled + */ +#define USB_MULTIPROCINTRPT (BIT(20)) +#define USB_MULTIPROCINTRPT_M (USB_MULTIPROCINTRPT_V << USB_MULTIPROCINTRPT_S) +#define USB_MULTIPROCINTRPT_V 0x00000001 +#define USB_MULTIPROCINTRPT_S 20 +/** USB_NPTXQDEPTH : RO; bitpos: [24:22]; default: 1; + * Non-periodic Request Queue Depth + * 2'b01: 4 + */ +#define USB_NPTXQDEPTH 0x00000003 +#define USB_NPTXQDEPTH_M (USB_NPTXQDEPTH_V << USB_NPTXQDEPTH_S) +#define USB_NPTXQDEPTH_V 0x00000003 +#define USB_NPTXQDEPTH_S 22 +/** USB_PTXQDEPTH : RO; bitpos: [26:24]; default: 2; + * Host Mode Periodic Request Queue Depth. + * 2'b10: 8 + */ +#define USB_PTXQDEPTH 0x00000003 +#define USB_PTXQDEPTH_M (USB_PTXQDEPTH_V << USB_PTXQDEPTH_S) +#define USB_PTXQDEPTH_V 0x00000003 +#define USB_PTXQDEPTH_S 24 +/** USB_TKNQDEPTH : RO; bitpos: [31:26]; default: 8; + * Device Mode IN Token Sequence Learning Queue Depth. + */ +#define USB_TKNQDEPTH 0x0000001F +#define USB_TKNQDEPTH_M (USB_TKNQDEPTH_V << USB_TKNQDEPTH_S) +#define USB_TKNQDEPTH_V 0x0000001F +#define USB_TKNQDEPTH_S 26 +/** USB_OTG_ENABLE_IC_USB : RO; bitpos: [31]; default: 0; + * 0x0 (DISABLE): Disabled the IC_USB Full-Speed Serial Transceiver interface + * 0x1 (ENABLE): Enabled the IC_USB Full-Speed Serial Transceiver interface + */ +#define USB_OTG_ENABLE_IC_USB (BIT(31)) +#define USB_OTG_ENABLE_IC_USB_M (USB_OTG_ENABLE_IC_USB_V << USB_OTG_ENABLE_IC_USB_S) +#define USB_OTG_ENABLE_IC_USB_V 0x00000001 +#define USB_OTG_ENABLE_IC_USB_S 31 + + +/** USB_GHWCFG3_REG register + * User Hardware Configuration 3 Register + */ +#define USB_GHWCFG3_REG (SOC_DPORT_USB_BASE + 0x4c) +/** USB_XFERSIZEWIDTH : RO; bitpos: [4:0]; default: 5; + * Width of Transfer Size Counters + * 0x5 (WIDTH16): Width of Transfer Size Counter 16 bits + */ +#define USB_XFERSIZEWIDTH 0x0000000F +#define USB_XFERSIZEWIDTH_M (USB_XFERSIZEWIDTH_V << USB_XFERSIZEWIDTH_S) +#define USB_XFERSIZEWIDTH_V 0x0000000F +#define USB_XFERSIZEWIDTH_S 0 +/** USB_PKTSIZEWIDTH : RO; bitpos: [7:4]; default: 3; + * Width of Packet Size Counters + * 3'b011: 7 bits + */ +#define USB_PKTSIZEWIDTH 0x00000007 +#define USB_PKTSIZEWIDTH_M (USB_PKTSIZEWIDTH_V << USB_PKTSIZEWIDTH_S) +#define USB_PKTSIZEWIDTH_V 0x00000007 +#define USB_PKTSIZEWIDTH_S 4 +/** USB_OTGEN : RO; bitpos: [7]; default: 1; + * OTG Function Enabled. + */ +#define USB_OTGEN (BIT(7)) +#define USB_OTGEN_M (USB_OTGEN_V << USB_OTGEN_S) +#define USB_OTGEN_V 0x00000001 +#define USB_OTGEN_S 7 +/** USB_I2CINTSEL : RO; bitpos: [8]; default: 0; + * 1'b0: I2C Interface is not available on the controller. + */ +#define USB_I2CINTSEL (BIT(8)) +#define USB_I2CINTSEL_M (USB_I2CINTSEL_V << USB_I2CINTSEL_S) +#define USB_I2CINTSEL_V 0x00000001 +#define USB_I2CINTSEL_S 8 +/** USB_VNDCTLSUPT : RO; bitpos: [9]; default: 0; + * Vendor Control Interface is not available . + */ +#define USB_VNDCTLSUPT (BIT(9)) +#define USB_VNDCTLSUPT_M (USB_VNDCTLSUPT_V << USB_VNDCTLSUPT_S) +#define USB_VNDCTLSUPT_V 0x00000001 +#define USB_VNDCTLSUPT_S 9 +/** USB_OPTFEATURE : RO; bitpos: [10]; default: 1; + * Optional Features have been Removed. + */ +#define USB_OPTFEATURE (BIT(10)) +#define USB_OPTFEATURE_M (USB_OPTFEATURE_V << USB_OPTFEATURE_S) +#define USB_OPTFEATURE_V 0x00000001 +#define USB_OPTFEATURE_S 10 +/** USB_RSTTYPE : RO; bitpos: [11]; default: 0; + * Asynchronous reset is used in the core + */ +#define USB_RSTTYPE (BIT(11)) +#define USB_RSTTYPE_M (USB_RSTTYPE_V << USB_RSTTYPE_S) +#define USB_RSTTYPE_V 0x00000001 +#define USB_RSTTYPE_S 11 +/** USB_ADPSUPPORT : RO; bitpos: [12]; default: 0; + * ADP logic is not present along with the controller. + */ +#define USB_ADPSUPPORT (BIT(12)) +#define USB_ADPSUPPORT_M (USB_ADPSUPPORT_V << USB_ADPSUPPORT_S) +#define USB_ADPSUPPORT_V 0x00000001 +#define USB_ADPSUPPORT_S 12 +/** USB_HSICMODE : RO; bitpos: [13]; default: 0; + * HSIC mode specified for Mode of Operation. + * 1'b0: Non-HSIC-capable + */ +#define USB_HSICMODE (BIT(13)) +#define USB_HSICMODE_M (USB_HSICMODE_V << USB_HSICMODE_S) +#define USB_HSICMODE_V 0x00000001 +#define USB_HSICMODE_S 13 +/** USB_BCSUPPORT : RO; bitpos: [14]; default: 0; + * 1'b0: No Battery Charger Support + */ +#define USB_BCSUPPORT (BIT(14)) +#define USB_BCSUPPORT_M (USB_BCSUPPORT_V << USB_BCSUPPORT_S) +#define USB_BCSUPPORT_V 0x00000001 +#define USB_BCSUPPORT_S 14 +/** USB_LPMMODE : RO; bitpos: [15]; default: 0; + * LPM mode specified for Mode of Operation. + */ +#define USB_LPMMODE (BIT(15)) +#define USB_LPMMODE_M (USB_LPMMODE_V << USB_LPMMODE_S) +#define USB_LPMMODE_V 0x00000001 +#define USB_LPMMODE_S 15 +/** USB_DFIFODEPTH : RO; bitpos: [32:16]; default: 256; + * DFIFO Depth.This value is in terms of 32-bit words. + */ +#define USB_DFIFODEPTH 0x0000FFFF +#define USB_DFIFODEPTH_M (USB_DFIFODEPTH_V << USB_DFIFODEPTH_S) +#define USB_DFIFODEPTH_V 0x0000FFFF +#define USB_DFIFODEPTH_S 16 + + +/** USB_GHWCFG4_REG register + * User Hardware Configuration 4 Register + */ +#define USB_GHWCFG4_REG (SOC_DPORT_USB_BASE + 0x50) +/** USB_G_NUMDEVPERIOEPS : RO; bitpos: [4:0]; default: 0; + * Number of Device Mode Periodic IN Endpoints. + */ +#define USB_G_NUMDEVPERIOEPS 0x0000000F +#define USB_G_NUMDEVPERIOEPS_M (USB_G_NUMDEVPERIOEPS_V << USB_G_NUMDEVPERIOEPS_S) +#define USB_G_NUMDEVPERIOEPS_V 0x0000000F +#define USB_G_NUMDEVPERIOEPS_S 0 +/** USB_G_PARTIALPWRDN : RO; bitpos: [4]; default: 1; + * Enable Partial Power Down. + */ +#define USB_G_PARTIALPWRDN (BIT(4)) +#define USB_G_PARTIALPWRDN_M (USB_G_PARTIALPWRDN_V << USB_G_PARTIALPWRDN_S) +#define USB_G_PARTIALPWRDN_V 0x00000001 +#define USB_G_PARTIALPWRDN_S 4 +/** USB_G_AHBFREQ : RO; bitpos: [5]; default: 1; + * Minimum AHB Frequency Less Than 60 MHz + */ +#define USB_G_AHBFREQ (BIT(5)) +#define USB_G_AHBFREQ_M (USB_G_AHBFREQ_V << USB_G_AHBFREQ_S) +#define USB_G_AHBFREQ_V 0x00000001 +#define USB_G_AHBFREQ_S 5 +/** USB_G_HIBERNATION : RO; bitpos: [6]; default: 0; + * 1'b0: Hibernation feature not enabled. + */ +#define USB_G_HIBERNATION (BIT(6)) +#define USB_G_HIBERNATION_M (USB_G_HIBERNATION_V << USB_G_HIBERNATION_S) +#define USB_G_HIBERNATION_V 0x00000001 +#define USB_G_HIBERNATION_S 6 +/** USB_G_EXTENDEDHIBERNATION : RO; bitpos: [7]; default: 0; + * Extended Hibernation feature not enabled + */ +#define USB_G_EXTENDEDHIBERNATION (BIT(7)) +#define USB_G_EXTENDEDHIBERNATION_M (USB_G_EXTENDEDHIBERNATION_V << USB_G_EXTENDEDHIBERNATION_S) +#define USB_G_EXTENDEDHIBERNATION_V 0x00000001 +#define USB_G_EXTENDEDHIBERNATION_S 7 +/** USB_G_ACGSUPT : RO; bitpos: [12]; default: 0; + * Active Clock Gating is not enabled. + */ +#define USB_G_ACGSUPT (BIT(12)) +#define USB_G_ACGSUPT_M (USB_G_ACGSUPT_V << USB_G_ACGSUPT_S) +#define USB_G_ACGSUPT_V 0x00000001 +#define USB_G_ACGSUPT_S 12 +/** USB_G_ENHANCEDLPMSUPT : RO; bitpos: [13]; default: 1; + * Enhanced LPM Support. + */ +#define USB_G_ENHANCEDLPMSUPT (BIT(13)) +#define USB_G_ENHANCEDLPMSUPT_M (USB_G_ENHANCEDLPMSUPT_V << USB_G_ENHANCEDLPMSUPT_S) +#define USB_G_ENHANCEDLPMSUPT_V 0x00000001 +#define USB_G_ENHANCEDLPMSUPT_S 13 +/** USB_G_PHYDATAWIDTH : RO; bitpos: [16:14]; default: 2; + * UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width (PhyDataWidth) When a ULPI PHY + * is used, an internal wrapper converts ULPI to UTMI+ + * 2'b10: 8/16 bits, software selectable + */ +#define USB_G_PHYDATAWIDTH 0x00000003 +#define USB_G_PHYDATAWIDTH_M (USB_G_PHYDATAWIDTH_V << USB_G_PHYDATAWIDTH_S) +#define USB_G_PHYDATAWIDTH_V 0x00000003 +#define USB_G_PHYDATAWIDTH_S 14 +/** USB_G_NUMCTLEPS : RO; bitpos: [20:16]; default: 0; + * Number of Device Mode Control Endpoints in Addition to Endpoint 0 + */ +#define USB_G_NUMCTLEPS 0x0000000F +#define USB_G_NUMCTLEPS_M (USB_G_NUMCTLEPS_V << USB_G_NUMCTLEPS_S) +#define USB_G_NUMCTLEPS_V 0x0000000F +#define USB_G_NUMCTLEPS_S 16 +/** USB_G_IDDQFLTR : RO; bitpos: [20]; default: 1; + * IDDIG Filter Enable. + */ +#define USB_G_IDDQFLTR (BIT(20)) +#define USB_G_IDDQFLTR_M (USB_G_IDDQFLTR_V << USB_G_IDDQFLTR_S) +#define USB_G_IDDQFLTR_V 0x00000001 +#define USB_G_IDDQFLTR_S 20 +/** USB_G_VBUSVALIDFLTR : RO; bitpos: [21]; default: 1; + * VBUS Valid Filter Enabled. + */ +#define USB_G_VBUSVALIDFLTR (BIT(21)) +#define USB_G_VBUSVALIDFLTR_M (USB_G_VBUSVALIDFLTR_V << USB_G_VBUSVALIDFLTR_S) +#define USB_G_VBUSVALIDFLTR_V 0x00000001 +#define USB_G_VBUSVALIDFLTR_S 21 +/** USB_G_AVALIDFLTR : RO; bitpos: [22]; default: 1; + * a_valid Filter Enabled. + */ +#define USB_G_AVALIDFLTR (BIT(22)) +#define USB_G_AVALIDFLTR_M (USB_G_AVALIDFLTR_V << USB_G_AVALIDFLTR_S) +#define USB_G_AVALIDFLTR_V 0x00000001 +#define USB_G_AVALIDFLTR_S 22 +/** USB_G_BVALIDFLTR : RO; bitpos: [23]; default: 1; + * b_valid Filter Enabled. + */ +#define USB_G_BVALIDFLTR (BIT(23)) +#define USB_G_BVALIDFLTR_M (USB_G_BVALIDFLTR_V << USB_G_BVALIDFLTR_S) +#define USB_G_BVALIDFLTR_V 0x00000001 +#define USB_G_BVALIDFLTR_S 23 +/** USB_G_SESSENDFLTR : RO; bitpos: [24]; default: 1; + * session_end Filter Enabled. + */ +#define USB_G_SESSENDFLTR (BIT(24)) +#define USB_G_SESSENDFLTR_M (USB_G_SESSENDFLTR_V << USB_G_SESSENDFLTR_S) +#define USB_G_SESSENDFLTR_V 0x00000001 +#define USB_G_SESSENDFLTR_S 24 +/** USB_G_DEDFIFOMODE : RO; bitpos: [25]; default: 1; + * Enable Dedicated Transmit FIFO for device IN Endpoints + */ +#define USB_G_DEDFIFOMODE (BIT(25)) +#define USB_G_DEDFIFOMODE_M (USB_G_DEDFIFOMODE_V << USB_G_DEDFIFOMODE_S) +#define USB_G_DEDFIFOMODE_V 0x00000001 +#define USB_G_DEDFIFOMODE_S 25 +/** USB_G_INEPS : RO; bitpos: [30:26]; default: 4; + * Number of Device Mode IN Endpoints Including Control Endpoints. + */ +#define USB_G_INEPS 0x0000000F +#define USB_G_INEPS_M (USB_G_INEPS_V << USB_G_INEPS_S) +#define USB_G_INEPS_V 0x0000000F +#define USB_G_INEPS_S 26 +/** USB_G_DESCDMAENABLED : RO; bitpos: [30]; default: 1; + * 0x1: Scatter/Gather DMA configuration. + */ +#define USB_G_DESCDMAENABLED (BIT(30)) +#define USB_G_DESCDMAENABLED_M (USB_G_DESCDMAENABLED_V << USB_G_DESCDMAENABLED_S) +#define USB_G_DESCDMAENABLED_V 0x00000001 +#define USB_G_DESCDMAENABLED_S 30 +/** USB_G_DESCDMA : RO; bitpos: [31]; default: 1; + * Scatter/Gather DMA configuration + * 1'b1: Dynamic configuration + */ +#define USB_G_DESCDMA (BIT(31)) +#define USB_G_DESCDMA_M (USB_G_DESCDMA_V << USB_G_DESCDMA_S) +#define USB_G_DESCDMA_V 0x00000001 +#define USB_G_DESCDMA_S 31 + + +/** USB_HFNUM_REG register + * Frame Number configure Resigster + */ +#define USB_HFNUM_REG (SOC_DPORT_USB_BASE + 0x408) +/** USB_FRNUM : RO; bitpos: [14:0]; default: 16383; + * Frame Number + * 0x0 (INACTIVE): No SOF is transmitted + * 0x1 (ACTIVE): SOF is transmitted + */ +#define USB_FRNUM 0x00003FFF +#define USB_FRNUM_M (USB_FRNUM_V << USB_FRNUM_S) +#define USB_FRNUM_V 0x00003FFF +#define USB_FRNUM_S 0 +/** USB_FRREM : RO; bitpos: [32:16]; default: 0; + * Frame Time Remaining.ndicates the amount of time remaining in the current + * microframe + * (HS) or Frame (FS/LS), in terms of PHY clocks. + */ +#define USB_FRREM 0x0000FFFF +#define USB_FRREM_M (USB_FRREM_V << USB_FRREM_S) +#define USB_FRREM_V 0x0000FFFF +#define USB_FRREM_S 16 + + +/** USB_HPTXSTS_REG register + * Host Periodic Transmit FIFO/Queue Status Register + */ +#define USB_HPTXSTS_REG (SOC_DPORT_USB_BASE + 0x410) +/** USB_PTXFSPCAVAIL : RO; bitpos: [16:0]; default: 256; + * Periodic Transmit Data FIFO Space Available. Values are in terms of 32-bit words. + */ +#define USB_PTXFSPCAVAIL 0x0000FFFF +#define USB_PTXFSPCAVAIL_M (USB_PTXFSPCAVAIL_V << USB_PTXFSPCAVAIL_S) +#define USB_PTXFSPCAVAIL_V 0x0000FFFF +#define USB_PTXFSPCAVAIL_S 0 +/** USB_PTXQSPCAVAIL : RO; bitpos: [21:16]; default: 8; + * Periodic Transmit Request Queue Space Available. + */ +#define USB_PTXQSPCAVAIL 0x0000001F +#define USB_PTXQSPCAVAIL_M (USB_PTXQSPCAVAIL_V << USB_PTXQSPCAVAIL_S) +#define USB_PTXQSPCAVAIL_V 0x0000001F +#define USB_PTXQSPCAVAIL_S 16 +/** USB_PTXQTOP : RO; bitpos: [32:24]; default: 0; + * Bit [31]: Odd/Even (micro)Frame. 1'b0: send in even (micro)Frame + * Bits [30:27]: Channel/endpoint number + * Bits [26:25]: Type. 2'b00: IN/OUT. 2'b01: Zero-length packet. 2'b10: CSPLIT + * 2'b11: Disable channel command + * Bit [24]: Terminate + */ +#define USB_PTXQTOP 0x000000FF +#define USB_PTXQTOP_M (USB_PTXQTOP_V << USB_PTXQTOP_S) +#define USB_PTXQTOP_V 0x000000FF +#define USB_PTXQTOP_S 24 + + +/** USB_HCDMAB$n_REG register + * Host Channel $n DMA Buffer Address Register + */ +#define USB_HCDMAB$N_REG (SOC_DPORT_USB_BASE + 0x51c) +/** USB_H_HCDMAB0 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address + */ +#define USB_H_HCDMAB0 0xFFFFFFFF +#define USB_H_HCDMAB0_M (USB_H_HCDMAB0_V << USB_H_HCDMAB0_S) +#define USB_H_HCDMAB0_V 0xFFFFFFFF +#define USB_H_HCDMAB0_S 0 + + +/** USB_HCDMAB1_REG register + * Host Channel 1 DMA Buffer Address Register + */ +#define USB_HCDMAB1_REG (SOC_DPORT_USB_BASE + 0x53c) +/** USB_H_HCDMAB1 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address + */ +#define USB_H_HCDMAB1 0xFFFFFFFF +#define USB_H_HCDMAB1_M (USB_H_HCDMAB1_V << USB_H_HCDMAB1_S) +#define USB_H_HCDMAB1_V 0xFFFFFFFF +#define USB_H_HCDMAB1_S 0 + + +/** USB_HCDMAB2_REG register + * Host Channel 2 DMA Buffer Address Register + */ +#define USB_HCDMAB2_REG (SOC_DPORT_USB_BASE + 0x55c) +/** USB_H_HCDMAB2 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address + */ +#define USB_H_HCDMAB2 0xFFFFFFFF +#define USB_H_HCDMAB2_M (USB_H_HCDMAB2_V << USB_H_HCDMAB2_S) +#define USB_H_HCDMAB2_V 0xFFFFFFFF +#define USB_H_HCDMAB2_S 0 + + +/** USB_HCDMAB3_REG register + * Host Channel 3 DMA Buffer Address Register + */ +#define USB_HCDMAB3_REG (SOC_DPORT_USB_BASE + 0x57c) +/** USB_H_HCDMAB3 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address + */ +#define USB_H_HCDMAB3 0xFFFFFFFF +#define USB_H_HCDMAB3_M (USB_H_HCDMAB3_V << USB_H_HCDMAB3_S) +#define USB_H_HCDMAB3_V 0xFFFFFFFF +#define USB_H_HCDMAB3_S 0 + + +/** USB_HCDMAB4_REG register + * Host Channel 4 DMA Buffer Address Register + */ +#define USB_HCDMAB4_REG (SOC_DPORT_USB_BASE + 0x59c) +/** USB_H_HCDMAB4 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address + */ +#define USB_H_HCDMAB4 0xFFFFFFFF +#define USB_H_HCDMAB4_M (USB_H_HCDMAB4_V << USB_H_HCDMAB4_S) +#define USB_H_HCDMAB4_V 0xFFFFFFFF +#define USB_H_HCDMAB4_S 0 + + +/** USB_HCDMAB5_REG register + * Host Channel 5 DMA Buffer Address Register + */ +#define USB_HCDMAB5_REG (SOC_DPORT_USB_BASE + 0x5bc) +/** USB_H_HCDMAB5 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address + */ +#define USB_H_HCDMAB5 0xFFFFFFFF +#define USB_H_HCDMAB5_M (USB_H_HCDMAB5_V << USB_H_HCDMAB5_S) +#define USB_H_HCDMAB5_V 0xFFFFFFFF +#define USB_H_HCDMAB5_S 0 + + +/** USB_HCDMAB6_REG register + * Host Channel 6 DMA Buffer Address Register + */ +#define USB_HCDMAB6_REG (SOC_DPORT_USB_BASE + 0x5dc) +/** USB_H_HCDMAB6 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address + */ +#define USB_H_HCDMAB6 0xFFFFFFFF +#define USB_H_HCDMAB6_M (USB_H_HCDMAB6_V << USB_H_HCDMAB6_S) +#define USB_H_HCDMAB6_V 0xFFFFFFFF +#define USB_H_HCDMAB6_S 0 + + +/** USB_HCDMAB7_REG register + * Host Channel 7 DMA Buffer Address Register + */ +#define USB_HCDMAB7_REG (SOC_DPORT_USB_BASE + 0x5fc) +/** USB_H_HCDMAB7 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address + */ +#define USB_H_HCDMAB7 0xFFFFFFFF +#define USB_H_HCDMAB7_M (USB_H_HCDMAB7_V << USB_H_HCDMAB7_S) +#define USB_H_HCDMAB7_V 0xFFFFFFFF +#define USB_H_HCDMAB7_S 0 + + +/** USB_DSTS_REG register + * Device Status Register + */ +#define USB_DSTS_REG (SOC_DPORT_USB_BASE + 0x808) +/** USB_SUSPSTS : RO; bitpos: [0]; default: 0; + * Suspend Status + * 0x0 : No suspend state + * 0x1 : Suspend state + */ +#define USB_SUSPSTS (BIT(0)) +#define USB_SUSPSTS_M (USB_SUSPSTS_V << USB_SUSPSTS_S) +#define USB_SUSPSTS_V 0x00000001 +#define USB_SUSPSTS_S 0 +/** USB_ENUMSPD : RO; bitpos: [3:1]; default: 1; + * 0x0 : High speed (PHY clock is running at 30 or 60 MHz) + * 0x1 : Full speed (PHY clock is running at 30 or 60 MHz) + * 0x2 : Low speed (PHY clock is running at 6 MHz) + * 0x3 : Full speed (PHY clock is running at 48 MHz) + */ +#define USB_ENUMSPD 0x00000003 +#define USB_ENUMSPD_M (USB_ENUMSPD_V << USB_ENUMSPD_S) +#define USB_ENUMSPD_V 0x00000003 +#define USB_ENUMSPD_S 1 +/** USB_ERRTICERR : RO; bitpos: [3]; default: 0; + * 0x0 : No Erratic Error + * 0x1 : Erratic Error + */ +#define USB_ERRTICERR (BIT(3)) +#define USB_ERRTICERR_M (USB_ERRTICERR_V << USB_ERRTICERR_S) +#define USB_ERRTICERR_V 0x00000001 +#define USB_ERRTICERR_S 3 +/** USB_SOFFN : RO; bitpos: [22:8]; default: 0; + * Frame or Microframe Number of the Received SOF (SOFFN). This field contains a + * Frame number. + */ +#define USB_SOFFN 0x00003FFF +#define USB_SOFFN_M (USB_SOFFN_V << USB_SOFFN_S) +#define USB_SOFFN_V 0x00003FFF +#define USB_SOFFN_S 8 +/** USB_DEVLNSTS : RO; bitpos: [24:22]; default: 0; + * Device Line Status + * DevLnSts[1]: Logic level of D+ + * DevLnSts[0]: Logic level of D- + */ +#define USB_DEVLNSTS 0x00000003 +#define USB_DEVLNSTS_M (USB_DEVLNSTS_V << USB_DEVLNSTS_S) +#define USB_DEVLNSTS_V 0x00000003 +#define USB_DEVLNSTS_S 22 + + +/** USB_DTXFSTS0_REG register + * Device IN Endpoint Transmit FIFO Status Register 0 + */ +#define USB_DTXFSTS0_REG (SOC_DPORT_USB_BASE + 0x918) +/** USB_D_INEPTXFSPCAVAIL0 : RO; bitpos: [16:0]; default: 0; + * Indicates the amount of free space available in the Endpoint TxFIFO. + */ +#define USB_D_INEPTXFSPCAVAIL0 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL0_M (USB_D_INEPTXFSPCAVAIL0_V << USB_D_INEPTXFSPCAVAIL0_S) +#define USB_D_INEPTXFSPCAVAIL0_V 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL0_S 0 + + +/** USB_DIEPDMAB0_REG register + * Device IN Endpoint 16 Buffer Address Register + */ +#define USB_DIEPDMAB0_REG (SOC_DPORT_USB_BASE + 0x91c) +/** USB_D_DMABUFFERADDR0 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_D_DMABUFFERADDR0 0xFFFFFFFF +#define USB_D_DMABUFFERADDR0_M (USB_D_DMABUFFERADDR0_V << USB_D_DMABUFFERADDR0_S) +#define USB_D_DMABUFFERADDR0_V 0xFFFFFFFF +#define USB_D_DMABUFFERADDR0_S 0 + + +/** USB_DTXFSTS1_REG register + * Device IN Endpoint Transmit FIFO Status Register 1 + */ +#define USB_DTXFSTS1_REG (SOC_DPORT_USB_BASE + 0x938) +/** USB_D_INEPTXFSPCAVAIL1 : RO; bitpos: [16:0]; default: 0; + * Indicates the amount of free space available in the Endpoint TxFIFO. + */ +#define USB_D_INEPTXFSPCAVAIL1 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL1_M (USB_D_INEPTXFSPCAVAIL1_V << USB_D_INEPTXFSPCAVAIL1_S) +#define USB_D_INEPTXFSPCAVAIL1_V 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL1_S 0 + + +/** USB_DIEPDMAB1_REG register + * Device IN Endpoint 16 Buffer Address Register + */ +#define USB_DIEPDMAB1_REG (SOC_DPORT_USB_BASE + 0x93c) +/** USB_D_DMABUFFERADDR1 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_D_DMABUFFERADDR1 0xFFFFFFFF +#define USB_D_DMABUFFERADDR1_M (USB_D_DMABUFFERADDR1_V << USB_D_DMABUFFERADDR1_S) +#define USB_D_DMABUFFERADDR1_V 0xFFFFFFFF +#define USB_D_DMABUFFERADDR1_S 0 + + +/** USB_DTXFSTS2_REG register + * Device IN Endpoint Transmit FIFO Status Register 2 + */ +#define USB_DTXFSTS2_REG (SOC_DPORT_USB_BASE + 0x958) +/** USB_D_INEPTXFSPCAVAIL2 : RO; bitpos: [16:0]; default: 0; + * Indicates the amount of free space available in the Endpoint TxFIFO. + */ +#define USB_D_INEPTXFSPCAVAIL2 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL2_M (USB_D_INEPTXFSPCAVAIL2_V << USB_D_INEPTXFSPCAVAIL2_S) +#define USB_D_INEPTXFSPCAVAIL2_V 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL2_S 0 + + +/** USB_DIEPDMAB2_REG register + * Device IN Endpoint 16 Buffer Address Register + */ +#define USB_DIEPDMAB2_REG (SOC_DPORT_USB_BASE + 0x95c) +/** USB_D_DMABUFFERADDR2 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_D_DMABUFFERADDR2 0xFFFFFFFF +#define USB_D_DMABUFFERADDR2_M (USB_D_DMABUFFERADDR2_V << USB_D_DMABUFFERADDR2_S) +#define USB_D_DMABUFFERADDR2_V 0xFFFFFFFF +#define USB_D_DMABUFFERADDR2_S 0 + + +/** USB_DTXFSTS3_REG register + * Device IN Endpoint Transmit FIFO Status Register 3 + */ +#define USB_DTXFSTS3_REG (SOC_DPORT_USB_BASE + 0x978) +/** USB_D_INEPTXFSPCAVAIL3 : RO; bitpos: [16:0]; default: 0; + * Indicates the amount of free space available in the Endpoint TxFIFO. + */ +#define USB_D_INEPTXFSPCAVAIL3 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL3_M (USB_D_INEPTXFSPCAVAIL3_V << USB_D_INEPTXFSPCAVAIL3_S) +#define USB_D_INEPTXFSPCAVAIL3_V 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL3_S 0 + + +/** USB_DIEPDMAB3_REG register + * Device IN Endpoint 16 Buffer Address Register + */ +#define USB_DIEPDMAB3_REG (SOC_DPORT_USB_BASE + 0x97c) +/** USB_D_DMABUFFERADDR3 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_D_DMABUFFERADDR3 0xFFFFFFFF +#define USB_D_DMABUFFERADDR3_M (USB_D_DMABUFFERADDR3_V << USB_D_DMABUFFERADDR3_S) +#define USB_D_DMABUFFERADDR3_V 0xFFFFFFFF +#define USB_D_DMABUFFERADDR3_S 0 + + +/** USB_DTXFSTS4_REG register + * Device IN Endpoint Transmit FIFO Status Register 4 + */ +#define USB_DTXFSTS4_REG (SOC_DPORT_USB_BASE + 0x998) +/** USB_D_INEPTXFSPCAVAIL4 : RO; bitpos: [16:0]; default: 0; + * Indicates the amount of free space available in the Endpoint TxFIFO. + */ +#define USB_D_INEPTXFSPCAVAIL4 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL4_M (USB_D_INEPTXFSPCAVAIL4_V << USB_D_INEPTXFSPCAVAIL4_S) +#define USB_D_INEPTXFSPCAVAIL4_V 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL4_S 0 + + +/** USB_DIEPDMAB4_REG register + * Device IN Endpoint 16 Buffer Address Register + */ +#define USB_DIEPDMAB4_REG (SOC_DPORT_USB_BASE + 0x99c) +/** USB_D_DMABUFFERADDR4 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_D_DMABUFFERADDR4 0xFFFFFFFF +#define USB_D_DMABUFFERADDR4_M (USB_D_DMABUFFERADDR4_V << USB_D_DMABUFFERADDR4_S) +#define USB_D_DMABUFFERADDR4_V 0xFFFFFFFF +#define USB_D_DMABUFFERADDR4_S 0 + + +/** USB_DTXFSTS5_REG register + * Device IN Endpoint Transmit FIFO Status Register 5 + */ +#define USB_DTXFSTS5_REG (SOC_DPORT_USB_BASE + 0x9b8) +/** USB_D_INEPTXFSPCAVAIL5 : RO; bitpos: [16:0]; default: 0; + * Indicates the amount of free space available in the Endpoint TxFIFO. + */ +#define USB_D_INEPTXFSPCAVAIL5 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL5_M (USB_D_INEPTXFSPCAVAIL5_V << USB_D_INEPTXFSPCAVAIL5_S) +#define USB_D_INEPTXFSPCAVAIL5_V 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL5_S 0 + + +/** USB_DIEPDMAB5_REG register + * Device IN Endpoint 16 Buffer Address Register + */ +#define USB_DIEPDMAB5_REG (SOC_DPORT_USB_BASE + 0x9bc) +/** USB_D_DMABUFFERADDR5 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_D_DMABUFFERADDR5 0xFFFFFFFF +#define USB_D_DMABUFFERADDR5_M (USB_D_DMABUFFERADDR5_V << USB_D_DMABUFFERADDR5_S) +#define USB_D_DMABUFFERADDR5_V 0xFFFFFFFF +#define USB_D_DMABUFFERADDR5_S 0 + + +/** USB_DTXFSTS6_REG register + * Device IN Endpoint Transmit FIFO Status Register 6 + */ +#define USB_DTXFSTS6_REG (SOC_DPORT_USB_BASE + 0x9d8) +/** USB_D_INEPTXFSPCAVAIL6 : RO; bitpos: [16:0]; default: 0; + * Indicates the amount of free space available in the Endpoint TxFIFO. + */ +#define USB_D_INEPTXFSPCAVAIL6 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL6_M (USB_D_INEPTXFSPCAVAIL6_V << USB_D_INEPTXFSPCAVAIL6_S) +#define USB_D_INEPTXFSPCAVAIL6_V 0x0000FFFF +#define USB_D_INEPTXFSPCAVAIL6_S 0 + + +/** USB_DIEPDMAB6_REG register + * Device IN Endpoint 16 Buffer Address Register + */ +#define USB_DIEPDMAB6_REG (SOC_DPORT_USB_BASE + 0x9dc) +/** USB_D_DMABUFFERADDR6 : RO; bitpos: [32:0]; default: 0; + * Holds the current buffer address.This register is updated as and when the data + * transfer for the corresponding end point is in progress. This register is present + * only in Scatter/Gather DMA mode. Otherwise this field is reserved. + */ +#define USB_D_DMABUFFERADDR6 0xFFFFFFFF +#define USB_D_DMABUFFERADDR6_M (USB_D_DMABUFFERADDR6_V << USB_D_DMABUFFERADDR6_S) +#define USB_D_DMABUFFERADDR6_V 0xFFFFFFFF +#define USB_D_DMABUFFERADDR6_S 0 + + + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/usb_struct.h b/components/soc/esp32s3/include/soc/usb_struct.h new file mode 100644 index 0000000000..e387490e9f --- /dev/null +++ b/components/soc/esp32s3/include/soc/usb_struct.h @@ -0,0 +1,107 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "usb_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct usb_reg { + volatile uint32_t gotgctl; /*!< 0x0 */ + volatile uint32_t gotgint; + volatile uint32_t gahbcfg; + volatile uint32_t gusbcfg; + volatile uint32_t grstctl; /*!< 0x10 */ + volatile uint32_t gintsts; + volatile uint32_t gintmsk; + volatile uint32_t grxstsr; + volatile uint32_t grxstsp; /*!< 0x20 */ + volatile uint32_t grxfsiz; + volatile uint32_t gnptxfsiz; + volatile uint32_t gnptxsts; + volatile uint32_t reserved0x2c; + volatile uint32_t gpvndctl; /*!< 0x30 */ + volatile uint32_t ggpio; + volatile uint32_t guid; + volatile uint32_t gsnpsid; + volatile uint32_t ghwcfg1; /*!< 0x40 */ + volatile uint32_t ghwcfg2; + volatile uint32_t ghwcfg3; + volatile uint32_t ghwcfg4; /*!< 0x50 */ + volatile uint32_t glpmcfg; /*!< 0x54 */ + volatile uint32_t gpwrdn; /*!< 0x58 */ + volatile uint32_t gdfifocfg; /*!< 0x5c */ + volatile uint32_t gadpctl; /*!< 0x60 */ + uint32_t reserved0x64[39]; + volatile uint32_t hptxfsiz; /*!< 0x100 */ + volatile uint32_t dieptxf[15]; /*!< 0x104 */ + uint32_t reserved0x140[176]; /*!< 0x140 */ + /** + * The Host Global Registers structure defines the size and relative + * field offsets for the Host Mode Global Registers. Host Global + * Registers offsets 400h-7FFh. + */ + volatile uint32_t hcfg; /*!< Host Configuration Register. Offset: 400h */ + volatile uint32_t hfir; /*!< Host Frame Interval Register. Offset: 404h */ + volatile uint32_t hfnum; /*!< Host Frame Number / Frame Remaining Register. Offset: 408h */ + uint32_t reserved0x40C; /*!< Reserved. Offset: 40Ch */ + volatile uint32_t hptxsts; /*!< Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ + volatile uint32_t haint; /*!< Host All Channels Interrupt Register. Offset: 414h */ + volatile uint32_t haintmsk; /*!< Host All Channels Interrupt Mask Register. Offset: 418h */ + volatile uint32_t hflbaddr; /*!< Host Frame List Base Address Register . Offset: 41Ch */ + uint32_t reserved0x420[7]; + volatile uint32_t hprt; //0x440 + uint32_t reserved0x444[240]; + volatile uint32_t dcfg; /*!< Device Configuration Register. Offset 800h */ + volatile uint32_t dctl; /*!< Device Control Register. Offset: 804h */ + volatile uint32_t dsts; /*!< Device Status Register (Read Only). Offset: 808h */ + uint32_t reserved0x80c; /*!< Reserved. Offset: 80Ch */ + volatile uint32_t diepmsk; /*!< Device IN Endpoint Common Interrupt Mask Register. Offset: 810h */ + volatile uint32_t doepmsk; /*!< Device OUT Endpoint Common Interrupt Mask Register. Offset: 814h */ + volatile uint32_t daint; /*!< Device All Endpoints Interrupt Register. Offset: 818h */ + volatile uint32_t daintmsk; /*!< Device All Endpoints Interrupt Mask Register. Offset: 81Ch */ + volatile uint32_t dtknqr1; /*!< Device IN Token Queue Read Register-1 (Read Only). Offset: 820h */ + volatile uint32_t dtknqr2; /*!< Device IN Token Queue Read Register-2 (Read Only). Offset: 824h */ + volatile uint32_t dvbusdis; /*!< Device VBUS discharge Register. Offset: 828h */ + volatile uint32_t dvbuspulse; /*!< Device VBUS Pulse Register. Offset: 82Ch */ + volatile uint32_t dtknqr3_dthrctl; /*!< Device IN Token Queue Read Register-3 (Read Only). Device Thresholding control register (Read/Write) Offset: 830h */ + volatile uint32_t dtknqr4_fifoemptymsk; /*!< Device IN Token Queue Read Register-4 (Read Only). Device IN EPs empty Inr. Mask Register (Read/Write)Offset: 834h */ + volatile uint32_t deachint; /*!< Device Each Endpoint Interrupt Register (Read Only). Offset: 838h */ + volatile uint32_t deachintmsk; /*!< Device Each Endpoint Interrupt mask Register (Read/Write). Offset: 83Ch */ + volatile uint32_t diepeachintmsk[16]; /*!< Device Each In Endpoint Interrupt mask Register (Read/Write). Offset: 840h */ + volatile uint32_t doepeachintmsk[16]; /*!< Device Each Out Endpoint Interrupt mask Register (Read/Write). Offset: 880h */ + uint32_t reserved0x8c0[16]; + /* Input Endpoints*/ + usb_in_endpoint_t in_ep_reg[USB_IN_EP_NUM]; /*!< 0x900*/ + uint32_t reserved6[72]; + /* Output Endpoints */ + usb_out_endpoint_t out_ep_reg[USB_OUT_EP_NUM]; + uint32_t reserved7[136]; + uint32_t pcgctrl; /*!<0xe00*/ + uint32_t pcgctrl1; + uint8_t reserved8[0x1000 - 0xe08]; /*!<0xd00*/ + uint32_t fifo[16][0x400]; /*!<0x1000*/ + uint8_t reserved0x11000[0x20000 - 0x11000]; + uint32_t dbg_fifo[0x20000]; /*!< 0x20000*/ +} usb_dev_t; + +extern usb_dev_t USB0; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/usb_types.h b/components/soc/esp32s3/include/soc/usb_types.h new file mode 100644 index 0000000000..69e213ec84 --- /dev/null +++ b/components/soc/esp32s3/include/soc/usb_types.h @@ -0,0 +1,73 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/* USB IN EP index */ +typedef enum { + USB_IN_EP_0 = 0, + USB_IN_EP_1, + USB_IN_EP_2, + USB_IN_EP_3, + USB_IN_EP_4, + USB_IN_EP_5, + USB_IN_EP_6, + USB_IN_EP_NUM +} usb_in_ep_idx_t; + +/* USB OUT EP index */ +typedef enum { + USB_OUT_EP_0 = 0, + USB_OUT_EP_1, + USB_OUT_EP_2, + USB_OUT_EP_3, + USB_OUT_EP_4, + USB_OUT_EP_5, + USB_OUT_EP_6, + USB_OUT_EP_NUM +} usb_out_ep_idx_t; + +/* USB IN EP Register block type */ +typedef struct usb_in_ep_reg { + volatile uint32_t diepctl; + uint32_t reserved; + volatile uint32_t diepint; + uint32_t reserved1; + volatile uint32_t dieptsiz; + volatile uint32_t diepdma; + volatile uint32_t dtxfsts; + uint32_t reserved2; +} usb_in_endpoint_t; + +/* USB OUT EP Register block type */ +typedef struct usb_out_ep_reg { + volatile uint32_t doepctl; + uint32_t reserved; + volatile uint32_t doepint; + uint32_t reserved1; + volatile uint32_t doeptsiz; + volatile uint32_t doepdma; + uint32_t reserved2; + uint32_t reserved3; +} usb_out_endpoint_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/usb_wrap_reg.h b/components/soc/esp32s3/include/soc/usb_wrap_reg.h new file mode 100644 index 0000000000..e4ea6b7a77 --- /dev/null +++ b/components/soc/esp32s3/include/soc/usb_wrap_reg.h @@ -0,0 +1,252 @@ +/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_WRAP_OTG_CONF_REG register + * PAD/DFIFO/PHY configuration register. + */ +#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0) +/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software override of srp session end signal.1'b0: + * the signal is controlled by the chip input.1'b1: the signal is controlled by the + * software. + */ +#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0)) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001 +#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0 +/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0; + * Software override value of srp session end signal. + */ +#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1)) +#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S) +#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001 +#define USB_WRAP_SRP_SESSEND_VALUE_S 1 +/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0; + * Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY + */ +#define USB_WRAP_PHY_SEL (BIT(2)) +#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S) +#define USB_WRAP_PHY_SEL_V 0x00000001 +#define USB_WRAP_PHY_SEL_S 2 +/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ +#define USB_WRAP_DFIFO_FORCE_PD (BIT(3)) +#define USB_WRAP_DFIFO_FORCE_PD_M (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S) +#define USB_WRAP_DFIFO_FORCE_PD_V 0x00000001 +#define USB_WRAP_DFIFO_FORCE_PD_S 3 +/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid. + */ +#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4)) +#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S) +#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001 +#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4 +/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0; + * Enable software to control USB D+ D- exchange + */ +#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5)) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001 +#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5 +/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0; + * USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-. + */ +#define USB_WRAP_EXCHG_PINS (BIT(6)) +#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S) +#define USB_WRAP_EXCHG_PINS_V 0x00000001 +#define USB_WRAP_EXCHG_PINS_S 6 +/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold. + */ +#define USB_WRAP_VREFH 0x00000003 +#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S) +#define USB_WRAP_VREFH_V 0x00000003 +#define USB_WRAP_VREFH_S 7 +/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold. + */ +#define USB_WRAP_VREFL 0x00000003 +#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S) +#define USB_WRAP_VREFL_V 0x00000003 +#define USB_WRAP_VREFL_S 9 +/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0; + * Enable software to control input threshold. + */ +#define USB_WRAP_VREF_OVERRIDE (BIT(11)) +#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S) +#define USB_WRAP_VREF_OVERRIDE_V 0x00000001 +#define USB_WRAP_VREF_OVERRIDE_S 11 +/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0; + * Enable software to control USB pad in pullup or pulldown mode. + */ +#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12)) +#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S) +#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001 +#define USB_WRAP_PAD_PULL_OVERRIDE_S 12 +/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0; + * Control USB D+ pullup. + */ +#define USB_WRAP_DP_PULLUP (BIT(13)) +#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S) +#define USB_WRAP_DP_PULLUP_V 0x00000001 +#define USB_WRAP_DP_PULLUP_S 13 +/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0; + * Control USB D+ pulldown. + */ +#define USB_WRAP_DP_PULLDOWN (BIT(14)) +#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S) +#define USB_WRAP_DP_PULLDOWN_V 0x00000001 +#define USB_WRAP_DP_PULLDOWN_S 14 +/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0; + * Control USB D+ pullup. + */ +#define USB_WRAP_DM_PULLUP (BIT(15)) +#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S) +#define USB_WRAP_DM_PULLUP_V 0x00000001 +#define USB_WRAP_DM_PULLUP_S 15 +/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0; + * Control USB D+ pulldown. + */ +#define USB_WRAP_DM_PULLDOWN (BIT(16)) +#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S) +#define USB_WRAP_DM_PULLDOWN_V 0x00000001 +#define USB_WRAP_DM_PULLDOWN_S 16 +/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0; + * Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K. + */ +#define USB_WRAP_PULLUP_VALUE (BIT(17)) +#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S) +#define USB_WRAP_PULLUP_VALUE_V 0x00000001 +#define USB_WRAP_PULLUP_VALUE_S 17 +/** USB_WRAP_PAD_ENABLE : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ +#define USB_WRAP_PAD_ENABLE (BIT(18)) +#define USB_WRAP_PAD_ENABLE_M (USB_WRAP_PAD_ENABLE_V << USB_WRAP_PAD_ENABLE_S) +#define USB_WRAP_PAD_ENABLE_V 0x00000001 +#define USB_WRAP_PAD_ENABLE_S 18 +/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 1; + * Force AHB clock always on. + */ +#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19)) +#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S) +#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001 +#define USB_WRAP_AHB_CLK_FORCE_ON_S 19 +/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1; + * Force PHY clock always on. + */ +#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20)) +#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S) +#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001 +#define USB_WRAP_PHY_CLK_FORCE_ON_S 20 +/** USB_WRAP_PHY_TX_EDGE_SEL : R/W; bitpos: [21]; default: 0; + * Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge. + */ +#define USB_WRAP_PHY_TX_EDGE_SEL (BIT(21)) +#define USB_WRAP_PHY_TX_EDGE_SEL_M (USB_WRAP_PHY_TX_EDGE_SEL_V << USB_WRAP_PHY_TX_EDGE_SEL_S) +#define USB_WRAP_PHY_TX_EDGE_SEL_V 0x00000001 +#define USB_WRAP_PHY_TX_EDGE_SEL_S 21 +/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ +#define USB_WRAP_DFIFO_FORCE_PU (BIT(22)) +#define USB_WRAP_DFIFO_FORCE_PU_M (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S) +#define USB_WRAP_DFIFO_FORCE_PU_V 0x00000001 +#define USB_WRAP_DFIFO_FORCE_PU_S 22 +/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ +#define USB_WRAP_CLK_EN (BIT(31)) +#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S) +#define USB_WRAP_CLK_EN_V 0x00000001 +#define USB_WRAP_CLK_EN_S 31 + +/** USB_WRAP_TEST_CONF_REG register + * TEST relative configuration registers. + */ +#define USB_WRAP_TEST_CONF_REG (DR_REG_USB_WRAP_BASE + 0x4) +/** USB_WRAP_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable to test the USB pad. + */ +#define USB_WRAP_TEST_ENABLE (BIT(0)) +#define USB_WRAP_TEST_ENABLE_M (USB_WRAP_TEST_ENABLE_V << USB_WRAP_TEST_ENABLE_S) +#define USB_WRAP_TEST_ENABLE_V 0x00000001 +#define USB_WRAP_TEST_ENABLE_S 0 +/** USB_WRAP_TEST_USB_WRAP_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test. + */ +#define USB_WRAP_TEST_USB_WRAP_OE (BIT(1)) +#define USB_WRAP_TEST_USB_WRAP_OE_M (USB_WRAP_TEST_USB_WRAP_OE_V << USB_WRAP_TEST_USB_WRAP_OE_S) +#define USB_WRAP_TEST_USB_WRAP_OE_V 0x00000001 +#define USB_WRAP_TEST_USB_WRAP_OE_S 1 +/** USB_WRAP_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test. + */ +#define USB_WRAP_TEST_TX_DP (BIT(2)) +#define USB_WRAP_TEST_TX_DP_M (USB_WRAP_TEST_TX_DP_V << USB_WRAP_TEST_TX_DP_S) +#define USB_WRAP_TEST_TX_DP_V 0x00000001 +#define USB_WRAP_TEST_TX_DP_S 2 +/** USB_WRAP_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test. + */ +#define USB_WRAP_TEST_TX_DM (BIT(3)) +#define USB_WRAP_TEST_TX_DM_M (USB_WRAP_TEST_TX_DM_V << USB_WRAP_TEST_TX_DM_S) +#define USB_WRAP_TEST_TX_DM_V 0x00000001 +#define USB_WRAP_TEST_TX_DM_S 3 +/** USB_WRAP_TEST_RX_RCV : RO; bitpos: [4]; default: 0; + * USB differential rx value in test. + */ +#define USB_WRAP_TEST_RX_RCV (BIT(4)) +#define USB_WRAP_TEST_RX_RCV_M (USB_WRAP_TEST_RX_RCV_V << USB_WRAP_TEST_RX_RCV_S) +#define USB_WRAP_TEST_RX_RCV_V 0x00000001 +#define USB_WRAP_TEST_RX_RCV_S 4 +/** USB_WRAP_TEST_RX_DP : RO; bitpos: [5]; default: 0; + * USB D+ rx value in test. + */ +#define USB_WRAP_TEST_RX_DP (BIT(5)) +#define USB_WRAP_TEST_RX_DP_M (USB_WRAP_TEST_RX_DP_V << USB_WRAP_TEST_RX_DP_S) +#define USB_WRAP_TEST_RX_DP_V 0x00000001 +#define USB_WRAP_TEST_RX_DP_S 5 +/** USB_WRAP_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test. + */ +#define USB_WRAP_TEST_RX_DM (BIT(6)) +#define USB_WRAP_TEST_RX_DM_M (USB_WRAP_TEST_RX_DM_V << USB_WRAP_TEST_RX_DM_S) +#define USB_WRAP_TEST_RX_DM_V 0x00000001 +#define USB_WRAP_TEST_RX_DM_S 6 + +/** USB_WRAP_DATE_REG register + * Version register. + */ +#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc) +/** USB_WRAP_DATE : R/W; bitpos: [31:0]; default: 419631616; + * data register. + */ +#define USB_WRAP_DATE 0xFFFFFFFF +#define USB_WRAP_DATE_M (USB_WRAP_DATE_V << USB_WRAP_DATE_S) +#define USB_WRAP_DATE_V 0xFFFFFFFF +#define USB_WRAP_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/usb_wrap_struct.h b/components/soc/esp32s3/include/soc/usb_wrap_struct.h new file mode 100644 index 0000000000..147afc3228 --- /dev/null +++ b/components/soc/esp32s3/include/soc/usb_wrap_struct.h @@ -0,0 +1,441 @@ +/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Control/Status registers */ +/** Type of otg_conf register + * PAD/DFIFO/PHY configuration register. + */ +typedef union { + struct { + /** srp_sessend_override : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software override of srp session end signal.1'b0: + * the signal is controlled by the chip input.1'b1: the signal is controlled by the + * software. + */ + uint32_t srp_sessend_override:1; + /** srp_sessend_value : R/W; bitpos: [1]; default: 0; + * Software override value of srp session end signal. + */ + uint32_t srp_sessend_value:1; + /** phy_sel : R/W; bitpos: [2]; default: 0; + * Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY + */ + uint32_t phy_sel:1; + /** dfifo_force_pd : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pd:1; + /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid. + */ + uint32_t dbnce_fltr_bypass:1; + /** exchg_pins_override : R/W; bitpos: [5]; default: 0; + * Enable software to control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [6]; default: 0; + * USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-. + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold. + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold. + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [11]; default: 0; + * Enable software to control input threshold. + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [12]; default: 0; + * Enable software to control USB pad in pullup or pulldown mode. + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [13]; default: 0; + * Control USB D+ pullup. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [14]; default: 0; + * Control USB D+ pulldown. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [15]; default: 0; + * Control USB D+ pullup. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [16]; default: 0; + * Control USB D+ pulldown. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [17]; default: 0; + * Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K. + */ + uint32_t pullup_value:1; + /** pad_enable : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ + uint32_t pad_enable:1; + /** ahb_clk_force_on : R/W; bitpos: [19]; default: 1; + * Force AHB clock always on. + */ + uint32_t ahb_clk_force_on:1; + /** phy_clk_force_on : R/W; bitpos: [20]; default: 1; + * Force PHY clock always on. + */ + uint32_t phy_clk_force_on:1; + /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0; + * Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge. + */ + uint32_t phy_tx_edge_sel:1; + /** dfifo_force_pu : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pu:1; + uint32_t reserved_23:8; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} usb_wrap_otg_conf_reg_t; + +/** Type of test_conf register + * TEST relative configuration registers. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable to test the USB pad. + */ + uint32_t test_enable:1; + /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test. + */ + uint32_t test_usb_wrap_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test. + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test. + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 0; + * USB differential rx value in test. + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 0; + * USB D+ rx value in test. + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test. + */ + uint32_t test_rx_dm:1; + }; + uint32_t val; +} usb_wrap_test_conf_reg_t; + + +/** Status registers */ +/** Type of date register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 419631616; + * data register. + */ + uint32_t date:32; + }; + uint32_t val; +} usb_wrap_date_reg_t; + + +typedef struct { + volatile usb_wrap_otg_conf_reg_t otg_conf; + volatile usb_wrap_test_conf_reg_t test_conf; + uint32_t reserved_008; + uint32_t reserved_00c; + uint32_t reserved_010; + uint32_t reserved_014; + uint32_t reserved_018; + uint32_t reserved_01c; + uint32_t reserved_020; + uint32_t reserved_024; + uint32_t reserved_028; + uint32_t reserved_02c; + uint32_t reserved_030; + uint32_t reserved_034; + uint32_t reserved_038; + uint32_t reserved_03c; + uint32_t reserved_040; + uint32_t reserved_044; + uint32_t reserved_048; + uint32_t reserved_04c; + uint32_t reserved_050; + uint32_t reserved_054; + uint32_t reserved_058; + uint32_t reserved_05c; + uint32_t reserved_060; + uint32_t reserved_064; + uint32_t reserved_068; + uint32_t reserved_06c; + uint32_t reserved_070; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + uint32_t reserved_0fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + volatile usb_wrap_date_reg_t date; +} usb_wrap_dev_t; + +_Static_assert(sizeof(usb_wrap_dev_t)==0x400, "Invalid USB_WRAP size"); + +extern usb_wrap_dev_t USB_WRAP; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/world_controller_reg.h b/components/soc/esp32s3/include/soc/world_controller_reg.h new file mode 100644 index 0000000000..5304463d68 --- /dev/null +++ b/components/soc/esp32s3/include/soc/world_controller_reg.h @@ -0,0 +1,1317 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_WORLD_CONTROLLER_REG_H_ +#define _SOC_WORLD_CONTROLLER_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_1_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x0) +/* WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 1 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_2_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4) +/* WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 2 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_3_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x8) +/* WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 3 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_4_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xC) +/* WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 4 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_5_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x10) +/* WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 5 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_6_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x14) +/* WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 6 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_7_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x18) +/* WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 7 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_8_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x1C) +/* WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 8 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_9_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x20) +/* WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 9 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_10_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x24) +/* WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 10 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_11_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x28) +/* WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 11 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_12_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x2C) +/* WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 12 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_13_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x30) +/* WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_0 Entry 13 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_CHECK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x7C) +/* WORLD_CONTROLLER_CORE_0_ENTRY_CHECK : R/W ;bitpos:[13:1] ;default: 1'b1 ; */ +/*description: This filed is used to enable entry address check .*/ +#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK 0x00001FFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_M ((WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_S)) +#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_V 0x1FFF +#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_S 1 + +#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x100) +/* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: This field is used to set address that need to write when enter WORLD0.*/ +#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_MAX_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x104) +/* WORLD_CONTROLLER_CORE_0_MESSAGE_MAX : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: This filed is used to set the max value of clear write_buffer.*/ +#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX 0x0000000F +#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_S)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_V 0xF +#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x80) +/* WORLD_CONTROLLER_CORE_0_CURRENT_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 1 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_1 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_1_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_1_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_1_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 1.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 1 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x84) +/* WORLD_CONTROLLER_CORE_0_CURRENT_2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 2 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_2 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_2_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_2_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_2_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 2.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 2 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x88) +/* WORLD_CONTROLLER_CORE_0_CURRENT_3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 3 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_3 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_3_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_3_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_3_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 3.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 3 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE4_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x8C) +/* WORLD_CONTROLLER_CORE_0_CURRENT_4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 4 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_4 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_4_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_4_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_4_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 4.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 4 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE5_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x90) +/* WORLD_CONTROLLER_CORE_0_CURRENT_5 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 5 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_5 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_5_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_5_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_5_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 5.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_5 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 5 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE6_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x94) +/* WORLD_CONTROLLER_CORE_0_CURRENT_6 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 6 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_6 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_6_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_6_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_6_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 6.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_6 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 6 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE7_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x98) +/* WORLD_CONTROLLER_CORE_0_CURRENT_7 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 7 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_7 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_7_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_7_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_7_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 7.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_7 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 7 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE8_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x9C) +/* WORLD_CONTROLLER_CORE_0_CURRENT_8 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 8 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_8 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_8_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_8_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_8_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 8.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_8 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 8 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE9_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA0) +/* WORLD_CONTROLLER_CORE_0_CURRENT_9 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 9 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_9 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_9_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_9_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_9_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 9.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_9 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 9 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE10_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA4) +/* WORLD_CONTROLLER_CORE_0_CURRENT_10 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 10 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_10 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_10_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_10_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_10_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 10.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_10 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 10 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE11_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA8) +/* WORLD_CONTROLLER_CORE_0_CURRENT_11 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 11 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_11 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_11_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_11_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_11_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 11.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_11 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 11 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE12_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xAC) +/* WORLD_CONTROLLER_CORE_0_CURRENT_12 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 12 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_12 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_12_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_12_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_12_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 12.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_12 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 12 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE13_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xB0) +/* WORLD_CONTROLLER_CORE_0_CURRENT_13 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 13 .*/ +#define WORLD_CONTROLLER_CORE_0_CURRENT_13 (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_13_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_CURRENT_13_V 0x1 +#define WORLD_CONTROLLER_CORE_0_CURRENT_13_S 5 +/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 13.*/ +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13 0x0000000F +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_S)) +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_V 0xF +#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_S 1 +/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_13 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 13 .*/ +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13 (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_V 0x1 +#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xFC) +/* WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */ +/*description: This field is used to quickly read and rewrite the current field of all STATUSTA +BLE registers.For example,bit 1 represents the current field of STATUSTABLE1, bi +t2 represents the current field of STATUSTABLE2, and so on..*/ +#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT 0x00001FFF +#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_M ((WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S)) +#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V 0x1FFF +#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S 1 + +#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x108) +/* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: If this bit is 1, it means that is checking clear write_buffer operation, and is + checking address..*/ +#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE (BIT(6)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_M (BIT(6)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_V 0x1 +#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_S 6 +/* WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: If this bit is 1, it means that is checking clear write_buffer operation, and is + checking data..*/ +#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_V 0x1 +#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_S 5 +/* WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT : RO ;bitpos:[4:1] ;default: 4'b0 ; */ +/*description: This field indicates the data to be written next time.*/ +#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT 0x0000000F +#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_S)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_V 0xF +#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_S 1 +/* WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit indicates whether the check is successful.*/ +#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_V 0x1 +#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x140) +/* WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: This field is used to configure the entry address from WORLD0 to WORLD1, when th +e CPU executes to this address, switch to WORLD1.*/ +#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PREPARE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x144) +/* WORLD_CONTROLLER_CORE_0_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1.*/ +#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE 0x00000003 +#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_M ((WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S)) +#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V 0x3 +#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_UPDATE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x148) +/* WORLD_CONTROLLER_CORE_0_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: This field is used to update configuration completed, can write any value, the h +ardware only checks the write operation of this register and does not case about + its value.*/ +#define WORLD_CONTROLLER_CORE_0_UPDATE 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_UPDATE_M ((WORLD_CONTROLLER_CORE_0_UPDATE_V)<<(WORLD_CONTROLLER_CORE_0_UPDATE_S)) +#define WORLD_CONTROLLER_CORE_0_UPDATE_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_UPDATE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_CANCEL_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x14C) +/* WORLD_CONTROLLER_CORE_0_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: This field is used to cancel switch world configuration, if the trigger address +and update configuration complete, can use this register to cancel world switch. + can write any value, the hardware only checks the write operation of this regis +ter and does not case about its value.*/ +#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_M ((WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S)) +#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_IRAM0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x150) +/* WORLD_CONTROLLER_CORE_0_WORLD_IRAM0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: this field is used to read current world of Iram0 bus.*/ +#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0 0x00000003 +#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_M ((WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_S)) +#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_V 0x3 +#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x154) +/* WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: this field is used to read current world of Dram0 bus and PIF bus.*/ +#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF 0x00000003 +#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_M ((WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_S)) +#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_V 0x3 +#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x158) +/* WORLD_CONTROLLER_CORE_0_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit indicates whether is preparing to switch to WORLD1, 1 means value..*/ +#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_V 0x1 +#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x180) +/* WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: this field is used to set NMI mask, it can write any value, when write this regi +ster, the hardware start masking NMI interrupt.*/ +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S)) +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x184) +/* WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: this field to used to set trigger address, when CPU executes to this address, NM +I mask automatically fails.*/ +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S)) +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x188) +/* WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: this field is used to disable NMI mask, it will not take effect immediately, onl +y when the CPU executes to the trigger address will it start to cancel NMI mask.*/ +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S)) +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x18C) +/* WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: this field is used to cancel NMI mask disable function..*/ +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_S)) +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x190) +/* WORLD_CONTROLLER_CORE_0_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: this bit is used to mask NMI interrupt, it can directly mask NMI interrupt.*/ +#define WORLD_CONTROLLER_CORE_0_NMI_MASK (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_V 0x1 +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x194) +/* WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: this bit is used to indicates whether the NMI interrupt is being masked, 1 means + NMI interrupt is being masked,.*/ +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_V 0x1 +#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_1_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x400) +/* WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 1 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_2_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x404) +/* WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 2 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_3_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x408) +/* WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 3 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_4_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x40C) +/* WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 4 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_5_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x410) +/* WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 5 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_6_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x414) +/* WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 6 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_7_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x418) +/* WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 7 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_8_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x41C) +/* WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 8 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_9_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x420) +/* WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 9 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_10_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x424) +/* WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 10 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_11_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x428) +/* WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 11 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_12_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x42C) +/* WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 12 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_13_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x430) +/* WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ +/*description: Core_1 Entry 13 address from WORLD1 to WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_CHECK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x47C) +/* WORLD_CONTROLLER_CORE_1_ENTRY_CHECK : R/W ;bitpos:[13:1] ;default: 1'b1 ; */ +/*description: This filed is used to enable entry address check .*/ +#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK 0x00001FFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_M ((WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_S)) +#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_V 0x1FFF +#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_S 1 + +#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x500) +/* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: This field is used to set address that need to write when enter WORLD0.*/ +#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_MAX_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x504) +/* WORLD_CONTROLLER_CORE_1_MESSAGE_MAX : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: This filed is used to set the max value of clear write_buffer.*/ +#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX 0x0000000F +#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_S)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_V 0xF +#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x480) +/* WORLD_CONTROLLER_CORE_1_CURRENT_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 1 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_1 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_1_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_1_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_1_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 1.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 1 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x484) +/* WORLD_CONTROLLER_CORE_1_CURRENT_2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 2 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_2 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_2_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_2_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_2_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 2.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 2 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x488) +/* WORLD_CONTROLLER_CORE_1_CURRENT_3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 3 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_3 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_3_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_3_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_3_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 3.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 3 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE4_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x48C) +/* WORLD_CONTROLLER_CORE_1_CURRENT_4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 4 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_4 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_4_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_4_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_4_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 4.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 4 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE5_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x490) +/* WORLD_CONTROLLER_CORE_1_CURRENT_5 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 5 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_5 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_5_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_5_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_5_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 5.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_5 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 5 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE6_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x494) +/* WORLD_CONTROLLER_CORE_1_CURRENT_6 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 6 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_6 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_6_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_6_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_6_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 6.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_6 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 6 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE7_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x498) +/* WORLD_CONTROLLER_CORE_1_CURRENT_7 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 7 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_7 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_7_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_7_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_7_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 7.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_7 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 7 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE8_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x49C) +/* WORLD_CONTROLLER_CORE_1_CURRENT_8 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 8 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_8 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_8_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_8_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_8_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 8.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_8 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 8 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE9_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A0) +/* WORLD_CONTROLLER_CORE_1_CURRENT_9 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 9 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_9 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_9_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_9_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_9_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 9.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_9 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 9 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE10_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A4) +/* WORLD_CONTROLLER_CORE_1_CURRENT_10 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 10 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_10 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_10_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_10_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_10_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 10.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_10 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 10 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE11_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A8) +/* WORLD_CONTROLLER_CORE_1_CURRENT_11 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 11 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_11 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_11_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_11_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_11_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 11.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_11 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 11 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE12_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4AC) +/* WORLD_CONTROLLER_CORE_1_CURRENT_12 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 12 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_12 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_12_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_12_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_12_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 12.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_12 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 12 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE13_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4B0) +/* WORLD_CONTROLLER_CORE_1_CURRENT_13 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This bit is used to confirm whether the current state is in entry 13 .*/ +#define WORLD_CONTROLLER_CORE_1_CURRENT_13 (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_13_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_CURRENT_13_V 0x1 +#define WORLD_CONTROLLER_CORE_1_CURRENT_13_S 5 +/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ +/*description: This filed is used to confirm in which entry before enter entry 13.*/ +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13 0x0000000F +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_S)) +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_V 0xF +#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_S 1 +/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_13 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to confirm world before enter entry 13 .*/ +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13 (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_V 0x1 +#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4FC) +/* WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */ +/*description: This field is used to quickly read and rewrite the current field of all STATUSTA +BLE registers.For example,bit 1 represents the current field of STATUSTABLE1, bi +t2 represents the current field of STATUSTABLE2, and so on..*/ +#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT 0x00001FFF +#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_M ((WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S)) +#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V 0x1FFF +#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S 1 + +#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x508) +/* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: If this bit is 1, it means that is checking clear write_buffer operation, and is + checking address..*/ +#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE (BIT(6)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_M (BIT(6)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_V 0x1 +#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_S 6 +/* WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: If this bit is 1, it means that is checking clear write_buffer operation, and is + checking data..*/ +#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_M (BIT(5)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_V 0x1 +#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_S 5 +/* WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT : RO ;bitpos:[4:1] ;default: 4'b0 ; */ +/*description: This field indicates the data to be written next time.*/ +#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT 0x0000000F +#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_S)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_V 0xF +#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_S 1 +/* WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit indicates whether the check is successful.*/ +#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_V 0x1 +#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x540) +/* WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: This field is used to configure the entry address from WORLD0 to WORLD1, when th +e CPU executes to this address, switch to WORLD1.*/ +#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PREPARE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x544) +/* WORLD_CONTROLLER_CORE_1_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1.*/ +#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE 0x00000003 +#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_M ((WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S)) +#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V 0x3 +#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_UPDATE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x548) +/* WORLD_CONTROLLER_CORE_1_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: This field is used to update configuration completed, can write any value, the h +ardware only checks the write operation of this register and does not case about + its value.*/ +#define WORLD_CONTROLLER_CORE_1_UPDATE 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_UPDATE_M ((WORLD_CONTROLLER_CORE_1_UPDATE_V)<<(WORLD_CONTROLLER_CORE_1_UPDATE_S)) +#define WORLD_CONTROLLER_CORE_1_UPDATE_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_UPDATE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_CANCEL_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x54C) +/* WORLD_CONTROLLER_CORE_1_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: This field is used to cancel switch world configuration, if the trigger address +and update configuration complete, can use this register to cancel world switch. + can write any value, the hardware only checks the write operation of this regis +ter and does not case about its value.*/ +#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_M ((WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S)) +#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_IRAM0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x550) +/* WORLD_CONTROLLER_CORE_1_WORLD_IRAM0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: this field is used to read current world of Iram0 bus.*/ +#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0 0x00000003 +#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_M ((WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_S)) +#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_V 0x3 +#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x554) +/* WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: this field is used to read current world of Dram0 bus and PIF bus.*/ +#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF 0x00000003 +#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_M ((WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_S)) +#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_V 0x3 +#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x558) +/* WORLD_CONTROLLER_CORE_1_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit indicates whether is preparing to switch to WORLD1, 1 means value..*/ +#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_V 0x1 +#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x580) +/* WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: this field is used to set NMI mask, it can write any value, when write this regi +ster, the hardware start masking NMI interrupt.*/ +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S)) +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x584) +/* WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: this field to used to set trigger address, when CPU executes to this address, NM +I mask automatically fails.*/ +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S)) +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x588) +/* WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: this field is used to disable NMI mask, it will not take effect immediately, onl +y when the CPU executes to the trigger address will it start to cancel NMI mask.*/ +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S)) +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x58C) +/* WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: this field is used to cancel NMI mask disable function..*/ +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_S)) +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_V 0xFFFFFFFF +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x590) +/* WORLD_CONTROLLER_CORE_1_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: this bit is used to mask NMI interrupt, it can directly mask NMI interrupt.*/ +#define WORLD_CONTROLLER_CORE_1_NMI_MASK (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_V 0x1 +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_S 0 + +#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x594) +/* WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: this bit is used to indicates whether the NMI interrupt is being masked, 1 means + NMI interrupt is being masked,.*/ +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_M (BIT(0)) +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_V 0x1 +#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SPI2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x800) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_SPI2, 2'b01 means WORLD0, 2'b10 means WOR +LD1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SPI3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x804) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_SPI3, 2'b01 means WORLD0, 2'b10 means WOR +LD1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_UCHI0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x808) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_UCHI0, 2'b01 means WORLD0, 2'b10 means WO +RLD1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_I2S0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x80C) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_I2S0, 2'b01 means WORLD0, 2'b10 means WOR +LD1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_I2S1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x810) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_I2S1, 2'b01 means WORLD0, 2'b10 means WOR +LD1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_LCD_CAM_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x814) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_LCD_CAM, 2'b01 means WORLD0, 2'b10 means +WORLD1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_AES_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x818) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_AES, 2'b01 means WORLD0, 2'b10 means WORL +D1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SHA_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x81C) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_SHA, 2'b01 means WORLD0, 2'b10 means WORL +D1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_ADC_DAC_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x820) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_ADC_DAC, 2'b01 means WORLD0, 2'b10 means +WORLD1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_USB_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x824) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_USB, 2'b01 means WORLD0, 2'b10 means WORL +D1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SDIO_HOST_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x828) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_SDIO_HOST, 2'b01 means WORLD0, 2'b10 mean +s WORLD1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_MAC_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x82C) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_MAC, 2'b01 means WORLD0, 2'b10 means WORL +D1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SLC_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x830) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_SLC, 2'b01 means WORLD0, 2'b10 means WORL +D1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_S 0 + +#define WORLD_CONTROLLER_WCL_DMA_APBPERI_LC_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x834) +/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of DMA_LC, 2'b01 means WORLD0, 2'b10 means WORLD +1 .*/ +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC 0x00000003 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_M ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_S)) +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_V 0x3 +#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_SPI2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x900) +/* WORLD_CONTROLLER_WORLD_EDMA_SPI2 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_SPI2, 2'b01 means WORLD0, 2'b10 means WO +RLD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_SPI2 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_SPI2_M ((WORLD_CONTROLLER_WORLD_EDMA_SPI2_V)<<(WORLD_CONTROLLER_WORLD_EDMA_SPI2_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_SPI2_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_SPI2_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_SPI3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x904) +/* WORLD_CONTROLLER_WORLD_EDMA_SPI3 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_SPI3, 2'b01 means WORLD0, 2'b10 means WO +RLD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_SPI3 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_SPI3_M ((WORLD_CONTROLLER_WORLD_EDMA_SPI3_V)<<(WORLD_CONTROLLER_WORLD_EDMA_SPI3_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_SPI3_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_SPI3_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_UCHI0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x908) +/* WORLD_CONTROLLER_WORLD_EDMA_UCHI0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_UCHI0, 2'b01 means WORLD0, 2'b10 means W +ORLD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_UCHI0 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_UCHI0_M ((WORLD_CONTROLLER_WORLD_EDMA_UCHI0_V)<<(WORLD_CONTROLLER_WORLD_EDMA_UCHI0_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_UCHI0_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_UCHI0_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_I2S0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x90C) +/* WORLD_CONTROLLER_WORLD_EDMA_I2S0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_I2S0, 2'b01 means WORLD0, 2'b10 means WO +RLD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_I2S0 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_I2S0_M ((WORLD_CONTROLLER_WORLD_EDMA_I2S0_V)<<(WORLD_CONTROLLER_WORLD_EDMA_I2S0_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_I2S0_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_I2S0_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_I2S1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x910) +/* WORLD_CONTROLLER_WORLD_EDMA_I2S1 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_I2S1, 2'b01 means WORLD0, 2'b10 means WO +RLD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_I2S1 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_I2S1_M ((WORLD_CONTROLLER_WORLD_EDMA_I2S1_V)<<(WORLD_CONTROLLER_WORLD_EDMA_I2S1_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_I2S1_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_I2S1_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_LCD_CAM_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x914) +/* WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_LCD_CAM, 2'b01 means WORLD0, 2'b10 means + WORLD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_M ((WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_V)<<(WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_AES_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x918) +/* WORLD_CONTROLLER_WORLD_EDMA_AES : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_AES, 2'b01 means WORLD0, 2'b10 means WOR +LD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_AES 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_AES_M ((WORLD_CONTROLLER_WORLD_EDMA_AES_V)<<(WORLD_CONTROLLER_WORLD_EDMA_AES_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_AES_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_AES_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_SHA_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x91C) +/* WORLD_CONTROLLER_WORLD_EDMA_SHA : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_SHA, 2'b01 means WORLD0, 2'b10 means WOR +LD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_SHA 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_SHA_M ((WORLD_CONTROLLER_WORLD_EDMA_SHA_V)<<(WORLD_CONTROLLER_WORLD_EDMA_SHA_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_SHA_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_SHA_S 0 + +#define WORLD_CONTROLLER_WCL_EDMA_ADC_DAC_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x920) +/* WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This field is used to set world of EDMA_ADC_DAC, 2'b01 means WORLD0, 2'b10 means + WORLD1 .*/ +#define WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC 0x00000003 +#define WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_M ((WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_V)<<(WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_S)) +#define WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_V 0x3 +#define WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_WORLD_CONTROLLER_REG_H_ */