alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-15 06:26:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

global: rename esp32s2beta to esp32s2

Browse Source
This commit is contained in:
morris
2020-01-17 11:47:08 +08:00
parent 95743f4ee6
commit e30cd361a8
458 changed files with 660 additions and 1923 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
components/bootloader_support/src/bootloader_random.c
View File

@@ -22,7 +22,7 @@
#include "soc/i2s_periph.h"
#include "esp_log.h"
#include "soc/io_mux_reg.h"
#if CONFIG_IDF_TARGET_ESP32S2BETA
#if CONFIG_IDF_TARGET_ESP32S2
#include "soc/apb_saradc_reg.h"
#endif
@@ -62,7 +62,7 @@ void bootloader_fill_random(void *buffer, size_t length)
random ^= REG_READ(WDEV_RND_REG);
RSR(CCOUNT, now);
} while (now - start < 80 * 32 * 2); /* extra factor of 2 is precautionary */
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#elif CONFIG_IDF_TARGET_ESP32S2
// ToDo: Get random from register
random = 12345678;
#endif
@@ -101,7 +101,7 @@ void bootloader_random_enable(void)
#endif // BOOTLOADER_BUILD
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#elif CONFIG_IDF_TARGET_ESP32S2
/* Disable IO1 digital function for random function. */
PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U);
PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U);
@@ -126,7 +126,7 @@ void bootloader_random_enable(void)
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#elif CONFIG_IDF_TARGET_ESP32S2
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
@@ -145,7 +145,7 @@ void bootloader_random_enable(void)
CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL);
SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#elif CONFIG_IDF_TARGET_ESP32S2
SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 4, APB_SARADC_SAR_CLK_DIV_S);
SET_PERI_REG_BITS(APB_SARADC_FSM_REG, APB_SARADC_RSTB_WAIT, 8, APB_SARADC_RSTB_WAIT_S); /* was 1 */
SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 0, APB_SARADC_WORK_MODE_S);
@@ -184,7 +184,7 @@ void bootloader_random_disable(void)
#if CONFIG_IDF_TARGET_ESP32
CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#elif CONFIG_IDF_TARGET_ESP32S2
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
#endif
@@ -194,7 +194,7 @@ void bootloader_random_disable(void)
CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX
| SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#elif CONFIG_IDF_TARGET_ESP32S2
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL | APB_SARADC_DATA_TO_I2S);
SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);