mirror of
https://github.com/espressif/esp-idf.git
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global: rename esp32s2beta to esp32s2
This commit is contained in:
morris
391
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
Normal file
391
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
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@@ -0,0 +1,391 @@
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "bootloader_common.h"
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#include "soc/efuse_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/io_mux_reg.h"
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#include "esp32s2/rom/efuse.h"
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#include "esp32s2/rom/gpio.h"
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#include "esp32s2/rom/spi_flash.h"
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#include "bootloader_init.h"
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#include "bootloader_clock.h"
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#include "bootloader_flash_config.h"
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#include "esp32s2/rom/cache.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/rom/spi_flash.h"
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#include "esp32s2/rom/rtc.h"
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#include "esp32s2/rom/uart.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_image_format.h"
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#include "flash_qio_mode.h"
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#include "soc/assist_debug_reg.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/extmem_reg.h"
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#include "soc/rtc.h"
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#include "soc/spi_periph.h"
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#include <string.h>
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static const char *TAG = "boot.esp32s2";
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void bootloader_configure_spi_pins(int drv)
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{
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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uint8_t wp_pin = ets_efuse_get_wp_pad();
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uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
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uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
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uint8_t d_gpio_num = SPI_D_GPIO_NUM;
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uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
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uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
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uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
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if (spiconfig == 0) {
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} else {
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clk_gpio_num = spiconfig & 0x3f;
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q_gpio_num = (spiconfig >> 6) & 0x3f;
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d_gpio_num = (spiconfig >> 12) & 0x3f;
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cs0_gpio_num = (spiconfig >> 18) & 0x3f;
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hd_gpio_num = (spiconfig >> 24) & 0x3f;
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wp_gpio_num = wp_pin;
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}
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gpio_pad_set_drv(clk_gpio_num, drv);
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gpio_pad_set_drv(q_gpio_num, drv);
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gpio_pad_set_drv(d_gpio_num, drv);
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gpio_pad_set_drv(cs0_gpio_num, drv);
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if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
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gpio_pad_set_drv(hd_gpio_num, drv);
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}
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if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
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gpio_pad_set_drv(wp_gpio_num, drv);
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}
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}
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static void bootloader_reset_mmu(void)
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{
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//ToDo: save the autoload value
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Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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Cache_MMU_Init();
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/* normal ROM boot exits with DROM0 cache unmasked,
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but serial bootloader exits with it masked. */
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REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
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}
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static void update_flash_config(const esp_image_header_t *bootloader_hdr)
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{
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uint32_t size;
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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size = 2;
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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size = 8;
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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default:
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size = 2;
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}
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uint32_t autoload = Cache_Suspend_ICache();
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// Set flash chip size
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esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
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// TODO: set mode
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// TODO: set frequency
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Cache_Resume_ICache(autoload);
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}
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static void print_flash_info(const esp_image_header_t *bootloader_hdr)
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{
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ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
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ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
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ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
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ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
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ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
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const char *str;
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switch (bootloader_hdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_40M:
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str = "40MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_26M:
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str = "26.7MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_20M:
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str = "20MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_80M:
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str = "80MHz";
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break;
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default:
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str = "20MHz";
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break;
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}
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ESP_LOGI(TAG, "SPI Speed : %s", str);
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/* SPI mode could have been set to QIO during boot already,
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so test the SPI registers not the flash header */
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uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
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if (spi_ctrl & SPI_MEM_FREAD_QIO) {
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str = "QIO";
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} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
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str = "QOUT";
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} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
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str = "DIO";
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} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
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str = "DOUT";
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} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
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str = "FAST READ";
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} else {
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str = "SLOW READ";
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}
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ESP_LOGI(TAG, "SPI Mode : %s", str);
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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str = "1MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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str = "2MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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str = "4MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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str = "8MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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str = "16MB";
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break;
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default:
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str = "2MB";
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break;
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}
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ESP_LOGI(TAG, "SPI Flash Size : %s", str);
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}
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static void IRAM_ATTR bootloader_init_flash_configure(void)
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{
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bootloader_flash_dummy_config(&bootloader_image_hdr);
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bootloader_flash_cs_timing_config();
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}
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static esp_err_t bootloader_init_spi_flash(void)
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{
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bootloader_init_flash_configure();
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#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
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ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
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return ESP_FAIL;
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}
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#endif
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esp_rom_spiflash_unlock();
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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bootloader_enable_qio_mode();
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#endif
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print_flash_info(&bootloader_image_hdr);
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update_flash_config(&bootloader_image_hdr);
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return ESP_OK;
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}
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static void bootloader_init_uart_console(void)
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{
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#if CONFIG_ESP_CONSOLE_UART_NONE
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ets_install_putc1(NULL);
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ets_install_putc2(NULL);
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#else // CONFIG_ESP_CONSOLE_UART_NONE
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const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
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uartAttach(NULL);
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ets_install_uart_printf();
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// Wait for UART FIFO to be empty.
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uart_tx_wait_idle(0);
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#if CONFIG_ESP_CONSOLE_UART_CUSTOM
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// Some constants to make the following code less upper-case
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const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
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const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
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// Switch to the new UART (this just changes UART number used for
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// ets_printf in ROM code).
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uart_tx_switch(uart_num);
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// If console is attached to UART1 or if non-default pins are used,
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// need to reconfigure pins using GPIO matrix
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if (uart_num != 0 || uart_tx_gpio != 1 || uart_rx_gpio != 3) {
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// Change pin mode for GPIO1/3 from UART to GPIO
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_GPIO3);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_GPIO1);
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// Route GPIO signals to/from pins
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// (arrays should be optimized away by the compiler)
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const uint32_t tx_idx_list[3] = {U0TXD_OUT_IDX, U1TXD_OUT_IDX, U2TXD_OUT_IDX};
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const uint32_t rx_idx_list[3] = {U0RXD_IN_IDX, U1RXD_IN_IDX, U2RXD_IN_IDX};
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const uint32_t uart_reset[3] = {DPORT_UART_RST, DPORT_UART1_RST, DPORT_UART2_RST};
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const uint32_t tx_idx = tx_idx_list[uart_num];
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const uint32_t rx_idx = rx_idx_list[uart_num];
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[uart_rx_gpio]);
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gpio_pad_pullup(uart_rx_gpio);
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gpio_matrix_out(uart_tx_gpio, tx_idx, 0, 0);
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gpio_matrix_in(uart_rx_gpio, rx_idx, 0);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, uart_reset[uart_num]);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, uart_reset[uart_num]);
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}
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#endif // CONFIG_ESP_CONSOLE_UART_CUSTOM
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// Set configured UART console baud rate
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const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
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uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
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#endif // CONFIG_ESP_CONSOLE_UART_NONE
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}
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static void wdt_reset_cpu0_info_enable(void)
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{
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DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_ASSIST_DEBUG);
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DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_ASSIST_DEBUG);
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REG_WRITE(ASSIST_DEBUG_PRO_PDEBUGENABLE, 1);
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REG_WRITE(ASSIST_DEBUG_PRO_RCD_RECORDING, 1);
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}
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static void wdt_reset_info_dump(int cpu)
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{
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uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
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lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
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const char *cpu_name = cpu ? "APP" : "PRO";
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stat = 0xdeadbeef;
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pid = 0;
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inst = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGINST);
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dstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS);
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data = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGDATA);
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pc = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGPC);
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lsstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT);
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lsaddr = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR);
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lsdata = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA);
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if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
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DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
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ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x (waiti mode)", cpu_name, pc);
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} else {
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ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x", cpu_name, pc);
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}
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ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08x", cpu_name, stat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08x", cpu_name, pid);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08x", cpu_name, inst);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08x", cpu_name, dstat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08x", cpu_name, data);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08x", cpu_name, pc);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08x", cpu_name, lsstat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08x", cpu_name, lsaddr);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08x", cpu_name, lsdata);
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}
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static void bootloader_check_wdt_reset(void)
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{
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int wdt_rst = 0;
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RESET_REASON rst_reas[2];
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rst_reas[0] = rtc_get_reset_reason(0);
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if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
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rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (wdt_rst) {
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// if reset by WDT dump info from trace port
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wdt_reset_info_dump(0);
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}
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wdt_reset_cpu0_info_enable();
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}
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void abort(void)
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{
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#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
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ets_printf("abort() was called at PC 0x%08x\r\n", (intptr_t)__builtin_return_address(0) - 3);
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#endif
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if (esp_cpu_in_ocd_debug_mode()) {
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__asm__("break 0,0");
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}
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while (1) {
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}
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}
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static void bootloader_super_wdt_auto_feed(void)
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{
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REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
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}
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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bootloader_super_wdt_auto_feed();
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// protect memory region
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cpu_configure_region_protection();
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/* check that static RAM is after the stack */
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#ifndef NDEBUG
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{
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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}
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#endif
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// clear bss section
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bootloader_clear_bss_section();
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// reset MMU
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bootloader_reset_mmu();
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// config clock
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bootloader_clock_configure();
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// initialize uart console, from now on, we can use esp_log
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bootloader_init_uart_console();
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/* print 2nd bootloader banner */
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bootloader_print_banner();
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// update flash ID
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bootloader_flash_update_id();
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// read bootloader header
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if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
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goto err;
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}
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// read chip revision and check if it's compatible to bootloader
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if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
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goto err;
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}
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// initialize spi flash
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if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
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goto err;
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}
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// check whether a WDT reset happend
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bootloader_check_wdt_reset();
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// config WDT
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bootloader_config_wdt();
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// enable RNG early entropy source
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bootloader_enable_random();
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err:
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return ret;
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}
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