From 0856806db0dec2e50352e36295087597e5e14724 Mon Sep 17 00:00:00 2001 From: hebinglin Date: Mon, 29 Dec 2025 16:09:29 +0800 Subject: [PATCH] change(hal): add lpio oe and out inv ll apis --- .../esp32c5/include/hal/rtc_io_ll.h | 28 +++++++++++++++++++ .../esp32c61/include/hal/rtc_io_ll.h | 28 +++++++++++++++++++ .../esp32h4/include/hal/rtc_io_ll.h | 28 +++++++++++++++++++ 3 files changed, 84 insertions(+) diff --git a/components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h index 43bdc5fb9c..1666673132 100644 --- a/components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h @@ -443,6 +443,34 @@ static inline void rtcio_ll_clear_interrupt_status(void) LP_GPIO.status_w1tc.val = 0x7F; } +/** + * @brief Configure the source of output enable signal for the pad. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT-1. + * @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG + * @param oen_inv True if the output enable signal needs to be inverted, otherwise False. + */ +static inline void rtcio_ll_set_output_enable_ctrl(uint8_t rtcio_num, bool ctrl_by_periph, bool oen_inv) +{ + (void)ctrl_by_periph; // deterministic: + // When the IO is used as a simple LP GPIO output, oe signal can only be controlled by the oe register; + // When the IO connects to a peripheral signal through IOMUX, oe signal can only be controlled by the peripheral + LP_GPIO.funcn_out_sel_cfg[rtcio_num].funcn_oe_inv_sel = oen_inv; +} + +/** + * @brief Connect a peripheral signal which tagged as output attribute with a RTCIO. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT-1. + * @param signal_idx Peripheral signal index (tagged as output attribute). + * @param out_inv True if the output signal needs to be inverted, otherwise False. + */ +static inline void rtcio_ll_set_output_signal_matrix_source(uint8_t rtcio_num, uint32_t signal_idx, bool out_inv) +{ + (void)signal_idx; // no LP GPIO matrix on the target + LP_GPIO.funcn_out_sel_cfg[rtcio_num].funcn_out_inv_sel = out_inv; +} + #ifdef __cplusplus } #endif diff --git a/components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h index 196ddbab7b..d8da5115c7 100644 --- a/components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h @@ -442,6 +442,34 @@ static inline void rtcio_ll_clear_interrupt_status(void) LP_GPIO.status_w1tc.val = 0x7F; } +/** + * @brief Configure the source of output enable signal for the pad. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT-1. + * @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG + * @param oen_inv True if the output enable signal needs to be inverted, otherwise False. + */ +static inline void rtcio_ll_set_output_enable_ctrl(uint8_t rtcio_num, bool ctrl_by_periph, bool oen_inv) +{ + (void)ctrl_by_periph; // deterministic: + // When the IO is used as a simple LP GPIO output, oe signal can only be controlled by the oe register; + // When the IO connects to a peripheral signal through IOMUX, oe signal can only be controlled by the peripheral + LP_GPIO.funcn_out_sel_cfg[rtcio_num].funcn_oe_inv_sel = oen_inv; +} + +/** + * @brief Connect a peripheral signal which tagged as output attribute with a RTCIO. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT-1. + * @param signal_idx Peripheral signal index (tagged as output attribute). + * @param out_inv True if the output signal needs to be inverted, otherwise False. + */ +static inline void rtcio_ll_set_output_signal_matrix_source(uint8_t rtcio_num, uint32_t signal_idx, bool out_inv) +{ + (void)signal_idx; // no LP GPIO matrix on the target + LP_GPIO.funcn_out_sel_cfg[rtcio_num].funcn_out_inv_sel = out_inv; +} + #ifdef __cplusplus } #endif diff --git a/components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h index c05f6b3ea0..5e6034974b 100644 --- a/components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h +++ b/components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h @@ -442,6 +442,34 @@ static inline void rtcio_ll_clear_interrupt_status(void) LP_GPIO.status_w1tc.val = 0x3F; } +/** + * @brief Configure the source of output enable signal for the pad. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT-1. + * @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG + * @param oen_inv True if the output enable signal needs to be inverted, otherwise False. + */ +static inline void rtcio_ll_set_output_enable_ctrl(uint8_t rtcio_num, bool ctrl_by_periph, bool oen_inv) +{ + (void)ctrl_by_periph; // deterministic: + // When the IO is used as a simple LP GPIO output, oe signal can only be controlled by the oe register; + // When the IO connects to a peripheral signal through IOMUX, oe signal can only be controlled by the peripheral + LP_GPIO.funcn_out_sel_cfg[rtcio_num].funcn_oe_inv_sel = oen_inv; +} + +/** + * @brief Connect a peripheral signal which tagged as output attribute with a RTCIO. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT-1. + * @param signal_idx Peripheral signal index (tagged as output attribute). + * @param out_inv True if the output signal needs to be inverted, otherwise False. + */ +static inline void rtcio_ll_set_output_signal_matrix_source(uint8_t rtcio_num, uint32_t signal_idx, bool out_inv) +{ + (void)signal_idx; // no LP GPIO matrix on the target + LP_GPIO.funcn_out_sel_cfg[rtcio_num].funcn_out_inv_sel = out_inv; +} + #ifdef __cplusplus } #endif