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feat(esp-system): support reset reasons on P4

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This commit is contained in:
Marius Vikhammer
2023-08-30 18:12:42 +08:00
parent 1de2c44281
commit e58becec0a
10 changed files with 121 additions and 84 deletions
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4
components/esp_system/test_apps/esp_system_unity_tests/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

6
components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt
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@@ -8,8 +8,6 @@ set(requires "unity"
set(SRC "test_app_main.c"
"test_backtrace.c"
"test_delay.c"
"test_ipc_isr.c"
"test_ipc_isr.S"
"test_ipc.c"
"test_reset_reason.c"
"test_sleep.c"
@@ -17,6 +15,10 @@ set(SRC "test_app_main.c"
"test_system_time.c"
"test_task_wdt.c")
if(CONFIG_ESP_IPC_ISR_ENABLE)
list(APPEND SRC "test_ipc_isr.c" "test_ipc_isr.S")
endif()
idf_component_register(SRCS ${SRC}
PRIV_INCLUDE_DIRS .
PRIV_REQUIRES "${requires}"

42
components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
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@@ -36,6 +36,7 @@
#define BROWNOUT "SW_CPU_RESET"
#endif // CONFIG_ESP32_REV_MIN_FULL >= 300
#define STORE_ERROR "StoreProhibited"
#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define DEEPSLEEP "DSLEEP"
@@ -46,6 +47,7 @@
#define RTC_WDT "RTCWDT_RTC_RST"
#define BROWNOUT "BROWN_OUT_RST"
#define STORE_ERROR "StoreProhibited"
#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
#define DEEPSLEEP "DSLEEP"
@@ -56,6 +58,7 @@
#define RTC_WDT "RTCWDT_RTC_RST"
#define BROWNOUT "BROWNOUT_RST"
#define STORE_ERROR LOAD_STORE_ERROR
#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
#elif CONFIG_IDF_TARGET_ESP32C2
#define DEEPSLEEP "DSLEEP"
#define LOAD_STORE_ERROR "Store access fault"
@@ -65,6 +68,7 @@
#define RTC_WDT "RTCWDT_RTC_RST"
#define BROWNOUT "BROWNOUT_RST"
#define STORE_ERROR LOAD_STORE_ERROR
#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
#elif CONFIG_IDF_TARGET_ESP32C6
#define DEEPSLEEP "DSLEEP"
@@ -75,6 +79,18 @@
#define RTC_WDT "LP_WDT_SYS"
#define BROWNOUT "LP_BOD_SYS"
#define STORE_ERROR LOAD_STORE_ERROR
#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
#elif CONFIG_IDF_TARGET_ESP32P4
#define DEEPSLEEP "DSLEEP"
#define LOAD_STORE_ERROR "Store access fault"
#define RESET "SW_CPU_RESET"
#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0"
#define INT_WDT "HP_SYS_HP_WDT_RESET"
#define RTC_WDT "LP_WDT_SYS"
#define BROWNOUT "LP_BOD_SYS"
#define STORE_ERROR LOAD_STORE_ERROR
#define INT_WDT_HW_ESP_RST ESP_RST_WDT // On P4 there is only one reset reason for MWDT0/1
#endif // CONFIG_IDF_TARGET_ESP32
@@ -88,7 +104,6 @@ TEST_CASE("reset reason ESP_RST_POWERON", "[reset][ignore]")
}
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32H2)
static __NOINIT_ATTR uint32_t s_noinit_val;
#if CHECK_RTC_MEM
@@ -118,6 +133,8 @@ static void setup_values(void)
#endif //CHECK_RTC_MEM
}
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-7529
static void do_deep_sleep(void)
{
setup_values();
@@ -144,6 +161,8 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason][rese
do_deep_sleep,
check_reset_reason_deep_sleep);
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
static void do_exception(void)
{
setup_values();
@@ -232,6 +251,7 @@ static void do_int_wdt(void)
while(1);
}
static void do_int_wdt_hw(void)
{
setup_values();
@@ -240,10 +260,10 @@ static void do_int_wdt_hw(void)
#else
XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);
#endif
while(1);
while(1) { }
}
static void check_reset_reason_int_wdt(void)
static void check_reset_reason_int_wdt_sw(void)
{
TEST_ASSERT_EQUAL(ESP_RST_INT_WDT, esp_reset_reason());
#if CHECK_RTC_MEM
@@ -251,15 +271,23 @@ static void check_reset_reason_int_wdt(void)
#endif //CHECK_RTC_MEM
}
static void check_reset_reason_int_wdt_hw(void)
{
TEST_ASSERT_EQUAL(INT_WDT_HW_ESP_RST, esp_reset_reason());
#if CHECK_RTC_MEM
TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
#endif //CHECK_RTC_MEM
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (panic)",
"[reset_reason][reset="INT_WDT_PANIC","RESET"]",
do_int_wdt,
check_reset_reason_int_wdt);
check_reset_reason_int_wdt_sw);
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (hw)",
"[reset_reason][reset="INT_WDT"]",
do_int_wdt_hw,
check_reset_reason_int_wdt);
check_reset_reason_int_wdt_hw);
#if CONFIG_ESP_TASK_WDT_EN
static void do_task_wdt(void)
@@ -350,11 +378,10 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event",
do_brownout,
check_reset_reason_brownout);
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
#ifndef CONFIG_FREERTOS_UNICORE
#if CONFIG_IDF_TARGET_ARCH_XTENSA
#include "xt_instr_macros.h"
#include "xtensa/config/specreg.h"
@@ -434,6 +461,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after an exception in a ta
init_task_do_exception,
test2_finish);
#endif //CONFIG_IDF_TARGET_ARCH_XTENSA
#endif // CONFIG_FREERTOS_UNICORE
#endif // CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY

4
components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
View File

@@ -30,6 +30,8 @@
#include "nvs_flash.h"
#include "nvs.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-7529
#if SOC_PMU_SUPPORTED
#include "esp_private/esp_pmu.h"
#else
@@ -665,3 +667,5 @@ TEST_CASE("wake up using GPIO (2 or 4 low)", "[deepsleep][ignore]")
esp_deep_sleep_start();
}
#endif // SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4)