From e69eeb73555bfa7e08968cecddfe13c4bc9a8317 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Fri, 12 Sep 2025 16:45:58 +0800 Subject: [PATCH] feat(2ddma): ESP32P4 ECO5 2DDMA related updates Added one more pair of 2DDMA channels Priority bit width increased corespondingly Added three new CSC modes for RX channel 0 --- components/esp_hw_support/dma/dma2d.c | 23 +- components/esp_hw_support/dma/dma2d_priv.h | 4 +- .../test_apps/dma2d/main/test_dma2d.c | 2 +- .../port/soc/esp32p4/system_internal.c | 4 +- components/hal/esp32p4/include/hal/dma2d_ll.h | 184 +- components/hal/include/hal/dma2d_types.h | 9 +- components/soc/esp32p4/dma2d_periph.c | 2 + .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 +- components/soc/esp32p4/include/soc/soc_caps.h | 4 +- .../register/hw_ver1/soc/dma2d_struct.h | 45 +- .../register/hw_ver3/soc/dma2d_eco5_reg.h | 7537 ----------------- .../register/hw_ver3/soc/dma2d_eco5_struct.h | 2085 ----- .../esp32p4/register/hw_ver3/soc/dma2d_reg.h | 2128 ++++- .../register/hw_ver3/soc/dma2d_struct.h | 196 +- 14 files changed, 2227 insertions(+), 10000 deletions(-) delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h diff --git a/components/esp_hw_support/dma/dma2d.c b/components/esp_hw_support/dma/dma2d.c index 86666610a1..bc31ef81b0 100644 --- a/components/esp_hw_support/dma/dma2d.c +++ b/components/esp_hw_support/dma/dma2d.c @@ -23,7 +23,6 @@ #include "hal/dma2d_ll.h" #include "soc/dma2d_channel.h" #include "soc/dma2d_periph.h" -#include "soc/soc_caps.h" #include "esp_bit_defs.h" /** @@ -365,20 +364,20 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl _lock_acquire(&s_platform.mutex); if (!s_platform.groups[group_id]) { dma2d_group_t *pre_alloc_group = heap_caps_calloc(1, sizeof(dma2d_group_t), DMA2D_MEM_ALLOC_CAPS); - dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(SOC_DMA2D_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS); - dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(SOC_DMA2D_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS); + dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(DMA2D_LL_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS); + dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(DMA2D_LL_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS); if (pre_alloc_group && pre_alloc_tx_channels && pre_alloc_rx_channels) { pre_alloc_group->group_id = group_id; pre_alloc_group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; TAILQ_INIT(&pre_alloc_group->pending_trans_tailq); - pre_alloc_group->tx_channel_free_mask = (1 << SOC_DMA2D_TX_CHANNELS_PER_GROUP) - 1; - pre_alloc_group->rx_channel_free_mask = (1 << SOC_DMA2D_RX_CHANNELS_PER_GROUP) - 1; + pre_alloc_group->tx_channel_free_mask = (1 << DMA2D_LL_TX_CHANNELS_PER_GROUP) - 1; + pre_alloc_group->rx_channel_free_mask = (1 << DMA2D_LL_RX_CHANNELS_PER_GROUP) - 1; pre_alloc_group->tx_channel_reserved_mask = dma2d_tx_channel_reserved_mask[group_id]; pre_alloc_group->rx_channel_reserved_mask = dma2d_rx_channel_reserved_mask[group_id]; pre_alloc_group->tx_periph_m2m_free_id_mask = DMA2D_LL_TX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK; pre_alloc_group->rx_periph_m2m_free_id_mask = DMA2D_LL_RX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK; pre_alloc_group->intr_priority = -1; - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { pre_alloc_group->tx_chans[i] = &pre_alloc_tx_channels[i]; dma2d_tx_channel_t *tx_chan = pre_alloc_group->tx_chans[i]; tx_chan->base.group = pre_alloc_group; @@ -386,7 +385,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl tx_chan->base.direction = DMA2D_CHANNEL_DIRECTION_TX; tx_chan->base.spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; } - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { pre_alloc_group->rx_chans[i] = &pre_alloc_rx_channels[i]; dma2d_rx_channel_t *rx_chan = pre_alloc_group->rx_chans[i]; rx_chan->base.group = pre_alloc_group; @@ -435,7 +434,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl // Allocate TX and RX interrupts if (s_platform.groups[group_id]) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { dma2d_rx_channel_t *rx_chan = s_platform.groups[group_id]->rx_chans[i]; if (rx_chan->base.intr == NULL) { ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].rx_irq_id[i], @@ -450,7 +449,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl } } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { dma2d_tx_channel_t *tx_chan = s_platform.groups[group_id]->tx_chans[i]; if (tx_chan->base.intr == NULL) { ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].tx_irq_id[i], @@ -510,12 +509,12 @@ esp_err_t dma2d_release_pool(dma2d_pool_handle_t dma2d_pool) } if (do_deinitialize) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { if (dma2d_group->rx_chans[i]->base.intr) { esp_intr_free(dma2d_group->rx_chans[i]->base.intr); } } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { if (dma2d_group->tx_chans[i]->base.intr) { esp_intr_free(dma2d_group->tx_chans[i]->base.intr); } @@ -983,7 +982,7 @@ esp_err_t dma2d_force_end(dma2d_trans_t *trans, bool *need_yield) // Stop the RX channel and its bundled TX channels first dma2d_stop(&rx_chan->base); uint32_t tx_chans = rx_chan->bundled_tx_channel_mask; - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { if (tx_chans & (1 << i)) { dma2d_stop(&group->tx_chans[i]->base); } diff --git a/components/esp_hw_support/dma/dma2d_priv.h b/components/esp_hw_support/dma/dma2d_priv.h index dcf46bf328..074553c052 100644 --- a/components/esp_hw_support/dma/dma2d_priv.h +++ b/components/esp_hw_support/dma/dma2d_priv.h @@ -57,8 +57,8 @@ struct dma2d_group_t { uint8_t rx_channel_reserved_mask; // Bit mask indicating the being reserved RX channels uint32_t tx_periph_m2m_free_id_mask; // Bit mask indicating the available TX M2M peripheral selelction IDs at the moment uint32_t rx_periph_m2m_free_id_mask; // Bit mask indicating the available RX M2M peripheral selelction IDs at the moment - dma2d_tx_channel_t *tx_chans[SOC_DMA2D_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels - dma2d_rx_channel_t *rx_chans[SOC_DMA2D_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels + dma2d_tx_channel_t *tx_chans[DMA2D_LL_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels + dma2d_rx_channel_t *rx_chans[DMA2D_LL_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels int intr_priority; // All channels in the same group should share the same interrupt priority }; diff --git a/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c b/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c index 33a49d1a47..931688448e 100644 --- a/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c +++ b/components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c @@ -22,7 +22,7 @@ // This tests the hardware capability of multiple 2D-DMA transactions running together, and the driver capbility of // transactions being send to a queue, and waiting for free channels becoming available, and being picked to start the // real hardware operation. -#define M2M_TRANS_TIMES (8) +#define M2M_TRANS_TIMES (12) // Descriptor and buffer address and size should aligned to 64 bytes (the cacheline size alignment restriction) to be used by CPU diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index 3b9955a629..c624191484 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -53,11 +53,11 @@ void esp_system_reset_modules_on_exit(void) } } if (dma2d_ll_is_bus_clock_enabled(0)) { - for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) { dma2d_ll_rx_abort(DMA2D_LL_GET_HW(0), i, true); while (!dma2d_ll_rx_is_reset_avail(DMA2D_LL_GET_HW(0), i)); } - for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) { + for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) { dma2d_ll_tx_abort(DMA2D_LL_GET_HW(0), i, true); while (!dma2d_ll_tx_is_reset_avail(DMA2D_LL_GET_HW(0), i)); } diff --git a/components/hal/esp32p4/include/hal/dma2d_ll.h b/components/hal/esp32p4/include/hal/dma2d_ll.h index f36fcdd433..8c0fab8884 100644 --- a/components/hal/esp32p4/include/hal/dma2d_ll.h +++ b/components/hal/esp32p4/include/hal/dma2d_ll.h @@ -11,8 +11,10 @@ #include "hal/dma2d_types.h" #include "soc/dma2d_channel.h" #include "soc/dma2d_struct.h" +#include "soc/soc_caps.h" #include "hal/misc.h" #include "hal/assert.h" +#include "hal/config.h" #include "soc/soc.h" #include "soc/hp_sys_clkrst_struct.h" @@ -22,6 +24,14 @@ extern "C" { #define DMA2D_LL_GET_HW(id) (((id) == 0) ? (&DMA2D) : NULL) +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define DMA2D_LL_TX_CHANNELS_PER_GROUP SOC_DMA2D_TX_CHANNELS_PER_GROUP // Number of 2D-DMA TX (OUT) channels in each group +#define DMA2D_LL_RX_CHANNELS_PER_GROUP SOC_DMA2D_RX_CHANNELS_PER_GROUP // Number of 2D-DMA RX (IN) channels in each group +#else +#define DMA2D_LL_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group +#define DMA2D_LL_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group +#endif + // 2D-DMA interrupts #define DMA2D_LL_RX_EVENT_MASK (0x3FFF) #define DMA2D_LL_TX_EVENT_MASK (0x1FFF) @@ -57,8 +67,11 @@ extern "C" { // Bit masks that are used to indicate availability of some sub-features in the channels #define DMA2D_LL_TX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // TX channels that support reorder feature +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2 | BIT3) // TX channels that support color space conversion feature +#else #define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2) // TX channels that support color space conversion feature - +#endif #define DMA2D_LL_RX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // RX channels that support reorder feature #define DMA2D_LL_RX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0) // RX channels that support color space conversion feature @@ -158,16 +171,13 @@ static inline uint32_t dma2d_ll_get_scramble_order_sel(dma2d_scramble_order_t or } /////////////////////////////////////// RX /////////////////////////////////////////// -#define DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, ch, reg) ((volatile void*[]){&dev->in_channel0.reg, &dev->in_channel1.reg}[(ch)]) - /** * @brief Get 2D-DMA RX channel interrupt status word */ __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_int_st_chn_reg_t *reg = (volatile dma2d_in_int_st_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st); - return reg->val; + return dev->in_channel[channel].in_int_st.val & DMA2D_LL_RX_EVENT_MASK; } /** @@ -176,11 +186,10 @@ static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32 __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) { - volatile dma2d_in_int_ena_chn_reg_t *reg = (volatile dma2d_in_int_ena_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_ena); if (enable) { - reg->val = reg->val | (mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val | (mask & DMA2D_LL_RX_EVENT_MASK); } else { - reg->val = reg->val & ~(mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val & ~(mask & DMA2D_LL_RX_EVENT_MASK); } } @@ -190,8 +199,7 @@ static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t chann __attribute__((always_inline)) static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t channel, uint32_t mask) { - volatile dma2d_in_int_clr_chn_reg_t *reg = (volatile dma2d_in_int_clr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_clr); - reg->val = (mask & DMA2D_LL_RX_EVENT_MASK); + dev->in_channel[channel].in_int_clr.val = (mask & DMA2D_LL_RX_EVENT_MASK); } /** @@ -199,7 +207,7 @@ static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t */ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *dev, uint32_t channel) { - return (volatile void *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st); + return (volatile void *)(&dev->in_channel[channel].in_int_st); } /** @@ -208,8 +216,7 @@ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *d __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_check_owner_chn = enable; + dev->in_channel[channel].in_conf0.in_check_owner_chn = enable; } /** @@ -218,8 +225,7 @@ static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t cha __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_page_bound_en_chn = enable; + dev->in_channel[channel].in_conf0.in_page_bound_en_chn = enable; } /** @@ -249,8 +255,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t // Unsupported data burst length abort(); } - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_mem_burst_length_chn = sel; + dev->in_channel[channel].in_conf0.in_mem_burst_length_chn = sel; } /** @@ -259,8 +264,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->indscr_burst_en_chn = enable; + dev->in_channel[channel].in_conf0.indscr_burst_en_chn = enable; } /** @@ -269,9 +273,8 @@ static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_ __attribute__((always_inline)) static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_rst_chn = 1; - reg->in_rst_chn = 0; + dev->in_channel[channel].in_conf0.in_rst_chn = 1; + dev->in_channel[channel].in_conf0.in_rst_chn = 0; } /** @@ -280,8 +283,7 @@ static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state); - return reg->in_reset_avail_chn; + return dev->in_channel[channel].in_state.in_reset_avail_chn; } /** @@ -290,8 +292,7 @@ static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel __attribute__((always_inline)) static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool disable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_cmd_disable_chn = disable; + dev->in_channel[channel].in_conf0.in_cmd_disable_chn = disable; } /** @@ -300,8 +301,7 @@ static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool di __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_dscr_port(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_dscr_port_en_chn = enable; + dev->in_channel[channel].in_conf0.in_dscr_port_en_chn = enable; } /** @@ -328,8 +328,7 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c // Unsupported macro block size abort(); } - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_macro_block_size_chn = sel; + dev->in_channel[channel].in_conf0.in_macro_block_size_chn = sel; } /** @@ -338,9 +337,8 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_pop_chn_reg_t *reg = (volatile dma2d_in_pop_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_pop); - reg->infifo_pop_chn = 1; - return reg->infifo_rdata_chn; + dev->in_channel[channel].in_pop.infifo_pop_chn = 1; + return dev->in_channel[channel].in_pop.infifo_rdata_chn; } /** @@ -349,8 +347,7 @@ static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, uint32_t addr) { - volatile dma2d_in_link_addr_chn_reg_t *reg = (volatile dma2d_in_link_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_addr); - reg->inlink_addr_chn = addr; + dev->in_channel[channel].in_link_addr.inlink_addr_chn = addr; } /** @@ -359,8 +356,7 @@ static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, __attribute__((always_inline)) static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_start_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_start_chn = 1; } /** @@ -369,8 +365,7 @@ static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_stop_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_stop_chn = 1; } /** @@ -379,8 +374,7 @@ static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_restart_chn = 1; + dev->in_channel[channel].in_link_conf.inlink_restart_chn = 1; } /** @@ -389,8 +383,7 @@ static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t channel, int owner) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - reg->inlink_auto_ret_chn = owner; + dev->in_channel[channel].in_link_conf.inlink_auto_ret_chn = owner; } /** @@ -399,8 +392,7 @@ static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf); - return reg->inlink_park_chn; + return dev->in_channel[channel].in_link_conf.inlink_park_chn; } /** @@ -409,8 +401,7 @@ static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t chann __attribute__((always_inline)) static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state); - return (reg->in_state_chn == 0); + return (dev->in_channel[channel].in_state.in_state_chn == 0); } /** @@ -419,8 +410,7 @@ static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel) __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_suc_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_suc_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_suc_eof_des_addr); - return reg->val; + return dev->in_channel[channel].in_suc_eof_des_addr.val; } /** @@ -429,8 +419,7 @@ static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, u __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_err_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_err_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_err_eof_des_addr); - return reg->val; + return dev->in_channel[channel].in_err_eof_des_addr.val; } /** @@ -439,18 +428,7 @@ static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uin __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_prefetched_desc_addr(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_dscr_chn_reg_t *reg = (volatile dma2d_in_dscr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_dscr); - return reg->val; -} - -/** - * @brief Set priority for 2D-DMA RX channel - */ -__attribute__((always_inline)) -static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio) -{ - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_priority_chn = prio; + return dev->in_channel[channel].in_dscr.val; } /** @@ -459,10 +437,8 @@ static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, __attribute__((always_inline)) static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t channel, dma2d_trigger_peripheral_t periph, int periph_id) { - volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel); - peri_sel_reg->in_peri_sel_chn = periph_id; - volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - conf0_reg->in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M); + dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = periph_id; + dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M); } /** @@ -471,10 +447,8 @@ static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t chan __attribute__((always_inline)) static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel); - peri_sel_reg->in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE; - volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - conf0_reg->in_mem_trans_en_chn = false; + dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE; + dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = false; } // REORDER FUNCTION (Only CH0 supports this feature) @@ -485,8 +459,7 @@ static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t __attribute__((always_inline)) static inline void dma2d_ll_rx_enable_reorder(dma2d_dev_t *dev, uint32_t channel, bool enable) { - volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0); - reg->in_reorder_en_chn = enable; + dev->in_channel[channel].in_conf0.in_reorder_en_chn = enable; } // COLOR SPACE CONVERSION FUNCTION @@ -524,6 +497,17 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint proc_en = false; output_sel = 1; break; + case DMA2D_CSC_RX_YUV444_TO_YUV422: + input_sel = 0; + proc_en = false; + output_sel = 2; + break; + case DMA2D_CSC_RX_YUV444_TO_YUV420: + case DMA2D_CSC_RX_YUV422_TO_YUV420: + input_sel = 0; + proc_en = false; + output_sel = 3; + break; case DMA2D_CSC_RX_YUV420_TO_RGB888_601: case DMA2D_CSC_RX_YUV422_TO_RGB888_601: input_sel = 0; @@ -581,13 +565,13 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint abort(); } - dev->in_channel0.in_color_convert.in_color_input_sel_chn = input_sel; - dev->in_channel0.in_color_convert.in_color_3b_proc_en_chn = proc_en; - dev->in_channel0.in_color_convert.in_color_output_sel_chn = output_sel; + dev->in_channel[channel].in_color_convert.in_color_input_sel_chn = input_sel; + dev->in_channel[channel].in_color_convert.in_color_3b_proc_en_chn = proc_en; + dev->in_channel[channel].in_color_convert.in_color_output_sel_chn = output_sel; if (proc_en) { HAL_ASSERT(table); - typeof(dev->in_channel0.in_color_param_group) color_param_group; + typeof(dev->in_channel[channel].in_color_param_group) color_param_group; color_param_group.param_h.a = table[0][0]; color_param_group.param_h.b = table[0][1]; @@ -604,12 +588,12 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint color_param_group.param_l.c = table[2][2]; color_param_group.param_l.d = table[2][3]; - dev->in_channel0.in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0]; - dev->in_channel0.in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1]; - dev->in_channel0.in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0]; - dev->in_channel0.in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1]; - dev->in_channel0.in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0]; - dev->in_channel0.in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1]; + dev->in_channel[channel].in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0]; + dev->in_channel[channel].in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1]; + dev->in_channel[channel].in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0]; + dev->in_channel[channel].in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1]; + dev->in_channel[channel].in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0]; + dev->in_channel[channel].in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1]; } } @@ -620,7 +604,7 @@ __attribute__((always_inline)) static inline void dma2d_ll_rx_set_csc_pre_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order) { HAL_ASSERT(channel == 0); // Only channel 0 supports scramble - dev->in_channel0.in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order); + dev->in_channel[channel].in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order); } /** @@ -630,7 +614,7 @@ __attribute__((always_inline)) static inline void dma2d_ll_rx_set_csc_post_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order) { HAL_ASSERT(channel == 0); // Only channel 0 supports scramble - dev->in_channel0.in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order); + dev->in_channel[channel].in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order); } // Arbiter @@ -659,8 +643,7 @@ static inline void dma2d_ll_rx_set_arb_timeout(dma2d_dev_t *dev, uint32_t timeou __attribute__((always_inline)) static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t channel, uint32_t token_num) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_token_num_chn = token_num; + dev->in_channel[channel].in_arb.in_arb_token_num_chn = token_num; } /** @@ -669,20 +652,22 @@ static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t chan __attribute__((always_inline)) static inline uint32_t dma2d_ll_rx_get_arb_token_num(dma2d_dev_t *dev, uint32_t channel) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - return reg->in_arb_token_num_chn; + return dev->in_channel[channel].in_arb.in_arb_token_num_chn; } /** - * @brief Set 2D-DMA RX channel arbiter priority + * @brief Set priority for 2D-DMA RX channel */ __attribute__((always_inline)) -static inline void dma2d_ll_rx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) +static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) { - volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb); - reg->in_arb_priority_chn = priority; + dev->in_channel[channel].in_arb.in_arb_priority_chn = priority; } +// ETM + +// note that in_ch1 in_etm_conf register addr is different before and after rev3 chip! + /////////////////////////////////////// TX /////////////////////////////////////////// /** * @brief Get 2D-DMA TX channel interrupt status word @@ -954,15 +939,6 @@ static inline uint32_t dma2d_ll_tx_get_prefetched_desc_addr(dma2d_dev_t *dev, ui return dev->out_channel[channel].out_dscr.val; } -/** - * @brief Set priority for 2D-DMA TX channel - */ -__attribute__((always_inline)) -static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio) -{ - dev->out_channel[channel].out_arb.out_arb_priority_chn = prio; -} - /** * @brief Connect 2D-DMA TX channel to a given peripheral */ @@ -1165,10 +1141,10 @@ static inline uint32_t dma2d_ll_tx_get_arb_token_num(dma2d_dev_t *dev, uint32_t } /** - * @brief Set 2D-DMA TX channel arbiter priority + * @brief Set priority for 2D-DMA TX channel */ __attribute__((always_inline)) -static inline void dma2d_ll_tx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) +static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority) { dev->out_channel[channel].out_arb.out_arb_priority_chn = priority; } diff --git a/components/hal/include/hal/dma2d_types.h b/components/hal/include/hal/dma2d_types.h index b66c791deb..82b2e64107 100644 --- a/components/hal/include/hal/dma2d_types.h +++ b/components/hal/include/hal/dma2d_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -236,8 +236,9 @@ typedef enum { typedef enum { DMA2D_CSC_RX_NONE, /*!< 2D-DMA RX perform no CSC */ DMA2D_CSC_RX_SCRAMBLE, /*!< 2D-DMA RX perform only data scramble */ - DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422 to YUV444 conversion */ - DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420 to YUV444 conversion */ + DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422 to YUV444-MIPI conversion */ + DMA2D_CSC_RX_YUV422_TO_YUV420, /*!< 2D-DMA RX perform YUV422 to YUV420-MIPI conversion */ + DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420 to YUV444-MIPI conversion */ DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT601 standard) */ DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT601 standard) */ DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT709 standard) */ @@ -246,6 +247,8 @@ typedef enum { DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT601 standard) */ DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT709 standard) */ DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV444_TO_YUV422, /*!< 2D-DMA RX perform YUV444 to YUV422-MIPI conversion */ + DMA2D_CSC_RX_YUV444_TO_YUV420, /*!< 2D-DMA RX perform YUV444 to YUV420-MIPI conversion */ DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT601 standard) */ DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT601 standard) */ DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT709 standard) */ diff --git a/components/soc/esp32p4/dma2d_periph.c b/components/soc/esp32p4/dma2d_periph.c index e7043df942..7cd670382a 100644 --- a/components/soc/esp32p4/dma2d_periph.c +++ b/components/soc/esp32p4/dma2d_periph.c @@ -14,10 +14,12 @@ const dma2d_signal_conn_t dma2d_periph_signals = { [0] = ETS_DMA2D_OUT_CH0_INTR_SOURCE, [1] = ETS_DMA2D_OUT_CH1_INTR_SOURCE, [2] = ETS_DMA2D_OUT_CH2_INTR_SOURCE, + [3] = ETS_DMA2D_OUT_CH3_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0 }, .rx_irq_id = { [0] = ETS_DMA2D_IN_CH0_INTR_SOURCE, [1] = ETS_DMA2D_IN_CH1_INTR_SOURCE, + [2] = ETS_DMA2D_IN_CH2_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0 } } } diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 86bd4b005d..50a46199dc 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -629,11 +629,11 @@ config SOC_DMA2D_GROUPS config SOC_DMA2D_TX_CHANNELS_PER_GROUP int - default 3 + default 4 config SOC_DMA2D_RX_CHANNELS_PER_GROUP int - default 2 + default 3 config SOC_ETM_GROUPS int diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index cd17bcd502..91e6e23ae5 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -225,8 +225,8 @@ /*-------------------------- 2D-DMA CAPS -------------------------------------*/ #define SOC_DMA2D_GROUPS (1U) // Number of 2D-DMA groups -#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group -#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group +#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (4) // Number of 2D-DMA TX (OUT) channels in each group (4th channel only exists on P4 ver. >= 3.0) +#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA RX (IN) channels in each group (3rd channel only exists on P4 ver. >= 3.0) // #define SOC_DMA2D_SUPPORT_ETM (1) // Support ETM submodule /*-------------------------- ETM CAPS --------------------------------------*/ diff --git a/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h index b3f91e92b3..a63f6d64ff 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1763,42 +1763,21 @@ typedef struct { volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; volatile dma2d_in_arb_chn_reg_t in_arb; volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert; - volatile dma2d_in_scramble_chn_reg_t in_scramble; - volatile dma2d_color_param_group_chn_reg_t in_color_param_group; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_570[36]; -} dma2d_in_ch0_reg_t; - -typedef struct { - volatile dma2d_in_conf0_chn_reg_t in_conf0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena; - volatile dma2d_in_int_st_chn_reg_t in_int_st; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr; - volatile dma2d_infifo_status_chn_reg_t infifo_status; - volatile dma2d_in_pop_chn_reg_t in_pop; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr; - volatile dma2d_in_state_chn_reg_t in_state; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; - volatile dma2d_in_dscr_chn_reg_t in_dscr; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; - volatile dma2d_in_arb_chn_reg_t in_arb; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_64c[45]; -} dma2d_in_ch1_reg_t; + union { + volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */ + volatile dma2d_in_etm_conf_chn_reg_t in1_etm_conf; /* specific for channel1 */ + }; + volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */ + volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */ + volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */ + volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; /* On ver. less than 3.0, channel 1 in_etm_conf register is at the in_ro_pd_conf addr. Here is to only be compatible with new ECOs. Workaround should be done in LL layer. */ + uint32_t reserved_in[36]; +} dma2d_in_chn_reg_t; typedef struct dma2d_dev_t { volatile dma2d_out_chn_reg_t out_channel[3]; uint32_t reserved_300[128]; - volatile dma2d_in_ch0_reg_t in_channel0; - volatile dma2d_in_ch1_reg_t in_channel1; + volatile dma2d_in_chn_reg_t in_channel[2]; uint32_t reserved_700[192]; volatile dma2d_axi_err_reg_t axi_err; volatile dma2d_rst_conf_reg_t rst_conf; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h deleted file mode 100644 index 3077ad0e45..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h +++ /dev/null @@ -1,7537 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** DMA2D_OUT_CONF0_CH0_REG register - * Configures the tx direction of channel 0 - */ -#define DMA2D_OUT_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x0) -/** DMA2D_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH0 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH0_M (DMA2D_OUT_AUTO_WRBACK_CH0_V << DMA2D_OUT_AUTO_WRBACK_CH0_S) -#define DMA2D_OUT_AUTO_WRBACK_CH0_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH0_S 0 -/** DMA2D_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH0 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH0_M (DMA2D_OUT_EOF_MODE_CH0_V << DMA2D_OUT_EOF_MODE_CH0_S) -#define DMA2D_OUT_EOF_MODE_CH0_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH0_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH0_M (DMA2D_OUTDSCR_BURST_EN_CH0_V << DMA2D_OUTDSCR_BURST_EN_CH0_S) -#define DMA2D_OUTDSCR_BURST_EN_CH0_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH0_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH0 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH0_M (DMA2D_OUT_ECC_AES_EN_CH0_V << DMA2D_OUT_ECC_AES_EN_CH0_S) -#define DMA2D_OUT_ECC_AES_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH0_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH0 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH0_M (DMA2D_OUT_CHECK_OWNER_CH0_V << DMA2D_OUT_CHECK_OWNER_CH0_S) -#define DMA2D_OUT_CHECK_OWNER_CH0_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH0_S 4 -/** DMA2D_OUT_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH0 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH0_M (DMA2D_OUT_LOOP_TEST_CH0_V << DMA2D_OUT_LOOP_TEST_CH0_S) -#define DMA2D_OUT_LOOP_TEST_CH0_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH0_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_M (DMA2D_OUT_MEM_BURST_LENGTH_CH0_V << DMA2D_OUT_MEM_BURST_LENGTH_CH0_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH0 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH0_M (DMA2D_OUT_DSCR_PORT_EN_CH0_V << DMA2D_OUT_DSCR_PORT_EN_CH0_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH0_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH0_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH0 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_M (DMA2D_OUT_PAGE_BOUND_EN_CH0_V << DMA2D_OUT_PAGE_BOUND_EN_CH0_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH0_S 12 -/** DMA2D_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH0 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH0_M (DMA2D_OUT_REORDER_EN_CH0_V << DMA2D_OUT_REORDER_EN_CH0_S) -#define DMA2D_OUT_REORDER_EN_CH0_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH0_S 16 -/** DMA2D_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH0 (BIT(24)) -#define DMA2D_OUT_RST_CH0_M (DMA2D_OUT_RST_CH0_V << DMA2D_OUT_RST_CH0_S) -#define DMA2D_OUT_RST_CH0_V 0x00000001U -#define DMA2D_OUT_RST_CH0_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH0 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH0_M (DMA2D_OUT_CMD_DISABLE_CH0_V << DMA2D_OUT_CMD_DISABLE_CH0_S) -#define DMA2D_OUT_CMD_DISABLE_CH0_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH0_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S 26 - -/** DMA2D_OUT_INT_RAW_CH0_REG register - * Raw interrupt status of TX channel 0 - */ -#define DMA2D_OUT_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x4) -/** DMA2D_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH0_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_RAW_M (DMA2D_OUT_DONE_CH0_INT_RAW_V << DMA2D_OUT_DONE_CH0_INT_RAW_S) -#define DMA2D_OUT_DONE_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH0_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_RAW_M (DMA2D_OUT_EOF_CH0_INT_RAW_V << DMA2D_OUT_EOF_CH0_INT_RAW_S) -#define DMA2D_OUT_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH0_REG register - * Interrupt enable bits of TX channel 0 - */ -#define DMA2D_OUT_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x8) -/** DMA2D_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_ENA_M (DMA2D_OUT_DONE_CH0_INT_ENA_V << DMA2D_OUT_DONE_CH0_INT_ENA_S) -#define DMA2D_OUT_DONE_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_ENA_M (DMA2D_OUT_EOF_CH0_INT_ENA_V << DMA2D_OUT_EOF_CH0_INT_ENA_S) -#define DMA2D_OUT_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH0_REG register - * Masked interrupt status of TX channel 0 - */ -#define DMA2D_OUT_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0xc) -/** DMA2D_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_ST_M (DMA2D_OUT_DONE_CH0_INT_ST_V << DMA2D_OUT_DONE_CH0_INT_ST_S) -#define DMA2D_OUT_DONE_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_ST_M (DMA2D_OUT_EOF_CH0_INT_ST_V << DMA2D_OUT_EOF_CH0_INT_ST_S) -#define DMA2D_OUT_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH0_REG register - * Interrupt clear bits of TX channel 0 - */ -#define DMA2D_OUT_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x10) -/** DMA2D_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH0_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH0_INT_CLR_M (DMA2D_OUT_DONE_CH0_INT_CLR_V << DMA2D_OUT_DONE_CH0_INT_CLR_S) -#define DMA2D_OUT_DONE_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH0_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH0_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH0_INT_CLR_M (DMA2D_OUT_EOF_CH0_INT_CLR_V << DMA2D_OUT_EOF_CH0_INT_CLR_S) -#define DMA2D_OUT_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH0_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH0_REG register - * Represents the status of the tx fifo of channel 0 - */ -#define DMA2D_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x14) -/** DMA2D_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH0 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH0_M (DMA2D_OUTFIFO_FULL_L2_CH0_V << DMA2D_OUTFIFO_FULL_L2_CH0_S) -#define DMA2D_OUTFIFO_FULL_L2_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH0_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH0 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_M (DMA2D_OUTFIFO_EMPTY_L2_CH0_V << DMA2D_OUTFIFO_EMPTY_L2_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH0_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH0 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH0_M (DMA2D_OUTFIFO_CNT_L2_CH0_V << DMA2D_OUTFIFO_CNT_L2_CH0_S) -#define DMA2D_OUTFIFO_CNT_L2_CH0_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH0_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_M (DMA2D_OUT_REMAIN_UNDER_1B_CH0_V << DMA2D_OUT_REMAIN_UNDER_1B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_M (DMA2D_OUT_REMAIN_UNDER_2B_CH0_V << DMA2D_OUT_REMAIN_UNDER_2B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_M (DMA2D_OUT_REMAIN_UNDER_3B_CH0_V << DMA2D_OUT_REMAIN_UNDER_3B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_M (DMA2D_OUT_REMAIN_UNDER_4B_CH0_V << DMA2D_OUT_REMAIN_UNDER_4B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_M (DMA2D_OUT_REMAIN_UNDER_5B_CH0_V << DMA2D_OUT_REMAIN_UNDER_5B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_M (DMA2D_OUT_REMAIN_UNDER_6B_CH0_V << DMA2D_OUT_REMAIN_UNDER_6B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_M (DMA2D_OUT_REMAIN_UNDER_7B_CH0_V << DMA2D_OUT_REMAIN_UNDER_7B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_M (DMA2D_OUT_REMAIN_UNDER_8B_CH0_V << DMA2D_OUT_REMAIN_UNDER_8B_CH0_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH0 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH0_M (DMA2D_OUTFIFO_FULL_L1_CH0_V << DMA2D_OUTFIFO_FULL_L1_CH0_S) -#define DMA2D_OUTFIFO_FULL_L1_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH0_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH0 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_M (DMA2D_OUTFIFO_EMPTY_L1_CH0_V << DMA2D_OUTFIFO_EMPTY_L1_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH0_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH0 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH0_M (DMA2D_OUTFIFO_CNT_L1_CH0_V << DMA2D_OUTFIFO_CNT_L1_CH0_S) -#define DMA2D_OUTFIFO_CNT_L1_CH0_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH0_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH0 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH0_M (DMA2D_OUTFIFO_FULL_L3_CH0_V << DMA2D_OUTFIFO_FULL_L3_CH0_S) -#define DMA2D_OUTFIFO_FULL_L3_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH0_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH0 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_M (DMA2D_OUTFIFO_EMPTY_L3_CH0_V << DMA2D_OUTFIFO_EMPTY_L3_CH0_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH0_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH0 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH0_M (DMA2D_OUTFIFO_CNT_L3_CH0_V << DMA2D_OUTFIFO_CNT_L3_CH0_S) -#define DMA2D_OUTFIFO_CNT_L3_CH0_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH0_S 24 - -/** DMA2D_OUT_PUSH_CH0_REG register - * Configures the tx fifo of channel 0 - */ -#define DMA2D_OUT_PUSH_CH0_REG (DR_REG_DMA2D_BASE + 0x18) -/** DMA2D_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH0 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH0_M (DMA2D_OUTFIFO_WDATA_CH0_V << DMA2D_OUTFIFO_WDATA_CH0_S) -#define DMA2D_OUTFIFO_WDATA_CH0_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH0_S 0 -/** DMA2D_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH0 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH0_M (DMA2D_OUTFIFO_PUSH_CH0_V << DMA2D_OUTFIFO_PUSH_CH0_S) -#define DMA2D_OUTFIFO_PUSH_CH0_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH0_S 10 - -/** DMA2D_OUT_LINK_CONF_CH0_REG register - * Configures the tx descriptor operations of channel 0 - */ -#define DMA2D_OUT_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x1c) -/** DMA2D_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH0 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH0_M (DMA2D_OUTLINK_STOP_CH0_V << DMA2D_OUTLINK_STOP_CH0_S) -#define DMA2D_OUTLINK_STOP_CH0_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH0_S 20 -/** DMA2D_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH0 (BIT(21)) -#define DMA2D_OUTLINK_START_CH0_M (DMA2D_OUTLINK_START_CH0_V << DMA2D_OUTLINK_START_CH0_S) -#define DMA2D_OUTLINK_START_CH0_V 0x00000001U -#define DMA2D_OUTLINK_START_CH0_S 21 -/** DMA2D_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH0 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH0_M (DMA2D_OUTLINK_RESTART_CH0_V << DMA2D_OUTLINK_RESTART_CH0_S) -#define DMA2D_OUTLINK_RESTART_CH0_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH0_S 22 -/** DMA2D_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH0 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH0_M (DMA2D_OUTLINK_PARK_CH0_V << DMA2D_OUTLINK_PARK_CH0_S) -#define DMA2D_OUTLINK_PARK_CH0_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH0_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH0_REG register - * Configures the tx descriptor address of channel 0 - */ -#define DMA2D_OUT_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x20) -/** DMA2D_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH0_M (DMA2D_OUTLINK_ADDR_CH0_V << DMA2D_OUTLINK_ADDR_CH0_S) -#define DMA2D_OUTLINK_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH0_S 0 - -/** DMA2D_OUT_STATE_CH0_REG register - * Represents the working status of the tx descriptor of channel 0 - */ -#define DMA2D_OUT_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x24) -/** DMA2D_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_M (DMA2D_OUTLINK_DSCR_ADDR_CH0_V << DMA2D_OUTLINK_DSCR_ADDR_CH0_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH0_S 0 -/** DMA2D_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH0 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH0_M (DMA2D_OUT_DSCR_STATE_CH0_V << DMA2D_OUT_DSCR_STATE_CH0_S) -#define DMA2D_OUT_DSCR_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH0_S 18 -/** DMA2D_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH0 0x0000000FU -#define DMA2D_OUT_STATE_CH0_M (DMA2D_OUT_STATE_CH0_V << DMA2D_OUT_STATE_CH0_S) -#define DMA2D_OUT_STATE_CH0_V 0x0000000FU -#define DMA2D_OUT_STATE_CH0_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH0 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH0_M (DMA2D_OUT_RESET_AVAIL_CH0_V << DMA2D_OUT_RESET_AVAIL_CH0_S) -#define DMA2D_OUT_RESET_AVAIL_CH0_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH0_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x28) -/** DMA2D_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH0_M (DMA2D_OUT_EOF_DES_ADDR_CH0_V << DMA2D_OUT_EOF_DES_ADDR_CH0_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_OUT_DSCR_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x2c) -/** DMA2D_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH0_M (DMA2D_OUTLINK_DSCR_CH0_V << DMA2D_OUTLINK_DSCR_CH0_S) -#define DMA2D_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH0_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x30) -/** DMA2D_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH0_M (DMA2D_OUTLINK_DSCR_BF0_CH0_V << DMA2D_OUTLINK_DSCR_BF0_CH0_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH0_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH0_REG register - * Represents the address associated with the outlink descriptor of channel 0 - */ -#define DMA2D_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x34) -/** DMA2D_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH0_M (DMA2D_OUTLINK_DSCR_BF1_CH0_V << DMA2D_OUTLINK_DSCR_BF1_CH0_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH0_S 0 - -/** DMA2D_OUT_PERI_SEL_CH0_REG register - * Configures the tx peripheral of channel 0 - */ -#define DMA2D_OUT_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x38) -/** DMA2D_OUT_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH0 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH0_M (DMA2D_OUT_PERI_SEL_CH0_V << DMA2D_OUT_PERI_SEL_CH0_S) -#define DMA2D_OUT_PERI_SEL_CH0_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH0_S 0 - -/** DMA2D_OUT_ARB_CH0_REG register - * Configures the tx arbiter of channel 0 - */ -#define DMA2D_OUT_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x3c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH0 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH0_M (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH0_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH0 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_M (DMA2D_OUT_ARB_PRIORITY_H_CH0_V << DMA2D_OUT_ARB_PRIORITY_H_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH0_S 6 - -/** DMA2D_OUT_RO_STATUS_CH0_REG register - * Represents the status of the tx reorder module of channel 0 - */ -#define DMA2D_OUT_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x40) -/** DMA2D_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH0 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH0_M (DMA2D_OUTFIFO_RO_CNT_CH0_V << DMA2D_OUTFIFO_RO_CNT_CH0_S) -#define DMA2D_OUTFIFO_RO_CNT_CH0_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH0_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH0 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH0_M (DMA2D_OUT_RO_WR_STATE_CH0_V << DMA2D_OUT_RO_WR_STATE_CH0_S) -#define DMA2D_OUT_RO_WR_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH0_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH0 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH0_M (DMA2D_OUT_RO_RD_STATE_CH0_V << DMA2D_OUT_RO_RD_STATE_CH0_S) -#define DMA2D_OUT_RO_RD_STATE_CH0_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH0_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH0 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH0_M (DMA2D_OUT_PIXEL_BYTE_CH0_V << DMA2D_OUT_PIXEL_BYTE_CH0_S) -#define DMA2D_OUT_PIXEL_BYTE_CH0_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH0_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_M (DMA2D_OUT_BURST_BLOCK_NUM_CH0_V << DMA2D_OUT_BURST_BLOCK_NUM_CH0_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_S 14 - -/** DMA2D_OUT_RO_PD_CONF_CH0_REG register - * Configures the tx reorder memory of channel 0 - */ -#define DMA2D_OUT_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x44) -/** DMA2D_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0 (BIT(4)) -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_M (DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S) -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S 4 -/** DMA2D_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0 (BIT(5)) -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_M (DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S) -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S 5 -/** DMA2D_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0 (BIT(6)) -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_M (DMA2D_OUT_RO_RAM_CLK_FO_CH0_V << DMA2D_OUT_RO_RAM_CLK_FO_CH0_S) -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_V 0x00000001U -#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_S 6 - -/** DMA2D_OUT_COLOR_CONVERT_CH0_REG register - * Configures the tx color convert of channel 0 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x48) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_M (DMA2D_OUT_COLOR_INPUT_SEL_CH0_V << DMA2D_OUT_COLOR_INPUT_SEL_CH0_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH0_REG register - * Configures the tx scramble of channel 0 - */ -#define DMA2D_OUT_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x4c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x50) -/** DMA2D_OUT_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_M (DMA2D_OUT_COLOR_PARAM_H0_CH0_V << DMA2D_OUT_COLOR_PARAM_H0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x54) -/** DMA2D_OUT_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_M (DMA2D_OUT_COLOR_PARAM_H1_CH0_V << DMA2D_OUT_COLOR_PARAM_H1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x58) -/** DMA2D_OUT_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_M (DMA2D_OUT_COLOR_PARAM_M0_CH0_V << DMA2D_OUT_COLOR_PARAM_M0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x5c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_M (DMA2D_OUT_COLOR_PARAM_M1_CH0_V << DMA2D_OUT_COLOR_PARAM_M1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x60) -/** DMA2D_OUT_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH0 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_M (DMA2D_OUT_COLOR_PARAM_L0_CH0_V << DMA2D_OUT_COLOR_PARAM_L0_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH0_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH0_REG register - * Configures the tx color convert parameter of channel 0 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x64) -/** DMA2D_OUT_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH0 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_M (DMA2D_OUT_COLOR_PARAM_L1_CH0_V << DMA2D_OUT_COLOR_PARAM_L1_CH0_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH0_S 0 - -/** DMA2D_OUT_ETM_CONF_CH0_REG register - * Configures the tx etm of channel 0 - */ -#define DMA2D_OUT_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x68) -/** DMA2D_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH0 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH0_M (DMA2D_OUT_ETM_EN_CH0_V << DMA2D_OUT_ETM_EN_CH0_S) -#define DMA2D_OUT_ETM_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH0_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH0 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH0_M (DMA2D_OUT_ETM_LOOP_EN_CH0_V << DMA2D_OUT_ETM_LOOP_EN_CH0_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH0_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH0_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH0 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_M (DMA2D_OUT_DSCR_TASK_MAK_CH0_V << DMA2D_OUT_DSCR_TASK_MAK_CH0_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH0_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH0_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH0_REG (DR_REG_DMA2D_BASE + 0x6c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH0 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH0 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S 14 - -/** DMA2D_OUT_CONF0_CH1_REG register - * Configures the tx direction of channel 1 - */ -#define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100) -/** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH1 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH1_M (DMA2D_OUT_AUTO_WRBACK_CH1_V << DMA2D_OUT_AUTO_WRBACK_CH1_S) -#define DMA2D_OUT_AUTO_WRBACK_CH1_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH1_S 0 -/** DMA2D_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH1 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH1_M (DMA2D_OUT_EOF_MODE_CH1_V << DMA2D_OUT_EOF_MODE_CH1_S) -#define DMA2D_OUT_EOF_MODE_CH1_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH1_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH1_M (DMA2D_OUTDSCR_BURST_EN_CH1_V << DMA2D_OUTDSCR_BURST_EN_CH1_S) -#define DMA2D_OUTDSCR_BURST_EN_CH1_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH1_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH1 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH1_M (DMA2D_OUT_ECC_AES_EN_CH1_V << DMA2D_OUT_ECC_AES_EN_CH1_S) -#define DMA2D_OUT_ECC_AES_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH1_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH1 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH1_M (DMA2D_OUT_CHECK_OWNER_CH1_V << DMA2D_OUT_CHECK_OWNER_CH1_S) -#define DMA2D_OUT_CHECK_OWNER_CH1_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH1_S 4 -/** DMA2D_OUT_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH1 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH1_M (DMA2D_OUT_LOOP_TEST_CH1_V << DMA2D_OUT_LOOP_TEST_CH1_S) -#define DMA2D_OUT_LOOP_TEST_CH1_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH1_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_M (DMA2D_OUT_MEM_BURST_LENGTH_CH1_V << DMA2D_OUT_MEM_BURST_LENGTH_CH1_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH1 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH1_M (DMA2D_OUT_DSCR_PORT_EN_CH1_V << DMA2D_OUT_DSCR_PORT_EN_CH1_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH1_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH1_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH1 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_M (DMA2D_OUT_PAGE_BOUND_EN_CH1_V << DMA2D_OUT_PAGE_BOUND_EN_CH1_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH1_S 12 -/** DMA2D_OUT_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH1 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH1_M (DMA2D_OUT_REORDER_EN_CH1_V << DMA2D_OUT_REORDER_EN_CH1_S) -#define DMA2D_OUT_REORDER_EN_CH1_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH1_S 16 -/** DMA2D_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH1 (BIT(24)) -#define DMA2D_OUT_RST_CH1_M (DMA2D_OUT_RST_CH1_V << DMA2D_OUT_RST_CH1_S) -#define DMA2D_OUT_RST_CH1_V 0x00000001U -#define DMA2D_OUT_RST_CH1_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH1 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH1_M (DMA2D_OUT_CMD_DISABLE_CH1_V << DMA2D_OUT_CMD_DISABLE_CH1_S) -#define DMA2D_OUT_CMD_DISABLE_CH1_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH1_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S 26 - -/** DMA2D_OUT_INT_RAW_CH1_REG register - * Raw interrupt status of TX channel 1 - */ -#define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104) -/** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH1_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_RAW_M (DMA2D_OUT_DONE_CH1_INT_RAW_V << DMA2D_OUT_DONE_CH1_INT_RAW_S) -#define DMA2D_OUT_DONE_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH1_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_RAW_M (DMA2D_OUT_EOF_CH1_INT_RAW_V << DMA2D_OUT_EOF_CH1_INT_RAW_S) -#define DMA2D_OUT_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 1 - */ -#define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108) -/** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_ENA_M (DMA2D_OUT_DONE_CH1_INT_ENA_V << DMA2D_OUT_DONE_CH1_INT_ENA_S) -#define DMA2D_OUT_DONE_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_ENA_M (DMA2D_OUT_EOF_CH1_INT_ENA_V << DMA2D_OUT_EOF_CH1_INT_ENA_S) -#define DMA2D_OUT_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 1 - */ -#define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c) -/** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_ST_M (DMA2D_OUT_DONE_CH1_INT_ST_V << DMA2D_OUT_DONE_CH1_INT_ST_S) -#define DMA2D_OUT_DONE_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_ST_M (DMA2D_OUT_EOF_CH1_INT_ST_V << DMA2D_OUT_EOF_CH1_INT_ST_S) -#define DMA2D_OUT_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 1 - */ -#define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110) -/** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH1_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH1_INT_CLR_M (DMA2D_OUT_DONE_CH1_INT_CLR_V << DMA2D_OUT_DONE_CH1_INT_CLR_S) -#define DMA2D_OUT_DONE_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH1_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH1_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH1_INT_CLR_M (DMA2D_OUT_EOF_CH1_INT_CLR_V << DMA2D_OUT_EOF_CH1_INT_CLR_S) -#define DMA2D_OUT_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH1_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH1_REG register - * Represents the status of the tx fifo of channel 1 - */ -#define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114) -/** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH1 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH1_M (DMA2D_OUTFIFO_FULL_L2_CH1_V << DMA2D_OUTFIFO_FULL_L2_CH1_S) -#define DMA2D_OUTFIFO_FULL_L2_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH1_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH1 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_M (DMA2D_OUTFIFO_EMPTY_L2_CH1_V << DMA2D_OUTFIFO_EMPTY_L2_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH1_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH1 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH1_M (DMA2D_OUTFIFO_CNT_L2_CH1_V << DMA2D_OUTFIFO_CNT_L2_CH1_S) -#define DMA2D_OUTFIFO_CNT_L2_CH1_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH1_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_M (DMA2D_OUT_REMAIN_UNDER_1B_CH1_V << DMA2D_OUT_REMAIN_UNDER_1B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_M (DMA2D_OUT_REMAIN_UNDER_2B_CH1_V << DMA2D_OUT_REMAIN_UNDER_2B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_M (DMA2D_OUT_REMAIN_UNDER_3B_CH1_V << DMA2D_OUT_REMAIN_UNDER_3B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_M (DMA2D_OUT_REMAIN_UNDER_4B_CH1_V << DMA2D_OUT_REMAIN_UNDER_4B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_M (DMA2D_OUT_REMAIN_UNDER_5B_CH1_V << DMA2D_OUT_REMAIN_UNDER_5B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_M (DMA2D_OUT_REMAIN_UNDER_6B_CH1_V << DMA2D_OUT_REMAIN_UNDER_6B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_M (DMA2D_OUT_REMAIN_UNDER_7B_CH1_V << DMA2D_OUT_REMAIN_UNDER_7B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_M (DMA2D_OUT_REMAIN_UNDER_8B_CH1_V << DMA2D_OUT_REMAIN_UNDER_8B_CH1_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH1 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH1_M (DMA2D_OUTFIFO_FULL_L1_CH1_V << DMA2D_OUTFIFO_FULL_L1_CH1_S) -#define DMA2D_OUTFIFO_FULL_L1_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH1_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH1 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_M (DMA2D_OUTFIFO_EMPTY_L1_CH1_V << DMA2D_OUTFIFO_EMPTY_L1_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH1_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH1 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH1_M (DMA2D_OUTFIFO_CNT_L1_CH1_V << DMA2D_OUTFIFO_CNT_L1_CH1_S) -#define DMA2D_OUTFIFO_CNT_L1_CH1_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH1_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH1 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH1_M (DMA2D_OUTFIFO_FULL_L3_CH1_V << DMA2D_OUTFIFO_FULL_L3_CH1_S) -#define DMA2D_OUTFIFO_FULL_L3_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH1_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH1 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_M (DMA2D_OUTFIFO_EMPTY_L3_CH1_V << DMA2D_OUTFIFO_EMPTY_L3_CH1_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH1_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH1 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH1_M (DMA2D_OUTFIFO_CNT_L3_CH1_V << DMA2D_OUTFIFO_CNT_L3_CH1_S) -#define DMA2D_OUTFIFO_CNT_L3_CH1_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH1_S 24 - -/** DMA2D_OUT_PUSH_CH1_REG register - * Configures the tx fifo of channel 1 - */ -#define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118) -/** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH1 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH1_M (DMA2D_OUTFIFO_WDATA_CH1_V << DMA2D_OUTFIFO_WDATA_CH1_S) -#define DMA2D_OUTFIFO_WDATA_CH1_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH1_S 0 -/** DMA2D_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH1 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH1_M (DMA2D_OUTFIFO_PUSH_CH1_V << DMA2D_OUTFIFO_PUSH_CH1_S) -#define DMA2D_OUTFIFO_PUSH_CH1_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH1_S 10 - -/** DMA2D_OUT_LINK_CONF_CH1_REG register - * Configures the tx descriptor operations of channel 1 - */ -#define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c) -/** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH1 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH1_M (DMA2D_OUTLINK_STOP_CH1_V << DMA2D_OUTLINK_STOP_CH1_S) -#define DMA2D_OUTLINK_STOP_CH1_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH1_S 20 -/** DMA2D_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH1 (BIT(21)) -#define DMA2D_OUTLINK_START_CH1_M (DMA2D_OUTLINK_START_CH1_V << DMA2D_OUTLINK_START_CH1_S) -#define DMA2D_OUTLINK_START_CH1_V 0x00000001U -#define DMA2D_OUTLINK_START_CH1_S 21 -/** DMA2D_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH1 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH1_M (DMA2D_OUTLINK_RESTART_CH1_V << DMA2D_OUTLINK_RESTART_CH1_S) -#define DMA2D_OUTLINK_RESTART_CH1_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH1_S 22 -/** DMA2D_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH1 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH1_M (DMA2D_OUTLINK_PARK_CH1_V << DMA2D_OUTLINK_PARK_CH1_S) -#define DMA2D_OUTLINK_PARK_CH1_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH1_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH1_REG register - * Configures the tx descriptor address of channel 1 - */ -#define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120) -/** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH1_M (DMA2D_OUTLINK_ADDR_CH1_V << DMA2D_OUTLINK_ADDR_CH1_S) -#define DMA2D_OUTLINK_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH1_S 0 - -/** DMA2D_OUT_STATE_CH1_REG register - * Represents the working status of the tx descriptor of channel 1 - */ -#define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124) -/** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_M (DMA2D_OUTLINK_DSCR_ADDR_CH1_V << DMA2D_OUTLINK_DSCR_ADDR_CH1_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH1_S 0 -/** DMA2D_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH1 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH1_M (DMA2D_OUT_DSCR_STATE_CH1_V << DMA2D_OUT_DSCR_STATE_CH1_S) -#define DMA2D_OUT_DSCR_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH1_S 18 -/** DMA2D_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH1 0x0000000FU -#define DMA2D_OUT_STATE_CH1_M (DMA2D_OUT_STATE_CH1_V << DMA2D_OUT_STATE_CH1_S) -#define DMA2D_OUT_STATE_CH1_V 0x0000000FU -#define DMA2D_OUT_STATE_CH1_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH1 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH1_M (DMA2D_OUT_RESET_AVAIL_CH1_V << DMA2D_OUT_RESET_AVAIL_CH1_S) -#define DMA2D_OUT_RESET_AVAIL_CH1_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH1_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128) -/** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH1_M (DMA2D_OUT_EOF_DES_ADDR_CH1_V << DMA2D_OUT_EOF_DES_ADDR_CH1_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_OUT_DSCR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c) -/** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH1_M (DMA2D_OUTLINK_DSCR_CH1_V << DMA2D_OUTLINK_DSCR_CH1_S) -#define DMA2D_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH1_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130) -/** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH1_M (DMA2D_OUTLINK_DSCR_BF0_CH1_V << DMA2D_OUTLINK_DSCR_BF0_CH1_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH1_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 1 - */ -#define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134) -/** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH1_M (DMA2D_OUTLINK_DSCR_BF1_CH1_V << DMA2D_OUTLINK_DSCR_BF1_CH1_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH1_S 0 - -/** DMA2D_OUT_PERI_SEL_CH1_REG register - * Configures the tx peripheral of channel 1 - */ -#define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138) -/** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH1 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH1_M (DMA2D_OUT_PERI_SEL_CH1_V << DMA2D_OUT_PERI_SEL_CH1_S) -#define DMA2D_OUT_PERI_SEL_CH1_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH1_S 0 - -/** DMA2D_OUT_ARB_CH1_REG register - * Configures the tx arbiter of channel 1 - */ -#define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH1 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH1_M (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH1_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH1 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_M (DMA2D_OUT_ARB_PRIORITY_H_CH1_V << DMA2D_OUT_ARB_PRIORITY_H_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH1_S 6 - -/** DMA2D_OUT_RO_STATUS_CH1_REG register - * Represents the status of the tx reorder module of channel 1 - */ -#define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140) -/** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH1 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH1_M (DMA2D_OUTFIFO_RO_CNT_CH1_V << DMA2D_OUTFIFO_RO_CNT_CH1_S) -#define DMA2D_OUTFIFO_RO_CNT_CH1_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH1_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH1 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH1 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH1_M (DMA2D_OUT_RO_WR_STATE_CH1_V << DMA2D_OUT_RO_WR_STATE_CH1_S) -#define DMA2D_OUT_RO_WR_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH1_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH1 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH1 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH1_M (DMA2D_OUT_RO_RD_STATE_CH1_V << DMA2D_OUT_RO_RD_STATE_CH1_S) -#define DMA2D_OUT_RO_RD_STATE_CH1_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH1_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH1 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH1 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH1_M (DMA2D_OUT_PIXEL_BYTE_CH1_V << DMA2D_OUT_PIXEL_BYTE_CH1_S) -#define DMA2D_OUT_PIXEL_BYTE_CH1_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH1_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH1 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_M (DMA2D_OUT_BURST_BLOCK_NUM_CH1_V << DMA2D_OUT_BURST_BLOCK_NUM_CH1_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH1_REG register - * Configures the tx color convert of channel 1 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_M (DMA2D_OUT_COLOR_INPUT_SEL_CH1_V << DMA2D_OUT_COLOR_INPUT_SEL_CH1_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH1_REG register - * Configures the tx scramble of channel 1 - */ -#define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150) -/** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_M (DMA2D_OUT_COLOR_PARAM_H0_CH1_V << DMA2D_OUT_COLOR_PARAM_H0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154) -/** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_M (DMA2D_OUT_COLOR_PARAM_H1_CH1_V << DMA2D_OUT_COLOR_PARAM_H1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158) -/** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_M (DMA2D_OUT_COLOR_PARAM_M0_CH1_V << DMA2D_OUT_COLOR_PARAM_M0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_M (DMA2D_OUT_COLOR_PARAM_M1_CH1_V << DMA2D_OUT_COLOR_PARAM_M1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160) -/** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH1 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_M (DMA2D_OUT_COLOR_PARAM_L0_CH1_V << DMA2D_OUT_COLOR_PARAM_L0_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH1_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH1_REG register - * Configures the tx color convert parameter of channel 1 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164) -/** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH1 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_M (DMA2D_OUT_COLOR_PARAM_L1_CH1_V << DMA2D_OUT_COLOR_PARAM_L1_CH1_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH1_S 0 - -/** DMA2D_OUT_ETM_CONF_CH1_REG register - * Configures the tx etm of channel 1 - */ -#define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168) -/** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH1 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH1_M (DMA2D_OUT_ETM_EN_CH1_V << DMA2D_OUT_ETM_EN_CH1_S) -#define DMA2D_OUT_ETM_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH1_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH1 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH1_M (DMA2D_OUT_ETM_LOOP_EN_CH1_V << DMA2D_OUT_ETM_LOOP_EN_CH1_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH1_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH1_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH1 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_M (DMA2D_OUT_DSCR_TASK_MAK_CH1_V << DMA2D_OUT_DSCR_TASK_MAK_CH1_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH1_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH1_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH1_REG (DR_REG_DMA2D_BASE + 0x16c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH1 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH1 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S 14 - -/** DMA2D_OUT_CONF0_CH2_REG register - * Configures the tx direction of channel 2 - */ -#define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200) -/** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH2 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH2_M (DMA2D_OUT_AUTO_WRBACK_CH2_V << DMA2D_OUT_AUTO_WRBACK_CH2_S) -#define DMA2D_OUT_AUTO_WRBACK_CH2_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH2_S 0 -/** DMA2D_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH2 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH2_M (DMA2D_OUT_EOF_MODE_CH2_V << DMA2D_OUT_EOF_MODE_CH2_S) -#define DMA2D_OUT_EOF_MODE_CH2_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH2_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH2 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH2_M (DMA2D_OUTDSCR_BURST_EN_CH2_V << DMA2D_OUTDSCR_BURST_EN_CH2_S) -#define DMA2D_OUTDSCR_BURST_EN_CH2_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH2_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH2 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH2_M (DMA2D_OUT_ECC_AES_EN_CH2_V << DMA2D_OUT_ECC_AES_EN_CH2_S) -#define DMA2D_OUT_ECC_AES_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH2_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH2 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH2_M (DMA2D_OUT_CHECK_OWNER_CH2_V << DMA2D_OUT_CHECK_OWNER_CH2_S) -#define DMA2D_OUT_CHECK_OWNER_CH2_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH2_S 4 -/** DMA2D_OUT_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH2 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH2_M (DMA2D_OUT_LOOP_TEST_CH2_V << DMA2D_OUT_LOOP_TEST_CH2_S) -#define DMA2D_OUT_LOOP_TEST_CH2_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH2_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_M (DMA2D_OUT_MEM_BURST_LENGTH_CH2_V << DMA2D_OUT_MEM_BURST_LENGTH_CH2_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH2 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH2_M (DMA2D_OUT_DSCR_PORT_EN_CH2_V << DMA2D_OUT_DSCR_PORT_EN_CH2_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH2_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH2_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH2 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_M (DMA2D_OUT_PAGE_BOUND_EN_CH2_V << DMA2D_OUT_PAGE_BOUND_EN_CH2_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH2_S 12 -/** DMA2D_OUT_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH2 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH2_M (DMA2D_OUT_REORDER_EN_CH2_V << DMA2D_OUT_REORDER_EN_CH2_S) -#define DMA2D_OUT_REORDER_EN_CH2_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH2_S 16 -/** DMA2D_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH2 (BIT(24)) -#define DMA2D_OUT_RST_CH2_M (DMA2D_OUT_RST_CH2_V << DMA2D_OUT_RST_CH2_S) -#define DMA2D_OUT_RST_CH2_V 0x00000001U -#define DMA2D_OUT_RST_CH2_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH2 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH2_M (DMA2D_OUT_CMD_DISABLE_CH2_V << DMA2D_OUT_CMD_DISABLE_CH2_S) -#define DMA2D_OUT_CMD_DISABLE_CH2_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH2_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S 26 - -/** DMA2D_OUT_INT_RAW_CH2_REG register - * Raw interrupt status of TX channel 2 - */ -#define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204) -/** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH2_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_RAW_M (DMA2D_OUT_DONE_CH2_INT_RAW_V << DMA2D_OUT_DONE_CH2_INT_RAW_S) -#define DMA2D_OUT_DONE_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH2_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_RAW_M (DMA2D_OUT_EOF_CH2_INT_RAW_V << DMA2D_OUT_EOF_CH2_INT_RAW_S) -#define DMA2D_OUT_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of TX channel 2 - */ -#define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208) -/** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_ENA_M (DMA2D_OUT_DONE_CH2_INT_ENA_V << DMA2D_OUT_DONE_CH2_INT_ENA_S) -#define DMA2D_OUT_DONE_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_ENA_M (DMA2D_OUT_EOF_CH2_INT_ENA_V << DMA2D_OUT_EOF_CH2_INT_ENA_S) -#define DMA2D_OUT_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH2_REG register - * Masked interrupt status of TX channel 2 - */ -#define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c) -/** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_ST_M (DMA2D_OUT_DONE_CH2_INT_ST_V << DMA2D_OUT_DONE_CH2_INT_ST_S) -#define DMA2D_OUT_DONE_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_ST_M (DMA2D_OUT_EOF_CH2_INT_ST_V << DMA2D_OUT_EOF_CH2_INT_ST_S) -#define DMA2D_OUT_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of TX channel 2 - */ -#define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210) -/** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH2_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH2_INT_CLR_M (DMA2D_OUT_DONE_CH2_INT_CLR_V << DMA2D_OUT_DONE_CH2_INT_CLR_S) -#define DMA2D_OUT_DONE_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH2_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH2_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH2_INT_CLR_M (DMA2D_OUT_EOF_CH2_INT_CLR_V << DMA2D_OUT_EOF_CH2_INT_CLR_S) -#define DMA2D_OUT_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH2_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH2_REG register - * Represents the status of the tx fifo of channel 2 - */ -#define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214) -/** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH2 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH2_M (DMA2D_OUTFIFO_FULL_L2_CH2_V << DMA2D_OUTFIFO_FULL_L2_CH2_S) -#define DMA2D_OUTFIFO_FULL_L2_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH2_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH2 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_M (DMA2D_OUTFIFO_EMPTY_L2_CH2_V << DMA2D_OUTFIFO_EMPTY_L2_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH2_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH2 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH2_M (DMA2D_OUTFIFO_CNT_L2_CH2_V << DMA2D_OUTFIFO_CNT_L2_CH2_S) -#define DMA2D_OUTFIFO_CNT_L2_CH2_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH2_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_M (DMA2D_OUT_REMAIN_UNDER_1B_CH2_V << DMA2D_OUT_REMAIN_UNDER_1B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_M (DMA2D_OUT_REMAIN_UNDER_2B_CH2_V << DMA2D_OUT_REMAIN_UNDER_2B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_M (DMA2D_OUT_REMAIN_UNDER_3B_CH2_V << DMA2D_OUT_REMAIN_UNDER_3B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_M (DMA2D_OUT_REMAIN_UNDER_4B_CH2_V << DMA2D_OUT_REMAIN_UNDER_4B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_M (DMA2D_OUT_REMAIN_UNDER_5B_CH2_V << DMA2D_OUT_REMAIN_UNDER_5B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_M (DMA2D_OUT_REMAIN_UNDER_6B_CH2_V << DMA2D_OUT_REMAIN_UNDER_6B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_M (DMA2D_OUT_REMAIN_UNDER_7B_CH2_V << DMA2D_OUT_REMAIN_UNDER_7B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_M (DMA2D_OUT_REMAIN_UNDER_8B_CH2_V << DMA2D_OUT_REMAIN_UNDER_8B_CH2_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH2 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH2_M (DMA2D_OUTFIFO_FULL_L1_CH2_V << DMA2D_OUTFIFO_FULL_L1_CH2_S) -#define DMA2D_OUTFIFO_FULL_L1_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH2_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH2 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_M (DMA2D_OUTFIFO_EMPTY_L1_CH2_V << DMA2D_OUTFIFO_EMPTY_L1_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH2_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH2 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH2_M (DMA2D_OUTFIFO_CNT_L1_CH2_V << DMA2D_OUTFIFO_CNT_L1_CH2_S) -#define DMA2D_OUTFIFO_CNT_L1_CH2_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH2_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH2 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH2_M (DMA2D_OUTFIFO_FULL_L3_CH2_V << DMA2D_OUTFIFO_FULL_L3_CH2_S) -#define DMA2D_OUTFIFO_FULL_L3_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH2_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH2 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_M (DMA2D_OUTFIFO_EMPTY_L3_CH2_V << DMA2D_OUTFIFO_EMPTY_L3_CH2_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH2_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH2 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH2_M (DMA2D_OUTFIFO_CNT_L3_CH2_V << DMA2D_OUTFIFO_CNT_L3_CH2_S) -#define DMA2D_OUTFIFO_CNT_L3_CH2_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH2_S 24 - -/** DMA2D_OUT_PUSH_CH2_REG register - * Configures the tx fifo of channel 2 - */ -#define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218) -/** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH2 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH2_M (DMA2D_OUTFIFO_WDATA_CH2_V << DMA2D_OUTFIFO_WDATA_CH2_S) -#define DMA2D_OUTFIFO_WDATA_CH2_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH2_S 0 -/** DMA2D_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH2 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH2_M (DMA2D_OUTFIFO_PUSH_CH2_V << DMA2D_OUTFIFO_PUSH_CH2_S) -#define DMA2D_OUTFIFO_PUSH_CH2_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH2_S 10 - -/** DMA2D_OUT_LINK_CONF_CH2_REG register - * Configures the tx descriptor operations of channel 2 - */ -#define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c) -/** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH2 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH2_M (DMA2D_OUTLINK_STOP_CH2_V << DMA2D_OUTLINK_STOP_CH2_S) -#define DMA2D_OUTLINK_STOP_CH2_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH2_S 20 -/** DMA2D_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH2 (BIT(21)) -#define DMA2D_OUTLINK_START_CH2_M (DMA2D_OUTLINK_START_CH2_V << DMA2D_OUTLINK_START_CH2_S) -#define DMA2D_OUTLINK_START_CH2_V 0x00000001U -#define DMA2D_OUTLINK_START_CH2_S 21 -/** DMA2D_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH2 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH2_M (DMA2D_OUTLINK_RESTART_CH2_V << DMA2D_OUTLINK_RESTART_CH2_S) -#define DMA2D_OUTLINK_RESTART_CH2_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH2_S 22 -/** DMA2D_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH2 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH2_M (DMA2D_OUTLINK_PARK_CH2_V << DMA2D_OUTLINK_PARK_CH2_S) -#define DMA2D_OUTLINK_PARK_CH2_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH2_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH2_REG register - * Configures the tx descriptor address of channel 2 - */ -#define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220) -/** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH2_M (DMA2D_OUTLINK_ADDR_CH2_V << DMA2D_OUTLINK_ADDR_CH2_S) -#define DMA2D_OUTLINK_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH2_S 0 - -/** DMA2D_OUT_STATE_CH2_REG register - * Represents the working status of the tx descriptor of channel 2 - */ -#define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224) -/** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_M (DMA2D_OUTLINK_DSCR_ADDR_CH2_V << DMA2D_OUTLINK_DSCR_ADDR_CH2_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH2_S 0 -/** DMA2D_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH2 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH2_M (DMA2D_OUT_DSCR_STATE_CH2_V << DMA2D_OUT_DSCR_STATE_CH2_S) -#define DMA2D_OUT_DSCR_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH2_S 18 -/** DMA2D_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH2 0x0000000FU -#define DMA2D_OUT_STATE_CH2_M (DMA2D_OUT_STATE_CH2_V << DMA2D_OUT_STATE_CH2_S) -#define DMA2D_OUT_STATE_CH2_V 0x0000000FU -#define DMA2D_OUT_STATE_CH2_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH2 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH2_M (DMA2D_OUT_RESET_AVAIL_CH2_V << DMA2D_OUT_RESET_AVAIL_CH2_S) -#define DMA2D_OUT_RESET_AVAIL_CH2_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH2_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228) -/** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH2_M (DMA2D_OUT_EOF_DES_ADDR_CH2_V << DMA2D_OUT_EOF_DES_ADDR_CH2_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_OUT_DSCR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c) -/** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH2_M (DMA2D_OUTLINK_DSCR_CH2_V << DMA2D_OUTLINK_DSCR_CH2_S) -#define DMA2D_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH2_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230) -/** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH2_M (DMA2D_OUTLINK_DSCR_BF0_CH2_V << DMA2D_OUTLINK_DSCR_BF0_CH2_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH2_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 2 - */ -#define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234) -/** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH2_M (DMA2D_OUTLINK_DSCR_BF1_CH2_V << DMA2D_OUTLINK_DSCR_BF1_CH2_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH2_S 0 - -/** DMA2D_OUT_PERI_SEL_CH2_REG register - * Configures the tx peripheral of channel 2 - */ -#define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238) -/** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH2 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH2_M (DMA2D_OUT_PERI_SEL_CH2_V << DMA2D_OUT_PERI_SEL_CH2_S) -#define DMA2D_OUT_PERI_SEL_CH2_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH2_S 0 - -/** DMA2D_OUT_ARB_CH2_REG register - * Configures the tx arbiter of channel 2 - */ -#define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH2 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH2_M (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH2_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH2 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_M (DMA2D_OUT_ARB_PRIORITY_H_CH2_V << DMA2D_OUT_ARB_PRIORITY_H_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH2_S 6 - -/** DMA2D_OUT_RO_STATUS_CH2_REG register - * Represents the status of the tx reorder module of channel 2 - */ -#define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240) -/** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH2 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH2_M (DMA2D_OUTFIFO_RO_CNT_CH2_V << DMA2D_OUTFIFO_RO_CNT_CH2_S) -#define DMA2D_OUTFIFO_RO_CNT_CH2_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH2_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH2 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH2 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH2_M (DMA2D_OUT_RO_WR_STATE_CH2_V << DMA2D_OUT_RO_WR_STATE_CH2_S) -#define DMA2D_OUT_RO_WR_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH2_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH2 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH2 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH2_M (DMA2D_OUT_RO_RD_STATE_CH2_V << DMA2D_OUT_RO_RD_STATE_CH2_S) -#define DMA2D_OUT_RO_RD_STATE_CH2_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH2_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH2 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH2 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH2_M (DMA2D_OUT_PIXEL_BYTE_CH2_V << DMA2D_OUT_PIXEL_BYTE_CH2_S) -#define DMA2D_OUT_PIXEL_BYTE_CH2_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH2_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH2 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_M (DMA2D_OUT_BURST_BLOCK_NUM_CH2_V << DMA2D_OUT_BURST_BLOCK_NUM_CH2_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH2_REG register - * Configures the tx color convert of channel 2 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_M (DMA2D_OUT_COLOR_INPUT_SEL_CH2_V << DMA2D_OUT_COLOR_INPUT_SEL_CH2_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH2_REG register - * Configures the tx scramble of channel 2 - */ -#define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250) -/** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_M (DMA2D_OUT_COLOR_PARAM_H0_CH2_V << DMA2D_OUT_COLOR_PARAM_H0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254) -/** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_M (DMA2D_OUT_COLOR_PARAM_H1_CH2_V << DMA2D_OUT_COLOR_PARAM_H1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258) -/** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_M (DMA2D_OUT_COLOR_PARAM_M0_CH2_V << DMA2D_OUT_COLOR_PARAM_M0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_M (DMA2D_OUT_COLOR_PARAM_M1_CH2_V << DMA2D_OUT_COLOR_PARAM_M1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260) -/** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH2 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_M (DMA2D_OUT_COLOR_PARAM_L0_CH2_V << DMA2D_OUT_COLOR_PARAM_L0_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH2_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH2_REG register - * Configures the tx color convert parameter of channel 2 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264) -/** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH2 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_M (DMA2D_OUT_COLOR_PARAM_L1_CH2_V << DMA2D_OUT_COLOR_PARAM_L1_CH2_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH2_S 0 - -/** DMA2D_OUT_ETM_CONF_CH2_REG register - * Configures the tx etm of channel 2 - */ -#define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268) -/** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH2 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH2_M (DMA2D_OUT_ETM_EN_CH2_V << DMA2D_OUT_ETM_EN_CH2_S) -#define DMA2D_OUT_ETM_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH2_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH2 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH2_M (DMA2D_OUT_ETM_LOOP_EN_CH2_V << DMA2D_OUT_ETM_LOOP_EN_CH2_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH2_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH2_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH2 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_M (DMA2D_OUT_DSCR_TASK_MAK_CH2_V << DMA2D_OUT_DSCR_TASK_MAK_CH2_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH2_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH2_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH2_REG (DR_REG_DMA2D_BASE + 0x26c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH2 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH2 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S 14 - -/** DMA2D_OUT_CONF0_CH3_REG register - * Configures the tx direction of channel 3 - */ -#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300) -/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ -#define DMA2D_OUT_AUTO_WRBACK_CH3 (BIT(0)) -#define DMA2D_OUT_AUTO_WRBACK_CH3_M (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S) -#define DMA2D_OUT_AUTO_WRBACK_CH3_V 0x00000001U -#define DMA2D_OUT_AUTO_WRBACK_CH3_S 0 -/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ -#define DMA2D_OUT_EOF_MODE_CH3 (BIT(1)) -#define DMA2D_OUT_EOF_MODE_CH3_M (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S) -#define DMA2D_OUT_EOF_MODE_CH3_V 0x00000001U -#define DMA2D_OUT_EOF_MODE_CH3_S 1 -/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ -#define DMA2D_OUTDSCR_BURST_EN_CH3 (BIT(2)) -#define DMA2D_OUTDSCR_BURST_EN_CH3_M (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S) -#define DMA2D_OUTDSCR_BURST_EN_CH3_V 0x00000001U -#define DMA2D_OUTDSCR_BURST_EN_CH3_S 2 -/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_OUT_ECC_AES_EN_CH3 (BIT(3)) -#define DMA2D_OUT_ECC_AES_EN_CH3_M (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S) -#define DMA2D_OUT_ECC_AES_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ECC_AES_EN_CH3_S 3 -/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_OUT_CHECK_OWNER_CH3 (BIT(4)) -#define DMA2D_OUT_CHECK_OWNER_CH3_M (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S) -#define DMA2D_OUT_CHECK_OWNER_CH3_V 0x00000001U -#define DMA2D_OUT_CHECK_OWNER_CH3_S 4 -/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_OUT_LOOP_TEST_CH3 (BIT(5)) -#define DMA2D_OUT_LOOP_TEST_CH3_M (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S) -#define DMA2D_OUT_LOOP_TEST_CH3_V 0x00000001U -#define DMA2D_OUT_LOOP_TEST_CH3_S 5 -/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S) -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V 0x00000007U -#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S 6 -/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S) -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V 0x00000003U -#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S 9 -/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_OUT_DSCR_PORT_EN_CH3 (BIT(11)) -#define DMA2D_OUT_DSCR_PORT_EN_CH3_M (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S) -#define DMA2D_OUT_DSCR_PORT_EN_CH3_V 0x00000001U -#define DMA2D_OUT_DSCR_PORT_EN_CH3_S 11 -/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ -#define DMA2D_OUT_PAGE_BOUND_EN_CH3 (BIT(12)) -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S) -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V 0x00000001U -#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S 12 -/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_OUT_REORDER_EN_CH3 (BIT(16)) -#define DMA2D_OUT_REORDER_EN_CH3_M (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S) -#define DMA2D_OUT_REORDER_EN_CH3_V 0x00000001U -#define DMA2D_OUT_REORDER_EN_CH3_S 16 -/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ -#define DMA2D_OUT_RST_CH3 (BIT(24)) -#define DMA2D_OUT_RST_CH3_M (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S) -#define DMA2D_OUT_RST_CH3_V 0x00000001U -#define DMA2D_OUT_RST_CH3_S 24 -/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_OUT_CMD_DISABLE_CH3 (BIT(25)) -#define DMA2D_OUT_CMD_DISABLE_CH3_M (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S) -#define DMA2D_OUT_CMD_DISABLE_CH3_V 0x00000001U -#define DMA2D_OUT_CMD_DISABLE_CH3_S 25 -/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 (BIT(26)) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S) -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V 0x00000001U -#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S 26 - -/** DMA2D_OUT_INT_RAW_CH3_REG register - * Raw interrupt status of TX channel 3 - */ -#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304) -/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ -#define DMA2D_OUT_DONE_CH3_INT_RAW (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_RAW_M (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S) -#define DMA2D_OUT_DONE_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_RAW_S 0 -/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ -#define DMA2D_OUT_EOF_CH3_INT_RAW (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_RAW_M (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S) -#define DMA2D_OUT_EOF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_RAW_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S 12 - -/** DMA2D_OUT_INT_ENA_CH3_REG register - * Interrupt enable bits of TX channel 3 - */ -#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308) -/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_ENA (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_ENA_M (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S) -#define DMA2D_OUT_DONE_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_ENA_S 0 -/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_ENA (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_ENA_M (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S) -#define DMA2D_OUT_EOF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_ENA_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S 12 - -/** DMA2D_OUT_INT_ST_CH3_REG register - * Masked interrupt status of TX channel 3 - */ -#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c) -/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_ST (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_ST_M (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S) -#define DMA2D_OUT_DONE_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_ST_S 0 -/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_ST (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_ST_M (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S) -#define DMA2D_OUT_EOF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_ST_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S 12 - -/** DMA2D_OUT_INT_CLR_CH3_REG register - * Interrupt clear bits of TX channel 3 - */ -#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310) -/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ -#define DMA2D_OUT_DONE_CH3_INT_CLR (BIT(0)) -#define DMA2D_OUT_DONE_CH3_INT_CLR_M (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S) -#define DMA2D_OUT_DONE_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DONE_CH3_INT_CLR_S 0 -/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_EOF_CH3_INT_CLR (BIT(1)) -#define DMA2D_OUT_EOF_CH3_INT_CLR_M (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S) -#define DMA2D_OUT_EOF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_EOF_CH3_INT_CLR_S 1 -/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR (BIT(2)) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S) -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S 2 -/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(3)) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S) -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S 3 -/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(4)) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S 4 -/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(5)) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S 5 -/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR (BIT(6)) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S 6 -/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR (BIT(7)) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S 7 -/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(8)) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S 8 -/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(9)) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S 9 -/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR (BIT(10)) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S 10 -/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR (BIT(11)) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S) -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S 11 -/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR (BIT(12)) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S) -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V 0x00000001U -#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S 12 - -/** DMA2D_OUTFIFO_STATUS_CH3_REG register - * Represents the status of the tx fifo of channel 3 - */ -#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314) -/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L2_CH3 (BIT(0)) -#define DMA2D_OUTFIFO_FULL_L2_CH3_M (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S) -#define DMA2D_OUTFIFO_FULL_L2_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L2_CH3_S 0 -/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L2_CH3 (BIT(1)) -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S 1 -/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L2_CH3 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH3_M (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S) -#define DMA2D_OUTFIFO_CNT_L2_CH3_V 0x0000000FU -#define DMA2D_OUTFIFO_CNT_L2_CH3_S 2 -/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3 (BIT(7)) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S 7 -/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3 (BIT(8)) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S 8 -/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3 (BIT(9)) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S 9 -/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3 (BIT(10)) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S 10 -/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3 (BIT(11)) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S 11 -/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3 (BIT(12)) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S 12 -/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3 (BIT(13)) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S 13 -/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1; - * reserved - */ -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3 (BIT(14)) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S) -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V 0x00000001U -#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S 14 -/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L1_CH3 (BIT(15)) -#define DMA2D_OUTFIFO_FULL_L1_CH3_M (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S) -#define DMA2D_OUTFIFO_FULL_L1_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L1_CH3_S 15 -/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L1_CH3 (BIT(16)) -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S 16 -/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L1_CH3 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH3_M (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S) -#define DMA2D_OUTFIFO_CNT_L1_CH3_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L1_CH3_S 17 -/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_FULL_L3_CH3 (BIT(22)) -#define DMA2D_OUTFIFO_FULL_L3_CH3_M (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S) -#define DMA2D_OUTFIFO_FULL_L3_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_FULL_L3_CH3_S 22 -/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ -#define DMA2D_OUTFIFO_EMPTY_L3_CH3 (BIT(23)) -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S) -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S 23 -/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ -#define DMA2D_OUTFIFO_CNT_L3_CH3 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH3_M (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S) -#define DMA2D_OUTFIFO_CNT_L3_CH3_V 0x0000001FU -#define DMA2D_OUTFIFO_CNT_L3_CH3_S 24 - -/** DMA2D_OUT_PUSH_CH3_REG register - * Configures the tx fifo of channel 3 - */ -#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318) -/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_WDATA_CH3 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH3_M (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S) -#define DMA2D_OUTFIFO_WDATA_CH3_V 0x000003FFU -#define DMA2D_OUTFIFO_WDATA_CH3_S 0 -/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ -#define DMA2D_OUTFIFO_PUSH_CH3 (BIT(10)) -#define DMA2D_OUTFIFO_PUSH_CH3_M (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S) -#define DMA2D_OUTFIFO_PUSH_CH3_V 0x00000001U -#define DMA2D_OUTFIFO_PUSH_CH3_S 10 - -/** DMA2D_OUT_LINK_CONF_CH3_REG register - * Configures the tx descriptor operations of channel 3 - */ -#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c) -/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_STOP_CH3 (BIT(20)) -#define DMA2D_OUTLINK_STOP_CH3_M (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S) -#define DMA2D_OUTLINK_STOP_CH3_V 0x00000001U -#define DMA2D_OUTLINK_STOP_CH3_S 20 -/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ -#define DMA2D_OUTLINK_START_CH3 (BIT(21)) -#define DMA2D_OUTLINK_START_CH3_M (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S) -#define DMA2D_OUTLINK_START_CH3_V 0x00000001U -#define DMA2D_OUTLINK_START_CH3_S 21 -/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ -#define DMA2D_OUTLINK_RESTART_CH3 (BIT(22)) -#define DMA2D_OUTLINK_RESTART_CH3_M (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S) -#define DMA2D_OUTLINK_RESTART_CH3_V 0x00000001U -#define DMA2D_OUTLINK_RESTART_CH3_S 22 -/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ -#define DMA2D_OUTLINK_PARK_CH3 (BIT(23)) -#define DMA2D_OUTLINK_PARK_CH3_M (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S) -#define DMA2D_OUTLINK_PARK_CH3_V 0x00000001U -#define DMA2D_OUTLINK_PARK_CH3_S 23 - -/** DMA2D_OUT_LINK_ADDR_CH3_REG register - * Configures the tx descriptor address of channel 3 - */ -#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320) -/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ -#define DMA2D_OUTLINK_ADDR_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH3_M (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S) -#define DMA2D_OUTLINK_ADDR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_ADDR_CH3_S 0 - -/** DMA2D_OUT_STATE_CH3_REG register - * Represents the working status of the tx descriptor of channel 3 - */ -#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324) -/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ -#define DMA2D_OUTLINK_DSCR_ADDR_CH3 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S) -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V 0x0003FFFFU -#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S 0 -/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ -#define DMA2D_OUT_DSCR_STATE_CH3 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH3_M (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S) -#define DMA2D_OUT_DSCR_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_DSCR_STATE_CH3_S 18 -/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ -#define DMA2D_OUT_STATE_CH3 0x0000000FU -#define DMA2D_OUT_STATE_CH3_M (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S) -#define DMA2D_OUT_STATE_CH3_V 0x0000000FU -#define DMA2D_OUT_STATE_CH3_S 20 -/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_OUT_RESET_AVAIL_CH3 (BIT(24)) -#define DMA2D_OUT_RESET_AVAIL_CH3_M (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S) -#define DMA2D_OUT_RESET_AVAIL_CH3_V 0x00000001U -#define DMA2D_OUT_RESET_AVAIL_CH3_S 24 - -/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328) -/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH3_M (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S) -#define DMA2D_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUT_EOF_DES_ADDR_CH3_S 0 - -/** DMA2D_OUT_DSCR_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c) -/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ -#define DMA2D_OUTLINK_DSCR_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH3_M (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S) -#define DMA2D_OUTLINK_DSCR_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_CH3_S 0 - -/** DMA2D_OUT_DSCR_BF0_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330) -/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ -#define DMA2D_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH3_M (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S) -#define DMA2D_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF0_CH3_S 0 - -/** DMA2D_OUT_DSCR_BF1_CH3_REG register - * Represents the address associated with the outlink descriptor of channel 3 - */ -#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334) -/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ -#define DMA2D_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH3_M (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S) -#define DMA2D_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFFU -#define DMA2D_OUTLINK_DSCR_BF1_CH3_S 0 - -/** DMA2D_OUT_PERI_SEL_CH3_REG register - * Configures the tx peripheral of channel 3 - */ -#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338) -/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ -#define DMA2D_OUT_PERI_SEL_CH3 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH3_M (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S) -#define DMA2D_OUT_PERI_SEL_CH3_V 0x00000007U -#define DMA2D_OUT_PERI_SEL_CH3_S 0 - -/** DMA2D_OUT_ARB_CH3_REG register - * Configures the tx arbiter of channel 3 - */ -#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c) -/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S) -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V 0x0000000FU -#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_CH3 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH3_M (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S) -#define DMA2D_OUT_ARB_PRIORITY_CH3_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_CH3_S 4 -/** DMA2D_OUT_ARB_PRIORITY_H_CH3 : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ -#define DMA2D_OUT_ARB_PRIORITY_H_CH3 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_M (DMA2D_OUT_ARB_PRIORITY_H_CH3_V << DMA2D_OUT_ARB_PRIORITY_H_CH3_S) -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_V 0x00000003U -#define DMA2D_OUT_ARB_PRIORITY_H_CH3_S 6 - -/** DMA2D_OUT_RO_STATUS_CH3_REG register - * Represents the status of the tx reorder module of channel 3 - */ -#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340) -/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ -#define DMA2D_OUTFIFO_RO_CNT_CH3 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH3_M (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S) -#define DMA2D_OUTFIFO_RO_CNT_CH3_V 0x0000003FU -#define DMA2D_OUTFIFO_RO_CNT_CH3_S 0 -/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_OUT_RO_WR_STATE_CH3 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH3_M (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S) -#define DMA2D_OUT_RO_WR_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_RO_WR_STATE_CH3_S 6 -/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_OUT_RO_RD_STATE_CH3 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH3_M (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S) -#define DMA2D_OUT_RO_RD_STATE_CH3_V 0x00000003U -#define DMA2D_OUT_RO_RD_STATE_CH3_S 8 -/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_OUT_PIXEL_BYTE_CH3 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH3_M (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S) -#define DMA2D_OUT_PIXEL_BYTE_CH3_V 0x0000000FU -#define DMA2D_OUT_PIXEL_BYTE_CH3_S 10 -/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S) -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V 0x0000000FU -#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S 14 - -/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register - * Configures the tx color convert of channel 3 - */ -#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348) -/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S) -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V 0x00000003U -#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S 0 -/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3 (BIT(2)) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S) -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V 0x00000001U -#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S 2 -/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S) -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V 0x00000007U -#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S 3 - -/** DMA2D_OUT_SCRAMBLE_CH3_REG register - * Configures the tx scramble of channel 3 - */ -#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c) -/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S) -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V 0x00000007U -#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350) -/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354) -/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_H1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358) -/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c) -/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_M1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360) -/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L0_CH3 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V 0x001FFFFFU -#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S 0 - -/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register - * Configures the tx color convert parameter of channel 3 - */ -#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364) -/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_OUT_COLOR_PARAM_L1_CH3 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S) -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V 0x0FFFFFFFU -#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S 0 - -/** DMA2D_OUT_ETM_CONF_CH3_REG register - * Configures the tx etm of channel 3 - */ -#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368) -/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_EN_CH3 (BIT(0)) -#define DMA2D_OUT_ETM_EN_CH3_M (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S) -#define DMA2D_OUT_ETM_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ETM_EN_CH3_S 0 -/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_OUT_ETM_LOOP_EN_CH3 (BIT(1)) -#define DMA2D_OUT_ETM_LOOP_EN_CH3_M (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S) -#define DMA2D_OUT_ETM_LOOP_EN_CH3_V 0x00000001U -#define DMA2D_OUT_ETM_LOOP_EN_CH3_S 1 -/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_OUT_DSCR_TASK_MAK_CH3 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S) -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V 0x00000003U -#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S 2 - -/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register - * Configures the tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c) -/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S) -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S 0 -/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S) -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V 0x00003FFFU -#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S 14 - -/** DMA2D_IN_CONF0_CH0_REG register - * Configures the rx direction of channel 0 - */ -#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500) -/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH0 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH0_M (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S) -#define DMA2D_IN_MEM_TRANS_EN_CH0_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH0_S 0 -/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH0_M (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S) -#define DMA2D_INDSCR_BURST_EN_CH0_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH0_S 2 -/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH0 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH0_M (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S) -#define DMA2D_IN_ECC_AES_EN_CH0_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH0_S 3 -/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH0 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH0_M (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S) -#define DMA2D_IN_CHECK_OWNER_CH0_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH0_S 4 -/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH0 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH0_M (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S) -#define DMA2D_IN_LOOP_TEST_CH0_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH0_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH0 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH0 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH0_M (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S) -#define DMA2D_IN_DSCR_PORT_EN_CH0_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH0_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH0 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH0_M (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH0_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH0_S 12 -/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH0 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH0_M (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S) -#define DMA2D_IN_REORDER_EN_CH0_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH0_S 16 -/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH0 (BIT(24)) -#define DMA2D_IN_RST_CH0_M (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S) -#define DMA2D_IN_RST_CH0_V 0x00000001U -#define DMA2D_IN_RST_CH0_S 24 -/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH0 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH0_M (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S) -#define DMA2D_IN_CMD_DISABLE_CH0_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH0_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S 26 - -/** DMA2D_IN_INT_RAW_CH0_REG register - * Raw interrupt status of RX channel 0 - */ -#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504) -/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH0_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_RAW_M (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S) -#define DMA2D_IN_DONE_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH0_REG register - * Interrupt enable bits of RX channel 0 - */ -#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508) -/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_ENA_M (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S) -#define DMA2D_IN_DONE_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH0_REG register - * Masked interrupt status of RX channel 0 - */ -#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c) -/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_ST_M (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S) -#define DMA2D_IN_DONE_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH0_REG register - * Interrupt clear bits of RX channel 0 - */ -#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510) -/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH0_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH0_INT_CLR_M (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S) -#define DMA2D_IN_DONE_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH0_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH0_REG register - * Represents the status of the rx fifo of channel 0 - */ -#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514) -/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH0 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH0_M (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S) -#define DMA2D_INFIFO_FULL_L2_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH0_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH0 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH0_M (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S) -#define DMA2D_INFIFO_EMPTY_L2_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH0_S 1 -/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH0 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH0_M (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S) -#define DMA2D_INFIFO_CNT_L2_CH0_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH0_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH0 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH0 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH0 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH0 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH0 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH0 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH0 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH0 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S 14 -/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH0 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH0_M (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S) -#define DMA2D_INFIFO_FULL_L1_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH0_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH0 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH0_M (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S) -#define DMA2D_INFIFO_EMPTY_L1_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH0_S 16 -/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH0 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH0_M (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S) -#define DMA2D_INFIFO_CNT_L1_CH0_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH0_S 17 -/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH0 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH0_M (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S) -#define DMA2D_INFIFO_FULL_L3_CH0_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH0_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH0 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH0_M (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S) -#define DMA2D_INFIFO_EMPTY_L3_CH0_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH0_S 23 -/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH0 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH0_M (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S) -#define DMA2D_INFIFO_CNT_L3_CH0_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH0_S 24 - -/** DMA2D_IN_POP_CH0_REG register - * Configures the rx fifo of channel 0 - */ -#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518) -/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH0 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH0_M (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S) -#define DMA2D_INFIFO_RDATA_CH0_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH0_S 0 -/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH0 (BIT(11)) -#define DMA2D_INFIFO_POP_CH0_M (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S) -#define DMA2D_INFIFO_POP_CH0_V 0x00000001U -#define DMA2D_INFIFO_POP_CH0_S 11 - -/** DMA2D_IN_LINK_CONF_CH0_REG register - * Configures the rx descriptor operations of channel 0 - */ -#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c) -/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH0 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH0_M (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S) -#define DMA2D_INLINK_AUTO_RET_CH0_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH0_S 20 -/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH0 (BIT(21)) -#define DMA2D_INLINK_STOP_CH0_M (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S) -#define DMA2D_INLINK_STOP_CH0_V 0x00000001U -#define DMA2D_INLINK_STOP_CH0_S 21 -/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH0 (BIT(22)) -#define DMA2D_INLINK_START_CH0_M (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S) -#define DMA2D_INLINK_START_CH0_V 0x00000001U -#define DMA2D_INLINK_START_CH0_S 22 -/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH0 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH0_M (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S) -#define DMA2D_INLINK_RESTART_CH0_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH0_S 23 -/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH0 (BIT(24)) -#define DMA2D_INLINK_PARK_CH0_M (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S) -#define DMA2D_INLINK_PARK_CH0_V 0x00000001U -#define DMA2D_INLINK_PARK_CH0_S 24 - -/** DMA2D_IN_LINK_ADDR_CH0_REG register - * Configures the rx descriptor address of channel 0 - */ -#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520) -/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH0_M (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S) -#define DMA2D_INLINK_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH0_S 0 - -/** DMA2D_IN_STATE_CH0_REG register - * Represents the working status of the rx descriptor of channel 0 - */ -#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524) -/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH0 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH0_M (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S) -#define DMA2D_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH0_S 0 -/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH0 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH0_M (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S) -#define DMA2D_IN_DSCR_STATE_CH0_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH0_S 18 -/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH0 0x00000007U -#define DMA2D_IN_STATE_CH0_M (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S) -#define DMA2D_IN_STATE_CH0_V 0x00000007U -#define DMA2D_IN_STATE_CH0_S 20 -/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH0 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH0_M (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S) -#define DMA2D_IN_RESET_AVAIL_CH0_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH0_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S 0 - -/** DMA2D_IN_DSCR_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530) -/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH0_M (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S) -#define DMA2D_INLINK_DSCR_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH0_S 0 - -/** DMA2D_IN_DSCR_BF0_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534) -/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH0_M (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S) -#define DMA2D_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH0_S 0 - -/** DMA2D_IN_DSCR_BF1_CH0_REG register - * Represents the address associated with the inlink descriptor of channel 0 - */ -#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538) -/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH0_M (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S) -#define DMA2D_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH0_S 0 - -/** DMA2D_IN_PERI_SEL_CH0_REG register - * Configures the rx peripheral of channel 0 - */ -#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c) -/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH0 0x00000007U -#define DMA2D_IN_PERI_SEL_CH0_M (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S) -#define DMA2D_IN_PERI_SEL_CH0_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH0_S 0 - -/** DMA2D_IN_ARB_CH0_REG register - * Configures the rx arbiter of channel 0 - */ -#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540) -/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH0 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH0 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH0_M (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH0_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH0 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH0_M (DMA2D_IN_ARB_PRIORITY_H_CH0_V << DMA2D_IN_ARB_PRIORITY_H_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH0_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH0_S 5 - -/** DMA2D_IN_RO_STATUS_CH0_REG register - * Represents the status of the rx reorder module of channel 0 - */ -#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544) -/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH0 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH0_M (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S) -#define DMA2D_INFIFO_RO_CNT_CH0_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH0_S 0 -/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH0 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH0_M (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S) -#define DMA2D_IN_RO_WR_STATE_CH0_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH0_S 5 -/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH0 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH0_M (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S) -#define DMA2D_IN_RO_RD_STATE_CH0_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH0_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH0 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH0_M (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S) -#define DMA2D_IN_PIXEL_BYTE_CH0_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH0_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH0 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH0_REG register - * Configures the rx reorder memory of channel 0 - */ -#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH0 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH0_REG register - * Configures the Rx color convert of channel 0 - */ -#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH0 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S 3 - -/** DMA2D_IN_SCRAMBLE_CH0_REG register - * Configures the rx scramble of channel 0 - */ -#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554) -/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH0_M (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558) -/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH0_M (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c) -/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH0_M (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560) -/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH0_M (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564) -/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH0 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH0_M (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH0_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH0_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH0_REG register - * Configures the rx color convert parameter of channel 0 - */ -#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568) -/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH0 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH0_M (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH0_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH0_S 0 - -/** DMA2D_IN_ETM_CONF_CH0_REG register - * Configures the rx etm of channel 0 - */ -#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c) -/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH0 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH0_M (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S) -#define DMA2D_IN_ETM_EN_CH0_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH0_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH0 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH0_M (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S) -#define DMA2D_IN_ETM_LOOP_EN_CH0_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH0_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH0 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH0_M (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH0_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH0_S 2 - -/** DMA2D_IN_CONF0_CH1_REG register - * Configures the rx direction of channel 1 - */ -#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600) -/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH1 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH1_M (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S) -#define DMA2D_IN_MEM_TRANS_EN_CH1_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH1_S 0 -/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH1_M (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S) -#define DMA2D_INDSCR_BURST_EN_CH1_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH1_S 2 -/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH1 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH1_M (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S) -#define DMA2D_IN_ECC_AES_EN_CH1_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH1_S 3 -/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH1 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH1_M (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S) -#define DMA2D_IN_CHECK_OWNER_CH1_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH1_S 4 -/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH1 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH1_M (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S) -#define DMA2D_IN_LOOP_TEST_CH1_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH1_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH1 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH1 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH1_M (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S) -#define DMA2D_IN_DSCR_PORT_EN_CH1_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH1_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH1 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH1_M (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH1_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH1_S 12 -/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH1 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH1_M (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S) -#define DMA2D_IN_REORDER_EN_CH1_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH1_S 16 -/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH1 (BIT(24)) -#define DMA2D_IN_RST_CH1_M (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S) -#define DMA2D_IN_RST_CH1_V 0x00000001U -#define DMA2D_IN_RST_CH1_S 24 -/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH1 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH1_M (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S) -#define DMA2D_IN_CMD_DISABLE_CH1_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH1_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S 26 - -/** DMA2D_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 1 - */ -#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604) -/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH1_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_RAW_M (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S) -#define DMA2D_IN_DONE_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 1 - */ -#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608) -/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_ENA_M (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S) -#define DMA2D_IN_DONE_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 1 - */ -#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c) -/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_ST_M (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S) -#define DMA2D_IN_DONE_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 1 - */ -#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610) -/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH1_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH1_INT_CLR_M (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S) -#define DMA2D_IN_DONE_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH1_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH1_REG register - * Represents the status of the rx fifo of channel 1 - */ -#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614) -/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH1 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH1_M (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S) -#define DMA2D_INFIFO_FULL_L2_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH1_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH1 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH1_M (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S) -#define DMA2D_INFIFO_EMPTY_L2_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH1_S 1 -/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH1 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH1_M (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S) -#define DMA2D_INFIFO_CNT_L2_CH1_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH1_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH1 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH1 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH1 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH1 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH1 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH1 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH1 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH1 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S 14 -/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH1 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH1_M (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S) -#define DMA2D_INFIFO_FULL_L1_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH1_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH1 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH1_M (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S) -#define DMA2D_INFIFO_EMPTY_L1_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH1_S 16 -/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH1 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH1_M (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S) -#define DMA2D_INFIFO_CNT_L1_CH1_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH1_S 17 -/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH1 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH1_M (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S) -#define DMA2D_INFIFO_FULL_L3_CH1_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH1_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH1 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH1_M (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S) -#define DMA2D_INFIFO_EMPTY_L3_CH1_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH1_S 23 -/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH1 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH1_M (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S) -#define DMA2D_INFIFO_CNT_L3_CH1_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH1_S 24 - -/** DMA2D_IN_POP_CH1_REG register - * Configures the rx fifo of channel 1 - */ -#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618) -/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH1 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH1_M (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S) -#define DMA2D_INFIFO_RDATA_CH1_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH1_S 0 -/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH1 (BIT(11)) -#define DMA2D_INFIFO_POP_CH1_M (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S) -#define DMA2D_INFIFO_POP_CH1_V 0x00000001U -#define DMA2D_INFIFO_POP_CH1_S 11 - -/** DMA2D_IN_LINK_CONF_CH1_REG register - * Configures the rx descriptor operations of channel 1 - */ -#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c) -/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH1 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH1_M (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S) -#define DMA2D_INLINK_AUTO_RET_CH1_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH1_S 20 -/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH1 (BIT(21)) -#define DMA2D_INLINK_STOP_CH1_M (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S) -#define DMA2D_INLINK_STOP_CH1_V 0x00000001U -#define DMA2D_INLINK_STOP_CH1_S 21 -/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH1 (BIT(22)) -#define DMA2D_INLINK_START_CH1_M (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S) -#define DMA2D_INLINK_START_CH1_V 0x00000001U -#define DMA2D_INLINK_START_CH1_S 22 -/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH1 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH1_M (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S) -#define DMA2D_INLINK_RESTART_CH1_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH1_S 23 -/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH1 (BIT(24)) -#define DMA2D_INLINK_PARK_CH1_M (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S) -#define DMA2D_INLINK_PARK_CH1_V 0x00000001U -#define DMA2D_INLINK_PARK_CH1_S 24 - -/** DMA2D_IN_LINK_ADDR_CH1_REG register - * Configures the rx descriptor address of channel 1 - */ -#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620) -/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH1_M (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S) -#define DMA2D_INLINK_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH1_S 0 - -/** DMA2D_IN_STATE_CH1_REG register - * Represents the working status of the rx descriptor of channel 1 - */ -#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624) -/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH1 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH1_M (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S) -#define DMA2D_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH1_S 0 -/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH1 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH1_M (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S) -#define DMA2D_IN_DSCR_STATE_CH1_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH1_S 18 -/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH1 0x00000007U -#define DMA2D_IN_STATE_CH1_M (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S) -#define DMA2D_IN_STATE_CH1_V 0x00000007U -#define DMA2D_IN_STATE_CH1_S 20 -/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH1 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH1_M (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S) -#define DMA2D_IN_RESET_AVAIL_CH1_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH1_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S 0 - -/** DMA2D_IN_DSCR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630) -/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH1_M (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S) -#define DMA2D_INLINK_DSCR_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH1_S 0 - -/** DMA2D_IN_DSCR_BF0_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634) -/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH1_M (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S) -#define DMA2D_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH1_S 0 - -/** DMA2D_IN_DSCR_BF1_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 1 - */ -#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638) -/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH1_M (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S) -#define DMA2D_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH1_S 0 - -/** DMA2D_IN_PERI_SEL_CH1_REG register - * Configures the rx peripheral of channel 1 - */ -#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c) -/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH1 0x00000007U -#define DMA2D_IN_PERI_SEL_CH1_M (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S) -#define DMA2D_IN_PERI_SEL_CH1_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH1_S 0 - -/** DMA2D_IN_ARB_CH1_REG register - * Configures the rx arbiter of channel 1 - */ -#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640) -/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH1 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH1 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH1_M (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH1_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH1 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH1_M (DMA2D_IN_ARB_PRIORITY_H_CH1_V << DMA2D_IN_ARB_PRIORITY_H_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH1_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH1_S 5 - -/** DMA2D_IN_RO_STATUS_CH1_REG register - * Represents the status of the rx reorder module of channel 1 - */ -#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644) -/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH1 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH1_M (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S) -#define DMA2D_INFIFO_RO_CNT_CH1_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH1_S 0 -/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH1 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH1_M (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S) -#define DMA2D_IN_RO_WR_STATE_CH1_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH1_S 5 -/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH1 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH1_M (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S) -#define DMA2D_IN_RO_RD_STATE_CH1_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH1_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH1 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH1_M (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S) -#define DMA2D_IN_PIXEL_BYTE_CH1_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH1_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH1 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH1_REG register - * Configures the rx reorder memory of channel 1 - */ -#define DMA2D_IN_RO_PD_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH1 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_M (DMA2D_IN_RO_RAM_FORCE_PD_CH1_V << DMA2D_IN_RO_RAM_FORCE_PD_CH1_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH1 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_M (DMA2D_IN_RO_RAM_FORCE_PU_CH1_V << DMA2D_IN_RO_RAM_FORCE_PU_CH1_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH1 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH1 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_M (DMA2D_IN_RO_RAM_CLK_FO_CH1_V << DMA2D_IN_RO_RAM_CLK_FO_CH1_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH1_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH1_REG register - * Configures the Rx color convert of channel 1 - */ -#define DMA2D_IN_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x64c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_M (DMA2D_IN_COLOR_3B_PROC_EN_CH1_V << DMA2D_IN_COLOR_3B_PROC_EN_CH1_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH1 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_M (DMA2D_IN_COLOR_INPUT_SEL_CH1_V << DMA2D_IN_COLOR_INPUT_SEL_CH1_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH1_S 3 - -/** DMA2D_IN_SCRAMBLE_CH1_REG register - * Configures the rx scramble of channel 1 - */ -#define DMA2D_IN_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x650) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH1 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x654) -/** DMA2D_IN_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH1_M (DMA2D_IN_COLOR_PARAM_H0_CH1_V << DMA2D_IN_COLOR_PARAM_H0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x658) -/** DMA2D_IN_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH1_M (DMA2D_IN_COLOR_PARAM_H1_CH1_V << DMA2D_IN_COLOR_PARAM_H1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x65c) -/** DMA2D_IN_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH1_M (DMA2D_IN_COLOR_PARAM_M0_CH1_V << DMA2D_IN_COLOR_PARAM_M0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x660) -/** DMA2D_IN_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH1_M (DMA2D_IN_COLOR_PARAM_M1_CH1_V << DMA2D_IN_COLOR_PARAM_M1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x664) -/** DMA2D_IN_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH1 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH1_M (DMA2D_IN_COLOR_PARAM_L0_CH1_V << DMA2D_IN_COLOR_PARAM_L0_CH1_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH1_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH1_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH1_REG register - * Configures the rx color convert parameter of channel 1 - */ -#define DMA2D_IN_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x668) -/** DMA2D_IN_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH1 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH1_M (DMA2D_IN_COLOR_PARAM_L1_CH1_V << DMA2D_IN_COLOR_PARAM_L1_CH1_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH1_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH1_S 0 - -/** DMA2D_IN_ETM_CONF_CH1_REG register - * Configures the rx etm of channel 1 - */ -#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c) -/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH1 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH1_M (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S) -#define DMA2D_IN_ETM_EN_CH1_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH1_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH1 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH1_M (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S) -#define DMA2D_IN_ETM_LOOP_EN_CH1_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH1_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH1 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH1_M (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH1_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH1_S 2 - -/** DMA2D_IN_CONF0_CH2_REG register - * Configures the rx direction of channel 2 - */ -#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700) -/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ -#define DMA2D_IN_MEM_TRANS_EN_CH2 (BIT(0)) -#define DMA2D_IN_MEM_TRANS_EN_CH2_M (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S) -#define DMA2D_IN_MEM_TRANS_EN_CH2_V 0x00000001U -#define DMA2D_IN_MEM_TRANS_EN_CH2_S 0 -/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ -#define DMA2D_INDSCR_BURST_EN_CH2 (BIT(2)) -#define DMA2D_INDSCR_BURST_EN_CH2_M (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S) -#define DMA2D_INDSCR_BURST_EN_CH2_V 0x00000001U -#define DMA2D_INDSCR_BURST_EN_CH2_S 2 -/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ -#define DMA2D_IN_ECC_AES_EN_CH2 (BIT(3)) -#define DMA2D_IN_ECC_AES_EN_CH2_M (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S) -#define DMA2D_IN_ECC_AES_EN_CH2_V 0x00000001U -#define DMA2D_IN_ECC_AES_EN_CH2_S 3 -/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ -#define DMA2D_IN_CHECK_OWNER_CH2 (BIT(4)) -#define DMA2D_IN_CHECK_OWNER_CH2_M (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S) -#define DMA2D_IN_CHECK_OWNER_CH2_V 0x00000001U -#define DMA2D_IN_CHECK_OWNER_CH2_S 4 -/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; - * reserved - */ -#define DMA2D_IN_LOOP_TEST_CH2 (BIT(5)) -#define DMA2D_IN_LOOP_TEST_CH2_M (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S) -#define DMA2D_IN_LOOP_TEST_CH2_V 0x00000001U -#define DMA2D_IN_LOOP_TEST_CH2_S 5 -/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ -#define DMA2D_IN_MEM_BURST_LENGTH_CH2 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S) -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V 0x00000007U -#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S 6 -/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S) -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V 0x00000003U -#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S 9 -/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ -#define DMA2D_IN_DSCR_PORT_EN_CH2 (BIT(11)) -#define DMA2D_IN_DSCR_PORT_EN_CH2_M (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S) -#define DMA2D_IN_DSCR_PORT_EN_CH2_V 0x00000001U -#define DMA2D_IN_DSCR_PORT_EN_CH2_S 11 -/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ -#define DMA2D_IN_PAGE_BOUND_EN_CH2 (BIT(12)) -#define DMA2D_IN_PAGE_BOUND_EN_CH2_M (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S) -#define DMA2D_IN_PAGE_BOUND_EN_CH2_V 0x00000001U -#define DMA2D_IN_PAGE_BOUND_EN_CH2_S 12 -/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ -#define DMA2D_IN_REORDER_EN_CH2 (BIT(16)) -#define DMA2D_IN_REORDER_EN_CH2_M (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S) -#define DMA2D_IN_REORDER_EN_CH2_V 0x00000001U -#define DMA2D_IN_REORDER_EN_CH2_S 16 -/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ -#define DMA2D_IN_RST_CH2 (BIT(24)) -#define DMA2D_IN_RST_CH2_M (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S) -#define DMA2D_IN_RST_CH2_V 0x00000001U -#define DMA2D_IN_RST_CH2_S 24 -/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ -#define DMA2D_IN_CMD_DISABLE_CH2 (BIT(25)) -#define DMA2D_IN_CMD_DISABLE_CH2_M (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S) -#define DMA2D_IN_CMD_DISABLE_CH2_V 0x00000001U -#define DMA2D_IN_CMD_DISABLE_CH2_S 25 -/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S) -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U -#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S 26 - -/** DMA2D_IN_INT_RAW_CH2_REG register - * Raw interrupt status of RX channel 2 - */ -#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704) -/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ -#define DMA2D_IN_DONE_CH2_INT_RAW (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_RAW_M (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S) -#define DMA2D_IN_DONE_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_RAW_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S 13 - -/** DMA2D_IN_INT_ENA_CH2_REG register - * Interrupt enable bits of RX channel 2 - */ -#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708) -/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_ENA (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_ENA_M (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S) -#define DMA2D_IN_DONE_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_ENA_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S 13 - -/** DMA2D_IN_INT_ST_CH2_REG register - * Masked interrupt status of RX channel 2 - */ -#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c) -/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_ST (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_ST_M (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S) -#define DMA2D_IN_DONE_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_ST_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_ST (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_ST (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S 13 - -/** DMA2D_IN_INT_CLR_CH2_REG register - * Interrupt clear bits of RX channel 2 - */ -#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710) -/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ -#define DMA2D_IN_DONE_CH2_INT_CLR (BIT(0)) -#define DMA2D_IN_DONE_CH2_INT_CLR_M (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S) -#define DMA2D_IN_DONE_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DONE_CH2_INT_CLR_S 0 -/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S) -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S 1 -/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S) -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S 2 -/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S 3 -/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S 4 -/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S 5 -/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S 6 -/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S 7 -/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S) -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S 8 -/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S) -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S 9 -/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(10)) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S 10 -/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR (BIT(11)) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S) -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S 11 -/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR (BIT(12)) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S) -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S 12 -/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR (BIT(13)) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S) -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U -#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S 13 - -/** DMA2D_INFIFO_STATUS_CH2_REG register - * Represents the status of the rx fifo of channel 2 - */ -#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714) -/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ -#define DMA2D_INFIFO_FULL_L2_CH2 (BIT(0)) -#define DMA2D_INFIFO_FULL_L2_CH2_M (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S) -#define DMA2D_INFIFO_FULL_L2_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L2_CH2_S 0 -/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ -#define DMA2D_INFIFO_EMPTY_L2_CH2 (BIT(1)) -#define DMA2D_INFIFO_EMPTY_L2_CH2_M (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S) -#define DMA2D_INFIFO_EMPTY_L2_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L2_CH2_S 1 -/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ -#define DMA2D_INFIFO_CNT_L2_CH2 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH2_M (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S) -#define DMA2D_INFIFO_CNT_L2_CH2_V 0x0000000FU -#define DMA2D_INFIFO_CNT_L2_CH2_S 2 -/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_1B_CH2 (BIT(7)) -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S 7 -/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_2B_CH2 (BIT(8)) -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S 8 -/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_3B_CH2 (BIT(9)) -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S 9 -/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_4B_CH2 (BIT(10)) -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S 10 -/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_5B_CH2 (BIT(11)) -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S 11 -/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_6B_CH2 (BIT(12)) -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S 12 -/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_7B_CH2 (BIT(13)) -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S 13 -/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0; - * reserved - */ -#define DMA2D_IN_REMAIN_UNDER_8B_CH2 (BIT(14)) -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S) -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V 0x00000001U -#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S 14 -/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L1_CH2 (BIT(15)) -#define DMA2D_INFIFO_FULL_L1_CH2_M (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S) -#define DMA2D_INFIFO_FULL_L1_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L1_CH2_S 15 -/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L1_CH2 (BIT(16)) -#define DMA2D_INFIFO_EMPTY_L1_CH2_M (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S) -#define DMA2D_INFIFO_EMPTY_L1_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L1_CH2_S 16 -/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L1_CH2 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH2_M (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S) -#define DMA2D_INFIFO_CNT_L1_CH2_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L1_CH2_S 17 -/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ -#define DMA2D_INFIFO_FULL_L3_CH2 (BIT(22)) -#define DMA2D_INFIFO_FULL_L3_CH2_M (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S) -#define DMA2D_INFIFO_FULL_L3_CH2_V 0x00000001U -#define DMA2D_INFIFO_FULL_L3_CH2_S 22 -/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ -#define DMA2D_INFIFO_EMPTY_L3_CH2 (BIT(23)) -#define DMA2D_INFIFO_EMPTY_L3_CH2_M (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S) -#define DMA2D_INFIFO_EMPTY_L3_CH2_V 0x00000001U -#define DMA2D_INFIFO_EMPTY_L3_CH2_S 23 -/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ -#define DMA2D_INFIFO_CNT_L3_CH2 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH2_M (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S) -#define DMA2D_INFIFO_CNT_L3_CH2_V 0x0000001FU -#define DMA2D_INFIFO_CNT_L3_CH2_S 24 - -/** DMA2D_IN_POP_CH2_REG register - * Configures the rx fifo of channel 2 - */ -#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718) -/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_RDATA_CH2 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH2_M (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S) -#define DMA2D_INFIFO_RDATA_CH2_V 0x000007FFU -#define DMA2D_INFIFO_RDATA_CH2_S 0 -/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ -#define DMA2D_INFIFO_POP_CH2 (BIT(11)) -#define DMA2D_INFIFO_POP_CH2_M (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S) -#define DMA2D_INFIFO_POP_CH2_V 0x00000001U -#define DMA2D_INFIFO_POP_CH2_S 11 - -/** DMA2D_IN_LINK_CONF_CH2_REG register - * Configures the rx descriptor operations of channel 2 - */ -#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c) -/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ -#define DMA2D_INLINK_AUTO_RET_CH2 (BIT(20)) -#define DMA2D_INLINK_AUTO_RET_CH2_M (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S) -#define DMA2D_INLINK_AUTO_RET_CH2_V 0x00000001U -#define DMA2D_INLINK_AUTO_RET_CH2_S 20 -/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_STOP_CH2 (BIT(21)) -#define DMA2D_INLINK_STOP_CH2_M (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S) -#define DMA2D_INLINK_STOP_CH2_V 0x00000001U -#define DMA2D_INLINK_STOP_CH2_S 21 -/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ -#define DMA2D_INLINK_START_CH2 (BIT(22)) -#define DMA2D_INLINK_START_CH2_M (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S) -#define DMA2D_INLINK_START_CH2_V 0x00000001U -#define DMA2D_INLINK_START_CH2_S 22 -/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ -#define DMA2D_INLINK_RESTART_CH2 (BIT(23)) -#define DMA2D_INLINK_RESTART_CH2_M (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S) -#define DMA2D_INLINK_RESTART_CH2_V 0x00000001U -#define DMA2D_INLINK_RESTART_CH2_S 23 -/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ -#define DMA2D_INLINK_PARK_CH2 (BIT(24)) -#define DMA2D_INLINK_PARK_CH2_M (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S) -#define DMA2D_INLINK_PARK_CH2_V 0x00000001U -#define DMA2D_INLINK_PARK_CH2_S 24 - -/** DMA2D_IN_LINK_ADDR_CH2_REG register - * Configures the rx descriptor address of channel 2 - */ -#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720) -/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ -#define DMA2D_INLINK_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH2_M (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S) -#define DMA2D_INLINK_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_ADDR_CH2_S 0 - -/** DMA2D_IN_STATE_CH2_REG register - * Represents the working status of the rx descriptor of channel 2 - */ -#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724) -/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ -#define DMA2D_INLINK_DSCR_ADDR_CH2 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH2_M (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S) -#define DMA2D_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU -#define DMA2D_INLINK_DSCR_ADDR_CH2_S 0 -/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ -#define DMA2D_IN_DSCR_STATE_CH2 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH2_M (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S) -#define DMA2D_IN_DSCR_STATE_CH2_V 0x00000003U -#define DMA2D_IN_DSCR_STATE_CH2_S 18 -/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; - * reserved - */ -#define DMA2D_IN_STATE_CH2 0x00000007U -#define DMA2D_IN_STATE_CH2_M (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S) -#define DMA2D_IN_STATE_CH2_V 0x00000007U -#define DMA2D_IN_STATE_CH2_S 20 -/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ -#define DMA2D_IN_RESET_AVAIL_CH2 (BIT(23)) -#define DMA2D_IN_RESET_AVAIL_CH2_M (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S) -#define DMA2D_IN_RESET_AVAIL_CH2_V 0x00000001U -#define DMA2D_IN_RESET_AVAIL_CH2_S 23 - -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728) -/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S) -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c) -/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S) -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU -#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S 0 - -/** DMA2D_IN_DSCR_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730) -/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ -#define DMA2D_INLINK_DSCR_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH2_M (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S) -#define DMA2D_INLINK_DSCR_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_CH2_S 0 - -/** DMA2D_IN_DSCR_BF0_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734) -/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ -#define DMA2D_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH2_M (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S) -#define DMA2D_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF0_CH2_S 0 - -/** DMA2D_IN_DSCR_BF1_CH2_REG register - * Represents the address associated with the inlink descriptor of channel 2 - */ -#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738) -/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ -#define DMA2D_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH2_M (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S) -#define DMA2D_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU -#define DMA2D_INLINK_DSCR_BF1_CH2_S 0 - -/** DMA2D_IN_PERI_SEL_CH2_REG register - * Configures the rx peripheral of channel 2 - */ -#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c) -/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ -#define DMA2D_IN_PERI_SEL_CH2 0x00000007U -#define DMA2D_IN_PERI_SEL_CH2_M (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S) -#define DMA2D_IN_PERI_SEL_CH2_V 0x00000007U -#define DMA2D_IN_PERI_SEL_CH2_S 0 - -/** DMA2D_IN_ARB_CH2_REG register - * Configures the rx arbiter of channel 2 - */ -#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740) -/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ -#define DMA2D_IN_ARB_TOKEN_NUM_CH2 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S) -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V 0x0000000FU -#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_CH2 (BIT(4)) -#define DMA2D_IN_ARB_PRIORITY_CH2_M (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S) -#define DMA2D_IN_ARB_PRIORITY_CH2_V 0x00000001U -#define DMA2D_IN_ARB_PRIORITY_CH2_S 4 -/** DMA2D_IN_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ -#define DMA2D_IN_ARB_PRIORITY_H_CH2 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH2_M (DMA2D_IN_ARB_PRIORITY_H_CH2_V << DMA2D_IN_ARB_PRIORITY_H_CH2_S) -#define DMA2D_IN_ARB_PRIORITY_H_CH2_V 0x00000007U -#define DMA2D_IN_ARB_PRIORITY_H_CH2_S 5 - -/** DMA2D_IN_RO_STATUS_CH2_REG register - * Represents the status of the rx reorder module of channel 2 - */ -#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744) -/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ -#define DMA2D_INFIFO_RO_CNT_CH2 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH2_M (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S) -#define DMA2D_INFIFO_RO_CNT_CH2_V 0x0000001FU -#define DMA2D_INFIFO_RO_CNT_CH2_S 0 -/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ -#define DMA2D_IN_RO_WR_STATE_CH2 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH2_M (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S) -#define DMA2D_IN_RO_WR_STATE_CH2_V 0x00000003U -#define DMA2D_IN_RO_WR_STATE_CH2_S 5 -/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ -#define DMA2D_IN_RO_RD_STATE_CH2 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH2_M (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S) -#define DMA2D_IN_RO_RD_STATE_CH2_V 0x00000003U -#define DMA2D_IN_RO_RD_STATE_CH2_S 7 -/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ -#define DMA2D_IN_PIXEL_BYTE_CH2 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH2_M (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S) -#define DMA2D_IN_PIXEL_BYTE_CH2_V 0x0000000FU -#define DMA2D_IN_PIXEL_BYTE_CH2_S 9 -/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ -#define DMA2D_IN_BURST_BLOCK_NUM_CH2 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S) -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V 0x0000000FU -#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S 13 - -/** DMA2D_IN_RO_PD_CONF_CH2_REG register - * Configures the rx reorder memory of channel 2 - */ -#define DMA2D_IN_RO_PD_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x748) -/** DMA2D_IN_RO_RAM_FORCE_PD_CH2 : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2 (BIT(4)) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_M (DMA2D_IN_RO_RAM_FORCE_PD_CH2_V << DMA2D_IN_RO_RAM_FORCE_PD_CH2_S) -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_S 4 -/** DMA2D_IN_RO_RAM_FORCE_PU_CH2 : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2 (BIT(5)) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_M (DMA2D_IN_RO_RAM_FORCE_PU_CH2_V << DMA2D_IN_RO_RAM_FORCE_PU_CH2_S) -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_S 5 -/** DMA2D_IN_RO_RAM_CLK_FO_CH2 : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ -#define DMA2D_IN_RO_RAM_CLK_FO_CH2 (BIT(6)) -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_M (DMA2D_IN_RO_RAM_CLK_FO_CH2_V << DMA2D_IN_RO_RAM_CLK_FO_CH2_S) -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_V 0x00000001U -#define DMA2D_IN_RO_RAM_CLK_FO_CH2_S 6 - -/** DMA2D_IN_COLOR_CONVERT_CH2_REG register - * Configures the Rx color convert of channel 2 - */ -#define DMA2D_IN_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x74c) -/** DMA2D_IN_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S) -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V 0x00000003U -#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S 0 -/** DMA2D_IN_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2 (BIT(2)) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_M (DMA2D_IN_COLOR_3B_PROC_EN_CH2_V << DMA2D_IN_COLOR_3B_PROC_EN_CH2_S) -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_V 0x00000001U -#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_S 2 -/** DMA2D_IN_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ -#define DMA2D_IN_COLOR_INPUT_SEL_CH2 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_M (DMA2D_IN_COLOR_INPUT_SEL_CH2_V << DMA2D_IN_COLOR_INPUT_SEL_CH2_S) -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_V 0x00000007U -#define DMA2D_IN_COLOR_INPUT_SEL_CH2_S 3 - -/** DMA2D_IN_SCRAMBLE_CH2_REG register - * Configures the rx scramble of channel 2 - */ -#define DMA2D_IN_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x750) -/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_M (DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S) -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S 0 -/** DMA2D_IN_SCRAMBLE_SEL_POST_CH2 : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_M (DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S) -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V 0x00000007U -#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S 3 - -/** DMA2D_IN_COLOR_PARAM0_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x754) -/** DMA2D_IN_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH2_M (DMA2D_IN_COLOR_PARAM_H0_CH2_V << DMA2D_IN_COLOR_PARAM_H0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_H0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_H0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM1_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x758) -/** DMA2D_IN_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_H1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH2_M (DMA2D_IN_COLOR_PARAM_H1_CH2_V << DMA2D_IN_COLOR_PARAM_H1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_H1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_H1_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM2_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x75c) -/** DMA2D_IN_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH2_M (DMA2D_IN_COLOR_PARAM_M0_CH2_V << DMA2D_IN_COLOR_PARAM_M0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_M0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_M0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM3_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x760) -/** DMA2D_IN_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_M1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH2_M (DMA2D_IN_COLOR_PARAM_M1_CH2_V << DMA2D_IN_COLOR_PARAM_M1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_M1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_M1_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM4_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x764) -/** DMA2D_IN_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L0_CH2 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH2_M (DMA2D_IN_COLOR_PARAM_L0_CH2_V << DMA2D_IN_COLOR_PARAM_L0_CH2_S) -#define DMA2D_IN_COLOR_PARAM_L0_CH2_V 0x001FFFFFU -#define DMA2D_IN_COLOR_PARAM_L0_CH2_S 0 - -/** DMA2D_IN_COLOR_PARAM5_CH2_REG register - * Configures the rx color convert parameter of channel 2 - */ -#define DMA2D_IN_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x768) -/** DMA2D_IN_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ -#define DMA2D_IN_COLOR_PARAM_L1_CH2 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH2_M (DMA2D_IN_COLOR_PARAM_L1_CH2_V << DMA2D_IN_COLOR_PARAM_L1_CH2_S) -#define DMA2D_IN_COLOR_PARAM_L1_CH2_V 0x0FFFFFFFU -#define DMA2D_IN_COLOR_PARAM_L1_CH2_S 0 - -/** DMA2D_IN_ETM_CONF_CH2_REG register - * Configures the rx etm of channel 2 - */ -#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c) -/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_EN_CH2 (BIT(0)) -#define DMA2D_IN_ETM_EN_CH2_M (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S) -#define DMA2D_IN_ETM_EN_CH2_V 0x00000001U -#define DMA2D_IN_ETM_EN_CH2_S 0 -/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ -#define DMA2D_IN_ETM_LOOP_EN_CH2 (BIT(1)) -#define DMA2D_IN_ETM_LOOP_EN_CH2_M (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S) -#define DMA2D_IN_ETM_LOOP_EN_CH2_V 0x00000001U -#define DMA2D_IN_ETM_LOOP_EN_CH2_S 1 -/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ -#define DMA2D_IN_DSCR_TASK_MAK_CH2 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH2_M (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S) -#define DMA2D_IN_DSCR_TASK_MAK_CH2_V 0x00000003U -#define DMA2D_IN_DSCR_TASK_MAK_CH2_S 2 - -/** DMA2D_AXI_ERR_REG register - * Represents the status of th axi bus - */ -#define DMA2D_AXI_ERR_REG (DR_REG_DMA2D_BASE + 0xa00) -/** DMA2D_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0; - * AXI read id err cnt - */ -#define DMA2D_RID_ERR_CNT 0x0000000FU -#define DMA2D_RID_ERR_CNT_M (DMA2D_RID_ERR_CNT_V << DMA2D_RID_ERR_CNT_S) -#define DMA2D_RID_ERR_CNT_V 0x0000000FU -#define DMA2D_RID_ERR_CNT_S 0 -/** DMA2D_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0; - * AXI read resp err cnt - */ -#define DMA2D_RRESP_ERR_CNT 0x0000000FU -#define DMA2D_RRESP_ERR_CNT_M (DMA2D_RRESP_ERR_CNT_V << DMA2D_RRESP_ERR_CNT_S) -#define DMA2D_RRESP_ERR_CNT_V 0x0000000FU -#define DMA2D_RRESP_ERR_CNT_S 4 -/** DMA2D_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0; - * AXI write resp err cnt - */ -#define DMA2D_WRESP_ERR_CNT 0x0000000FU -#define DMA2D_WRESP_ERR_CNT_M (DMA2D_WRESP_ERR_CNT_V << DMA2D_WRESP_ERR_CNT_S) -#define DMA2D_WRESP_ERR_CNT_V 0x0000000FU -#define DMA2D_WRESP_ERR_CNT_S 8 -/** DMA2D_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0; - * AXI read cmd fifo remain cmd count - */ -#define DMA2D_RD_FIFO_CNT 0x00000007U -#define DMA2D_RD_FIFO_CNT_M (DMA2D_RD_FIFO_CNT_V << DMA2D_RD_FIFO_CNT_S) -#define DMA2D_RD_FIFO_CNT_V 0x00000007U -#define DMA2D_RD_FIFO_CNT_S 12 -/** DMA2D_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0; - * AXI read backup cmd fifo remain cmd count - */ -#define DMA2D_RD_BAK_FIFO_CNT 0x0000000FU -#define DMA2D_RD_BAK_FIFO_CNT_M (DMA2D_RD_BAK_FIFO_CNT_V << DMA2D_RD_BAK_FIFO_CNT_S) -#define DMA2D_RD_BAK_FIFO_CNT_V 0x0000000FU -#define DMA2D_RD_BAK_FIFO_CNT_S 15 -/** DMA2D_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0; - * AXI write cmd fifo remain cmd count - */ -#define DMA2D_WR_FIFO_CNT 0x00000007U -#define DMA2D_WR_FIFO_CNT_M (DMA2D_WR_FIFO_CNT_V << DMA2D_WR_FIFO_CNT_S) -#define DMA2D_WR_FIFO_CNT_V 0x00000007U -#define DMA2D_WR_FIFO_CNT_S 19 -/** DMA2D_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0; - * AXI write backup cmd fifo remain cmd count - */ -#define DMA2D_WR_BAK_FIFO_CNT 0x0000000FU -#define DMA2D_WR_BAK_FIFO_CNT_M (DMA2D_WR_BAK_FIFO_CNT_V << DMA2D_WR_BAK_FIFO_CNT_S) -#define DMA2D_WR_BAK_FIFO_CNT_V 0x0000000FU -#define DMA2D_WR_BAK_FIFO_CNT_S 22 - -/** DMA2D_RST_CONF_REG register - * Configures the reset of axi - */ -#define DMA2D_RST_CONF_REG (DR_REG_DMA2D_BASE + 0xa04) -/** DMA2D_AXIM_RD_RST : R/W; bitpos: [0]; default: 0; - * Write 1 then write 0 to this bit to reset axi master read data FIFO. - */ -#define DMA2D_AXIM_RD_RST (BIT(0)) -#define DMA2D_AXIM_RD_RST_M (DMA2D_AXIM_RD_RST_V << DMA2D_AXIM_RD_RST_S) -#define DMA2D_AXIM_RD_RST_V 0x00000001U -#define DMA2D_AXIM_RD_RST_S 0 -/** DMA2D_AXIM_WR_RST : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset axi master write data FIFO. - */ -#define DMA2D_AXIM_WR_RST (BIT(1)) -#define DMA2D_AXIM_WR_RST_M (DMA2D_AXIM_WR_RST_V << DMA2D_AXIM_WR_RST_S) -#define DMA2D_AXIM_WR_RST_V 0x00000001U -#define DMA2D_AXIM_WR_RST_S 1 -/** DMA2D_CLK_EN : R/W; bitpos: [2]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ -#define DMA2D_CLK_EN (BIT(2)) -#define DMA2D_CLK_EN_M (DMA2D_CLK_EN_V << DMA2D_CLK_EN_S) -#define DMA2D_CLK_EN_V 0x00000001U -#define DMA2D_CLK_EN_S 2 - -/** DMA2D_INTR_MEM_START_ADDR_REG register - * The start address of accessible address space. - */ -#define DMA2D_INTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa08) -/** DMA2D_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ -#define DMA2D_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_M (DMA2D_ACCESS_INTR_MEM_START_ADDR_V << DMA2D_ACCESS_INTR_MEM_START_ADDR_S) -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_START_ADDR_S 0 - -/** DMA2D_INTR_MEM_END_ADDR_REG register - * The end address of accessible address space. - */ -#define DMA2D_INTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa0c) -/** DMA2D_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ -#define DMA2D_ACCESS_INTR_MEM_END_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_M (DMA2D_ACCESS_INTR_MEM_END_ADDR_V << DMA2D_ACCESS_INTR_MEM_END_ADDR_S) -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_INTR_MEM_END_ADDR_S 0 - -/** DMA2D_EXTR_MEM_START_ADDR_REG register - * The start address of accessible address space. - */ -#define DMA2D_EXTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa10) -/** DMA2D_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_M (DMA2D_ACCESS_EXTR_MEM_START_ADDR_V << DMA2D_ACCESS_EXTR_MEM_START_ADDR_S) -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_S 0 - -/** DMA2D_EXTR_MEM_END_ADDR_REG register - * The end address of accessible address space. - */ -#define DMA2D_EXTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa14) -/** DMA2D_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_M (DMA2D_ACCESS_EXTR_MEM_END_ADDR_V << DMA2D_ACCESS_EXTR_MEM_END_ADDR_S) -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_V 0xFFFFFFFFU -#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_S 0 - -/** DMA2D_OUT_ARB_CONFIG_REG register - * Configures the tx arbiter - */ -#define DMA2D_OUT_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa18) -/** DMA2D_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ -#define DMA2D_OUT_ARB_TIMEOUT_NUM 0x0000FFFFU -#define DMA2D_OUT_ARB_TIMEOUT_NUM_M (DMA2D_OUT_ARB_TIMEOUT_NUM_V << DMA2D_OUT_ARB_TIMEOUT_NUM_S) -#define DMA2D_OUT_ARB_TIMEOUT_NUM_V 0x0000FFFFU -#define DMA2D_OUT_ARB_TIMEOUT_NUM_S 0 -/** DMA2D_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define DMA2D_OUT_WEIGHT_EN (BIT(16)) -#define DMA2D_OUT_WEIGHT_EN_M (DMA2D_OUT_WEIGHT_EN_V << DMA2D_OUT_WEIGHT_EN_S) -#define DMA2D_OUT_WEIGHT_EN_V 0x00000001U -#define DMA2D_OUT_WEIGHT_EN_S 16 - -/** DMA2D_IN_ARB_CONFIG_REG register - * Configures the rx arbiter - */ -#define DMA2D_IN_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa1c) -/** DMA2D_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ -#define DMA2D_IN_ARB_TIMEOUT_NUM 0x0000FFFFU -#define DMA2D_IN_ARB_TIMEOUT_NUM_M (DMA2D_IN_ARB_TIMEOUT_NUM_V << DMA2D_IN_ARB_TIMEOUT_NUM_S) -#define DMA2D_IN_ARB_TIMEOUT_NUM_V 0x0000FFFFU -#define DMA2D_IN_ARB_TIMEOUT_NUM_S 0 -/** DMA2D_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0; - * reserved - */ -#define DMA2D_IN_WEIGHT_EN (BIT(16)) -#define DMA2D_IN_WEIGHT_EN_M (DMA2D_IN_WEIGHT_EN_V << DMA2D_IN_WEIGHT_EN_S) -#define DMA2D_IN_WEIGHT_EN_V 0x00000001U -#define DMA2D_IN_WEIGHT_EN_S 16 - -/** DMA2D_RDN_RESULT_REG register - * reserved - */ -#define DMA2D_RDN_RESULT_REG (DR_REG_DMA2D_BASE + 0xa20) -/** DMA2D_RDN_ENA : R/W; bitpos: [0]; default: 0; - * reserved - */ -#define DMA2D_RDN_ENA (BIT(0)) -#define DMA2D_RDN_ENA_M (DMA2D_RDN_ENA_V << DMA2D_RDN_ENA_S) -#define DMA2D_RDN_ENA_V 0x00000001U -#define DMA2D_RDN_ENA_S 0 -/** DMA2D_RDN_RESULT : RO; bitpos: [1]; default: 0; - * reserved - */ -#define DMA2D_RDN_RESULT (BIT(1)) -#define DMA2D_RDN_RESULT_M (DMA2D_RDN_RESULT_V << DMA2D_RDN_RESULT_S) -#define DMA2D_RDN_RESULT_V 0x00000001U -#define DMA2D_RDN_RESULT_S 1 - -/** DMA2D_RDN_ECO_HIGH_REG register - * reserved - */ -#define DMA2D_RDN_ECO_HIGH_REG (DR_REG_DMA2D_BASE + 0xa24) -/** DMA2D_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; - * The start address of accessible address space. - */ -#define DMA2D_RDN_ECO_HIGH 0xFFFFFFFFU -#define DMA2D_RDN_ECO_HIGH_M (DMA2D_RDN_ECO_HIGH_V << DMA2D_RDN_ECO_HIGH_S) -#define DMA2D_RDN_ECO_HIGH_V 0xFFFFFFFFU -#define DMA2D_RDN_ECO_HIGH_S 0 - -/** DMA2D_RDN_ECO_LOW_REG register - * reserved - */ -#define DMA2D_RDN_ECO_LOW_REG (DR_REG_DMA2D_BASE + 0xa28) -/** DMA2D_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; - * The start address of accessible address space. - */ -#define DMA2D_RDN_ECO_LOW 0xFFFFFFFFU -#define DMA2D_RDN_ECO_LOW_M (DMA2D_RDN_ECO_LOW_V << DMA2D_RDN_ECO_LOW_S) -#define DMA2D_RDN_ECO_LOW_V 0xFFFFFFFFU -#define DMA2D_RDN_ECO_LOW_S 0 - -/** DMA2D_DATE_REG register - * register version. - */ -#define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c) -/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 37822864; - * register version. - */ -#define DMA2D_DATE 0xFFFFFFFFU -#define DMA2D_DATE_M (DMA2D_DATE_V << DMA2D_DATE_S) -#define DMA2D_DATE_V 0xFFFFFFFFU -#define DMA2D_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h deleted file mode 100644 index d637f6ecab..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h +++ /dev/null @@ -1,2085 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of out_conf0_chn register - * Configures the tx direction of channel n - */ -typedef union { - struct { - /** out_auto_wrback_chn : R/W; bitpos: [0]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data pointed by - * outlink descriptor has been received. - */ - uint32_t out_auto_wrback_chn:1; - /** out_eof_mode_chn : R/W; bitpos: [1]; default: 1; - * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is - * generated when data need to read has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_chn:1; - /** outdscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_chn:1; - /** out_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t out_ecc_aes_en_chn:1; - /** out_check_owner_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_chn:1; - /** out_loop_test_chn : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t out_loop_test_chn:1; - /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t out_mem_burst_length_chn:3; - /** out_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0; - * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ - uint32_t out_macro_block_size_chn:2; - /** out_dscr_port_en_chn : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ - uint32_t out_dscr_port_en_chn:1; - /** out_page_bound_en_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI read data don't cross the address boundary which - * define by mem_burst_length - */ - uint32_t out_page_bound_en_chn:1; - uint32_t reserved_13:3; - /** out_reorder_en_chn : R/W; bitpos: [16]; default: 0; - * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ - uint32_t out_reorder_en_chn:1; - uint32_t reserved_17:7; - /** out_rst_chn : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset TX channel - */ - uint32_t out_rst_chn:1; - /** out_cmd_disable_chn : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t out_cmd_disable_chn:1; - /** out_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t out_arb_weight_opt_dis_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} dma2d_out_conf0_chn_reg_t; - -/** Type of out_push_chn register - * Configures the tx fifo of channel n - */ -typedef union { - struct { - /** outfifo_wdata_chn : R/W; bitpos: [9:0]; default: 0; - * This register stores the data that need to be pushed into DMA Tx FIFO. - */ - uint32_t outfifo_wdata_chn:10; - /** outfifo_push_chn : R/W/SC; bitpos: [10]; default: 0; - * Set this bit to push data into DMA Tx FIFO. - */ - uint32_t outfifo_push_chn:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} dma2d_out_push_chn_reg_t; - -/** Type of out_link_conf_chn register - * Configures the tx descriptor operations of channel n - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** outlink_stop_chn : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_chn:1; - /** outlink_start_chn : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_chn:1; - /** outlink_restart_chn : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_chn:1; - /** outlink_park_chn : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_chn:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} dma2d_out_link_conf_chn_reg_t; - -/** Type of out_link_addr_chn register - * Configures the tx descriptor address of channel n - */ -typedef union { - struct { - /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * This register stores the first outlink descriptor's address. - */ - uint32_t outlink_addr_chn:32; - }; - uint32_t val; -} dma2d_out_link_addr_chn_reg_t; - -/** Type of out_arb_chn register - * Configures the tx arbiter of channel n - */ -typedef union { - struct { - /** out_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t out_arb_token_num_chn:4; - /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1; - * Set the priority of channel - */ - uint32_t out_arb_priority_chn:2; - /** out_arb_priority_h_chn : R/W; bitpos: [7:6]; default: 0; - * Set the priority of channel - */ - uint32_t out_arb_priority_h_chn:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} dma2d_out_arb_chn_reg_t; - -/** Type of out_ro_pd_conf_chn register - * Configures the tx reorder memory of channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** out_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ - uint32_t out_ro_ram_force_pd_chn:1; - /** out_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ - uint32_t out_ro_ram_force_pu_chn:1; - /** out_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ - uint32_t out_ro_ram_clk_fo_chn:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} dma2d_out_ro_pd_conf_chn_reg_t; - -/** Type of out_color_convert_chn register - * Configures the tx color convert of channel n - */ -typedef union { - struct { - /** out_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * YUV444 to YUV422 2: output directly - */ - uint32_t out_color_output_sel_chn:2; - /** out_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ - uint32_t out_color_3b_proc_en_chn:1; - /** out_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: RGB565 to RGB888 1: - * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: - * disable color space convert - */ - uint32_t out_color_input_sel_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_out_color_convert_chn_reg_t; - -/** Type of out_scramble_chn register - * Configures the tx scramble of channel n - */ -typedef union { - struct { - /** out_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t out_scramble_sel_pre_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_out_scramble_chn_reg_t; - -/** Type of out_color_param0_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t out_color_param_h0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param0_chn_reg_t; - -/** Type of out_color_param1_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t out_color_param_h1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param1_chn_reg_t; - -/** Type of out_color_param2_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t out_color_param_m0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param2_chn_reg_t; - -/** Type of out_color_param3_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t out_color_param_m1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param3_chn_reg_t; - -/** Type of out_color_param4_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t out_color_param_l0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_out_color_param4_chn_reg_t; - -/** Type of out_color_param5_chn register - * Configures the tx color convert parameter of channel n - */ -typedef union { - struct { - /** out_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t out_color_param_l1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_color_param5_chn_reg_t; - -/** Type of out_etm_conf_chn register - * Configures the tx etm of channel n - */ -typedef union { - struct { - /** out_etm_en_chn : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ - uint32_t out_etm_en_chn:1; - /** out_etm_loop_en_chn : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ - uint32_t out_etm_loop_en_chn:1; - /** out_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ - uint32_t out_dscr_task_mak_chn:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} dma2d_out_etm_conf_chn_reg_t; - -/** Type of out_dscr_port_blk_chn register - * Configures the tx block size in dscr port mode - */ -typedef union { - struct { - /** out_dscr_port_blk_h_chn : R/W; bitpos: [13:0]; default: 18; - * Set the vertical height of tx block size in dscr port mode - */ - uint32_t out_dscr_port_blk_h_chn:14; - /** out_dscr_port_blk_v_chn : R/W; bitpos: [27:14]; default: 18; - * Set the horizontal width of tx block size in dscr port mode - */ - uint32_t out_dscr_port_blk_v_chn:14; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_out_dscr_port_blk_chn_reg_t; - -/** Type of in_conf0_chn register - * Configures the rx direction of channel n - */ -typedef union { - struct { - /** in_mem_trans_en_chn : R/W; bitpos: [0]; default: 0; - * enable memory trans of the same channel - */ - uint32_t in_mem_trans_en_chn:1; - uint32_t reserved_1:1; - /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor - * when accessing SRAM. - */ - uint32_t indscr_burst_en_chn:1; - /** in_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0; - * When access address space is ecc/aes area, this bit should be set to 1. In this - * case, the start address of square should be 16-bit aligned. The width of square - * multiply byte number of one pixel should be 16-bit aligned. - */ - uint32_t in_ecc_aes_en_chn:1; - /** in_check_owner_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_chn:1; - /** in_loop_test_chn : R/W; bitpos: [5]; default: 0; - * reserved - */ - uint32_t in_loop_test_chn:1; - /** in_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 - * bytes 4: 128 bytes - */ - uint32_t in_mem_burst_length_chn:3; - /** in_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0; - * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: - * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link - * descriptor - */ - uint32_t in_macro_block_size_chn:2; - /** in_dscr_port_en_chn : R/W; bitpos: [11]; default: 0; - * Set this bit to 1 to obtain descriptor from IP port - */ - uint32_t in_dscr_port_en_chn:1; - /** in_page_bound_en_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to 1 to make sure AXI write data don't cross the address boundary - * which define by mem_burst_length - */ - uint32_t in_page_bound_en_chn:1; - uint32_t reserved_13:3; - /** in_reorder_en_chn : R/W; bitpos: [16]; default: 0; - * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this - * selection - */ - uint32_t in_reorder_en_chn:1; - uint32_t reserved_17:7; - /** in_rst_chn : R/W; bitpos: [24]; default: 0; - * Write 1 then write 0 to this bit to reset Rx channel - */ - uint32_t in_rst_chn:1; - /** in_cmd_disable_chn : R/W; bitpos: [25]; default: 0; - * Write 1 before reset and write 0 after reset - */ - uint32_t in_cmd_disable_chn:1; - /** in_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0; - * Set this bit to 1 to disable arbiter optimum weight function. - */ - uint32_t in_arb_weight_opt_dis_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} dma2d_in_conf0_chn_reg_t; - -/** Type of in_pop_chn register - * Configures the rx fifo of channel n - */ -typedef union { - struct { - /** infifo_rdata_chn : RO; bitpos: [10:0]; default: 1024; - * This register stores the data popping from DMA Rx FIFO. - */ - uint32_t infifo_rdata_chn:11; - /** infifo_pop_chn : R/W/SC; bitpos: [11]; default: 0; - * Set this bit to pop data from DMA Rx FIFO. - */ - uint32_t infifo_pop_chn:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} dma2d_in_pop_chn_reg_t; - -/** Type of in_link_conf_chn register - * Configures the rx descriptor operations of channel n - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_chn:1; - /** inlink_stop_chn : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_chn:1; - /** inlink_start_chn : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_chn:1; - /** inlink_restart_chn : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_chn:1; - /** inlink_park_chn : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} dma2d_in_link_conf_chn_reg_t; - -/** Type of in_link_addr_chn register - * Configures the rx descriptor address of channel n - */ -typedef union { - struct { - /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * This register stores the first inlink descriptor's address. - */ - uint32_t inlink_addr_chn:32; - }; - uint32_t val; -} dma2d_in_link_addr_chn_reg_t; - -/** Type of in_arb_chn register - * Configures the rx arbiter of channel n - */ -typedef union { - struct { - /** in_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1; - * Set the max number of token count of arbiter - */ - uint32_t in_arb_token_num_chn:4; - /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1; - * Set the priority of channel - */ - uint32_t in_arb_priority_chn:1; - /** in_arb_priority_h_chn : R/W; bitpos: [7:5]; default: 0; - * Set the priority of channel - */ - uint32_t in_arb_priority_h_chn:3; - uint32_t reserved_8:24; - }; - uint32_t val; -} dma2d_in_arb_chn_reg_t; - -/** Type of in_ro_pd_conf_chn register - * Configures the rx reorder memory of channel n - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** in_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0; - * dma reorder ram power down - */ - uint32_t in_ro_ram_force_pd_chn:1; - /** in_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1; - * dma reorder ram power up - */ - uint32_t in_ro_ram_force_pu_chn:1; - /** in_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. - * 0: A gate-clock will be used when accessing the RAM in DMA. - */ - uint32_t in_ro_ram_clk_fo_chn:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} dma2d_in_ro_pd_conf_chn_reg_t; - -/** Type of in_color_convert_chn register - * Configures the Rx color convert of channel n - */ -typedef union { - struct { - /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; - * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 - */ - uint32_t in_color_output_sel_chn:2; - /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; - * Enable generic color convert module between color input & color output, need to - * configure parameter. - */ - uint32_t in_color_3b_proc_en_chn:1; - /** in_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7; - * Set first color convert process and input color type 0: YUV422/420 to YUV444 - * 1: YUV422 2: YUV444/420 7: disable color space convert - */ - uint32_t in_color_input_sel_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_in_color_convert_chn_reg_t; - -/** Type of in_scramble_chn register - * Configures the rx scramble of channel n - */ -typedef union { - struct { - /** in_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0; - * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : - * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t in_scramble_sel_pre_chn:3; - /** in_scramble_sel_post_chn : R/W; bitpos: [5:3]; default: 0; - * Scramble data after color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : BYTE1-0-2 - * 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 - */ - uint32_t in_scramble_sel_post_chn:3; - uint32_t reserved_6:26; - }; - uint32_t val; -} dma2d_in_scramble_chn_reg_t; - -/** Type of in_color_param0_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298; - * Set first 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t in_color_param_h0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param0_chn_reg_t; - -/** Type of in_color_param1_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121; - * Set last 2 parameter of most significant byte of pending 3 bytes - */ - uint32_t in_color_param_h1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param1_chn_reg_t; - -/** Type of in_color_param2_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050; - * Set first 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t in_color_param_m0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param2_chn_reg_t; - -/** Type of in_color_param3_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784; - * Set last 2 parameter of midium significant byte of pending 3 bytes - */ - uint32_t in_color_param_m1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param3_chn_reg_t; - -/** Type of in_color_param4_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682; - * Set first 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t in_color_param_l0_chn:21; - uint32_t reserved_21:11; - }; - uint32_t val; -} dma2d_in_color_param4_chn_reg_t; - -/** Type of in_color_param5_chn register - * Configures the rx color convert parameter of channel n - */ -typedef union { - struct { - /** in_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392; - * Set last 2 parameter of least significant byte of pending 3 bytes - */ - uint32_t in_color_param_l1_chn:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} dma2d_in_color_param5_chn_reg_t; - -/** Type of in_etm_conf_chn register - * Configures the rx etm of channel n - */ -typedef union { - struct { - /** in_etm_en_chn : R/W; bitpos: [0]; default: 0; - * Configures the enable of the etm function, 1 is enable. - */ - uint32_t in_etm_en_chn:1; - /** in_etm_loop_en_chn : R/W; bitpos: [1]; default: 0; - * Configures the enable of the descriptors loop etm function, 1 is enable. - */ - uint32_t in_etm_loop_en_chn:1; - /** in_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1; - * Configures the maximum number of cacheable descriptors. - */ - uint32_t in_dscr_task_mak_chn:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} dma2d_in_etm_conf_chn_reg_t; - -/** Type of rst_conf register - * Configures the reset of axi - */ -typedef union { - struct { - /** axim_rd_rst : R/W; bitpos: [0]; default: 0; - * Write 1 then write 0 to this bit to reset axi master read data FIFO. - */ - uint32_t axim_rd_rst:1; - /** axim_wr_rst : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset axi master write data FIFO. - */ - uint32_t axim_wr_rst:1; - /** clk_en : R/W; bitpos: [2]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ - uint32_t clk_en:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_rst_conf_reg_t; - -/** Type of intr_mem_start_addr register - * The start address of accessible address space. - */ -typedef union { - struct { - /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_intr_mem_start_addr:32; - }; - uint32_t val; -} dma2d_intr_mem_start_addr_reg_t; - -/** Type of intr_mem_end_addr register - * The end address of accessible address space. - */ -typedef union { - struct { - /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_intr_mem_end_addr:32; - }; - uint32_t val; -} dma2d_intr_mem_end_addr_reg_t; - -/** Type of extr_mem_start_addr register - * The start address of accessible address space. - */ -typedef union { - struct { - /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944; - * The start address of accessible address space. - */ - uint32_t access_extr_mem_start_addr:32; - }; - uint32_t val; -} dma2d_extr_mem_start_addr_reg_t; - -/** Type of extr_mem_end_addr register - * The end address of accessible address space. - */ -typedef union { - struct { - /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103; - * The end address of accessible address space. The access address beyond this range - * would lead to descriptor error. - */ - uint32_t access_extr_mem_end_addr:32; - }; - uint32_t val; -} dma2d_extr_mem_end_addr_reg_t; - -/** Type of out_arb_config register - * Configures the tx arbiter - */ -typedef union { - struct { - /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ - uint32_t out_arb_timeout_num:16; - /** out_weight_en : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t out_weight_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_out_arb_config_reg_t; - -/** Type of in_arb_config register - * Configures the rx arbiter - */ -typedef union { - struct { - /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0; - * Set the max number of timeout count of arbiter - */ - uint32_t in_arb_timeout_num:16; - /** in_weight_en : R/W; bitpos: [16]; default: 0; - * reserved - */ - uint32_t in_weight_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_in_arb_config_reg_t; - -/** Type of rdn_result register - * reserved - */ -typedef union { - struct { - /** rdn_ena : R/W; bitpos: [0]; default: 0; - * reserved - */ - uint32_t rdn_ena:1; - /** rdn_result : RO; bitpos: [1]; default: 0; - * reserved - */ - uint32_t rdn_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} dma2d_rdn_result_reg_t; - -/** Type of rdn_eco_high register - * reserved - */ -typedef union { - struct { - /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * The start address of accessible address space. - */ - uint32_t rdn_eco_high:32; - }; - uint32_t val; -} dma2d_rdn_eco_high_reg_t; - -/** Type of rdn_eco_low register - * reserved - */ -typedef union { - struct { - /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; - * The start address of accessible address space. - */ - uint32_t rdn_eco_low:32; - }; - uint32_t val; -} dma2d_rdn_eco_low_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of out_int_raw_chn register - * Raw interrupt status of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. - */ - uint32_t out_done_chn_int_raw:1; - /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. - */ - uint32_t out_eof_chn_int_raw:1; - /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink descriptor error, - * including owner error, the second and third word error of outlink descriptor for Tx - * channel 0. - */ - uint32_t out_dscr_err_chn_int_raw:1; - /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a outlink - * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. - */ - uint32_t out_total_eof_chn_int_raw:1; - /** outfifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l1_chn_int_raw:1; - /** outfifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l1_chn_int_raw:1; - /** outfifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l2_chn_int_raw:1; - /** outfifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l2_chn_int_raw:1; - /** outfifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo is overflow. - */ - uint32_t outfifo_ovf_l3_chn_int_raw:1; - /** outfifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo is underflow. - */ - uint32_t outfifo_udf_l3_chn_int_raw:1; - /** outfifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ - uint32_t outfifo_ro_ovf_chn_int_raw:1; - /** outfifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ - uint32_t outfifo_ro_udf_chn_int_raw:1; - /** out_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t out_dscr_task_ovf_chn_int_raw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_raw_chn_reg_t; - -/** Type of out_int_ena_chn register - * Interrupt enable bits of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_ena:1; - /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_ena:1; - /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_ena:1; - /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_ena:1; - /** outfifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_ena:1; - /** outfifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_ena:1; - /** outfifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_ena:1; - /** outfifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_ena:1; - /** outfifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_ena:1; - /** outfifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_ena:1; - /** outfifo_ro_ovf_chn_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_ena:1; - /** outfifo_ro_udf_chn_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_ena:1; - /** out_dscr_task_ovf_chn_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_ena:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_ena_chn_reg_t; - -/** Type of out_int_st_chn register - * Masked interrupt status of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_st:1; - /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_st:1; - /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_st:1; - /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_st:1; - /** outfifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_st:1; - /** outfifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_st:1; - /** outfifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_st:1; - /** outfifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_st:1; - /** outfifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_st:1; - /** outfifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_st:1; - /** outfifo_ro_ovf_chn_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_st:1; - /** outfifo_ro_udf_chn_int_st : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_st:1; - /** out_dscr_task_ovf_chn_int_st : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_st:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_st_chn_reg_t; - -/** Type of out_int_clr_chn register - * Interrupt clear bits of TX channel n - */ -typedef union { - struct { - /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - uint32_t out_done_chn_int_clr:1; - /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - uint32_t out_eof_chn_int_clr:1; - /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - uint32_t out_dscr_err_chn_int_clr:1; - /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - uint32_t out_total_eof_chn_int_clr:1; - /** outfifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l1_chn_int_clr:1; - /** outfifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t outfifo_udf_l1_chn_int_clr:1; - /** outfifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l2_chn_int_clr:1; - /** outfifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t outfifo_udf_l2_chn_int_clr:1; - /** outfifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t outfifo_ovf_l3_chn_int_clr:1; - /** outfifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t outfifo_udf_l3_chn_int_clr:1; - /** outfifo_ro_ovf_chn_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t outfifo_ro_ovf_chn_int_clr:1; - /** outfifo_ro_udf_chn_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t outfifo_ro_udf_chn_int_clr:1; - /** out_dscr_task_ovf_chn_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t out_dscr_task_ovf_chn_int_clr:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} dma2d_out_int_clr_chn_reg_t; - -/** Type of in_int_raw_chn register - * Raw interrupt status of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been transmitted to peripherals for Rx channel 0. - */ - uint32_t in_done_chn_int_raw:1; - /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and no data error is detected for Rx channel 0. - */ - uint32_t in_suc_eof_chn_int_raw:1; - /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received and data error is detected - */ - uint32_t in_err_eof_chn_int_raw:1; - /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink descriptor error, - * including owner error, the second and third word error of inlink descriptor for Rx - * channel 0. - */ - uint32_t in_dscr_err_chn_int_raw:1; - /** infifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l1_chn_int_raw:1; - /** infifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l1_chn_int_raw:1; - /** infifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l2_chn_int_raw:1; - /** infifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l2_chn_int_raw:1; - /** infifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - */ - uint32_t infifo_ovf_l3_chn_int_raw:1; - /** infifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - */ - uint32_t infifo_udf_l3_chn_int_raw:1; - /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when the last descriptor is done but fifo - * also remain data. - */ - uint32_t in_dscr_empty_chn_int_raw:1; - /** infifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is overflow. - */ - uint32_t infifo_ro_ovf_chn_int_raw:1; - /** infifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw interrupt bit turns to high level when reorder fifo is underflow. - */ - uint32_t infifo_ro_udf_chn_int_raw:1; - /** in_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - */ - uint32_t in_dscr_task_ovf_chn_int_raw:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_raw_chn_reg_t; - -/** Type of in_int_ena_chn register - * Interrupt enable bits of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_ena:1; - /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_ena:1; - /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_ena:1; - /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_ena:1; - /** infifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_ena:1; - /** infifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_ena:1; - /** infifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_ena:1; - /** infifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_ena:1; - /** infifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_ena:1; - /** infifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_ena:1; - /** in_dscr_empty_chn_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_ena:1; - /** infifo_ro_ovf_chn_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_ena:1; - /** infifo_ro_udf_chn_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_ena:1; - /** in_dscr_task_ovf_chn_int_ena : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_ena:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_ena_chn_reg_t; - -/** Type of in_int_st_chn register - * Masked interrupt status of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_st:1; - /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_st:1; - /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_st:1; - /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_st:1; - /** infifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_st:1; - /** infifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_st:1; - /** infifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_st:1; - /** infifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_st:1; - /** infifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_st:1; - /** infifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_st:1; - /** in_dscr_empty_chn_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_st:1; - /** infifo_ro_ovf_chn_int_st : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_st:1; - /** infifo_ro_udf_chn_int_st : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_st:1; - /** in_dscr_task_ovf_chn_int_st : RO; bitpos: [13]; default: 0; - * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_st:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_st_chn_reg_t; - -/** Type of in_int_clr_chn register - * Interrupt clear bits of RX channel n - */ -typedef union { - struct { - /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - uint32_t in_done_chn_int_clr:1; - /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - uint32_t in_suc_eof_chn_int_clr:1; - /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - uint32_t in_err_eof_chn_int_clr:1; - /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - */ - uint32_t in_dscr_err_chn_int_clr:1; - /** infifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - uint32_t infifo_ovf_l1_chn_int_clr:1; - /** infifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - uint32_t infifo_udf_l1_chn_int_clr:1; - /** infifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - */ - uint32_t infifo_ovf_l2_chn_int_clr:1; - /** infifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - */ - uint32_t infifo_udf_l2_chn_int_clr:1; - /** infifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - */ - uint32_t infifo_ovf_l3_chn_int_clr:1; - /** infifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - */ - uint32_t infifo_udf_l3_chn_int_clr:1; - /** in_dscr_empty_chn_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - uint32_t in_dscr_empty_chn_int_clr:1; - /** infifo_ro_ovf_chn_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. - */ - uint32_t infifo_ro_ovf_chn_int_clr:1; - /** infifo_ro_udf_chn_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. - */ - uint32_t infifo_ro_udf_chn_int_clr:1; - /** in_dscr_task_ovf_chn_int_clr : WT; bitpos: [13]; default: 0; - * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - */ - uint32_t in_dscr_task_ovf_chn_int_clr:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} dma2d_in_int_clr_chn_reg_t; - - -/** Group: Status Registers */ -/** Type of outfifo_status_chn register - * Represents the status of the tx fifo of channel n - */ -typedef union { - struct { - /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l2_chn:1; - /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l2_chn:1; - /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l2_chn:4; - uint32_t reserved_6:1; - /** out_remain_under_1b_chn : RO; bitpos: [7]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_chn:1; - /** out_remain_under_2b_chn : RO; bitpos: [8]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_chn:1; - /** out_remain_under_3b_chn : RO; bitpos: [9]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_chn:1; - /** out_remain_under_4b_chn : RO; bitpos: [10]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_chn:1; - /** out_remain_under_5b_chn : RO; bitpos: [11]; default: 1; - * reserved - */ - uint32_t out_remain_under_5b_chn:1; - /** out_remain_under_6b_chn : RO; bitpos: [12]; default: 1; - * reserved - */ - uint32_t out_remain_under_6b_chn:1; - /** out_remain_under_7b_chn : RO; bitpos: [13]; default: 1; - * reserved - */ - uint32_t out_remain_under_7b_chn:1; - /** out_remain_under_8b_chn : RO; bitpos: [14]; default: 1; - * reserved - */ - uint32_t out_remain_under_8b_chn:1; - /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l1_chn:1; - /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l1_chn:1; - /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l1_chn:5; - /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_l3_chn:1; - /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_l3_chn:1; - /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_l3_chn:5; - uint32_t reserved_29:3; - }; - uint32_t val; -} dma2d_outfifo_status_chn_reg_t; - -/** Type of out_state_chn register - * Represents the working status of the tx descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_chn:18; - /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * This register stores the current descriptor state machine state. - */ - uint32_t out_dscr_state_chn:2; - /** out_state_chn : RO; bitpos: [23:20]; default: 0; - * This register stores the current control module state machine state. - */ - uint32_t out_state_chn:4; - /** out_reset_avail_chn : RO; bitpos: [24]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t out_reset_avail_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} dma2d_out_state_chn_reg_t; - -/** Type of out_eof_des_addr_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_out_eof_des_addr_chn_reg_t; - -/** Type of out_dscr_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the next outlink descriptor address y. - */ - uint32_t outlink_dscr_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_chn_reg_t; - -/** Type of out_dscr_bf0_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor's next address y-1. - */ - uint32_t outlink_dscr_bf0_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_bf0_chn_reg_t; - -/** Type of out_dscr_bf1_chn register - * Represents the address associated with the outlink descriptor of channel n - */ -typedef union { - struct { - /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last outlink descriptor's next address y-2. - */ - uint32_t outlink_dscr_bf1_chn:32; - }; - uint32_t val; -} dma2d_out_dscr_bf1_chn_reg_t; - -/** Type of out_ro_status_chn register - * Represents the status of the tx reorder module of channel n - */ -typedef union { - struct { - /** outfifo_ro_cnt_chn : RO; bitpos: [5:0]; default: 0; - * The register stores the byte number of the data in color convert Tx FIFO for - * channel 0. - */ - uint32_t outfifo_ro_cnt_chn:6; - /** out_ro_wr_state_chn : RO; bitpos: [7:6]; default: 0; - * The register stores the state of read ram of reorder - */ - uint32_t out_ro_wr_state_chn:2; - /** out_ro_rd_state_chn : RO; bitpos: [9:8]; default: 0; - * The register stores the state of write ram of reorder - */ - uint32_t out_ro_rd_state_chn:2; - /** out_pixel_byte_chn : RO; bitpos: [13:10]; default: 0; - * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ - uint32_t out_pixel_byte_chn:4; - /** out_burst_block_num_chn : RO; bitpos: [17:14]; default: 0; - * the number of macro blocks contained in a burst of data at TX channel - */ - uint32_t out_burst_block_num_chn:4; - uint32_t reserved_18:14; - }; - uint32_t val; -} dma2d_out_ro_status_chn_reg_t; - -/** Type of infifo_status_chn register - * Represents the status of the rx fifo of channel n - */ -typedef union { - struct { - /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. - */ - uint32_t infifo_full_l2_chn:1; - /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. - */ - uint32_t infifo_empty_l2_chn:1; - /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. - */ - uint32_t infifo_cnt_l2_chn:4; - uint32_t reserved_6:1; - /** in_remain_under_1b_chn : RO; bitpos: [7]; default: 0; - * reserved - */ - uint32_t in_remain_under_1b_chn:1; - /** in_remain_under_2b_chn : RO; bitpos: [8]; default: 0; - * reserved - */ - uint32_t in_remain_under_2b_chn:1; - /** in_remain_under_3b_chn : RO; bitpos: [9]; default: 0; - * reserved - */ - uint32_t in_remain_under_3b_chn:1; - /** in_remain_under_4b_chn : RO; bitpos: [10]; default: 0; - * reserved - */ - uint32_t in_remain_under_4b_chn:1; - /** in_remain_under_5b_chn : RO; bitpos: [11]; default: 0; - * reserved - */ - uint32_t in_remain_under_5b_chn:1; - /** in_remain_under_6b_chn : RO; bitpos: [12]; default: 0; - * reserved - */ - uint32_t in_remain_under_6b_chn:1; - /** in_remain_under_7b_chn : RO; bitpos: [13]; default: 0; - * reserved - */ - uint32_t in_remain_under_7b_chn:1; - /** in_remain_under_8b_chn : RO; bitpos: [14]; default: 0; - * reserved - */ - uint32_t in_remain_under_8b_chn:1; - /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ - uint32_t infifo_full_l1_chn:1; - /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ - uint32_t infifo_empty_l1_chn:1; - /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ - uint32_t infifo_cnt_l1_chn:5; - /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Rx FIFO full signal for Rx channel 0. - */ - uint32_t infifo_full_l3_chn:1; - /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Rx FIFO empty signal for Rx channel 0. - */ - uint32_t infifo_empty_l3_chn:1; - /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel 0. - */ - uint32_t infifo_cnt_l3_chn:5; - uint32_t reserved_29:3; - }; - uint32_t val; -} dma2d_infifo_status_chn_reg_t; - -/** Type of in_state_chn register - * Represents the working status of the rx descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_chn:18; - /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_chn:2; - /** in_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t in_state_chn:3; - /** in_reset_avail_chn : RO; bitpos: [23]; default: 1; - * This register indicate that if the channel reset is safety. - */ - uint32_t in_reset_avail_chn:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} dma2d_in_state_chn_reg_t; - -/** Type of in_suc_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_in_suc_eof_des_addr_chn_reg_t; - -/** Type of in_err_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. - */ - uint32_t in_err_eof_des_addr_chn:32; - }; - uint32_t val; -} dma2d_in_err_eof_des_addr_chn_reg_t; - -/** Type of in_dscr_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the next inlink descriptor address x. - */ - uint32_t inlink_dscr_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_chn_reg_t; - -/** Type of in_dscr_bf0_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor's next address x-1. - */ - uint32_t inlink_dscr_bf0_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_bf0_chn_reg_t; - -/** Type of in_dscr_bf1_chn register - * Represents the address associated with the inlink descriptor of channel n - */ -typedef union { - struct { - /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor's next address x-2. - */ - uint32_t inlink_dscr_bf1_chn:32; - }; - uint32_t val; -} dma2d_in_dscr_bf1_chn_reg_t; - -/** Type of in_ro_status_chn register - * Represents the status of the rx reorder module of channel n - */ -typedef union { - struct { - /** infifo_ro_cnt_chn : RO; bitpos: [4:0]; default: 0; - * The register stores the byte number of the data in color convert Rx FIFO for - * channel 0. - */ - uint32_t infifo_ro_cnt_chn:5; - /** in_ro_wr_state_chn : RO; bitpos: [6:5]; default: 0; - * The register stores the state of read ram of reorder - */ - uint32_t in_ro_wr_state_chn:2; - /** in_ro_rd_state_chn : RO; bitpos: [8:7]; default: 0; - * The register stores the state of write ram of reorder - */ - uint32_t in_ro_rd_state_chn:2; - /** in_pixel_byte_chn : RO; bitpos: [12:9]; default: 0; - * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes - * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - */ - uint32_t in_pixel_byte_chn:4; - /** in_burst_block_num_chn : RO; bitpos: [16:13]; default: 0; - * the number of macro blocks contained in a burst of data at RX channel - */ - uint32_t in_burst_block_num_chn:4; - uint32_t reserved_17:15; - }; - uint32_t val; -} dma2d_in_ro_status_chn_reg_t; - -/** Type of axi_err register - * Represents the status of th axi bus - */ -typedef union { - struct { - /** rid_err_cnt : RO; bitpos: [3:0]; default: 0; - * AXI read id err cnt - */ - uint32_t rid_err_cnt:4; - /** rresp_err_cnt : RO; bitpos: [7:4]; default: 0; - * AXI read resp err cnt - */ - uint32_t rresp_err_cnt:4; - /** wresp_err_cnt : RO; bitpos: [11:8]; default: 0; - * AXI write resp err cnt - */ - uint32_t wresp_err_cnt:4; - /** rd_fifo_cnt : RO; bitpos: [14:12]; default: 0; - * AXI read cmd fifo remain cmd count - */ - uint32_t rd_fifo_cnt:3; - /** rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0; - * AXI read backup cmd fifo remain cmd count - */ - uint32_t rd_bak_fifo_cnt:4; - /** wr_fifo_cnt : RO; bitpos: [21:19]; default: 0; - * AXI write cmd fifo remain cmd count - */ - uint32_t wr_fifo_cnt:3; - /** wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0; - * AXI write backup cmd fifo remain cmd count - */ - uint32_t wr_bak_fifo_cnt:4; - uint32_t reserved_26:6; - }; - uint32_t val; -} dma2d_axi_err_reg_t; - -/** Type of date register - * register version. - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 37822864; - * register version. - */ - uint32_t date:32; - }; - uint32_t val; -} dma2d_date_reg_t; - - -/** Group: Peripheral Select Registers */ -/** Type of out_peri_sel_chn register - * Configures the tx peripheral of channel n - */ -typedef union { - struct { - /** out_peri_sel_chn : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Tx channel 0: jpeg 1: - * display-1 2: display-2 3: display-3 7: no choose - */ - uint32_t out_peri_sel_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_out_peri_sel_chn_reg_t; - -/** Type of in_peri_sel_chn register - * Configures the rx peripheral of channel n - */ -typedef union { - struct { - /** in_peri_sel_chn : R/W; bitpos: [2:0]; default: 7; - * This register is used to select peripheral for Rx channel 0: jpeg 1: - * display-1 2: display-2 7: no choose - */ - uint32_t in_peri_sel_chn:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} dma2d_in_peri_sel_chn_reg_t; - - -typedef struct { - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch0; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch0; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch0; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch0; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch0; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch0; - volatile dma2d_out_push_chn_reg_t out_push_ch0; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch0; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch0; - volatile dma2d_out_state_chn_reg_t out_state_ch0; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch0; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch0; - volatile dma2d_out_arb_chn_reg_t out_arb_ch0; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch0; - volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf_ch0; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch0; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch0; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch0; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch0; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch0; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch0; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch0; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch0; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch0; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch0; - uint32_t reserved_070[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch1; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch1; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch1; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch1; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch1; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch1; - volatile dma2d_out_push_chn_reg_t out_push_ch1; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch1; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch1; - volatile dma2d_out_state_chn_reg_t out_state_ch1; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch1; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch1; - volatile dma2d_out_arb_chn_reg_t out_arb_ch1; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch1; - uint32_t reserved_144; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch1; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch1; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch1; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch1; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch1; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch1; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch1; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch1; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch1; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch1; - uint32_t reserved_170[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch2; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch2; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch2; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch2; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch2; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch2; - volatile dma2d_out_push_chn_reg_t out_push_ch2; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch2; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch2; - volatile dma2d_out_state_chn_reg_t out_state_ch2; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch2; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch2; - volatile dma2d_out_arb_chn_reg_t out_arb_ch2; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch2; - uint32_t reserved_244; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch2; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch2; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch2; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch2; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch2; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch2; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch2; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch2; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch2; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch2; - uint32_t reserved_270[36]; - volatile dma2d_out_conf0_chn_reg_t out_conf0_ch3; - volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch3; - volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch3; - volatile dma2d_out_int_st_chn_reg_t out_int_st_ch3; - volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch3; - volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch3; - volatile dma2d_out_push_chn_reg_t out_push_ch3; - volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch3; - volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch3; - volatile dma2d_out_state_chn_reg_t out_state_ch3; - volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch3; - volatile dma2d_out_dscr_chn_reg_t out_dscr_ch3; - volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch3; - volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch3; - volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch3; - volatile dma2d_out_arb_chn_reg_t out_arb_ch3; - volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch3; - uint32_t reserved_344; - volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch3; - volatile dma2d_out_scramble_chn_reg_t out_scramble_ch3; - volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch3; - volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch3; - volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch3; - volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch3; - volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch3; - volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch3; - volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch3; - volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch3; - uint32_t reserved_370[100]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch0; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch0; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch0; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch0; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch0; - volatile dma2d_in_pop_chn_reg_t in_pop_ch0; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch0; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch0; - volatile dma2d_in_state_chn_reg_t in_state_ch0; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch0; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch0; - volatile dma2d_in_arb_chn_reg_t in_arb_ch0; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch0; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch0; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch0; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch0; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch0; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch0; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch0; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch0; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch0; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch0; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch0; - uint32_t reserved_570[36]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch1; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch1; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch1; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch1; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch1; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch1; - volatile dma2d_in_pop_chn_reg_t in_pop_ch1; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch1; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch1; - volatile dma2d_in_state_chn_reg_t in_state_ch1; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch1; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch1; - volatile dma2d_in_arb_chn_reg_t in_arb_ch1; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch1; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch1; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch1; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch1; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch1; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch1; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch1; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch1; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch1; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch1; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch1; - uint32_t reserved_670[36]; - volatile dma2d_in_conf0_chn_reg_t in_conf0_ch2; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch2; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch2; - volatile dma2d_in_int_st_chn_reg_t in_int_st_ch2; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch2; - volatile dma2d_infifo_status_chn_reg_t infifo_status_ch2; - volatile dma2d_in_pop_chn_reg_t in_pop_ch2; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch2; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch2; - volatile dma2d_in_state_chn_reg_t in_state_ch2; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; - volatile dma2d_in_dscr_chn_reg_t in_dscr_ch2; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch2; - volatile dma2d_in_arb_chn_reg_t in_arb_ch2; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch2; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch2; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch2; - volatile dma2d_in_scramble_chn_reg_t in_scramble_ch2; - volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch2; - volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch2; - volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch2; - volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch2; - volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch2; - volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch2; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch2; - uint32_t reserved_770[164]; - volatile dma2d_axi_err_reg_t axi_err; - volatile dma2d_rst_conf_reg_t rst_conf; - volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr; - volatile dma2d_intr_mem_end_addr_reg_t intr_mem_end_addr; - volatile dma2d_extr_mem_start_addr_reg_t extr_mem_start_addr; - volatile dma2d_extr_mem_end_addr_reg_t extr_mem_end_addr; - volatile dma2d_out_arb_config_reg_t out_arb_config; - volatile dma2d_in_arb_config_reg_t in_arb_config; - volatile dma2d_rdn_result_reg_t rdn_result; - volatile dma2d_rdn_eco_high_reg_t rdn_eco_high; - volatile dma2d_rdn_eco_low_reg_t rdn_eco_low; - volatile dma2d_date_reg_t date; -} dma2d_dev_t; - -extern dma2d_dev_t DMA2D; - -#ifndef __cplusplus -_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h index b16c0654e9..861ee70e05 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h @@ -11,8 +11,6 @@ extern "C" { #endif -//TODO: IDF-13427 - /** DMA2D_OUT_CONF0_CH0_REG register * Configures the tx direction of channel 0 */ @@ -811,12 +809,12 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH0 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH0 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH0_M (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S) -#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH0_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH0_S 4 /** DMA2D_OUT_RO_STATUS_CH0_REG register @@ -1049,7 +1047,7 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S 14 /** DMA2D_OUT_CONF0_CH1_REG register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel 1 */ #define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100) /** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0; @@ -1162,7 +1160,7 @@ extern "C" { #define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S 26 /** DMA2D_OUT_INT_RAW_CH1_REG register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel 1 */ #define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104) /** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -1264,7 +1262,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S 12 /** DMA2D_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel 1 */ #define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108) /** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -1360,7 +1358,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S 12 /** DMA2D_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel 1 */ #define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c) /** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -1456,7 +1454,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S 12 /** DMA2D_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel 1 */ #define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110) /** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -1552,7 +1550,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S 12 /** DMA2D_OUTFIFO_STATUS_CH1_REG register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel 1 */ #define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114) /** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; @@ -1676,7 +1674,7 @@ extern "C" { #define DMA2D_OUTFIFO_CNT_L3_CH1_S 24 /** DMA2D_OUT_PUSH_CH1_REG register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel 1 */ #define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118) /** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0; @@ -1695,7 +1693,7 @@ extern "C" { #define DMA2D_OUTFIFO_PUSH_CH1_S 10 /** DMA2D_OUT_LINK_CONF_CH1_REG register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel 1 */ #define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c) /** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; @@ -1729,7 +1727,7 @@ extern "C" { #define DMA2D_OUTLINK_PARK_CH1_S 23 /** DMA2D_OUT_LINK_ADDR_CH1_REG register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel 1 */ #define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120) /** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; @@ -1741,7 +1739,7 @@ extern "C" { #define DMA2D_OUTLINK_ADDR_CH1_S 0 /** DMA2D_OUT_STATE_CH1_REG register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel 1 */ #define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124) /** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; @@ -1774,7 +1772,7 @@ extern "C" { #define DMA2D_OUT_RESET_AVAIL_CH1_S 24 /** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128) /** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1787,7 +1785,7 @@ extern "C" { #define DMA2D_OUT_EOF_DES_ADDR_CH1_S 0 /** DMA2D_OUT_DSCR_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c) /** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1799,7 +1797,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_CH1_S 0 /** DMA2D_OUT_DSCR_BF0_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130) /** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1811,7 +1809,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF0_CH1_S 0 /** DMA2D_OUT_DSCR_BF1_CH1_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 1 */ #define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134) /** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -1823,7 +1821,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF1_CH1_S 0 /** DMA2D_OUT_PERI_SEL_CH1_REG register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel 1 */ #define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138) /** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; @@ -1836,7 +1834,7 @@ extern "C" { #define DMA2D_OUT_PERI_SEL_CH1_S 0 /** DMA2D_OUT_ARB_CH1_REG register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel 1 */ #define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c) /** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; @@ -1846,16 +1844,16 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH1 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH1 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH1_M (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S) -#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH1_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH1_S 4 /** DMA2D_OUT_RO_STATUS_CH1_REG register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel 1 */ #define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140) /** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0; @@ -1897,7 +1895,7 @@ extern "C" { #define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S 14 /** DMA2D_OUT_COLOR_CONVERT_CH1_REG register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel 1 */ #define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148) /** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; @@ -1927,7 +1925,7 @@ extern "C" { #define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S 3 /** DMA2D_OUT_SCRAMBLE_CH1_REG register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel 1 */ #define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c) /** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0; @@ -1940,7 +1938,7 @@ extern "C" { #define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM0_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150) /** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298; @@ -1952,7 +1950,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM1_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154) /** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121; @@ -1964,7 +1962,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H1_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM2_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158) /** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050; @@ -1976,7 +1974,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM3_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c) /** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784; @@ -1988,7 +1986,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M1_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM4_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160) /** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682; @@ -2000,7 +1998,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L0_CH1_S 0 /** DMA2D_OUT_COLOR_PARAM5_CH1_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 1 */ #define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164) /** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392; @@ -2012,7 +2010,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L1_CH1_S 0 /** DMA2D_OUT_ETM_CONF_CH1_REG register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel 1 */ #define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168) /** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; @@ -2057,7 +2055,7 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S 14 /** DMA2D_OUT_CONF0_CH2_REG register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel 2 */ #define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200) /** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0; @@ -2170,7 +2168,7 @@ extern "C" { #define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S 26 /** DMA2D_OUT_INT_RAW_CH2_REG register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel 2 */ #define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204) /** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -2272,7 +2270,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S 12 /** DMA2D_OUT_INT_ENA_CH2_REG register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel 2 */ #define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208) /** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -2368,7 +2366,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S 12 /** DMA2D_OUT_INT_ST_CH2_REG register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel 2 */ #define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c) /** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; @@ -2464,7 +2462,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S 12 /** DMA2D_OUT_INT_CLR_CH2_REG register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel 2 */ #define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210) /** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; @@ -2560,7 +2558,7 @@ extern "C" { #define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S 12 /** DMA2D_OUTFIFO_STATUS_CH2_REG register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel 2 */ #define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214) /** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; @@ -2684,7 +2682,7 @@ extern "C" { #define DMA2D_OUTFIFO_CNT_L3_CH2_S 24 /** DMA2D_OUT_PUSH_CH2_REG register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel 2 */ #define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218) /** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0; @@ -2703,7 +2701,7 @@ extern "C" { #define DMA2D_OUTFIFO_PUSH_CH2_S 10 /** DMA2D_OUT_LINK_CONF_CH2_REG register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel 2 */ #define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c) /** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; @@ -2737,7 +2735,7 @@ extern "C" { #define DMA2D_OUTLINK_PARK_CH2_S 23 /** DMA2D_OUT_LINK_ADDR_CH2_REG register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel 2 */ #define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220) /** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; @@ -2749,7 +2747,7 @@ extern "C" { #define DMA2D_OUTLINK_ADDR_CH2_S 0 /** DMA2D_OUT_STATE_CH2_REG register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel 2 */ #define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224) /** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; @@ -2782,7 +2780,7 @@ extern "C" { #define DMA2D_OUT_RESET_AVAIL_CH2_S 24 /** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228) /** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2795,7 +2793,7 @@ extern "C" { #define DMA2D_OUT_EOF_DES_ADDR_CH2_S 0 /** DMA2D_OUT_DSCR_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c) /** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2807,7 +2805,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_CH2_S 0 /** DMA2D_OUT_DSCR_BF0_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230) /** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2819,7 +2817,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF0_CH2_S 0 /** DMA2D_OUT_DSCR_BF1_CH2_REG register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel 2 */ #define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234) /** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; @@ -2831,7 +2829,7 @@ extern "C" { #define DMA2D_OUTLINK_DSCR_BF1_CH2_S 0 /** DMA2D_OUT_PERI_SEL_CH2_REG register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel 2 */ #define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238) /** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; @@ -2844,7 +2842,7 @@ extern "C" { #define DMA2D_OUT_PERI_SEL_CH2_S 0 /** DMA2D_OUT_ARB_CH2_REG register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel 2 */ #define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c) /** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; @@ -2854,16 +2852,16 @@ extern "C" { #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S) #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V 0x0000000FU #define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S 0 -/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1; +/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_OUT_ARB_PRIORITY_CH2 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH2 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH2_M (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S) -#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x00000003U +#define DMA2D_OUT_ARB_PRIORITY_CH2_V 0x0000000FU #define DMA2D_OUT_ARB_PRIORITY_CH2_S 4 /** DMA2D_OUT_RO_STATUS_CH2_REG register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel 2 */ #define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240) /** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0; @@ -2905,7 +2903,7 @@ extern "C" { #define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S 14 /** DMA2D_OUT_COLOR_CONVERT_CH2_REG register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel 2 */ #define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248) /** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; @@ -2935,7 +2933,7 @@ extern "C" { #define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S 3 /** DMA2D_OUT_SCRAMBLE_CH2_REG register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel 2 */ #define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c) /** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0; @@ -2948,7 +2946,7 @@ extern "C" { #define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM0_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250) /** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298; @@ -2960,7 +2958,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM1_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254) /** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121; @@ -2972,7 +2970,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_H1_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM2_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258) /** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050; @@ -2984,7 +2982,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM3_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c) /** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784; @@ -2996,7 +2994,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_M1_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM4_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260) /** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682; @@ -3008,7 +3006,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L0_CH2_S 0 /** DMA2D_OUT_COLOR_PARAM5_CH2_REG register - * Configures the tx color convert parameter of channel 0 + * Configures the tx color convert parameter of channel 2 */ #define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264) /** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392; @@ -3020,7 +3018,7 @@ extern "C" { #define DMA2D_OUT_COLOR_PARAM_L1_CH2_S 0 /** DMA2D_OUT_ETM_CONF_CH2_REG register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel 2 */ #define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268) /** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; @@ -3064,6 +3062,1014 @@ extern "C" { #define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V 0x00003FFFU #define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S 14 +/** DMA2D_OUT_CONF0_CH3_REG register + * Configures the tx direction of channel 3 + */ +#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300) +/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data pointed by + * outlink descriptor has been received. + */ +#define DMA2D_OUT_AUTO_WRBACK_CH3 (BIT(0)) +#define DMA2D_OUT_AUTO_WRBACK_CH3_M (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S) +#define DMA2D_OUT_AUTO_WRBACK_CH3_V 0x00000001U +#define DMA2D_OUT_AUTO_WRBACK_CH3_S 0 +/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1; + * EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is + * generated when data need to read has been popped from FIFO in DMA + */ +#define DMA2D_OUT_EOF_MODE_CH3 (BIT(1)) +#define DMA2D_OUT_EOF_MODE_CH3_M (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S) +#define DMA2D_OUT_EOF_MODE_CH3_V 0x00000001U +#define DMA2D_OUT_EOF_MODE_CH3_S 1 +/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define DMA2D_OUTDSCR_BURST_EN_CH3 (BIT(2)) +#define DMA2D_OUTDSCR_BURST_EN_CH3_M (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S) +#define DMA2D_OUTDSCR_BURST_EN_CH3_V 0x00000001U +#define DMA2D_OUTDSCR_BURST_EN_CH3_S 2 +/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0; + * When access address space is ecc/aes area, this bit should be set to 1. In this + * case, the start address of square should be 16-bit aligned. The width of square + * multiply byte number of one pixel should be 16-bit aligned. + */ +#define DMA2D_OUT_ECC_AES_EN_CH3 (BIT(3)) +#define DMA2D_OUT_ECC_AES_EN_CH3_M (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S) +#define DMA2D_OUT_ECC_AES_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ECC_AES_EN_CH3_S 3 +/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define DMA2D_OUT_CHECK_OWNER_CH3 (BIT(4)) +#define DMA2D_OUT_CHECK_OWNER_CH3_M (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S) +#define DMA2D_OUT_CHECK_OWNER_CH3_V 0x00000001U +#define DMA2D_OUT_CHECK_OWNER_CH3_S 4 +/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define DMA2D_OUT_LOOP_TEST_CH3 (BIT(5)) +#define DMA2D_OUT_LOOP_TEST_CH3_M (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S) +#define DMA2D_OUT_LOOP_TEST_CH3_V 0x00000001U +#define DMA2D_OUT_LOOP_TEST_CH3_S 5 +/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0; + * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * bytes 4: 128 bytes + */ +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3 0x00000007U +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S) +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V 0x00000007U +#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S 6 +/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0; + * Sel TX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: + * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link + * descriptor + */ +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 0x00000003U +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S) +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V 0x00000003U +#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S 9 +/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0; + * Set this bit to 1 to obtain descriptor from IP port + */ +#define DMA2D_OUT_DSCR_PORT_EN_CH3 (BIT(11)) +#define DMA2D_OUT_DSCR_PORT_EN_CH3_M (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S) +#define DMA2D_OUT_DSCR_PORT_EN_CH3_V 0x00000001U +#define DMA2D_OUT_DSCR_PORT_EN_CH3_S 11 +/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0; + * Set this bit to 1 to make sure AXI read data don't cross the address boundary which + * define by mem_burst_length + */ +#define DMA2D_OUT_PAGE_BOUND_EN_CH3 (BIT(12)) +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S) +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V 0x00000001U +#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S 12 +/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0; + * Enable TX channel 0 macro block reorder when set to 1, only channel0 have this + * selection + */ +#define DMA2D_OUT_REORDER_EN_CH3 (BIT(16)) +#define DMA2D_OUT_REORDER_EN_CH3_M (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S) +#define DMA2D_OUT_REORDER_EN_CH3_V 0x00000001U +#define DMA2D_OUT_REORDER_EN_CH3_S 16 +/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset TX channel + */ +#define DMA2D_OUT_RST_CH3 (BIT(24)) +#define DMA2D_OUT_RST_CH3_M (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S) +#define DMA2D_OUT_RST_CH3_V 0x00000001U +#define DMA2D_OUT_RST_CH3_S 24 +/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0; + * Write 1 before reset and write 0 after reset + */ +#define DMA2D_OUT_CMD_DISABLE_CH3 (BIT(25)) +#define DMA2D_OUT_CMD_DISABLE_CH3_M (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S) +#define DMA2D_OUT_CMD_DISABLE_CH3_V 0x00000001U +#define DMA2D_OUT_CMD_DISABLE_CH3_S 25 +/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0; + * Set this bit to 1 to disable arbiter optimum weight function. + */ +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 (BIT(26)) +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S) +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V 0x00000001U +#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S 26 + +/** DMA2D_OUT_INT_RAW_CH3_REG register + * Raw interrupt status of TX channel 3 + */ +#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304) +/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define DMA2D_OUT_DONE_CH3_INT_RAW (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_RAW_M (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S) +#define DMA2D_OUT_DONE_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_RAW_S 0 +/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define DMA2D_OUT_EOF_CH3_INT_RAW (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_RAW_M (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S) +#define DMA2D_OUT_EOF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_RAW_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error, + * including owner error, the second and third word error of outlink descriptor for Tx + * channel 0. + */ +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. + */ +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. + */ +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. + */ +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. + */ +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when fifo is overflow. + */ +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when fifo is underflow. + */ +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is overflow. + */ +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is underflow. + */ +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + */ +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S 12 + +/** DMA2D_OUT_INT_ENA_CH3_REG register + * Interrupt enable bits of TX channel 3 + */ +#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308) +/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define DMA2D_OUT_DONE_CH3_INT_ENA (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_ENA_M (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S) +#define DMA2D_OUT_DONE_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_ENA_S 0 +/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_EOF_CH3_INT_ENA (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_ENA_M (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S) +#define DMA2D_OUT_EOF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_ENA_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S 12 + +/** DMA2D_OUT_INT_ST_CH3_REG register + * Masked interrupt status of TX channel 3 + */ +#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c) +/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define DMA2D_OUT_DONE_CH3_INT_ST (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_ST_M (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S) +#define DMA2D_OUT_DONE_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_ST_S 0 +/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_EOF_CH3_INT_ST (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_ST_M (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S) +#define DMA2D_OUT_EOF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_ST_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S 12 + +/** DMA2D_OUT_INT_CLR_CH3_REG register + * Interrupt clear bits of TX channel 3 + */ +#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310) +/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define DMA2D_OUT_DONE_CH3_INT_CLR (BIT(0)) +#define DMA2D_OUT_DONE_CH3_INT_CLR_M (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S) +#define DMA2D_OUT_DONE_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DONE_CH3_INT_CLR_S 0 +/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_EOF_CH3_INT_CLR (BIT(1)) +#define DMA2D_OUT_EOF_CH3_INT_CLR_M (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S) +#define DMA2D_OUT_EOF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_EOF_CH3_INT_CLR_S 1 +/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR (BIT(2)) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S) +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S 2 +/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(3)) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S) +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S 3 +/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(4)) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S 4 +/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(5)) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S 5 +/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR (BIT(6)) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S 6 +/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR (BIT(7)) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S 7 +/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(8)) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S 8 +/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(9)) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S 9 +/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR (BIT(10)) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S 10 +/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR (BIT(11)) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S) +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S 11 +/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR (BIT(12)) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S) +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V 0x00000001U +#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S 12 + +/** DMA2D_OUTFIFO_STATUS_CH3_REG register + * Represents the status of the tx fifo of channel 3 + */ +#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314) +/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0; + * Tx FIFO full signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_FULL_L2_CH3 (BIT(0)) +#define DMA2D_OUTFIFO_FULL_L2_CH3_M (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S) +#define DMA2D_OUTFIFO_FULL_L2_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L2_CH3_S 0 +/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1; + * Tx FIFO empty signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_EMPTY_L2_CH3 (BIT(1)) +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S 1 +/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + */ +#define DMA2D_OUTFIFO_CNT_L2_CH3 0x0000000FU +#define DMA2D_OUTFIFO_CNT_L2_CH3_M (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S) +#define DMA2D_OUTFIFO_CNT_L2_CH3_V 0x0000000FU +#define DMA2D_OUTFIFO_CNT_L2_CH3_S 2 +/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3 (BIT(7)) +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S 7 +/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3 (BIT(8)) +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S 8 +/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3 (BIT(9)) +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S 9 +/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3 (BIT(10)) +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S 10 +/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3 (BIT(11)) +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S 11 +/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3 (BIT(12)) +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S 12 +/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3 (BIT(13)) +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S 13 +/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1; + * reserved + */ +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3 (BIT(14)) +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S) +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V 0x00000001U +#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S 14 +/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0; + * Tx FIFO full signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_FULL_L1_CH3 (BIT(15)) +#define DMA2D_OUTFIFO_FULL_L1_CH3_M (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S) +#define DMA2D_OUTFIFO_FULL_L1_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L1_CH3_S 15 +/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1; + * Tx FIFO empty signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_EMPTY_L1_CH3 (BIT(16)) +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S 16 +/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + */ +#define DMA2D_OUTFIFO_CNT_L1_CH3 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L1_CH3_M (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S) +#define DMA2D_OUTFIFO_CNT_L1_CH3_V 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L1_CH3_S 17 +/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0; + * Tx FIFO full signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_FULL_L3_CH3 (BIT(22)) +#define DMA2D_OUTFIFO_FULL_L3_CH3_M (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S) +#define DMA2D_OUTFIFO_FULL_L3_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_FULL_L3_CH3_S 22 +/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1; + * Tx FIFO empty signal for Tx channel 0. + */ +#define DMA2D_OUTFIFO_EMPTY_L3_CH3 (BIT(23)) +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S) +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S 23 +/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0; + * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + */ +#define DMA2D_OUTFIFO_CNT_L3_CH3 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L3_CH3_M (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S) +#define DMA2D_OUTFIFO_CNT_L3_CH3_V 0x0000001FU +#define DMA2D_OUTFIFO_CNT_L3_CH3_S 24 + +/** DMA2D_OUT_PUSH_CH3_REG register + * Configures the tx fifo of channel 3 + */ +#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318) +/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0; + * This register stores the data that need to be pushed into DMA Tx FIFO. + */ +#define DMA2D_OUTFIFO_WDATA_CH3 0x000003FFU +#define DMA2D_OUTFIFO_WDATA_CH3_M (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S) +#define DMA2D_OUTFIFO_WDATA_CH3_V 0x000003FFU +#define DMA2D_OUTFIFO_WDATA_CH3_S 0 +/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0; + * Set this bit to push data into DMA Tx FIFO. + */ +#define DMA2D_OUTFIFO_PUSH_CH3 (BIT(10)) +#define DMA2D_OUTFIFO_PUSH_CH3_M (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S) +#define DMA2D_OUTFIFO_PUSH_CH3_V 0x00000001U +#define DMA2D_OUTFIFO_PUSH_CH3_S 10 + +/** DMA2D_OUT_LINK_CONF_CH3_REG register + * Configures the tx descriptor operations of channel 3 + */ +#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c) +/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define DMA2D_OUTLINK_STOP_CH3 (BIT(20)) +#define DMA2D_OUTLINK_STOP_CH3_M (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S) +#define DMA2D_OUTLINK_STOP_CH3_V 0x00000001U +#define DMA2D_OUTLINK_STOP_CH3_S 20 +/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define DMA2D_OUTLINK_START_CH3 (BIT(21)) +#define DMA2D_OUTLINK_START_CH3_M (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S) +#define DMA2D_OUTLINK_START_CH3_V 0x00000001U +#define DMA2D_OUTLINK_START_CH3_S 21 +/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define DMA2D_OUTLINK_RESTART_CH3 (BIT(22)) +#define DMA2D_OUTLINK_RESTART_CH3_M (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S) +#define DMA2D_OUTLINK_RESTART_CH3_V 0x00000001U +#define DMA2D_OUTLINK_RESTART_CH3_S 22 +/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define DMA2D_OUTLINK_PARK_CH3 (BIT(23)) +#define DMA2D_OUTLINK_PARK_CH3_M (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S) +#define DMA2D_OUTLINK_PARK_CH3_V 0x00000001U +#define DMA2D_OUTLINK_PARK_CH3_S 23 + +/** DMA2D_OUT_LINK_ADDR_CH3_REG register + * Configures the tx descriptor address of channel 3 + */ +#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320) +/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the first outlink descriptor's address. + */ +#define DMA2D_OUTLINK_ADDR_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_ADDR_CH3_M (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S) +#define DMA2D_OUTLINK_ADDR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_ADDR_CH3_S 0 + +/** DMA2D_OUT_STATE_CH3_REG register + * Represents the working status of the tx descriptor of channel 3 + */ +#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324) +/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define DMA2D_OUTLINK_DSCR_ADDR_CH3 0x0003FFFFU +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S) +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V 0x0003FFFFU +#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S 0 +/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0; + * This register stores the current descriptor state machine state. + */ +#define DMA2D_OUT_DSCR_STATE_CH3 0x00000003U +#define DMA2D_OUT_DSCR_STATE_CH3_M (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S) +#define DMA2D_OUT_DSCR_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_DSCR_STATE_CH3_S 18 +/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0; + * This register stores the current control module state machine state. + */ +#define DMA2D_OUT_STATE_CH3 0x0000000FU +#define DMA2D_OUT_STATE_CH3_M (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S) +#define DMA2D_OUT_STATE_CH3_V 0x0000000FU +#define DMA2D_OUT_STATE_CH3_S 20 +/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1; + * This register indicate that if the channel reset is safety. + */ +#define DMA2D_OUT_RESET_AVAIL_CH3 (BIT(24)) +#define DMA2D_OUT_RESET_AVAIL_CH3_M (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S) +#define DMA2D_OUT_RESET_AVAIL_CH3_V 0x00000001U +#define DMA2D_OUT_RESET_AVAIL_CH3_S 24 + +/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 + */ +#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328) +/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define DMA2D_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFFU +#define DMA2D_OUT_EOF_DES_ADDR_CH3_M (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S) +#define DMA2D_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUT_EOF_DES_ADDR_CH3_S 0 + +/** DMA2D_OUT_DSCR_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 + */ +#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c) +/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the next outlink descriptor address y. + */ +#define DMA2D_OUTLINK_DSCR_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_CH3_M (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S) +#define DMA2D_OUTLINK_DSCR_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_CH3_S 0 + +/** DMA2D_OUT_DSCR_BF0_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 + */ +#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330) +/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor's next address y-1. + */ +#define DMA2D_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF0_CH3_M (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S) +#define DMA2D_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF0_CH3_S 0 + +/** DMA2D_OUT_DSCR_BF1_CH3_REG register + * Represents the address associated with the outlink descriptor of channel 3 + */ +#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334) +/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last outlink descriptor's next address y-2. + */ +#define DMA2D_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF1_CH3_M (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S) +#define DMA2D_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFFU +#define DMA2D_OUTLINK_DSCR_BF1_CH3_S 0 + +/** DMA2D_OUT_PERI_SEL_CH3_REG register + * Configures the tx peripheral of channel 3 + */ +#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338) +/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7; + * This register is used to select peripheral for Tx channel 0: jpeg 1: + * display-1 2: display-2 3: display-3 7: no choose + */ +#define DMA2D_OUT_PERI_SEL_CH3 0x00000007U +#define DMA2D_OUT_PERI_SEL_CH3_M (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S) +#define DMA2D_OUT_PERI_SEL_CH3_V 0x00000007U +#define DMA2D_OUT_PERI_SEL_CH3_S 0 + +/** DMA2D_OUT_ARB_CH3_REG register + * Configures the tx arbiter of channel 3 + */ +#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c) +/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1; + * Set the max number of token count of arbiter + */ +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3 0x0000000FU +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S) +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V 0x0000000FU +#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S 0 +/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [7:4]; default: 1; + * Set the priority of channel + */ +#define DMA2D_OUT_ARB_PRIORITY_CH3 0x0000000FU +#define DMA2D_OUT_ARB_PRIORITY_CH3_M (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S) +#define DMA2D_OUT_ARB_PRIORITY_CH3_V 0x0000000FU +#define DMA2D_OUT_ARB_PRIORITY_CH3_S 4 + +/** DMA2D_OUT_RO_STATUS_CH3_REG register + * Represents the status of the tx reorder module of channel 3 + */ +#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340) +/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0; + * The register stores the byte number of the data in color convert Tx FIFO for + * channel 0. + */ +#define DMA2D_OUTFIFO_RO_CNT_CH3 0x0000003FU +#define DMA2D_OUTFIFO_RO_CNT_CH3_M (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S) +#define DMA2D_OUTFIFO_RO_CNT_CH3_V 0x0000003FU +#define DMA2D_OUTFIFO_RO_CNT_CH3_S 0 +/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0; + * The register stores the state of read ram of reorder + */ +#define DMA2D_OUT_RO_WR_STATE_CH3 0x00000003U +#define DMA2D_OUT_RO_WR_STATE_CH3_M (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S) +#define DMA2D_OUT_RO_WR_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_RO_WR_STATE_CH3_S 6 +/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0; + * The register stores the state of write ram of reorder + */ +#define DMA2D_OUT_RO_RD_STATE_CH3 0x00000003U +#define DMA2D_OUT_RO_RD_STATE_CH3_M (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S) +#define DMA2D_OUT_RO_RD_STATE_CH3_V 0x00000003U +#define DMA2D_OUT_RO_RD_STATE_CH3_S 8 +/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0; + * the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes + * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes + */ +#define DMA2D_OUT_PIXEL_BYTE_CH3 0x0000000FU +#define DMA2D_OUT_PIXEL_BYTE_CH3_M (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S) +#define DMA2D_OUT_PIXEL_BYTE_CH3_V 0x0000000FU +#define DMA2D_OUT_PIXEL_BYTE_CH3_S 10 +/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0; + * the number of macro blocks contained in a burst of data at TX channel + */ +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3 0x0000000FU +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S) +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V 0x0000000FU +#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S 14 + +/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register + * Configures the tx color convert of channel 3 + */ +#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348) +/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * Set final color convert process and output type 0: RGB888 to RGB565 1: + * YUV444 to YUV422 2: output directly + */ +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 0x00000003U +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S) +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V 0x00000003U +#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S 0 +/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Enable generic color convert module between color input & color output, need to + * configure parameter. + */ +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3 (BIT(2)) +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S) +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V 0x00000001U +#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S 2 +/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7; + * Set first color convert process and input color type 0: RGB565 to RGB888 1: + * YUV422 to YUV444 2: Other 2byte/pixel type 3: Other 3byte/pixel type 7: + * disable color space convert + */ +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3 0x00000007U +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S) +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V 0x00000007U +#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S 3 + +/** DMA2D_OUT_SCRAMBLE_CH3_REG register + * Configures the tx scramble of channel 3 + */ +#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c) +/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0; + * Scramble data before color convert : 0 : BYTE2-1-0 1 : BYTE2-0-1 2 : + * BYTE1-0-2 3 : BYTE1-2-0 4 : BYTE0-2-1 5 : BYTE0-1-2 + */ +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 0x00000007U +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S) +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V 0x00000007U +#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350) +/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298; + * Set first 2 parameter of most significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_H0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354) +/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121; + * Set last 2 parameter of most significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_H1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358) +/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050; + * Set first 2 parameter of midium significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_M0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c) +/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784; + * Set last 2 parameter of midium significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_M1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360) +/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682; + * Set first 2 parameter of least significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_L0_CH3 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V 0x001FFFFFU +#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S 0 + +/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register + * Configures the tx color convert parameter of channel 3 + */ +#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364) +/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392; + * Set last 2 parameter of least significant byte of pending 3 bytes + */ +#define DMA2D_OUT_COLOR_PARAM_L1_CH3 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S) +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V 0x0FFFFFFFU +#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S 0 + +/** DMA2D_OUT_ETM_CONF_CH3_REG register + * Configures the tx etm of channel 3 + */ +#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368) +/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0; + * Configures the enable of the etm function, 1 is enable. + */ +#define DMA2D_OUT_ETM_EN_CH3 (BIT(0)) +#define DMA2D_OUT_ETM_EN_CH3_M (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S) +#define DMA2D_OUT_ETM_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ETM_EN_CH3_S 0 +/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0; + * Configures the enable of the descriptors loop etm function, 1 is enable. + */ +#define DMA2D_OUT_ETM_LOOP_EN_CH3 (BIT(1)) +#define DMA2D_OUT_ETM_LOOP_EN_CH3_M (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S) +#define DMA2D_OUT_ETM_LOOP_EN_CH3_V 0x00000001U +#define DMA2D_OUT_ETM_LOOP_EN_CH3_S 1 +/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1; + * Configures the maximum number of cacheable descriptors. + */ +#define DMA2D_OUT_DSCR_TASK_MAK_CH3 0x00000003U +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S) +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V 0x00000003U +#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S 2 + +/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register + * Configures the tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c) +/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18; + * Set the horizontal width of tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S) +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S 0 +/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18; + * Set the vertical height of tx block size in dscr port mode + */ +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S) +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V 0x00003FFFU +#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S 14 + /** DMA2D_IN_CONF0_CH0_REG register * Configures the rx direction of channel 0 */ @@ -3668,42 +4674,42 @@ extern "C" { #define DMA2D_IN_REMAIN_UNDER_8B_CH0_V 0x00000001U #define DMA2D_IN_REMAIN_UNDER_8B_CH0_S 14 /** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel 0. */ #define DMA2D_INFIFO_FULL_L1_CH0 (BIT(15)) #define DMA2D_INFIFO_FULL_L1_CH0_M (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S) #define DMA2D_INFIFO_FULL_L1_CH0_V 0x00000001U #define DMA2D_INFIFO_FULL_L1_CH0_S 15 /** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel 0. */ #define DMA2D_INFIFO_EMPTY_L1_CH0 (BIT(16)) #define DMA2D_INFIFO_EMPTY_L1_CH0_M (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S) #define DMA2D_INFIFO_EMPTY_L1_CH0_V 0x00000001U #define DMA2D_INFIFO_EMPTY_L1_CH0_S 16 /** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. */ #define DMA2D_INFIFO_CNT_L1_CH0 0x0000001FU #define DMA2D_INFIFO_CNT_L1_CH0_M (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S) #define DMA2D_INFIFO_CNT_L1_CH0_V 0x0000001FU #define DMA2D_INFIFO_CNT_L1_CH0_S 17 /** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel 0. */ #define DMA2D_INFIFO_FULL_L3_CH0 (BIT(22)) #define DMA2D_INFIFO_FULL_L3_CH0_M (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S) #define DMA2D_INFIFO_FULL_L3_CH0_V 0x00000001U #define DMA2D_INFIFO_FULL_L3_CH0_S 22 /** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel 0. */ #define DMA2D_INFIFO_EMPTY_L3_CH0 (BIT(23)) #define DMA2D_INFIFO_EMPTY_L3_CH0_M (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S) #define DMA2D_INFIFO_EMPTY_L3_CH0_V 0x00000001U #define DMA2D_INFIFO_EMPTY_L3_CH0_S 23 /** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. */ #define DMA2D_INFIFO_CNT_L3_CH0 0x0000001FU #define DMA2D_INFIFO_CNT_L3_CH0_M (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S) @@ -3902,12 +4908,12 @@ extern "C" { #define DMA2D_IN_ARB_TOKEN_NUM_CH0_M (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S) #define DMA2D_IN_ARB_TOKEN_NUM_CH0_V 0x0000000FU #define DMA2D_IN_ARB_TOKEN_NUM_CH0_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1; +/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_IN_ARB_PRIORITY_CH0 (BIT(4)) +#define DMA2D_IN_ARB_PRIORITY_CH0 0x0000000FU #define DMA2D_IN_ARB_PRIORITY_CH0_M (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S) -#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x00000001U +#define DMA2D_IN_ARB_PRIORITY_CH0_V 0x0000000FU #define DMA2D_IN_ARB_PRIORITY_CH0_S 4 /** DMA2D_IN_RO_STATUS_CH0_REG register @@ -3980,12 +4986,12 @@ extern "C" { #define DMA2D_IN_RO_RAM_CLK_FO_CH0_S 6 /** DMA2D_IN_COLOR_CONVERT_CH0_REG register - * Configures the tx color convert of channel 0 + * Configures the Rx color convert of channel 0 */ #define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c) /** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly + * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 */ #define DMA2D_IN_COLOR_OUTPUT_SEL_CH0 0x00000003U #define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S) @@ -4128,7 +5134,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_MAK_CH0_S 2 /** DMA2D_IN_CONF0_CH1_REG register - * Configures the rx direction of channel 0 + * Configures the rx direction of channel 1 */ #define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600) /** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0; @@ -4232,7 +5238,7 @@ extern "C" { #define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S 26 /** DMA2D_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 0 + * Raw interrupt status of RX channel 1 */ #define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604) /** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; @@ -4341,7 +5347,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S 13 /** DMA2D_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 0 + * Interrupt enable bits of RX channel 1 */ #define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608) /** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; @@ -4444,7 +5450,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S 13 /** DMA2D_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 0 + * Masked interrupt status of RX channel 1 */ #define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c) /** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; @@ -4547,7 +5553,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S 13 /** DMA2D_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 0 + * Interrupt clear bits of RX channel 1 */ #define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610) /** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; @@ -4650,7 +5656,7 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S 13 /** DMA2D_INFIFO_STATUS_CH1_REG register - * Represents the status of the rx fifo of channel 0 + * Represents the status of the rx fifo of channel 1 */ #define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614) /** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0; @@ -4731,42 +5737,42 @@ extern "C" { #define DMA2D_IN_REMAIN_UNDER_8B_CH1_V 0x00000001U #define DMA2D_IN_REMAIN_UNDER_8B_CH1_S 14 /** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel 0. */ #define DMA2D_INFIFO_FULL_L1_CH1 (BIT(15)) #define DMA2D_INFIFO_FULL_L1_CH1_M (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S) #define DMA2D_INFIFO_FULL_L1_CH1_V 0x00000001U #define DMA2D_INFIFO_FULL_L1_CH1_S 15 /** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel 0. */ #define DMA2D_INFIFO_EMPTY_L1_CH1 (BIT(16)) #define DMA2D_INFIFO_EMPTY_L1_CH1_M (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S) #define DMA2D_INFIFO_EMPTY_L1_CH1_V 0x00000001U #define DMA2D_INFIFO_EMPTY_L1_CH1_S 16 /** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. */ #define DMA2D_INFIFO_CNT_L1_CH1 0x0000001FU #define DMA2D_INFIFO_CNT_L1_CH1_M (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S) #define DMA2D_INFIFO_CNT_L1_CH1_V 0x0000001FU #define DMA2D_INFIFO_CNT_L1_CH1_S 17 /** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel 0. */ #define DMA2D_INFIFO_FULL_L3_CH1 (BIT(22)) #define DMA2D_INFIFO_FULL_L3_CH1_M (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S) #define DMA2D_INFIFO_FULL_L3_CH1_V 0x00000001U #define DMA2D_INFIFO_FULL_L3_CH1_S 22 /** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel 0. */ #define DMA2D_INFIFO_EMPTY_L3_CH1 (BIT(23)) #define DMA2D_INFIFO_EMPTY_L3_CH1_M (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S) #define DMA2D_INFIFO_EMPTY_L3_CH1_V 0x00000001U #define DMA2D_INFIFO_EMPTY_L3_CH1_S 23 /** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. */ #define DMA2D_INFIFO_CNT_L3_CH1 0x0000001FU #define DMA2D_INFIFO_CNT_L3_CH1_M (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S) @@ -4774,7 +5780,7 @@ extern "C" { #define DMA2D_INFIFO_CNT_L3_CH1_S 24 /** DMA2D_IN_POP_CH1_REG register - * Configures the rx fifo of channel 0 + * Configures the rx fifo of channel 1 */ #define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618) /** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024; @@ -4793,7 +5799,7 @@ extern "C" { #define DMA2D_INFIFO_POP_CH1_S 11 /** DMA2D_IN_LINK_CONF_CH1_REG register - * Configures the rx descriptor operations of channel 0 + * Configures the rx descriptor operations of channel 1 */ #define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c) /** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; @@ -4835,7 +5841,7 @@ extern "C" { #define DMA2D_INLINK_PARK_CH1_S 24 /** DMA2D_IN_LINK_ADDR_CH1_REG register - * Configures the rx descriptor address of channel 0 + * Configures the rx descriptor address of channel 1 */ #define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620) /** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; @@ -4847,7 +5853,7 @@ extern "C" { #define DMA2D_INLINK_ADDR_CH1_S 0 /** DMA2D_IN_STATE_CH1_REG register - * Represents the working status of the rx descriptor of channel 0 + * Represents the working status of the rx descriptor of channel 1 */ #define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624) /** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; @@ -4880,7 +5886,7 @@ extern "C" { #define DMA2D_IN_RESET_AVAIL_CH1_S 23 /** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628) /** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4893,7 +5899,7 @@ extern "C" { #define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S 0 /** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c) /** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4906,7 +5912,7 @@ extern "C" { #define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S 0 /** DMA2D_IN_DSCR_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630) /** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4918,7 +5924,7 @@ extern "C" { #define DMA2D_INLINK_DSCR_CH1_S 0 /** DMA2D_IN_DSCR_BF0_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634) /** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4930,7 +5936,7 @@ extern "C" { #define DMA2D_INLINK_DSCR_BF0_CH1_S 0 /** DMA2D_IN_DSCR_BF1_CH1_REG register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel 1 */ #define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638) /** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; @@ -4942,7 +5948,7 @@ extern "C" { #define DMA2D_INLINK_DSCR_BF1_CH1_S 0 /** DMA2D_IN_PERI_SEL_CH1_REG register - * Configures the rx peripheral of channel 0 + * Configures the rx peripheral of channel 1 */ #define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c) /** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7; @@ -4955,7 +5961,7 @@ extern "C" { #define DMA2D_IN_PERI_SEL_CH1_S 0 /** DMA2D_IN_ARB_CH1_REG register - * Configures the rx arbiter of channel 0 + * Configures the rx arbiter of channel 1 */ #define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640) /** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1; @@ -4965,16 +5971,16 @@ extern "C" { #define DMA2D_IN_ARB_TOKEN_NUM_CH1_M (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S) #define DMA2D_IN_ARB_TOKEN_NUM_CH1_V 0x0000000FU #define DMA2D_IN_ARB_TOKEN_NUM_CH1_S 0 -/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1; +/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ -#define DMA2D_IN_ARB_PRIORITY_CH1 (BIT(4)) +#define DMA2D_IN_ARB_PRIORITY_CH1 0x0000000FU #define DMA2D_IN_ARB_PRIORITY_CH1_M (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S) -#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x00000001U +#define DMA2D_IN_ARB_PRIORITY_CH1_V 0x0000000FU #define DMA2D_IN_ARB_PRIORITY_CH1_S 4 /** DMA2D_IN_RO_STATUS_CH1_REG register - * Represents the status of the rx reorder module of channel 0 + * Represents the status of the rx reorder module of channel 1 */ #define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644) /** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0; @@ -5016,9 +6022,9 @@ extern "C" { #define DMA2D_IN_BURST_BLOCK_NUM_CH1_S 13 /** DMA2D_IN_ETM_CONF_CH1_REG register - * Configures the rx etm of channel 0 + * Configures the rx etm of channel 1 */ -#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648) +#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c) /** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0; * Configures the enable of the etm function, 1 is enable. */ @@ -5041,6 +6047,920 @@ extern "C" { #define DMA2D_IN_DSCR_TASK_MAK_CH1_V 0x00000003U #define DMA2D_IN_DSCR_TASK_MAK_CH1_S 2 +/** DMA2D_IN_CONF0_CH2_REG register + * Configures the rx direction of channel 2 + */ +#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700) +/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0; + * enable memory trans of the same channel + */ +#define DMA2D_IN_MEM_TRANS_EN_CH2 (BIT(0)) +#define DMA2D_IN_MEM_TRANS_EN_CH2_M (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S) +#define DMA2D_IN_MEM_TRANS_EN_CH2_V 0x00000001U +#define DMA2D_IN_MEM_TRANS_EN_CH2_S 0 +/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor + * when accessing SRAM. + */ +#define DMA2D_INDSCR_BURST_EN_CH2 (BIT(2)) +#define DMA2D_INDSCR_BURST_EN_CH2_M (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S) +#define DMA2D_INDSCR_BURST_EN_CH2_V 0x00000001U +#define DMA2D_INDSCR_BURST_EN_CH2_S 2 +/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0; + * When access address space is ecc/aes area, this bit should be set to 1. In this + * case, the start address of square should be 16-bit aligned. The width of square + * multiply byte number of one pixel should be 16-bit aligned. + */ +#define DMA2D_IN_ECC_AES_EN_CH2 (BIT(3)) +#define DMA2D_IN_ECC_AES_EN_CH2_M (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S) +#define DMA2D_IN_ECC_AES_EN_CH2_V 0x00000001U +#define DMA2D_IN_ECC_AES_EN_CH2_S 3 +/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define DMA2D_IN_CHECK_OWNER_CH2 (BIT(4)) +#define DMA2D_IN_CHECK_OWNER_CH2_M (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S) +#define DMA2D_IN_CHECK_OWNER_CH2_V 0x00000001U +#define DMA2D_IN_CHECK_OWNER_CH2_S 4 +/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define DMA2D_IN_LOOP_TEST_CH2 (BIT(5)) +#define DMA2D_IN_LOOP_TEST_CH2_M (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S) +#define DMA2D_IN_LOOP_TEST_CH2_V 0x00000001U +#define DMA2D_IN_LOOP_TEST_CH2_S 5 +/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0; + * Block size of Rx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * bytes 4: 128 bytes + */ +#define DMA2D_IN_MEM_BURST_LENGTH_CH2 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S) +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V 0x00000007U +#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S 6 +/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0; + * Sel RX macro-block size 0: 8pixel*8pixel 1: 8pixel*16pixel 2: + * 16pixel*16pixel 3: no macro-block , only useful in mode 1 of the link + * descriptor + */ +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S) +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V 0x00000003U +#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S 9 +/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0; + * Set this bit to 1 to obtain descriptor from IP port + */ +#define DMA2D_IN_DSCR_PORT_EN_CH2 (BIT(11)) +#define DMA2D_IN_DSCR_PORT_EN_CH2_M (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S) +#define DMA2D_IN_DSCR_PORT_EN_CH2_V 0x00000001U +#define DMA2D_IN_DSCR_PORT_EN_CH2_S 11 +/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to 1 to make sure AXI write data don't cross the address boundary + * which define by mem_burst_length + */ +#define DMA2D_IN_PAGE_BOUND_EN_CH2 (BIT(12)) +#define DMA2D_IN_PAGE_BOUND_EN_CH2_M (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S) +#define DMA2D_IN_PAGE_BOUND_EN_CH2_V 0x00000001U +#define DMA2D_IN_PAGE_BOUND_EN_CH2_S 12 +/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0; + * Enable RX channel 0 macro block reorder when set to 1, only channel0 have this + * selection + */ +#define DMA2D_IN_REORDER_EN_CH2 (BIT(16)) +#define DMA2D_IN_REORDER_EN_CH2_M (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S) +#define DMA2D_IN_REORDER_EN_CH2_V 0x00000001U +#define DMA2D_IN_REORDER_EN_CH2_S 16 +/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0; + * Write 1 then write 0 to this bit to reset Rx channel + */ +#define DMA2D_IN_RST_CH2 (BIT(24)) +#define DMA2D_IN_RST_CH2_M (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S) +#define DMA2D_IN_RST_CH2_V 0x00000001U +#define DMA2D_IN_RST_CH2_S 24 +/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0; + * Write 1 before reset and write 0 after reset + */ +#define DMA2D_IN_CMD_DISABLE_CH2 (BIT(25)) +#define DMA2D_IN_CMD_DISABLE_CH2_M (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S) +#define DMA2D_IN_CMD_DISABLE_CH2_V 0x00000001U +#define DMA2D_IN_CMD_DISABLE_CH2_S 25 +/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0; + * Set this bit to 1 to disable arbiter optimum weight function. + */ +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 (BIT(26)) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S) +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V 0x00000001U +#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S 26 + +/** DMA2D_IN_INT_RAW_CH2_REG register + * Raw interrupt status of RX channel 2 + */ +#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704) +/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been transmitted to peripherals for Rx channel 0. + */ +#define DMA2D_IN_DONE_CH2_INT_RAW (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_RAW_M (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S) +#define DMA2D_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_RAW_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and no data error is detected for Rx channel 0. + */ +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received and data error is detected + */ +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error, + * including owner error, the second and third word error of inlink descriptor for Rx + * channel 0. + */ +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + */ +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + */ +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when the last descriptor is done but fifo + * also remain data. + */ +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is overflow. + */ +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when reorder fifo is underflow. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S 13 + +/** DMA2D_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of RX channel 2 + */ +#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708) +/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH2_INT_ENA (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_ENA_M (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S) +#define DMA2D_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_ENA_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S 13 + +/** DMA2D_IN_INT_ST_CH2_REG register + * Masked interrupt status of RX channel 2 + */ +#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c) +/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH2_INT_ST (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_ST_M (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S) +#define DMA2D_IN_DONE_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_ST_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S 13 + +/** DMA2D_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of RX channel 2 + */ +#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710) +/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define DMA2D_IN_DONE_CH2_INT_CLR (BIT(0)) +#define DMA2D_IN_DONE_CH2_INT_CLR_M (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S) +#define DMA2D_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DONE_CH2_INT_CLR_S 0 +/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S) +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S) +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR (BIT(4)) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S 4 +/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR (BIT(5)) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S 5 +/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR (BIT(6)) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S 6 +/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR (BIT(7)) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S 7 +/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR (BIT(8)) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S) +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S 8 +/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + */ +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR (BIT(9)) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S) +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S 9 +/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(10)) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S 10 +/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR (BIT(11)) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S) +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S 11 +/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt. + */ +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR (BIT(12)) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S) +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S 12 +/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + */ +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR (BIT(13)) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S) +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V 0x00000001U +#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S 13 + +/** DMA2D_INFIFO_STATUS_CH2_REG register + * Represents the status of the rx fifo of channel 2 + */ +#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714) +/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0; + * Rx FIFO full signal for Rx channel. + */ +#define DMA2D_INFIFO_FULL_L2_CH2 (BIT(0)) +#define DMA2D_INFIFO_FULL_L2_CH2_M (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S) +#define DMA2D_INFIFO_FULL_L2_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L2_CH2_S 0 +/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1; + * Rx FIFO empty signal for Rx channel. + */ +#define DMA2D_INFIFO_EMPTY_L2_CH2 (BIT(1)) +#define DMA2D_INFIFO_EMPTY_L2_CH2_M (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S) +#define DMA2D_INFIFO_EMPTY_L2_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L2_CH2_S 1 +/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel. + */ +#define DMA2D_INFIFO_CNT_L2_CH2 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH2_M (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S) +#define DMA2D_INFIFO_CNT_L2_CH2_V 0x0000000FU +#define DMA2D_INFIFO_CNT_L2_CH2_S 2 +/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_1B_CH2 (BIT(7)) +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S 7 +/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_2B_CH2 (BIT(8)) +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S 8 +/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_3B_CH2 (BIT(9)) +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S 9 +/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_4B_CH2 (BIT(10)) +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S 10 +/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_5B_CH2 (BIT(11)) +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S 11 +/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_6B_CH2 (BIT(12)) +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S 12 +/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_7B_CH2 (BIT(13)) +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S 13 +/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0; + * reserved + */ +#define DMA2D_IN_REMAIN_UNDER_8B_CH2 (BIT(14)) +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S) +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V 0x00000001U +#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S 14 +/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L1_CH2 (BIT(15)) +#define DMA2D_INFIFO_FULL_L1_CH2_M (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S) +#define DMA2D_INFIFO_FULL_L1_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L1_CH2_S 15 +/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L1_CH2 (BIT(16)) +#define DMA2D_INFIFO_EMPTY_L1_CH2_M (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S) +#define DMA2D_INFIFO_EMPTY_L1_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L1_CH2_S 16 +/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L1_CH2 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH2_M (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S) +#define DMA2D_INFIFO_CNT_L1_CH2_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L1_CH2_S 17 +/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0; + * Rx FIFO full signal for Rx channel 0. + */ +#define DMA2D_INFIFO_FULL_L3_CH2 (BIT(22)) +#define DMA2D_INFIFO_FULL_L3_CH2_M (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S) +#define DMA2D_INFIFO_FULL_L3_CH2_V 0x00000001U +#define DMA2D_INFIFO_FULL_L3_CH2_S 22 +/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1; + * Rx FIFO empty signal for Rx channel 0. + */ +#define DMA2D_INFIFO_EMPTY_L3_CH2 (BIT(23)) +#define DMA2D_INFIFO_EMPTY_L3_CH2_M (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S) +#define DMA2D_INFIFO_EMPTY_L3_CH2_V 0x00000001U +#define DMA2D_INFIFO_EMPTY_L3_CH2_S 23 +/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0; + * The register stores the byte number of the data in Rx FIFO for Rx channel 0. + */ +#define DMA2D_INFIFO_CNT_L3_CH2 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH2_M (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S) +#define DMA2D_INFIFO_CNT_L3_CH2_V 0x0000001FU +#define DMA2D_INFIFO_CNT_L3_CH2_S 24 + +/** DMA2D_IN_POP_CH2_REG register + * Configures the rx fifo of channel 2 + */ +#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718) +/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024; + * This register stores the data popping from DMA Rx FIFO. + */ +#define DMA2D_INFIFO_RDATA_CH2 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH2_M (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S) +#define DMA2D_INFIFO_RDATA_CH2_V 0x000007FFU +#define DMA2D_INFIFO_RDATA_CH2_S 0 +/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0; + * Set this bit to pop data from DMA Rx FIFO. + */ +#define DMA2D_INFIFO_POP_CH2 (BIT(11)) +#define DMA2D_INFIFO_POP_CH2_M (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S) +#define DMA2D_INFIFO_POP_CH2_V 0x00000001U +#define DMA2D_INFIFO_POP_CH2_S 11 + +/** DMA2D_IN_LINK_CONF_CH2_REG register + * Configures the rx descriptor operations of channel 2 + */ +#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c) +/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Configure the value of the owner field written back to the inlink descriptor. + * 1: Write back 1. 0: Write back 0. + */ +#define DMA2D_INLINK_AUTO_RET_CH2 (BIT(20)) +#define DMA2D_INLINK_AUTO_RET_CH2_M (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S) +#define DMA2D_INLINK_AUTO_RET_CH2_V 0x00000001U +#define DMA2D_INLINK_AUTO_RET_CH2_S 20 +/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define DMA2D_INLINK_STOP_CH2 (BIT(21)) +#define DMA2D_INLINK_STOP_CH2_M (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S) +#define DMA2D_INLINK_STOP_CH2_V 0x00000001U +#define DMA2D_INLINK_STOP_CH2_S 21 +/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define DMA2D_INLINK_START_CH2 (BIT(22)) +#define DMA2D_INLINK_START_CH2_M (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S) +#define DMA2D_INLINK_START_CH2_V 0x00000001U +#define DMA2D_INLINK_START_CH2_S 22 +/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define DMA2D_INLINK_RESTART_CH2 (BIT(23)) +#define DMA2D_INLINK_RESTART_CH2_M (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S) +#define DMA2D_INLINK_RESTART_CH2_V 0x00000001U +#define DMA2D_INLINK_RESTART_CH2_S 23 +/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define DMA2D_INLINK_PARK_CH2 (BIT(24)) +#define DMA2D_INLINK_PARK_CH2_M (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S) +#define DMA2D_INLINK_PARK_CH2_V 0x00000001U +#define DMA2D_INLINK_PARK_CH2_S 24 + +/** DMA2D_IN_LINK_ADDR_CH2_REG register + * Configures the rx descriptor address of channel 2 + */ +#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720) +/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the first inlink descriptor's address. + */ +#define DMA2D_INLINK_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH2_M (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S) +#define DMA2D_INLINK_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_ADDR_CH2_S 0 + +/** DMA2D_IN_STATE_CH2_REG register + * Represents the working status of the rx descriptor of channel 2 + */ +#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724) +/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define DMA2D_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH2_M (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S) +#define DMA2D_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define DMA2D_INLINK_DSCR_ADDR_CH2_S 0 +/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define DMA2D_IN_DSCR_STATE_CH2 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH2_M (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S) +#define DMA2D_IN_DSCR_STATE_CH2_V 0x00000003U +#define DMA2D_IN_DSCR_STATE_CH2_S 18 +/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define DMA2D_IN_STATE_CH2 0x00000007U +#define DMA2D_IN_STATE_CH2_M (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S) +#define DMA2D_IN_STATE_CH2_V 0x00000007U +#define DMA2D_IN_STATE_CH2_S 20 +/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1; + * This register indicate that if the channel reset is safety. + */ +#define DMA2D_IN_RESET_AVAIL_CH2 (BIT(23)) +#define DMA2D_IN_RESET_AVAIL_CH2_M (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S) +#define DMA2D_IN_RESET_AVAIL_CH2_V 0x00000001U +#define DMA2D_IN_RESET_AVAIL_CH2_S 23 + +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728) +/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S) +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c) +/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. + */ +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S) +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** DMA2D_IN_DSCR_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730) +/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the next inlink descriptor address x. + */ +#define DMA2D_INLINK_DSCR_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH2_M (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S) +#define DMA2D_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_CH2_S 0 + +/** DMA2D_IN_DSCR_BF0_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734) +/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor's next address x-1. + */ +#define DMA2D_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH2_M (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S) +#define DMA2D_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF0_CH2_S 0 + +/** DMA2D_IN_DSCR_BF1_CH2_REG register + * Represents the address associated with the inlink descriptor of channel 2 + */ +#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738) +/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor's next address x-2. + */ +#define DMA2D_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH2_M (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S) +#define DMA2D_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define DMA2D_INLINK_DSCR_BF1_CH2_S 0 + +/** DMA2D_IN_PERI_SEL_CH2_REG register + * Configures the rx peripheral of channel 2 + */ +#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c) +/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7; + * This register is used to select peripheral for Rx channel 0: jpeg 1: + * display-1 2: display-2 7: no choose + */ +#define DMA2D_IN_PERI_SEL_CH2 0x00000007U +#define DMA2D_IN_PERI_SEL_CH2_M (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S) +#define DMA2D_IN_PERI_SEL_CH2_V 0x00000007U +#define DMA2D_IN_PERI_SEL_CH2_S 0 + +/** DMA2D_IN_ARB_CH2_REG register + * Configures the rx arbiter of channel 2 + */ +#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740) +/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1; + * Set the max number of token count of arbiter + */ +#define DMA2D_IN_ARB_TOKEN_NUM_CH2 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S) +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V 0x0000000FU +#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S 0 +/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [7:4]; default: 1; + * Set the priority of channel + */ +#define DMA2D_IN_ARB_PRIORITY_CH2 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH2_M (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S) +#define DMA2D_IN_ARB_PRIORITY_CH2_V 0x0000000FU +#define DMA2D_IN_ARB_PRIORITY_CH2_S 4 + +/** DMA2D_IN_RO_STATUS_CH2_REG register + * Represents the status of the rx reorder module of channel 2 + */ +#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744) +/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0; + * The register stores the byte number of the data in color convert Rx FIFO for + * channel 0. + */ +#define DMA2D_INFIFO_RO_CNT_CH2 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH2_M (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S) +#define DMA2D_INFIFO_RO_CNT_CH2_V 0x0000001FU +#define DMA2D_INFIFO_RO_CNT_CH2_S 0 +/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0; + * The register stores the state of read ram of reorder + */ +#define DMA2D_IN_RO_WR_STATE_CH2 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH2_M (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S) +#define DMA2D_IN_RO_WR_STATE_CH2_V 0x00000003U +#define DMA2D_IN_RO_WR_STATE_CH2_S 5 +/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0; + * The register stores the state of write ram of reorder + */ +#define DMA2D_IN_RO_RD_STATE_CH2 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH2_M (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S) +#define DMA2D_IN_RO_RD_STATE_CH2_V 0x00000003U +#define DMA2D_IN_RO_RD_STATE_CH2_S 7 +/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0; + * the number of bytes contained in a pixel at RX channel 0: 1byte 1: 1.5bytes + * 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes + */ +#define DMA2D_IN_PIXEL_BYTE_CH2 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH2_M (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S) +#define DMA2D_IN_PIXEL_BYTE_CH2_V 0x0000000FU +#define DMA2D_IN_PIXEL_BYTE_CH2_S 9 +/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0; + * the number of macro blocks contained in a burst of data at RX channel + */ +#define DMA2D_IN_BURST_BLOCK_NUM_CH2 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S) +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V 0x0000000FU +#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S 13 + +/** DMA2D_IN_ETM_CONF_CH2_REG register + * Configures the rx etm of channel 2 + */ +#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c) +/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0; + * Configures the enable of the etm function, 1 is enable. + */ +#define DMA2D_IN_ETM_EN_CH2 (BIT(0)) +#define DMA2D_IN_ETM_EN_CH2_M (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S) +#define DMA2D_IN_ETM_EN_CH2_V 0x00000001U +#define DMA2D_IN_ETM_EN_CH2_S 0 +/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0; + * Configures the enable of the descriptors loop etm function, 1 is enable. + */ +#define DMA2D_IN_ETM_LOOP_EN_CH2 (BIT(1)) +#define DMA2D_IN_ETM_LOOP_EN_CH2_M (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S) +#define DMA2D_IN_ETM_LOOP_EN_CH2_V 0x00000001U +#define DMA2D_IN_ETM_LOOP_EN_CH2_S 1 +/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1; + * Configures the maximum number of cacheable descriptors. + */ +#define DMA2D_IN_DSCR_TASK_MAK_CH2 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH2_M (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S) +#define DMA2D_IN_DSCR_TASK_MAK_CH2_V 0x00000003U +#define DMA2D_IN_DSCR_TASK_MAK_CH2_S 2 + /** DMA2D_AXI_ERR_REG register * Represents the status of th axi bus */ @@ -5257,7 +7177,7 @@ extern "C" { * register version. */ #define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c) -/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 36716816; +/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 37822864; * register version. */ #define DMA2D_DATE 0xFFFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h index 30fef532db..7105d670bc 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h @@ -10,11 +10,8 @@ extern "C" { #endif -//TODO: IDF-13427 - -/** Group: out */ /** Type of out_conf0_chn register - * Configures the tx direction of channel 0 + * Configures the tx direction of channel n */ typedef union { struct { @@ -48,7 +45,7 @@ typedef union { */ uint32_t out_loop_test_chn:1; /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0; - * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 + * Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64 * bytes 4: 128 bytes */ uint32_t out_mem_burst_length_chn:3; @@ -92,7 +89,7 @@ typedef union { } dma2d_out_conf0_chn_reg_t; /** Type of out_int_raw_chn register - * Raw interrupt status of TX channel 0 + * Raw interrupt status of TX channel n */ typedef union { struct { @@ -160,7 +157,7 @@ typedef union { } dma2d_out_int_raw_chn_reg_t; /** Type of out_int_ena_chn register - * Interrupt enable bits of TX channel 0 + * Interrupt enable bits of TX channel n */ typedef union { struct { @@ -222,7 +219,7 @@ typedef union { } dma2d_out_int_ena_chn_reg_t; /** Type of out_int_st_chn register - * Masked interrupt status of TX channel 0 + * Masked interrupt status of TX channel n */ typedef union { struct { @@ -284,7 +281,7 @@ typedef union { } dma2d_out_int_st_chn_reg_t; /** Type of out_int_clr_chn register - * Interrupt clear bits of TX channel 0 + * Interrupt clear bits of TX channel n */ typedef union { struct { @@ -346,20 +343,20 @@ typedef union { } dma2d_out_int_clr_chn_reg_t; /** Type of outfifo_status_chn register - * Represents the status of the tx fifo of channel 0 + * Represents the status of the tx fifo of channel n */ typedef union { struct { /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l2_chn:1; /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l2_chn:1; /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l2_chn:4; uint32_t reserved_6:1; @@ -396,27 +393,27 @@ typedef union { */ uint32_t out_remain_under_8b_chn:1; /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l1_chn:1; /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l1_chn:1; /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l1_chn:5; /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_l3_chn:1; /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_l3_chn:1; /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_l3_chn:5; uint32_t reserved_29:3; @@ -425,7 +422,7 @@ typedef union { } dma2d_outfifo_status_chn_reg_t; /** Type of out_push_chn register - * Configures the tx fifo of channel 0 + * Configures the tx fifo of channel n */ typedef union { struct { @@ -443,7 +440,7 @@ typedef union { } dma2d_out_push_chn_reg_t; /** Type of out_link_conf_chn register - * Configures the tx descriptor operations of channel 0 + * Configures the tx descriptor operations of channel n */ typedef union { struct { @@ -471,7 +468,7 @@ typedef union { } dma2d_out_link_conf_chn_reg_t; /** Type of out_link_addr_chn register - * Configures the tx descriptor address of channel 0 + * Configures the tx descriptor address of channel n */ typedef union { struct { @@ -484,7 +481,7 @@ typedef union { } dma2d_out_link_addr_chn_reg_t; /** Type of out_state_chn register - * Represents the working status of the tx descriptor of channel 0 + * Represents the working status of the tx descriptor of channel n */ typedef union { struct { @@ -510,7 +507,7 @@ typedef union { } dma2d_out_state_chn_reg_t; /** Type of out_eof_des_addr_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -524,7 +521,7 @@ typedef union { } dma2d_out_eof_des_addr_chn_reg_t; /** Type of out_dscr_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -537,7 +534,7 @@ typedef union { } dma2d_out_dscr_chn_reg_t; /** Type of out_dscr_bf0_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -550,7 +547,7 @@ typedef union { } dma2d_out_dscr_bf0_chn_reg_t; /** Type of out_dscr_bf1_chn register - * Represents the address associated with the outlink descriptor of channel 0 + * Represents the address associated with the outlink descriptor of channel n */ typedef union { struct { @@ -563,7 +560,7 @@ typedef union { } dma2d_out_dscr_bf1_chn_reg_t; /** Type of out_peri_sel_chn register - * Configures the tx peripheral of channel 0 + * Configures the tx peripheral of channel n */ typedef union { struct { @@ -578,7 +575,7 @@ typedef union { } dma2d_out_peri_sel_chn_reg_t; /** Type of out_arb_chn register - * Configures the tx arbiter of channel 0 + * Configures the tx arbiter of channel n */ typedef union { struct { @@ -586,17 +583,17 @@ typedef union { * Set the max number of token count of arbiter */ uint32_t out_arb_token_num_chn:4; - /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1; + /** out_arb_priority_chn : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ - uint32_t out_arb_priority_chn:2; - uint32_t reserved_6:26; + uint32_t out_arb_priority_chn:4; + uint32_t reserved_8:24; }; uint32_t val; } dma2d_out_arb_chn_reg_t; /** Type of out_ro_status_chn register - * Represents the status of the tx reorder module of channel 0 + * Represents the status of the tx reorder module of channel n */ typedef union { struct { @@ -628,7 +625,7 @@ typedef union { } dma2d_out_ro_status_chn_reg_t; /** Type of out_ro_pd_conf_chn register - * Configures the tx reorder memory of channel 0 + * Configures the tx reorder memory of channel n */ typedef union { struct { @@ -652,7 +649,7 @@ typedef union { } dma2d_out_ro_pd_conf_chn_reg_t; /** Type of out_color_convert_chn register - * Configures the tx color convert of channel 0 + * Configures the tx color convert of channel n */ typedef union { struct { @@ -678,7 +675,7 @@ typedef union { } dma2d_out_color_convert_chn_reg_t; /** Type of out_scramble_chn register - * Configures the tx scramble of channel 0 + * Configures the tx scramble of channel n */ typedef union { struct { @@ -693,7 +690,7 @@ typedef union { } dma2d_out_scramble_chn_reg_t; /** Type of out_etm_conf_chn register - * Configures the tx etm of channel 0 + * Configures the tx etm of channel n */ typedef union { struct { @@ -732,10 +729,8 @@ typedef union { uint32_t val; } dma2d_out_dscr_port_blk_chn_reg_t; - -/** Group: in */ /** Type of in_conf0_chn register - * Configures the rx direction of channel 0 + * Configures the rx direction of channel n */ typedef union { struct { @@ -808,7 +803,7 @@ typedef union { } dma2d_in_conf0_chn_reg_t; /** Type of in_int_raw_chn register - * Raw interrupt status of RX channel 0 + * Raw interrupt status of RX channel n */ typedef union { struct { @@ -880,7 +875,7 @@ typedef union { } dma2d_in_int_raw_chn_reg_t; /** Type of in_int_ena_chn register - * Interrupt enable bits of RX channel 0 + * Interrupt enable bits of RX channel n */ typedef union { struct { @@ -946,7 +941,7 @@ typedef union { } dma2d_in_int_ena_chn_reg_t; /** Type of in_int_st_chn register - * Masked interrupt status of RX channel 0 + * Masked interrupt status of RX channel n */ typedef union { struct { @@ -1012,7 +1007,7 @@ typedef union { } dma2d_in_int_st_chn_reg_t; /** Type of in_int_clr_chn register - * Interrupt clear bits of RX channel 0 + * Interrupt clear bits of RX channel n */ typedef union { struct { @@ -1078,20 +1073,20 @@ typedef union { } dma2d_in_int_clr_chn_reg_t; /** Type of infifo_status_chn register - * Represents the status of the rx fifo of channel 0 + * Represents the status of the rx fifo of channel n */ typedef union { struct { /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0; - * Rx FIFO full signal for Rx channel. + * Rx FIFO full signal for Rx channel n. */ uint32_t infifo_full_l2_chn:1; /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1; - * Rx FIFO empty signal for Rx channel. + * Rx FIFO empty signal for Rx channel n. */ uint32_t infifo_empty_l2_chn:1; /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0; - * The register stores the byte number of the data in Rx FIFO for Rx channel. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l2_chn:4; uint32_t reserved_6:1; @@ -1128,27 +1123,27 @@ typedef union { */ uint32_t in_remain_under_8b_chn:1; /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Tx channel n. */ uint32_t infifo_full_l1_chn:1; /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Tx channel n. */ uint32_t infifo_empty_l1_chn:1; /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l1_chn:5; /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0; - * Tx FIFO full signal for Tx channel 0. + * Rx FIFO full signal for Rx channel n. */ uint32_t infifo_full_l3_chn:1; /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1; - * Tx FIFO empty signal for Tx channel 0. + * Rx FIFO empty signal for Rx channel n. */ uint32_t infifo_empty_l3_chn:1; /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0; - * The register stores the byte number of the data in Tx FIFO for Tx channel 0. + * The register stores the byte number of the data in Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_l3_chn:5; uint32_t reserved_29:3; @@ -1157,7 +1152,7 @@ typedef union { } dma2d_infifo_status_chn_reg_t; /** Type of in_pop_chn register - * Configures the rx fifo of channel 0 + * Configures the rx fifo of channel n */ typedef union { struct { @@ -1175,7 +1170,7 @@ typedef union { } dma2d_in_pop_chn_reg_t; /** Type of in_link_conf_chn register - * Configures the rx descriptor operations of channel 0 + * Configures the rx descriptor operations of channel n */ typedef union { struct { @@ -1208,7 +1203,7 @@ typedef union { } dma2d_in_link_conf_chn_reg_t; /** Type of in_link_addr_chn register - * Configures the rx descriptor address of channel 0 + * Configures the rx descriptor address of channel n */ typedef union { struct { @@ -1221,7 +1216,7 @@ typedef union { } dma2d_in_link_addr_chn_reg_t; /** Type of in_state_chn register - * Represents the working status of the rx descriptor of channel 0 + * Represents the working status of the rx descriptor of channel n */ typedef union { struct { @@ -1247,7 +1242,7 @@ typedef union { } dma2d_in_state_chn_reg_t; /** Type of in_suc_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1261,7 +1256,7 @@ typedef union { } dma2d_in_suc_eof_des_addr_chn_reg_t; /** Type of in_err_eof_des_addr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1275,7 +1270,7 @@ typedef union { } dma2d_in_err_eof_des_addr_chn_reg_t; /** Type of in_dscr_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1288,7 +1283,7 @@ typedef union { } dma2d_in_dscr_chn_reg_t; /** Type of in_dscr_bf0_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1301,7 +1296,7 @@ typedef union { } dma2d_in_dscr_bf0_chn_reg_t; /** Type of in_dscr_bf1_chn register - * Represents the address associated with the inlink descriptor of channel 0 + * Represents the address associated with the inlink descriptor of channel n */ typedef union { struct { @@ -1314,7 +1309,7 @@ typedef union { } dma2d_in_dscr_bf1_chn_reg_t; /** Type of in_peri_sel_chn register - * Configures the rx peripheral of channel 0 + * Configures the rx peripheral of channel n */ typedef union { struct { @@ -1329,7 +1324,7 @@ typedef union { } dma2d_in_peri_sel_chn_reg_t; /** Type of in_arb_chn register - * Configures the rx arbiter of channel 0 + * Configures the rx arbiter of channel n */ typedef union { struct { @@ -1337,17 +1332,17 @@ typedef union { * Set the max number of token count of arbiter */ uint32_t in_arb_token_num_chn:4; - /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1; + /** in_arb_priority_chn : R/W; bitpos: [7:4]; default: 1; * Set the priority of channel */ - uint32_t in_arb_priority_chn:1; - uint32_t reserved_5:27; + uint32_t in_arb_priority_chn:4; + uint32_t reserved_8:24; }; uint32_t val; } dma2d_in_arb_chn_reg_t; /** Type of in_ro_status_chn register - * Represents the status of the rx reorder module of channel 0 + * Represents the status of the rx reorder module of channel n */ typedef union { struct { @@ -1379,7 +1374,7 @@ typedef union { } dma2d_in_ro_status_chn_reg_t; /** Type of in_ro_pd_conf_chn register - * Configures the rx reorder memory of channel 0 + * Configures the rx reorder memory of channel n */ typedef union { struct { @@ -1403,13 +1398,13 @@ typedef union { } dma2d_in_ro_pd_conf_chn_reg_t; /** Type of in_color_convert_chn register - * Configures the tx color convert of channel 0 + * Configures the Rx color convert of channel n */ typedef union { struct { /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0; * Set final color convert process and output type 0: RGB888 to RGB565 1: - * output directly + * output directly 2: YUV444 to YUV422 3: YUV444 to YUV420 */ uint32_t in_color_output_sel_chn:2; /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0; @@ -1428,7 +1423,7 @@ typedef union { } dma2d_in_color_convert_chn_reg_t; /** Type of in_scramble_chn register - * Configures the rx scramble of channel 0 + * Configures the rx scramble of channel n */ typedef union { struct { @@ -1448,7 +1443,7 @@ typedef union { } dma2d_in_scramble_chn_reg_t; /** Type of in_etm_conf_chn register - * Configures the rx etm of channel 0 + * Configures the rx etm of channel n */ typedef union { struct { @@ -1469,8 +1464,6 @@ typedef union { uint32_t val; } dma2d_in_etm_conf_chn_reg_t; - -/** Group: Status Registers */ /** Type of axi_err register * Represents the status of th axi bus */ @@ -1514,7 +1507,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36716816; + /** date : R/W; bitpos: [31:0]; default: 37822864; * register version. */ uint32_t date:32; @@ -1522,8 +1515,6 @@ typedef union { uint32_t val; } dma2d_date_reg_t; - -/** Group: Configuration Registers */ /** Type of rst_conf register * Configures the reset of axi */ @@ -1681,7 +1672,6 @@ typedef union { uint32_t val; } dma2d_rdn_eco_low_reg_t; - /** Type of in/out_color_param_h/m/l_chn register * Configures the rx/tx color convert parameter of channel n */ @@ -1713,12 +1703,14 @@ typedef union { uint32_t val[2]; } dma2d_color_param_reg_t; + typedef struct { volatile dma2d_color_param_reg_t param_h; volatile dma2d_color_param_reg_t param_m; volatile dma2d_color_param_reg_t param_l; } dma2d_color_param_group_chn_reg_t; + typedef struct { volatile dma2d_out_conf0_chn_reg_t out_conf0; volatile dma2d_out_int_raw_chn_reg_t out_int_raw; @@ -1746,32 +1738,6 @@ typedef struct { uint32_t reserved_out[36]; } dma2d_out_chn_reg_t; -typedef struct { - volatile dma2d_in_conf0_chn_reg_t in_conf0; - volatile dma2d_in_int_raw_chn_reg_t in_int_raw; - volatile dma2d_in_int_ena_chn_reg_t in_int_ena; - volatile dma2d_in_int_st_chn_reg_t in_int_st; - volatile dma2d_in_int_clr_chn_reg_t in_int_clr; - volatile dma2d_infifo_status_chn_reg_t infifo_status; - volatile dma2d_in_pop_chn_reg_t in_pop; - volatile dma2d_in_link_conf_chn_reg_t in_link_conf; - volatile dma2d_in_link_addr_chn_reg_t in_link_addr; - volatile dma2d_in_state_chn_reg_t in_state; - volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; - volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; - volatile dma2d_in_dscr_chn_reg_t in_dscr; - volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0; - volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1; - volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; - volatile dma2d_in_arb_chn_reg_t in_arb; - volatile dma2d_in_ro_status_chn_reg_t in_ro_status; - volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; - volatile dma2d_in_color_convert_chn_reg_t in_color_convert; - volatile dma2d_in_scramble_chn_reg_t in_scramble; - volatile dma2d_color_param_group_chn_reg_t in_color_param_group; - volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_570[36]; -} dma2d_in_ch0_reg_t; typedef struct { volatile dma2d_in_conf0_chn_reg_t in_conf0; @@ -1792,16 +1758,20 @@ typedef struct { volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel; volatile dma2d_in_arb_chn_reg_t in_arb; volatile dma2d_in_ro_status_chn_reg_t in_ro_status; + volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */ + volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */ + volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */ + volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */ volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; - uint32_t reserved_64c[45]; -} dma2d_in_ch1_reg_t; + uint32_t reserved_in[36]; +} dma2d_in_chn_reg_t; + typedef struct dma2d_dev_t { - volatile dma2d_out_chn_reg_t out_channel[3]; - uint32_t reserved_300[128]; - volatile dma2d_in_ch0_reg_t in_channel0; - volatile dma2d_in_ch1_reg_t in_channel1; - uint32_t reserved_700[192]; + volatile dma2d_out_chn_reg_t out_channel[4]; + uint32_t reserved_400[64]; + volatile dma2d_in_chn_reg_t in_channel[3]; + uint32_t reserved_800[128]; volatile dma2d_axi_err_reg_t axi_err; volatile dma2d_rst_conf_reg_t rst_conf; volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;