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gdma: dynamic alloc DMA channels

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This commit is contained in:
morris
2020-12-09 20:29:26 +08:00
parent e277d8ef23
commit e6d23a35ec
28 changed files with 1211 additions and 59 deletions
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7
components/soc/esp32s3/include/soc/gdma_caps.h
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@@ -14,6 +14,7 @@
#pragma once
#define SOC_GDMA_CHANNELS_NUM (5) /*!< GDMA has 5 TX and 5 RX channels in ESP32-S3 */
#define SOC_GDMA_L2_FIFO_BASE_SIZE (16) /*!< GDMA L2 FIFO basic size is 16 Bytes */
#define SOC_GDMA_SUPPORT_EXTMEM (1)
#define SOC_GDMA_GROUPS (1)
#define SOC_GDMA_PAIRS_PER_GROUP (5)
#define SOC_GDMA_L2_FIFO_BASE_SIZE (16)
#define SOC_GDMA_SUPPORT_EXTMEM (1)

29
components/soc/esp32s3/include/soc/gdma_channel.h Normal file
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@@ -0,0 +1,29 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_SPI3 (1)
#define SOC_GDMA_TRIG_PERIPH_UART0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_I2S1 (4)
#define SOC_GDMA_TRIG_PERIPH_LCD0 (5)
#define SOC_GDMA_TRIG_PERIPH_CAM0 (5)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_DAC0 (8)

1
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -151,7 +151,6 @@
// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
// Remove them when GDMA driver API is ready
#define SOC_GDMA_M2M_DMA_CHANNEL (0)
#define SOC_GDMA_SPI2_DMA_CHANNEL (1)
#define SOC_GDMA_SPI3_DMA_CHANNEL (2)
#define SOC_GDMA_SHA_DMA_CHANNEL (3)