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feat(bluetooth/controller): adopting new HCI layer code and support UHCI function on ESP32-C6 and ESP32-H2

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This commit is contained in:
zwl
2024-07-04 21:14:14 +08:00
committed by Zhao Wei Liang
parent 1390711c27
commit e761c1de8f
12 changed files with 450 additions and 379 deletions
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62
components/bt/controller/esp32c6/Kconfig.in
View File

@@ -2,19 +2,37 @@
menu "HCI Config" menu "HCI Config"
choice BT_LE_HCI_INTERFACE choice BT_LE_HCI_INTERFACE
prompt "Select HCI interface" prompt "HCI mode"
default BT_LE_HCI_INTERFACE_USE_RAM default BT_LE_HCI_INTERFACE_USE_RAM
config BT_LE_HCI_INTERFACE_USE_RAM config BT_LE_HCI_INTERFACE_USE_RAM
bool "ram" bool "VHCI"
help help
Use RAM as HCI interface Use RAM as HCI interface
config BT_LE_HCI_INTERFACE_USE_UART config BT_LE_HCI_INTERFACE_USE_UART
bool "uart" bool "UART(H4)"
help help
Use UART as HCI interface Use UART as HCI interface
endchoice endchoice
choice BT_LE_UART_HCI_MODE_CHOICE
prompt "UART HCI mode"
depends on BT_LE_HCI_INTERFACE_USE_UART
default BT_LE_UART_HCI_NO_DMA_MODE
help
Specify UART HCI mode: DMA or No DMA
config BT_LE_UART_HCI_DMA_MODE
bool "UHCI(UART with DMA)(EXPERIMENTAL)"
help
UART HCI Mode with DMA functionality.
config BT_LE_UART_HCI_NO_DMA_MODE
bool "UART(NO DMA)"
help
UART HCI Mode without DMA functionality.
endchoice
config BT_LE_HCI_UART_PORT config BT_LE_HCI_UART_PORT
int "HCI UART port" int "HCI UART port"
depends on BT_LE_HCI_INTERFACE_USE_UART depends on BT_LE_HCI_INTERFACE_USE_UART
@@ -73,12 +91,40 @@ menu "HCI Config"
UART_PARITY_ODD UART_PARITY_ODD
endchoice endchoice
config BT_LE_HCI_UART_TASK_STACK_SIZE config BT_LE_HCI_UART_RX_BUFFER_SIZE
int "HCI uart task stack size" int "The size of rx ring buffer memory"
depends on BT_LE_HCI_INTERFACE_USE_UART depends on BT_LE_UART_HCI_NO_DMA_MODE
default 1000 default 512
help help
Set the size of uart task stack The size of rx ring buffer memory
config BT_LE_HCI_UART_TX_BUFFER_SIZE
int "The size of tx ring buffer memory"
depends on BT_LE_UART_HCI_NO_DMA_MODE
default 256
help
The size of tx ring buffer memory
config BT_LE_HCI_TRANS_TASK_STACK_SIZE
int "HCI transport task stack size"
depends on !BT_LE_HCI_INTERFACE_USE_RAM
default 1024
help
This configures stack size of hci transport task
config BT_LE_HCI_TRANS_RX_MEM_NUM
int "The amount of rx memory received at the same time"
depends on BT_LE_UART_HCI_DMA_MODE
default 3
help
The amount of rx memory received at the same time
config BT_LE_HCI_LLDESCS_POOL_NUM
int "The amount of lldecs memory for driver dma mode"
depends on BT_LE_UART_HCI_DMA_MODE
default 20
help
The amount of lldecs memory for driver dma mode
endmenu endmenu
config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT

178
components/bt/controller/esp32c6/bt.c
View File

@@ -30,7 +30,7 @@
#endif // CONFIG_ESP_COEX_ENABLED #endif // CONFIG_ESP_COEX_ENABLED
#include "nimble/nimble_npl_os.h" #include "nimble/nimble_npl_os.h"
#include "ble_hci_trans.h" #include "esp_hci_transport.h"
#include "os/endian.h" #include "os/endian.h"
#include "esp_bt.h" #include "esp_bt.h"
@@ -41,7 +41,6 @@
#include "esp_phy_init.h" #include "esp_phy_init.h"
#endif #endif
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
#include "hci_uart.h"
#include "bt_osi_mem.h" #include "bt_osi_mem.h"
#if SOC_PM_RETENTION_HAS_CLOCK_BUG #if SOC_PM_RETENTION_HAS_CLOCK_BUG
@@ -52,10 +51,6 @@
#include "esp_private/sleep_modem.h" #include "esp_private/sleep_modem.h"
#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#include "hci/hci_hal.h"
#endif // CONFIG_BT_BLUEDROID_ENABLED
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
@@ -71,16 +66,11 @@
#define OSI_COEX_VERSION 0x00010006 #define OSI_COEX_VERSION 0x00010006
#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD #define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
#define EXT_FUNC_VERSION 0x20221122 #define EXT_FUNC_VERSION 0x20240422
#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
#define BT_ASSERT_PRINT ets_printf #define BT_ASSERT_PRINT ets_printf
#ifdef CONFIG_BT_BLUEDROID_ENABLED
/* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */
#define ACL_DATA_MBUF_LEADINGSPCAE 4
#endif // CONFIG_BT_BLUEDROID_ENABLED
/* Types definition /* Types definition
************************************************************************ ************************************************************************
*/ */
@@ -99,12 +89,6 @@ struct ext_funcs_t {
int (*_esp_intr_free)(void **ret_handle); int (*_esp_intr_free)(void **ret_handle);
void *(* _malloc)(size_t size); void *(* _malloc)(size_t size);
void (*_free)(void *p); void (*_free)(void *p);
void (*_hal_uart_start_tx)(int);
int (*_hal_uart_init_cbs)(int, hci_uart_tx_char, hci_uart_tx_done, hci_uart_rx_char, void *);
int (*_hal_uart_config)(int, int32_t, uint8_t, uint8_t, uart_parity_t, uart_hw_flowcontrol_t);
int (*_hal_uart_close)(int);
void (*_hal_uart_blocking_tx)(int, uint8_t);
int (*_hal_uart_init)(int, void *);
int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param,
uint32_t prio, void *task_handle, uint32_t core_id); uint32_t prio, void *task_handle, uint32_t core_id);
void (* _task_delete)(void *task_handle); void (* _task_delete)(void *task_handle);
@@ -181,16 +165,6 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
void *param, uint32_t prio, void *task_handle, uint32_t core_id); void *param, uint32_t prio, void *task_handle, uint32_t core_id);
static void task_delete_wrapper(void *task_handle); static void task_delete_wrapper(void *task_handle);
#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static void hci_uart_start_tx_wrapper(int uart_no);
static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg);
static int hci_uart_config_wrapper(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits,
uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl);
static int hci_uart_close_wrapper(int uart_no);
static void hci_uart_blocking_tx_wrapper(int port, uint8_t data);
static int hci_uart_init_wrapper(int uart_no, void *cfg);
#endif // CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
void *arg, void **ret_handle_in); void *arg, void **ret_handle_in);
static int esp_intr_free_wrapper(void **ret_handle); static int esp_intr_free_wrapper(void **ret_handle);
@@ -208,7 +182,6 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
*/ */
/* Static variable declare */ /* Static variable declare */
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE}; const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
@@ -238,14 +211,6 @@ struct ext_funcs_t ext_funcs_ro = {
._esp_intr_free = esp_intr_free_wrapper, ._esp_intr_free = esp_intr_free_wrapper,
._malloc = bt_osi_mem_malloc_internal, ._malloc = bt_osi_mem_malloc_internal,
._free = bt_osi_mem_free, ._free = bt_osi_mem_free,
#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
._hal_uart_start_tx = hci_uart_start_tx_wrapper,
._hal_uart_init_cbs = hci_uart_init_cbs_wrapper,
._hal_uart_config = hci_uart_config_wrapper,
._hal_uart_close = hci_uart_close_wrapper,
._hal_uart_blocking_tx = hci_uart_blocking_tx_wrapper,
._hal_uart_init = hci_uart_init_wrapper,
#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
._task_create = task_create_wrapper, ._task_create = task_create_wrapper,
._task_delete = task_delete_wrapper, ._task_delete = task_delete_wrapper,
._osi_assert = osi_assert_wrapper, ._osi_assert = osi_assert_wrapper,
@@ -290,75 +255,6 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
#endif // CONFIG_SW_COEXIST_ENABLE #endif // CONFIG_SW_COEXIST_ENABLE
} }
#ifdef CONFIG_BT_BLUEDROID_ENABLED
bool esp_vhci_host_check_send_available(void)
{
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
return false;
}
return true;
}
static struct os_mbuf *ble_hs_mbuf_gen_pkt(uint16_t leading_space)
{
struct os_mbuf *om;
int rc;
om = os_msys_get_pkthdr(0, 0);
if (om == NULL) {
return NULL;
}
if (om->om_omp->omp_databuf_len < leading_space) {
rc = os_mbuf_free_chain(om);
assert(rc == 0);
return NULL;
}
om->om_data += leading_space;
return om;
}
struct os_mbuf *ble_hs_mbuf_acl_pkt(void)
{
return ble_hs_mbuf_gen_pkt(4 + 1);
}
void esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
{
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
return;
}
if (*(data) == DATA_TYPE_COMMAND) {
struct ble_hci_cmd *cmd = NULL;
cmd = (struct ble_hci_cmd *) ble_hci_trans_buf_alloc(BLE_HCI_TRANS_BUF_CMD);
assert(cmd);
memcpy((uint8_t *)cmd, data + 1, len - 1);
ble_hci_trans_hs_cmd_tx((uint8_t *)cmd);
}
if (*(data) == DATA_TYPE_ACL) {
struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE);
assert(om);
assert(os_mbuf_append(om, &data[1], len - 1) == 0);
ble_hci_trans_hs_acl_tx(om);
}
}
esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
{
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
return ESP_FAIL;
}
ble_hci_trans_cfg_hs(ble_hs_hci_rx_evt, NULL, ble_hs_rx_data, NULL);
return ESP_OK;
}
#endif // CONFIG_BT_BLUEDROID_ENABLED
static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
void *param, uint32_t prio, void *task_handle, uint32_t core_id) void *param, uint32_t prio, void *task_handle, uint32_t core_id)
{ {
@@ -390,56 +286,6 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer
return rc; return rc;
} }
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static void hci_uart_start_tx_wrapper(int uart_no)
{
hci_uart_start_tx(uart_no);
}
static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg)
{
int rc = -1;
rc = hci_uart_init_cbs(uart_no, tx_func, tx_done, rx_func, arg);
return rc;
}
static int hci_uart_config_wrapper(int port_num, int32_t baud_rate, uint8_t data_bits,
uint8_t stop_bits, uart_parity_t parity,
uart_hw_flowcontrol_t flow_ctl)
{
int rc = -1;
rc = hci_uart_config(port_num, baud_rate, data_bits, stop_bits, parity, flow_ctl);
return rc;
}
static int hci_uart_close_wrapper(int uart_no)
{
int rc = -1;
rc = hci_uart_close(uart_no);
return rc;
}
static void hci_uart_blocking_tx_wrapper(int port, uint8_t data)
{
//This function is nowhere to use.
}
static int hci_uart_init_wrapper(int uart_no, void *cfg)
{
//This function is nowhere to use.
return 0;
}
#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static int ble_hci_unregistered_hook(void*, void*)
{
ESP_LOGD(NIMBLE_PORT_LOG_TAG,"%s ble hci rx_evt is not registered.",__func__);
return 0;
}
static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
void *arg, void **ret_handle_in) void *arg, void **ret_handle_in)
{ {
@@ -718,6 +564,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
ble_npl_count_info_t npl_info; ble_npl_count_info_t npl_info;
uint32_t slow_clk_freq = 0; uint32_t slow_clk_freq = 0;
uint8_t hci_transport_mode;
memset(&npl_info, 0, sizeof(ble_npl_count_info_t)); memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
@@ -862,11 +709,23 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
ble_hci_trans_cfg_hs((ble_hci_trans_rx_cmd_fn *)ble_hci_unregistered_hook,NULL, #if CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
(ble_hci_trans_rx_acl_fn *)ble_hci_unregistered_hook,NULL); hci_transport_mode = HCI_TRANSPORT_VHCI;
return ESP_OK; #elif CONFIG_BT_LE_HCI_INTERFACE_USE_UART
hci_transport_mode = HCI_TRANSPORT_UART_NO_DMA;
#if CONFIG_BT_LE_UART_HCI_DMA_MODE
hci_transport_mode = HCI_TRANSPORT_UART_UHCI;
#endif // CONFIG_BT_LE_UART_HCI_DMA_MODE
#endif // CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
ret = hci_transport_init(hci_transport_mode);
if (ret) {
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "hci transport init failed %d", ret);
goto free_controller;
}
return ESP_OK;
free_controller: free_controller:
hci_transport_deinit();
controller_sleep_deinit(); controller_sleep_deinit();
os_msys_deinit(); os_msys_deinit();
r_ble_controller_deinit(); r_ble_controller_deinit();
@@ -897,6 +756,7 @@ esp_err_t esp_bt_controller_deinit(void)
return ESP_FAIL; return ESP_FAIL;
} }
hci_transport_deinit();
controller_sleep_deinit(); controller_sleep_deinit();
os_msys_deinit(); os_msys_deinit();

21
components/bt/controller/esp32c6/esp_bt_cfg.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -129,6 +129,21 @@ extern "C" {
#else #else
#define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0) #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0)
#endif #endif
#if defined (CONFIG_BT_LE_HCI_UART_FLOWCTRL)
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (CONFIG_BT_LE_HCI_UART_FLOWCTRL)
#if DEFAULT_BT_LE_HCI_UART_FLOW_CTRL
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (CONFIG_BT_LE_HCI_UART_CTS_PIN)
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (CONFIG_BT_LE_HCI_UART_RTS_PIN)
#else
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (-1)
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (-1)
#endif
#else
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (-1)
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (-1)
#endif
#endif #endif
#define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF #define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF
@@ -169,8 +184,6 @@ extern "C" {
#define DEFAULT_BT_LE_HCI_UART_DATA_BITS (UART_DATA_8_BITS) #define DEFAULT_BT_LE_HCI_UART_DATA_BITS (UART_DATA_8_BITS)
#define DEFAULT_BT_LE_HCI_UART_STOP_BITS (UART_STOP_BITS_1) #define DEFAULT_BT_LE_HCI_UART_STOP_BITS (UART_STOP_BITS_1)
#define DEFAULT_BT_LE_HCI_UART_PARITY (0) #define DEFAULT_BT_LE_HCI_UART_PARITY (0)
#define DEFAULT_BT_LE_HCI_UART_TASK_STACK_SIZE (CONFIG_BT_LE_HCI_UART_TASK_STACK_SIZE)
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
#else #else
#define DEFAULT_BT_LE_HCI_UART_TX_PIN (0) #define DEFAULT_BT_LE_HCI_UART_TX_PIN (0)
#define DEFAULT_BT_LE_HCI_UART_RX_PIN (0) #define DEFAULT_BT_LE_HCI_UART_RX_PIN (0)
@@ -179,8 +192,6 @@ extern "C" {
#define DEFAULT_BT_LE_HCI_UART_DATA_BITS (0) #define DEFAULT_BT_LE_HCI_UART_DATA_BITS (0)
#define DEFAULT_BT_LE_HCI_UART_STOP_BITS (0) #define DEFAULT_BT_LE_HCI_UART_STOP_BITS (0)
#define DEFAULT_BT_LE_HCI_UART_PARITY (0) #define DEFAULT_BT_LE_HCI_UART_PARITY (0)
#define DEFAULT_BT_LE_HCI_UART_TASK_STACK_SIZE (0)
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
#endif #endif
/* Unchanged configuration */ /* Unchanged configuration */

62
components/bt/controller/esp32h2/Kconfig.in
View File

@@ -2,19 +2,37 @@
menu "HCI Config" menu "HCI Config"
choice BT_LE_HCI_INTERFACE choice BT_LE_HCI_INTERFACE
prompt "Select HCI interface" prompt "HCI mode"
default BT_LE_HCI_INTERFACE_USE_RAM default BT_LE_HCI_INTERFACE_USE_RAM
config BT_LE_HCI_INTERFACE_USE_RAM config BT_LE_HCI_INTERFACE_USE_RAM
bool "ram" bool "VHCI"
help help
Use RAM as HCI interface Use RAM as HCI interface
config BT_LE_HCI_INTERFACE_USE_UART config BT_LE_HCI_INTERFACE_USE_UART
bool "uart" bool "UART(H4)"
help help
Use UART as HCI interface Use UART as HCI interface
endchoice endchoice
choice BT_LE_UART_HCI_MODE_CHOICE
prompt "UART HCI mode"
depends on BT_LE_HCI_INTERFACE_USE_UART
default BT_LE_UART_HCI_NO_DMA_MODE
help
Specify UART HCI mode: DMA or No DMA
config BT_LE_UART_HCI_DMA_MODE
bool "UHCI(UART with DMA)(EXPERIMENTAL)"
help
UART HCI Mode with DMA functionality.
config BT_LE_UART_HCI_NO_DMA_MODE
bool "UART(NO DMA)"
help
UART HCI Mode without DMA functionality.
endchoice
config BT_LE_HCI_UART_PORT config BT_LE_HCI_UART_PORT
int "HCI UART port" int "HCI UART port"
depends on BT_LE_HCI_INTERFACE_USE_UART depends on BT_LE_HCI_INTERFACE_USE_UART
@@ -73,12 +91,40 @@ menu "HCI Config"
UART_PARITY_ODD UART_PARITY_ODD
endchoice endchoice
config BT_LE_HCI_UART_TASK_STACK_SIZE config BT_LE_HCI_UART_RX_BUFFER_SIZE
int "HCI uart task stack size" int "The size of rx ring buffer memory"
depends on BT_LE_HCI_INTERFACE_USE_UART depends on BT_LE_UART_HCI_NO_DMA_MODE
default 1000 default 512
help help
Set the size of uart task stack The size of rx ring buffer memory
config BT_LE_HCI_UART_TX_BUFFER_SIZE
int "The size of tx ring buffer memory"
depends on BT_LE_UART_HCI_NO_DMA_MODE
default 256
help
The size of tx ring buffer memory
config BT_LE_HCI_TRANS_TASK_STACK_SIZE
int "HCI transport task stack size"
depends on !BT_LE_HCI_INTERFACE_USE_RAM
default 1024
help
This configures stack size of hci transport task
config BT_LE_HCI_TRANS_RX_MEM_NUM
int "The amount of rx memory received at the same time"
depends on BT_LE_UART_HCI_DMA_MODE
default 3
help
The amount of rx memory received at the same time
config BT_LE_HCI_LLDESCS_POOL_NUM
int "The amount of lldecs memory for driver dma mode"
depends on BT_LE_UART_HCI_DMA_MODE
default 20
help
The amount of lldecs memory for driver dma mode
endmenu endmenu
config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT

178
components/bt/controller/esp32h2/bt.c
View File

@@ -30,7 +30,7 @@
#endif // CONFIG_ESP_COEX_ENABLED #endif // CONFIG_ESP_COEX_ENABLED
#include "nimble/nimble_npl_os.h" #include "nimble/nimble_npl_os.h"
#include "ble_hci_trans.h" #include "esp_hci_transport.h"
#include "os/endian.h" #include "os/endian.h"
#include "esp_bt.h" #include "esp_bt.h"
@@ -39,7 +39,6 @@
#include "esp_pm.h" #include "esp_pm.h"
#include "esp_phy_init.h" #include "esp_phy_init.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
#include "hci_uart.h"
#include "bt_osi_mem.h" #include "bt_osi_mem.h"
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
@@ -47,10 +46,6 @@
#include "esp_private/sleep_retention.h" #include "esp_private/sleep_retention.h"
#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
#ifdef CONFIG_BT_BLUEDROID_ENABLED
#include "hci/hci_hal.h"
#endif // CONFIG_BT_BLUEDROID_ENABLED
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
@@ -64,16 +59,11 @@
#define OSI_COEX_VERSION 0x00010006 #define OSI_COEX_VERSION 0x00010006
#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD #define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
#define EXT_FUNC_VERSION 0x20221122 #define EXT_FUNC_VERSION 0x20240422
#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
#define BT_ASSERT_PRINT ets_printf #define BT_ASSERT_PRINT ets_printf
#ifdef CONFIG_BT_BLUEDROID_ENABLED
/* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */
#define ACL_DATA_MBUF_LEADINGSPCAE 4
#endif // CONFIG_BT_BLUEDROID_ENABLED
/* Types definition /* Types definition
************************************************************************ ************************************************************************
*/ */
@@ -92,12 +82,6 @@ struct ext_funcs_t {
int (*_esp_intr_free)(void **ret_handle); int (*_esp_intr_free)(void **ret_handle);
void *(* _malloc)(size_t size); void *(* _malloc)(size_t size);
void (*_free)(void *p); void (*_free)(void *p);
void (*_hal_uart_start_tx)(int);
int (*_hal_uart_init_cbs)(int, hci_uart_tx_char, hci_uart_tx_done, hci_uart_rx_char, void *);
int (*_hal_uart_config)(int, int32_t, uint8_t, uint8_t, uart_parity_t, uart_hw_flowcontrol_t);
int (*_hal_uart_close)(int);
void (*_hal_uart_blocking_tx)(int, uint8_t);
int (*_hal_uart_init)(int, void *);
int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param,
uint32_t prio, void *task_handle, uint32_t core_id); uint32_t prio, void *task_handle, uint32_t core_id);
void (* _task_delete)(void *task_handle); void (* _task_delete)(void *task_handle);
@@ -173,16 +157,6 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
void *param, uint32_t prio, void *task_handle, uint32_t core_id); void *param, uint32_t prio, void *task_handle, uint32_t core_id);
static void task_delete_wrapper(void *task_handle); static void task_delete_wrapper(void *task_handle);
#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static void hci_uart_start_tx_wrapper(int uart_no);
static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg);
static int hci_uart_config_wrapper(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits,
uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl);
static int hci_uart_close_wrapper(int uart_no);
static void hci_uart_blocking_tx_wrapper(int port, uint8_t data);
static int hci_uart_init_wrapper(int uart_no, void *cfg);
#endif // CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
void *arg, void **ret_handle_in); void *arg, void **ret_handle_in);
static int esp_intr_free_wrapper(void **ret_handle); static int esp_intr_free_wrapper(void **ret_handle);
@@ -200,7 +174,6 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
*/ */
/* Static variable declare */ /* Static variable declare */
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE}; const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
@@ -230,14 +203,6 @@ struct ext_funcs_t ext_funcs_ro = {
._esp_intr_free = esp_intr_free_wrapper, ._esp_intr_free = esp_intr_free_wrapper,
._malloc = bt_osi_mem_malloc_internal, ._malloc = bt_osi_mem_malloc_internal,
._free = bt_osi_mem_free, ._free = bt_osi_mem_free,
#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
._hal_uart_start_tx = hci_uart_start_tx_wrapper,
._hal_uart_init_cbs = hci_uart_init_cbs_wrapper,
._hal_uart_config = hci_uart_config_wrapper,
._hal_uart_close = hci_uart_close_wrapper,
._hal_uart_blocking_tx = hci_uart_blocking_tx_wrapper,
._hal_uart_init = hci_uart_init_wrapper,
#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
._task_create = task_create_wrapper, ._task_create = task_create_wrapper,
._task_delete = task_delete_wrapper, ._task_delete = task_delete_wrapper,
._osi_assert = osi_assert_wrapper, ._osi_assert = osi_assert_wrapper,
@@ -282,75 +247,6 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
#endif // CONFIG_SW_COEXIST_ENABLE #endif // CONFIG_SW_COEXIST_ENABLE
} }
#ifdef CONFIG_BT_BLUEDROID_ENABLED
bool esp_vhci_host_check_send_available(void)
{
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
return false;
}
return true;
}
static struct os_mbuf *ble_hs_mbuf_gen_pkt(uint16_t leading_space)
{
struct os_mbuf *om;
int rc;
om = os_msys_get_pkthdr(0, 0);
if (om == NULL) {
return NULL;
}
if (om->om_omp->omp_databuf_len < leading_space) {
rc = os_mbuf_free_chain(om);
assert(rc == 0);
return NULL;
}
om->om_data += leading_space;
return om;
}
struct os_mbuf *ble_hs_mbuf_acl_pkt(void)
{
return ble_hs_mbuf_gen_pkt(4 + 1);
}
void esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
{
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
return;
}
if (*(data) == DATA_TYPE_COMMAND) {
struct ble_hci_cmd *cmd = NULL;
cmd = (struct ble_hci_cmd *) ble_hci_trans_buf_alloc(BLE_HCI_TRANS_BUF_CMD);
assert(cmd);
memcpy((uint8_t *)cmd, data + 1, len - 1);
ble_hci_trans_hs_cmd_tx((uint8_t *)cmd);
}
if (*(data) == DATA_TYPE_ACL) {
struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE);
assert(om);
assert(os_mbuf_append(om, &data[1], len - 1) == 0);
ble_hci_trans_hs_acl_tx(om);
}
}
esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
{
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
return ESP_FAIL;
}
ble_hci_trans_cfg_hs(ble_hs_hci_rx_evt, NULL, ble_hs_rx_data, NULL);
return ESP_OK;
}
#endif // CONFIG_BT_BLUEDROID_ENABLED
static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
void *param, uint32_t prio, void *task_handle, uint32_t core_id) void *param, uint32_t prio, void *task_handle, uint32_t core_id)
{ {
@@ -382,56 +278,6 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer
return rc; return rc;
} }
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static void hci_uart_start_tx_wrapper(int uart_no)
{
hci_uart_start_tx(uart_no);
}
static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg)
{
int rc = -1;
rc = hci_uart_init_cbs(uart_no, tx_func, tx_done, rx_func, arg);
return rc;
}
static int hci_uart_config_wrapper(int port_num, int32_t baud_rate, uint8_t data_bits,
uint8_t stop_bits, uart_parity_t parity,
uart_hw_flowcontrol_t flow_ctl)
{
int rc = -1;
rc = hci_uart_config(port_num, baud_rate, data_bits, stop_bits, parity, flow_ctl);
return rc;
}
static int hci_uart_close_wrapper(int uart_no)
{
int rc = -1;
rc = hci_uart_close(uart_no);
return rc;
}
static void hci_uart_blocking_tx_wrapper(int port, uint8_t data)
{
//This function is nowhere to use.
}
static int hci_uart_init_wrapper(int uart_no, void *cfg)
{
//This function is nowhere to use.
return 0;
}
#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
static int ble_hci_unregistered_hook(void*, void*)
{
ESP_LOGD(NIMBLE_PORT_LOG_TAG,"%s ble hci rx_evt is not registered.",__func__);
return 0;
}
static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
void *arg, void **ret_handle_in) void *arg, void **ret_handle_in)
{ {
@@ -689,6 +535,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
ble_npl_count_info_t npl_info; ble_npl_count_info_t npl_info;
uint32_t slow_clk_freq = 0; uint32_t slow_clk_freq = 0;
uint8_t hci_transport_mode;
memset(&npl_info, 0, sizeof(ble_npl_count_info_t)); memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) { if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
@@ -831,11 +678,23 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
ble_hci_trans_cfg_hs((ble_hci_trans_rx_cmd_fn *)ble_hci_unregistered_hook,NULL, #if CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
(ble_hci_trans_rx_acl_fn *)ble_hci_unregistered_hook,NULL); hci_transport_mode = HCI_TRANSPORT_VHCI;
return ESP_OK; #elif CONFIG_BT_LE_HCI_INTERFACE_USE_UART
hci_transport_mode = HCI_TRANSPORT_UART_NO_DMA;
#if CONFIG_BT_LE_UART_HCI_DMA_MODE
hci_transport_mode = HCI_TRANSPORT_UART_UHCI;
#endif // CONFIG_BT_LE_UART_HCI_DMA_MODE
#endif // CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
ret = hci_transport_init(hci_transport_mode);
if (ret) {
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "hci transport init failed %d", ret);
goto free_controller;
}
return ESP_OK;
free_controller: free_controller:
hci_transport_deinit();
controller_sleep_deinit(); controller_sleep_deinit();
os_msys_deinit(); os_msys_deinit();
r_ble_controller_deinit(); r_ble_controller_deinit();
@@ -865,6 +724,7 @@ esp_err_t esp_bt_controller_deinit(void)
return ESP_FAIL; return ESP_FAIL;
} }
hci_transport_deinit();
controller_sleep_deinit(); controller_sleep_deinit();
os_msys_deinit(); os_msys_deinit();

22
components/bt/controller/esp32h2/esp_bt_cfg.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -124,12 +124,26 @@ extern "C" {
#else #else
#define DEFAULT_BT_LE_POWER_CONTROL_ENABLED (0) #define DEFAULT_BT_LE_POWER_CONTROL_ENABLED (0)
#endif #endif
#if defined(CONFIG_BT_LE_50_FEATURE_SUPPORT) #if defined(CONFIG_BT_LE_50_FEATURE_SUPPORT)
#define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1) #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (1)
#else #else
#define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0) #define DEFAULT_BT_LE_50_FEATURE_SUPPORT (0)
#endif #endif
#if defined (CONFIG_BT_LE_HCI_UART_FLOWCTRL)
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (CONFIG_BT_LE_HCI_UART_FLOWCTRL)
#if DEFAULT_BT_LE_HCI_UART_FLOW_CTRL
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (CONFIG_BT_LE_HCI_UART_CTS_PIN)
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (CONFIG_BT_LE_HCI_UART_RTS_PIN)
#else
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (-1)
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (-1)
#endif
#else
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
#define DEFAULT_BT_LE_HCI_UART_CTS_PIN (-1)
#define DEFAULT_BT_LE_HCI_UART_RTS_PIN (-1)
#endif
#endif #endif
#define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF #define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF
@@ -170,8 +184,6 @@ extern "C" {
#define DEFAULT_BT_LE_HCI_UART_DATA_BITS (UART_DATA_8_BITS) #define DEFAULT_BT_LE_HCI_UART_DATA_BITS (UART_DATA_8_BITS)
#define DEFAULT_BT_LE_HCI_UART_STOP_BITS (UART_STOP_BITS_1) #define DEFAULT_BT_LE_HCI_UART_STOP_BITS (UART_STOP_BITS_1)
#define DEFAULT_BT_LE_HCI_UART_PARITY (0) #define DEFAULT_BT_LE_HCI_UART_PARITY (0)
#define DEFAULT_BT_LE_HCI_UART_TASK_STACK_SIZE (CONFIG_BT_LE_HCI_UART_TASK_STACK_SIZE)
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
#else #else
#define DEFAULT_BT_LE_HCI_UART_TX_PIN (0) #define DEFAULT_BT_LE_HCI_UART_TX_PIN (0)
#define DEFAULT_BT_LE_HCI_UART_RX_PIN (0) #define DEFAULT_BT_LE_HCI_UART_RX_PIN (0)
@@ -180,8 +192,6 @@ extern "C" {
#define DEFAULT_BT_LE_HCI_UART_DATA_BITS (0) #define DEFAULT_BT_LE_HCI_UART_DATA_BITS (0)
#define DEFAULT_BT_LE_HCI_UART_STOP_BITS (0) #define DEFAULT_BT_LE_HCI_UART_STOP_BITS (0)
#define DEFAULT_BT_LE_HCI_UART_PARITY (0) #define DEFAULT_BT_LE_HCI_UART_PARITY (0)
#define DEFAULT_BT_LE_HCI_UART_TASK_STACK_SIZE (0)
#define DEFAULT_BT_LE_HCI_UART_FLOW_CTRL (0)
#endif #endif
/* Unchanged configuration */ /* Unchanged configuration */

2
components/bt/controller/lib_esp32c6/esp32c6-bt-lib

Submodule components/bt/controller/lib_esp32c6/esp32c6-bt-lib updated: 4a63b2963a...2085541b6e

2
components/bt/controller/lib_esp32h2/esp32h2-bt-lib

Submodule components/bt/controller/lib_esp32h2/esp32h2-bt-lib updated: 96b48749e2...9e29a8b39f

18
components/bt/include/esp32c6/include/esp_bt.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -155,7 +155,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
*/ */
esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
#define CONFIG_VERSION 0x20231124 #define CONFIG_VERSION 0x20240422
#define CONFIG_MAGIC 0x5A5AA5A5 #define CONFIG_MAGIC 0x5A5AA5A5
/** /**
@@ -196,13 +196,6 @@ typedef struct {
uint8_t controller_run_cpu; /*!< CPU core on which the controller runs */ uint8_t controller_run_cpu; /*!< CPU core on which the controller runs */
uint8_t enable_qa_test; /*!< Enable quality assurance (QA) testing */ uint8_t enable_qa_test; /*!< Enable quality assurance (QA) testing */
uint8_t enable_bqb_test; /*!< Enable Bluetooth Qualification Test (BQB) testing */ uint8_t enable_bqb_test; /*!< Enable Bluetooth Qualification Test (BQB) testing */
uint8_t enable_uart_hci; /*!< Enable UART HCI (Host Controller Interface) */
uint8_t ble_hci_uart_port; /*!< UART port number for Bluetooth HCI */
uint32_t ble_hci_uart_baud; /*!< Baud rate for Bluetooth HCI UART */
uint8_t ble_hci_uart_data_bits; /*!< Number of data bits for Bluetooth HCI UART */
uint8_t ble_hci_uart_stop_bits; /*!< Number of stop bits for Bluetooth HCI UART */
uint8_t ble_hci_uart_flow_ctrl; /*!< Flow control settings for Bluetooth HCI UART */
uint8_t ble_hci_uart_uart_parity; /*!< Parity settings for Bluetooth HCI UART */
uint8_t enable_tx_cca; /*!< Enable Transmit Clear Channel Assessment (TX CCA) */ uint8_t enable_tx_cca; /*!< Enable Transmit Clear Channel Assessment (TX CCA) */
uint8_t cca_rssi_thresh; /*!< RSSI threshold for Transmit Clear Channel Assessment (CCA) */ uint8_t cca_rssi_thresh; /*!< RSSI threshold for Transmit Clear Channel Assessment (CCA) */
uint8_t sleep_en; /*!< Enable sleep mode */ uint8_t sleep_en; /*!< Enable sleep mode */
@@ -253,13 +246,6 @@ typedef struct {
.controller_run_cpu = 0, \ .controller_run_cpu = 0, \
.enable_qa_test = RUN_QA_TEST, \ .enable_qa_test = RUN_QA_TEST, \
.enable_bqb_test = RUN_BQB_TEST, \ .enable_bqb_test = RUN_BQB_TEST, \
.enable_uart_hci = HCI_UART_EN, \
.ble_hci_uart_port = DEFAULT_BT_LE_HCI_UART_PORT, \
.ble_hci_uart_baud = DEFAULT_BT_LE_HCI_UART_BAUD, \
.ble_hci_uart_data_bits = DEFAULT_BT_LE_HCI_UART_DATA_BITS, \
.ble_hci_uart_stop_bits = DEFAULT_BT_LE_HCI_UART_STOP_BITS, \
.ble_hci_uart_flow_ctrl = DEFAULT_BT_LE_HCI_UART_FLOW_CTRL, \
.ble_hci_uart_uart_parity = DEFAULT_BT_LE_HCI_UART_PARITY, \
.enable_tx_cca = DEFAULT_BT_LE_TX_CCA_ENABLED, \ .enable_tx_cca = DEFAULT_BT_LE_TX_CCA_ENABLED, \
.cca_rssi_thresh = 256 - DEFAULT_BT_LE_CCA_RSSI_THRESH, \ .cca_rssi_thresh = 256 - DEFAULT_BT_LE_CCA_RSSI_THRESH, \
.sleep_en = NIMBLE_SLEEP_ENABLE, \ .sleep_en = NIMBLE_SLEEP_ENABLE, \

18
components/bt/include/esp32h2/include/esp_bt.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -160,7 +160,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
*/ */
esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
#define CONFIG_VERSION 0x20231124 #define CONFIG_VERSION 0x20240422
#define CONFIG_MAGIC 0x5A5AA5A5 #define CONFIG_MAGIC 0x5A5AA5A5
/** /**
@@ -201,13 +201,6 @@ typedef struct {
uint8_t controller_run_cpu; /*!< CPU number on which the Bluetooth controller task runs */ uint8_t controller_run_cpu; /*!< CPU number on which the Bluetooth controller task runs */
uint8_t enable_qa_test; /*!< Enable for QA test */ uint8_t enable_qa_test; /*!< Enable for QA test */
uint8_t enable_bqb_test; /*!< Enable for BQB test */ uint8_t enable_bqb_test; /*!< Enable for BQB test */
uint8_t enable_uart_hci; /*!< Enable UART for HCI (Host Controller Interface) */
uint8_t ble_hci_uart_port; /*!< Port of UART for HCI */
uint32_t ble_hci_uart_baud; /*!< Baudrate of UART for HCI */
uint8_t ble_hci_uart_data_bits; /*!< Data bits of UART for HCI */
uint8_t ble_hci_uart_stop_bits; /*!< Stop bits of UART for HCI */
uint8_t ble_hci_uart_flow_ctrl; /*!< Flow control of UART for HCI */
uint8_t ble_hci_uart_uart_parity; /*!< UART parity */
uint8_t enable_tx_cca; /*!< Enable Clear Channel Assessment (CCA) when transmitting */ uint8_t enable_tx_cca; /*!< Enable Clear Channel Assessment (CCA) when transmitting */
uint8_t cca_rssi_thresh; /*!< RSSI threshold for CCA */ uint8_t cca_rssi_thresh; /*!< RSSI threshold for CCA */
uint8_t sleep_en; /*!< Enable sleep functionality */ uint8_t sleep_en; /*!< Enable sleep functionality */
@@ -258,13 +251,6 @@ typedef struct {
.controller_run_cpu = 0, \ .controller_run_cpu = 0, \
.enable_qa_test = RUN_QA_TEST, \ .enable_qa_test = RUN_QA_TEST, \
.enable_bqb_test = RUN_BQB_TEST, \ .enable_bqb_test = RUN_BQB_TEST, \
.enable_uart_hci = HCI_UART_EN, \
.ble_hci_uart_port = DEFAULT_BT_LE_HCI_UART_PORT, \
.ble_hci_uart_baud = DEFAULT_BT_LE_HCI_UART_BAUD, \
.ble_hci_uart_data_bits = DEFAULT_BT_LE_HCI_UART_DATA_BITS, \
.ble_hci_uart_stop_bits = DEFAULT_BT_LE_HCI_UART_STOP_BITS, \
.ble_hci_uart_flow_ctrl = DEFAULT_BT_LE_HCI_UART_FLOW_CTRL, \
.ble_hci_uart_uart_parity = DEFAULT_BT_LE_HCI_UART_PARITY, \
.enable_tx_cca = DEFAULT_BT_LE_TX_CCA_ENABLED, \ .enable_tx_cca = DEFAULT_BT_LE_TX_CCA_ENABLED, \
.cca_rssi_thresh = 256 - DEFAULT_BT_LE_CCA_RSSI_THRESH, \ .cca_rssi_thresh = 256 - DEFAULT_BT_LE_CCA_RSSI_THRESH, \
.sleep_en = NIMBLE_SLEEP_ENABLE, \ .sleep_en = NIMBLE_SLEEP_ENABLE, \

133
components/hal/esp32c6/include/hal/uhci_ll.h Normal file
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@@ -0,0 +1,133 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdio.h>
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
UHCI_RX_LEN_EOF = 0x4,
UHCI_RX_EOF_MAX = 0x7,
} uhci_rxeof_cfg_t;
static inline void uhci_ll_init(uhci_dev_t *hw)
{
typeof(hw->conf0) conf0_reg;
hw->conf0.clk_en = 1;
conf0_reg.val = 0;
conf0_reg.clk_en = 1;
hw->conf0.val = conf0_reg.val;
hw->conf1.val = 0;
}
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
{
hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
}
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
{
if (seper_char->sub_chr_en) {
typeof(hw->esc_conf0) esc_conf0_reg;
esc_conf0_reg.val = hw->esc_conf0.val;
esc_conf0_reg.seper_char = seper_char->seper_chr;
esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1;
esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2;
hw->esc_conf0.val = esc_conf0_reg.val;
hw->escape_conf.tx_c0_esc_en = 1;
hw->escape_conf.rx_c0_esc_en = 1;
} else {
hw->escape_conf.tx_c0_esc_en = 0;
hw->escape_conf.rx_c0_esc_en = 0;
}
}
static inline void uhci_ll_get_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_chr)
{
(void)hw;
(void)seper_chr;
}
static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr)
{
typeof(hw->escape_conf) escape_conf_reg;
escape_conf_reg.val = hw->escape_conf.val;
if (sub_ctr->flow_en == 1) {
typeof(hw->esc_conf2) esc_conf2_reg;
esc_conf2_reg.val = hw->esc_conf2.val;
typeof(hw->esc_conf3) esc_conf3_reg;
esc_conf3_reg.val = hw->esc_conf3.val;
esc_conf2_reg.esc_seq1 = sub_ctr->xon_chr;
esc_conf2_reg.esc_seq1_char0 = sub_ctr->xon_sub1;
esc_conf2_reg.esc_seq1_char1 = sub_ctr->xon_sub2;
esc_conf3_reg.esc_seq2 = sub_ctr->xoff_chr;
esc_conf3_reg.esc_seq2_char0 = sub_ctr->xoff_sub1;
esc_conf3_reg.esc_seq2_char1 = sub_ctr->xoff_sub2;
escape_conf_reg.tx_11_esc_en = 1;
escape_conf_reg.tx_13_esc_en = 1;
escape_conf_reg.rx_11_esc_en = 1;
escape_conf_reg.rx_13_esc_en = 1;
hw->esc_conf2.val = esc_conf2_reg.val;
hw->esc_conf3.val = esc_conf3_reg.val;
} else {
escape_conf_reg.tx_11_esc_en = 0;
escape_conf_reg.tx_13_esc_en = 0;
escape_conf_reg.rx_11_esc_en = 0;
escape_conf_reg.rx_13_esc_en = 0;
}
hw->escape_conf.val = escape_conf_reg.val;
}
static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_ena.val |= intr_mask;
}
static inline void uhci_ll_disable_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_ena.val &= (~intr_mask);
}
static inline void uhci_ll_clear_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_clr.val = intr_mask;
}
static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
{
return hw->int_st.val;
}
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
hw->conf0.uart_rx_brk_eof_en = 1;
}
if (eof_mode & UHCI_RX_IDLE_EOF) {
hw->conf0.uart_idle_eof_en = 1;
}
if (eof_mode & UHCI_RX_LEN_EOF) {
hw->conf0.len_eof_en = 1;
}
}
#ifdef __cplusplus
}
#endif

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components/hal/esp32h2/include/hal/uhci_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdio.h>
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
UHCI_RX_LEN_EOF = 0x4,
UHCI_RX_EOF_MAX = 0x7,
} uhci_rxeof_cfg_t;
static inline void uhci_ll_init(uhci_dev_t *hw)
{
typeof(hw->conf0) conf0_reg;
hw->conf0.clk_en = 1;
conf0_reg.val = 0;
conf0_reg.clk_en = 1;
hw->conf0.val = conf0_reg.val;
hw->conf1.val = 0;
}
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
{
hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
}
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
{
if (seper_char->sub_chr_en) {
typeof(hw->esc_conf0) esc_conf0_reg;
esc_conf0_reg.val = hw->esc_conf0.val;
esc_conf0_reg.seper_char = seper_char->seper_chr;
esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1;
esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2;
hw->esc_conf0.val = esc_conf0_reg.val;
hw->escape_conf.tx_c0_esc_en = 1;
hw->escape_conf.rx_c0_esc_en = 1;
} else {
hw->escape_conf.tx_c0_esc_en = 0;
hw->escape_conf.rx_c0_esc_en = 0;
}
}
static inline void uhci_ll_get_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_chr)
{
(void)hw;
(void)seper_chr;
}
static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr)
{
typeof(hw->escape_conf) escape_conf_reg;
escape_conf_reg.val = hw->escape_conf.val;
if (sub_ctr->flow_en == 1) {
typeof(hw->esc_conf2) esc_conf2_reg;
esc_conf2_reg.val = hw->esc_conf2.val;
typeof(hw->esc_conf3) esc_conf3_reg;
esc_conf3_reg.val = hw->esc_conf3.val;
esc_conf2_reg.esc_seq1 = sub_ctr->xon_chr;
esc_conf2_reg.esc_seq1_char0 = sub_ctr->xon_sub1;
esc_conf2_reg.esc_seq1_char1 = sub_ctr->xon_sub2;
esc_conf3_reg.esc_seq2 = sub_ctr->xoff_chr;
esc_conf3_reg.esc_seq2_char0 = sub_ctr->xoff_sub1;
esc_conf3_reg.esc_seq2_char1 = sub_ctr->xoff_sub2;
escape_conf_reg.tx_11_esc_en = 1;
escape_conf_reg.tx_13_esc_en = 1;
escape_conf_reg.rx_11_esc_en = 1;
escape_conf_reg.rx_13_esc_en = 1;
hw->esc_conf2.val = esc_conf2_reg.val;
hw->esc_conf3.val = esc_conf3_reg.val;
} else {
escape_conf_reg.tx_11_esc_en = 0;
escape_conf_reg.tx_13_esc_en = 0;
escape_conf_reg.rx_11_esc_en = 0;
escape_conf_reg.rx_13_esc_en = 0;
}
hw->escape_conf.val = escape_conf_reg.val;
}
static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_ena.val |= intr_mask;
}
static inline void uhci_ll_disable_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_ena.val &= (~intr_mask);
}
static inline void uhci_ll_clear_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_clr.val = intr_mask;
}
static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
{
return hw->int_st.val;
}
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
hw->conf0.uart_rx_brk_eof_en = 1;
}
if (eof_mode & UHCI_RX_IDLE_EOF) {
hw->conf0.uart_idle_eof_en = 1;
}
if (eof_mode & UHCI_RX_LEN_EOF) {
hw->conf0.len_eof_en = 1;
}
}
#ifdef __cplusplus
}
#endif