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Merge branch 'doc/ulp_st_bits' into 'master'
ulp: update ST instruction description (Github PR) Closes IDFGH-3224 See merge request espressif/esp-idf!13159
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@@ -364,9 +364,9 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
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4 cycles to execute, 4 cycles to fetch next instruction
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**Description**
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The instruction stores the 16-bit value of Rsrc to the lower half-word of memory with address Rdst+offset. The upper half-word is written with the current program counter (PC), expressed in words, shifted left by 5 bits::
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The instruction stores the 16-bit value of Rsrc to the lower half-word of memory with address Rdst+offset. The upper half-word is written with the current program counter (PC) (expressed in words, shifted left by 5 bits) OR'd with Rdst (0..3)::
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Mem[Rdst + offset / 4]{31:0} = {PC[10:0], 5'b0, Rsrc[15:0]}
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Mem[Rdst + offset / 4]{31:0} = {PC[10:0], 3'b0, Rdst, Rsrc[15:0]}
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The application can use higher 16 bits to determine which instruction in the ULP program has written any particular word into memory.
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