alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-09-30 19:19:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

rtc: add rtc related changes from feature/support_7.2.7_soc

Browse Source
This commit is contained in:
Marius Vikhammer
2021-03-18 15:23:31 +08:00
parent 2aead8ba57
commit e83d213c56
6 changed files with 1965 additions and 2071 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@@ -40,7 +40,7 @@ static const char *TAG = "rtc_clk";
#define DELAY_RTC_CLK_SWITCH 5
// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
static uint32_t s_cur_pll_freq = RTC_PLL_FREQ_480M;
static uint32_t s_cur_pll_freq;
static void rtc_clk_cpu_freq_to_8m(void);
@@ -306,7 +306,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1);
s_cur_pll_freq = pll_freq;
}

39
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@@ -25,7 +25,6 @@
#include "regi2c_ulp.h"
#include "soc_log.h"
#define RTC_CNTL_MEM_FORCE_PU (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
#define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
static char *TAG = "rtcinit";
@@ -47,15 +46,22 @@ void rtc_init(rtc_config_t cfg)
rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
// set bt timer
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles);
// set rtc peri timer
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles);
// set digital wrap timer
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
// set rtc memory timer
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTLMEM_POWERUP_TIMER, rtc_init_cfg.rtc_mem_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTLMEM_WAIT_TIMER, rtc_init_cfg.rtc_mem_wait_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
/* Reset RTC bias to default value (needed if waking up from deep sleep) */
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10);
@@ -64,10 +70,6 @@ void rtc_init(rtc_config_t cfg)
if (cfg.clkctl_init) {
//clear CMMU clock force on
CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
//clear rom clock force on
REG_SET_FIELD(SYSCON_CLKGATE_FORCE_ON_REG, SYSCON_ROM_CLKGATE_FORCE_ON, 0);
//clear sram clock force on
REG_SET_FIELD(SYSCON_CLKGATE_FORCE_ON_REG, SYSCON_SRAM_CLKGATE_FORCE_ON, 0);
//clear tag clock force on
CLEAR_PERI_REG_MASK(EXTMEM_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_DCACHE_TAG_MEM_FORCE_ON);
CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);
@@ -89,6 +91,9 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
//open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
//cancel bbpll force pu if setting no force power up
if (!cfg.bbpll_fpu) {
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
@@ -104,9 +109,7 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
//combine two rtc memory options
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO);
if (cfg.rtc_dboost_fpd) {
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
@@ -114,11 +117,6 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
}
//cancel digital pu force
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
/* If this mask is enabled, all soc memories cannot enter power down mode */
/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
@@ -129,12 +127,19 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO);
//cancel digital PADS force no iso
if (cfg.cpu_waiti_clk_gate) {
SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
} else {
SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
}

25
components/esp_hw_support/port/esp32s3/rtc_sleep.c
View File

@@ -37,7 +37,6 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
{
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
@@ -74,22 +73,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
}
if (cfg.rtc_fastmem_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO);
}
if (cfg.rtc_slowmem_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO);
}
@@ -105,6 +96,22 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
}
if (cfg.bt_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
}
if (cfg.cpu_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
}
if (cfg.dig_peri_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
}
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);

9
components/soc/esp32s3/include/soc/rtc.h
View File

@@ -249,10 +249,16 @@ typedef struct {
typedef struct {
uint16_t wifi_powerup_cycles : 7;
uint16_t wifi_wait_cycles : 9;
uint16_t bt_powerup_cycles : 7;
uint16_t bt_wait_cycles : 9;
uint16_t rtc_powerup_cycles : 7;
uint16_t rtc_wait_cycles : 9;
uint16_t cpu_top_powerup_cycles : 7;
uint16_t cpu_top_wait_cycles : 9;
uint16_t dg_wrap_powerup_cycles : 7;
uint16_t dg_wrap_wait_cycles : 9;
uint16_t dg_peri_powerup_cycles : 7;
uint16_t dg_peri_wait_cycles : 9;
uint16_t rtc_mem_powerup_cycles : 7;
uint16_t rtc_mem_wait_cycles : 9;
} rtc_init_config_t;
@@ -633,6 +639,9 @@ typedef struct {
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t bt_pd_en : 1; //!< power down BT
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode

1664
components/soc/esp32s3/include/soc/rtc_cntl_reg.h
View File

File diff suppressed because it is too large Load Diff

156
components/soc/esp32s3/include/soc/rtc_cntl_struct.h
View File

@@ -13,18 +13,15 @@
// limitations under the License.
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
uint32_t sw_stall_procpu_c0 : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
@@ -49,7 +46,7 @@ typedef volatile struct {
};
uint32_t val;
} options0;
uint32_t slp_timer0;
uint32_t slp_timer0; /**/
union {
struct {
uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/
@@ -69,7 +66,7 @@ typedef volatile struct {
};
uint32_t val;
} time_update;
uint32_t time_low0;
uint32_t time_low0; /*RTC timer low 32 bits*/
union {
struct {
uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/
@@ -113,8 +110,8 @@ typedef volatile struct {
struct {
uint32_t wifi_wait_timer: 9;
uint32_t wifi_powerup_timer: 7;
uint32_t rom_ram_wait_timer : 9;
uint32_t rom_ram_powerup_timer : 7;
uint32_t bt_wait_timer: 9;
uint32_t bt_powerup_timer: 7;
};
uint32_t val;
} timer3;
@@ -131,16 +128,16 @@ typedef volatile struct {
struct {
uint32_t reserved0: 8;
uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/
uint32_t rtcmem_wait_timer : 9;
uint32_t rtcmem_powerup_timer : 7;
uint32_t reserved16: 16;
};
uint32_t val;
} timer5;
union {
struct {
uint32_t reserved0 : 16;
uint32_t dg_dcdc_wait_timer : 9;
uint32_t dg_dcdc_powerup_timer : 7;
uint32_t cpu_top_wait_timer: 9;
uint32_t cpu_top_powerup_timer: 7;
uint32_t dg_peri_wait_timer: 9;
uint32_t dg_peri_powerup_timer: 7;
};
uint32_t val;
} timer6;
@@ -301,10 +298,10 @@ typedef volatile struct {
};
uint32_t val;
} int_clr;
uint32_t store[4];
uint32_t store[4]; /**/
union {
struct {
uint32_t xtal32k_en : 1; /*xtal 32k watch dog enable*/
uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/
uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/
uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/
uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/
@@ -330,8 +327,8 @@ typedef volatile struct {
struct {
uint32_t reserved0: 29;
uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/
uint32_t ext_wakeup0_lv : 1; /*0: external wakeup at low level*/
uint32_t ext_wakeup1_lv : 1;
uint32_t wakeup0_lv: 1; /*0: external wakeup at low level*/
uint32_t wakeup1_lv: 1;
};
uint32_t val;
} ext_wakeup_conf;
@@ -426,7 +423,8 @@ typedef volatile struct {
uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/
uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/
uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/
uint32_t reserved26 : 6;
uint32_t dbg_atten_wakeup: 4;
uint32_t reserved30: 2;
};
uint32_t val;
} bias_conf;
@@ -446,24 +444,19 @@ typedef volatile struct {
} rtc;
union {
struct {
uint32_t rtc_fastmem_force_noiso : 1; /*Fast RTC memory force no ISO*/
uint32_t rtc_fastmem_force_iso : 1; /*Fast RTC memory force ISO*/
uint32_t rtc_slowmem_force_noiso : 1; /*RTC memory force no ISO*/
uint32_t rtc_slowmem_force_iso : 1; /*RTC memory force ISO*/
uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/
uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/
uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/
uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/
uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/
uint32_t rtc_force_noiso: 1; /*rtc_peri force no ISO*/
uint32_t rtc_fastmem_folw_cpu : 1; /*1: Fast RTC memory PD following CPU*/
uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU*/
uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/
uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/
uint32_t rtc_slowmem_folw_cpu : 1; /*1: RTC memory PD following CPU*/
uint32_t rtc_slowmem_force_lpd : 1; /*RTC memory force PD*/
uint32_t rtc_slowmem_force_lpu : 1; /*RTC memory force no PD*/
uint32_t rtc_fastmem_force_pd : 1; /*Fast RTC memory force power down*/
uint32_t rtc_fastmem_force_pu : 1; /*Fast RTC memory force power up*/
uint32_t rtc_fastmem_pd_en : 1; /*enable power down fast RTC memory in sleep*/
uint32_t rtc_slowmem_force_pd : 1; /*RTC memory force power down*/
uint32_t rtc_slowmem_force_pu : 1; /*RTC memory force power up*/
uint32_t rtc_slowmem_pd_en : 1; /*enable power down RTC memory in sleep*/
uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU*/
uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/
uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/
uint32_t reserved12: 6; /*enable power down RTC memory in sleep*/
uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/
uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/
uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/
@@ -471,37 +464,28 @@ typedef volatile struct {
uint32_t reserved22: 10;
};
uint32_t val;
} pwc;
} rtc_pwc;
union {
struct {
uint32_t reserved0: 3;
uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/
uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/
uint32_t rom0_force_pd : 1; /*ROM force power down*/
uint32_t rom0_force_pu : 1; /*ROM force power up*/
uint32_t inter_ram0_force_pd : 1; /*internal SRAM 0 force power down*/
uint32_t inter_ram0_force_pu : 1; /*internal SRAM 0 force power up*/
uint32_t inter_ram1_force_pd : 1; /*internal SRAM 1 force power down*/
uint32_t inter_ram1_force_pu : 1; /*internal SRAM 1 force power up*/
uint32_t inter_ram2_force_pd : 1; /*internal SRAM 2 force power down*/
uint32_t inter_ram2_force_pu : 1; /*internal SRAM 2 force power up*/
uint32_t inter_ram3_force_pd : 1; /*internal SRAM 3 force power down*/
uint32_t inter_ram3_force_pu : 1; /*internal SRAM 3 force power up*/
uint32_t inter_ram4_force_pd : 1; /*internal SRAM 4 force power down*/
uint32_t inter_ram4_force_pu : 1; /*internal SRAM 4 force power up*/
uint32_t reserved5: 6; /*internal SRAM 1 force power up*/
uint32_t bt_force_pd: 1; /*internal SRAM 2 force power down*/
uint32_t bt_force_pu: 1; /*internal SRAM 2 force power up*/
uint32_t dg_peri_force_pd: 1; /*internal SRAM 3 force power down*/
uint32_t dg_peri_force_pu: 1; /*internal SRAM 3 force power up*/
uint32_t reserved15: 2; /*internal SRAM 4 force power up*/
uint32_t wifi_force_pd: 1; /*wifi force power down*/
uint32_t wifi_force_pu: 1; /*wifi force power up*/
uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/
uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/
uint32_t dg_dcdc_force_pd : 1; /*digital dcdc force power down*/
uint32_t dg_dcdc_force_pu : 1; /*digital dcdc force power up*/
uint32_t dg_dcdc_pd_en : 1; /*enable power down digital dcdc in sleep*/
uint32_t rom0_pd_en : 1; /*enable power down ROM in sleep*/
uint32_t inter_ram0_pd_en : 1; /*enable power down internal SRAM 0 in sleep*/
uint32_t inter_ram1_pd_en : 1; /*enable power down internal SRAM 1 in sleep*/
uint32_t inter_ram2_pd_en : 1; /*enable power down internal SRAM 2 in sleep*/
uint32_t inter_ram3_pd_en : 1; /*enable power down internal SRAM 3 in sleep*/
uint32_t inter_ram4_pd_en : 1; /*enable power down internal SRAM 4 in sleep*/
uint32_t cpu_top_force_pd: 1; /*digital dcdc force power down*/
uint32_t cpu_top_force_pu: 1; /*digital dcdc force power up*/
uint32_t reserved23: 4; /*enable power down internal SRAM 1 in sleep*/
uint32_t bt_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/
uint32_t dg_peri_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/
uint32_t cpu_top_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/
uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/
uint32_t dg_wrap_pd_en: 1;
};
@@ -519,18 +503,13 @@ typedef volatile struct {
uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/
uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/
uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/
uint32_t rom0_force_iso : 1; /*ROM force ISO*/
uint32_t rom0_force_noiso : 1; /*ROM force no ISO*/
uint32_t inter_ram0_force_iso : 1; /*internal SRAM 0 force ISO*/
uint32_t inter_ram0_force_noiso : 1; /*internal SRAM 0 force no ISO*/
uint32_t inter_ram1_force_iso : 1; /*internal SRAM 1 force ISO*/
uint32_t inter_ram1_force_noiso : 1; /*internal SRAM 1 force no ISO*/
uint32_t inter_ram2_force_iso : 1; /*internal SRAM 2 force ISO*/
uint32_t inter_ram2_force_noiso : 1; /*internal SRAM 2 force no ISO*/
uint32_t inter_ram3_force_iso : 1; /*internal SRAM 3 force ISO*/
uint32_t inter_ram3_force_noiso : 1; /*internal SRAM 3 force no ISO*/
uint32_t inter_ram4_force_iso : 1; /*internal SRAM 4 force ISO*/
uint32_t inter_ram4_force_noiso : 1; /*internal SRAM 4 force no ISO*/
uint32_t reserved16: 6; /*internal SRAM 1 force no ISO*/
uint32_t bt_force_iso: 1; /*internal SRAM 2 force ISO*/
uint32_t bt_force_noiso: 1; /*internal SRAM 2 force no ISO*/
uint32_t dg_peri_force_iso: 1; /*internal SRAM 3 force ISO*/
uint32_t dg_peri_force_noiso: 1; /*internal SRAM 3 force no ISO*/
uint32_t cpu_top_force_iso: 1; /*internal SRAM 4 force ISO*/
uint32_t cpu_top_force_noiso: 1; /*internal SRAM 4 force no ISO*/
uint32_t wifi_force_iso: 1; /*wifi force ISO*/
uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/
uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/
@@ -556,10 +535,10 @@ typedef volatile struct {
};
uint32_t val;
} wdt_config0;
uint32_t wdt_config1;
uint32_t wdt_config2;
uint32_t wdt_config3;
uint32_t wdt_config4;
uint32_t wdt_config1; /**/
uint32_t wdt_config2; /**/
uint32_t wdt_config3; /**/
uint32_t wdt_config4; /**/
union {
struct {
uint32_t reserved0: 31;
@@ -567,7 +546,7 @@ typedef volatile struct {
};
uint32_t val;
} wdt_feed;
uint32_t wdt_wprotect;
uint32_t wdt_wprotect; /**/
union {
struct {
uint32_t swd_reset_flag: 1; /*swd reset flag*/
@@ -582,7 +561,7 @@ typedef volatile struct {
};
uint32_t val;
} swd_conf;
uint32_t swd_wprotect;
uint32_t swd_wprotect; /**/
union {
struct {
uint32_t reserved0: 20;
@@ -591,10 +570,10 @@ typedef volatile struct {
};
uint32_t val;
} sw_cpu_stall;
uint32_t store4;
uint32_t store5;
uint32_t store6;
uint32_t store7;
uint32_t store4; /**/
uint32_t store5; /**/
uint32_t store6; /**/
uint32_t store7; /**/
union {
struct {
uint32_t xpd_rom0: 1; /*rom0 power down*/
@@ -629,7 +608,7 @@ typedef volatile struct {
};
uint32_t val;
} low_power_st;
uint32_t diag0;
uint32_t diag0; /**/
union {
struct {
uint32_t touch_pad0_hold: 1;
@@ -658,18 +637,18 @@ typedef volatile struct {
};
uint32_t val;
} pad_hold;
uint32_t dig_pad_hold;
uint32_t dig_pad_hold; /**/
union {
struct {
uint32_t ext_wakeup1_sel : 22; /*Bitmap to select RTC pads for ext wakeup1*/
uint32_t ext_wakeup1_status_clr : 1; /*clear ext wakeup1 status*/
uint32_t sel: 22; /*Bitmap to select RTC pads for ext wakeup1*/
uint32_t status_clr: 1; /*clear ext wakeup1 status*/
uint32_t reserved23: 9;
};
uint32_t val;
} ext_wakeup1;
union {
struct {
uint32_t ext_wakeup1_status : 22; /*ext wakeup1 status*/
uint32_t status: 22; /*ext wakeup1 status*/
uint32_t reserved22: 10;
};
uint32_t val;
@@ -690,7 +669,7 @@ typedef volatile struct {
};
uint32_t val;
} brown_out;
uint32_t time_low1;
uint32_t time_low1; /*RTC timer low 32 bits*/
union {
struct {
uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/
@@ -698,7 +677,7 @@ typedef volatile struct {
};
uint32_t val;
} time_high1;
uint32_t xtal32k_clk_factor;
uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/
union {
struct {
uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/
@@ -795,7 +774,7 @@ typedef volatile struct {
uint32_t touch_slp_th: 22; /*the threshold for sleep touch pad*/
uint32_t reserved22: 4;
uint32_t touch_slp_approach_en: 1; /*sleep pad approach function enable*/
uint32_t touch_slp_pad : 5; /* */
uint32_t touch_slp_pad: 5;
};
uint32_t val;
} touch_slp_thres;
@@ -939,7 +918,10 @@ typedef volatile struct {
} int_ena_w1tc;
union {
struct {
uint32_t reserved0 : 26;
uint32_t reserved0: 18;
uint32_t retention_clk_sel: 1;
uint32_t retention_done_wait: 3;
uint32_t retention_clkoff_wait: 4;
uint32_t retention_en: 1;
uint32_t retention_wait: 5; /*wait cycles for rention operation*/
};
@@ -965,6 +947,4 @@ extern rtc_cntl_dev_t RTCCNTL;
}
#endif
#endif /* _SOC_RTC_CNTL_STRUCT_H_ */