Merge branch 'feature/esp32c5_mp_rtcio_support' into 'master'

feat(rtcio): support RTCIO on ESP32C5 MP

Closes IDF-8719

See merge request espressif/esp-idf!31371

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -295,6 +295,14 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
     bool
     default y
 
+config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+    bool
+    default y
+
+config SOC_LP_IO_CLOCK_IS_INDEPENDENT
+    bool
+    default y
+
 config SOC_GPIO_IN_RANGE_MAX
     int
     default 28
@@ -325,7 +333,19 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
 
 config SOC_RTCIO_PIN_COUNT
     int
-    default 0
+    default 8
+
+config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+    bool
+    default y
+
+config SOC_RTCIO_HOLD_SUPPORTED
+    bool
+    default y
+
+config SOC_RTCIO_WAKE_SUPPORTED
+    bool
+    default y
 
 config SOC_I2C_NUM
     int

components/soc/esp32c5/include/soc/rtc_io_channel.h

@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define RTCIO_GPIO0_CHANNEL         0   //RTCIO_CHANNEL_0
+#define RTCIO_CHANNEL_0_GPIO_NUM    0
+
+#define RTCIO_GPIO1_CHANNEL         1   //RTCIO_CHANNEL_1
+#define RTCIO_CHANNEL_1_GPIO_NUM    1
+
+#define RTCIO_GPIO2_CHANNEL         2   //RTCIO_CHANNEL_2
+#define RTCIO_CHANNEL_2_GPIO_NUM    2
+
+#define RTCIO_GPIO3_CHANNEL         3   //RTCIO_CHANNEL_3
+#define RTCIO_CHANNEL_3_GPIO_NUM    3
+
+#define RTCIO_GPIO4_CHANNEL         4   //RTCIO_CHANNEL_4
+#define RTCIO_CHANNEL_4_GPIO_NUM    4
+
+#define RTCIO_GPIO5_CHANNEL         5   //RTCIO_CHANNEL_5
+#define RTCIO_CHANNEL_5_GPIO_NUM    5
+
+#define RTCIO_GPIO6_CHANNEL         6   //RTCIO_CHANNEL_6
+#define RTCIO_CHANNEL_6_GPIO_NUM    6
+
+#define RTCIO_GPIO7_CHANNEL         7   //RTCIO_CHANNEL_7
+#define RTCIO_CHANNEL_7_GPIO_NUM    7

components/soc/esp32c5/include/soc/soc_caps.h

@@ -196,7 +196,9 @@
 // On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
 #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
 // GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
-// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)  // TODO: [ESP32C5] IDF-8719
+#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
+// LP IO peripherals have independent clock gating to manage
+#define SOC_LP_IO_CLOCK_IS_INDEPENDENT      (1)
 
 #define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
@@ -219,13 +221,13 @@
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM           (3)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
-#define SOC_RTCIO_PIN_COUNT                 0UL
-// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1  /* This macro indicates that the target has separate RTC IOMUX hardware feature,
-                                            //  * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
-                                            //  * when the pins are switched to RTC function.
-                                            //  */
-// #define SOC_RTCIO_HOLD_SUPPORTED            1
-// #define SOC_RTCIO_WAKE_SUPPORTED            1
+#define SOC_RTCIO_PIN_COUNT                 8
+#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED    1  /* This macro indicates that the target has separate RTC IOMUX hardware feature,
+                                                * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
+                                                * when the pins are switched to RTC function.
+                                                */
+#define SOC_RTCIO_HOLD_SUPPORTED            1
+#define SOC_RTCIO_WAKE_SUPPORTED            1
 
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 // #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */

components/soc/esp32c5/include/soc/uart_pins.h

@@ -40,7 +40,7 @@
 #define U1RTS_MUX_FUNC  (-1)
 #define U1CTS_MUX_FUNC  (-1)
 
-#define LP_U0TXD_MUX_FUNC  (1)
-#define LP_U0RXD_MUX_FUNC  (1)
-#define LP_U0RTS_MUX_FUNC  (1)
-#define LP_U0CTS_MUX_FUNC  (1)
+#define LP_U0TXD_MUX_FUNC  (0)
+#define LP_U0RXD_MUX_FUNC  (0)
+#define LP_U0RTS_MUX_FUNC  (0)
+#define LP_U0CTS_MUX_FUNC  (0)

components/soc/esp32c5/rtc_io_periph.c

@@ -0,0 +1,39 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/rtc_io_periph.h"
+
+const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
+    RTCIO_GPIO0_CHANNEL,    //GPIO0
+    RTCIO_GPIO1_CHANNEL,    //GPIO1
+    RTCIO_GPIO2_CHANNEL,    //GPIO2
+    RTCIO_GPIO3_CHANNEL,    //GPIO3
+    RTCIO_GPIO4_CHANNEL,    //GPIO4
+    RTCIO_GPIO5_CHANNEL,    //GPIO5
+    RTCIO_GPIO6_CHANNEL,    //GPIO6
+    RTCIO_GPIO7_CHANNEL,    //GPIO7
+    -1,//GPIO8
+    -1,//GPIO9
+    -1,//GPIO10
+    -1,//GPIO11
+    -1,//GPIO12
+    -1,//GPIO13
+    -1,//GPIO14
+    -1,//GPIO15
+    -1,//GPIO16
+    -1,//GPIO17
+    -1,//GPIO18
+    -1,//GPIO19
+    -1,//GPIO20
+    -1,//GPIO21
+    -1,//GPIO22
+    -1,//GPIO23
+    -1,//GPIO24
+    -1,//GPIO25
+    -1,//GPIO26
+    -1,//GPIO27
+    -1,//GPIO28
+};