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Merge branch 'feat/support_c5_c61_clkoutput' into 'master'

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feat(esp_hw_support): support clock output feature on esp32c5/esp32c61

Closes IDF-10968 and IDF-10970

See merge request espressif/esp-idf!40801
This commit is contained in:
Wu Zheng Hui
2025-07-30 16:13:52 +08:00
parent b0f22503b4 bf3c79068d
commit e8ef305398
18 changed files with 212 additions and 80 deletions
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6
components/hal/esp32c5/clk_tree_hal.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -72,10 +72,10 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
{
abort(); // TODO: IDF-10968
gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
}
void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
{
abort(); // TODO: IDF-10968
gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
}

33
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@@ -603,6 +603,39 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
return REG_READ(RTC_SLOW_CLK_CAL_REG);
}
/*
* Enable/Disable the clock gate for clock output signal source
*/
static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
{
switch (clk_src)
{
case CLKOUT_SIG_PLL_F22M:
PCR.ctrl_clk_out_en.clk22_oen = en;
break;
case CLKOUT_SIG_PLL_F44M:
PCR.ctrl_clk_out_en.clk44_oen = en;
break;
case CLKOUT_SIG_PLL_F40M:
PCR.ctrl_clk_out_en.clk_bb_oen = en;
break;
case CLKOUT_SIG_PLL_F80M:
PCR.ctrl_clk_out_en.clk80_oen = en;
break;
case CLKOUT_SIG_PLL_F160M:
PCR.ctrl_clk_out_en.clk160_oen = en;
break;
case CLKOUT_SIG_PLL_F480M:
PCR.ctrl_clk_out_en.clk_480m_oen = en;
break;
case CLKOUT_SIG_XTAL:
PCR.ctrl_clk_out_en.clk_xtal_oen = en;
break;
default:
break;
}
}
#ifdef __cplusplus
}
#endif

14
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@@ -17,6 +17,7 @@
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/gpio_ext_reg.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
@@ -716,6 +717,19 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num
IO_MUX.gpio[gpio_num].mcu_oe = 1;
}
/**
* @brief Control the pin in the IOMUX
*
* @param bmap write mask of control value
* @param val Control value
* @param shift write mask shift of control value
*/
__attribute__((always_inline))
static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
{
SET_PERI_REG_BITS(GPIO_EXT_PIN_CTRL_REG, bmap, val, shift);
}
#ifdef __cplusplus
}
#endif