From e90d76e5b70a3f6fba5db9f2fd702a38e2c01ffb Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 9 Nov 2022 19:17:35 +0800 Subject: [PATCH] bugfix: fix uart fifo lost data issue --- components/hal/esp32c6/include/hal/uart_ll.h | 4 ++-- components/soc/esp32c6/include/soc/uart_struct.h | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h index 5411edebbf..c98beed511 100644 --- a/components/hal/esp32c6/include/hal/uart_ll.h +++ b/components/hal/esp32c6/include/hal/uart_ll.h @@ -271,7 +271,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) { for (int i = 0; i < (int)rd_len; i++) { - buf[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo, rxfifo_rd_byte); + buf[i] = hw->fifo.rxfifo_rd_byte; } } @@ -287,7 +287,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) { for (int i = 0; i < (int)wr_len; i++) { - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo, rxfifo_rd_byte, buf[i]); + hw->fifo.rxfifo_rd_byte = buf[i]; } } diff --git a/components/soc/esp32c6/include/soc/uart_struct.h b/components/soc/esp32c6/include/soc/uart_struct.h index 487c05b90a..d1deab0044 100644 --- a/components/soc/esp32c6/include/soc/uart_struct.h +++ b/components/soc/esp32c6/include/soc/uart_struct.h @@ -19,8 +19,7 @@ typedef union { /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; * UART $n accesses FIFO via this register. */ - uint32_t rxfifo_rd_byte:8; - uint32_t reserved_8:24; + uint32_t rxfifo_rd_byte:32; }; uint32_t val; } uart_fifo_reg_t;