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Merge branch 'refactor/rtc_cal_clk' into 'master'

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refactor(clk): add soc_clk_calibration_clk_src_t for all targets

Closes IDF-11790

See merge request espressif/esp-idf!40737
This commit is contained in:
Song Ruo Jing
2025-07-31 19:49:17 +08:00
parent 6bd8b52ad7 48233e0e7e
commit e94d9cee7a
89 changed files with 1078 additions and 953 deletions
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26
components/hal/esp32s3/include/hal/clk_tree_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,6 +13,7 @@
#include "soc/rtc_cntl_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h"
#include "soc/timer_group_struct.h"
#include "hal/assert.h"
#include "hal/log.h"
#include "esp32s3/rom/rtc.h"
@@ -494,6 +495,29 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
}
/**
* @brief Select the frequency calculation clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
{
switch (clk_sel) {
case CLK_CAL_RC_SLOW:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 0;
break;
case CLK_CAL_RC_FAST_D256:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 1;
break;
case CLK_CAL_32K_XTAL:
TIMERG0.rtccalicfg.rtc_cali_clk_sel = 2;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
}
/**
* @brief Select the clock source for RTC_SLOW_CLK
*