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sdmmc: I/O phase adjustments

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1. Fix incorrect meaning of SDMMC.clock bits, synchronize the names
   with the TRM.
2. Choose input and output phases to satisfy typical timing
   requirements.
3. Move use_hold_reg setting into the host driver, since it is related
   to timing.

Closes https://github.com/espressif/esp-idf/issues/8521
Related to https://github.com/espressif/esp-idf/issues/8257
This commit is contained in:
Ivan Grokhotkov
2022-03-12 00:53:43 +01:00
committed by Armando
parent ad46b43c2c
commit e9badf51c7
4 changed files with 21 additions and 23 deletions
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4
components/soc/esp32/include/soc/sdmmc_struct.h
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@@ -379,9 +379,9 @@ typedef volatile struct sdmmc_dev_s {
uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
uint32_t phase_din: 3; ///< phase of data input clock
uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
uint32_t div_factor_l: 4; ///< controls clock period; it will be (div_factor_l + 1) / 160MHz
uint32_t div_factor_n: 4; ///< should be equal to div_factor_l
uint32_t reserved21: 11;
};
uint32_t val;