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feat(esp32p4): added hal support
This commit is contained in:
Armando
550
components/hal/esp32p4/include/hal/clk_tree_ll.h
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550
components/hal/esp32p4/include/hal/clk_tree_ll.h
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/rtc.h"
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#include "hal/regi2c_ctrl.h"
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#include "soc/regi2c_bbpll.h"
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#include "hal/assert.h"
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#include "hal/log.h"
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#include "esp32p4/rom/rtc.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MHZ (1000000)
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#define CLK_LL_PLL_80M_FREQ_MHZ (80)
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#define CLK_LL_PLL_120M_FREQ_MHZ (120)
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#define CLK_LL_PLL_160M_FREQ_MHZ (160)
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#define CLK_LL_PLL_240M_FREQ_MHZ (240)
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#define CLK_LL_PLL_480M_FREQ_MHZ (480)
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#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
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.dac = 3, \
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.dres = 3, \
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.dgm = 3, \
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.dbuf = 1, \
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}
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/**
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* @brief XTAL32K_CLK enable modes
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*/
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typedef enum {
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CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL, //!< Enable the external 32kHz crystal for XTAL32K_CLK
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CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL, //!< Enable the external clock signal for OSC_SLOW_CLK
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CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP, //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */
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} clk_ll_xtal32k_enable_mode_t;
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/**
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* @brief XTAL32K_CLK configuration structure
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*/
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typedef struct {
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uint32_t dac : 6;
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uint32_t dres : 3;
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uint32_t dgm : 3;
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uint32_t dbuf: 1;
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} clk_ll_xtal32k_config_t;
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/**
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* @brief Power up BBPLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
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{
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}
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/**
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* @brief Power down BBPLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
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{
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}
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/**
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* @brief Enable the 32kHz crystal oscillator
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*
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* @param mode Used to determine the xtal32k configuration parameters
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
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{
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}
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/**
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* @brief Disable the 32kHz crystal oscillator
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
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{
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}
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/**
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* @brief Get the state of the 32kHz crystal clock
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*
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* @return True if the 32kHz XTAL is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
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{
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return 0;
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}
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/**
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* @brief Enable the internal oscillator output for RC32K_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void)
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{
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}
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/**
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* @brief Disable the internal oscillator output for RC32K_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void)
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{
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}
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/**
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* @brief Get the state of the internal oscillator for RC32K_CLK
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*
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* @return True if the oscillator is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void)
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{
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return 0;
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}
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/**
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* @brief Enable the internal oscillator output for RC_FAST_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
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{
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}
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/**
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* @brief Disable the internal oscillator output for RC_FAST_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
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{
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}
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/**
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* @brief Get the state of the internal oscillator for RC_FAST_CLK
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*
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* @return True if the oscillator is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
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{
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return 0;
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}
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/**
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* @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
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{
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}
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/**
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* @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
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{
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}
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/**
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* @brief Get the state of the digital RC_FAST_CLK
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*
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* @return True if the digital RC_FAST_CLK is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
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{
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return 0;
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}
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/**
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* @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
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{
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}
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/**
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* @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
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{
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}
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/**
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* @brief Get the state of the digital XTAL32K_CLK
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*
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* @return True if the digital XTAL32K_CLK is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
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{
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return 0;
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}
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/**
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* @brief Enable the digital RC32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void)
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{
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}
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/**
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* @brief Disable the digital RC32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void)
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{
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}
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/**
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* @brief Get the state of the digital RC32K_CLK
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*
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* @return True if the digital RC32K_CLK is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void)
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{
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return 0;
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}
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/**
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* @brief Get PLL_CLK frequency
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*
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* @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid.
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
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{
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// The target has a fixed 480MHz SPLL
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return CLK_LL_PLL_480M_FREQ_MHZ;
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}
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/**
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* @brief Set BBPLL frequency from XTAL source (Digital part)
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*
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* @param pll_freq_mhz PLL frequency, in MHz
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*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz)
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{
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}
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/**
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* @brief Set BBPLL frequency from XTAL source (Analog part)
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*
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* @param pll_freq_mhz PLL frequency, in MHz
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* @param xtal_freq_mhz XTAL frequency, in MHz
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*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
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{
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}
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/**
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* @brief Select the clock source for CPU_CLK (SOC Clock Root)
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*
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* @param in_sel One of the clock sources in soc_cpu_clk_src_t
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel)
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{
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}
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/**
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* @brief Get the clock source for CPU_CLK (SOC Clock Root)
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*
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* @return Currently selected clock source (one of soc_cpu_clk_src_t values)
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*/
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static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void)
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{
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return SOC_CPU_CLK_SRC_XTAL;
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}
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/**
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* @brief Set CPU_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
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*
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* @param divider Divider. (PCR_HS_DIV_NUM + 1) * (PCR_CPU_HS_DIV_NUM + 1) = divider.
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpu_set_hs_divider(uint32_t divider)
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{
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}
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/**
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* @brief Set CPU_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST)
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*
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* @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_CPU_LS_DIV_NUM + 1) = divider.
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpu_set_ls_divider(uint32_t divider)
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{
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}
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/**
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* @brief Get CPU_CLK's high-speed divider
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*
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* @return Divider. Divider = (PCR_HS_DIV_NUM + 1) * (PCR_CPU_HS_DIV_NUM + 1).
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_hs_divider(void)
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{
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return 0;
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}
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/**
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* @brief Get CPU_CLK's low-speed divider
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*
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* @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_CPU_LS_DIV_NUM + 1).
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_ls_divider(void)
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{
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return 0;
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}
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/**
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* @brief Set AHB_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
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*
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* @param divider Divider. (PCR_HS_DIV_NUM + 1) * (PCR_AHB_HS_DIV_NUM + 1) = divider.
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*/
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static inline __attribute__((always_inline)) void clk_ll_ahb_set_hs_divider(uint32_t divider)
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{
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}
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/**
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* @brief Set AHB_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST)
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*
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* @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1) = divider.
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*/
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static inline __attribute__((always_inline)) void clk_ll_ahb_set_ls_divider(uint32_t divider)
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{
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}
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/**
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* @brief Get AHB_CLK's high-speed divider
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*
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* @return Divider. Divider = (PCR_HS_DIV_NUM + 1) * (PCR_AHB_HS_DIV_NUM + 1).
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_hs_divider(void)
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{
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return 0;
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}
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/**
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* @brief Get AHB_CLK's low-speed divider
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*
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* @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1).
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_ls_divider(void)
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{
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return 0;
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}
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/**
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* @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider
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*
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* @param divider Divider. PCR_APB_DIV_NUM = divider - 1.
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*/
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static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider)
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{
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}
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/**
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* @brief Get APB_CLK divider
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*
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* @return Divider. Divider = (PCR_APB_DIV_NUM + 1).
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void)
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{
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return 0;
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}
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/**
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* @brief Set MSPI_FAST_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
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*
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* @param divider Divider.
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*/
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static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_hs_divider(uint32_t divider)
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{
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}
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/**
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* @brief Set MSPI_FAST_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST)
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*
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* @param divider Divider.
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*/
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static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divider(uint32_t divider)
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{
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}
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/**
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* @brief Select the calibration 32kHz clock source for timergroup0
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*
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* @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK)
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*/
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static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel)
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{
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}
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/**
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* @brief Get the calibration 32kHz clock source for timergroup0
|
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*
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* @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks)
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*/
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static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
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||||
{
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return 0;
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}
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|
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/**
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* @brief Select the clock source for RTC_SLOW_CLK
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*
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* @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
|
||||
*/
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||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
|
||||
{
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||||
|
||||
}
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||||
|
||||
/**
|
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* @brief Get the clock source for RTC_SLOW_CLK
|
||||
*
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* @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
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*/
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||||
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
|
||||
{
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||||
return 0;
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||||
}
|
||||
|
||||
/**
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||||
* @brief Select the clock source for RTC_FAST_CLK
|
||||
*
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||||
* @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
|
||||
*/
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static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
|
||||
{
|
||||
|
||||
}
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||||
|
||||
/**
|
||||
* @brief Get the clock source for RTC_FAST_CLK
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX.
|
||||
*
|
||||
* @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RC_FAST_CLK divider
|
||||
*
|
||||
* @return Divider. Divider = (CK8M_DIV_SEL + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
|
||||
{
|
||||
// No divider on the target, always return divider = 1
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RC_SLOW_CLK divider
|
||||
*
|
||||
* @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
|
||||
{
|
||||
}
|
||||
|
||||
/************************** LP STORAGE REGISTER STORE/LOAD **************************/
|
||||
/**
|
||||
* @brief Store XTAL_CLK frequency in RTC storage register
|
||||
*
|
||||
* Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
|
||||
* halves. These are the routines to work with that representation.
|
||||
*
|
||||
* @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
|
||||
* otherwise there will be a conflict with the low bit, which is used to disable logs
|
||||
* in the ROM code.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load XTAL_CLK frequency from RTC storage register
|
||||
*
|
||||
* Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
|
||||
* halves. These are the routines to work with that representation.
|
||||
*
|
||||
* @return XTAL frequency, in MHz. Returns 0 if value in reg is invalid.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void)
|
||||
{
|
||||
return 40;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store RTC_SLOW_CLK calibration value in RTC storage register
|
||||
*
|
||||
* Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds,
|
||||
* in Q13.19 fixed-point format).
|
||||
*
|
||||
* @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register
|
||||
*
|
||||
* This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches
|
||||
*
|
||||
* @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user