mirror of
https://github.com/espressif/esp-idf.git
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feat(esp32p4): added hal support
This commit is contained in:
Armando
450
components/hal/esp32p4/include/hal/mmu_ll.h
Normal file
450
components/hal/esp32p4/include/hal/mmu_ll.h
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@@ -0,0 +1,450 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for MMU register operations
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#pragma once
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#include "soc/spi_mem_c_reg.h"
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#include "soc/spi_mem_s_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/assert.h"
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#include "hal/mmu_types.h"
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#include "hal/efuse_ll.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Convert MMU virtual address to linear address
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*
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* @param vaddr virtual address
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*
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* @return linear address
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*/
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static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
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{
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return vaddr & SOC_MMU_LINEAR_FLASH_ADDR_MASK;
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}
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/**
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* Convert MMU linear address to virtual address
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*
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* @param laddr linear address
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* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
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*
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* @return virtual address
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*/
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static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type)
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{
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uint32_t raw_laddr = (laddr & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP);
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uint32_t vaddr_base = 0;
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if (vaddr_type == MMU_VADDR_FLASH) {
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vaddr_base = SOC_MMU_FLASH_VADDR_BASE;
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} else {
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vaddr_base = SOC_MMU_PSRAM_VADDR_BASE;
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}
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return vaddr_base | raw_laddr;
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}
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__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
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{
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unsigned cnt = efuse_ll_get_flash_crypt_cnt();
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// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
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cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
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return (cnt == 1);
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}
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/**
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* Get MMU page size
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*
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* @param mmu_id MMU ID
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*
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* @return MMU page size code
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*/
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__attribute__((always_inline))
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static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
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{
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(void)mmu_id;
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return MMU_PAGE_64KB;
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}
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/**
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* Set MMU page size
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*
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* @param size MMU page size
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*/
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__attribute__((always_inline))
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static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
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{
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(void)mmu_id;
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(void)size;
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return;
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}
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/**
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* Check if the external memory vaddr region is valid
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*
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* @param mmu_id MMU ID
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* @param vaddr_start start of the virtual address
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* @param len length, in bytes
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* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
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*
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* @return
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* True for valid
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*/
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__attribute__((always_inline))
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static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
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{
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(void)mmu_id;
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(void)type;
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uint32_t vaddr_end = vaddr_start + len;
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return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
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}
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/**
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* Check if the paddr region is valid
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*
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* @param mmu_id MMU ID
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* @param paddr_start start of the physical address
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* @param len length, in bytes
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*
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* @return
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* True for valid
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*/
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static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
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{
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(void)mmu_id;
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return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
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(len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
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((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM));
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}
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/**
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* To get the MMU table entry id to be mapped
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*
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* @param mmu_id MMU ID
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* @param vaddr virtual address to be mapped
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*
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* @return
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* MMU table entry id
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*/
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__attribute__((always_inline))
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static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
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{
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(void)mmu_id;
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mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
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uint32_t shift_code = 0;
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switch (page_size) {
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case MMU_PAGE_64KB:
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shift_code = 16;
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break;
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case MMU_PAGE_32KB:
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shift_code = 15;
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break;
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case MMU_PAGE_16KB:
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shift_code = 14;
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break;
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case MMU_PAGE_8KB:
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shift_code = 13;
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break;
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default:
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HAL_ASSERT(shift_code);
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}
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return ((vaddr & MMU_VADDR_MASK) >> shift_code);
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}
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/**
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* Format the paddr to be mappable
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*
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* @param mmu_id MMU ID
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* @param paddr physical address to be mapped
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* @param target paddr memory target, not used
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*
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* @return
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* mmu_val - paddr in MMU table supported format
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*/
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__attribute__((always_inline))
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static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
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{
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(void)mmu_id;
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(void)target;
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mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
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uint32_t shift_code = 0;
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switch (page_size) {
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case MMU_PAGE_64KB:
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shift_code = 16;
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break;
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case MMU_PAGE_32KB:
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shift_code = 15;
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break;
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case MMU_PAGE_16KB:
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shift_code = 14;
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break;
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case MMU_PAGE_8KB:
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shift_code = 13;
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break;
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default:
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HAL_ASSERT(shift_code);
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}
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return paddr >> shift_code;
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}
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/**
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* Write to the MMU table to map the virtual memory and the physical memory
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*
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* @param mmu_id MMU ID
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* @param entry_id MMU entry ID
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* @param mmu_val Value to be set into an MMU entry, for physical address
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* @param target MMU target physical memory.
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*/
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__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
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{
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(void)mmu_id;
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(void)target;
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uint32_t index_reg, content_reg, sensitive, invalid_mask;
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if (mmu_id == 0) { // flash mmu
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index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
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content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
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sensitive = MMU_SENSITIVE;
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invalid_mask = MMU_INVALID_MASK;
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} else { // psram mmu
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index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
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content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
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sensitive = DMMU_SENSITIVE;
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invalid_mask = DMMU_INVALID_MASK;
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mmu_val |= MMU_PSRAM_ACCESS_SPIRAM;
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}
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uint32_t mmu_raw_value;
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if (mmu_ll_cache_encryption_enabled()) {
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mmu_val |= sensitive;
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}
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/* Note: for ESP32-P4, invert invalid bit for compatible with upper-layer software */
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mmu_raw_value = mmu_val ^ invalid_mask;
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REG_WRITE(index_reg, entry_id);
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REG_WRITE(content_reg, mmu_raw_value);
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}
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/**
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* Read the raw value from MMU table
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*
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* @param mmu_id MMU ID
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* @param entry_id MMU entry ID
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* @param mmu_val Value to be read from MMU table
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*/
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__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
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{
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(void)mmu_id;
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uint32_t mmu_raw_value;
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uint32_t ret;
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uint32_t index_reg, content_reg, sensitive, invalid_mask;
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if (mmu_id == 0) { // flash mmu
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index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
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content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
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sensitive = MMU_SENSITIVE;
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invalid_mask = MMU_INVALID_MASK;
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} else { // psram mmu
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index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
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content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
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sensitive = DMMU_SENSITIVE;
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invalid_mask = DMMU_INVALID_MASK;
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}
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REG_WRITE(index_reg, entry_id);
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mmu_raw_value = REG_READ(content_reg);
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if (mmu_ll_cache_encryption_enabled()) {
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mmu_raw_value &= ~sensitive;
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}
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/* Note: for ESP32-P4, invert invalid bit for compatible with upper-layer software */
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ret = mmu_raw_value ^ invalid_mask;
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return ret;
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}
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/**
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* Set MMU table entry as invalid
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*
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* @param mmu_id MMU ID
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* @param entry_id MMU entry
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*/
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__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
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{
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uint32_t index_reg, content_reg;
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if (mmu_id == 0) { // flash mmu
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index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
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content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
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} else { // psram mmu
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index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
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content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
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}
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REG_WRITE(index_reg, entry_id);
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REG_WRITE(content_reg, MMU_INVALID);
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}
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/**
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* Unmap all the items in the MMU table
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*
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* @param mmu_id MMU ID
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*/
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__attribute__((always_inline))
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static inline void mmu_ll_unmap_all(uint32_t mmu_id)
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{
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for (int i = 0; i < MMU_ENTRY_NUM; i++) {
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mmu_ll_set_entry_invalid(mmu_id, i);
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}
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}
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/**
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* Check MMU table entry value is valid
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*
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* @param mmu_id MMU ID
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* @param entry_id MMU entry ID
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*
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* @return Ture for MMU entry is valid; False for invalid
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*/
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static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
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{
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uint32_t mmu_raw_value;
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uint32_t index_reg, content_reg, invalid_mask;
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if (mmu_id == 0) { // flash mmu
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index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
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content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
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invalid_mask = MMU_INVALID_MASK;
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} else { // psram mmu
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index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
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content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
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invalid_mask = DMMU_INVALID_MASK;
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}
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REG_WRITE(index_reg, entry_id);
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mmu_raw_value = REG_READ(content_reg);
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/* Note: for ESP32-P4, the invalid-bit of MMU: 0 for invalid, 1 for valid */
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return (mmu_raw_value & invalid_mask) ? true : false;
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}
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/**
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* Get the MMU table entry target
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*
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* @param mmu_id MMU ID
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* @param entry_id MMU entry ID
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*
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* @return Target, see `mmu_target_t`
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*/
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static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
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{
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if (mmu_id == 0)
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return MMU_TARGET_FLASH0;
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else
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return MMU_TARGET_PSRAM0;
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}
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/**
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* Convert MMU entry ID to paddr base
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*
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* @param mmu_id MMU ID
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* @param entry_id MMU entry ID
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*
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* @return paddr base
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*/
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static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
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{
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(void)mmu_id;
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HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
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mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
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uint32_t shift_code = 0;
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switch (page_size) {
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case MMU_PAGE_64KB:
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shift_code = 16;
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break;
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case MMU_PAGE_32KB:
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shift_code = 15;
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break;
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case MMU_PAGE_16KB:
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shift_code = 14;
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break;
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case MMU_PAGE_8KB:
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shift_code = 13;
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break;
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default:
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HAL_ASSERT(shift_code);
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}
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if (mmu_id == 0) {
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REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, entry_id);
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return (REG_READ(SPI_MEM_C_MMU_ITEM_CONTENT_REG) & MMU_VALID_VAL_MASK) << shift_code;
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} else {
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REG_WRITE(SPI_MEM_S_MMU_ITEM_INDEX_REG, entry_id);
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return (REG_READ(SPI_MEM_S_MMU_ITEM_CONTENT_REG) & MMU_VALID_VAL_MASK) << shift_code;
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}
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}
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|
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/**
|
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* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
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*
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* @return MMU entry ID, -1 for invalid
|
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*/
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static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
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{
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//TODO, should check PSRAM as well?
|
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(void)mmu_id;
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for (int i = 0; i < MMU_ENTRY_NUM; i++) {
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if (mmu_ll_check_entry_valid(mmu_id, i)) {
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if (mmu_ll_get_entry_target(mmu_id, i) == target) {
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REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, i);
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if ((REG_READ(SPI_MEM_C_MMU_ITEM_CONTENT_REG) & MMU_VALID_VAL_MASK) == mmu_val) {
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return i;
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||||
}
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||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user