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esp_hw_support: merge C3 changes to master

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Merge RTC related C3 changes to master
This commit is contained in:
Marius Vikhammer
2020-12-29 15:39:52 +08:00
parent 39cbf2f7ed
commit eb788deb03
20 changed files with 357 additions and 362 deletions
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135
components/soc/esp32c3/i2c_apll.h
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@@ -1,135 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file i2c_apll.h
* @brief Register definitions for audio PLL (APLL)
*
* This file lists register fields of APLL, located on an internal configuration
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
* rtc_clk_apll_enable function in rtc_clk.c.
*/
#define I2C_APLL 0X6D
#define I2C_APLL_HOSTID 3
#define I2C_APLL_IR_CAL_DELAY 0
#define I2C_APLL_IR_CAL_DELAY_MSB 3
#define I2C_APLL_IR_CAL_DELAY_LSB 0
#define I2C_APLL_IR_CAL_RSTB 0
#define I2C_APLL_IR_CAL_RSTB_MSB 4
#define I2C_APLL_IR_CAL_RSTB_LSB 4
#define I2C_APLL_IR_CAL_START 0
#define I2C_APLL_IR_CAL_START_MSB 5
#define I2C_APLL_IR_CAL_START_LSB 5
#define I2C_APLL_IR_CAL_UNSTOP 0
#define I2C_APLL_IR_CAL_UNSTOP_MSB 6
#define I2C_APLL_IR_CAL_UNSTOP_LSB 6
#define I2C_APLL_OC_ENB_FCAL 0
#define I2C_APLL_OC_ENB_FCAL_MSB 7
#define I2C_APLL_OC_ENB_FCAL_LSB 7
#define I2C_APLL_IR_CAL_EXT_CAP 1
#define I2C_APLL_IR_CAL_EXT_CAP_MSB 4
#define I2C_APLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_APLL_IR_CAL_ENX_CAP 1
#define I2C_APLL_IR_CAL_ENX_CAP_MSB 5
#define I2C_APLL_IR_CAL_ENX_CAP_LSB 5
#define I2C_APLL_OC_LBW 1
#define I2C_APLL_OC_LBW_MSB 6
#define I2C_APLL_OC_LBW_LSB 6
#define I2C_APLL_IR_CAL_CK_DIV 2
#define I2C_APLL_IR_CAL_CK_DIV_MSB 3
#define I2C_APLL_IR_CAL_CK_DIV_LSB 0
#define I2C_APLL_OC_DCHGP 2
#define I2C_APLL_OC_DCHGP_MSB 6
#define I2C_APLL_OC_DCHGP_LSB 4
#define I2C_APLL_OC_ENB_VCON 2
#define I2C_APLL_OC_ENB_VCON_MSB 7
#define I2C_APLL_OC_ENB_VCON_LSB 7
#define I2C_APLL_OR_CAL_CAP 3
#define I2C_APLL_OR_CAL_CAP_MSB 4
#define I2C_APLL_OR_CAL_CAP_LSB 0
#define I2C_APLL_OR_CAL_UDF 3
#define I2C_APLL_OR_CAL_UDF_MSB 5
#define I2C_APLL_OR_CAL_UDF_LSB 5
#define I2C_APLL_OR_CAL_OVF 3
#define I2C_APLL_OR_CAL_OVF_MSB 6
#define I2C_APLL_OR_CAL_OVF_LSB 6
#define I2C_APLL_OR_CAL_END 3
#define I2C_APLL_OR_CAL_END_MSB 7
#define I2C_APLL_OR_CAL_END_LSB 7
#define I2C_APLL_OR_OUTPUT_DIV 4
#define I2C_APLL_OR_OUTPUT_DIV_MSB 4
#define I2C_APLL_OR_OUTPUT_DIV_LSB 0
#define I2C_APLL_OC_TSCHGP 4
#define I2C_APLL_OC_TSCHGP_MSB 6
#define I2C_APLL_OC_TSCHGP_LSB 6
#define I2C_APLL_EN_FAST_CAL 4
#define I2C_APLL_EN_FAST_CAL_MSB 7
#define I2C_APLL_EN_FAST_CAL_LSB 7
#define I2C_APLL_OC_DHREF_SEL 5
#define I2C_APLL_OC_DHREF_SEL_MSB 1
#define I2C_APLL_OC_DHREF_SEL_LSB 0
#define I2C_APLL_OC_DLREF_SEL 5
#define I2C_APLL_OC_DLREF_SEL_MSB 3
#define I2C_APLL_OC_DLREF_SEL_LSB 2
#define I2C_APLL_SDM_DITHER 5
#define I2C_APLL_SDM_DITHER_MSB 4
#define I2C_APLL_SDM_DITHER_LSB 4
#define I2C_APLL_SDM_STOP 5
#define I2C_APLL_SDM_STOP_MSB 5
#define I2C_APLL_SDM_STOP_LSB 5
#define I2C_APLL_SDM_RSTB 5
#define I2C_APLL_SDM_RSTB_MSB 6
#define I2C_APLL_SDM_RSTB_LSB 6
#define I2C_APLL_OC_DVDD 6
#define I2C_APLL_OC_DVDD_MSB 4
#define I2C_APLL_OC_DVDD_LSB 0
#define I2C_APLL_DSDM2 7
#define I2C_APLL_DSDM2_MSB 5
#define I2C_APLL_DSDM2_LSB 0
#define I2C_APLL_DSDM1 8
#define I2C_APLL_DSDM1_MSB 7
#define I2C_APLL_DSDM1_LSB 0
#define I2C_APLL_DSDM0 9
#define I2C_APLL_DSDM0_MSB 7
#define I2C_APLL_DSDM0_LSB 0

34
components/soc/esp32c3/include/soc/rtc.h
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@@ -101,11 +101,11 @@ extern "C" {
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (1000)
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (2)
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (1000)
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (2)
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
/*
set sleep_init default param
@@ -117,6 +117,7 @@ set sleep_init default param
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
/**
* @brief Possible main XTAL frequency values.
@@ -232,9 +233,9 @@ typedef struct {
} x32k_config_t;
#define X32K_CONFIG_DEFAULT() { \
.dac = 1, \
.dac = 3, \
.dres = 3, \
.dgm = 0, \
.dgm = 3, \
.dbuf = 1, \
}
@@ -717,20 +718,15 @@ void rtc_sleep_low_init(uint32_t slowclk_period);
*/
void rtc_sleep_set_wakeup_time(uint64_t t);
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only)
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only)
#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only)
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
#define RTC_COCPU_TRIG_EN BIT(11)
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only)
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12)
#define RTC_COCPU_TRAP_TRIG_EN BIT(13)
#define RTC_USB_TRIG_EN BIT(14)
#define RTC_BROWNOUT_DET_TRIG_EN BIT(16)
/**
* @brief Enter deep or light sleep mode