mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-10 04:43:33 +00:00
Merge branch 'feature/esp32c5beta3_light_sleep_support_stage_1' into 'master'
feat(esp_hw_support): esp32c5 sleep support (Stage 2: support basic pmu sleep function) See merge request espressif/esp-idf!29549
This commit is contained in:
Wu Zheng Hui
17
components/hal/esp32c5/include/hal/lp_aon_hal.h
Normal file
17
components/hal/esp32c5/include/hal/lp_aon_hal.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/lp_aon_ll.h"
|
||||
|
||||
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
|
||||
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
|
||||
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
|
||||
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
|
||||
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
|
||||
|
||||
#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)
|
||||
97
components/hal/esp32c5/include/hal/lp_aon_ll.h
Normal file
97
components/hal/esp32c5/include/hal/lp_aon_ll.h
Normal file
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C5 LP_AON register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_aon_struct.h"
|
||||
#include "hal/misc.h"
|
||||
#include "esp32c5/rom/rtc.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source status
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the ext1 wakeup source status
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the wake-up LP_IO of the ext1 wake-up source
|
||||
* @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
|
||||
* @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level
|
||||
* each bit's corresponding position is set to 0, the wakeup level will be low
|
||||
* on the contrary, each bit's corresponding position is set to 1, the wakeup
|
||||
* level will be high
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask)
|
||||
{
|
||||
uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
|
||||
wakeup_sel_mask |= io_mask;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
|
||||
|
||||
uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
|
||||
wakeup_level_mask |= io_mask & level_mask;
|
||||
wakeup_level_mask &= ~(io_mask & ~level_mask);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear all ext1 wakup-source setting
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source setting
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
|
||||
* Set the flag to inform
|
||||
* @param true: deepsleep false: lightsleep
|
||||
*/
|
||||
static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
|
||||
{
|
||||
if (dslp) {
|
||||
REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
|
||||
|
||||
} else {
|
||||
REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
181
components/hal/esp32c5/include/hal/lp_timer_ll.h
Normal file
181
components/hal/esp32c5/include/hal/lp_timer_ll.h
Normal file
@@ -0,0 +1,181 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C5 LP_Timer register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#include "soc/lp_aon_reg.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/lp_timer_types.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set lp_timer alarm target
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
* @param timer_id lp_timer target num
|
||||
* @param value next alarm value
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->target[timer_id].hi.main_timer_tar_high = (value >> 32) & 0xFFFF;
|
||||
dev->target[timer_id].lo.main_timer_tar_low = value & 0xFFFFFFFF;
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable lp_timer alarm
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
* @param timer_id lp_timer target num
|
||||
* @param en enable bit
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->target[timer_id].hi.main_timer_tar_en = en;
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get lp_timer low bits value of counter
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
* @param buffer_id lp_timer counter buffer num
|
||||
*
|
||||
* @return The lp_timer low bits value of counter
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
return dev->counter[buffer_id].lo.main_timer_buf_low;
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get lp_timer high bits value of counter
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
* @param buffer_id lp_timer counter buffer num
|
||||
*
|
||||
* @return The lp_timer high bits value of counter
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
return dev->counter[buffer_id].hi.main_timer_buf_high;
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update lp_timer counter
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->update.main_timer_update = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear lp_timer alarm intr status
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->int_clr.soc_wakeup_int_clr = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear lp_timer overflow intr status
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->int_clr.overflow_clr = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear lp_timer lp_alarm intr status
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->lp_int_clr.main_timer_lp_int_clr = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Convert lp_timer time to count
|
||||
*
|
||||
* @param time_in_us time in us
|
||||
*
|
||||
* @return lp_timer count
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
#else
|
||||
HAL_ASSERT(false && "lp_timer not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
265
components/hal/esp32c5/include/hal/pau_ll.h
Normal file
265
components/hal/esp32c5/include/hal/pau_ll.h
Normal file
@@ -0,0 +1,265 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C5 PAU(Power Assist Unit) register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/pau_reg.h"
|
||||
#include "soc/pau_struct.h"
|
||||
#include "hal/pau_types.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
return dev->regdma_conf.flow_err;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.link_sel = link;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.to_mem = to_mem ? 1 : 0;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.start = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.start = 0;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.sel_mac = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.sel_mac = 0;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.start_mac = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_conf.start_mac = 0;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_link_0_addr.val = (uint32_t)link_addr;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_link_1_addr.val = (uint32_t)link_addr;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_link_2_addr.val = (uint32_t)link_addr;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_link_3_addr.val = (uint32_t)link_addr;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->regdma_link_mac_addr.val = (uint32_t)link_addr;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
return dev->regdma_current_link_addr.val;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
return dev->regdma_backup_addr.val;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
return dev->regdma_mem_addr.val;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
return dev->int_raw.val;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
return dev->int_st.val;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->int_ena.done_int_ena = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->int_ena.done_int_ena = 0;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->int_ena.error_int_ena = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->int_ena.error_int_ena = 0;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->int_clr.done_int_clr = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
dev->int_clr.error_int_clr = 1;
|
||||
#else
|
||||
HAL_ASSERT(false && "pau not supported yet");
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
73
components/hal/esp32c5/include/hal/sar_ctrl_ll.h
Normal file
73
components/hal/esp32c5/include/hal/sar_ctrl_ll.h
Normal file
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* SAR related peripherals are interdependent.
|
||||
* Related peripherals are:
|
||||
* - ADC
|
||||
* - PWDET
|
||||
*
|
||||
* All of above peripherals require SAR to work correctly.
|
||||
* As SAR has some registers that will influence above mentioned peripherals.
|
||||
* This file gives an abstraction for such registers
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/apb_saradc_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
|
||||
#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23)
|
||||
|
||||
|
||||
typedef enum {
|
||||
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
|
||||
SAR_CTRL_LL_POWER_ON, //SAR power on
|
||||
SAR_CTRL_LL_POWER_OFF, //SAR power off
|
||||
} sar_ctrl_ll_power_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
SAR power control
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Set SAR power mode when controlled by PWDET
|
||||
*
|
||||
* @param[in] mode See `sar_ctrl_ll_power_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
|
||||
{
|
||||
if (mode == SAR_CTRL_LL_POWER_FSM) {
|
||||
REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
|
||||
} else if (mode == SAR_CTRL_LL_POWER_ON) {
|
||||
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
|
||||
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
|
||||
} else if (mode == SAR_CTRL_LL_POWER_OFF) {
|
||||
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
|
||||
REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SAR power ctrl source
|
||||
*
|
||||
* @param[in] force set PWDET as SAR power ctrl source when force is true
|
||||
*/
|
||||
static inline void sar_ctrl_ll_force_power_ctrl_from_pwdet(bool force)
|
||||
{
|
||||
APB_SARADC.saradc_ctrl.saradc_saradc2_pwdet_drv = force;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
56
components/hal/esp32c5/pau_hal.c
Normal file
56
components/hal/esp32c5/pau_hal.c
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pau_hal.h"
|
||||
#include "hal/pau_types.h"
|
||||
|
||||
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
|
||||
{
|
||||
pau_ll_set_regdma_link0_addr(hal->dev, (*link_addr)[0]);
|
||||
pau_ll_set_regdma_link1_addr(hal->dev, (*link_addr)[1]);
|
||||
pau_ll_set_regdma_link2_addr(hal->dev, (*link_addr)[2]);
|
||||
/* The link 3 of REGDMA is reserved, PMU state switching will not use
|
||||
* REGDMA link 3 */
|
||||
}
|
||||
|
||||
void pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
|
||||
{
|
||||
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
|
||||
pau_ll_set_regdma_select_wifimac_link(hal->dev);
|
||||
pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
|
||||
pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
|
||||
|
||||
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
|
||||
}
|
||||
|
||||
void pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
|
||||
{
|
||||
pau_ll_set_regdma_wifimac_link_backup_start_disable(hal->dev);
|
||||
pau_ll_set_regdma_deselect_wifimac_link(hal->dev);
|
||||
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
|
||||
}
|
||||
|
||||
void pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore)
|
||||
{
|
||||
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
|
||||
/* The link 3 of REGDMA is reserved, we use it as an extra linked list to
|
||||
* provide backup and restore services for BLE, IEEE802.15.4 and possibly
|
||||
* other modules */
|
||||
pau_ll_select_regdma_entry_link(hal->dev, 3);
|
||||
pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore);
|
||||
pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev);
|
||||
|
||||
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
|
||||
}
|
||||
|
||||
void pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
|
||||
{
|
||||
pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev);
|
||||
pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */
|
||||
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
|
||||
}
|
||||
@@ -4,8 +4,6 @@
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PAU (ESP32-C6 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pau_hal.h"
|
||||
|
||||
@@ -4,8 +4,6 @@
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PAU (ESP32-C6 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
Reference in New Issue
Block a user