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Merge branch 'feature/usb_p4_ver2' into 'master'

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feat(usb/host): Add USB support to ESP32-P4 v3 (ECO5)

Closes IDF-13507 and IDF-13742

See merge request espressif/esp-idf!41602
This commit is contained in:
Tomas Rezucha
2025-09-20 14:57:53 +02:00
parent 44a66c7521 ce590e4bae
commit ecc1144054
9 changed files with 238 additions and 165 deletions
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29
components/hal/esp32p4/include/hal/usb_dwc_ll.h
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@@ -28,7 +28,8 @@ extern "C" {
----------------------------------------------------------------------------- */
#define USB_DWC_QTD_LIST_MEM_ALIGN 512
#define USB_DWC_FRAME_LIST_MEM_ALIGN 512 // The frame list needs to be 512 bytes aligned (contrary to the databook)
#define USB_DWC_FRAME_LIST_MEM_ALIGN 512 // The frame list needs to be 512 bytes aligned (contrary to the databook)
#define USB_DWC_CORE_REG_GSNPSID_4_20a 0x4F54420A // From 4.20a upward, the reset sequence is changed
/* -----------------------------------------------------------------------------
------------------------------- Global Registers -------------------------------
@@ -279,12 +280,28 @@ static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw)
static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw)
{
hw->grstctl_reg.csftrst = 1;
}
const uint32_t gnspsid = hw->gsnpsid_reg.val;
static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw)
{
return hw->grstctl_reg.csftrst;
// Start core soft reset
hw->grstctl_reg.csftrst = 1;
// Wait for the reset to complete
if (gnspsid < USB_DWC_CORE_REG_GSNPSID_4_20a) {
// Version < 4.20a
while (hw->grstctl_reg.csftrst) {
;
}
} else {
// Version >= 4.20a
while (!(hw->grstctl_reg.csftrstdone)) {
;
}
usb_dwc_grstctl_reg_t grstctl;
grstctl.val = hw->grstctl_reg.val;
grstctl.csftrst = 0; // Clear RESET bit once reset is done
grstctl.csftrstdone = 1; // Write 1 to clear RESET_DONE bit
hw->grstctl_reg.val = grstctl.val;
}
}
// --------------------------- GINTSTS Register --------------------------------