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https://github.com/espressif/esp-idf.git
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Merge branch 'feature/usb_p4_ver2' into 'master'
feat(usb/host): Add USB support to ESP32-P4 v3 (ECO5) Closes IDF-13507 and IDF-13742 See merge request espressif/esp-idf!41602
This commit is contained in:
Tomas Rezucha
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -14,10 +14,13 @@ extern "C" {
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/*
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Registers and fields were generated based on a set of USB-DWC configuration options.
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ESP32-P4 contains 2 instances of USB-DWC with different configurations, the structure below corresponds to the HS instance.
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The FS instance contains a subset of registers from HS instance, the user (HAL) is responsible for accessing only existing fields.
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ESP32-P4 contains 2 instances of USB-DWC with different configurations and versions, the structure below corresponds to the High Speed v4.30a instance.
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The Full Speed instance contains a subset of registers from High Speed instance, the user (HAL) is responsible for accessing only existing fields.
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See ESP32-P4 "usb_dwc_cfg.h" for more details.
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List of changes v4.00a -> v4.30a
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- GRSTCTL register now contains the CSftRstDone bit which indicates the completion of a soft reset.
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*/
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/* ---------------------------- Register Types ------------------------------ */
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@@ -129,7 +132,8 @@ typedef union {
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uint32_t rxfflsh: 1;
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uint32_t txfflsh: 1;
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uint32_t txfnum: 5;
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uint32_t reserved_11: 19;
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uint32_t reserved_11: 18;
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uint32_t csftrstdone: 1;
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uint32_t dmareq: 1;
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uint32_t ahbidle: 1;
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};
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181
components/soc/esp32p4/register/hw_ver3/soc/usb_dwc_cfg.h
Normal file
181
components/soc/esp32p4/register/hw_ver3/soc/usb_dwc_cfg.h
Normal file
@@ -0,0 +1,181 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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HS Instance:
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Configuration Set ID: 11
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*/
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/* 3.1 Basic Config Parameters */
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#define OTG20_MODE 0
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#define OTG20_ARCHITECTURE 2
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#define OTG20_SINGLE_POINT 1
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#define OTG20_ENABLE_LPM 0
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#define OTG20_EN_DED_TX_FIFO 1
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#define OTG20_EN_DESC_DMA 1
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#define OTG20_MULTI_PROC_INTRPT 1
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/* 3.2 USB Physical Layer Interface Parameters */
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#define OTG20_HSPHY_INTERFACE 3 // Although we support both UTMI+ and ULPI, the ULPI is not wired out of the USB-DWC. Hence only UTMI+ can be used
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#define OTG20_HSPHY_DWIDTH 2
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#define OTG20_FSPHY_INTERFACE 2
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#define OTG20_ENABLE_IC_USB 0
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#define OTG20_ENABLE_HSIC 0
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#define OTG20_I2C_INTERFACE 0
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#define OTG20_ULPI_CARKIT 1
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#define OTG20_ADP_SUPPORT 1
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#define OTG20_BC_SUPPORT 0
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#define OTG20_VENDOR_CTL_INTERFACE 1
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/* 3.3 Device Endpoint Configuration Parameters */
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#define OTG20_NUM_EPS 15
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#define OTG20_NUM_IN_EPS 8
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#define OTG20_NUM_CRL_EPS 1
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/* 3.4 Host Endpoint Configuration Parameters */
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#define OTG20_NUM_HOST_CHAN 16
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#define OTG20_EN_PERIO_HOST 1
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/* 3.5 Endpoint Channel FIFO Configuration Parameters */
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#define OTG20_DFIFO_DEPTH 1024
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#define OTG20_DFIFO_DYNAMIC 1
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#define OTG20_RX_DFIFO_DEPTH 1024
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#define OTG20_TX_HNPERIO_DFIFO_DEPTH 1024
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#define OTG20_TX_HPERIO_DFIFO_DEPTH 1024
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#define OTG20_NPERIO_TX_QUEUE_DEPTH 8
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#define OTG20_PERIO_TX_QUEUE_DEPTH 16
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/* 3.6 Additional Configuration Options Parameters */
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#define OTG20_TRANS_COUNT_WIDTH 17
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#define OTG20_PACKET_COUNT_WIDTH 8
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#define OTG20_RM_OPT_FEATURES 1
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#define OTG20_EN_PWROPT 1
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#define OTG20_SYNC_RESET_TYPE 0
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#define OTG20_EN_IDDIG_FILTER 1
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#define OTG20_EN_VBUSVALID_FILTER 1
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#define OTG20_EN_A_VALID_FILTER 1
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#define OTG20_EN_B_VALID_FILTER 1
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#define OTG20_EN_SESSIONEND_FILTER 1
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#define OTG20_EXCP_CNTL_XFER_FLOW 1
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#define OTG20_PWR_CLAMP 0
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#define OTG20_PWR_SWITCH_POLARITY 0
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/* 3.7 Endpoint Direction Parameters */
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#define OTG20_EP_DIR_1 0
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#define OTG20_EP_DIR_2 0
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#define OTG20_EP_DIR_3 0
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#define OTG20_EP_DIR_4 0
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#define OTG20_EP_DIR_5 0
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#define OTG20_EP_DIR_6 0
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#define OTG20_EP_DIR_7 0
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#define OTG20_EP_DIR_8 0
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#define OTG20_EP_DIR_9 0
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#define OTG20_EP_DIR_10 0
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#define OTG20_EP_DIR_11 0
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#define OTG20_EP_DIR_12 0
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#define OTG20_EP_DIR_13 0
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#define OTG20_EP_DIR_14 0
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#define OTG20_EP_DIR_15 0
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/* 3.8 Device Periodic FIFO Depth Parameters */
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/* 3.9 Device IN Endpoint FIFO Depth Parameters */
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#define OTG20_TX_DINEP_DFIFO_DEPTH_0 512
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#define OTG20_TX_DINEP_DFIFO_DEPTH_1 512
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#define OTG20_TX_DINEP_DFIFO_DEPTH_2 512
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#define OTG20_TX_DINEP_DFIFO_DEPTH_3 512
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#define OTG20_TX_DINEP_DFIFO_DEPTH_4 512
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#define OTG20_TX_DINEP_DFIFO_DEPTH_5 512
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#define OTG20_TX_DINEP_DFIFO_DEPTH_6 512
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#define OTG20_TX_DINEP_DFIFO_DEPTH_7 512
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/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
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#define OTG20_U2UB_EN 0
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/*
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FS Instance:
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Configuration Set ID: 1
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*/
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/* 3.1 Basic Config Parameters */
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#define OTG11_MODE 0
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#define OTG11_ARCHITECTURE 2
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#define OTG11_SINGLE_POINT 1
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#define OTG11_ENABLE_LPM 0
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#define OTG11_EN_DED_TX_FIFO 1
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#define OTG11_EN_DESC_DMA 1
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#define OTG11_MULTI_PROC_INTRPT 0
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/* 3.2 USB Physical Layer Interface Parameters */
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#define OTG11_HSPHY_INTERFACE 0
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#define OTG11_FSPHY_INTERFACE 1
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#define OTG11_ENABLE_IC_USB 0
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#define OTG11_I2C_INTERFACE 0
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#define OTG11_ADP_SUPPORT 0
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#define OTG11_BC_SUPPORT 0
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/* 3.3 Device Endpoint Configuration Parameters */
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#define OTG11_NUM_EPS 6
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#define OTG11_NUM_IN_EPS 5
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#define OTG11_NUM_CRL_EPS 0
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/* 3.4 Host Endpoint Configuration Parameters */
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#define OTG11_NUM_HOST_CHAN 8
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#define OTG11_EN_PERIO_HOST 1
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/* 3.5 Endpoint Channel FIFO Configuration Parameters */
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#define OTG11_DFIFO_DEPTH 256
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#define OTG11_DFIFO_DYNAMIC 1
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#define OTG11_RX_DFIFO_DEPTH 256
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#define OTG11_TX_HNPERIO_DFIFO_DEPTH 256
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#define OTG11_TX_NPERIO_DFIFO_DEPTH 256
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#define OTG11_TX_HPERIO_DFIFO_DEPTH 256
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#define OTG11_NPERIO_TX_QUEUE_DEPTH 4
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#define OTG11_PERIO_TX_QUEUE_DEPTH 8
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/* 3.6 Additional Configuration Options Parameters */
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#define OTG11_TRANS_COUNT_WIDTH 16
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#define OTG11_PACKET_COUNT_WIDTH 7
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#define OTG11_RM_OPT_FEATURES 1
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#define OTG11_EN_PWROPT 1
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#define OTG11_SYNC_RESET_TYPE 0
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#define OTG11_EN_IDDIG_FILTER 1
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#define OTG11_EN_VBUSVALID_FILTER 1
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#define OTG11_EN_A_VALID_FILTER 1
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#define OTG11_EN_B_VALID_FILTER 1
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#define OTG11_EN_SESSIONEND_FILTER 1
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#define OTG11_EXCP_CNTL_XFER_FLOW 1
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#define OTG11_PWR_CLAMP 0
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#define OTG11_PWR_SWITCH_POLARITY 0
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/* 3.7 Endpoint Direction Parameters */
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#define OTG11_EP_DIR_1 0
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#define OTG11_EP_DIR_2 0
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#define OTG11_EP_DIR_3 0
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#define OTG11_EP_DIR_4 0
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#define OTG11_EP_DIR_5 0
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#define OTG11_EP_DIR_6 0
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/* 3.8 Device Periodic FIFO Depth Parameters */
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/* 3.9 Device IN Endpoint FIFO Depth Parameters */
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#define OTG11_TX_DINEP_DFIFO_DEPTH_1 256
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#define OTG11_TX_DINEP_DFIFO_DEPTH_2 256
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#define OTG11_TX_DINEP_DFIFO_DEPTH_3 256
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#define OTG11_TX_DINEP_DFIFO_DEPTH_4 256
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/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
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#define OTG11_U2UB_EN 0
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#ifdef __cplusplus
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}
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#endif
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@@ -1,139 +0,0 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: USB wrapper registers. */
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/** Type of otg_conf register
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* USB wrapper configuration registers.
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*/
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typedef union {
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struct {
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/** srp_sessend_override : R/W; bitpos: [0]; default: 0;
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* This bit is used to enable the software over-ride of srp session end signal. 1'b0:
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* the signal is controlled by the chip input, 1'b1: the signal is controlled by the
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* software.
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*/
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uint32_t srp_sessend_override:1;
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/** srp_sessend_value : R/W; bitpos: [1]; default: 0;
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* Software over-ride value of srp session end signal.
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*/
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uint32_t srp_sessend_value:1;
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/** phy_sel : R/W; bitpos: [2]; default: 0;
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* Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
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*/
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uint32_t phy_sel:1;
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/** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
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* Force the dfifo to go into low power mode. The data in dfifo will not lost.
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*/
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uint32_t dfifo_force_pd:1;
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/** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
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* Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
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*/
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uint32_t dbnce_fltr_bypass:1;
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/** exchg_pins_override : R/W; bitpos: [5]; default: 0;
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* Enable software controlle USB D+ D- exchange
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*/
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uint32_t exchg_pins_override:1;
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/** exchg_pins : R/W; bitpos: [6]; default: 0;
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* USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
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*/
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uint32_t exchg_pins:1;
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/** vrefh : R/W; bitpos: [8:7]; default: 0;
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* Control single-end input high threshold,1.76V to 2V, step 80mV.
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*/
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uint32_t vrefh:2;
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/** vrefl : R/W; bitpos: [10:9]; default: 0;
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* Control single-end input low threshold,0.8V to 1.04V, step 80mV.
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*/
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uint32_t vrefl:2;
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/** vref_override : R/W; bitpos: [11]; default: 0;
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* Enable software controlle input threshold.
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*/
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uint32_t vref_override:1;
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/** pad_pull_override : R/W; bitpos: [12]; default: 0;
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* Enable software controlle USB D+ D- pullup pulldown.
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*/
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uint32_t pad_pull_override:1;
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/** dp_pullup : R/W; bitpos: [13]; default: 0;
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* Controlle USB D+ pullup.
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*/
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uint32_t dp_pullup:1;
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/** dp_pulldown : R/W; bitpos: [14]; default: 0;
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* Controlle USB D+ pulldown.
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*/
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uint32_t dp_pulldown:1;
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/** dm_pullup : R/W; bitpos: [15]; default: 0;
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* Controlle USB D+ pullup.
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*/
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uint32_t dm_pullup:1;
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/** dm_pulldown : R/W; bitpos: [16]; default: 0;
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* Controlle USB D+ pulldown.
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*/
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uint32_t dm_pulldown:1;
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/** pullup_value : R/W; bitpos: [17]; default: 0;
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* Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
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*/
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uint32_t pullup_value:1;
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/** usb_pad_enable : R/W; bitpos: [18]; default: 0;
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* Enable USB pad function.
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*/
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uint32_t usb_pad_enable:1;
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/** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
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* Force ahb clock always on.
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*/
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uint32_t ahb_clk_force_on:1;
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/** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
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* Force phy clock always on.
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*/
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uint32_t phy_clk_force_on:1;
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uint32_t reserved_21:1;
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/** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
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* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
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*/
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uint32_t dfifo_force_pu:1;
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uint32_t reserved_23:8;
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/** clk_en : R/W; bitpos: [31]; default: 0;
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* Disable auto clock gating of CSR registers.
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*/
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uint32_t clk_en:1;
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};
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uint32_t val;
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} usb_wrap_otg_conf_reg_t;
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/** Type of date register
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* Date register.
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*/
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typedef union {
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struct {
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/** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
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* Date register.
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*/
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uint32_t usb_wrap_date:32;
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};
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uint32_t val;
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} usb_wrap_date_reg_t;
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typedef struct {
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volatile usb_wrap_otg_conf_reg_t otg_conf;
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uint32_t reserved_004[254];
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volatile usb_wrap_date_reg_t date;
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} usb_wrap_dev_t;
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extern usb_wrap_dev_t USB_WRAP;
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#ifndef __cplusplus
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_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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