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esp32c2: xts-aes register prefix discrepency

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This commit is contained in:
harshal.patil
2023-05-17 11:18:13 +05:30
parent 0058fb3a05
commit ed4ceea43d
4 changed files with 150 additions and 22 deletions
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20
components/hal/esp32c2/include/hal/spi_flash_encrypted_ll.h
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@@ -15,7 +15,7 @@
#include <stdbool.h>
#include <string.h>
#include "soc/system_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/xts_aes_reg.h"
#include "soc/soc.h"
#include "hal/assert.h"
@@ -60,7 +60,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
// Our hardware only support flash encryption
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
REG_WRITE(AES_XTS_DESTINATION_REG, type);
REG_WRITE(XTS_AES_DESTINATION_REG, type);
}
/**
@@ -71,7 +71,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
{
// Desired block should not be larger than the block size.
REG_WRITE(AES_XTS_SIZE_REG, size >> 5);
REG_WRITE(XTS_AES_LINESIZE_REG, size >> 5);
}
/**
@@ -85,7 +85,7 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
{
uint32_t plaintext_offs = (address % 64);
memcpy((void *)(AES_XTS_PLAIN_BASE + plaintext_offs), buffer, size);
memcpy((void *)(XTS_AES_PLAIN_MEM + plaintext_offs), buffer, size);
}
/**
@@ -95,7 +95,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
*/
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
{
REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr);
REG_WRITE(XTS_AES_PHYSICAL_ADDRESS_REG, flash_addr);
}
/**
@@ -103,7 +103,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
*/
static inline void spi_flash_encrypt_ll_calculate_start(void)
{
REG_WRITE(AES_XTS_TRIGGER_REG, 1);
REG_WRITE(XTS_AES_TRIGGER_REG, 1);
}
/**
@@ -111,7 +111,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_READ(AES_XTS_STATE_REG) == 0x1) {
while(REG_READ(XTS_AES_STATE_REG) == 0x1) {
}
}
@@ -120,8 +120,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
*/
static inline void spi_flash_encrypt_ll_done(void)
{
REG_WRITE(AES_XTS_RELEASE_REG, 1);
while(REG_READ(AES_XTS_STATE_REG) != 0x3) {
REG_WRITE(XTS_AES_RELEASE_REG, 1);
while(REG_READ(XTS_AES_STATE_REG) != 0x3) {
}
}
@@ -130,7 +130,7 @@ static inline void spi_flash_encrypt_ll_done(void)
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
REG_WRITE(AES_XTS_DESTROY_REG, 1);
REG_WRITE(XTS_AES_DESTROY_REG, 1);
}
/**