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spi_flash: 2nd stage for supporting flash suspend. (1). Support more esp chips (2). Improve real-time performance (3). Making timing more stable (4) Add documents

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This commit is contained in:
Cao Sen Miao
2023-05-11 20:10:30 +08:00
parent 476e50b026
commit ed96dadd06
34 changed files with 514 additions and 103 deletions
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12
components/hal/esp32c6/include/hal/gpspi_flash_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -140,6 +140,16 @@ static inline void gpspi_flash_ll_user_start(spi_dev_t *dev)
dev->cmd.usr = 1;
}
/**
* In user mode, it is set to indicate that program/erase operation will be triggered.
*
* @param dev Beginning address of the peripheral registers.
*/
static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
{
// Not supported on GPSPI
}
/**
* Set HD pin high when flash work at spi mode.
*

4
components/hal/esp32c6/include/hal/spi_flash_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -65,6 +65,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) { /* Not supported on gpspi on ESP32-C6*/ }
#define spi_flash_ll_set_pe_bit(dev) gpspi_flash_ll_set_pe_bit((spi_dev_t*)dev)
#else
#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
@@ -92,6 +93,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_set_pe_bit(dev) spimem_flash_ll_set_pe_bit((spi_mem_dev_t*)dev)
#endif

68
components/hal/esp32c6/include/hal/spimem_flash_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -33,6 +33,8 @@ extern "C" {
#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL ))
#define spimem_flash_ll_hw_get_id(dev) ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1)
#define SPIMEM_FLASH_LL_SPI0_MAX_LOCK_VAL_MSPI_TICKS (0x1f)
typedef typeof(SPIMEM1.clock.val) spimem_flash_ll_clock_reg_t;
/*------------------------------------------------------------------------------
@@ -208,6 +210,30 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
}
/**
* Configure the delay after Suspend/Resume
*
* @param dev Beginning address of the peripheral registers.
* @param dly_val delay time
*/
static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dly_val)
{
dev->ctrl1.cs_hold_dly_res = dly_val;
dev->sus_status.flash_per_dly_128 = 1;
dev->sus_status.flash_pes_dly_128 = 1;
}
/**
* Configure the cs hold delay time(used to set the minimum CS high time tSHSL)
*
* @param dev Beginning address of the peripheral registers.
* @param cs_hold_delay cs hold delay time
*/
static inline void spimem_flash_set_cs_hold_delay(spi_mem_dev_t *dev, uint32_t cs_hold_delay)
{
SPIMEM0.ctrl2.cs_hold_delay = cs_hold_delay;
}
/**
* Initialize auto wait idle mode
*
@@ -233,6 +259,35 @@ static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
return dev->sus_status.flash_sus;
}
/**
* @brief Set lock for SPI0 so that spi0 can request new cache request after a cache transfer.
*
* @param dev Beginning address of the peripheral registers.
* @param lock_time Lock delay time
*/
static inline void spimem_flash_ll_sus_set_spi0_lock_trans(spi_mem_dev_t *dev, uint32_t lock_time)
{
dev->sus_status.spi0_lock_en = 1;
SPIMEM0.fsm.lock_delay_time = lock_time;
}
/**
* @brief Get tsus unit values in SPI_CLK cycles
*
* @param dev Beginning address of the peripheral registers.
* @return uint32_t tsus unit values
*/
static inline uint32_t spimem_flash_ll_get_tsus_unit_in_cycles(spi_mem_dev_t *dev)
{
uint32_t tsus_unit = 0;
if (dev->sus_status.flash_pes_dly_128 == 1) {
tsus_unit = 128;
} else {
tsus_unit = 4;
}
return tsus_unit;
}
/**
* Enable/disable write protection for the flash chip.
*
@@ -321,6 +376,17 @@ static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev)
dev->cmd.usr = 1;
}
/**
* In user mode, it is set to indicate that program/erase operation will be triggered.
* This function is combined with `spimem_flash_ll_user_start`. The pe_bit will be cleared automatically once the operation done.
*
* @param dev Beginning address of the peripheral registers.
*/
static inline void spimem_flash_ll_set_pe_bit(spi_mem_dev_t *dev)
{
dev->cmd.flash_pe = 1;
}
/**
* Check whether the host is idle to perform new commands.
*