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sdmmc: add peripheral driver and protocol layer
This commit is contained in:
Ivan Grokhotkov
committed by
Ivan Grokhotkov
Ivan Grokhotkov
parent
0efaa4f4b8
commit
edd924f273
303
components/driver/include/driver/sdmmc_defs.h
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303
components/driver/include/driver/sdmmc_defs.h
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@@ -0,0 +1,303 @@
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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* Adaptations to ESP-IDF Copyright (c) 2016 Espressif Systems (Shanghai) PTE LTD
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _SDMMC_DEFS_H_
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#define _SDMMC_DEFS_H_
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#include <stdint.h>
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#include <limits.h>
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/* MMC commands */ /* response type */
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#define MMC_GO_IDLE_STATE 0 /* R0 */
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#define MMC_SEND_OP_COND 1 /* R3 */
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#define MMC_ALL_SEND_CID 2 /* R2 */
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#define MMC_SET_RELATIVE_ADDR 3 /* R1 */
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#define MMC_SWITCH 6 /* R1B */
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#define MMC_SELECT_CARD 7 /* R1 */
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#define MMC_SEND_EXT_CSD 8 /* R1 */
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#define MMC_SEND_CSD 9 /* R2 */
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#define MMC_STOP_TRANSMISSION 12 /* R1B */
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#define MMC_SEND_STATUS 13 /* R1 */
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#define MMC_SET_BLOCKLEN 16 /* R1 */
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#define MMC_READ_BLOCK_SINGLE 17 /* R1 */
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#define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */
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#define MMC_SET_BLOCK_COUNT 23 /* R1 */
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#define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */
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#define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */
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#define MMC_APP_CMD 55 /* R1 */
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/* SD commands */ /* response type */
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#define SD_SEND_RELATIVE_ADDR 3 /* R6 */
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#define SD_SEND_SWITCH_FUNC 6 /* R1 */
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#define SD_SEND_IF_COND 8 /* R7 */
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/* SD application commands */ /* response type */
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#define SD_APP_SET_BUS_WIDTH 6 /* R1 */
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#define SD_APP_OP_COND 41 /* R3 */
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#define SD_APP_SEND_SCR 51 /* R1 */
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/* OCR bits */
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#define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */
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#define MMC_OCR_ACCESS_MODE_MASK 0x60000000 /* bits 30:29 */
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#define MMC_OCR_SECTOR_MODE (1<<30)
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#define MMC_OCR_BYTE_MODE (1<<29)
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#define MMC_OCR_3_5V_3_6V (1<<23)
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#define MMC_OCR_3_4V_3_5V (1<<22)
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#define MMC_OCR_3_3V_3_4V (1<<21)
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#define MMC_OCR_3_2V_3_3V (1<<20)
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#define MMC_OCR_3_1V_3_2V (1<<19)
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#define MMC_OCR_3_0V_3_1V (1<<18)
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#define MMC_OCR_2_9V_3_0V (1<<17)
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#define MMC_OCR_2_8V_2_9V (1<<16)
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#define MMC_OCR_2_7V_2_8V (1<<15)
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#define MMC_OCR_2_6V_2_7V (1<<14)
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#define MMC_OCR_2_5V_2_6V (1<<13)
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#define MMC_OCR_2_4V_2_5V (1<<12)
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#define MMC_OCR_2_3V_2_4V (1<<11)
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#define MMC_OCR_2_2V_2_3V (1<<10)
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#define MMC_OCR_2_1V_2_2V (1<<9)
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#define MMC_OCR_2_0V_2_1V (1<<8)
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#define MMC_OCR_1_65V_1_95V (1<<7)
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#define SD_OCR_SDHC_CAP (1<<30)
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#define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */
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/* R1 response type bits */
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#define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */
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#define MMC_R1_APP_CMD (1<<5) /* app. commands supported */
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/* 48-bit response decoding (32 bits w/o CRC) */
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#define MMC_R1(resp) ((resp)[0])
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#define MMC_R3(resp) ((resp)[0])
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#define SD_R6(resp) ((resp)[0])
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#define MMC_R1_CURRENT_STATE(resp) (((resp)[0] >> 9) & 0xf)
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/* RCA argument and response */
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#define MMC_ARG_RCA(rca) ((rca) << 16)
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#define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
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/* bus width argument */
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#define SD_ARG_BUS_WIDTH_1 0
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#define SD_ARG_BUS_WIDTH_4 2
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/* EXT_CSD fields */
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#define EXT_CSD_BUS_WIDTH 183 /* WO */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_STRUCTURE 194 /* RO */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_SEC_COUNT 212 /* RO */
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/* EXT_CSD field definitions */
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#define EXT_CSD_CMD_SET_NORMAL (1U << 0)
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#define EXT_CSD_CMD_SET_SECURE (1U << 1)
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#define EXT_CSD_CMD_SET_CPSECURE (1U << 2)
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/* EXT_CSD_HS_TIMING */
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#define EXT_CSD_HS_TIMING_BC 0
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#define EXT_CSD_HS_TIMING_HS 1
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#define EXT_CSD_HS_TIMING_HS200 2
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#define EXT_CSD_HS_TIMING_HS400 3
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/* EXT_CSD_BUS_WIDTH */
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#define EXT_CSD_BUS_WIDTH_1 0
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#define EXT_CSD_BUS_WIDTH_4 1
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#define EXT_CSD_BUS_WIDTH_8 2
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#define EXT_CSD_BUS_WIDTH_4_DDR 5
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#define EXT_CSD_BUS_WIDTH_8_DDR 6
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/* EXT_CSD_CARD_TYPE */
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/* The only currently valid values for this field are 0x01, 0x03, 0x07,
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* 0x0B and 0x0F. */
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#define EXT_CSD_CARD_TYPE_F_26M (1 << 0)
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#define EXT_CSD_CARD_TYPE_F_52M (1 << 1)
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#define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2)
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#define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3)
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#define EXT_CSD_CARD_TYPE_26M 0x01
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#define EXT_CSD_CARD_TYPE_52M 0x03
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#define EXT_CSD_CARD_TYPE_52M_V18 0x07
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#define EXT_CSD_CARD_TYPE_52M_V12 0x0b
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#define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f
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/* MMC_SWITCH access mode */
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#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
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#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */
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#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */
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#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
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/* MMC R2 response (CSD) */
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#define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
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#define MMC_CSD_CSDVER_1_0 1
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#define MMC_CSD_CSDVER_2_0 2
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#define MMC_CSD_CSDVER_EXT_CSD 3
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#define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
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#define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */
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#define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */
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#define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */
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#define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */
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#define MMC_CSD_MMCVER_4_0 4 /* MMC 4 */
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#define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
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#define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
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#define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
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(MMC_CSD_C_SIZE_MULT((resp))+2))
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#define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
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/* MMC v1 R2 response (CID) */
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#define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
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#define MMC_CID_PNM_V1_CPY(resp, pnm) \
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do { \
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(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
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(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
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(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
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(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
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(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
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(pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
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(pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
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(pnm)[7] = '\0'; \
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} while (0)
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#define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
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#define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
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#define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
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/* MMC v2 R2 response (CID) */
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#define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
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#define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
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#define MMC_CID_PNM_V2_CPY(resp, pnm) \
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do { \
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(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
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(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
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(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
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(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
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(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
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(pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
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(pnm)[6] = '\0'; \
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} while (0)
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#define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
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/* SD R2 response (CSD) */
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#define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
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#define SD_CSD_CSDVER_1_0 0
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#define SD_CSD_CSDVER_2_0 1
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#define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
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#define SD_CSD_TAAC_1_5_MSEC 0x26
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#define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
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#define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
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#define SD_CSD_SPEED_25_MHZ 0x32
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#define SD_CSD_SPEED_50_MHZ 0x5a
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#define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
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#define SD_CSD_CCC_BASIC (1 << 0) /* basic */
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#define SD_CSD_CCC_BR (1 << 2) /* block read */
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#define SD_CSD_CCC_BW (1 << 4) /* block write */
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#define SD_CSD_CCC_ERASE (1 << 5) /* erase */
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#define SD_CSD_CCC_WP (1 << 6) /* write protection */
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#define SD_CSD_CCC_LC (1 << 7) /* lock card */
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#define SD_CSD_CCC_AS (1 << 8) /*application specific*/
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#define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */
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#define SD_CSD_CCC_SWITCH (1 << 10) /* switch */
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#define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
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#define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
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#define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
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#define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
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#define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
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#define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
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#define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
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(SD_CSD_C_SIZE_MULT((resp))+2))
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#define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
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#define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
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#define SD_CSD_V2_BL_LEN 0x9 /* 512 */
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#define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
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#define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
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#define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
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#define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
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#define SD_CSD_VDD_RW_CURR_100mA 0x7
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#define SD_CSD_VDD_RW_CURR_80mA 0x6
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#define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
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#define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
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#define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
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#define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
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#define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
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#define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
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#define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
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#define SD_CSD_RW_BL_LEN_2G 0xa
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#define SD_CSD_RW_BL_LEN_1G 0x9
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#define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
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#define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
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#define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
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#define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
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#define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
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#define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
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/* SD R2 response (CID) */
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#define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
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#define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
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#define SD_CID_PNM_CPY(resp, pnm) \
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do { \
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(pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
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(pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
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(pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
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(pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
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(pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
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(pnm)[5] = '\0'; \
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} while (0)
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#define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
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#define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
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#define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
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/* SCR (SD Configuration Register) */
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#define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4)
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#define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */
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#define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4)
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#define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */
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#define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */
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#define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */
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#define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1)
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#define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3)
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#define SCR_SD_SECURITY_NONE 0 /* no security */
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#define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */
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#define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */
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#define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4)
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#define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */
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#define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */
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#define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1)
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#define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4)
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#define SCR_SD_SPEC4(scr) MMC_RSP_BITS((scr), 42, 1)
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#define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 8)
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#define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1)
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#define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1)
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#define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32)
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/* Status of Switch Function */
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#define SFUNC_STATUS_GROUP(status, group) \
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(__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16))
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#define SD_ACCESS_MODE_SDR12 0
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#define SD_ACCESS_MODE_SDR25 1
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#define SD_ACCESS_MODE_SDR50 2
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#define SD_ACCESS_MODE_SDR104 3
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#define SD_ACCESS_MODE_DDR50 4
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static inline uint32_t MMC_RSP_BITS(uint32_t *src, int start, int len)
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{
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uint32_t mask = (len % 32 == 0) ? UINT_MAX : UINT_MAX >> (32 - (len % 32));
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size_t word = 3 - start / 32;
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size_t shift = start % 32;
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uint32_t right = src[word] >> shift;
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uint32_t left = (len + shift <= 32) ? 0 : src[word - 1] << ((32 - shift) % 32);
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return (left | right) & mask;
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}
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#endif //_SDMMC_DEFS_H_
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165
components/driver/include/driver/sdmmc_host.h
Normal file
165
components/driver/include/driver/sdmmc_host.h
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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||||
// http://www.apache.org/licenses/LICENSE-2.0
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//
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||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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||||
#pragma once
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||||
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||||
#include <stdint.h>
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#include <stddef.h>
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#include "esp_err.h"
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||||
#include "sdmmc_types.h"
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||||
#include "driver/gpio.h"
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||||
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||||
#ifdef __cplusplus
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extern "C" {
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||||
#endif
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||||
#define SDMMC_HOST_SLOT_0 0 ///< SDMMC slot 0
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#define SDMMC_HOST_SLOT_1 1 ///< SDMMC slot 1
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||||
/**
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||||
* @brief Default sdmmc_host_t structure initializer for SDMMC peripheral
|
||||
*
|
||||
* Uses SDMMC peripheral, with 4-bit mode enabled, and max frequency set to 20MHz
|
||||
*/
|
||||
#define SDMMC_HOST_DEFAULT() {\
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||||
.flags = SDMMC_HOST_FLAG_4BIT, \
|
||||
.slot = SDMMC_HOST_SLOT_1, \
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||||
.max_freq_khz = SDMMC_FREQ_DEFAULT, \
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.io_voltage = 3.3f, \
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||||
.init = &sdmmc_host_init, \
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||||
.set_bus_width = &sdmmc_host_set_bus_width, \
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||||
.set_card_clk = &sdmmc_host_set_card_clk, \
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.do_transaction = &sdmmc_host_do_transaction, \
|
||||
.deinit = &sdmmc_host_deinit, \
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||||
}
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|
||||
/**
|
||||
* Extra configuration for SDMMC peripheral slot
|
||||
*/
|
||||
typedef struct {
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||||
gpio_num_t gpio_cd; ///< GPIO number of card detect signal
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||||
gpio_num_t gpio_wp; ///< GPIO number of write protect signal
|
||||
} sdmmc_slot_config_t;
|
||||
|
||||
#define SDMMC_SLOT_NO_CD ((gpio_num_t) -1) ///< indicates that card detect line is not used
|
||||
#define SDMMC_SLOT_NO_WP ((gpio_num_t) -1) ///< indicates that write protect line is not used
|
||||
|
||||
/**
|
||||
* Macro defining default configuration of SDMMC host slot
|
||||
*/
|
||||
#define SDMMC_SLOT_CONFIG_DEFAULT() {\
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||||
.gpio_cd = SDMMC_SLOT_NO_CD, \
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||||
.gpio_wp = SDMMC_SLOT_NO_WP, \
|
||||
}
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||||
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||||
/**
|
||||
* @brief Initialize SDMMC host peripheral
|
||||
*
|
||||
* @note This function is not thread safe
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK on success
|
||||
* - ESP_ERR_INVALID_STATE if sdmmc_host_init was already called
|
||||
* - ESP_ERR_NO_MEM if memory can not be allocated
|
||||
*/
|
||||
esp_err_t sdmmc_host_init();
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||||
|
||||
/**
|
||||
* @brief Initialize given slot of SDMMC peripheral
|
||||
*
|
||||
* On the ESP32, SDMMC peripheral has two slots:
|
||||
* - Slot 0: 8-bit wide, maps to HS1_* signals in PIN MUX
|
||||
* - Slot 1: 4-bit wide, maps to HS2_* signals in PIN MUX
|
||||
*
|
||||
* Card detect and write protect signals can be routed to
|
||||
* arbitrary GPIOs using GPIO matrix.
|
||||
*
|
||||
* @note This function is not thread safe
|
||||
*
|
||||
* @param slot slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
|
||||
* @param slot_config additional configuration for the slot
|
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* @return
|
||||
* - ESP_OK on success
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||||
* - ESP_ERR_INVALID_STATE if host has not been initialized using sdmmc_host_init
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||||
*/
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||||
esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t* slot_config);
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||||
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||||
/**
|
||||
* @brief Select bus width to be used for data transfer
|
||||
*
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||||
* SD/MMC card must be initialized prior to this command, and a command to set
|
||||
* bus width has to be sent to the card (e.g. SD_APP_SET_BUS_WIDTH)
|
||||
*
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||||
* @note This function is not thread safe
|
||||
*
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||||
* @param slot slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
|
||||
* @param width bus width (1, 4, or 8 for slot 0; 1 or 4 for slot 1)
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||||
* @return
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||||
* - ESP_OK on success
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||||
* - ESP_ERR_INVALID_ARG if slot number or width is not valid
|
||||
*/
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esp_err_t sdmmc_host_set_bus_width(int slot, size_t width);
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||||
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||||
/**
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* @brief Set card clock frequency
|
||||
*
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* Currently only integer fractions of 40MHz clock can be used.
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* For High Speed cards, 40MHz can be used.
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* For Default Speed cards, 20MHz can be used.
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*
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* @note This function is not thread safe
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*
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* @param slot slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
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* @param freq_khz card clock frequency, in kHz
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* @return
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* - ESP_OK on success
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* - other error codes may be returned in the future
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*/
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esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz);
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/**
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* @brief Send command to the card and get response
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*
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* This function returns when command is sent and response is received,
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* or data is transferred, or timeout occurs.
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*
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* @note This function is not thread safe w.r.t. init/deinit functions,
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* and bus width/clock speed configuration functions. Multiple tasks
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* can call sdmmc_host_do_transaction as long as other sdmmc_host_*
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* functions are not called.
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*
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* @param slot slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
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* @param cmdinfo pointer to structure describing command and data to transfer
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* @return
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* - ESP_OK on success
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* - ESP_ERR_TIMEOUT if response or data transfer has timed out
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* - ESP_ERR_INVALID_CRC if response or data transfer CRC check has failed
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* - ESP_ERR_INVALID_RESPONSE if the card has sent an invalid response
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*/
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esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo);
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/**
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* @brief Disable SDMMC host and release allocated resources
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*
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* @note This function is not thread safe
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*
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* @return
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* - ESP_OK on success
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||||
* - ESP_ERR_INVALID_STATE if sdmmc_host_init function has not been called
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*/
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esp_err_t sdmmc_host_deinit();
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#ifdef __cplusplus
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}
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#endif
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140
components/driver/include/driver/sdmmc_types.h
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140
components/driver/include/driver/sdmmc_types.h
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@@ -0,0 +1,140 @@
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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* Adaptations to ESP-IDF Copyright (c) 2016 Espressif Systems (Shanghai) PTE LTD
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*
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||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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||||
*/
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#ifndef _SDMMC_TYPES_H_
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#define _SDMMC_TYPES_H_
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#include <stdint.h>
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#include <stddef.h>
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#include "esp_err.h"
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/**
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* Decoded values from SD card Card Specific Data register
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*/
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typedef struct {
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int csd_ver; /*!< CSD structure format */
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int mmc_ver; /*!< MMC version (for CID format) */
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int capacity; /*!< total number of sectors */
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int sector_size; /*!< sector size in bytes */
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int read_block_len; /*!< block length for reads */
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int card_command_class; /*!< Card Command Class for SD */
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int tr_speed; /*!< Max transfer speed */
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} sdmmc_csd_t;
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/**
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* Decoded values from SD card Card IDentification register
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*/
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typedef struct {
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int mfg_id; /*!< manufacturer identification number */
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int oem_id; /*!< OEM/product identification number */
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char name[8]; /*!< product name (MMC v1 has the longest) */
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int revision; /*!< product revision */
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int serial; /*!< product serial number */
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int date; /*!< manufacturing date */
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} sdmmc_cid_t;
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/**
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* Decoded values from SD Configuration Register
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*/
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typedef struct {
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int sd_spec; /*!< SD Physical layer specification version, reported by card */
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int bus_width; /*!< bus widths supported by card: BIT(0) — 1-bit bus, BIT(2) — 4-bit bus */
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} sdmmc_scr_t;
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/**
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* SD/MMC command response buffer
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||||
*/
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typedef uint32_t sdmmc_response_t[4];
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||||
/**
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* SD/MMC command information
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*/
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typedef struct {
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||||
uint32_t opcode; /*!< SD or MMC command index */
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uint32_t arg; /*!< SD/MMC command argument */
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sdmmc_response_t response; /*!< response buffer */
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void* data; /*!< buffer to send or read into */
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||||
size_t datalen; /*!< length of data buffer */
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||||
size_t blklen; /*!< block length */
|
||||
int flags; /*!< see below */
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||||
#define SCF_ITSDONE 0x0001 /*!< command is complete */
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||||
#define SCF_CMD(flags) ((flags) & 0x00f0)
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#define SCF_CMD_AC 0x0000
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#define SCF_CMD_ADTC 0x0010
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||||
#define SCF_CMD_BC 0x0020
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||||
#define SCF_CMD_BCR 0x0030
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||||
#define SCF_CMD_READ 0x0040 /*!< read command (data expected) */
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#define SCF_RSP_BSY 0x0100
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#define SCF_RSP_136 0x0200
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#define SCF_RSP_CRC 0x0400
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||||
#define SCF_RSP_IDX 0x0800
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#define SCF_RSP_PRESENT 0x1000
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||||
/* response types */
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||||
#define SCF_RSP_R0 0 /*!< none */
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#define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
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#define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
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#define SCF_RSP_R2 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136)
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||||
#define SCF_RSP_R3 (SCF_RSP_PRESENT)
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||||
#define SCF_RSP_R4 (SCF_RSP_PRESENT)
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||||
#define SCF_RSP_R5 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
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||||
#define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
|
||||
#define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
|
||||
#define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
|
||||
esp_err_t error; /*!< error returned from transfer */
|
||||
} sdmmc_command_t;
|
||||
|
||||
/**
|
||||
* SD/MMC Host description
|
||||
*
|
||||
* This structure defines properties of SD/MMC host and functions
|
||||
* of SD/MMC host which can be used by upper layers.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t flags; /*!< flags defining host properties */
|
||||
#define SDMMC_HOST_FLAG_1BIT BIT(0) /*!< host supports 1-line SD and MMC protocol */
|
||||
#define SDMMC_HOST_FLAG_4BIT BIT(1) /*!< host supports 4-line SD and MMC protocol */
|
||||
#define SDMMC_HOST_FLAG_8BIT BIT(2) /*!< host supports 8-line MMC protocol */
|
||||
#define SDMMC_HOST_FLAG_SPI BIT(3) /*!< host supports SPI protocol */
|
||||
int slot; /*!< slot number, to be passed to host functions */
|
||||
int max_freq_khz; /*!< max frequency supported by the host */
|
||||
#define SDMMC_FREQ_DEFAULT 20000 /*!< SD/MMC Default speed (limited by clock divider) */
|
||||
#define SDMMC_FREQ_HIGHSPEED 40000 /*!< SD High speed (limited by clock divider) */
|
||||
#define SDMMC_FREQ_PROBING 4000 /*!< SD/MMC probing speed */
|
||||
float io_voltage; /*!< I/O voltage used by the controller (voltage switching is not supported) */
|
||||
esp_err_t (*init)(void); /*!< Host function to initialize the driver */
|
||||
esp_err_t (*set_bus_width)(int slot, size_t width); /*!< host function to set bus width */
|
||||
esp_err_t (*set_card_clk)(int slot, uint32_t freq_khz); /*!< host function to set card clock frequency */
|
||||
esp_err_t (*do_transaction)(int slot, sdmmc_command_t* cmdinfo); /*!< host function to do a transaction */
|
||||
esp_err_t (*deinit)(void); /*!< host function to deinitialize the driver */
|
||||
} sdmmc_host_t;
|
||||
|
||||
/**
|
||||
* SD/MMC card information structure
|
||||
*/
|
||||
typedef struct {
|
||||
sdmmc_host_t host; /*!< Host with which the card is associated */
|
||||
uint32_t ocr; /*!< OCR (Operation Conditions Register) value */
|
||||
sdmmc_cid_t cid; /*!< decoded CID (Card IDentification) register value */
|
||||
sdmmc_csd_t csd; /*!< decoded CSD (Card-Specific Data) register value */
|
||||
sdmmc_scr_t scr; /*!< decoded SCR (SD card Configuration Register) value */
|
||||
uint16_t rca; /*!< RCA (Relative Card Address) */
|
||||
} sdmmc_card_t;
|
||||
|
||||
|
||||
|
||||
|
||||
#endif // _SDMMC_TYPES_H_
|
||||
Reference in New Issue
Block a user