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feat(dsi): split the dphy config clock and pll reference clock

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this is a breaking change in the esp32p4 ver3.0 silicon.
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morris
2025-09-08 18:57:46 +08:00
parent b7fc7acb23
commit eedbd9f8e3
24 changed files with 469 additions and 235 deletions
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4
components/esp_lcd/sdkconfig.rename Normal file
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@@ -0,0 +1,4 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_LCD_DSI_ISR_IRAM_SAFE CONFIG_LCD_DSI_ISR_CACHE_SAFE