feat: enable RSA support for c5

This commit enables RSA peripheral support for ESP32-C5.
This commit is contained in:
nilesh.kale
2024-02-22 15:47:27 +05:30
parent 5e47ed70c2
commit ef3b40c5f1
4 changed files with 221 additions and 4 deletions

View File

@@ -55,6 +55,14 @@ config SOC_SYSTIMER_SUPPORTED
bool
default y
config SOC_MPI_SUPPORTED
bool
default y
config SOC_RSA_SUPPORTED
bool
default y
config SOC_ECC_SUPPORTED
bool
default y
@@ -339,6 +347,14 @@ config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_MPI_MEM_BLOCKS_NUM
int
default 4
config SOC_MPI_OPERATIONS_NUM
int
default 3
config SOC_RSA_MAX_BIT_LEN
int
default 3072

View File

@@ -46,9 +46,9 @@
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627
// #define SOC_MPI_SUPPORTED 1
#define SOC_MPI_SUPPORTED 1
// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8624
// #define SOC_RSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8620
#define SOC_RSA_SUPPORTED 1
// #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616
// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619
#define SOC_ECC_SUPPORTED 1
@@ -341,8 +341,8 @@
// #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */
/*--------------------------- MPI CAPS ---------------------------------------*/
// #define SOC_MPI_MEM_BLOCKS_NUM (4)
// #define SOC_MPI_OPERATIONS_NUM (3)
#define SOC_MPI_MEM_BLOCKS_NUM (4)
#define SOC_MPI_OPERATIONS_NUM (3)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)