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feat(driver_spi): spi master support sleep retention(recovery)

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This commit is contained in:
wanckl
2024-09-23 20:40:22 +08:00
parent 92d335548f
commit ef7406257a
41 changed files with 698 additions and 408 deletions
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4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -1023,6 +1023,10 @@ config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y

2
components/soc/esp32c5/include/soc/soc.h
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@@ -21,7 +21,7 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (DR_REG_GPSPI2_BASE) // only one GPSPI on C5
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C5
#define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C5
#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1

1
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -424,6 +424,7 @@
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define SOC_SPI_SUPPORT_SLEEP_RETENTION 1
#define SOC_SPI_SUPPORT_CLK_XTAL 1
#define SOC_SPI_SUPPORT_CLK_PLL_F160M 1
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1

2
components/soc/esp32c5/register/soc/reg_base.h
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@@ -40,7 +40,7 @@
*
*/
#define DR_REG_AHB_DMA_BASE 0x60080000
#define DR_REG_GPSPI2_BASE 0x60081000
#define DR_REG_SPI2_BASE 0x60081000
#define DR_REG_BITSCRAMBLER_BASE 0x60082000
#define DR_REG_KEYMNG_BASE 0x60087000
#define DR_REG_AES_BASE 0x60088000

67
components/soc/esp32c5/spi_periph.c
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@@ -13,29 +13,6 @@
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{
// MSPI has dedicated iomux pins
.spiclk_out = -1,
.spiclk_in = -1,
.spid_out = -1,
.spiq_out = -1,
.spiwp_out = -1,
.spihd_out = -1,
.spid_in = -1,
.spiq_in = -1,
.spiwp_in = -1,
.spihd_in = -1,
.spics_out = {-1},
.spics_in = -1,
.spiclk_iomux_pin = -1,
.spid_iomux_pin = -1,
.spiq_iomux_pin = -1,
.spiwp_iomux_pin = -1,
.spihd_iomux_pin = -1,
.spics0_iomux_pin = -1,
.irq = -1,
.irq_dma = -1,
.module = -1,
.hw = NULL,
.func = -1,
}, {
.spiclk_out = FSPICLK_OUT_IDX,
.spiclk_in = FSPICLK_IN_IDX,
@@ -57,8 +34,50 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
.spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
.irq = ETS_GPSPI2_INTR_SOURCE,
.irq_dma = -1,
.module = -1,
.hw = &GPSPI2,
.func = SPI2_FUNC_NUM,
},
};
/**
* Backup registers in Light sleep: (total cnt 12)
*
* cmd
* addr
* ctrl
* clock
* user
* user1
* user2
* ms_dlen
* misc
* dma_conf
* dma_int_ena
* slave
*/
#define SPI_RETENTION_REGS_CNT 12
static const uint32_t spi_regs_map[4] = {0x31ff, 0x1000000, 0x0, 0x0};
#define SPI_REG_RETENTION_ENTRIES(num) { \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
REG_SPI_BASE(num), REG_SPI_BASE(num), \
SPI_RETENTION_REGS_CNT, 0, 0, \
spi_regs_map[0], spi_regs_map[1], \
spi_regs_map[2], spi_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2) }, \
/* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
SPI_DMA_INT_SET_REG(num), \
SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET , \
UINT32_MAX, 1, 0), \
.owner = ENTRY(0) | ENTRY(2) }, \
}
static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2
const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi
{
.module_id = SLEEP_RETENTION_MODULE_GPSPI2,
.entry_array = spi2_regs_retention,
.array_size = ARRAY_SIZE(spi2_regs_retention),
},
};