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Merge branch 'esp32_s2_s3_cpu_freq_to_pll' into 'master'
EspS2/S3: fixed the bug of insufficient voltage when the CPU switches frequency See merge request espressif/esp-idf!25396
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@@ -84,7 +84,10 @@ extern "C" {
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
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#endif
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#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25
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#define RTC_DBIAS_240M RTC_CNTL_DBIAS_1V25
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_XTAL_80M_160M RTC_CNTL_DBIAS_1V10
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#define RTC_DBIAS_XTAL_80M_160M RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
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#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
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