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driver: Add esp32c3 ADC driver
Based on internal commit 3ef01301fffa552d4be6d81bc9d199c223224305
This commit is contained in:
Angus Gratton
@@ -34,11 +34,6 @@ extern "C" {
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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/**
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* Digital controller initialization.
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*/
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void adc_hal_digi_init(void);
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/**
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* Digital controller deinitialization.
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*/
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975
components/hal/esp32c3/include/hal/adc_ll.h
Normal file
975
components/hal/esp32c3/include/hal/adc_ll.h
Normal file
@@ -0,0 +1,975 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdbool.h>
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#include <stdlib.h>
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#include "soc/adc_periph.h"
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#include "hal/adc_types.h"
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#include "soc/apb_saradc_struct.h"
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#include "soc/apb_saradc_reg.h"
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#include "soc/rtc_cntl_struct.h"
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#include "soc/rtc_cntl_reg.h"
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#include "regi2c_ctrl.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ADC_NUM_1 = 0, /*!< SAR ADC 1 */
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ADC_NUM_2 = 1, /*!< SAR ADC 2 */
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ADC_NUM_MAX,
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} adc_ll_num_t;
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typedef enum {
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ADC_POWER_BY_FSM, /*!< ADC XPD controled by FSM. Used for polling mode */
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ADC_POWER_SW_ON, /*!< ADC XPD controled by SW. power on. Used for DMA mode */
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ADC_POWER_SW_OFF, /*!< ADC XPD controled by SW. power off. */
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ADC_POWER_MAX, /*!< For parameter check. */
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} adc_ll_power_t;
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typedef enum {
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ADC_RTC_DATA_OK = 0,
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ADC_RTC_CTRL_UNSELECTED = 1,
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ADC_RTC_CTRL_BREAK = 2,
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ADC_RTC_DATA_FAIL = -1,
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} adc_ll_rtc_raw_data_t;
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#ifdef _MSC_VER
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#pragma pack(push, 1)
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#endif /* _MSC_VER */
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/**
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* @brief Analyze whether the obtained raw data is correct.
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* ADC2 use arbiter by default. The arbitration result can be judged by the flag bit in the original data.
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*
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*/
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typedef struct {
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union {
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struct {
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uint16_t data: 13; /*!<ADC real output data info. Resolution: 13 bit. */
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uint16_t reserved: 1; /*!<reserved */
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uint16_t flag: 2; /*!<ADC data flag info.
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If (flag == 0), The data is valid.
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If (flag > 0), The data is invalid. */
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};
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uint16_t val;
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};
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} adc_ll_rtc_output_data_t;
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#ifdef _MSC_VER
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#pragma pack(pop)
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#endif /* _MSC_VER */
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/**
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* @brief ADC controller type selection.
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*
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* @note For ADC2, use the force option with care. The system power consumption detection will use ADC2.
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* If it is forced to switch to another controller, it may cause the system to obtain incorrect values.
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* @note Normally, there is no need to switch the controller manually.
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*/
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typedef enum {
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ADC_CTRL_RTC = 0, /*!<For ADC1. Select RTC controller. For ADC2. The controller is selected by the arbiter. Arbiter in default mode. */
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ADC_CTRL_DIG = 2, /*!<For ADC1. Select DIG controller. For ADC2. The controller is selected by the arbiter. Arbiter in default mode. */
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ADC2_CTRL_PWDET = 3,/*!<For ADC2. The controller is selected by the arbiter. Arbiter in default mode. */
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ADC2_CTRL_FORCE_PWDET = 3, /*!<For ADC2. Arbiter in shield mode. Force select Wi-Fi controller work. */
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ADC2_CTRL_FORCE_RTC = 4, /*!<For ADC2. Arbiter in shield mode. Force select RTC controller work. */
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ADC2_CTRL_FORCE_DIG = 6, /*!<For ADC2. Arbiter in shield mode. Force select digital controller work. */
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} adc_ll_controller_t;
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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/**
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* Set adc fsm interval parameter for digital controller. These values are fixed for same platforms.
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*
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* @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor.
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* @param start_wait Delay time after open xpd.
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* @param standby_wait Delay time to close xpd.
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*/
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static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
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{
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// Internal FSM reset wait time
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APB_SARADC.fsm_wait.rstb_wait = rst_wait;
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// Internal FSM start wait time
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APB_SARADC.fsm_wait.xpd_wait = start_wait;
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// Internal FSM standby wait time
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APB_SARADC.fsm_wait.standby_wait = standby_wait;
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}
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/**
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* Set adc sample cycle for digital controller.
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*
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* @note Normally, please use default value.
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* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
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* Range: 2 ~ 0xFF.
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*/
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static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
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{
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abort(); // TODO ESP32-C3 IDF-2094
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}
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/**
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* Set SAR ADC module clock division factor.
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* SAR ADC clock divided from digital controller clock.
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*
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* @param div Division factor.
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*/
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static inline void adc_ll_digi_set_clk_div(uint32_t div)
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{
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/* ADC clock devided from digital controller clock clk */
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APB_SARADC.ctrl.sar_clk_div = div;
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}
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/**
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* Set adc output data format for digital controller.
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*
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* @param format Output data format.
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*/
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static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format)
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{
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abort(); // TODO ESP32-C3 IDF-2094
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}
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/**
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* Set adc max conversion number for digital controller.
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* If the number of ADC conversion is equal to the maximum, the conversion is stopped.
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*
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* @param meas_num Max conversion number. Range: 0 ~ 255.
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*/
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static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
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{
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APB_SARADC.ctrl2.max_meas_num = meas_num;
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}
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/**
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* Enable max conversion number detection for digital controller.
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* If the number of ADC conversion is equal to the maximum, the conversion is stopped.
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*/
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static inline void adc_ll_digi_convert_limit_enable(void)
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{
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APB_SARADC.ctrl2.meas_num_limit = 1;
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}
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/**
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* Disable max conversion number detection for digital controller.
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* If the number of ADC conversion is equal to the maximum, the conversion is stopped.
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*/
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static inline void adc_ll_digi_convert_limit_disable(void)
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{
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APB_SARADC.ctrl2.meas_num_limit = 0;
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}
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/**
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* Set adc conversion mode for digital controller.
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*
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* @note ADC digital controller on C3 only has one pattern table list, and do conversions one by one
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*
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* @param mode Conversion mode select.
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*/
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static inline void adc_ll_digi_set_convert_mode(adc_digi_convert_mode_t mode)
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{
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abort(); // TODO ESP32-C3 IDF-2528
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}
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/**
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* Set pattern table length for digital controller.
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*
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* @param adc_n ADC unit.
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* @param patt_len Items range: 1 ~ 8.
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*/
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static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len)
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{
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/*
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* channel 可以配置为0～6， 其中 0～4 代表 ADC1 ， 5 代表 ADC2 ， 6 代表有 EN_TEST 的测试选项，可以采样内部的一些电压信号
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*/
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APB_SARADC.ctrl.sar_patt_len = patt_len - 1;
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}
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/**
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* Set pattern table for digital controller.
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*
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* @param adc_n ADC unit.
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* @param pattern_index Items index. Range: 0 ~ 15.
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* @param pattern Stored conversion rules.
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*/
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static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t pattern)
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{
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/*
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* channel 可以配置为0～6， 其中 0～4 代表 ADC1 ， 5 代表 ADC2 ， 6 代表有 EN_TEST 的测试选项，可以采样内部的一些电压信号
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*/
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uint32_t tab;
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uint8_t index = pattern_index / 4;
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uint8_t offset = (pattern_index % 4) * 6;
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tab = APB_SARADC.sar_patt_tab[index].sar_patt_tab1; // Read old register value
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tab &= (~(0xFC0000 >> offset)); // clear old data
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tab |= ((uint32_t)pattern.val << 18) >> offset; // Fill in the new data
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APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back
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}
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/**
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* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
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*
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* @param adc_n ADC unit.
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*/
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static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n)
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{
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/*
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* channel 可以配置为0～6， 其中 0～4 代表 ADC1 ， 5 代表 ADC2 ， 6 代表有 EN_TEST 的测试选项，可以采样内部的一些电压信号
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*/
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APB_SARADC.ctrl.sar_patt_p_clear = 1;
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APB_SARADC.ctrl.sar_patt_p_clear = 0;
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}
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/**
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* Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize.
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*
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* @note Only ADC2 have arbiter function.
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* @param cycle range: 0 ~ 4.
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*/
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static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
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{
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APB_SARADC.ctrl.wait_arb_cycle = cycle;
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}
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/**
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* ADC Digital controller output data invert or not.
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*
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* @param adc_n ADC unit.
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* @param inv_en data invert or not.
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*/
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static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en)
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{
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if (adc_n == ADC_NUM_1) {
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APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
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} else { // adc_n == ADC_NUM_2
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APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
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}
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}
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/**
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* Sets the number of interval clock cycles for the digital controller to trigger the measurement.
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*
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* @note The trigger interval should not be less than the sampling time of the SAR ADC.
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* @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095.
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*/
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static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
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{
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APB_SARADC.ctrl2.timer_target = cycle;
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}
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/**
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* Enable digital controller timer to trigger the measurement.
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*/
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static inline void adc_ll_digi_trigger_enable(void)
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{
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APB_SARADC.ctrl2.timer_en = 1;
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}
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/**
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* Disable digital controller timer to trigger the measurement.
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*/
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static inline void adc_ll_digi_trigger_disable(void)
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{
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APB_SARADC.ctrl2.timer_en = 0;
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}
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/**
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* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
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* Expression: controller_clk = APLL/APB * (div_num + div_b / div_a).
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*
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* @param div_num Division factor. Range: 1 ~ 255.
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* @param div_b Division factor. Range: 1 ~ 63.
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* @param div_a Division factor. Range: 1 ~ 63.
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*/
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static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
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{
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APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num;
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APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b;
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APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a;
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}
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/**
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* Enable clock and select clock source for ADC digital controller.
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*
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* @param use_apll true: use APLL clock; false: use APB clock.
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*/
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static inline void adc_ll_digi_controller_clk_enable(bool use_apll)
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{
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if (use_apll) {
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APB_SARADC.apb_adc_clkm_conf.clk_sel = 1; // APLL clock
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} else {
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APB_SARADC.apb_adc_clkm_conf.clk_sel = 2; // APB clock
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}
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APB_SARADC.ctrl.sar_clk_gated = 1;
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}
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/**
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* Disable clock for ADC digital controller.
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*/
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static inline void adc_ll_digi_controller_clk_disable(void)
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{
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APB_SARADC.ctrl.sar_clk_gated = 0;
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APB_SARADC.apb_adc_clkm_conf.clk_sel = 0;
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}
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/**
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* Reset adc digital controller filter.
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*
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* @param adc_n ADC unit.
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*/
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static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n)
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{
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APB_SARADC.filter_ctrl0.filter_reset = 1;
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}
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/**
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* Set adc digital controller filter factor.
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*
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* @param adc_n ADC unit.
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* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
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*/
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static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t factor)
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{
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adc_channel_t channel = 0;
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if (!APB_SARADC.filter_ctrl0.filter_channel0) {
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APB_SARADC.filter_ctrl0.filter_channel0 = (adc_n<<4) | channel;
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APB_SARADC.filter_ctrl1.filter_factor0 = factor;
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} else if (!APB_SARADC.filter_ctrl0.filter_channel1) {
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APB_SARADC.filter_ctrl0.filter_channel1 = (adc_n<<4) | channel;
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APB_SARADC.filter_ctrl1.filter_factor1 = factor;
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}
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}
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/**
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* Get adc digital controller filter factor.
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*
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* @param adc_n ADC unit.
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* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
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*/
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static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t *factor)
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{
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abort(); // TODO ESP32-C3 IDF-2528
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}
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/**
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* Enable/disable adc digital controller filter.
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* Filtering the ADC data to obtain smooth data at higher sampling rates.
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*
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* @note The filter will filter all the enabled channel data of the each ADC unit at the same time.
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* @param adc_n ADC unit.
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*/
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static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable)
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{
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abort(); // TODO ESP32-C3 IDF-2094
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}
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/**
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* Get the filtered data of adc digital controller filter.
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* The data after each measurement and filtering is updated to the DMA by the digital controller. But it can also be obtained manually through this API.
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*
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* @note The filter will filter all the enabled channel data of the each ADC unit at the same time.
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* @param adc_n ADC unit.
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* @return Filtered data.
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*/
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static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n)
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{
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abort(); // TODO ESP32-C3 IDF-2094
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}
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/**
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* Set monitor mode of adc digital controller.
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*
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* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
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* @param adc_n ADC unit.
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* @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt.
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* false: If ADC_OUT < threshold, Generates monitor interrupt.
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*/
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static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larger)
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{
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abort(); // TODO ESP32-C3 IDF-2094
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}
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/**
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* Set monitor threshold of adc digital controller.
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*
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* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
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* @param adc_n ADC unit.
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* @param threshold Monitor threshold.
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*/
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static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t threshold)
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{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable monitor of adc digital controller.
|
||||
*
|
||||
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
static inline void adc_ll_digi_monitor_enable(adc_ll_num_t adc_n, bool enable)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable interrupt of adc digital controller by bitmask.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param intr Interrupt bitmask.
|
||||
*/
|
||||
static inline void adc_ll_digi_intr_enable(adc_ll_num_t adc_n, adc_digi_intr_t intr)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable interrupt of adc digital controller by bitmask.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param intr Interrupt bitmask.
|
||||
*/
|
||||
static inline void adc_ll_digi_intr_disable(adc_ll_num_t adc_n, adc_digi_intr_t intr)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Clear interrupt of adc digital controller by bitmask.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param intr Interrupt bitmask.
|
||||
*/
|
||||
static inline void adc_ll_digi_intr_clear(adc_ll_num_t adc_n, adc_digi_intr_t intr)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Get interrupt status mask of adc digital controller.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @return
|
||||
* - intr Interrupt bitmask.
|
||||
*/
|
||||
static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Set DMA eof num of adc digital controller.
|
||||
* If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated.
|
||||
*
|
||||
* @param num eof num of DMA.
|
||||
*/
|
||||
static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
|
||||
{
|
||||
APB_SARADC.dma_conf.apb_adc_eof_num = num;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable output data to DMA from adc digital controller.
|
||||
*/
|
||||
static inline void adc_ll_digi_dma_enable(void)
|
||||
{
|
||||
APB_SARADC.dma_conf.apb_adc_trans = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable output data to DMA from adc digital controller.
|
||||
*/
|
||||
static inline void adc_ll_digi_dma_disable(void)
|
||||
{
|
||||
APB_SARADC.dma_conf.apb_adc_trans = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reset adc digital controller.
|
||||
*/
|
||||
static inline void adc_ll_digi_reset(void)
|
||||
{
|
||||
APB_SARADC.dma_conf.apb_adc_reset_fsm = 1;
|
||||
APB_SARADC.dma_conf.apb_adc_reset_fsm = 0;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
PWDET(Power detect) controller setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* Set adc cct for PWDET controller.
|
||||
*
|
||||
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
|
||||
* @param cct Range: 0 ~ 7.
|
||||
*/
|
||||
static inline void adc_ll_pwdet_set_cct(uint32_t cct)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Get adc cct for PWDET controller.
|
||||
*
|
||||
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
|
||||
* @return cct Range: 0 ~ 7.
|
||||
*/
|
||||
static inline uint32_t adc_ll_pwdet_get_cct(void)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
RTC controller setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* Set adc output data format for RTC controller.
|
||||
*
|
||||
* @note ESP32S2 RTC controller only support 13bit.
|
||||
* @prarm adc_n ADC unit.
|
||||
* @prarm bits Output data bits width option.
|
||||
*/
|
||||
static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable adc channel to start convert.
|
||||
*
|
||||
* @note Only one channel can be selected for once measurement.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param channel ADC channel number for each ADCn.
|
||||
*/
|
||||
static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable adc channel to start convert.
|
||||
*
|
||||
* @note Only one channel can be selected in once measurement.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param channel ADC channel number for each ADCn.
|
||||
*/
|
||||
static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n, int channel)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Start conversion once by software for RTC controller.
|
||||
*
|
||||
* @note It may be block to wait conversion idle for ADC1.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param channel ADC channel number for each ADCn.
|
||||
*/
|
||||
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Check the conversion done flag for each ADCn for RTC controller.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @return
|
||||
* -true : The conversion process is finish.
|
||||
* -false : The conversion process is not finish.
|
||||
*/
|
||||
static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the converted value for each ADCn for RTC controller.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @return
|
||||
* - Converted value.
|
||||
*/
|
||||
static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* ADC module RTC output data invert or not.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param inv_en data invert or not.
|
||||
*/
|
||||
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable ADCn conversion complete interrupt for RTC controller.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable ADCn conversion complete interrupt for RTC controller.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Reset RTC controller FSM.
|
||||
*/
|
||||
static inline void adc_ll_rtc_reset(void)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize.
|
||||
*
|
||||
* @note Only ADC2 have arbiter function.
|
||||
* @param cycle range: [0,4].
|
||||
*/
|
||||
static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Analyze whether the obtained raw data is correct.
|
||||
* ADC2 can use arbiter. The arbitration result can be judged by the flag bit in the original data.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param raw_data ADC raw data input (convert value).
|
||||
* @return
|
||||
* - 0: The data is correct to use.
|
||||
* - 1: The data is invalid. The current controller is not enabled by the arbiter.
|
||||
* - 2: The data is invalid. The current controller process was interrupted by a higher priority controller.
|
||||
* - -1: The data is error.
|
||||
*/
|
||||
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Common setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* Set ADC module power management.
|
||||
*
|
||||
* @param manage Set ADC power status.
|
||||
*/
|
||||
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
|
||||
{
|
||||
// /* Bit1 0:Fsm 1: SW mode
|
||||
// Bit0 0:SW mode power down 1: SW mode power on */
|
||||
if (manage == ADC_POWER_SW_ON) {
|
||||
APB_SARADC.ctrl.sar_clk_gated = 1;
|
||||
APB_SARADC.ctrl.xpd_sar_force = SENS_FORCE_XPD_SAR_PU;
|
||||
} else if (manage == ADC_POWER_BY_FSM) {
|
||||
APB_SARADC.ctrl.sar_clk_gated = 1;
|
||||
APB_SARADC.ctrl.xpd_sar_force = SENS_FORCE_XPD_SAR_FSM;
|
||||
} else if (manage == ADC_POWER_SW_OFF) {
|
||||
APB_SARADC.ctrl.xpd_sar_force = SENS_FORCE_XPD_SAR_PD;
|
||||
APB_SARADC.ctrl.sar_clk_gated = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Get ADC module power management.
|
||||
*
|
||||
* @return
|
||||
* - ADC power status.
|
||||
*/
|
||||
static inline adc_ll_power_t adc_ll_get_power_manage(void)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* ADC SAR clock division factor setting. ADC SAR clock devided from `RTC_FAST_CLK`.
|
||||
*
|
||||
* @param div Division factor.
|
||||
*/
|
||||
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the attenuation of a particular channel on ADCn.
|
||||
*
|
||||
* @note For any given channel, this function must be called before the first time conversion.
|
||||
*
|
||||
* The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,
|
||||
* usually 3.3V) requires setting >0dB signal attenuation for that ADC channel.
|
||||
*
|
||||
* When VDD_A is 3.3V:
|
||||
*
|
||||
* - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V
|
||||
* - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V
|
||||
* - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V
|
||||
* - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below)
|
||||
*
|
||||
* @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured
|
||||
* bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.)
|
||||
*
|
||||
* @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
|
||||
*
|
||||
* Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges:
|
||||
*
|
||||
* - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV
|
||||
* - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV
|
||||
* - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV
|
||||
* - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV
|
||||
*
|
||||
* For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param channel ADCn channel number.
|
||||
* @param atten The attenuation option.
|
||||
*/
|
||||
static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the attenuation of a particular channel on ADCn.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param channel ADCn channel number.
|
||||
* @return atten The attenuation option.
|
||||
*/
|
||||
static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Set ADC module controller.
|
||||
* There are five SAR ADC controllers:
|
||||
* Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes;
|
||||
* Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep;
|
||||
* the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param ctrl ADC controller.
|
||||
*/
|
||||
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Set ADC2 module arbiter work mode.
|
||||
* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
|
||||
* the low priority controller will read the invalid ADC data, and the validity of the data can be judged by the flag bit in the data.
|
||||
*
|
||||
* @note Only ADC2 support arbiter.
|
||||
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
|
||||
*
|
||||
* @param mode Refer to `adc_arbiter_mode_t`.
|
||||
*/
|
||||
static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode)
|
||||
{
|
||||
SENS.sar_meas2_mux.sar2_rtc_force = 0; // Enable arbiter in wakeup mode
|
||||
if (mode == ADC_ARB_MODE_FIX) {
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 1;
|
||||
} else if (mode == ADC_ARB_MODE_LOOP) {
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 0;
|
||||
} else {
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 1; // Shield arbiter.
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set ADC2 module controller priority in arbiter.
|
||||
* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
|
||||
* the low priority controller will read the invalid ADC data, and the validity of the data can be judged by the flag bit in the data.
|
||||
*
|
||||
* @note Only ADC2 support arbiter.
|
||||
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
|
||||
* @note Default priority: Wi-Fi(2) > RTC(1) > Digital(0);
|
||||
*
|
||||
* @param pri_rtc RTC controller priority. Range: 0 ~ 2.
|
||||
* @param pri_dig Digital controller priority. Range: 0 ~ 2.
|
||||
* @param pri_pwdet Wi-Fi controller priority. Range: 0 ~ 2.
|
||||
*/
|
||||
static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig, uint8_t pri_pwdet)
|
||||
{
|
||||
if (pri_rtc != pri_dig && pri_rtc != pri_pwdet && pri_dig != pri_pwdet) {
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_priority = pri_rtc;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_priority = pri_dig;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_priority = pri_pwdet;
|
||||
}
|
||||
/* Should select highest priority controller. */
|
||||
if (pri_rtc > pri_dig) {
|
||||
if (pri_rtc > pri_pwdet) {
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 1;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0;
|
||||
} else {
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1;
|
||||
}
|
||||
} else {
|
||||
if (pri_dig > pri_pwdet) {
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 1;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0;
|
||||
} else {
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
|
||||
APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Force switch ADC2 to RTC controller in sleep mode. Shield arbiter.
|
||||
* In sleep mode, the arbiter is in power-down mode.
|
||||
* Need to switch the controller to RTC to shield the control of the arbiter.
|
||||
* After waking up, it needs to switch to arbiter control.
|
||||
*
|
||||
* @note The hardware will do this automatically. In normal use, there is no need to call this interface to manually switch the controller.
|
||||
* @note Only support ADC2.
|
||||
*/
|
||||
static inline void adc_ll_enable_sleep_controller(void)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/**
|
||||
* Force switch ADC2 to arbiter in wakeup mode.
|
||||
* In sleep mode, the arbiter is in power-down mode.
|
||||
* Need to switch the controller to RTC to shield the control of the arbiter.
|
||||
* After waking up, it needs to switch to arbiter control.
|
||||
*
|
||||
* @note The hardware will do this automatically. In normal use, there is no need to call this interface to manually switch the controller.
|
||||
* @note Only support ADC2.
|
||||
*/
|
||||
static inline void adc_ll_disable_sleep_controller(void)
|
||||
{
|
||||
abort(); // TODO ESP32-C3 IDF-2094
|
||||
}
|
||||
|
||||
/* ADC calibration code. */
|
||||
#define ADC_HAL_CAL_OFFSET_RANGE (4096)
|
||||
#define ADC_HAL_CAL_TIMES (10)
|
||||
|
||||
/**
|
||||
* Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration.
|
||||
*
|
||||
* @note Different ADC units and different attenuation options use different calibration data (initial data).
|
||||
*
|
||||
* @param adc_n ADC index number.
|
||||
* @param channel adc channel number.
|
||||
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
|
||||
* false: Use IO external voltage as calibration voltage.
|
||||
*/
|
||||
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd)
|
||||
{
|
||||
// /* Enable i2s_write_reg function. */
|
||||
// void phy_get_romfunc_addr(void);
|
||||
// phy_get_romfunc_addr();
|
||||
// //CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
|
||||
// //SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
// CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
// SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
// /* Enable/disable internal connect GND (for calibration). */
|
||||
// if (adc_n == ADC_NUM_1) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_DREF_ADDR, 4);
|
||||
// if (internal_gnd) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 1);
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0);
|
||||
// }
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_DREF_ADDR, 4);
|
||||
// if (internal_gnd) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 1);
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0);
|
||||
// }
|
||||
// }
|
||||
}
|
||||
|
||||
/**
|
||||
* Resume register status after calibration.
|
||||
*
|
||||
* @param adc_n ADC index number.
|
||||
*/
|
||||
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
|
||||
{
|
||||
// if (adc_n == ADC_NUM_1) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0);
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0);
|
||||
// }
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the calibration result to ADC.
|
||||
*
|
||||
* @note Different ADC units and different attenuation options use different calibration data (initial data).
|
||||
*
|
||||
* @param adc_n ADC index number.
|
||||
*/
|
||||
static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param)
|
||||
{
|
||||
// uint8_t msb = param >> 8;
|
||||
// uint8_t lsb = param & 0xFF;
|
||||
// /* Enable i2s_write_reg function. */
|
||||
// void phy_get_romfunc_addr(void);
|
||||
// phy_get_romfunc_addr();
|
||||
// //SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
// CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
// SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
// if (adc_n == ADC_NUM_1) {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR1_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
// } else {
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_INITIAL_CODE_HIGH_ADDR, msb);
|
||||
// REGI2C_WRITE_MASK(I2C_ADC, SAR2_INITIAL_CODE_LOW_ADDR, lsb);
|
||||
// }
|
||||
}
|
||||
/* Temp code end. */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user