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docs(misc): fixed typos found with codespell

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This commit is contained in:
Marius Vikhammer
2024-03-28 11:50:58 +08:00
parent 1c73c657c9
commit f1e65b8373
57 changed files with 91 additions and 91 deletions
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8
docs/en/api-reference/system/efuse.rst
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@@ -45,7 +45,7 @@ For more details, see **{IDF_TARGET_NAME} Technical Reference Manual** > **eFuse
:SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK and SOC_ECDSA_SUPPORTED: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used for any purpose except for flash encryption or ECDSA (due to a HW bug);
:SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK and not SOC_ECDSA_SUPPORTED: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used for any purpose except for flash encryption (due to a HW bug);
:not SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK: * EFUSE_BLK9 (also named EFUSE_BLK_KEY5) can be used as key (for secure_boot or flash_encryption) or for user purposes;
* EFUSE_BLK10 (also named EFUSE_BLK_SYS_DATA_PART2) is reseved for system purposes.
* EFUSE_BLK10 (also named EFUSE_BLK_SYS_DATA_PART2) is reserved for system purposes.
.. only:: esp32c2
@@ -163,9 +163,9 @@ Solution: Describe ``SERIAL_NUMBER`` to be included in ``USER_DATA``. (``USER_DA
.. code-block:: none
Field at FEILD, EFUSE_BLK3, 0, 50 out of range FEILD.MAJOR_NUMBER, EFUSE_BLK3, 60, 32
Field at FIELD, EFUSE_BLK3, 0, 50 out of range FIELD.MAJOR_NUMBER, EFUSE_BLK3, 60, 32
Solution: Change ``bit_start`` for ``FIELD.MAJOR_NUMBER`` from 60 to 0, so ``MAJOR_NUMBER`` is in the ``FEILD`` range.
Solution: Change ``bit_start`` for ``FIELD.MAJOR_NUMBER`` from 60 to 0, so ``MAJOR_NUMBER`` is in the ``FIELD`` range.
``efuse_table_gen.py`` Tool
---------------------------
@@ -216,7 +216,7 @@ Supported Coding Scheme
* ``Repeat`` (value 2).
The coding scheme affects only EFUSE_BLK1, EFUSE_BLK2 and EFUSE_BLK3 blocks. EUSE_BLK0 block always has a coding scheme ``None``.
Coding changes the number of bits that can be written into a block, the block length is constant 256, some of these bits are used for encoding and not avaliable for the user.
Coding changes the number of bits that can be written into a block, the block length is constant 256, some of these bits are used for encoding and not available for the user.
When using a coding scheme, the length of the payload that can be written is limited (for more details ``20.3.1.3 System Parameter coding_scheme``):

4
docs/en/api-reference/system/inc/espefuse_summary_ESP32-C6.rst
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@@ -77,7 +77,7 @@
e_download is disabled or enabled. 1: disabled. 0:
enabled
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0)
led or enabled(except in SPI boot mode). 1: disabl
led or enabled(except in SPI boot mode). 1: disable
ed. 0: enabled
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000)
and disables otherwise
@@ -105,7 +105,7 @@
SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000)
ck feature
SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0)
or enabled when Secure Boot is enabled. 1: disabl
or enabled when Secure Boot is enabled. 1: disable
ed. 0: enabled
BLOCK_KEY0 (BLOCK4)
Purpose: USER

4
docs/en/api-reference/system/inc/espefuse_summary_ESP32-H2.rst
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@@ -76,7 +76,7 @@
e_download is disabled or enabled. 1: disabled. 0:
enabled
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0)
led or enabled(except in SPI boot mode). 1: disabl
led or enabled(except in SPI boot mode). 1: disable
ed. 0: enabled
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000)
and disables otherwise
@@ -107,7 +107,7 @@
SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000)
ck feature
SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0)
or enabled when Secure Boot is enabled. 1: disabl
or enabled when Secure Boot is enabled. 1: disable
ed. 0: enabled
BLOCK_KEY0 (BLOCK4)
Purpose: USER

6
docs/en/api-reference/system/inc/espefuse_summary_ESP32-P4.rst
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@@ -31,7 +31,7 @@
eset at low level. 10: enable printing when GPIO8
is reset at high level. 11: force disable printing
HYS_EN_PAD (BLOCK0) Represents whether the hysteresis function of corr = False R/W (0b0)
esponding PAD is enabled. 1: enabled. 0:disabled
corresponding PAD is enabled. 1: enabled. 0:disabled
DCDC_VSET (BLOCK0) Set the dcdc voltage default = 0 R/W (0b00000)
PXA0_TIEH_SEL_0 (BLOCK0) TBD = 0 R/W (0b00)
PXA0_TIEH_SEL_1 (BLOCK0) TBD = 0 R/W (0b00)
@@ -100,7 +100,7 @@
SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Set this bit to disable accessing MSPI flash/MSPI = False R/W (0b0)
ram by SYS AXI matrix during boot_mode_download
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0)
led or enabled(except in SPI boot mode). 1: disabl
led or enabled(except in SPI boot mode). 1: disable
ed. 0: enabled
FORCE_USE_KEY_MANAGER_KEY (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0x0)
must come from key manager.. 1 is true; 0 is false
@@ -139,7 +139,7 @@
SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000)
ck feature
SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0)
or enabled when Secure Boot is enabled. 1: disabl
or enabled when Secure Boot is enabled. 1: disable
ed. 0: enabled
BLOCK_KEY0 (BLOCK4)
Purpose: USER

2
docs/en/api-reference/system/mm.rst
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@@ -48,7 +48,7 @@ Virtual Memory Capabilities
.. only:: esp32s2
4 MB external memory addresses (from 0x40400000 to 0x40800000) which have the :cpp:enumerator:`MMU_MEM_CAP_EXEC` and :cpp:enumerator:`MMU_MEM_CAP_READ` capabilities are not avaiable for users to allocate, due to hardware limitations.
4 MB external memory addresses (from 0x40400000 to 0x40800000) which have the :cpp:enumerator:`MMU_MEM_CAP_EXEC` and :cpp:enumerator:`MMU_MEM_CAP_READ` capabilities are not available for users to allocate, due to hardware limitations.
You can call :cpp:func:`esp_mmu_map_get_max_consecutive_free_block_size` to know the largest consecutive mappable block size with certain capabilities.

2
docs/en/api-reference/system/ota.rst
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@@ -239,7 +239,7 @@ The created object can now be used to perform operations on the target device:
.. code-block:: python
# Erase otadata, reseting the device to factory app
# Erase otadata, resetting the device to factory app
target.erase_otadata()
# Erase contents of OTA app slot 0

2
docs/en/api-reference/system/power_management.rst
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@@ -98,7 +98,7 @@ Dynamic Frequency Scaling and Peripheral Drivers
When DFS is enabled, the APB frequency can be changed multiple times within a single RTOS tick. The APB frequency change does not affect the operation of some peripherals, while other peripherals may have issues. For example, Timer Group peripheral timers keeps counting, however, the speed at which they count changes proportionally to the APB frequency.
Peripheral clock sources such as ``REF_TICK``, ``XTAL``, ``RC_FAST`` (i.e., ``RTC_8M``), their frequencies will not be inflenced by APB frequency. And therefore, to ensure the peripheral behaves consistently during DFS, it is recommanded to select one of these clocks as the peripheral clock source. For more specific guidelines, please refer to the "Power Management" section of each peripheral's "API Reference > Peripherals API" page.
Peripheral clock sources such as ``REF_TICK``, ``XTAL``, ``RC_FAST`` (i.e., ``RTC_8M``), their frequencies will not be inflenced by APB frequency. And therefore, to ensure the peripheral behaves consistently during DFS, it is recommended to select one of these clocks as the peripheral clock source. For more specific guidelines, please refer to the "Power Management" section of each peripheral's "API Reference > Peripherals API" page.
Currently, the following peripheral drivers are aware of DFS and use the ``ESP_PM_APB_FREQ_MAX`` lock for the duration of the transaction:

2
docs/en/api-reference/system/ulp-lp-core.rst
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@@ -16,7 +16,7 @@ The ULP LP-Core coprocessor has the following features:
Compiling Code for the ULP LP-Core
----------------------------------
The ULP LP-Core code is compiled together with your ESP-IDF project as a separate binary and automatically embedded into the main project binary. To acheive this do the following:
The ULP LP-Core code is compiled together with your ESP-IDF project as a separate binary and automatically embedded into the main project binary. To achieve this do the following:
1. Place the ULP LP-Core code, written in C or assembly (with the ``.S`` extension), in a dedicated directory within the component directory, such as ``ulp/``.

2
docs/en/api-reference/system/ulp_macros.rst
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@@ -29,7 +29,7 @@ The ``program`` array is an array of ``ulp_insn_t``, i.e., ULP coprocessor instr
To generate branch instructions, special ``M_`` preprocessor defines are used. ``M_LABEL`` define can be used to define a branch target. Label identifier is a 16-bit integer. ``M_Bxxx`` defines can be used to generate branch instructions with target set to a particular label.
Implementation note: these ``M_`` preprocessor defines will be translated into two ulp_insn_t values: one is a token value which contains label number, and the other is the actual instruction. ``ulp_process_macros_and_load`` function resolves the label number to the address, modifies the branch instruction to use the correct address, and removes the extra ``ulp_insn_t`` token which contains the label numer.
Implementation note: these ``M_`` preprocessor defines will be translated into two ulp_insn_t values: one is a token value which contains label number, and the other is the actual instruction. ``ulp_process_macros_and_load`` function resolves the label number to the address, modifies the branch instruction to use the correct address, and removes the extra ``ulp_insn_t`` token which contains the label number.
Here is an example of using labels and branches::

2
docs/en/api-reference/system/wdts.rst
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@@ -172,7 +172,7 @@ The following config options control TWDT configuration. They are all enabled by
JTAG & Watchdogs
----------------
While debugging using OpenOCD, the CPUs are halted every time a breakpoint is reached. However if the watchdog timers continue to run when a breakpoint is encountered, they will eventually trigger a reset making it very difficult to debug code. Therefore OpenOCD will disable the hardware timers of both the interrupt and task watchdogs at every breakpoint. Moreover, OpenOCD will not reenable them upon leaving the breakpoint. This means that interrupt watchdog and task watchdog functionality will essentially be disabled. No warnings or panics from either watchdogs will be generated when the {IDF_TARGET_NAME} is connected to OpenOCD via JTAG.
While debugging using OpenOCD, the CPUs are halted every time a breakpoint is reached. However if the watchdog timers continue to run when a breakpoint is encountered, they will eventually trigger a reset making it very difficult to debug code. Therefore OpenOCD will disable the hardware timers of both the interrupt and task watchdogs at every breakpoint. Moreover, OpenOCD will not re-enable them upon leaving the breakpoint. This means that interrupt watchdog and task watchdog functionality will essentially be disabled. No warnings or panics from either watchdogs will be generated when the {IDF_TARGET_NAME} is connected to OpenOCD via JTAG.
API Reference