diff --git a/docs/en/api-guides/memory-types.rst b/docs/en/api-guides/memory-types.rst index ed69d7c6f0..87455bea14 100644 --- a/docs/en/api-guides/memory-types.rst +++ b/docs/en/api-guides/memory-types.rst @@ -189,10 +189,10 @@ The ``DRAM_ATTR`` attribute can be used to force constants from DROM into the :r .. only:: SOC_MEM_TCM_SUPPORTED - TCM (Tightly-Coupled Memory) + SPM (Scratchpad Memory) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - TCM is memory placed near the CPU, accessible at CPU frequency without passing through a cache. Even though on average, it may not surpass the efficiency or speed of cached memory, it does provide predictable and consistent access times. TCM can be useful for time-critical routines where having a deterministic access speed is important. + SPM (Scratchpad Memory) is a dedicated on-chip memory located near the processor core, offering deterministic access timing. SPM does not rely on hardware caching mechanisms; instead, its access is explicitly managed by software, ensuring predictable and stable latency. The access latency of SPM is configuration dependent. When parity check is enabled, the latency is 4 clock cycles and memory bandwidth is reduced. When parity check is disabled, the latency is 1 clock cycle. This type of memory is typically used to store critical code and data that are sensitive to access timing, making it suitable for real-time systems or embedded applications with strict performance and response time requirements. DMA-Capable Requirement diff --git a/docs/zh_CN/api-guides/memory-types.rst b/docs/zh_CN/api-guides/memory-types.rst index 4f17cbad86..fcb5e8b1c5 100644 --- a/docs/zh_CN/api-guides/memory-types.rst +++ b/docs/zh_CN/api-guides/memory-types.rst @@ -189,10 +189,10 @@ DROM(数据存储在 flash 中) .. only:: SOC_MEM_TCM_SUPPORTED - 紧密耦合内存 (TCM) + SPM(暂存内存) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - TCM 是靠近 CPU 放置的内存,支持在 CPU 频率下直接访问,无需通过 cache。虽然在一般情况下,TCM 的效率或速度相较 cache 偏低,但是访问 TCM 所需的时间是可以预测且始终一致的。具有稳定的访问速度对于时间关键型例程来说十分重要,因此 TCM 对于此类例程而言非常有用。 + SPM (Scratchpad Memory) 是一种位于处理器核心附近的片上专用存储器,具备确定性的访问时序。SPM 不依赖硬件缓存机制,访问由软件显式管理,访问延迟可预测且稳定。具体访问延迟可能受硬件配置影响:启用奇偶校验功能时,访问延迟为 4 个时钟周期,带宽也会相应下降;关闭奇偶校验后,访问延迟可低至 1 个时钟周期。该内存通常用于存放对访问时序敏感的关键代码和数据,适用于对性能和响应时间要求严格的实时系统或嵌入式应用。 具备 DMA 功能