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feat(parlio): support parlio on C5

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This commit is contained in:
laokaiyao
2024-06-19 17:15:36 +08:00
parent 55d2c23e0b
commit f301db44b8
10 changed files with 804 additions and 18 deletions
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44
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -27,6 +27,10 @@ config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_PARLIO_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@@ -575,6 +579,46 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_PARLIO_GROUPS
int
default 1
config SOC_PARLIO_TX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_RX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
int
default 8
config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
int
default 8
config SOC_PARLIO_TX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
bool
default y
config SOC_PARLIO_TRANS_BIT_ALIGN
bool
default y
config SOC_PARLIO_TX_SIZE_BY_DMA
bool
default y
config SOC_MPI_MEM_BLOCKS_NUM
int
default 4

14
components/soc/esp32c5/include/soc/clk_tree_defs.h
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@@ -520,10 +520,16 @@ typedef enum {
/**
* @brief PARLIO clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6)
PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
typedef enum {
PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */
#if SOC_CLK_TREE_SUPPORTED // TODO: [ESP32C5] IDF-8642 remove when clock tree is supported
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
#else
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_parlio_clk_src_t;
//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////

2
components/soc/esp32c5/include/soc/parl_io_struct.h
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@@ -468,7 +468,7 @@ typedef union {
} parl_io_version_reg_t;
typedef struct {
typedef struct parl_io_dev_t {
volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;

18
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -27,7 +27,7 @@
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686
#define SOC_PARLIO_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727
@@ -342,12 +342,16 @@
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
// #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */
#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */
/*--------------------------- MPI CAPS ---------------------------------------*/
#define SOC_MPI_MEM_BLOCKS_NUM (4)

50
components/soc/esp32c5/parlio_periph.c Normal file
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@@ -0,0 +1,50 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/parlio_periph.h"
#include "soc/gpio_sig_map.h"
const parlio_signal_conn_t parlio_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_PARLIO_MODULE,
.tx_irq_id = ETS_PARL_IO_TX_INTR_SOURCE,
.rx_irq_id = ETS_PARL_IO_RX_INTR_SOURCE,
.tx_units = {
[0] = {
.data_sigs = {
PARL_TX_DATA0_IDX,
PARL_TX_DATA1_IDX,
PARL_TX_DATA2_IDX,
PARL_TX_DATA3_IDX,
PARL_TX_DATA4_IDX,
PARL_TX_DATA5_IDX,
PARL_TX_DATA6_IDX,
PARL_TX_DATA7_IDX,
},
.clk_out_sig = PARL_TX_CLK_OUT_IDX,
.clk_in_sig = PARL_TX_CLK_IN_IDX,
}
},
.rx_units = {
[0] = {
.data_sigs = {
PARL_RX_DATA0_IDX,
PARL_RX_DATA1_IDX,
PARL_RX_DATA2_IDX,
PARL_RX_DATA3_IDX,
PARL_RX_DATA4_IDX,
PARL_RX_DATA5_IDX,
PARL_RX_DATA6_IDX,
PARL_RX_DATA7_IDX,
},
.clk_out_sig = PARL_RX_CLK_OUT_IDX,
.clk_in_sig = PARL_RX_CLK_IN_IDX,
}
}
},
},
};