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Merge branch 'refactor/mspi_soc_c5_c61' into 'master'

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fix(mspi): Refactor mspi ll/soc for c5 and c61

Closes IDF-5157

See merge request espressif/esp-idf!32151
This commit is contained in:
C.S.M
2024-08-16 10:34:21 +08:00
parent f6ec756b8e bc80476411
commit f40380c472
34 changed files with 13196 additions and 10355 deletions
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47
components/hal/esp32c5/include/hal/psram_ctrlr_ll.h
View File

@@ -18,7 +18,6 @@
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/spi_mem_struct.h"
#include "soc/spi1_mem_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/clk_tree_defs.h"
#include "rom/opi_flash.h"
@@ -53,9 +52,9 @@ static inline void psram_ctrlr_ll_set_wr_cmd(uint32_t mspi_id, uint32_t cmd_bitl
{
(void)mspi_id;
HAL_ASSERT(cmd_bitlen > 0);
SPIMEM0.cache_sctrl.sram_usr_wcmd = 1;
SPIMEM0.sram_dwr_cmd.sram_usr_wr_cmd_bitlen = cmd_bitlen - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_dwr_cmd, sram_usr_wr_cmd_value, cmd_val);
SPIMEM0.mem_cache_sctrl.mem_cache_sram_usr_wcmd = 1;
SPIMEM0.mem_sram_dwr_cmd.mem_cache_sram_usr_wr_cmd_bitlen = cmd_bitlen - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.mem_sram_dwr_cmd, mem_cache_sram_usr_wr_cmd_value, cmd_val);
}
/**
@@ -70,9 +69,9 @@ static inline void psram_ctrlr_ll_set_rd_cmd(uint32_t mspi_id, uint32_t cmd_bitl
{
(void)mspi_id;
HAL_ASSERT(cmd_bitlen > 0);
SPIMEM0.cache_sctrl.sram_usr_rcmd = 1;
SPIMEM0.sram_drd_cmd.sram_usr_rd_cmd_bitlen = cmd_bitlen - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_drd_cmd, sram_usr_rd_cmd_value, cmd_val);
SPIMEM0.mem_cache_sctrl.mem_cache_sram_usr_rcmd = 1;
SPIMEM0.mem_sram_drd_cmd.mem_cache_sram_usr_rd_cmd_bitlen = cmd_bitlen - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.mem_sram_drd_cmd, mem_cache_sram_usr_rd_cmd_value, cmd_val);
}
/**
@@ -86,7 +85,7 @@ static inline void psram_ctrlr_ll_set_addr_bitlen(uint32_t mspi_id, uint32_t add
{
(void)mspi_id;
HAL_ASSERT(addr_bitlen > 0);
SPIMEM0.cache_sctrl.sram_addr_bitlen = addr_bitlen - 1;
SPIMEM0.mem_cache_sctrl.mem_sram_addr_bitlen = addr_bitlen - 1;
}
/**
@@ -100,8 +99,8 @@ static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_
{
(void)mspi_id;
HAL_ASSERT(dummy_n > 0);
SPIMEM0.cache_sctrl.usr_rd_sram_dummy = 1;
SPIMEM0.cache_sctrl.sram_rdummy_cyclelen = dummy_n - 1;
SPIMEM0.mem_cache_sctrl.mem_usr_rd_sram_dummy = 1;
SPIMEM0.mem_cache_sctrl.mem_sram_rdummy_cyclelen = dummy_n - 1;
}
/**
@@ -113,7 +112,7 @@ static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_bus_clock(uint32_t mspi_id, uint32_t clock_conf)
{
SPIMEM0.sram_clk.val = clock_conf;
SPIMEM0.mem_sram_clk.val = clock_conf;
}
/**
@@ -143,21 +142,21 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode)
{
typeof (SPIMEM0.cache_sctrl) cache_sctrl;
cache_sctrl.val = SPIMEM0.cache_sctrl.val;
typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val;
cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
mem_cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
switch (read_mode) {
case PSRAM_HAL_CMD_SPI:
cache_sctrl.usr_sram_dio = 1;
mem_cache_sctrl.mem_usr_sram_dio = 1;
break;
case PSRAM_HAL_CMD_QPI:
cache_sctrl.usr_sram_qio = 1;
mem_cache_sctrl.mem_usr_sram_qio = 1;
break;
default:
abort();
}
SPIMEM0.cache_sctrl.val = cache_sctrl.val;
SPIMEM0.mem_cache_sctrl.val = mem_cache_sctrl.val;
}
/**
@@ -171,8 +170,8 @@ static inline void psram_ctrlr_ll_set_cs_setup(uint32_t mspi_id, uint32_t setup_
{
(void)mspi_id;
HAL_ASSERT(setup_n > 0);
SPIMEM0.spi_smem_ac.reg_smem_cs_setup = 1;
SPIMEM0.spi_smem_ac.reg_smem_cs_setup_time = setup_n - 1;
SPIMEM0.smem_ac.smem_cs_setup = 1;
SPIMEM0.smem_ac.smem_cs_setup_time = setup_n - 1;
}
/**
@@ -186,8 +185,8 @@ static inline void psram_ctrlr_ll_set_cs_hold(uint32_t mspi_id, uint32_t hold_n)
{
(void)mspi_id;
HAL_ASSERT(hold_n > 0);
SPIMEM0.spi_smem_ac.reg_smem_cs_hold = 1;
SPIMEM0.spi_smem_ac.reg_smem_cs_hold_time = hold_n - 1;
SPIMEM0.smem_ac.smem_cs_hold = 1;
SPIMEM0.smem_ac.smem_cs_hold_time = hold_n - 1;
}
/**
@@ -201,7 +200,7 @@ static inline void psram_ctrlr_ll_set_cs_hold_delay(uint32_t mspi_id, uint32_t h
{
(void)mspi_id;
HAL_ASSERT(hold_delay_n > 0);
SPIMEM0.spi_smem_ac.reg_smem_cs_hold_delay = hold_delay_n - 1;
SPIMEM0.smem_ac.smem_cs_hold_delay = hold_delay_n - 1;
}
/**
@@ -243,8 +242,8 @@ static inline void psram_ctrlr_ll_common_transaction_base(uint32_t mspi_id, esp_
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_cs_pin(uint32_t mspi_id, psram_ll_cs_id_t cs_id)
{
SPIMEM0.misc.cs0_dis = (cs_id == 0) ? 0 : 1;
SPIMEM0.misc.cs1_dis = (cs_id == 1) ? 0 : 1;
SPIMEM1.misc.cs0_dis = (cs_id == 0) ? 0 : 1;
SPIMEM1.misc.cs1_dis = (cs_id == 1) ? 0 : 1;
}
/**

7
components/hal/esp32c5/include/hal/spi_flash_ll.h
View File

@@ -45,6 +45,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@@ -95,6 +98,10 @@ typedef union {
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

89
components/hal/esp32c5/include/hal/spimem_flash_ll.h
View File

@@ -18,7 +18,6 @@
#include <sys/param.h> // For MIN/MAX
#include <stdbool.h>
#include <string.h>
#include "sdkconfig.h" // TODO: remove
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
@@ -212,7 +211,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
*/
static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
{
dev->flash_sus_ctrl.frd_sus_2b = 0;
dev->flash_sus_ctrl.fmem_rd_sus_2b = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
}
@@ -237,7 +236,7 @@ static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dl
*/
static inline void spimem_flash_set_cs_hold_delay(spi_mem_dev_t *dev, uint32_t cs_hold_delay)
{
SPIMEM0.ctrl2.cs_hold_delay = cs_hold_delay;
SPIMEM0.ctrl2.mem_cs_hold_delay = cs_hold_delay;
}
/**
@@ -256,14 +255,19 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool
/**
* This function is used to set dummy phase when auto suspend is enabled.
*
* @note This function is only used when timing tuning is enabled.
* @note This function is only used when timing tuning is enabled. This function is only used in quad flash
*
* @param dev Beginning address of the peripheral registers.
* @param extra_dummy extra dummy length. Get from timing tuning.
*/
static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy)
{
// Not supported on this chip.
if (extra_dummy > 0) {
dev->flash_waiti_ctrl.waiti_dummy_cyclelen = extra_dummy - 1;
dev->flash_waiti_ctrl.waiti_dummy = 1;
} else {
dev->flash_waiti_ctrl.waiti_dummy = 0;
}
}
/**
@@ -287,7 +291,7 @@ static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
static inline void spimem_flash_ll_sus_set_spi0_lock_trans(spi_mem_dev_t *dev, uint32_t lock_time)
{
dev->sus_status.spi0_lock_en = 1;
SPIMEM0.fsm.lock_delay_time = lock_time;
SPIMEM0.mem_fsm.mem_lock_delay_time = lock_time;
}
/**
@@ -329,6 +333,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@@ -354,6 +359,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@@ -507,6 +513,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@@ -547,6 +554,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@@ -561,8 +569,8 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
*/
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.usr_addr_4byte = 0;
dev->rd_status.wb_mode = extra_addr;
dev->cache_fctrl.cache_usr_addr_4byte = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr);
}
/**
@@ -582,6 +590,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@@ -608,14 +617,23 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
*/
static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
{
dev->ctrl2.cs_hold_time = hold_n - 1;
dev->user.cs_hold = (hold_n > 0? 1: 0);
// Not supported on esp32c5
}
/**
* Set CS setup time
*
* @param dev Beginning address of the peripheral registers.
* @param cs_setup_time CS setup time
*/
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
{
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
dev->ctrl2.cs_setup_time = cs_setup_time - 1;
// Not supported on esp32c5
}
static inline void spimem_flash_ll_set_extra_dummy(spi_mem_dev_t *dev, uint32_t extra_dummy)
{
//for compatibility
}
/**
@@ -675,7 +693,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
dev->ctrl.wp_reg = level;
}
/**
@@ -688,6 +706,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif