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refactor the adc driver
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fuzhibo
207
components/soc/include/hal/adc_hal.h
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207
components/soc/include/hal/adc_hal.h
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#pragma once
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#include "hal/adc_types.h"
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#include "hal/adc_ll.h"
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typedef struct {
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bool conv_limit_en;
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uint32_t conv_limit_num;
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uint32_t clk_div;
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uint32_t adc1_pattern_len;
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uint32_t adc2_pattern_len;
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adc_ll_pattern_table_t *adc1_pattern;
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adc_ll_pattern_table_t *adc2_pattern;
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adc_ll_convert_mode_t conv_mode;
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adc_ll_dig_output_format_t format;
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} adc_hal_dig_config_t;
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* ADC module initialization.
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*/
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void adc_hal_init(void);
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/**
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* Set adc sample cycle for digital controller.
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*
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* @note Normally, please use default value.
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* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
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* Range: 2 ~ 0xFF.
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*/
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#define adc_hal_dig_set_sample_cycle(sample_cycle) adc_ll_dig_set_sample_cycle(sample_cycle)
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/**
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* Set ADC module power management.
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*
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* @prarm manage Set ADC power status.
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*/
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#define adc_hal_set_power_manage(manage) adc_ll_set_power_manage(manage)
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/**
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* Get ADC module power management.
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*
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* @return
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* - ADC power status.
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*/
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#define adc_hal_get_power_manage() adc_ll_get_power_manage()
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/**
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* ADC module clock division factor setting. ADC clock devided from APB clock.
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*
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* @prarm div Division factor.
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*/
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#define adc_hal_set_clk_div(div) adc_ll_set_clk_div(div)
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/**
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* ADC module output data invert or not.
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*
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* @prarm adc_n ADC unit.
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*/
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#define adc_hal_output_invert(adc_n, inv_en) adc_ll_output_invert(adc_n, inv_en)
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/**
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* Set ADC module controller.
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* There are five SAR ADC controllers:
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* Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes;
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* Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep;
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* the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2.
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*
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* @prarm adc_n ADC unit.
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* @prarm ctrl ADC controller.
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*/
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#define adc_hal_set_controller(adc_n, ctrl) adc_ll_set_controller(adc_n, ctrl)
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/**
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* Set the attenuation of a particular channel on ADCn.
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*
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* @note For any given channel, this function must be called before the first time conversion.
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*
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* The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,
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* usually 3.3V) requires setting >0dB signal attenuation for that ADC channel.
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*
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* When VDD_A is 3.3V:
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*
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* - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V
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* - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V
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* - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V
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* - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below)
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*
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* @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured
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* bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.)
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*
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* @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
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*
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* Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges:
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*
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* - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV
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* - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV
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* - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV
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* - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV
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*
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* For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges.
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*
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* @prarm adc_n ADC unit.
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* @prarm channel ADCn channel number.
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* @prarm atten The attenuation option.
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*/
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#define adc_hal_set_atten(adc_n, channel, atten) adc_ll_set_atten(adc_n, channel, atten)
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/**
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* Close ADC AMP module if don't use it for power save.
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*/
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#define adc_hal_amp_disable() adc_ll_amp_disable()
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/*---------------------------------------------------------------
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PWDET(Power detect) controller setting
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---------------------------------------------------------------*/
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/**
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* Set adc cct for PWDET controller.
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*
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* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
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* @prarm cct Range: 0 ~ 7.
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*/
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#define adc_hal_pwdet_set_cct(cct) adc_ll_pwdet_set_cct(cct)
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/**
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* Get adc cct for PWDET controller.
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*
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* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
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* @return cct Range: 0 ~ 7.
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*/
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#define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct()
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/*---------------------------------------------------------------
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RTC controller setting
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---------------------------------------------------------------*/
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/**
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* Set adc output data format for RTC controller.
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*
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* @prarm adc_n ADC unit.
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* @prarm bits Output data bits width option.
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*/
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#define adc_hal_rtc_set_output_format(adc_n, bits) adc_ll_rtc_set_output_format(adc_n, bits)
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/**
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* Get the converted value for each ADCn for RTC controller.
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*
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* @note It may be block to wait conversion finish.
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* @prarm adc_n ADC unit.
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* @return
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* - Converted value.
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*/
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int adc_hal_convert(adc_ll_num_t adc_n, int channel);
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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/**
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* Setting the digital controller.
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*
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* @prarm adc_hal_dig_config_t cfg Pointer to digital controller paramter.
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*/
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void adc_hal_dig_controller_config(const adc_hal_dig_config_t *cfg);
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/**
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* Set I2S DMA data source for digital controller.
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*
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* @param src i2s data source.
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*/
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#define adc_hal_dig_set_data_source(src) adc_ll_dig_set_data_source(src)
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/*---------------------------------------------------------------
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Hall sensor setting
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---------------------------------------------------------------*/
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/**
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* Enable hall sensor.
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*/
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#define adc_hal_hall_enable() adc_ll_hall_enable()
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/**
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* Disable hall sensor.
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*/
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#define adc_hal_hall_disable() adc_ll_hall_disable()
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/**
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* Start hall convert and return the hall value.
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*
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* @return Hall value.
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*/
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int adc_hal_hall_convert(void);
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/**
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* @brief Output ADC2 reference voltage to gpio
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*
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* This function utilizes the testing mux exclusive to ADC2 to route the
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* reference voltage one of ADC2's channels.
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*
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* @param[in] io GPIO number
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* @return
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* - true: v_ref successfully routed to selected gpio
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* - false: Unsupported gpio
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*/
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#define adc_hal_vref_output(io) adc_ll_vref_output(io)
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